Active solid-state devices (e.g., transistors, solid-state diodes) inventions 07/07

20070170416 - Semiconductor light emitting unit, method for manufacturing same and linear light source: A semiconductor light emitting unit is provided which comprises: a support 1 formed with longitudinal side walls 15 disposed opposite to each other for forming a pair of light reflective surfaces 9, and a bottom wall 16 connected to longitudinal side walls 15 for forming a mount surface 3a between... Agent: Bachman & Lapointe, P.C.

20070170417 - Iii-v photonic integration on silicon: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of III-V material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. The coupling between the silicon waveguide and the... Agent: Gates & Cooper LLP Howard Hughes Center

20070170422 - Devices containing chiroptical switching materials and methods of making and using the same: A polycarbodiimide polymer that is reversibly switchable between two distinct optical orientations is described. The polymer is useful in forming devices such as filters, storage media, actuators, and displays. Methods of making and using such polymers are also described.... Agent: Myers Bigel Sibley & Sajovec

20070170424 - Organic electroluminescence device: An organic electroluminescence device having, between a pair of electrodes, at least a light-emitting layer, a first hole transport layer between the light-emitting layer and an anode, and a first electron transport layer between the light-emitting layer and a cathode, wherein the organic electroluminescence device has at least one of... Agent: Birch Stewart Kolasch & Birch

20070170420 - Organic memory device and method of fabricating the same: An organic memory device includes a top electrode, a bottom electrode, and a bistable organic polymer layer between the top and bottom electrodes. Moreover, the organic memory device further includes a surface treatment layer between the organic polymer layer and the bottom electrode. Because the surface treatment layer can stabilize... Agent: Jianq Chyun Intellectual Property Office

20070170426 - Silicon crystallizing mask, apparatus for crystallizing silicon having the mask and method for crystallizing silicon using the apparatus: In a silicon crystallization mask that may be used to enhance electrical characteristics of silicon, an apparatus for crystallizing silicon having the mask and a method for crystallizing silicon using the apparatus, the mask includes first slits and second slits. The first slits are configured to transmit light and are... Agent: Macpherson Kwok Chen & Heid LLP

20070170427 - Semiconductor device: A semiconductor device comprises a semiconductor substrate, a MOS transistor and an antifuse element. The MOS transistor is formed on the semiconductor substrate and comprises a channel region and a gate electrode. The channel region has a predetermined conductive type. The antifuse element is formed on the semiconductor substrate and... Agent: Mcdermott Will & Emery LLP

20070170431 - Display device and manufacturing method therefor: A display device, comprising an insulating substrate; a data conductor formed on the insulating substrate and comprising a conductive film; a thin film transistor having at least one source electrode electrically connected with the conductive film, and a drain electrode formed along a circumference of the source electrode and spaced... Agent: Macpherson Kwok Chen & Heid LLP

20070170430 - Electro-optical device, method for manufacturing electro-optical device, and electronic apparatus: An electro-optical device includes an anti-reflective layer arranged on the face of a first metal layer that is closer to a semiconductor layer than a second metal layer. The anti-reflective layer covers the channel region as viewed in plan view.... Agent: Advantedge Law Group, LLC

20070170438 - Wafer encapsulated microelectromechanical structure and method of manufacturing same: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or... Agent: Neil A. Steinberg

20070170439 - Wafer encapsulated microelectromechanical structure and method of manufacturing same: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or... Agent: Neil A. Steinberg

20070170440 - Wafer encapsulated microelectromechanical structure and method of manufacturing same: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or... Agent: Neil A. Steinberg

20070170441 - Nitride semiconductor device and method for manufacturing the same: A nitride semiconductor device includes: a substrate having a principal surface; a first nitride semiconductor layer formed on the principal surface of the substrate and includes one or more convex portions whose side surfaces are vertical to the principal surface; and a second nitride semiconductor layer selectively grown on the... Agent: Mcdermott Will & Emery LLP

20070170443 - Light generating module, liquid crystal display device having the same, and method of improving color reproducibility thereof: A light generating module includes a light emitting part and a power supplying part. The light emitting part includes a first region and a second region. First and second lights having different wavelengths from each other are generated in each of the first and second regions. The first region is... Agent: Cantor Colburn, LLP

20070170449 - Color sensor integrated light emitting diode for led backlight: A color sensor integrated light emitting diode (LED) is packaged with LED and color sensor mounted side by side inside LED package comprising a heat sink for mounting LED and the color sensor, both the color sensor and LED being buried by a high refractive index polymer followed by a... Agent: Dr. M. Anandan

20070170446 - Inorganic electroluminescent diode and method of fabricating the same: Disclosed are an inorganic electroluminescent diode and a method of fabricating the same. Specifically, this invention provides an inorganic electroluminescent diode, which includes a semiconductor nanocrystal layer formed of inorganic material, an electron transport layer or a hole transport layer formed on the semiconductor nanocrystal layer using amorphous inorganic material,... Agent: Cantor Colburn, LLP

20070170447 - Shifting spectral content in solid state light emitters by spatially separating lumiphor films: A lighting device, comprising at least one solid state light emitter, at least one first lumiphor and at least one second lumiphor which is spaced from the first lumiphor. The solid state light emitter can be a light emitting diode. A method of making a lighting device, comprising positioning at... Agent: Burr & Brown

20070170452 - Lighting device and light emitting module for the same: A light emitting module of a lighting device has a casing, a heat radiating member and terminals. The terminals extend from the casing and connects to a circuit board disposed along a light diffusing member. The heat radiating member extends in a direction perpendicular to the terminals. Alternatively, the terminals... Agent: Nixon & Vanderhye, PC

20070170413 - Semiconductor memory: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of... Agent: Miles & Stockbridge PC

20070170414 - Field emission devices using modified carbon nanotubes: The present invention relates to a field emission device comprising an anode and a cathode, wherein said cathode includes carbon nanotubes nanotubes which have been subjected to energy, plasma, chemical, or mechanical treatment. The present invention also relates to a field emission cathode comprising carbon nanotubes which have been subject... Agent: Kramer Levin Naftalis & Frankel LLP Intellectual Property Department

20070170415 - Semiconductor light emitting device: The refractive index of the material for forming a light emitting element, example of the material including a group III Nitride Compound Semiconductor, is relatively higher than that of air; therefore, in order to emit, into air, light generated in an active layer in conventional semiconductor light emitting devices, it... Agent: Hogan & Hartson L.L.P.

20070170418 - Broad-emission nanocrystals and methods of making and using same: In one aspect, the invention relates to an inorganic nanoparticle or nanocrystal, also referred to as a quantum dot, capable of emitting white light. In a further aspect, the invention relates to an inorganic nanoparticle capable of absorbing energy from a first electromagnetic region and capable of emitting light in... Agent: Needle & Rosenberg, P.C.

20070170421 - Fluorocarbon electrode modification layer: An organic device including at least two electrodes; at least one organic active layer, wherein the organic active layer is disposed in between two electrodes; and an electrode modification layer, wherein the electrode modification layer is disposed in between two electrodes and in contact with one of the electrodes; and... Agent: Pamela R. Crocker Patent Legal Staff

20070170419 - Organic electronic devices: The present invention relates to the improvement of organic electronic devices, in particular fluorescent electroluminescent devices, by using electron-transport materials of the formula (1) to (4) as shown in scheme 1... Agent: Connolly Bove Lodge & Hutz, LLP

20070170423 - Organic light-emitting display and method of making the same: Disclosed is an organic light-emitting display device in which a substrate and an encapsulation substrate are completely sealed using a frit; and the preparing method of the same. The organic light-emitting display device of the present invention includes a first substrate comprising a pixel region including an organic light-emitting diode... Agent: Knobbe Martens Olson & Bear LLP

20070170425 - Semiconductor integrated circuit device and test method thereof: The present invention provides a high-quality semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070170428 - Thin film material and method of manufacturing the same: A thin film material and a method of manufacturing the thin film material are obtained with which properties of films formed on a substrate can be improved. A superconducting wire 1 includes a substrate 2, an intermediate thin film layer (intermediate layer 3) formed on the substrate and comprised of... Agent: Foley And Lardner LLP Suite 500

20070170429 - Apparatus and method for manufacturing electro-optical devices: The present invention provides an electro-optical device capable of achieving an increased light emission efficiency and an enhanced visibility. An organic electroluminescents (EL) display device has a plurality of material layers including a luminescent layer. In a plurality of material layers layered in the direction of light emission from the... Agent: Oliff & Berridge, PLC

20070170432 - Thin film transistor array substrate and method of fabricating the same: A thin film transistor array substrate includes a gate line formed on a substrate, a data line formed on the substrate intersecting with the gate line to define a pixel region, a thin film transistor formed at the intersection of the gate line and the data line, the thin film... Agent: Morgan Lewis & Bockius LLP

20070170433 - Multilevel semiconductor device and method of manufacturing the same: A method of fabricating a multilevel semiconductor integrated circuit is provided, comprising: forming on a first active semiconductor structure a first plurality of transistors with respective gate structures disposed on a first substrate and source or drain regions disposed within the first substrate; depositing a first insulation layer on the... Agent: F. Chau & Associates, LLC

20070170435 - Liquid crystal display panel and fabricating method thereof: A liquid crystal display (LCD) panel is fabricated in a simplified process. The LCD panel includes a thin film transistor (TFT) array substrate with a gate and data lines crossing each other to define a pixel area, a TFT at the crossings of the gate and data lines, a protective... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070170434 - Thin film transistor, thin film transistor substrate, processes for producing the same, liquid crystal display using the same, and related devices and processes; and sputtering target, transparent electroconductive film formed by use of this,transparent e: Provided are a thin film transistor substrate having a transparent electroconductive film in which residues and so on resulting etching are hardly generated; a process for producing the same; and a liquid crystal display using this thin film transistor substrate. A thin film transistor substrate, comprising a transparent substrate, a... Agent: Millen, White, Zelano & Branigan, P.C.

20070170437 - Hierarchical assembly of interconnects for molecular electronics: A hierarchical assembly methodology can interconnect individual two- and/or three-terminal molecules with other nanoelements (nanoparticles, nanowires, etc.) to form solution-based suspensions of nanoscale assemblies. The nanoassemblies can then undergo chemical-selective alignment and attachment to nanopatterned silicon and/or other surfaces for interconnection and/or measurement.... Agent: Myers Bigel Sibley & Sajovec

20070170436 - High-withstand voltage wide-gap semiconductor device and power device: A semiconductor device with high withstand voltage, reduced forward-direction voltage degradation, long lifetime and high reliability, is provided. A junction between the drift layer and anode layer of a bipolar semiconductor device and an electric field relaxation layer are formed at a distance from each other, and an edge portion... Agent: Nixon & Vanderhye, PC

20070170442 - Nitride-based semiconductor light-emitting device and method of fabricating the same: A nitride-based semiconductor light-emitting device capable of stabilizing transverse light confinement is obtained. This nitride-based semiconductor light-emitting device comprises an emission layer, a cladding layer, formed on the emission layer, including a first nitride-based semiconductor layer and having a current path portion and a current blocking layer, formed to cover... Agent: Mcdermott Will & Emery LLP

20070170444 - Integrated led chip to emit multiple colors and method of manufacturing the same: The present invention is a monolithic, multi-colored LED chip and a method for making the same. The LED chip is comprised of a substrate and a plurality of light emitting structures, each light emitting structure capable of emitting a wavelength of light unique compared to others and each structure layered... Agent: Geoffrey E. Dobbin, Patent Attorney

20070170445 - Semiconductor light-emitting device: A semiconductor light-emitting device including a light-emitting layer forming portion, a semiconductor substrate of a first conductivity type, a first electrode which is disposed on a surface of the semiconductor substrate of the first conductivity type, a semiconductor substrate of a second conductivity type, and a second electrode which is... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070170448 - Semiconductor light emitting device and semiconductor light emitting device assembly: A semiconductor light emitting device capable of improving the light extraction efficiency while preventing deterioration of the light emission characteristic with time and a semiconductor light emitting device assembly including the semiconductor light emitting device are provided. The semiconductor light emitting device includes a semiconductor light emitting element containing a... Agent: Wolf Greenfield & Sacks, P.C.

20070170451 - Integrated circuit capable of operating at different supply voltages: A chip configuration for dual board voltage compatibility comprising ballast I/O pads, regulator control block and VDDCO pad. If 1.8V is available on board, all 1.8V pads are connected to the package pins and the VDDCO pad is double bonded with one 1.8V package pin. This ensures that the regulator... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070170450 - Package for a light emitting element with integrated electrostatic discharge protection: A package includes a substrate with a recess in which a light emitting element is mounted. A surface of the substrate forms an exterior surface of the package. A lid may be attached to the substrate to define a sealed region in which the light emitting element is mounted. The... Agent: Fish & Richardson P.C.

20070170453 - Package for mounting an optical element and a method of manufacturing the same: The optical mounting package of the present invention is featured by mounting a silicon frame on an insulating substrate for mounting the optical element. The package of the present invention is also featured by that the frame mounted on the insulating substrate for mounting the optical element is made of... Agent: Dickstein Shapiro LLP

20070170455 - Organic light emitting display device and method of fabricating the same: An organic light emitting device according to one embodiment of the present invention comprises a first substrate defining a pixel region and a non-pixel region; an array of organic light emitting pixels formed in the pixel region of the first substrate; a second substrate placed over the first substrate, the... Agent: Knobbe Martens Olson & Bear LLP

20070170456 - Light emitting diode package with coaxial leads: The leads of a light emitting diode are made coaxial. The inner lead protrudes lower than the outer lead. The package is inserted into a spongy display panel for power supply. The display panel has three layers: a lower conducting layer for contacting said inner lead and a top conducting... Agent: Hungchang Lin

20070170454 - Packages for semiconductor light emitting devices utilizing dispensed reflectors and methods of forming the same: A packaged LED includes a substrate, an LED chip on the upper surface of the substrate, a first encapsulant material, including a reflective material, on the substrate and spaced apart from the LED chip, and a second encapsulant material on the LED chip. A method of forming a packaged LED... Agent: Myers Bigel Sibley & Sajovec

20070170459 - Nitride semiconductor light generating device: A nitride semiconductor light generating device comprises an n-type gallium nitride based semiconductor layer, a quantum well active layer including an InX1AlY1Ga1-X1-Y1N (1>X1>0, 1>Y1>0) well layer and an InX2AlY2Ga1-X2-Y2N (1>X2>0, 1>Y2>0) barrier layer, an InX3AlY3Ga1-X3-Y3N (1>X3>0, 1>Y3>0) layer provided between the quantum well active layer and the n-type gallium nitride... Agent: Mcdermott Will & Emery LLP

20070170457 - Gallium nitride-based compound semiconductor multilayer structure and production method thereof: An object of the present invention is to provide a gallium nitride compound semiconductor multilayer structure useful for producing a gallium nitride compound semiconductor light-emitting device which operates at low voltage while maintaining satisfactory light emission output. The inventive gallium nitride compound semiconductor multilayer structure comprises a substrate, and an... Agent: Sughrue Mion, PLLC

20070170458 - Group iii nitride semiconductor light-emitting device, forming method thereof, lamp and light source using same: A Group III nitride semiconductor light-emitting device having a stacked structure includes a transparent crystal substrate having a front surface and a back surface, a first Group III nitride semiconductor layer of first conductive type formed on the front surface of the transparent crystal substrate, a second Group III nitride... Agent: Sughrue Mion, PLLC

20070170460 - Micro-electro mechanical systems switch and method of fabricating the same: A MEMS switch and a method of manufacturing the same are disclosed. The MEMS switch includes: a substrate including a trench, a ground line and a signal line having an opened portion; a moving plate separated from the substrate at a predetermined space and including a contact member for connecting... Agent: Blakely Sokoloff Taylor & Zafman

20070170461 - Gallium nitride-based compound semiconductor light-emitting device: An object of the present invention is to provide a gallium nitride compound semiconductor light-emitting device having a positive electrode that exhibits low contact resistance with a p-type gallium nitride compound semiconductor layer and that can be fabricated with high productivity. The inventive gallium nitride compound semiconductor light-emitting device includes... Agent: Sughrue Mion, PLLC

20070170462 - Photo sensor and preparation method thereof: A novel structure of photo sensor is disclosed. The equivalent circuit of the invented photo sensor comprises a photo transistor integrated with a surface photo sensor. The structure of the surface photo sensor is substantially identical to the base-emitter junction of the photo transistor and may be prepared in the... Agent: Bacon & Thomas, PLLC

20070170463 - Nitride semiconductor device: A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed... Agent: Mcdermott Will & Emery LLP

20070170464 - Transistor gate electrode having conductor material layer: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between... Agent: Intel/blakely

20070170465 - Level shifter for flat panel display device: A level shifter for a flat panel display device is provided. A first transistor has a first transistor source, a first transistor gate, and a first transistor drain. The first transistor source is connected to a first power supply and the first transistor gate and the first transistor drain are... Agent: Christie, Parker & Hale, LLP

20070170466 - Method for producing compound semiconductor wafer and compound semiconductor device: A method for producing a compound semiconductor wafer used for production of HBT by vapor growth of a sub-collector layer, a collector layer, a base layer and an emitter layer in this turn on a compound semiconductor substrate using MOCVD method wherein the base layer is grown as a p-type... Agent: Birch Stewart Kolasch & Birch

20070170467 - Semiconductor device: A semiconductor device includes a first transistor having a first gate oxide layer with a first thickness; a second transistor having a second gate oxide layer with a second thickness different from the first thickness; and at least one of a capacitor and a variable capacitance diode. The one of... Agent: Takeuchi & Kubotera, LLP

20070170468 - Method for manufacturing a semiconductor substrate and a method for manufacturing a semiconductor device and the semiconductor device manufactured thereby: A method for manufacturing a semiconductor substrate includes: forming an element isolation layer on a semiconductor base material for separating an element region from the other regions; forming a first semiconductor layer on the semiconductor base material; forming a second semiconductor layer on the first semiconductor layer, the second semiconductor... Agent: Advantedge Law Group, LLC

20070170469 - Ldmos device with improved esd performance: A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well;... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070170470 - Solid-state imaging device, signal charge detection device, and camera: The solid-state imaging device of the present invention includes: a floating diffusion capacity unit which is formed on a semiconductor substrate, and is operable to hold signal charges derived from incident light; an amplifier which is operable to convert the signal charges held in the floating diffusion capacity unit into... Agent: Greenblum & Bernstein, P.L.C

20070170471 - Three-dimensional integrated c-mos circuit and method for producing same: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and... Agent: Oliff & Berridge, PLC

20070170472 - Structure and method for making high density mosfet circuits with different height contact lines: Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits comprise a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate layer situated over the first gate layer. The contact line... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070170473 - Apparatus using manhattan geometry having non-manhattan current flow: A device is described, including a first diffusion region having a first terminal, a second diffusion region having a second terminal, and a channel region disposed between the first diffusion region and the second diffusion region. Further, the first terminal and the second terminal are offset to enable a non-Manhattan... Agent: Osha Liang L.L.P./sun

20070170474 - Semiconductor device and method of fabricating the same: A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate; a non-planar type transistor region having at least one of a fin type transistor region including a fin type transistor in which a current is induced to flow through side faces of a fin formed... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070170475 - Mounting structure of image pickup device: In a mounting structure of an image pickup device, an optical member allowing light to pass through is bonded to one side of an electric substrate with an adhesive with the image pickup device bonded to the other side of the electric substrate. In this structure, the hardness of an... Agent: Ostrolenk Faber Gerb & Soffen

20070170477 - Solid state imaging device and method for manufacturing the same: A plurality of light receiving elements are arranged in a matrix with uniform space therebetween in a light receiving region defined on a semiconductor substrate. A plurality of read-out electrodes are formed on the semiconductor substrate in an arrangement corresponding to the light receiving elements to read charges generated by... Agent: Mcdermott Will & Emery LLP

20070170478 - Solid-state imaging device: A solid-state imaging device comprising a plurality of pixels arrayed on a plane, wherein each of the pixels includes a semiconductor substrate and a plurality of photoelectric conversion devices, the plurality of photoelectric conversion devices include at least one on-substrate photoelectric conversion device stacked in an upper portion of the... Agent: Sughrue-265550

20070170476 - Lateral photodetectors with transparent electrodes: A photodetector includes a substrate and a layer of Ge formed on the substrate. A plurality of n-type doped regions and a plurality of p-type doped regions are formed in Ge region. These doped regions formed an alternating pattern. Electrodes are formed on n-type doped regions and on the p-type... Agent: Gauthier & Connors, LLP

20070170479 - Polarization transfer device and control method therefor: A polarization transfer device includes a ferroelectric thin film formed continuously as one piece; a plurality of polarization switches formed by placing the ferroelectric thin film between a first gate electrode and a second gate electrode; and a plurality of polarization accumulators formed by placing the ferroelectric thin film between... Agent: Oliff & Berridge, PLC

20070170480 - Nonvolatile ferroelectric memory device: A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line,... Agent: Heller Ehrman LLP

20070170481 - Nonvolatile ferroelectric memory device: A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line,... Agent: Heller Ehrman LLP

20070170484 - Semiconductor device and its manufacturing method: To realize miniaturization/high integration and increase in the amount of accumulated charges, and to give a memory structure having a high reliability. A 1 transistor 1 capacitor (1T1C) structure having 1 ferroelectric capacitor structure and 1 selection transistor every memory cell is adopted, and respective capacitor structures are disposed respectively... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070170483 - Capacitor of dynamic random access memory and method of manufacturing the capacitor: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the... Agent: Foley And Lardner LLP Suite 500

20070170485 - Semiconductor memory device and method for fabricating the same: A semiconductor memory device includes a plurality of memory cells. Each memory cell includes a capacitor which is composed of a first electrode, at least one particle made of ferroelectric or high dielectric constant material and selectively arranged on the first electrode, and a second electrode formed on the particle.... Agent: Mcdermott Will & Emery LLP

20070170482 - Semiconductor storage device and manufacturing method thereof: A semiconductor storage device including a capacitor whose stored signal quantity is large with respect to its area share ratio, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a transistor formed on a semiconductor substrate,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070170486 - Semiconductor device having self-aligned contact and method of fabricating the same: A semiconductor device includes a conductive pattern disposed on a substrate, a first interlayer dielectric layer disposed on the substrate and the conductive pattern, a first dummy pattern disposed on the first interlayer dielectric layer and partially overlapping the conductive pattern, a second interlayer dielectric layer disposed on the first... Agent: Marger Johnson & Mccollom, P.C.

20070170488 - Capacitor of semiconductor device and method for fabricating the same: A capacitor of a semiconductor device and a method for fabricating the same may be provided. The method may include forming an interlayer insulation layer, an etch stop layer, and/or a sacrificial insulation layer on a semiconductor substrate, patterning the interlayer insulation layer, the etch stop layer, and/or the sacrificial... Agent: Harness, Dickey & Pierce, P.L.C

20070170487 - Storage capacitor for semiconductor memory cells and method of manufacturing a storage capacitor: A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of... Agent: Dicke, Billig & Czaja

20070170489 - Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process: A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070170490 - Nonvolatile memory device and method of fabricating the same: A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on hte semiconductor substrate; a floating gate that is formed on the gate insulating film so as... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070170491 - Nonvolatile memory device and method of fabricating the same: a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the... Agent: Mills & Onello LLP

20070170492 - Germanium-silicon-carbide floating gates in memories: The use of a germanium carbide (GeC), or a germanium silicon carbide (GeSiC) layer as a floating gate material to replace heavily doped polysilicon (poly) in fabricating floating gates in EEPROM and flash memory results in increased tunneling currents and faster erase operations. Forming the floating gate includes depositing germanium-silicon-carbide... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070170493 - Non-volatile memory and manufacturing method thereof: A non-volatile memory is described, including a substrate, a floating gate, a control gate, a source region, and a drain region. A trench is disposed in the substrate, and a step-like recess is located in the substrate beside the trench. The floating gate is disposed on the sidewall of the... Agent: Jianq Chyun Intellectual Property Office

20070170494 - Nonvolatile memory device and method for fabricating the same: In a nonvolatile memory device, and a method for fabricating the nonvolatile memory device, two floating gates are formed so as to be isolated from each other in a single memory cell field. The method is comprised of forming a first conductive layer pattern to have pattern portions that are... Agent: Mills & Onello LLP

20070170495 - Non-volatile semiconductor storage device and manufacturing method of the same: Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and... Agent: Miles & Stockbridge PC

20070170496 - Nrom flash memory devices on ultrathin silicon: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070170497 - Semiconductor device and method for manufacturing the same: A semiconductor device comprises an active region formed in a semiconductor substrate; a recess region being formed within the active region and defining a protruding portion; and a gate structure formed within the recess region.... Agent: Townsend And Townsend And Crew, LLP

20070170499 - Semiconductor device and manufacturing method thereof: A semiconductor device has elements formed on a substrate separately from each other. Each of the elements includes first and second regions as a source and a drain; a gate electrode formed to have a buried gate structure, and a portion of the gate electrode is put between the first... Agent: Foley And Lardner LLP Suite 500

20070170498 - Configuration and method to form mosfet devices with low resistance silicide gate and mesa contact regions: A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.... Agent: Bo-in Lin

20070170500 - Semiconductor structure and method for forming thereof: A semiconductor structure and a method for forming the semiconductor structure are provided. The method for forming a semiconductor structure of the present invention may include the following steps. First, a substrate is provided, wherein a gate is formed over the substrate, and a plurality of offspacers are formed over... Agent: J C Patents, Inc.

20070170501 - Mos transistors including silicide layers on source/drain regions: A MOS transistor can include a substrate and a field region formed at the semiconductor substrate to define an active region. An I-shaped spacer is on sidewalls of the gate electrode. A lightly doped region and a heavily doped region are on the semiconductor substrate on sides of the gate... Agent: Myers Bigel Sibley & Sajovec

20070170503 - Composite substrate and method of fabricating the same: The invention specifically relates to methods of fabricating a composite substrate by providing a first insulating layer on a support substrate at a thickness of e1 and providing a second insulating layer on a source substrate at a thickness of e2, with each layer having an exposed face for bonding;... Agent: Winston & Strawn LLP Patent Department

20070170506 - Semiconductor device: The invention prevents the reduction of a display quality caused by a light leak current of a thin film transistor used in a display device. A lower metal layer is formed on a substrate, and a buffer film, a semiconductor layer, a gate insulation film, and a gate wiring are... Agent: Morrison & Foerster LLP

20070170504 - Thin film transistor substrate and method of fabricating the same and liquid crystal display having the thin film transistor substrate: The present invention provides a thin film transistor substrate with a structure for reducing coupling capacitance between a data line and a pixel electrode, a method of fabricating the thin film transistor substrate, and a liquid crystal display having the thin film transistor substrate. The present invention provides a thin... Agent: Cantor Colburn, LLP

20070170505 - Semiconductor device and manufacturing method thereof: To provide a wireless identification semiconductor device provided with a display function, which is capable of effectively utilizing electric power supplied by an electromagnetic wave. The following are included: an antenna; a power source generating circuit electrically connected to the antenna; an IC chip circuit and a display element electrically... Agent: Eric Robinson

20070170502 - Semiconductor device and method for manufacturing the same: The present invention provides a high-quality semiconductor device in which deterioration in transistor characteristics and an increase in interface layer due to a gate insulating film are suppressed, and a method for manufacturing the same. In the present invention, an interface layer, a diffusion suppressing layer and a high dielectric... Agent: Cantor Colburn, LLP

20070170507 - Structure and method for manufacturing planar strained si/sige substrate with multiple orientations and different stress levels: The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation... Agent: Scully, Scott, Murphy & Presser, P.C.

20070170508 - Semiconductor device and method of manufacturing the semiconductor device: In a method of manufacturing a semiconductor device to improve structural stability of a semiconductor device in a silicidation process, a substrate is provided to have an active region defined by an isolation layer. An etching mask is formed on the active region and the isolation layer to have a... Agent: Mills & Onello LLP

20070170509 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a Fin, a source region and a drain region, a first extension region, a second extension region and a channel region. The Fin is formed on a major surface of a semiconductor substrate. The source region and drain region are formed at both end portions of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070170510 - Electrostatic discharge protection circuit and diode thereof: A diode disposed on a substrate is provided. The diode includes a semiconductor pattern, a first conductor pattern, a second conductor pattern, an insulating layer, and a top conductor pattern. The first conductor pattern and the second conductor pattern are respectively disposed on a portion of the semiconductor pattern. The... Agent: Jianq Chyun Intellectual Property Office

20070170511 - Method for fabricating a recessed-gate mos transistor device: A method of fabricating a recess-gate transistor is provided. A first liner and a dielectric layer are formed on a substrate. An opening is formed in the first liner and dielectric layer. A second liner is formed on the dielectric layer and in the opening. The second liner is dry-etched... Agent: North America Intellectual Property Corporation

20070170512 - Electrostatic discharge protection device and method of fabricating same: Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with... Agent: Schmeiser, Olsen & Watts

20070170513 - Semiconductor device and manufacturing method thereof: A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and... Agent: Fish & Richardson P.C.

20070170514 - Igbt device and related device having robustness under extreme conditions: A semiconductor device in the form of an IGBT has a front side contact, a rear side contact, and a semiconductor volume disposed between the front side contact and the rear side contact. The semiconductor volume includes a field stop layer for spatially delimiting an electric field that can be... Agent: Maginot, Moore & Beck Chase Tower

20070170515 - Structure and method for enhanced triple well latchup robustness: Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p− substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070170516 - Triple-well cmos devices with increased latch-up immunity and methods of fabricating same: A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in... Agent: Schmeiser, Olsen & Watts

20070170517 - Cmos devices adapted to reduce latchup and methods of manufacturing the same: In a first aspect, a first apparatus is provided. The first apparatus is semiconductor device that includes (1) a shallow trench isolation (STI) oxide region; (2) a first metal-oxide-semiconductor field-effect transistor (MOSFET) coupled to a first side of the STI oxide region; (3) a second MOSFET coupled to a second... Agent: Ibm Corporation Intellectual Property Law Dept. 917

20070170518 - Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070170519 - Driver for driving a load using a charge pump circuit: A charge pump circuit includes MOSFETs and MOS capacitors formed on the same substrate. Each of the MOS capacitors has a multiplicity of first electrodes formed in one region of the substrate, insulating layers formed on/above respective substrate regions between neighboring first electrodes, each layer covering at least the respective... Agent: Hogan & Hartson L.L.P.

20070170520 - Three-dimensional memory cells: The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility. The present invention further discloses a 3D-M with seamless 3D-ROM cells. Seamless 3D-ROM can ensure a better manufacturing yield.... Agent: Guobiao Zhang

20070170523 - Circuit substrate and packaging thereof and the method for fabricating the packaging: A circuit substrate and its packaging and the method for fabricating the packaging are provided. A plurality of electrodes are formed on the surface of the circuit substrate, the electrodes are formed with fork structures, so that when the circuit substrate expands/contracts due to thermal processes, such that the probability... Agent: Ishimaru & Zahrt LLP

20070170524 - Esd protection device for high performance ic: The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps... Agent: Morgan, Lewis & Bockius LLP

20070170521 - Method and structure to process thick and thin fins and variable fin to fin spacing: Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070170522 - Semiconductor device and method for fabricating the same: The semiconductor device includes an active region, a recess, a Fin-type channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation... Agent: Heller Ehrman LLP

20070170525 - Discrete stress isolator: A discrete stress isolation apparatus for a Micro Electro-Mechanical System (MEMS) inertial sensor device having a mechanism die and a package. A capacitive device mechanism is formed in a substrate layer positioned between the mechanism die and package substrate. A discrete stress isolation structure is formed in the same substrate... Agent: Honeywell International Inc.

20070170526 - Thin-film transistor and manufacturing method thereof: A method for forming a thin-film transistor on an insulating substrate includes the steps of: forming a non-single-crystal semiconductor thin film on the insulating substrate; forming a gate insulating film on the non-single-crystal semiconductor thin film; forming a gate electrode including a lower gate electrode and an upper gate electrode... Agent: Norman P. Soloway Hayes Soloway P.C.

20070170527 - Structure for reducing overlap capacitance in field effect transistors: A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations... Agent: Cantor Colburn LLP - IBM Fishkill

20070170529 - Wafer encapsulated microelectromechanical structure and method of manufacturing same: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or... Agent: Neil A. Steinberg

20070170530 - Wafer encapsulated microelectromechanical structure and method of manufacturing same: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or... Agent: Neil A. Steinberg

20070170531 - Wafer encapsulated microelectromechanical structure and method of manufacturing same: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or... Agent: Neil A. Steinberg

20070170532 - Wafer encapsulated microelectromechanical structure and method of manufacturing same: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or... Agent: Neil A. Steinberg

20070170528 - Wafer encapsulated microelectromechanical structure and method of manufacturing same: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or... Agent: Neil A. Steinberg

20070170533 - Arrangements for an intergrated sensor: An integrated circuit can have a first substrate supporting a magnetic field sensing element and a second substrate supporting another magnetic field sensing element. The first and second substrates can be arranged in a variety of configurations. Another integrated circuit can have a first magnetic field sensing element and second... Agent: Daly, Crowley, Mofford & Durkee, LLP

20070170534 - Optical sensing apparatus with a noise interference rejection function: An optical sensing apparatus with a signal interference rejection function is fabricated in a semiconductor chip by using a CMOS process. The optical sensing apparatus comprises an optical sensing element having a light-receiving side for receiving an optical signal from the light-receiving side and converting the optical signal into an... Agent: Birch Stewart Kolasch & Birch

20070170535 - Photovoltaic devices with silicon dioxide encapsulation layer and method to make same: A photovoltaic device and method of manufacture provides a P-N junction formed between doped semiconductor materials and adapted to produce photovoltaic current in response to radiant energy reaching the P-N junction, and a silicon dioxide protective window layer located in proximity to doped semiconductor material and adapted to allow radiant... Agent: Burns & Levinson, LLP

20070170536 - Liquid phase epitaxial goi photodiode with buried high resistivity germanium layer: A device and associated method are provided for fabricating a liquid phase epitaxial (LPE) Germanium-on-Insulator (GOI) photodiode with buried high resistivity Germanium (Ge) layer. The method provides a silicon (Si) substrate, and forms a bottom insulator overlying the Si substrate with a Si seed access area. Then, a Ge P-I-N... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070170537 - Method and device for wavelength-sensitive photo-sensing: A semiconductor device includes a conducting channel (130) formed beneath a substrate surface with a pre-determined photo-conductivity spectral response. The channel is formed between two pn-junctions (126, 128) defining first and third photo-electric depletion regions at respective depths relative to the surface corresponding to penetration depths of light of different... Agent: Blakely Sokoloff Taylor & Zafman

20070170538 - Process for the fabricating an electronic integrated circuit and electronic integrated circuit thus obtained: An electronic integrated circuit is fabricated by forming on a substrate, of which a part is composed of absorbing material, a portion made of a sacrificial material. The sacrificial material includes cobalt, nickel, titanium, tantalum, tungsten, molybdenum, gallium, indium, silver, gold, iron and/or chromium. A rigid portion is then formed... Agent: Jenkens & Gilchrist, PC

20070170539 - Semiconductor device and method for manufacturing the same: The invention is directed to a method for manufacturing a field plate of a high voltage device. The field plate is located on a drift region of a substrate, wherein an isolation structure is located on the drift region. The method comprises steps of forming a first dielectric layer over... Agent: Jianq Chyun Intellectual Property Office

20070170540 - Silicon-rich silicon nitrides as etch stops in mems manufature: The fabrication of a MEMS device such as an interferometric modulator is improved by employing an etch stop layer between a sacrificial layer and a an electrode. The etch stop may reduce undesirable over-etching of the sacrificial layer and the electrode. The etch stop layer may also serve as a... Agent: Knobbe Martens Olson & Bear LLP

20070170541 - High-k dielectric for thermodynamically-stable substrate-type materials: Excellent capacitor-voltage characteristics with near-ideal hysteresis are realized in a capacitive-like structure that uses an electrode substrate-type material with a high-k dielectric layer having a thickness of a few-to-several Angstroms capacitance-based SiO2 equivalent (“TOx,Eq”). According to one particular example embodiment, a semiconductor device structure has an electrode substrate-type material having... Agent: Crawford Maunu PLLC

20070170542 - Method of filling a high aspect ratio trench isolation region and resulting structure: A method of filling a high aspect ratio trench isolation region, which allows for better gap-fill characteristics and avoids voids and seams in the isolation region. The method includes the steps of forming a trench, forming an oxide layer on the bottom and sidewalls of the trench, etching the oxide... Agent: Dickstein Shapiro LLP

20070170543 - Methods and semiconductor structures for latch-up suppression using a conductive region: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070170544 - Semiconductor device with metal fuses: A trench dummy element isolating region is formed in the fuse region of a semiconductor substrate. In the semiconductor substrate, a plurality of dummy element regions is formed so as to be enclosed by the trench dummy element isolating region. The occupancy rate of the plurality of dummy element regions... Agent: Amin, Turocy & Calvin, LLP

20070170545 - Fuse region and method of fabricating the same: In one embodiment a fuse region includes an insulating layer disposed on a substrate, a fuse disposed on the insulating layer and including a fuse barrier pattern and a fuse conductive pattern, which are stacked, and a supporting plug disposed beneath the fuse, and penetrating the insulating layer and the... Agent: Marger Johnson & Mccollom, P.C.

20070170547 - Semiconductor device and method for fabricating the same: The semiconductor device includes a semiconductor substrate, a plate electrode, and a metal layer. The semiconductor substrate includes a capacitor region and a dummy region. The plate electrode is formed over the semiconductor substrate, wherein a dummy plug of the plate electrode is formed in the dummy region. The metal... Agent: Heller Ehrman LLP

20070170548 - Semiconductor device and method for fabricating the same: After a capacitor forming portion is formed on a semiconductor substrate by patterning an insulating film and a silicon film, a sidewall insulating film is formed on each of the side surfaces of the capacitor forming portion. Then, the insulating film is selectively removed such that the silicon film is... Agent: Mcdermott Will & Emery LLP

20070170546 - Back end thin film capacitor having both plates of thin film resistor material at single metallization layer: An integrated circuit back end capacitor structure includes a first dielectric layer on a substrate, a thin film bottom plate on the first dielectric layer, and a second dielectric layer on the first dielectric layer and the bottom plate, and a thin film top plate disposed on the second dielectric... Agent: Texas Instruments Incorporated

20070170549 - Semiconductor device having igbt and diode: A semiconductor device includes: a substrate having a first side and a second side; an IGBT; and a diode. The substrate includes a first layer, a second layer on the first layer, a first side N region on the second layer, second side N and P regions on the second... Agent: Posz Law Group, PLC

20070170550 - Semiconductor device and method for fabricating the same: A semiconductor device includes a substrate and a semiconductor layer formed on the substrate. The substrate has: a flat region provided in a main surface thereof; a first indentation region provided in a portion of the main surface different from the flat region and formed with first recesses; and a... Agent: Mcdermott Will & Emery LLP

20070170551 - Semiconductor devices with oxide coatings selectively positioned over exposed features including semiconductor material and solutions for forming the coatings: A semiconductor device structure includes a passivation layer through which only non-semiconductor material-comprising structures are exposed. The semiconductor device structure is formed by selectively forming the passivation layer on an exposed semiconductor material-comprising surface by exposing surfaces of the semiconductor device to a liquid phase solution supersaturated in an oxide... Agent: Trask Britt, P.C./ Micron Technology

20070170552 - Ultra thin tcs (sicl4) cell nitride for dram capacitor with dcs (sih2cl2) interface seeding layer: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a... Agent: Whyte Hirschboeck Dudek S.c.

20070170553 - Methods and apparatuses for creating integrated circuit capacitance from gate array structures: Methods and apparatuses for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise a method of placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20070170556 - Semiconductor device having flange structure: A semiconductor device may include a semiconductor element. A layer of material may be provided on the semiconductor element which may have an opening through which a bond pad may be exposed. At least one flange structure may be provided on the first bond pad, the at least one flange... Agent: Harness, Dickey & Pierce, P.L.C

20070170554 - Integrated circuit package system with multiple molding: An integrated circuit package system is provided forming a lead from a padless lead frame, and encapsulating the lead for supporting an integrated circuit die with a first molding compound for encapsulation with a second molding compound.... Agent: Ishimaru & Zahrt LLP

20070170555 - Padless die support integrated circuit package system: An integrated circuit package system is provided forming a die support system from a padless lead frame having die supports with each substantially equally spaced from another, and attaching an integrated circuit die having a peripheral area on the die supports.... Agent: Ishimaru & Zahrt LLP

20070170557 - Mold forming method and apparatus, and plastic lens manufacturing method and apparatus: A method of forming a mold, concludes: winding a tape around peripheral surfaces of a first molding die and a second molding die to assemble a mold; forming on the tape an injection port for injecting a resin material for forming a plastic lens into the mold; and forming a... Agent: Sughrue Mion, PLLC

20070170559 - Integrated circuit package system: An integrated circuit package system is provided forming a lead finger from a padless lead frame, forming a lead tip hole in the lead finger, mounting an integrated circuit die having a solder bump on the lead finger, and reflowing the solder bump on the lead tip hole of the... Agent: Ishimaru & Zahrt LLP

20070170560 - Apparatus and methods for packaging integrated circuit chips with antennas formed from package lead wires: Apparatus and methods are provided for integrally packaging semiconductor IC (integrated circuit) chips with antennas having one or more radiating elements and tuning elements that are formed from package lead wires that are appropriated shaped and arranged to form antenna structures for millimeter wave applications.... Agent: F. Chau & Associates, LLC

20070170558 - Stacked integrated circuit package system: A stacked integrated circuit package system is provided providing a lead frame having a die paddle, attaching a first integrated circuit on the die paddle of the lead frame, connecting first electrical interconnects between the first integrated circuit and the lead frame, encapsulating the first integrated circuit and the first... Agent: Ishimaru & Zahrt LLP

20070170563 - Light emitting module and process thereof: A light emitting module includes a metal substrate, a bearing base, at least one LED, a printed circuit board, and at least one conductive wire. A first perforation is formed on the metal substrate and the bearing base is embedded into the first perforation of the metal substrate. According to... Agent: Rabin & Berdo, PC

20070170565 - Rf module, multi rf module including the rf module, and method of manufacturing the rf module: A radio frequency (RF) module and a multi RF module including the same include a base substrate, a first element capable of processing RF signals formed on the base substrate, a second element capable of processing RF signals separated from and disposed over the first element, a cap substrate coupled... Agent: Sughrue Mion, PLLC

20070170562 - Semiconductor photodetector: A semiconductor photodetector which can obtain spectral sensitivity characteristics close to relative luminous characteristics compared to a conventional semiconductor photodetector is obtained at low cost. The semiconductor photodetector includes a semiconductor light receiving element having high spectral sensitivity in wavelengths in a range from approximately 400 nm to 1,100 nm... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070170564 - Chip card module: A smart card module including a substrate having an upper face and a lower face, contact arrays arranged on the substrate lower face, conductor structures, which have vias arranged in cutouts in the substrate, arranged on the substrate upper face and connected to the contact arrays, a chip having connecting... Agent: Dickstein Shapiro LLP

20070170561 - Leaded package integrated circuit stacking: The present invention provides an improvement on the use of flexible circuit connectors for electrically coupling IC devices to one another in a stacked configuration by use of the flexible circuit to provide the connection of the stacked IC module to other circuits. Use of the flexible circuit as the... Agent: Fish & Richardson P.C.

20070170566 - Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument: A semiconductor device includes: a semiconductor substrate in which an integrated circuit is formed; an interconnect layer which includes a linear section and a land section connected with the linear section; and an underlayer disposed under the interconnect layer, and the land section includes a first section which is in... Agent: Hogan & Hartson L.L.P.

20070170567 - Semiconductor memory card: A semiconductor memory card which inputs/outputs signals by connecting to an external device, has a circuit board on an upper surface of which board terminals connected to board wiring are formed, and on a lower surface of which input/output card terminals for inputting/outputting signals to/from the external device, a power... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070170568 - Packaging for an interferometric modulator: A package is made of a transparent substrate having an interferometric modulator and a back plate. A non-hermetic seal joins the back plate to the substrate to form a package, and a desiccant resides inside the package. A method of packaging an interferometric modulator includes providing a transparent substrate and... Agent: Knobbe Martens Olson & Bear LLP

20070170569 - In-line apparatus and method for manufacturing double-sided stacked multi-chip packages: Provided are in-line semiconductor chip packaging apparatuses that include a buffer assembly in which a reversing unit rotates a lead frame 180° between die attaching and/or wire bonding operations and methods of manufacturing an integrated circuit chip package using such an in-line integrated circuit chip packaging apparatus. Between packaging process... Agent: Harness, Dickey & Pierce, P.L.C

20070170574 - Buried via technology for three dimensional integrated circuits: A three dimensional integrated circuit and method for making the same. The three dimensional integrated circuit has a first and a second active circuit layers with a first metal layer and a second metal layer, respectively. The metal layers are connected by metal inside a buried via. The fabrication method... Agent: Snell & Wilmer LLP (oc)

20070170572 - Multichip stack structure: A multi-chip stack structure includes a chip carrier, a plurality of chips stacked stepwise on the chip carrier, and a passive component disposed on the chip carrier. The passive component is located under the stepwise chips that are cantilevered over it. Therefore, the passive component serves as a block element... Agent: Edwards Angell Palmer & Dodge LLP

20070170573 - Semiconductor device, interposer chip and manufacturing method of semiconductor device: In this semiconductor device, memory chips are stacked on the surface of a wiring substrate, a microcomputer chip and an interposer chip are arranged on the surface of the memory chip, and the pad of a microcomputer chip and the pad of an interposer chip arranged almost circularly are connected... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070170575 - Stack chip and stack chip package having the same: Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit... Agent: Marger Johnson & Mccollom, P.C.

20070170570 - Integrated circuit package system including wide flange leadframe: An integrated circuit package system provides a known good die module by providing a leadframe, providing a first die, attaching the first die to the leadframe, and encapsulating at least the first die. A second die is attached to the known good die module such that the known good die... Agent: Ishimaru & Zahrt LLP

20070170571 - Low profile semiconductor system having a partial-cavity substrate: A system (100), which has an electrically insulating substrate (101) with a thickness, a first and a second surface. Electrically conductive paths (110) extend through the insulating body from the first to the second surface and have exit ports (120) at the end of the conductive paths on the first... Agent: Texas Instruments Incorporated

20070170576 - Wafer level stack structure for system-in-package and method thereof: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller... Agent: Harness, Dickey & Pierce, P.L.C

20070170577 - Semiconductor device with surface-mountable external contacts and method for manufacturing the same: A semiconductor device includes surface-mountable external contacts on an underside of the semiconductor device, wherein the external contacts are arranged on external contact pads and surrounded by a solder-resist layer. The external contacts of the outer edge regions include external contact pads that merge into inspection tags, wherein the inspection... Agent: Edell, Shapiro & Finnan, LLC

20070170578 - Semiconductor device, electronic apparatus comprising the same, and method for fabrication of substrate for semiconductor device used therein: A semiconductor device has upper electrodes and external terminals which are protruding above the both surfaces of a substrate for semiconductor device and connected to each other by penetrating electrodes, a first insulating film covering at least a metal pattern except for the portions of the first insulating film corresponding... Agent: Mcdermott Will & Emery LLP

20070170579 - Method of manufacturing semiconductor substrate, method of manufacturing semiconductor device, and semiconductor device: A method of manufacturing a semiconductor substrate includes: forming on a semiconductor base a first isolation layer for isolating an element region from another region; forming a first semiconductor layer on the semiconductor base; forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having an... Agent: Advantedge Law Group, LLC

20070170580 - Cooling apparatus for memory module: A cooling apparatus for a circuit module having a substrate extending axially with an IC chip of a first type and IC chips of a second type mounted thereon, comprising: a first heat spreading element disposed to form a heat conduction path with the IC chip of the first type;... Agent: F. Chau & Associates, LLC

20070170581 - Silicon-diamond composite heat spreader and associated methods: Diamond heat spreaders are produced having thermal properties approaching that of pure diamond. Diamond particles of relatively large grain size are tightly packed to maximize diamond-to-diamond contact. Subsequently, smaller diamond particles can optionally be introduced into the interstitial voids to further increase the diamond content per volume. An interstitial material... Agent: Thorpe North & Western, LLP.

20070170582 - Component-containing module and method for producing the same: A component-containing module includes a module substrate having first wiring lines provided on the top surface of the module substrate, a first circuit component mounted on the first wiring lines of the module substrate, a submodule substrate having an area smaller than the area of the module substrate and mounted... Agent: Murata Manufacturing Company, Ltd. C/o Keating & Bennett, LLP

20070170583 - Multilayer integrated circuit for rf communication and method for assembly thereof: A low profile radio frequency (RF) module and package with efficient heat dissipation characteristics, and a method of assembly thereof, are provided. In some embodiments, the RF module package comprises a radio frequency integrated circuit (RFIC) attached to a recessed area of a lead frame. The RFIC has an active... Agent: Avago Technologies, Ltd. C/o Klaas, Law, O'meara & Malkin, P.C.

20070170585 - Composite integrated device and methods for forming thereof: A method for making a composite integrated device includes providing a first integrated device having a substrate, an overlying interconnect region, and a contact, wherein the contact electrically contacts the interconnect region and is at a surface of the first integrated device. The method further includes forming a sidewall spacer... Agent: Freescale Semiconductor, Inc. Law Department

20070170584 - Semiconductor interconnect having adjacent reservoir for bonding and method for formation: A semiconductor device and method has interconnects with adjoining reservoir openings. A dielectric layer is formed as part of an uppermost of the one or more interconnect layers. Openings formed in the dielectric layer result in modified portions of the dielectric layer along portions of sidewalls of the openings. The... Agent: Freescale Semiconductor, Inc. Law Department

20070170587 - Ball grid array: A ball grid array includes: a semiconductor chip having multiple pads; and an interposer for mounting the semiconductor chip on a first surface. The interposer includes multiple wirings on the first surface and multiple ball terminals on a second surface opposite to the first surface. Each wiring is connected to... Agent: Nixon & Vanderhye, PC

20070170586 - Printed circuit board for semiconductor package and method of manufacturing the same: Disclosed are a printed circuit board for a semiconductor package and a method of manufacturing the same. Specifically, a printed circuit board for a semiconductor package includes predetermined circuit patterns, having a wire bonding portion and a bump portion for mounting a semiconductor and a soldering portion for connection to... Agent: Staas & Halsey LLP

20070170588 - Connection structure and fabrication method for the same: A conductive layer is formed in or on a substrate. A first metal film is then formed on the substrate including the conductive layer. The substrate is then subjected to heat treatment to allow the first metal film to react with the conductive layer to thereby form a silicide film... Agent: Mcdermott Will & Emery LLP

20070170590 - Method of fabricating semiconductor device: A semiconductor device and a method of fabricating a semiconductor device that includes forming an interlayer insulating film on a semiconductor substrate; depositing a first soft magnetic thin film on the interlayer insulating film through sputtering using a target containing at least one of Fe, Co, Ni, or alloys thereof,... Agent: Lee & Morse, P.C.

20070170589 - Semiconductor integrated circuit: A semiconductor integrated circuit according to the present invention includes a cell array composed of elements, conductive lines with a pattern of a line & space arranged on the cell array, connecting lines formed upper than the conductive lines, and contact holes which connect the conductive lines to the connecting... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070170591 - Semiconductor device and method for fabricating the same: The semiconductor device comprises on a semiconductor substrate an insulating structure formed of a plurality of insulating films; an interconnection structure buried in the insulating structure and formed of a plurality of conducting layers; and a plurality of dummy patterns formed of the same conducting layer as the conducting layers... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070170592 - Apparatus for solder crack deflection: An apparatus that includes a first component defining an interior of the apparatus; a first solder composition exterior to the first component; a second solder composition exterior to the first solder composition and the first component; and a second component exterior to the second solder composition, the first solder composition,... Agent: Intel/blakely

20070170594 - Insulating tube, semiconductor device employing the tube, and method of manufacturing the same: An insulating tube includes a underlying insulating film, a first sidewall insulating film disposed on the underlying insulating film, a second sidewall insulating film disposed on the underlying insulating film, opposite to the first sidewall insulating film so as to provide a cavity between the first and second sidewall insulating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070170593 - Product including conductor made of zinc or zinc aluminum alloy: A hole is defined in a body of a product. A conductor made of zinc or a Zn—Al alloy fills the hole. Zinc or the Zn—Al alloy melts at a temperature equal to or higher than 375 degrees Celsius. Molten Zinc or Zn—Al alloy reliably fills the hole. Zinc and... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070170595 - Semiconductor device components with conductive vias and systems including the components: A semiconductor device component includes at least one conductive via. The at least one conductive via may include a seed layer for facilitating adhesion of a conductive material within the via aperture, a barrier material and solder, or a silicon-containing filler. Systems including such semiconductor device components are also disclosed.... Agent: Trask Britt, P.C./ Micron Technology

20070170596 - Flip-chip light emitting diode with high light-emitting efficiency: A flip-chip light emitting diode with high light-emitting efficiency is disclosed. The LED includes a transparent conductive layer, an oxide layer, a reflective metal layer, a conductive layer, and a protective diffusion layer sequentially disposed over a p-type semiconductor layer. Thereby, light emitting from a light-emitting layer toward the p-type... Agent: Rosenberg, Klein & Lee

20070170597 - Process for producing components: f

20070170598 - Flexible circuit board, method for making the same, flexible multi-layer wiring circuit board, and method for making the same: There is provided a flexible circuit board 22 that, when deposited on another flexible circuit board 40, causes no gap to occur between wiring films 4a, 4a, of the flexible circuit board 40. Moreover, a plurality of flexible circuit boards are deposited on one another to provide a flexible multi-layer... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070170599 - Flip-attached and underfilled stacked semiconductor devices: A tape for use as a carrier in semiconductor assembly, which has one or more base sheets 101 of polymeric, preferably thermoplastic, material having first (101a) and second (101b) surfaces. A polymeric adhesive film (102, 104) and a foil (103, 105) of different, preferably inert, material are attached to the... Agent: Texas Instruments Incorporated

20070170601 - Semiconductor device and manufacturing method of them: A semiconductor device which can meet the requirement for a further increase in pins, which multi-functionalization and faster operation would entail is to be provided. Bonding pads and bonding pads are arranged in a zigzag pattern in a direction along an outer circumference of a main surface of a chip.... Agent: Miles & Stockbridge PC

20070170600 - Semiconductor device and manufacturing method thereof: A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070170602 - Mold flash removal process for electronic devices: A method is provided for removing excess encapsulation material from unmolded surfaces of a molded substrate including semiconductor packages by utilizing an acid solution. The method comprises the steps of mounting the substrate to a holding device with the unmolded surfaces facing an acid source for supplying an acid solution,... Agent: Ostrolenk Faber Gerb & Soffen

20070170603 - Hybrid mounted device and method of manufacturing the same: There is provided a hybrid mounted device that includes a element such as semiconductor laser diode (LD), and a board such as a silicon platform having formed thereon an optical waveguide. The LD is mounted to the silicon platform, and is optically coupled to the optical waveguide. The mounting position... Agent: Young & Thompson

20070164265 - Semiconductor memory device: A semiconductor memory device includes a first write line which is provided in a first direction, a first memory element which is connected to the first write line, a second memory element which is provided to neighbor the first memory element in the first direction, and is connected to the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070164266 - Semiconductor device and method of manufacturing the same: There is provided a semiconductor device. The semiconductor device includes a lower electrode, a contact connected to the lower electrode to have a double trench structure, a phase change material layer accommodated in the double trench to cause a phase change between a crystalline state and an amorphous state in... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070164269 - Method for forming underlayer composed of gan-based compound semiconductor, gan-based semiconductor light-emitting element, and method for manufacturing gan-based semiconductor light-emitting element: A method for forming an underlayer composed of a GaN-based compound semiconductor is provided. In this method, at the time of epitaxial growth of an underlayer on the surface of a sapphire substrate, no gap is generated between the underlayer and the surface of the sapphire substrate. The method for... Agent: Bell, Boyd & Lloyd, LLP

20070164275 - Light-emitting device, method for manufacturing light-emitting device, and electronic apparatus: A light-emitting device includes an organic insulating layer lying above a face of a substrate, reflective layers arranged on a face of the organic insulating layer, an Inorganic insulating layer extending over the reflective layers, pixel electrodes arranged on the inorganic insulating layer, and light-emitting sections arranged on the respective... Agent: Oliff & Berridge, PLC

20070164277 - Organic light emitting display: An organic light emitting display (OLED) includes a substrate, first and second driving units positioned on the substrate, a first light emitting diode (LED) connected with the first driving unit and including a first organic light emitting layer and a second emitting diode electrically connected with the second driving unit... Agent: Ked & Associates, LLP

20070164283 - Electro-optical apparatus, method for manufacturing electro-optical apparatus, and electronic device: An electro-optical apparatus includes a base, a resin film on the base, the resin film having at least one of projections and depressions at an upper surface thereof, and a light reflecting film disposed on the at least one of projections and depressions. The resin film under the light reflecting... Agent: Harness, Dickey & Pierce, P.L.C

20070164282 - Electrooptic device, method for manufacturing the same, and conductive-layer connection structure: An electrooptic device includes: a plurality of data lines and a plurality of scanning lines that intersect on a substrate; a pixel electrode provided for each of pixels corresponding to the intersection of the data lines and the scanning lines; a first conductive layer provided for each pixel and a... Agent: Oliff & Berridge, PLC

20070164284 - Thin film transistor array substrate and method for manufacturing the same: A thin film transistor array substrate and a method for manufacturing the thin film transistor array substrate are disclosed. Specifically, a thin film transistor array may be formed using a reduced number of masks.... Agent: Brinks Hofer Gilson & Lione

20070164292 - Gan semiconductor light-emitting element and method for manufacturing the same: A GaN semiconductor light-emitting element is provided. The GaN semiconductor light-emitting element includes an island-type seed region composed of a GaN-based compound semiconductor disposed on a substrate; an underlying layer having a three-dimensional shape composed of a GaN-based compound semiconductor, disposed on at least the seed region; a first GaN-based... Agent: Bell, Boyd & Lloyd, LLP

20070164291 - Light emitting diode module, backlight assembly having the same, and display device having the same: A light emitting diode module, a backlight assembly having the light emitting diode module, and a display device having the backlight assembly. The light emitting diode module includes a light emitting device including a light emitting diode chip, a body that surrounds the light emitting diode chip, and a heat... Agent: F. Chau & Associates, LLC

20070164293 - Light-emitting device and method for the production of light-emitting device: The invention concerns a light-emitting device comprising an electroluminescent element as a light source and a light-detecting element disposed superimposed on the electroluminescent element for detecting the quantity of light emitted by the electroluminescent element to generate an electric signal for use in the correction of the quantity of light... Agent: Greenblum & Bernstein, P.L.C

20070164294 - Organic light emitting display: Provided is an organic light emitting display, comprising a substrate; a driving unit formed over the substrate; a planarization layer formed over the driving unit, the planarization layer comprising a normal tapered edge portion; and an emission unit formed over the planarization layer to be electrically connected to the driving... Agent: Ked & Associates, LLP

20070164302 - Light emitting device and method for producing the same: A light emitting device capable of efficiently dissipating heat outward, and a method producing it are provided. The light emitting device comprises an insulating board, a metal member, a light emitting element, a conductive member and a transparent member. The insulating board has a through hole. The metal member is... Agent: Ditthavong Mori & Steiner, P.C.

20070164264 - Storage system using an array of electro-magnetic sensors: A record carrier (40) of a removable type has an information plane that is provided with a pattern of an electro-magnetic material constituting an array of bit locations (11). The presence or absence of said material at the information plane represent the value of a bit location. The device has... Agent: Philips Intellectual Property & Standards

20070164267 - Electrically rewritable non-volatile memory element and method of manufacturing the same: A non-volatile memory element comprises a bottom electrode 12; a top electrode 15; and a recording layer 13 containing phase change material and a block layer 14 that can block phase change of the recording layer 13, provided between the bottom electrode 12 and the top electrode 15. The block... Agent: Mcdermott Will & Emery LLP

20070164268 - Method and apparatus for providing a light source that combines different color leds: A method for creating an improved signal light is disclosed. For example, the improved signal light includes a housing, one or more first type of light emitting diodes (LEDs) emitting a light energy having a first dominant wavelength deployed in the housing, one or more second type of LEDs emitting... Agent: Patterson & Sheridan L.L.P.

20070164270 - Methods of fabricating nanostructures and nanowires and devices fabricated therefrom: One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will... Agent: John P. O'banion O'banion & Ritchey LLP

20070164271 - Resonant nanostructures and methods of use: Resonant nanostructures (RNSs) are provided in one embodiment of the present invention. RNSs may be nano- to micro-scale structures that resonate at specific frequencies through the application of an electromagnetic or acoustic stimulus. Resonant nanostructures provide new tools for diagnosing and treating disease. Resonant activation (RA) is also provided. RA... Agent: Greenberg Traurig, LLP

20070164274 - Brightness enforcement diffussion construction: A brightness enforcement diffusion construction includes a transparent substrate made of plastic material e.g., PET, PMMA, MS, PS or PC, a diffusion layer disposed on one side of the light coupling or illuminating surface of the substrate, and brightness enforcement layer disposed on the other side; the diffusion layer contains... Agent: Troxell Law Office PLLC

20070164276 - Method for forming memory layers: Layers are produced, where the layers include a first layer formed of a metal and a second layer formed of an organic compound, the metal and the organic compound entering into an interaction, so that the layer serves as an electroactive layer for nonvolatile memories, the metal layer being deposited... Agent: Edell, Shapiro & Finnan, LLC

20070164273 - Organic electronic devices: The present invention relates to the improvement of organic electronic devices, in particular fluorescent electroluminescent devices, by using electron-transport materials of the formula (I).... Agent: Connolly Bove Lodge & Hutz, LLP

20070164278 - Organic light emitting device and flat display including the same: Provided are an organic light emitting device (OLED) and a flat display including the OLED. The OLED includes an organic layer which includes a pixel electrode, an opposite electrode, and at least an emission layer between the pixel electrode and the opposite electrode, wherein the emission layer includes a long... Agent: Knobbe Martens Olson & Bear LLP

20070164272 - Three-terminal electrical bistable devices: A three terminal electrical bistable device that includes a tri-layer composed of an electrically conductive mixed layer sandwiched between two layers of low conductivity organic material that is interposed between a top electrode and a bottom electrode. The conducting mixed layer serves as the middle electrode. The device includes two... Agent: Venable LLP

20070164279 - Semiconductor chip: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer... Agent: Megica Corporation

20070164285 - Electron injection composition for light emitting element, light emitting element, and light emitting device: (where each of R1 to R8 represents hydrogen, halogen, a cyano group, an alkyl group having 1 to 10 carbon atoms, a haloalkyl group having 1 to 10 carbon atoms, an alkoxyl group having 1 to 10 carbon atoms, a substituted or unsubstituted aryl group, or a substituted or unsbstituted... Agent: Eric Robinson

20070164281 - Input display: An input display is provided in the present invention. The input display includes a thin film transistor (TFT) and a light blocking layer. The TFT includes a low-field electrode, a high-field electrode connected to the low-field electrode with a connecting section, and a field-effect area positioned on the connecting section... Agent: Haverstock & Owens LLP

20070164286 - Liquid crystal display, thin film transistor array panel therefor, and manufacturing method thereof: A thin film transistor array panel is provided, which includes: a gate line formed on an insulating substrate; a gate insulating layer on the gate line; a semiconductor layer on the gate insulating layer; a data line formed on the gate insulating layer; a drain electrode formed at least in... Agent: Macpherson Kwok Chen & Heid LLP

20070164280 - Thin film transistor, manufacturing method for thin film transistor and manufacturing method for display device: The present invention provides a thin film transistor that can be manufactured at lower cost and at higher yield by simplifying a manufacturing process, a manufacturing method thereof, and a manufacturing method of a display device using the thin film transistor. According to this invention, a pattern used in a... Agent: Nixon Peabody, LLP

20070164287 - Thin film transistor, its manufacture method and display device: On an insulating substrate, a first insulating buffer layer, a heat accumulating-light shielding layer having at least a silicon layer on the surface thereof, a second insulating buffer layer and a first silicon layer are laminated in the order recited from the bottom. The lamination structure of the heat accumulating-light... Agent: Greer, Burns & Crain

20070164288 - Liquid crystal display panel and manufacturing method of the same: A liquid crystal display panel where pixel cells defined by gate lines and data lines which are located to cross each other are arranged in a matrix shape, wherein each of the pixel cells includes a thin film transistor located at a crossing of the gate line and the data... Agent: Seyfarth Shaw, LLP

20070164290 - Semiconductor device and method of fabricating the same: There is provided an active matrix type display device in which the display device is formed of a driver circuit with an insulated gate FET capable of operating at high speed, and even if an area of a pixel electrode per unit pixel is made small, sufficient storage capacitance can... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070164289 - Thin film transistor substrate and fabricating method thereof: A thin film transistor substrate and a fabricating method that includes an opening hole that separates a gate shorting line connected to a gate shorting bar used upon a lighting-inspecting of a gate line into an odd and an even gate shorting line is provided.... Agent: Brinks Hofer Gilson & Lione

20070164295 - Light emitting device and electronic apparatus: A light emitting device which is capable of suppressing deterioration by diffusion of impurities such as moisture, oxygen, alkaline metal and alkaline earth metal, and concretely, a flexible light emitting device which has light emitting element formed on a plastic substrate. On the plastic substrate, disposed are two layers and... Agent: Nixon Peabody, LLP

20070164296 - Gallium nitride-based compound semiconductor multilayer structure and production method thereof: An object of the present invention is to provide a gallium nitride compound semiconductor multilayer structure useful for producing a gallium nitride compound semiconductor light-emitting device which operates at low voltage while maintaining a satisfactory light emission output. The inventive gallium nitride compound semiconductor multilayer structure comprises a substrate, and... Agent: Sughrue Mion, PLLC

20070164297 - Optical-element integrated semiconductor integrated circuit and fabrication method thereof: Light-emitting device array 2 is mounted on LSI 1, following which necessary light-emitting devices 2a among two or more light-emitting devices 2 that make up mounted light-emitting device array 2 are allowed to remain and unnecessary light-emitting devices 2a are removed in order to mount light-emitting devices on a plurality... Agent: Scully Scott Murphy & Presser, PC

20070164298 - Led having vertical structure and method for fabricating the same: A light emitting diode (LED) having a vertical structure and a method for fabricating the same. The light emitting diode (LED) having a vertical structure includes a support layer; a first electrode formed on the support layer; a plurality of semiconductor layers formed on the first electrode; a conductive semiconductor... Agent: Mckenna Long & Aldridge LLP

20070164299 - Hemt piezoelectric structures with zero alloy disorder: Electronic circuits dedicated to high frequency and high power applications based on gallium nitride (GaN) suffer from reliability problems. The main reason is a non-homogenous distribution of the electronic density in these structures that originates from alloy disorders at the atomic and micrometric scale. This invention provides processes for manufacturing... Agent: Winston & Strawn LLP Patent Department

20070164301 - Light-emitting device with improved light-emitting brightness: A light-emitting device with improved light-emitting brightness comprises a first electrode and a second electrode on the upper surface of a light emitting element. On the positions opposite to the first electrode and the second electrode, a first power supply electrode and a second power supply electrode are provided on... Agent: Rosenberg, Klein & Lee

20070164300 - White light emitting diode (white led) and method of manufacturing white led: Disclosed is a white light emitting diode possessing a phosphor layer to convert blue light into yellow light, provided on a blue light emitting diode, wherein the phosphor layer possesses an inorganic compound containing a phosphor, and particularly a white light emitting diode, wherein this inorganic compound is a phosphor.... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070164303 - [led lamp]: A LED lamp includes a substrate, which has through holes cut through the top wall and bottom wall thereof and electric contacts fixedly provided at the top wall corresponding to the through holes for connection to power source, metal locating blocks respectively fixedly mounted in the through holes inside the... Agent: Lightop Technology Co., Ltd.

20070164304 - Compound semiconductor light-emitting diode: A compound semiconductor light-emitting diode comprising a light-emitting layer composed of a Group III-V compound semiconductor, and a current diffusion layer provided on the light-emitting layer and composed of a Group III-V compound semiconductor, characterized in that the current diffusion layer is composed of a conductive boron-phosphide-based semiconductor and has... Agent: Sughrue Mion, PLLC

20070164306 - Group iii nitride semiconductor crystal and method of its manufacture, group iii nitride semiconductor device and method of its manufacture, and light-emitting appliance: The invention provides Group III nitride semiconductor crystals of a size appropriate for semiconductor devices and methods for manufacturing the same, Group III nitride semiconductor devices and methods for manufacturing the same, and light-emitting appliances. A method of manufacturing a Group III nitride semiconductor crystal includes a process of growing... Agent: Judge & MurakamiIPAssociates

20070164308 - Light emitting apparatus and light emitting method: A light emitting apparatus has a light emitting element with an emission wavelength in the range of 360 to 550 nm and a rare-earth element doped oxide nitride phosphor or cerium ion doped lanthanum silicon nitride phosphor. Part of light radiated from the light emitting element is wavelength-converted by the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070164307 - Light emitting diode: A light emitting diode comprising a semiconductor layer, a first electrode, a second electrode and a diamond-like carbon layer is provided. The semiconductor layer includes a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer. Wherein, the light emitting layer locates between the... Agent: Jianq Chyun Intellectual Property Office

20070164305 - Ohmic electrode structure of nitride semiconductor device: An ohmic electrode structure of a nitride semiconductor device having a nitride semiconductor. The ohmic electrode structure is provided with a first metal film formed on the nitride semiconductor and a second metal film formed on the first metal film. The first metal film is composed of at least one... Agent: Young & Thompson

20070164309 - Method of making a diode read/write memory cell in a programmed state: A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.... Agent: Foley And Lardner LLP Suite 500

20070164310 - Electrostatic discharge element and diode having horizontal current paths, and method of manufacturing the same: An electrostatic discharge element includes a first diode and a second diode. The first diode has a first well region formed in a substrate, a P-type ion-implanted region formed in the first well region, an N-type ion-implanted region formed in the first well region and spaced from the P-type ion-implanted... Agent: Mills & Onello LLP

20070164311 - Ingaas/gaas lasers on-silicon produced by-lepecvd and mocvd:

20070164312 - Electronic devices formed of high-purity molybdenum oxide: The present invention is directed to electronic devices comprising high-purity molybdenum oxide in at least a part of the devices. The devices according to the present invention such as a bipolar transistor, a field effect transistor and a thyristor have a high withstand voltage. The present invention is directed also... Agent: Eric Robinson

20070164313 - Gallium nitride high electron mobility transistor structure: A semiconductor structure, comprising: a substrate; a first aluminum nitride (AlN) layer having an aluminum/reactive nitride (Al/N) flux ratio less than 1 disposed on the substrate; and a second AlN layer having an Al/reactive N flux ratio greater than 1 disposed on the first AlN layer. The substrate is a... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20070164315 - Cap layers including aluminum nitride for nitride-based transistors and methods of fabricating same: High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070164314 - Nitrogen polar iii-nitride heterojunction jfet: An N-polar III-nitride heterojunction JFET which includes a P-type III-nitride body under the gate electrode thereof.... Agent: Ostrolenk Faber Gerb & Soffen

20070164316 - Heterojunction bipolar transistor and method for manufacturing the same, and power amplifier using the same: A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070164317 - Cell and semiconductor device: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a... Agent: Mcdermott Will & Emery LLP

20070164318 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a semiconductor layer formed on a semiconductor substrate by performing epitaxial growth; a first buried insulating layer which is buried in the first region under the semiconductor layer; and a second buried insulating layer which is buried in the second region under the semiconductor layer in... Agent: Oliff & Berridge, PLC

20070164319 - Silicon pillars for vertical transistors: In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas... Agent: Knobbe Martens Olson & Bear LLP

20070164320 - Tunable semiconductor component provided with a current barrier: Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source.... Agent: Ronald S. Kosie Bcf LLP

20070164322 - Methods of fabricating transistors including dielectrically-supported gate electrodes and related devices: Transistors are fabricated by forming a protective layer having a first opening extending therethrough on a substrate, forming a dielectric layer on the protective layer having a second opening extending therethrough that is wider than the first opening, and forming a gate electrode in the first and second openings. A... Agent: Myers Bigel Sibley & Sajovec

20070164321 - Methods of fabricating transistors including supported gate electrodes and related devices: Transistors are fabricated by forming a protective layer having an opening extending therethrough on a substrate, and forming a gate electrode in the opening. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the opening, and a second portion of the gate... Agent: Myers Bigel Sibley & Sajovec

20070164323 - Cmos gates with intermetallic compound tunable work functions: Gates of at least one of NMOS transistors and PMOS transistors of a CMOS integrated circuit are formed with an intermetallic compound. The work function of the gate electrode is tunable by controlling the selection of the metals that form a layer of the intermetallic compound. In one embodiment, a... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070164324 - Electronic access control device: An electronic lock utilizes two microprocessors remote from each other for enhanced security. The first microprocessor is disposed close to an input device such as a keypad, and the second microprocessor is disposed close to the lock mechanism and well protected from external access. The first microprocessor transmits a communication... Agent: Factor & Lake, Ltd

20070164325 - Three-dimensional multi-gate device and fabricating method thereof: A three-dimensional multi-gate device has a silicon fin, a gate structure, and a stress-adjusting layer. The gate structure contacts with three surface of the silicon fin to form a three-dimensional gate structure. The stress-adjusting layer is disposed on the gate structure to provide stress along the direction parallel to the... Agent: North America Intellectual Property Corporation

20070164327 - Protection element and fabrication method for the same: The protection element of the present invention is constructed of a MOS capacitor composed of a semiconductor substrate, an insulating film formed on the semiconductor substrate and a word line formed on the insulating film. A well region having a conductivity type opposite to that of the semiconductor substrate is... Agent: Mcdermott Will & Emery LLP

20070164326 - Field effect transistor: A field effect transistor includes a semiconductor layer structure including GaN channel layer 12 and AlGa electron supply layer 13, source electrode 1 and drain electrode 3 which are formed on electron supply layer 13 so as to be separated from each other, gate electrode 2 formed between source electrode... Agent: Sughrue Mion, PLLC

20070164328 - Method of manufacturing semiconductor device and the semiconductor device manufactured by the method: The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that... Agent: Oliff & Berridge, PLC

20070164330 - Display substrate and method of manufacturing the same: A display substrate includes a base substrate, a first metal pattern, a gate insulating layer, a second metal pattern, a channel layer and a pixel electrode. The first metal pattern is formed on the base substrate, and includes a gate line and a gate electrode of a switching element. The... Agent: Cantor Colburn, LLP

20070164329 - Light-collecting device and solid-state imaging apparatus: The light-collecting device includes light-transmitting films 101 which form concentric circles wherein, in each area divided by a constant width 103 of the divided area in an in-plane direction, a sum of line widths of a width 103 in the divided area is different each other. In each divided area,... Agent: Greenblum & Bernstein, P.L.C

20070164331 - Thin film transistor substrate for display device and fabricating method thereof: A thin film transistor (TFT) substrate is fabricated in three mask processes. In a first mask process, a gate line and a gate electrode are formed. In a second mask process, a data line, a source electrode, a drain electrode, a semiconductor layer, and a first upper storage electrode overlapping... Agent: Mckenna Long & Aldridge LLP

20070164332 - Shared-pixel-type image sensors for controlling capacitance of floating diffusion region: A shared-pixel-type image sensor includes a semiconductor substrate, four photoelectric conversion elements disposed adjacent to one another in one direction on the semiconductor substrate, two first transmission elements transmitting charges accumulated in two adjacent ones of the photoelectric conversion elements to a first floating diffusion region, respectively, two second transmission... Agent: Lee & Morse, P.C.

20070164333 - Integrated mis photosensitive device using continuous films: An integrated photosensitive device with a metal-insulator-semiconductor (MIS) photodiode constructed with one or more substantially continuous layers of semiconductor material and with a substantially continuous layer of dielectric material.... Agent: Vedder Price Kaufman & Kammholz

20070164335 - Pixel cells in a honeycomb arrangement: The present invention, in the various exemplary embodiments, provides a RGB color filter array. The red, green and blue pixel cells are arranged in a honeycomb pattern. The honeycomb layout provides the space to vary the size of pixel cells of an individual color so that, for example, the photosensor... Agent: Dickstein Shapiro LLP

20070164334 - Solid-state imaging device, production method and drive method thereof, and camera: A solid-state imaging device capable of reducing an eclipse (blocking) of an incident light at a circumferential portion of a light receiving portion and realizing a larger angle of view and high-speed driving. A single-layer transfer electrode configuration of forming first transfer electrodes and second transfer electrodes by one polysilicon... Agent: David R. Metzger Sonnenschein Nath & Rosenthal

20070164336 - Spin fet and spin memory: A spin FET according to an example of the present invention includes a magnetic pinned layer whose magnetization direction is fixed, a magnetic free layer whose magnetization direction is changed, a channel between the magnetic pinned layer and the magnetic free layer, a gate electrode provided on the channel via... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070164337 - Flip feram cell and method to form same: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric... Agent: Scully, Scott, Murphy & Presser, P.C.

20070164338 - Method of forming nano-sized mtj cell without contact hole: Provided is a method of manufacturing a nano-sized MTJ cell in which a contact in the MTJ cell is formed without forming a contact hole. The method of forming the MTJ cell includes forming an MTJ layer on a substrate, forming an MTJ cell region by patterning the MTJ layer,... Agent: Buchanan, Ingersoll & Rooney PC

20070164339 - Semiconductor device and manufacturing method thereof: A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070164340 - Semiconductor memory device: A semiconductor memory device excellent in data holding characteristics even when a cell area is reduced is disclosed. According to one aspect of the present invention, a semiconductor memory device comprises a transistor including a source, a drain and a channel region disposed in a semiconductor substrate, and including a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070164341 - Nonvolatile semiconductor memory device comprising shield electrode on source and method for manufacturing the same: A nonvolatile semiconductor memory device includes floating gates, source areas, drain areas, word lines, diffusion layers, source lines and shield wires. The source area is shared by the floating gates adjacent to each other in a column direction. The drain area faces the source area in the column direction with... Agent: Hogan & Hartson L.L.P.

20070164342 - Semiconductor memory device and method of manufacturing the same: A polysilicon film forming a memory gate interconnection and the like includes a part extending from a part positioned on one side surface of a control gate interconnection to a side opposite to a side where the control gate interconnection is positioned, and that part serves as a pad portion.... Agent: Mcdermott Will & Emery LLP

20070164344 - Nonvolatile semiconductor device and method of fabricating the same: A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the... Agent: F. Chau & Associates, LLC

20070164343 - Nonvolatile semiconductor memory device having element isolating region of trench type: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070164345 - Semiconductor device and method of manufacturing the same: An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion below the floating gate electrode. The first insulating film... Agent: Mcdermott Will & Emery LLP

20070164347 - Non-volatile memory devices suitable for lcd driver applications: Non-volatile memory devices according to embodiments of the present invention include an EEPROM transistor in a first portion of a semiconductor substrate, an access transistor in a second portion of the semiconductor substrate and an erase transistor in a third portion of the semiconductor substrate. The second portion of the... Agent: Myers Bigel Sibley & Sajovec

20070164348 - Contactless uniform-tunneling separate p-well (cusp)non-volatile memory array architecture, fabrication and operation: Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain... Agent: Leffert Jay & Polglaze P.A.

20070164346 - Semiconductor device: A semiconductor device is disclosed that includes a nonvolatile memory cell having a memory transistor and a selection transistor, and a peripheral circuit transistor. The memory transistor includes a memory gate oxide film that is arranged on a semiconductor substrate, and a floating gate made of polysilicon that is arranged... Agent: Cooper & Dunham, LLP

20070164349 - Circuit board, circuit apparatus, and method of manufacturing the circuit board: A circuit board includes a substrate and an insulating layer. The substrate has a first surface. The insulating layer has a second surface and is connected to the substrate. The first surface is in contact with the second surface. Heat-conductive particles are provided in the insulating layer. A part of... Agent: Ditthavong Mori & Steiner, P.C.

20070164350 - Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device: A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive enhancement layer are... Agent: Micron Technology, Inc.

20070164351 - Semiconductor device and method for manufacturing the same: A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070164352 - Multi-bit-per-cell nvm structures and architecture: A transistor structure, such as a Double-gated FET (DG FET), that has been modified to include a charge-trapping region used to store either 2- or 4-bits of information. The charge-trapping region can, for example, be embedded in the gate dielectric stack underneath each gate electrode, or placed on the sidewalls... Agent: John P. O'banion O'banion & Ritchey LLP

20070164354 - Mos transistor with elevated source and drain structures and method of fabrication thereof: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In... Agent: Mills & Onello LLP

20070164353 - Semiconductor device and method for manufacturing the same: A semiconductor device of the present invention includes vertical double diffused MOS transistor. A gate electrode of the vertical double diffused MOS transistor is disposed within a trench formed on a semiconductor substrate and projects from a surface of the semiconductor substrate. On a side surface of the gate electrode,... Agent: Rabin & Berdo, PC

20070164355 - Semiconductor device of high breakdown voltage and manufacturing method thereof: Disclosed are a semiconductor device of high breakdown voltage and a method manufacturing the same. According to the invention, it is possible to previously prevent an increase size of the device due to a separation of a high concentration impurity layer and a gate electrode pattern by embedding the gate... Agent: Ipla P.A.

20070164359 - Area-efficient gated diode structure and method of forming same: An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, and at least one trench electrode extending substantially vertically through the active region and at least... Agent: Wayne L. Ellenbogen Ryan, Mason & Lewis, LLP

20070164361 - Micro-mechanically strained semiconductor film: A semiconductor structure embodiment comprises a semiconductor membrane with local strained areas. The membrane with local strained areas is formed by a process including performing a local oxidation of silicon (LOCOS) process in a substrate and removing resulting oxide to form a recess in the substrate, and bonding a semiconductor... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070164360 - Semiconductor device and method of fabricating the same: A semiconductor device has a supporting substrate applied with a predetermined potential, an insulating layer formed on the supporting substrate, a semiconductor layer formed on the insulating layer, a FDSOI transistor formed on the semiconductor layer and including a source region, a drain region, and a channel region, the channel... Agent: Foley And Lardner LLP Suite 500

20070164356 - Strained semiconductor-on-insulator (ssoi) by a simox method: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that... Agent: Scully Scott Murphy & Presser, PC

20070164357 - Structure and method for mosfet gate electrode landing pad: A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070164358 - Structure and method to form semiconductor-on-pores (sop) for high device performance and low manufacturing cost: A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein... Agent: Scully Scott Murphy & Presser, PC

20070164362 - System and method for i/o esd protection with floating and/or biased polysilicon regions: A system and method for electrostatic discharge protection. The system includes a plurality of transistors. The plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The plurality of source regions and the plurality of drain regions are located within... Agent: Townsend And Townsend And Crew, LLP

20070164363 - Semiconductor device including capacitive circuit and short-circuit preventing circuit connected in series: In a semiconductor circuit device including a first terminal adapted to receive a first voltage and a second terminal adapted to receive a second voltage lower than the first voltage, a capacitive circuit and a short-circuit preventing circuit are provided in series between the first and second terminals. In this... Agent: Young & Thompson

20070164364 - Semiconductor device using sige for substrate and method for fabricating the same: A semiconductor device includes a first semiconductor layer, an n-type/p-type second semiconductor layer, p-type/n-type third semiconductor layers and a first gate electrode. The second semiconductor layer is formed on the first semiconductor layer and has an oxidation rate which is lower than that of the first semiconductor layer. The third... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070164367 - Cmos gates with solid-solution alloy tunable work functions: Gates of at least one of NMOS transistors and PMOS transistors of a CMOS integrated circuit are formed with a solid-solution alloy of at least two metals. The work function of the gate electrode is tunable by controlling the selection of the metals or the relative proportion of the metals... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070164366 - Mitigation of gate oxide thinning in dual gate cmos process technology: Excessive thinning of a thin oxide in a dual gate CMOS fabrication process is mitigated. A thick gate oxide utilized to form high voltage transistors is selectively patterned to leave some thick oxide in an active area where low voltage transistors are formed. Due to fabrication conditions, the thin gate... Agent: Texas Instruments Incorporated

20070164365 - Single stress liner for migration stability and speed: A single stress liner is applied over different type semiconductor devices. The single stress liner avoids the problems of a dual/hybrid stress liner scheme by eliminating the meeting area. The single stress liner may be tensile or compressive. In one embodiment, the semiconductor device includes a static random access memory... Agent: Hoffman, Warnick & D'alessandro LLC

20070164368 - Sram device having a common contact: Embodiments relate to a SRAM, in which a well isolation method may be applied so that an N-well and a P-well are separated from each other and that well walls of opposite conductive types are formed on facing sides. Also, the active regions of NMOS and PMOS may be connected... Agent: Sherr & Nourse, PLLC

20070164369 - Cobalt silicidation process for substrates comprised with a silicon-germanium layer: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source... Agent: Haynes And Boone, LLP

20070164370 - Semiconductor device and fabricating method thereof: A semiconductor device is provided. The semiconductor device comprises a substrate, a stacked gate structure, doped regions and high stress material layers. The stacked gate structure is located on the substrate. The stacked gate structure includes at least a dielectric layer and a gate sequentially disposed over the substrate. The... Agent: J.c. Patents, Inc.

20070164371 - Reliability degradation compensation using body bias: A system may include detection of reliability degradation of a transistor, and change of a body bias applied to the transistor based on the detected reliability degradation.... Agent: Buckley, Maschoff & Talwalkar LLC Attorneys For Intel Corporation

20070164373 - Mos transistor with elevated source and drain structures and method of fabrication thereof: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In... Agent: Mills & Onello LLP

20070164372 - Systems and methods for forming additional metal routing in semiconductor devices: Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate regions of the memory device. As the size of semiconductor components decreases and circuit densities increase, the density of the metal routing... Agent: Knobbe Martens Olson & Bear LLP

20070164374 - Molecular memory devices including solid-state dielectric layers and related methods: According to some embodiments, an article of manufacture comprises a substrate; a molecular layer on the substrate comprising at least one charge storage molecule coupled to the substrate by a molecular linker; a solid barrier dielectric layer directly on the molecular layer; and a conductive layer directly on the solid... Agent: Morgan, Lewis & Bockius, LLP.

20070164375 - Semiconductor device and manufacturing method thereof: A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070164376 - Method for edge sealing barrier films: An edge-sealed, encapsulated environmentally sensitive device. The device includes an environmentally sensitive device, and at least one edge-sealed barrier stack. The edge-sealed barrier stack includes a decoupling layer and at least two barrier layers. The environmentally sensitive device is sealed between an edge-sealed barrier stack and either a substrate or... Agent: Dinsmore & Shohl LLP One Dayton Centre

20070164377 - Semiconductor sensor using surface plasmons to increase energy absorption efficiency: Surface plasmons are used to increase an energy absorbing efficiency of a semiconductor sensor.... Agent: Agilent Technologies Inc.

20070164378 - Integrated mems package: Systems and methods of fabricating an integrated Micro-Electro-Mechanical Systems (MEMS) package. The MEMS package includes a substrate that has a substantially planar first surface including a cavity configured to receive a MEMS die. A substantially planar second surface is parallel to and spaced apart from the first surface. The second... Agent: Honeywell International Inc.

20070164379 - Isolation scheme for reducing film stress in a mems device: A method of electrically isolating a MEMS device is provided. In one example, a piezo-resistive pressure sensor having an exposed silicon region undergoes a Local Oxidation of Silicon (LOCOS) process. An electrically insulating structure is created in the LOCOS process. The insulating structure has a rounded, or curved, interface with... Agent: Honeywell International Inc.

20070164382 - Magnetic transistor: A magnetic transistor includes a magnetic section, a thin semiconductor layer, a first metal terminal, a second metal terminal, and a third metal terminal. The thin semiconductor layer is disposed on the magnetic section. The first metal terminal is disposed on one end of the magnetic section, acting as a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070164380 - Mram with split read-write cell structures: An MRAM cell is formed in two separate portions. A first portion, that includes a pinned layer, a tunneling barrier layer and first free layer part, is used to read the value of a stored bit of information. A second portion includes a second free layer part on which information... Agent: George O. Saile

20070164381 - Structure and method for a magnetic memory device with proximity writing: An MRAM device comprises a plurality of MRAM structures, each MRAM structure comprising a magnetoresistive memory cell in close proximity to a high permeability conductive line and a single transistor configured to access the magnetoresistive memory cell for both read and write operations. The high permeability conductive line acts a... Agent: Baker & Mckenzie LLP Patent Department

20070164383 - Magnetic random access memory with improved writing margin: A magnetic memory with improved writing margin is provided, which includes a magnetic tunnel junction device and an adjustment layer. The magnetic tunnel junction device includes an anti-ferromagnetic layer, a pinned layer, a tunnel barrier layer, and a free layer formed sequentially. The adjustment layer is formed on one side... Agent: Harness, Dickey & Pierce, P.L.C

20070164385 - Germanium/silicon avalanche photodetector with separate absorption and multiplication regions: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of... Agent: Blakely Sokoloff Taylor & Zafman

20070164384 - Solid-state imaging device and method for manufacturing the same: The solid-state imaging device includes at least a silicon layer formed with a photo sensor portion and a wiring layer formed on the front-surface side of the silicon layer, and in which light L is made to enter from the rear-surface side opposite to the front-surface side of the silicon... Agent: Sonnenschein Nath & Rosenthal LLP

20070164386 - Semiconductor device and fabrication method thereof: A semiconductor device and the fabrication method thereof are provided. The fabrication method includes providing a substrate module plate having a plurality of substrates; attaching at least one sensor chip to each of the substrates of the substrate module plate; electrically connecting each of the sensor chips to each of... Agent: Edwards Angell Palmer & Dodge LLP

20070164387 - Imaging system for correcting dark level with high accuracy: A digital camera is provided that includes an image pick-up subsection whose CCD includes a shaded sub-pixel, and a signal processor that includes a dark processor and a sub-signal processor. The digital camera acquires a dark current in an effective pixel area and a leak signal or leak data during... Agent: Birch Stewart Kolasch & Birch

20070164388 - Memory cell comprising a diode fabricated in a low resistivity, programmed state: A memory device includes at least one diode memory cell. The diode is fabricated in a low resistivity, programmed state.... Agent: Foley And Lardner LLP Suite 500

20070164389 - Cmos image sensor: Embodiments relate to an image sensor that may use a passivation layer and a method for manufacturing the same. In embodiments, an image sensor may include a semiconductor substrate on which a photodiode and a transistor for the image sensor are formed, and a passivation layer formed over an entire... Agent: Sherr & Nourse, PLLC

20070164390 - Silicon nitride passivation layers having oxidized interface: A method of forming a passivation film on a semiconductor substrate is provided and includes forming a first silicon nitride containing layer on the substrate, oxidizing the surface of the first silicon nitride containing layer, and forming a second silicon nitride containing layer on the oxidized surface of the first... Agent: Dinsmore & Shohl LLP

20070164391 - Trench isolation type semiconductor device and related method of manufacture: A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate,... Agent: Volentine & Whitt PLLC

20070164392 - Semiconductor device: Embodiments relate to a semiconductor device. According to embodiments, a semiconductor device may include a plurality of wells formed on a substrate, threshold voltage control ion layers formed around surfaces of the wells, device isolation layers arranged between the wells, ion compensation layers formed on edges and bottoms of the... Agent: Sherr & Nourse, PLLC

20070164393 - Photodetector comprising a monolithically integrated transimpedance amplifier and evaluation electronics, and production method: The aim of the invention is to configure a photodetector (10) such that no disadvantages are created for processing low luminous intensities on detectors known in prior art, especially when monolithically integrating the evalation electronics. Said aim is achieved by a photodetector for processing low luminous intensities, comprising a monolithically... Agent: Duane Morris, LLPIPDepartment

20070164394 - Semiconductor device: On a semiconductor substrate a silicon oxide film is formed and provided with a recess. In the recess a reflector layer of copper is disposed as a blocking layer with a barrier metal posed therebetween. The reflector layer of copper is covered with a silicon oxide film and thereon a... Agent: Mcdermott Will & Emery LLP

20070164396 - Multi-functional composite substrate structure: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may... Agent: Rabin & Berdo, PC

20070164395 - Chip package with built-in capacitor structure: A chip package with built-in capacitor structure including an integrated circuit (IC) unit, a capacitor unit, a carrier and a molding compound is provided. The capacitor unit is disposed on the IC unit and includes a first metal foil, a second metal foil, and a dielectric layer disposed between the... Agent: Jianq Chyun Intellectual Property Office

20070164397 - Process for forming a buried plate: A method is provided for making a buried plate region in a semiconductor substrate. According to such method, a trench is a single-crystal semiconductor region of a substrate is etched to form a trench elongated in a direction extending downwardly from a major surface of the substrate. A dopant source... Agent: International Business Machines Corporation Dept. 18g

20070164398 - Co-sputter deposition of metal-doped chalcogenides: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped... Agent: Dickstein Shapiro LLP

20070164399 - Hard coating for glass molding and glass molding die having the hard coating: A hard coating combining excellent mold releasability with respect to glass with excellent durability at high temperature environment of 600° C. or more, and a glass molding die having the hard coating are provided. A glass molding die has a hard coating formed on a molding surface of a base.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070164400 - Substrate structure and method for forming patterned layer on substrate structure: A substrate structure includes a substrate and a number of banks formed on the substrate. The banks and the substrate cooperatively define a number of accommodating rooms. The accommodating rooms are configured for accommodating ink. A spread-control layer is formed on the substrate beneath the accommodating rooms. The spread-control layer... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070164401 - Differential transmission line structure and wiring substrate: A differential transmission line structure comprises an insulating layer, a grounded conductive layer laminated to the insulating layer, and a differential transmission line formed in the insulating layer. A region in which the conductive layer is removed is formed in correspondence with a position of the differential transmission line.... Agent: Drinker Biddle & Reath (dc)

20070164404 - Semiconductor package: A semiconductor package may include a semiconductor chip assembly, a signal input/output member and an encapsulating member. The semiconductor chip assembly may include first pads and second pads. The first pads may be exposed in a first direction. The second pads may be exposed in a second direction substantially opposite... Agent: Harness, Dickey & Pierce, P.L.C

20070164403 - Semiconductor package structure and fabrication method thereof: A semiconductor package structure and a fabrication method thereof are provided. A semiconductor chip having an active surface and an inactive surface is coupled to a substrate. A plurality of bond pads are formed on the active surface of the semiconductor chip. The substrate can be arranged to expose the... Agent: Edwards Angell Palmer & Dodge LLP

20070164406 - Leadless lead-frame: A leadless lead-frame mainly includes a chip paddle and a plurality of leads. The chip paddle has chip disposal areas, and a grounding area surrounding the chip disposal area. The grounding area has a recession with a recession-bottom and a recession-wall connecting to the recession-bottom. An angle is formed between... Agent: Bacon & Thomas, PLLC

20070164405 - Low cost method to produce high volume lead frames: A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222) on all surfaces of the lead frame material (108), and subsequently forming a plurality of internal leads (124) in the lead frame material... Agent: Texas Instruments Incorporated

20070164402 - Semiconductor package and process for making the same: A semiconductor package mainly includes a leadframe and a first semiconductor chip such as an application specific integrated circuit (ASIC) encapsulated in a first package body having a cavity for receiving a second semiconductor chip such as a pressure sensor chip, and a cover disposed over the cavity of the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070164407 - Double encapsulated semiconductor package and manufacturing method thereof: A double encapsulated semiconductor package and manufacturing methods of forming the same are provided. Embodiments of the semiconductor package include a complex chip having normal and random pads formed on its active surface, the complex chip being attached to a first surface of a wiring substrate. First and second windows... Agent: Marger Johnson & Mccollom, P.C.

20070164408 - Light emitting diode packaging structure: A light emitting diode (LED) packaging structure includes a package body, a lead frame and a reflective wall. The package body includes a chip accommodating space for an LED chip, and a portion of the lead frame is exposed to the chip accommodating space. The reflective wall is connected with... Agent: Rosenberg, Klein & Lee

20070164411 - Semiconductor package structure and fabrication method thereof: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor chip having an active surface, a inactive surface, and a plurality of bond pads formed on the active surface; coupling one or more substrates to the active surface in such a way... Agent: Edwards Angell Palmer & Dodge LLP

20070164412 - Method of wire bonding over active area of a semiconductor circuit: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over... Agent: Megica Corporation

20070164409 - Semiconductor package with integrated heatsink and electromagnetic shield: The invention provides a mounting for a printed circuit board which mounting is suitable for receiving a semiconductor assembly wherein the mounting comprises: a base support having a semiconductor assembly facing surface, and an opposed printed surface board facing surface; a cover having a semiconductor assembly facing surface, an opposed... Agent: Hoffmann & Baron, LLP

20070164410 - Wafer level packaging cap and fabrication method thereof: A fabrication method of a wafer level packaging cap for covering a device wafer provided with a device thereon, includes forming an insulating layer on a wafer; removing a predetermined part of the insulating layer and exposing an upper surface of the wafer; forming a cap pad extending from an... Agent: Sughrue Mion, PLLC

20070164415 - Semiconductor device including bus with signal lines: A semiconductor memory device has the group of longest signal lines configured in a twisted wiring scheme, the group of signal lines of intermediate length configured in a shield wiring scheme, and the group of shortest signal lines configured in a single wiring scheme. As a whole, degradation in signal... Agent: Buchanan, Ingersoll & Rooney PC

20070164413 - Semiconductor device: The invention provides a semiconductor device which can reliably restrict transmission/reception of signals or a power source voltage between a reader/writer when peeled off after stuck to an object. The semiconductor device of the invention includes an integrated circuit and an antenna formed on a support base. In the semiconductor... Agent: Eric Robinson

20070164414 - Wireless ic device and component for wireless ic device: A wireless IC device includes a wireless IC chip, a power supply circuit board upon which the wireless IC chip is mounted, and in which a power supply circuit is provided, the power supply circuit includes a resonant circuit having a predetermined resonant frequency, and a radiation pattern, which is... Agent: Murata Manufacturing Company, Ltd. C/o Keating & Bennett, LLP

20070164416 - Managed memory component: A system and method for combining a leaded package IC and a semiconductor die using a flex circuitry. The leaded packaged IC is disposed along an obverse side of a flex circuit. In a preferred embodiment, the lower surface of the body of the leaded packaged IC contacts the surface... Agent: Fish & Richardson P.C.

20070164417 - Design and fabrication method for microsensor: A method for fabricating a micro-sensor device comprising the steps of fabricating on a parent substrate (10) at least one sensor element (21); forming an interconnect layer (32) having first and second surfaces remotely to the parent substrate (10) so as to enclose the at least one sensor element (21)... Agent: Nixon & Vanderhye, PC

20070164418 - Semiconductor module comprising semiconductor chips and method for producing the same: A semiconductor module includes: a plastic housing composition; at least one semiconductor chip with an active top side, a coplanar underside of the semiconductor module including the active top side of the semiconductor chip(s) and a surface of the plastic housing composition; a wiring structure arranged on the coplanar underside,... Agent: Edell, Shapiro & Finnan, LLC

20070164419 - Device package and methods for the fabrication and testing thereof: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second... Agent: Rohm And Haas Electronic Materials LLC

20070164420 - Apparatus and methods for packaging dielectric resonator antennas with integrated circuit chips: Apparatus and methods are provided for integrally packaging antenna devices with semiconductor IC (integrated circuit) chips, wherein IC chips are packaged with dielectric resonators antennas that are integrally constructed as part of a package molding (encapsulation) process, for example, to form compact integrated radio/wireless communications systems for millimeter wave applications.... Agent: F. Chau & Associates, LLC

20070164421 - Structure to monitor arcing in the processing steps of metal layer build on silicon-on-insulator semiconductors: The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge... Agent: Law Office Of Delio & Peterson, LLC.

20070164422 - Semiconductor wafer scale package system: A semiconductor wafer scale package system is provided including providing a semiconductor substrate having a through-hole via with a conductive coating, forming a filled via by filling the through-hole via with a conductive material, coupling a package substrate to the filled via, and singulating a chip scale package from the... Agent: Ishimaru & Zahrt LLP

20070164423 - Multi-chip semiconductor package: A multi-chip semiconductor package that includes two power semiconductor devices arranged in a half-bridge configuration between two opposing circuit boards.... Agent: Ostrolenk Faber Gerb & Soffen

20070164424 - Thermal interconnect and interface systems, methods of production and uses thereof: Components and materials, including thermal transfer materials, contemplated herein comprise at least one heat spreader component, at least one thermal interface material and in some contemplated embodiments at least one adhesive material. The heat spreader component comprises a top surface, a bottom surface and at least one heat spreader material.... Agent: Buchalter Nemer

20070164425 - Thermally enhanced semiconductor package and method of producing the same: This invention includes a heat sink structure for use in a semiconductor package that includes a ring structure with down sets and a heat sink connected to the ring structure. The down sets can be slanted or V-shaped. The invention also includes a method of manufacturing a semiconductor package that... Agent: Sughrue Mion, PLLC

20070164426 - Apparatus and method for integrated circuit cooling during testing and image based analysis: An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of... Agent: Cantor Colburn LLP - IBM Fishkill

20070164427 - Electromagnetically-actuated micropump for liquid metal alloy enclosed in cavity with flexible sidewalls: The present invention discloses a method of confining a liquid metal alloy within a closed-loop system; distributing a first portion of the liquid metal alloy in a cavity within the closed-loop system; turning on an electromagnet to generate a magnetic field to permeate flexible sidewalls of the cavity; attracting the... Agent: Intel Corporation C/o Intellevate, LLC

20070164429 - Package board having internal terminal interconnection and semiconductor package employing the same: A package board is provided. The package board includes a board body having a front surface and a back surface. A first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad are disposed on the front surface of... Agent: Marger Johnson & Mccollom, P.C.

20070164430 - Carbon nanotube circuit component structure: The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer,... Agent: Megica Corporation

20070164428 - High power module with open frame package: A semiconductor assembly is disclosed. The semiconductor assembly includes a multilayer substrate having at least two layers with conductive patterns insulated by at least two dielectric layers. The substrate includes a first surface and a second surface. A leadless package comprising a control chip is coupled to the multilayer substrate.... Agent: Townsend And Townsend And Crew, LLP

20070164431 - Wafer level chip scale package having rerouting layer and method of manufacturing the same: A wafer level chip scale package capable of reducing parasitic capacitances between a rerouting and the metal wiring of a wafer, and a method for manufacturing the same are provided. An embodiment of the wafer level chip scale package includes a wafer arranged with a plurality of bonding pads and... Agent: Marger Johnson & Mccollom, P.C.

20070164432 - Semiconductor device having alignment post electrode and method of manufacturing the same: A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070164433 - Ball grid array package: A ball grid array package includes a substrate with a top and bottom surface. A circuit component is located on the bottom surface. The circuit component has a pair of ends. A pair of conductors are located on the bottom surface. The conductors are connected to the ends of the... Agent: Cts Corporation

20070164435 - Semiconductor device: To reduce noise between a power supply wiring and ground wiring especially in a small, high-density semiconductor device for high-speed operation. A semiconductor device having a second dielectric layer 5 made of dielectric material of which the dielectric loss tan 6 is at least 0.2 and interposed between a power... Agent: Sughrue Mion, PLLC

20070164434 - Semiconductor device having wiring made by damascene method and capacitor and its manufacture method: A wiring trench is formed in an interlayer insulating film partway in the depth direction of the interlayer insulating film. A via hole is formed extending from the bottom of the wiring trench to the bottom of the interlayer insulating film. A capacitor recess is formed reaching the bottom of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070164436 - Dual metal interconnection: Embodiments relate to a dual metal interconnection structure of a semiconductor device and a method for manufacturing the same. In embodiments, the dual metal interconnection structure may include a contact plug selectively formed in an interlayer dielectric, which covers a silicon substrate, and contacted with an active area of the... Agent: Sherr & Nourse, PLLC

20070164438 - Interconnects with interlocks: Embodiments include interconnect of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a trench and via in the dielectric layer, the via extending to the contact surface. An interlock material is in the via with an interlock opening extending through the interlock... Agent: Intel/blakely

20070164437 - Semiconductor device and method of manufacturing the same: There is included an inorganic insulating film having a porous structure including a cylindrical vacancy oriented in parallel with the surface of a substrate subjected to a hydrophilic treatment or a hydrophobic treatment.... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20070164440 - Semiconductor device, dicing saw and method for manufacturing the semiconductor device: A first interlayer insulating film and a second interlayer insulating film are formed on a semiconductor substrate and first Cu interconnections are formed in the first interlayer insulating film and second Cu interconnections are formed in the second interlayer insulating film. Pad electrodes are formed on the second Cu interconnections... Agent: Mcdermott Will & Emery LLP

20070164439 - In-situ deposition for cu hillock suppression: A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than... Agent: Slater & Matsil, L.L.P.

20070164441 - Method of wire bonding over active area of a semiconductor circuit: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over... Agent: Megica Corporation

20070164442 - Use of ain as cooper passivation layer and thermal conductor: A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer passivates the copper layer surface and enhances the thermal conductivity of a semiconductor substrate by radiating heat from the substrate as well as from the... Agent: Dickstein Shapiro LLP

20070164443 - Semiconductor array and method for manufacturing a semiconductor array: c

20070164445 - Substrate and semiconductor device: Aiming at adjusting the height of bump electrodes connected to lands on a substrate, a semiconductor device 100 has a first interconnect substrate 103 and a second interconnect substrate 101. On one surface of these substrates, first lands 111 and second lands 113 are provided. The plane geometry of the... Agent: Young & Thompson

20070164444 - Stacked mounting structure: A stacked mounting structure includes at least two substrates namely a first substrate on which a first protruding electrode is formed and a second substrate on which a second protruding electrode is formed, and an intermediate substrate which is disposed between the first substrate and the second substrate, and which... Agent: Thomas Spinelli Scully, Scott, Murphy & Presser

20070164449 - Build-up package of optoelectronic chip: A build-up package of an optoelectronic chip mainly includes a transparent circuit carrier board, at least one optoelectronic chip, at least one dielectric layer and at least one wiring layer of a build-up package. The optoelectronic chip is flip-chip bonded to the transparent circuit carrier board. The build-up package is... Agent: Jianq Chyun Intellectual Property Office

20070164448 - Semiconductor chip package with attached electronic devices, and integrated circuit module having the same: Provided are a semiconductor chip package with attached electronic devices, and an integrated circuit module having the same. The semiconductor chip packages may include a supporting substrate, input/output bonding pads arranged on a first plane of the supporting substrate, and device bonding pads arranged on the edges of the first... Agent: Harness, Dickey & Pierce, P.L.C

20070164450 - Integrated circuit (ic) carrier assembly with suspension means: An integrated circuit (IC) carrier assembly includes a printed circuit board (PCB). A carrier is soldered to the PCB. The carrier includes a plurality of electrical contact islands surrounding a receiving zone for receiving an IC. Pairs of adjacent islands are interconnected by respective resilient suspension means. The IC is... Agent: Silverbrook Research Pty Ltd

20070164446 - Integrated circuit having second substrate to facilitate core power and ground distribution: An integrated circuit comprises a first substrate, an integrated circuit die attached to the first substrate, and a second substrate overlying at least a portion of the integrated circuit die. The second substrate comprises at least one conductor that is wire bonded to a conductor of the first substrate and... Agent: Ryan, Mason & Lewis, LLP

20070164447 - Semiconductor package and fabricating method thereof: A semiconductor package including a die, a substrate and bumps is provided. The die has die pads arranged on an active surface thereof and a first passivation layer. The first passivation layer is disposed on the active surface and has first openings for exposing the die pads, respectively. The substrate... Agent: J.c. Patents, Inc.

20070164452 - Method of wire bonding over active area of a semiconductor circuit: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over... Agent: Megica Corporation

20070164453 - Method of wire bonding over active area of a semiconductor circuit: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over... Agent: Megica Corporation

20070164451 - Power configuration method for structured asics: A method for electrically coupling a bond pad of an integrated circuit such as a field programmable device, an application-specific integrated circuit, or a rapid chip with an input/output device is disclosed. The bond pad is provided with a plurality of metal layers configurable for making a connection with the... Agent: Lsi Logic Corporation

20070164454 - Dispensed electrical interconnections: An electronic device includes a substrate, an electrical element on the substrate, a nonconductive adhesive material on the substrate, and a conductive adhesive material on the electrical element and extending onto the nonconductive adhesive material. Methods of forming a packaged LED include providing a substrate having an electrical element thereon,... Agent: Myers Bigel Sibley & Sajovec

20070164455 - Electronic device with bending wiring pattern: An object of the invention is to provide a form of bending wiring patterns whose wiring resistances can be as equal as possible based on a simple structure and to provide an electronic device based on the form. An electronic device having a substrate (100) on which a plurality of... Agent: Philips Intellectual Property & Standards

20070164456 - Repaired extrider dies and repairing method therefor: A method is provided for repairing a die for molding a structure. A die to be repaired has holes for supplying a material, grooves arranged in a lattice form for communicating with the respective holes and for forming the material into a desired shape, and worn-out portions caused by repeated... Agent: Nixon & Vanderhye, PC

20070164457 - Semiconductor package, substrate with conductive post, stacked type semiconductor device, manufacturing method of semiconductor package and manufacturing method of stacked type semiconductor device: A semiconductor package comprising: a substrate containing a wiring pattern connected to a plurality of external electrodes; one or more semiconductor chips connected to the wiring pattern and mounted on the substrate; a conductive post connected to a predetermined the external electrode and functioning as a relay electrode in a... Agent: Mcdermott Will & Emery LLP

20070164458 - Pattern forming method and its mold: In a mold in which a pattern is formed of a fine concavo-convex shape, two or more of alignment marks for determining a relative positional relation between a substrate and a mold are formed concentrically. Moreover, a damaged mark is identified from the positional information and shape of the respective... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070158632 - Method for fabricating a pillar-shaped phase change memory element: A method of fabricating a sub-feature size pillar structure on an integrated circuit. The process first provides a substrate having formed thereon a phase change layer, an electrode layer and a hard-mask layer. Then there is formed a feature-size hard-mask, by lithographically patterning, etching and stripping a photoresist layer, followed... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070158633 - Method for forming self-aligned thermal isolation cell for a variable resistance memory array: A non-volatile method with a self-aligned RRAM element. The method includes a lower electrode element, generally planar in form, having an inner contact surface. At the top of the device is a upper electrode element, spaced from the lower electrode element. A containment structure extends between the upper electrode element... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070158639 - Substrate-free light emitting diode and fabrication method thereof: A substrate-free light emitting diode (LED) including an epitaxy layer, a conductive supporting layer, and a first contact pad is provided. The epitaxy layer includes a first type doped semiconductor layer, a light emitting layer, and a second type doped semiconductor layer. The light emitting layer is disposed on the... Agent: Jianq Chyun Intellectual Property Office

20070158649 - Dual panel type organic electroluminescent display device: A dual panel type organic electroluminescent display device includes first and second substrates and a plurality of pixel regions and a plurality of power supply terminals at upper and lower sides of the plurality of pixel regions thereon, and further includes a plurality of dummy pixel regions each having substantially... Agent: Brinks Hofer Gilson & Lione

20070158648 - Organic thin film transistor and method of manufacturing the same: An organic TFT that has an improved contact between source and drain electrodes and an organic semiconductor layer, a method of manufacturing the same, and an organic light emitting display device having the organic TFT are disclosed. The organic TFT includes a substrate, a gate electrode disposed on the substrate,... Agent: Knobbe Martens Olson & Bear LLP

20070158650 - Method for manufacturing a semiconductor device: Embodiments relate to a method for manufacturing a semiconductor device. In embodiments, the method may include forming a gate electrode on the semiconductor substrate, forming a pattern having a groove at the edge of the gate electrode and performing an etching process using the pattern as a mask, so that... Agent: Sherr & Nourse, PLLC

20070158654 - Apparatus for fabricating large-surface area polycrystalline silicon sheets for solar cell application: A method and apparatus for forming a semiconductor sheet suitable for use as a solar cell by depositing an array of solidified drops of a feed material on a sheet support. The desired properties of the sheet fabricated with the teaching of this invention are: flatness, low residual stress, minority... Agent: Patterson & Sheridan, LLP

20070158674 - Light emitting device and manufacturing method thereof: A light emitting device is disclosed. The light emitting device includes a light emitting element (15), and a light emitting element container (11) having a concave section (20) for containing the light emitting element (15). The concave section (20) includes a side surface (20A) and a bottom surface (20B) almost... Agent: Ladas & Parry LLP

20070158631 - Phase change current density control structure: A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is between the first and second electrodes. A second layer including a metal-chalcogenide material is also between the first and second electrodes and is... Agent: Dickstein Shapiro LLP

20070158634 - Non-volatile semiconductor memory device allowing shrinking of memory cell: Dummy cells are disposed in alignment with memory cells arranged in rows and columns in a memory array. The memory cell includes a variable resistance element and a select transistor having a collector connected to a substrate region and selecting the variable resistance element in response to a row select... Agent: Burns, Donae, Swecker & Mathis, L.L.P.

20070158635 - Semiconductor memory device and method for fabricating the same: In a fabrication method according to the present invention, a first insulating film and tungsten plugs are formed over a substrate including a logic section and a memory section. An upper portion of one of the tungsten plug located in a memory section is removed, thereby forming a recess. A... Agent: Mcdermott Will & Emery LLP

20070158636 - Detecting and characterizing mask blank defects using angular distribution of scattered light: An embodiment of the present invention is a technique to inspect defects in mask blanks. A first iris diaphragm is located at an illumination source to limit an illumination angle of light emitted from the illumination source. A scattering limit unit is located at exit of a dark field optical... Agent: Blakely Sokoloff Taylor & Zafman

20070158637 - Semiconductor laser device: A semiconductor laser device comprises: a first cladding layer provided on a substrate, the first cladding layer being made of nitride semiconductor of a first conductivity type; an active layer provided on the first cladding layer, the active layer being made of a quantum well structure using nitride semiconductor; and... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070158638 - Dual band photodetector: A dual band photodetector for detecting infrared and ultraviolet optical signals is disclosed. Aspects include homojunction and heterojunction detectors comprised of one or more of GaN, AlGaN, and InGaN. In one aspect ultraviolet/infrared dual-band detector is disclosed that is configured to simultaneously detect UV and IR.... Agent: Needle & Rosenberg, P.C.

20070158640 - Electronic device including a poled superlattice having a net electrical dipole moment: An electronic device may include a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment. Each group of layers of the poled superlattice may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070158642 - Active electronic devices with nanowire composite components: Active, electrical, electronic and optoelectronic components and structures are fabricated to include composites containing electrically conductive nanostructures as part thereof. These nanostructures include nanowires, nanofibres, nanoribbons, nanoplates or nanotubes as single structures or an assembly of multiple structures. They are composed of carbon or other conductive materials.... Agent: Venable LLP

20070158643 - Bottom gate thin film transistors: A transistor is provided comprising: a substrate; a gate electrode; a semiconducting material not located between the substrate and the gate electrode; a source electrode in contact with the semiconducting material; a drain electrode in contact with the semiconducting material; and a dielectric material in contact with the gate electrode... Agent: 3m Innovative Properties Company

20070158647 - Junction structure of organic semiconductor device, organic thin film transistor and fabricating method thereof: A junction structure of an organic semiconductor device including an organic semiconductor layer, a conductive layer and a modifying layer is provided. The modifying layer is formed between the organic semiconductor layer and the conductive layer, wherein the modifying layer includes an inorganic compound or an organic complex compound. An... Agent: Jianq Chyun Intellectual Property Office

20070158646 - Organic semiconductor having polymeric and nonpolymeric constituents: A composition, comprising organic polymer molecules, and organic nonpolymeric molecules, wherein the composition is a semiconducting solid. The composition includes a distribution of crystal domains of the polymer molecules and inter-domain regions between the crystal domains, a concentration of polymer molecules being higher in the crystal domains than in the... Agent: Hitt Gaines, PC Alcatel-lucent

20070158644 - Organic thin-film transistor backplane with multi-layer contact structures and data lines: A backplane circuit includes an array of organic thin-film transistors (OTFTs), each OTFT including a source contact, a drain contact, and an organic semiconductor region extending between the source and drain contacts. The drain contacts in each row are connected to an address line. The source and drain contacts and... Agent: Bever, Hoffman & Harms, LLP

20070158645 - Self-align planerized bottom electrode phase change memory and manufacturing method: A method is described for self-aligning a bottom electrode in a phase change random access memory PCRAM device where a top electrode serves as a mask for self-aligning etching of the bottom electrode. The bottom electrode has a top surface that is planarized by chemical mechanical polishing. The top electrode... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070158641 - Thin-film transistor and method of fabricating same: A thin film transistor of the present invention is a thin film transistor (100) having a semiconductor layer (14), a source region (15) and a drain region (16) provided to be isolated from each other so as to mutually oppose the semiconductor layer. The semiconductor layer has π-conjugated organic semiconductor... Agent: Mcdermott Will & Emery LLP

20070158652 - Display substrate, method of manufacturing the same and display panel having the same: An improved display substrate is provided to reduce surface defects on insulating layers of organic thin film transistors. Related methods of manufacture are also provided. In one example, a display substrate includes a base, a plurality of data lines, a plurality of gate lines, a pixel defined by the data... Agent: Macpherson Kwok Chen & Heid LLP

20070158651 - Making organic thin film transistor array panels: An organic thin film transistor (OTFT) array panel includes a substrate, a data line formed on the substrate, a source electrode connected with the data line, a drain electrode, including a portion facing the source electrode, an insulating layer formed on the source electrode and the drain electrode and having... Agent: Macpherson Kwok Chen & Heid LLP

20070158653 - Silicon single crystal, a silicon wafer, an apparatus for producing the same, and a method for producing the same: The present invention is a silicon single crystal grown by CZ method, wherein Cu precipitates do not exist inside the silicon single crystal, a silicon wafer produced from the silicon single crystal, wherein Cu precipitates do not exist on a surface of and inside the wafer, and an apparatus for... Agent: Oliff & Berridge, PLC

20070158656 - Display device and manufacture thereof: An LCD includes a thin film display device having a plastic insulating substrate in which lifting of the edge of the thin film is avoided which includes a display region and a non-display region; a gate line assembly formed on the plastic insulating substrate with the use of a shadow... Agent: Macpherson Kwok Chen & Heid LLP

20070158655 - Laser repair structure and method for tft-lcd: A laser repair structure and method for TFT panel. A first metal conductor is located in the source-drain layer and having a contact hole to the pixel electrode, and the region of the first metal conductor is within the region of the storage capacitance line. To repair a white defect... Agent: Birch Stewart Kolasch & Birch

20070158657 - Light emitting device, method for manufacturing thereof and electronic appliance: An object of the invention is to provide a method for manufacturing a light emitting device capable of reducing deterioration of elements due to electrostatic charge caused in manufacturing the light emitting device. Another object of the invention is to provide a light emitting device in which defects due to... Agent: Eric Robinson

20070158658 - Methods of fabricating vertical jfet limited silicon carbide metal-oxide semiconductor field effect transistors: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070158660 - Optically active compositions and combinations of same with ingan semiconductors: New combinations of semiconductor devices in conjunction with optically active materials are set forth herein. In particular, light emitting semiconductors fashioned as diodes from indium gallium nitride construction are combined with high-performance optically active Langasite La3Ga5SiO14 crystalline materials. When Langasite is properly doped, it will respond to the light output... Agent: Acol Technologies S.a.

20070158659 - Semiconductor structure comprising active zones: A semiconductor structure with active zones, such as light diodes or photodiodes, including a substrate (SUB) with at least two active zones (AZ1-AZn), each of which emits or absorbs a radiation of differing wavelength. According to the invention, a multi-wavelength diode may be achieved, in which a first (lower) active... Agent: Dennison, Schultz & Macdonald

20070158662 - Two-dimensional photonic crystal led: A two-dimensional photonic crystal LED composed of a p-type semiconductor cladding layer 12, an active layer 11 of light-emitting material, and an n-type semiconductor cladding layer 13 placed between a pair of electrodes, where air holes 16 penetrating through the layers 12, 11 and 13 and arranged periodically in the... Agent: Oliff & Berridge, PLC

20070158661 - Zno nanostructure-based light emitting device: ZnO nanostructure-based LEDs are provided to improve the emission efficiency. The devices include several configurations. Single crystal ZnO or MgxZn1−xO nanotips are grown on the top of a GaN p-n junction. Also, n-type ZnO nanotips are grown on p-GaN film to form an n-type ZnO nanotip/p-GaN heterojunction LED. A ZnO... Agent: Hoffmann & Baron, LLP

20070158663 - Apparatus and method for optical isolation: An optoisolator device is shown having a die attachment device with a planar surface. A first circuit die has first and second planar surfaces and a first side surface. A receiver circuit and a first photodiode are formed on the first planar surface of the first circuit die, where the... Agent: Francissen Patent Law, P.C.

20070158665 - Light emitting diode: A method for fabricating a light emitting diode (LED) is provided. First, a first type doped semiconductor layer, an emitting layer and a second type doped semiconductor layer are sequentially formed on an epitaxy substrate. Then, a gold layer is formed on the second type doped semiconductor layer. Next, a... Agent: Jianq Chyun Intellectual Property Office

20070158664 - Mesa structure photon detection circuit: A MESA-type photonic detection device, including at least one first junction, which itself includes a first receiving layer and sides formed or etched in the receiving layer. These sides at least partially include a layer with a doping opposite the doping of the first receiving layer.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070158666 - Backlight unit: A backlight unit includes a light guide plate having a light-incidence plane and a light-exit plane and at least a light emitting diode (LED) mixing package located in proximity to the light-incidence plane for providing lights to the backlight unit. The LED mixing package includes at least a first color... Agent: North America Intellectual Property Corporation

20070158669 - Chip coated light emitting diode package and manufacturing method thereof: A chip coated LED package and a manufacturing method thereof. The chip coated LED package includes a light emitting chip composed of a chip die-attached on a submount and a resin layer uniformly covering an outer surface of the chip die. The chip coated LED package also includes an electrode... Agent: Mcdermott Will & Emery LLP

20070158668 - Close loop electrophoretic deposition of semiconductor devices: One close loop system and method for electrophoretic deposition (EPD) of phosphor material on light emitting diodes (LEDs). The system comprises a deposition chamber sealed from ambient air. A mixture of phosphor material and solution is provided to the chamber with the mixture also being sealed from ambient air. A... Agent: Koppel, Patrick & Heybl

20070158667 - Light-emitting diode structure with transparent window covering layer of multiple films: A light-emitting diode structure with transparent window covering layer of multiple films discloses at least a first transparent covering layer and a second covering layer, which are covered with the outside of the light-emitting diode chip. The light-emitting diode chip can emit more than two kinds of light waves to... Agent: Rosenberg, Klein & Lee

20070158670 - Semiconductor light-emitting device and method for manufacturing the device: A semiconductor light-emitting device has a pair of leads placed in parallel, a light-emitting element on the upper end of one lead, a bonding wire for electrically connecting the semiconductor light-emitting element of the upper end of another lead, and an envelope formed from a light-transmitting resin for sealing the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070158672 - Flat light source and manufacturing method thereof: A flat light source including a first substrate, ribs, a phosphor layer, a second substrate, electrode patterns and an insulating layer is provided. The ribs are disposed on the first substrate. The phosphor layer is disposed on the surface of the ribs. The second substrate is located above the first... Agent: Jianq Chyun Intellectual Property Office

20070158671 - Led and attachment structure of led: In a can type LED 3 where an anode A, a cathode K and an LED pedestal 31p are provided within a housing 31, and pins a1 and k1 of anode A and cathode K lead out at least to the outside of housing 31 so that a voltage can... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070158675 - Semiconductor light-emitting device and method for manufacturing the device: A semiconductor light-emitting device has a pair of leads placed in parallel, a light-emitting element on the upper end of one lead, a bonding wire for electrically connecting the semiconductor light-emitting element of the upper end of another lead, and an envelope formed from a light-transmitting resin for sealing the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070158673 - Wafer-level chip packaging process and chip package structure: A wafer-level chip packaging process includes the following steps. First, a wafer having a plurality of chip units, an active surface, and a corresponding back surface is provided. Each chip unit has a plurality of pads on the active surface. Next, a plurality of through holes is formed under the... Agent: Jianq Chyun Intellectual Property Office

20070158676 - Solid-state imaging device, production method and drive method thereof, and camera: A method of driving a solid-state imaging device using a 4 phase driving method, a 3 phase driving method or a 6 phase driving method. A single-layer transfer electrode configuration of forming first transfer electrodes and second transfer electrodes by one polysilicon layer is used. Two shunt wirings extending in... Agent: Sonnenschein Nath & Rosenthal LLP

20070158677 - Bipolar junction transistor: Embodiments relate to a bipolar junction transistor and a method for manufacturing the same. An oxide pattern may be formed on a P type semiconductor substrate. A low-density N type collector area may be formed in the semiconductor substrate. First spacers may be formed at sidewalls of the oxide pattern,... Agent: Sherr & Nourse, PLLC

20070158678 - Semiconductor device and method of forming a semiconductor device: A high voltage/power semiconductor device has a relatively lowly doped substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer. A low voltage terminal and a high voltage terminal are each electrically connected to the semiconductor layer. The device has a control terminal. The semiconductor... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070158679 - Semiconductor device with multiple channels and method of fabricating the same: A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer... Agent: Mills & Onello LLP

20070158680 - Semiconductor device having igbt and diode: A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor... Agent: Posz Law Group, PLC

20070158681 - Power integrated circuit device having embedded high-side power switch: In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage... Agent: Sidley Austin LLP

20070158682 - Semiconductor device: A semiconductor device is provided which comprises a connecting lead 4 mounted between a MOS-FET 1 and a regulatory IC 2 on a support plate 3. Connecting lead 4 has a thermally radiative and electrically conductive substrate 6 and electrically insulative and thermal transfer-resistive covering 7. Substrate 6 has one... Agent: Bachman & Lapointe, P.C.

20070158683 - Semiconductor devices including implanted regions and protective layers and methods of forming the same: Methods of forming a semiconductor device include forming a protective layer on a semiconductor layer, implanting ions having a first conductivity type through the protective layer into the semiconductor layer to form an implanted region of the semiconductor layer, and annealing the semiconductor layer and the protective layer to activate... Agent: Myers Bigel Sibley & Sajovec

20070158684 - Compound semiconductor, method of producing the same, and compound semiconductor device: An InGaP buffer layer (3) is formed on a semi-insulating GaAs substrate (1) to a thickness of not less than 5 nm and not greater than 500 nm and an InAlAs layer (4) and an InGaAs channel layer (5) are grown thereon to form a heterostructure. An In segregation effect... Agent: Birch Stewart Kolasch & Birch

20070158685 - Transistor epitaxial wafer and transistor produced by using same: A transistor epitaxial wafer having: a substrate; an n-type collector layer, a p-type base layer and an n-type emitter layer formed on the substrate in this order; and an n-type InGaAs non-alloy layer having an n-type InGaAs nonuniform composition layer formed on the n-type emitter layer and having an nonuniform... Agent: Mcginn Intellectual Property Law Group, PLLC

20070158686 - Igbt cathode design with improved safe operating area capability: In an insulated gate bipolar transistor, an improved safe operating area capability is achieved according to the invention by a two-fold base region comprising a first base region (81), which is disposed in the channel region (7) so that it encompasses the one or more source regions (6), but does... Agent: Buchanan, Ingersoll & Rooney PC

20070158687 - Base substrate, method of separating the base substrate and plasma display panel using the same: A plasma display panel (PDP) may include a first substrate having first discharge electrodes and a first separation border where the first substrate was separated from a first base substrate and a second substrate having second discharge electrodes and a second separation border where the second substrate was separated from... Agent: Lee & Morse, P.C.

20070158689 - D/a conversion circuit and semiconductor device: A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including... Agent: Eric Robinson

20070158688 - Memory device and a method of forming a memory device: A memory device includes a semiconductor substrate having a surface, a plurality of first and second conductive lines, a plurality of memory cells, and a plurality of landing pads. Each of the first conductive lines has a line width wb and two neighboring ones of the first conductive lines having... Agent: Dicke, Billig & Czaja

20070158690 - Programmable resistive ram and manufacturing method: Programmable resistive RAM cells have a resistance that depends on the size of the programmable resistive elements. Manufacturing methods and integrated circuits for programmable resistive elements with uniform resistance are disclosed that have a cross-section of reduced size compared to the cross-section of the interlayer contacts.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070158691 - Semiconductor device having soi structure: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070158693 - Device of active regions and gates and method of forming gate patterns using the same: A semiconductor device having an improved gate process margin includes two active regions spaced apart from each other on a semiconductor substrate and respectively having bent sides with recesses and protrusions corresponding to each other, and two line-shaped gate patterns respectively formed in the longitudinal directions of the active regions.... Agent: Townsend And Townsend And Crew, LLP

20070158694 - Semiconductor device and method of fabricating the same: A semiconductor device comprising a substrate having a well region, at least one well pickup region formed on the substrate to surround the well pickup region, a first drain region formed on the substrate to be positioned on one side of the source region, and a first gate electrode formed... Agent: Mayer, Brown, Rowe & Maw LLP

20070158692 - Semiconductor device: The present invention provides a semiconductor device capable of suppressing current collapse, and also of preventing dielectric breakdown voltage and gain from lowering so as to perform high-voltage operation and realize an ideal high output. On a substrate (101), there are formed a buffer layer (102) made of a first... Agent: Sughrue Mion, PLLC

20070158695 - System with meshed power and signal buses on cell array: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The... Agent: Haynes And Boone, LLP

20070158696 - Optical enhancement of integrated circuit photodetectors: A semiconductor integrated circuit structure and method for fabricating. The semiconductor integrated circuit structure includes a light sensitive device integral with a semiconductor substrate, a cover dielectric layer disposed over the light sensitive device, and a lens-formation dielectric layer disposed over the cover dielectric layer. Light is transmittable through the... Agent: Ratnerprestia

20070158697 - Phase change memory device using carbon nanotube and method for fabricating the same: Provided are a phase change memory device that can operate at low power and improve the scale of integration by reducing a contact area between a phase change material and a bottom electrode, and a method for fabricating the same. The phase change memory comprises a current source electrode, a... Agent: Foley And Lardner LLP Suite 500

20070158698 - Process for manufacturing a phase change selection device with reduced current leakage, and phase change selection device, in particular for phase change memory devices: In a phase change memory including an ovonic threshold switch, conduction around the phase change material layer in the ovonic threshold switch is reduced. In one embodiment, the reduction is achieved by undercutting the conductive layers on either side of the phase change material layer. In another embodiment, an angled... Agent: Seed Intellectual Property Law Group PLLC

20070158699 - Semiconductor device and semiconductor system: A semiconductor device includes a semiconductor substrate, a first and second semiconductor regions formed on the semiconductor substrate insulated and separated from each other, a gate dielectric film formed on the substrate to overlap the first and second semiconductor regions, a floating gate electrode formed on the gate dielectric film... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070158705 - Semiconductor device: A semiconductor device including a semiconductor substrate having at least one pair of a source region and a drain region being formed at a surface layer portion thereof, a gate insulating film being provided on a surface of the semiconductor substrate between the source region and the drain region and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070158704 - Semiconductor device and methods of fabricating the same: A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop... Agent: Harness, Dickey & Pierce, P.L.C

20070158703 - Electronic device and a process for forming the electronic device: An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to... Agent: Larson Newman Abel Polansky & White, LLP

20070158701 - Excessive round-hole shielded gate trench (sgt) mosfet devices and manufacturing processes: This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench... Agent: Bo-in Lin

20070158700 - Field effect transistor and method for producing the same: A field effect transistor comprising: a semiconductor layer projecting from the plane of a base; a gate electrode provided on opposite side surfaces of the semiconductor layer; a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer; and source/drain regions where a first... Agent: Foley And Lardner LLP Suite 500

20070158702 - Transistor including flatband voltage control through interface dipole engineering: A transistor comprising a semiconductor including a source, a drain, and a channel interposed between the source and the drain; a first dielectric layer having a first thickness, the first dielectric layer being positioned on the channel; a second dielectric layer having a second thickness, the second dielectric layer being... Agent: Blakely Sokoloff Taylor & Zafman

20070158707 - Image sensor and fabricating method thereof: An image sensor including a substrate, a plurality of conductive sections, a first type doped layer, an intrinsic layer, and a transparent electrode layer is provided. Wherein, the conductive sections are disposed on the substrate, and the dielectric layer is disposed between two adjacent conductive sections. In addition, the first... Agent: Jianq Chyun Intellectual Property Office

20070158706 - Thin film transistor: A thin film transistor for fabricating on a flexible substrate is provided. The thin film transistor includes a gate, a gate insulating layer, a channel layer, a first conductive pattern, and a second conductive pattern. The gate and the gate insulating layer are disposed on the flexible substrate, and the... Agent: Jianq Chyun Intellectual Property Office

20070158709 - Image sensor with improved surface depletion: An image sensor device having a pixel cell with a pinned photodiode, which utilizes the fixed charge of an high K dielectric layer over the n-type region for the pinning effect without implanting a p-type layer over the n-type region, and methods of forming such a device.... Agent: Dickstein Shapiro LLP

20070158710 - Low-noise image sensor and transistor for image sensor: Provided are a low-noise image sensor capable of improving the efficiency of charge transfer from a photodiode to a diffusion node region and effectively suppressing the generation of dark current, and a transistor for the image sensor. The image sensor includes: a photosensitive pixel having a transfer transistor formed in... Agent: Ladas & Parry LLP

20070158708 - Photodiode array, method for manufacturing same, and radiation detector: A theme is to prevent the generation of noise due to damage in a photodetecting portion in a mounting process in a photodiode array, a method of manufacturing the same, and a radiation detector. In a photodiode array, wherein a plurality of photodiodes (4) are formed in array form on... Agent: Drinker Biddle & Reath (dc)

20070158713 - Cmos imaging device: A CMOS imaging device formed of plural CMOS photosensors arranged in a row and column formation, wherein a first CMOS photosensor and a second CMOS photosensor adjacent with each other in a column direction are formed in a single, continuous device region defined on a semiconductor substrate by a device... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070158711 - Cmos sensors having charge pushing regions: Structures and method for forming the same. The semiconductor structure comprises a photo diode that includes a first semiconductor region and a second semiconductor region. The first and second semiconductor regions are doped with a first and second doping polarities, respectively, and the first and second doping polarities are opposite.... Agent: Schmeiser, Olsen & Watts

20070158712 - Process for fabricating an integrated circuit comprising a photodiode, and corresponding integrated circuit: An integrated circuit includes at least one photodiode associated with a transfer transistor. The photodiode is formed with an upper pn junction. The transfer transistor includes a lateral spacer located on a side facing the photodiode. An upper layer of the upper pn junction includes a lateral surface extension lying... Agent: Jenkens & Gilchrist, PC

20070158715 - Ferroelectric capacitor and method for fabricating the same: In a ferroelectric capacitor comprising: a lower electrode; a ferroelectric film formed on the lower electrode; and an upper electrode formed on the ferroelectric film, variations in composition profile of elements constituting the ferroelectric film are 50% or lower in the thickness direction of the ferroelectric film, and the polarization... Agent: Mcdermott Will & Emery LLP

20070158716 - Conductive memory stack with sidewall: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and... Agent: Unity Semiconductor Corporation

20070158714 - One-mask high-k metal-insulator-metal capacitor integration in copper back-end-of-line processing: A MIM capacitor technique is described wherein bottom plates (electrodes) are composed of gate conductor material, and are formed in the same layer, in the same way, using the same masking and processing steps as transistor gates. The top plates (electrodes) are formed using a simple single-mask, single-damascene process. Electrical... Agent: International Business Machines Corporation Dept. 18g

20070158717 - Integrated circuit comb capacitor: The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance... Agent: International Business Machines Corporation Dept. 18g

20070158721 - Semiconductor device and method for fabricating the same: A trench isolation surrounding the lateral sides of an active region of a P-channel MIS transistor PTr and a trench isolation surrounding the lateral sides of an active region of an N-channel MIS transistor NTr have different film qualities.... Agent: Mcdermott Will & Emery LLP

20070158718 - Dynamic random access memory and method of fabricating the same: A method of fabricating a dynamic random access memory is provided. A trench capacitor is formed in a substrate and an isolation structure is formed on the trench capacitor. A gate structure and a passing gate structure are formed on the substrate. The gate structure is on one side of... Agent: Jianq Chyun Intellectual Property Office

20070158719 - Dynamic random access memory structure and method for preparing the same: A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive... Agent: Oliff & Berridge, PLC

20070158720 - Semiconductor device with cells each having a trench capacitor and a switching transistor thereon: A semiconductor device includes a semiconductor substrate, at least one trench capacitor which is buried into the surface area of the semiconductor substrate, and a first insulation film which is formed on the trench capacitor. The semiconductor device further includes at least one switching transistor provided on the surface of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070158722 - Vertical gain cell: A vertical cell is realized. The cell includes a first vertical metal oxide semiconductor (MOS) transistor having a body between a drain region and a source region and a second vertical MOS transistor including at least a portion of the body of the first vertical MOS transistor.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070158723 - Semiconductor storage device with improved degree of memory cell integration and method of manufacturing thereof: A semiconductor storage device of the present invention has a configuration in which a plurality of memory cells respectively including a transistor connected to a storage element for accumulating data are used, a bit line and a word line for specifying one of a plurality of memory cells are used.... Agent: Sughrue Mion, PLLC

20070158727 - Semiconductor memory devices and methods of forming the same: A semiconductor memory device includes a semiconductor substrate including an insulating layer, a charge storage region of a first conductivity type on the insulating layer, and an insulating film on the insulating layer and surrounding the charge storage region. A body region of the first conductivity type is on an... Agent: Myers Bigel Sibley & Sajovec

20070158725 - Trench memory: A structure and a method for fabrication of the structure use a capacitor trench for a trench capacitor and a resistor trench for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench has a linewidth dimension narrower than the resistor trench. The... Agent: Scully Scott Murphy & Presser, PC

20070158728 - Buried plate structure for vertical dram devices: A buried plate region for a semiconductor memory storage capacitor is self aligned with respect to an upper portion of a deep trench containing the memory storage capacitor.... Agent: Cantor Colburn LLP - IBM Fishkill

20070158726 - Semiconductor device and method of manufacturing the same: Disclosed are a semiconductor device having a vertical trench gate structure to improve the integration degree and a method of manufacturing the same. The semiconductor device includes an epitaxial layer having a second conductive type on a first conductive type substrate having an active region and an isolation region, a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070158724 - Trench memory: A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of... Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP

20070158729 - Thin film transistor array panel and method of manufacture: A TFT array panel for a display has a gate insulating layer with substantially the same dielectric constant as the passivation layer and may be thicker than the passivation layer, while the storage capacitor includes a pixel electrode and a storage electrode overlapping each other along with the passivation layer... Agent: Macpherson Kwok Chen & Heid LLP

20070158731 - Memory devices employing ferroelectric layer as information storage elements and methods of fabricating the same: A memory device includes one or more layers of parallel strings of ferroelectric gate transistors on a substrate, each layer of parallel strings including a plurality of parallel line-shaped active regions and a plurality of word lines extending in parallel transversely across the active regions and disposed on ferroelectric patterns... Agent: Myers Bigel Sibley & Sajovec

20070158732 - Flash memory device having vertical split gate structure and method for manufacturing the same: Disclosed are a flash memory device having a vertical split gate structure and a method for manufacturing the same. The flash memory device includes a first trench formed in an active region of a semiconductor substrate and including a pair of opposite sidewalls, a second trench formed in the middle... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070158730 - Integrated circuit using finfets and having a static random access memory (sram): An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor... Agent: Freescale Semiconductor, Inc. Law Department

20070158735 - Method of fabricating a transistor: A method of forming a transistor reduces leakage current and hot carrier effects, and therefore improves current performance. The method of forming a transistor includes selectively etching the semiconductor substrate to form a substrate protrusion and expose a buried source/drain implant region. A gate insulating layer covers the substrate protrusion... Agent: Sherr & Nourse, PLLC

20070158737 - Semiconductor device with mask read-only memory and method of fabricating the same: A mask read only memory (ROM) device includes a plurality of isolation patterns disposed at predetermined regions of a semiconductor substrate to define a plurality of active regions. The semiconductor substrate includes a mask ROM region where a plurality of on cells and a plurality of off-cells are disposed. The... Agent: F. Chau & Associates, LLC

20070158734 - Electronic device with a multi-gated electrode structure and a process for forming the electronic device: An electronic device including a multi-gate electrode structure overlying the channel region further comprising a first and second gate electrode spaced apart from each other by a layer, and a process for forming the electronic device is disclosed. The multi-gate electrode structure can have a sidewall spacer structure having first... Agent: Larson Newman Abel Polansky & White, LLP

20070158733 - High-speed low-voltage programming and self-convergent high-speed low-voltage erasing schemes for eeprom: The present invention provides a high-speed low-voltage programming scheme and self-convergent high-speed low-voltage erasing schemes for Electrically Erasable Programmable Read-Only Memories (EEPROM). For the N-type Field Effect Transistor (NFET) based NVM programming, an elevated source voltage to the substrate can achieve high efficient Drain-Avalanche-Hot-Electron Injection (DAHEI) into the floating gate... Agent: Birch Stewart Kolasch & Birch

20070158736 - Semiconductor memory device and method of fabricating the same: A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070158738 - Flash memory device and method of manufacturing the same: A flash memory device and a method of manufacturing the same is disclosed. A gate dielectric film formed between a floating gate and a control gate of a flash memory device is formed by laminating an oxide film and a ZrO2 film. Accordingly, the reliability of the flash memory can... Agent: Townsend And Townsend And Crew, LLP

20070158739 - Higher performance cmos on (110) wafers: A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation... Agent: Scully Scott Murphy & Presser, PC

20070158740 - Semiconductor device and manufacturing method of the semiconductor device: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal... Agent: Rossi, Kimms & Mcdowell LLP.

20070158741 - Ldmos device and method of fabrication of ldmos device: A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070158744 - Thin film transistor array panel and manufacturing thereof: A thin film transistor array panel includes a substrate, a plurality of first and second signal lines crossing each other on the substrate, source electrodes connected to the first signal lines, drain electrodes connected to the second signal lines, pixel electrodes connected to the drain electrodes, a first partition formed... Agent: Macpherson Kwok Chen & Heid LLP

20070158742 - Mos transistor and manufacturing method thereof: There are provided a MOS transistor and a manufacturing method thereof. The MOS transistor includes a substrate on which an insulating layer is formed, a gate embedded in the insulating layer, wherein the top surface of the gate is exposed, a gate oxide layer formed on the insulating layer and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070158745 - Semiconductor device and manufacturing method thereof: When a metal layer 11 is provided over a substrate, an oxide layer 12 is provided in contact with the metal layer 11, a layer to be peeled 13 is formed, and the metal layer 11 is irradiated with a laser beam to perform oxidization and form a metal oxide... Agent: Eric Robinson

20070158743 - Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners: The present invention provides a semiconducting device structure including a thin SOI region, wherein the SOI device is formed with an optional single thin diffusion, i.e., offset, spacer and a single diffusion implant. The device silicon thickness is thin enough to permit the diffusion implants to abut the buried insulator... Agent: Scully Scott Murphy & Presser, PC

20070158746 - Semiconductor device having soi substrate: A semiconductor device includes first semiconductor layers with a first conductivity, second to fifth semiconductor layers with a second conductivity, gate electrodes, and a first wiring layer. The second semiconductor layers are each disposed between adjacent ones of the first semiconductor layers. The third semiconductor layer is in contact with... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070158747 - Soi cmos circuits with substrate bias: The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS... Agent: Scully Scott Murphy & Presser, PC

20070158748 - Resistor structure for esd protection circuits: A semiconductor device includes an ESD protection device on a substrate, and a resistor having a gate structure overlying a resistor well separating a first doped region coupled to the ESD protection device and a second doped region coupled to a supply voltage for passing an ESD current from the... Agent: L.howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070158749 - Low resistance peripheral contacts while maintaining dram array integrity: An apparatus having low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device, is disclosed. In a buried bit line connection process flow, the present invention utilizes chemical vapor deposition of titanium to form titanium silicide... Agent: Dinsmore & Shohl LLP One Dayton Centre

20070158750 - Integrated circuit arrangement with shockley diode or thyristor and method for production and use of a thyristor: An integrated circuit arrangement includes a Shockley diode or a thyristor. An inner region of the diode or of the thyristor is completely or partially shielded during the implantation of a p-type well. This gives rise to a Shockley diode or a thyristor having improved electrical properties, in particular with... Agent: Brinks Hofer Gilson & Lione Infineon

20070158751 - Semiconductor device and fabrication method thereof: In order to diversify a current control method of a semiconductor device, improve performance (including a current drive performance) of the semiconductor device, and reduce a size of the semiconductor device, a second gate may be formed inside a substrate that forms a channel upon applying a bias voltage thereto.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070158753 - Semiconductor device structure having low and high performance devices of same conductive type on same substrate: A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region... Agent: International Business Machines Corporation Dept. 18g

20070158752 - Sram array and analog fet with dual-strain layers: Disclosed is a semiconductor structure and associated method of performing the structure with good performance and stability trade-offs for digital circuits and SRAM cells and/or analog FETs on the same chip. Specifically, a dual-strain layer is formed over digital circuits and the other devices on a chip. The dual-strain layer... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070158754 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. In the epitaxial layers, P type buried diffusion layers and P type diffusion layers are formed, which form isolation regions. In this event, the P type buried diffusion layers... Agent: Morrison & Foerster LLP

20070158755 - Methods and semiconductor structures for latch-up suppression using a buried conductive region: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070158756 - Production method for a finfet transistor arrangement, and corresponding finfet transistor arrangement: The present invention provides a production method for a FinFET transistor arrangement, and a corresponding FinFET transistor arrangement. The method comprises the following steps: provision of a substrate (106, 108); formation of an active region (1) on the substrate, said active region having a source region (114), a drain region... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070158757 - Structure of a field effect transistor having metallic silicide and manufacturing method thereof: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the... Agent: Volentine Francos, & Whitt PLLC

20070158758 - Static random access memory and method for manufacturing the same: Disclosed is a static random access memory (SRAM), which includes first and second access transistors composed of metal oxide semiconductor (MOS) transistors, first and second drive transistors composed of MOS transistors, and first and second p-channel thin film transistors (TFTs) used as pull-up devices. The SRAM includes a ground potential... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070158759 - Silicon spring electrode and anisotropic conductive sheet: In order to provide an anisotropic conductive sheet which can be applied to more finely and more narrowly pitched electrodes and also to provide spring electrodes applied for the anisotropic conductive sheet, the spring electrodes manufactured as follows. A part having a bending leaf spring shape is formed out of... Agent: James C Wray

20070158760 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having... Agent: Mcdermott Will & Emery LLP

20070158761 - Gate structure of a semiconductor device: Embodiments relate to a gate structure of a semiconductor device and a method of manufacturing the gate structure. An oxide layer may be formed on a silicon substrate before a gate insulating layer is formed. The oxide layer may be etched to form an opening exposing a channel area of... Agent: Sherr & Nourse, PLLC

20070158764 - Electronic device including a fin-type transistor structure and a process for forming the electronic device: An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin... Agent: Larson Newman Abel Polansky & White, LLP

20070158762 - Low-capacitance contact for long gate-length devices with small contacted pitch: Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070158763 - Semiconductor transistors with expanded top portions of gates: A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed... Agent: Schmeiser, Olsen & Watts

20070158765 - Gallium lanthanide oxide films: Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070158766 - Nanosensors: Electrical devices comprised of nanowires are described, along with methods of their manufacture and use. The nanowires can be nanotubes and nanowires. The surface of the nanowires may be selectively functionalized. Nanodetector devices are described.... Agent: Wolf Greenfield & Sacks, P.C.

20070158768 - Electrical contacts formed of carbon nanotubes: An apparatus and method for a micromachined mechanical switch device having first and second cooperating electrical switch contacts formed by respective first and second patterns of robust carbon nanotube thin film structures for forming intermittent electrical contact between the first and second conductors in response to the applied force urging... Agent: Honeywell International Inc.

20070158769 - Integrated cmos-mems technology for wired implantable sensors: Disclosed are wired implantable integrated CMOS-MEMS sensors and fabrication methods. A first ceramic substrate comprising a biocompatible material such as fused silica is provided. A polysilicon layer is formed on the first substrate. An integrated circuit is fabricated adjacent to the surface of the first substrate. A passivation layer is... Agent: Law Offices Of Kenneth W. Float

20070158767 - Out-of-plane electrostatic actuator: A micro-electromechanical device includes a semiconductor substrate and an arm coupled to the substrate. The arm is pivotable out-of-plane relative to the substrate and at least a portion of the arm is deformable. The deformable portion of the arm deforms as the arm pivots relative to the substrate.... Agent: Lee & Hayes PLLC

20070158771 - Stratified photodiode for high resolution cmos image sensor implemented with sti technology: A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions... Agent: Morgan Lewis & Bockius LLP

20070158770 - Time-of-light flight type distance sensor: A lower cost range-finding image sensor based upon measurement of reflection time of light with reduced fabrication processes compared to standard CMOS manufacturing procedures. An oxide film is formed on a silicon substrate, and two photo-gate electrodes for charge-transfer are provided on the oxide film. Floating diffusion layers for taking... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070158772 - Method and apparatus providing a uniform color filter in a recessed region of an imager: A method and apparatus for improving the planarity of a recessed color filter array when the recessed region or trench depth exceeds the thickness of the color filter film. The method includes the steps of coating the entire wafer with an additional coating material after applying the CFA, then planarizing... Agent: Dickstein Shapiro LLP

20070158773 - Compact camera module: A compact camera module mainly includes an image sensor chip, a module case and a lens module. The image sensor chip has an active surface, a back surface and a plurality of side surfaces, wherein a sensor region is formed in the active surface. A plurality of lateral contact fingers... Agent: North America Intellectual Property Corporation

20070158774 - Solid image-pickup device and method for manufacturing the solid image pickup device: It is an object of the invention to provide an improved solid image-pickup device which is compact in size and low in production cost. The solid image-pickup device is so formed that its semiconductor substrate has on its surface an image-pickup area having a plurality of light sensors arranged thereon.... Agent: Robert J. Depke Lewis T. Steadman

20070158775 - Methods for implementation of a switching function in a microscale device and for fabrication of a microscale switch: Methods for Implementation of a Switching Function in a Microscale Device and for Fabrication of a Microscale Switch. According to one embodiment, a method is provided for implementing a switching function in a microscale device. The method can include providing a stationary electrode and a stationary contact formed on a... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070158776 - Pn-junction temperature sensing apparatus: A PN-junction temperature sensing apparatus for applying input signals to a semiconductor device and measuring temperature-dependent output signals has an odd number of current sources (1, 2, n) switches (5, 6, 7) with selectable outputs to connect the current sources (5, 6, 7) with a thermal sensor (12) or a... Agent: Baker Botts, L.L.P.

20070158777 - High voltage field effect device and method: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90)... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070158778 - Semiconductor device and module using the same: A semiconductor device according to this invention includes: two level shift switches (28A and 28B) each having first and second electrodes, a control electrode, a signal output electrode, and a first semiconductor region forming a transistor device section (28a,28b) which intervenes between the first electrode and the signal output electrode... Agent: Mcdermott Will & Emery LLP

20070158780 - Semiconductor integrated circuit device and method of fabricating the same: A semiconductor integrated circuit device with higher integration density and a method of fabricating the same are provided. The semiconductor integrated circuit device may include trench isolation regions in a semiconductor substrate that define an active region and a gate pattern that is used for a higher voltage and formed... Agent: Harness, Dickey & Pierce, P.L.C

20070158779 - Methods and semiconductor structures for latch-up suppression using a buried damage layer: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a damage layer formed in a substrate, a first doped well formed in the substrate, and a second doped well formed in the substrate proximate to the first doped well. The damage layer extends within the... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070158781 - Electrical fuses comprising thin film transistors (tfts), and methods for programming same: The present invention relates to electrical fuses that each comprises at least one thin film transistor. In one embodiment, the electrical fuse of the present invention comprises a hydrogenated thin film transistor with an adjacent heating element. Programming of such an electrical fuse can be effectuated by heating the hydrogenated... Agent: Scully Scott Murphy & Presser, PC

20070158782 - Inductor device for multiband radio frequency operation: The inductance of a monolithic planar inductor is distributed into smaller inductor portions. The smaller inductor portions are provided in a cascode configuration in a manner that causes inductor to function as a differential inductor device. The node between the immediate inductor portions is a common-mode point of the inductor... Agent: Squire, Sanders & Dempsey L.L.P.

20070158783 - Interdigitated capacitive structure for an integrated circuit: System and method for an improved interdigitated capacitive structure for an integrated circuit. A preferred embodiment comprises a first layer of a sequence of substantially parallel interdigitated strips, each strip of either a first polarity or a second polarity, the sequence alternating between a strip of the first polarity and... Agent: Slater & Matsil, L.L.P.

20070158784 - Semiconductor device and manufacturing method thereof: In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20070158785 - Gallium nitride crystals and wafers and method of making: A crystal comprising gallium nitride is disclosed. The crystal has at least one grain having at least one dimension greater than 2.75 mm, a dislocation density less than about 104 cm−2, and is substantially free of tilt boundaries.... Agent: General Electric Company Global Research

20070158786 - Compound semiconductor device and method of producing the same: A semiconductor device comprises an Si substrate (10) and a compound layer (11) of Si1-xGex disposed on the substrate (10). X is varied from 0 to 0.2 away from the substrate (10) towards the upper surface of the compound layer (11), with the rate of change of X increasing through... Agent: Tumey, L.L.P.

20070158787 - Heterogeneously integrated microsystem-on-a-chip: A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated,... Agent: Sandia Corporation

20070158788 - Die seal structure for reducing stress induced during die saw process: A seal ring structure between an integrated circuit region and a scribe line is provided. In one embodiment, the seal ring structure comprises a substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070158789 - Material comprising predetermined number of atomic layers and method for manufacturing predetermined number of atomic layers: The present invention relates to a composition of matter based on lamellar materials, and method of deriving one or more predetermined number of layers of material from a bulk lamellar material. In one aspect of the present invention, a material comprising a predetermined number of one or more layers is... Agent: Reveo, Inc.

20070158790 - Semiconductor devices with graded dopant regions: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation... Agent: Winstead Sechrest & Minick P.C.

20070158791 - Superconducting junction element and superconducting junction circuit: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier... Agent: Ladas & Parry

20070158793 - Carrier structure for semiconductor package: An exemplary carrier structure (20) for carrying workpieces includes a body (23) and an adhesive tape (27). The body defines a receiving hole (21) therethrough for receiving one or more of the workpieces therein. The adhesive tape is attached to one side of the body and covers the receiving hole... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070158795 - High density memory card system and method (254-hd\c1): The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to... Agent: Fish & Richardson P.C.

20070158792 - Overhang integrated circuit package system: An integrated circuit package system is provided attaching a film to a die paddle, applying an adhesive to the film, and attaching an integrated circuit die over the adhesive and the film to the die paddle.... Agent: Ishimaru & Zahrt LLP

20070158794 - Package structure of thin lead-frame: An assembly structure of thin lead-frame is provided. A lead-frame includes the plurality of leads and a layer located on the extension of the inner lead to bear a die. Then the molding compound is covered the die, the layer, and the plurality of leads but exposed the outer lead... Agent: Birch Stewart Kolasch & Birch

20070158796 - Semiconductor package: A semiconductor package that includes a semiconductor device that is integrated with a silicon substrate.... Agent: Ostrolenk Faber Gerb & Soffen

20070158797 - Circuit board and electronic assembly: A circuit board suitable for being electrically connected to a chip package is provided. The chip package has a chip pad and a plurality of inner leads. The circuit board includes at least one patterned conductive layer and at least one insulating layer. The patterned conductive layer has at least... Agent: J.c. Patents, Inc.

20070158799 - Interconnected ic packages with vertical smt pads: An electronic component is disclosed including a plurality of semiconductor packages soldered together in a side-by-side configuration. The packages are batch processed on a substrate panel. The panel includes a plurality of through-holes drilled through the panel and subsequently filled with metal such as copper or gold. These filled through-holes... Agent: Vierra Magen/sandisk Corporation

20070158800 - Managed memory component: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded... Agent: Fish & Richardson P.C.

20070158801 - Methods for packaging and encapsulating semiconductor device assemblies that include tape substrates: Packaging and encapsulation methods include use of a tape substrate with a mold gate that includes an aperture and a support element that extends over at least a portion of the aperture. The tape substrate may be part of a strip. A semiconductor device is secured and electrically connected to... Agent: Trask Britt, P.C./ Micron Technology

20070158798 - Wafer with optical control modules in ic fields: In a wafer (1) with a number of exposure fields (2), each of which exposure fields comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of saw paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1,... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070158803 - Memory packaging structure of mini sd card: A memory packaging structure of mini SD card, the main implementation technology thereof comprises: to perform the pin adjustment to the: memory originally employing TSOP (Thin Small Out-Line Package) packaging structure, eliminating the gap of 0.1 mm to 0.2 mm between the memory and the circuit board, thus completely attached... Agent: Rabin & Berdo, PC

20070158802 - High density memory card system and method: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to... Agent: Fish & Richardson P.C.

20070158804 - Semiconductor device, manufacturing method of semiconductor device, and rfid tag: The present invention provides a semiconductor device which is formed at low cost and has a great versatility, a manufacturing method thereof, and further a semiconductor device with an improved yield, and a manufacturing method thereof. A structure, which has a base including a plurality of depressions having different shapes... Agent: Cook, Alex, Mcfarron, Manzo Cummings & Mehler, Ltd.

20070158811 - Low profile managed memory component: A system and method for combining at least two semiconductor die using multi-layer flex circuitry is provided. A first semiconductor die is attached and preferably electrically connected to a first layer of the flex circuitry while a second semiconductor die is set, at least in part, into a window that... Agent: Fish & Richardson P.C.

20070158812 - Method of testing wires and apparatus for doing the same: In a substrate including a plurality of first wires to be tested, and a plurality of second wires each defining a capacity with each of the first wires, a method of testing whether said first wires are defective or not, includes (a) applying a voltage to the first wires, and... Agent: Young & Thompson

20070158805 - Bga-scale stacks comprised of layers containing integrated circuit die and a method for making the same: A three dimensional electronic module is disclosed. Conventional TSOP packages are modified to expose internal lead frame interconnects, thinned and stacked on a reroute substrate. The reroute substrate comprises conductive circuitry for the input and output of electrical signals from one or more TSOPs in the stack to a ball... Agent: W. Eric Boyd, Esq. Irvine Sensors Corp.

20070158807 - Edge interconnects for die stacking: Electronic devices and methods for fabricating electronic devices are described. One embodiment includes an electronic device having a first die, the first die having a top surface, a bottom surface, and a plurality of side surfaces. The first die also includes a plurality of metal pads on the top surface... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20070158814 - Electronic circuit package: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070158806 - Integrated circuit package system including honeycomb molding: An integrated circuit package system including a substrate with a top surface and a bottom surface. Configuring the top surface to include electrical contacts formed between a perimeter of the substrate and a semiconductor die. Aligning over the top surface of the substrate a mold plate with a honeycomb meshwork... Agent: Ishimaru & Zahrt LLP

20070158813 - Integrated circuit package-in-package system: A package-in-package system is provided including forming a top substrate having a first integrated circuit electrically connected thereto and mounting a second integrated circuit over the first integrated circuit. The system includes forming first electrical connectors on the second integrated circuit and encapsulating the second integrated circuit in a first... Agent: Ishimaru & Zahrt LLP

20070158809 - Multi-chip package system: A chip package system is provided including providing a chip having interconnects provided thereon; forming a molding compound on the chip and encapsulating the interconnects; and forming a recess in the molding compound above the interconnects to expose the interconnects.... Agent: Ishimaru & Zahrt LLP

20070158808 - Multiple chip module and package stacking method for storage devices: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. Combination of these modules and dies in a substrate creates a package with specific function or a range of memory... Agent: Uriarte Law

20070158810 - Stacked integrated circuit package-in-package system: A stacked integrated circuit package-in-package system is provided forming a first device having a first integrated circuit package comprises forming a first substrate with a first integrated circuit thereon, electrically connecting first electrical interconnects between the first integrated circuit and a top side of the first substrate, encapsulating a first... Agent: Ishimaru & Zahrt LLP

20070158816 - Contact spring application to semiconductor devices: A contact spring applicator is provided which includes an applicator substrate, a removable encapsulating layer and a plurality of contact springs embedded in the removable encapsulating layer. The contact springs are positioned such that a bond pad on each contact spring is adjacent to an upper surface of the removable... Agent: Marger Johnson & Mccollom/parc

20070158815 - Multi-chip ball grid array package and method of manufacture: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure... Agent: Sughrue Mion, PLLC

20070158818 - Integrated capacitors in package-level structures, processes of making same, and systems containing same: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070158817 - Semiconductor device: A semiconductor device includes, in first and second power source systems, electrostatic discharge (ESD) protective bonding pads connected by bonding wires to first and second power supply terminals and first and second ground terminals, first and second signal ESD protective element sections that are each connected to first and second... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20070158819 - Semiconductor device and a method of manufacturing the same: A semiconductor device and method having high output and having reduced external resistance is reduced and improved radiating performance. A MOSFET (70) has a connecting portion for electrically connecting a surface electrode of a semiconductor pellet and a plurality of inner leads, a resin encapsulant (29), a plurality of outer... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070158821 - Managed memory component: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry. The leaded packaged IC is disposed along one side of a flex circuit. The semiconductor die is disposed along the flex circuitry and preferably is between at least... Agent: Fish & Richardson P.C.

20070158820 - Integrated circuit package system with pedestal structure: An integrated circuit package system includes providing a substrate having a bond finger thereon and forming a pedestal on a portion of the bond finger. A first die is mounted on the substrate and adjacent to the bond finger. A portion of the first die, a portion of the bond... Agent: Ishimaru & Zahrt LLP

20070158822 - Dynamic quantity sensor: A dynamic quantity sensor includes a sensor chip (10) having a movable portion (13) at one surface side thereof and a silicon layer (14) at another surface side thereof. The movable portion (13) is displaced under application of a dynamic quantity. The silicon layer (14) is separated from the movable... Agent: Posz Law Group, PLC

20070158823 - Chip package thermal interface materials with dielectric obstructions for body-biasing, methods of using same, and systems containing same: A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070158824 - Hybrid composite material substrate: This invention relates to a hybrid composite material substrate. The substrate includes a conductive layer, an insulating layer, and a dispersion material extending from the conductive layer into the insulating layer.... Agent: Bacon & Thomas, PLLC

20070158827 - Electronic device comprising at least one printed circuit board and comprising a plurality of semiconductor components of identical type, and method: An electronic device is provided, in which semiconductor components are structurally identical among one another and have two groups of contact connections arranged on opposite main areas on a printed circuit board. Components are arranged in a manner laterally offset in a direction parallel to the printed circuit board area... Agent: Slater & Matsil LLP

20070158828 - Package structure and fabricating method thereof: A package structure and a fabricating method thereof are provided. The package structure includes a soft board and an optical chip. The soft board has a surface with a bump disposed thereon. The optical chip includes a main body and a conductive pillar. The main body has an active surface... Agent: Birch Stewart Kolasch & Birch

20070158825 - Recyclying faulty multi-die packages: The present invention teaches the recycling of a faulty multi-die memory package by isolating the functional part of the package and using it as a smaller memory package.... Agent: Dr. Mark Friedman Ltd. C/o Bill Polkinghorn

20070158826 - Semiconductor device: A semiconductor device includes a substrate, a semiconductor chip having a diaphragm, which vibrates in response to sound pressure variations, and a circuit chip that is electrically connected to the semiconductor chip so as to control the semiconductor chip, wherein the semiconductor chip is fixed to the surface of the... Agent: Dickstein Shapiro LLP

20070158830 - Circuit module: A circuit module is disclosed that includes a bare chip and a surface mounting component mounted on a surface of a substrate, and a sealing resin for sealing the bare chip and the surface mounting component. The sealing resin is molded entirely on the surface of the substrate by transfer... Agent: Ladas & Parry LLP

20070158829 - Connecting module having passive components: The present invention provides a connecting module having at least one passive component including a substrate, a connecting wire layout, at least one passive component and a chip-setting area, wherein the connecting wire layout is formed on the substrate, the passive components are formed on the connecting wire layout to... Agent: John Chen

20070158831 - Methods of manufacturing a three-dimensional semiconductor device and semiconductor devices fabricated thereby: A method of fabricating a three-dimensional semiconductor device is provided along with a three-dimensional semiconductor device fabricated thereby. The method includes forming a heat conductive plug to channel heat away from devices on a substrate, while high temperature processes are performed on a stacked semiconductor layer. The ability to use... Agent: Marger Johnson & Mccollom, P.C.

20070158838 - Circuit board, method for manufacturing the same, semiconductor device, and method for manufacturing the same: A circuit board for flip-chip packaging is provided which can achieve the connection reliability of a semiconductor device and the circuit board. The circuit board for flip-chip packaging includes, on a surface of a substrate (6), wiring patterns (1), connection pads (2) for flip-chip packaging, and a solder resist (3)... Agent: Steptoe & Johnson LLP

20070158836 - Pad layout: A pad layout suitable for being applied on a metal interconnection structure of an integrated circuit chip is provided. The pad layout includes a first signal pad, a second signal pad, a first non-signal pad, a second non-signal pad, a first trace, a second trace, a first guard ring and... Agent: J C Patents, Inc.

20070158834 - Electrical connections made with dissimilar metals: Electrical connections between different materials. An electrical connection system includes electrical components and an electrical connection between the electrical components. The electrical connection includes a functionally graded material. A method of making an electrical connection between different materials includes the steps of: providing an electrical component which includes a material;... Agent: SmithIPServices, P.C.

20070158832 - Electronic device and method of manufacturing the same: An electronic device wherein an electronic element is electrically connected to a substrate through an interposer and a method of manufacturing the same are disclosed. The electronic device comprises an electronic element and an interposer including an interposer base to which the electronic element is joined and plural post electrodes... Agent: Ladas & Parry LLP

20070158833 - Integrated circuit package system including stacked die: An integrated circuit package system is provided including providing a wafer with bond pads formed on the wafer. A solder bump is deposited on one or more bond pads. The bond pads and the solder bump are embedded within a mold compound formed on the wafer. A groove is formed... Agent: Ishimaru & Zahrt LLP

20070158835 - Method for designing interconnect for a new processing technology: A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070158837 - Semiconductor device: A semiconductor device 1 is a semiconductor device of the BGA type, and includes a semiconductor chip 10, a resin layer 20, an insulating layer 30, and an external electrode pad 40. The resin layer 20 is constituted by a sealing resin 22 and an underfill resin 24, and covers... Agent: Mcginn Intellectual Property Law Group, PLLC

20070158839 - Thermally balanced via: A chip has a wafer portion of a first coefficient of thermal expansion, the wafer portion including at least one via defined by a peripheral sidewall, an insulating region having second average coefficient of thermal expansion, located within the via and covering at least a portion of the peripheral sidewall... Agent: Morgan & Finnegan, L.L.P.

20070158842 - Integrated circuit package having metallic members intruding into solder balls: An integrated circuit package having metallic members intruding into solder balls. The integrated circuit package includes an integrated circuit, an encapsulant, a plurality of solder balls and a plurality of metallic members. A plurality of bonding pads is disposed on an integrated circuit. The encapsulant is made of an insulation... Agent: Pro-techtor International Services

20070158840 - Electronic device and method for bonding an electronic device: An electronic device (1) has a base plate (2) and an electronics housing (3) connected thereto, with a bond contact bearer (5). The latter rests on the base plate (2) via a supporting body (6) in such a manner that the supporting body (6) exerts a pretension force onto the... Agent: Fasse Patent Attorneys, P.A.

20070158841 - Structure of ball grid array package: A structure of Ball Grid Array package (BGA) is provided. The plurality of bumps are attached on a substrate when processed the surface mount technology (SMT) may get stronger support, avoid the assembly structure disintegration when bearing an external force. When user uses a semi-conductor module, the assembly structure will... Agent: Birch Stewart Kolasch & Birch

20070158843 - Semiconductor package having improved solder joint reliability and method of fabricating the same: A semiconductor package with improved solder joint reliability, and a method of fabricating the same are provided. The semiconductor package comprises a printed circuit board (PCB) having a plurality of interconnection layers formed on its surface, and having a plurality of through holes connected to the interconnection layers. An adhesive... Agent: Marger Johnson & Mccollom, P.C.

20070158844 - Copper metalized ohmic contact electrode of compound device: The present invention provides an ohmic contact for a copper metallization whose heat diffusion is improved and cost is reduced. Therein, the ohmic contact is formed through a depositing and an annealing of three metal layers of Pd, Ge and Cu; and, the contact resistance of the ohmic contact is... Agent: Troxell Law Office PLLC

20070158845 - Metal wiring of semiconductor device and method of fabricating the same: A metal wiring forming method in a semiconductor device can include forming an interlayer insulating film on a lower metal wiring, the first interlayer insulating film having a non-planar upper surface; forming a stop layer on the interlayer insulating film and over the lower metal wiring; forming an interlayer insulating... Agent: Marger Johnson & Mccollom, P.C.

20070158847 - Circuit board device with fine conductive structure: A circuit board device with a fine conductive structure is proposed. A circuit board having at least a circuit layer is provided and the circuit layer has at least one electrically conductive pad. At least one first dielectric layer is formed on surfaces of the circuit board and the circuit... Agent: Ishimaru & Zahrt LLP

20070158848 - Electronic component: An electronic component includes a substrate, and a capacitor unit on the substrate. The capacitor unit has a laminate structure including a first electrode layer provided on the substrate, a second electrode layer opposed to the first electrode layer, and a dielectric layer disposed between the first and the second... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070158846 - Method and system for innovative substrate/package design for a high performance integrated circuit chipset: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070158849 - Semiconductor device, method of fabricating the same, and pattern generating method: A semiconductor device according to an embodiment of the present invention has: a semiconductor substrate; an interlayer insulating film formed above the semiconductor substrate; a protective film formed on the interlayer insulating film, the protective film having a higher density than that of the interlayer insulating film; at least one... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070158850 - Method for manufacturing mold type semiconductor device: A mold type semiconductor device includes a semiconductor chip including a semiconductor part; a metallic layer; a solder layer; and a metallic member connecting to the semiconductor chip through the metallic layer and the solder layer. The solder layer is made of solder having yield stress smaller than that of... Agent: Posz Law Group, PLC

20070158852 - Circuit board with conductive structure and method for fabricating the same: A method for fabricating a circuit board with a conductive structure and the same are proposed. A buffer metal layer is formed on an electrically connecting pad of a circuit layer of a circuit board in advance. A conductive structure is then formed on the buffer metal layer to form... Agent: Fulbright And Jaworski LLP

20070158853 - Device with novel conductive via structure: The present invention is generally directed to various methods of forming conductive through-wafer vias. In one illustrative embodiment, the method comprises providing a layer of semiconducting material, forming a layer of metal on a first side of the layer of semiconducting material, forming an opening in the layer of semiconducting... Agent: Williams, Morgan & Amerson

20070158851 - Method to improve time dependent dielectric breakdown: In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the... Agent: International Business Machines Corporation Dept. 18g

20070158855 - Semiconductor-element mounting substrate, semiconductor device, and electronic equipment: A semiconductor-element mounting substrate is a substrate for mounting a semiconductor element, and includes a substrate body. The substrate body has a mounting surface, and the center portion of the mounting surface is provided with a die pattern. Through conductors are provided in a portion of the substrate body located... Agent: Mcdermott Will & Emery LLP

20070158856 - Gap control between interposer and substrate in electronic assemblies: Electronic assemblies and methods for forming assemblies are described. One embodiment includes a method of forming an electronic assembly, including forming a plurality of first solder bumps on one of a substrate and an interposer. The substrate and interposer are positioned so that the first solder bumps are located between... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20070158854 - Laser ablation and imprinting hybrid processing for fabrication of high density interconnect flip chip substrates: In some embodiments, laser ablation and imprinting hybrid processing for fabrication of high density interconnect flip chip substrates are presented. In this regard, a substrate in introduced having a dielectric layer wherein material has been removed from a surface and the cavity has been plated with conductive material resulting in... Agent: Intel Corporation C/o Intellevate, LLC

20070158857 - Semiconductor device having a plurality of semiconductor constructs: A semiconductor device includes a plurality of semiconductor constructs, each of the semiconductor constructs including a semiconductor substrate and external connection electrodes provided on an upper surface of the semiconductor substrate. The semiconductor substrates of the semiconductor constructs are different in a planar-size. The plurality of semiconductor constructs are stacked... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070158858 - Inter-stacking module system: An inter-stacking module system is provided by mounting an integrated circuit on a first substrate, the first substrate having a first bond pad, mounting an inter-stacking module substrate over the integrated circuit, forming an inter-stacking module bonding pad on the inter-stacking module substrate, and connecting bond wires between the inter-stacking... Agent: Ishimaru & Zahrt LLP

20070158859 - Power semiconductor module: A power semiconductor module has a ceramic substrate (9) which has on at least one side a patterned metallization (50) with a fineness of pattern of smaller than or equal to 800 μm, a first semiconductor chip (10) which has a power semiconductor component and which is arranged on the... Agent: Baker Botts, L.L.P.

20070158860 - Semiconductor component and apparatus for production of a semiconductor component: A semiconductor component for radio-frequency applications has at least one substrate and one chip, and with contact pads is disclosed. In one embodiment, bonding wires connect the contact pads on the chip to the contact connecting pads. Signals are passed via these contact pads such that signals at high frequencies... Agent: Dicke, Billig & Czaja

20070158861 - Method for fabricating semiconductor package with build-up layers formed on chip: A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose... Agent: Edwards Angell Palmer & Dodge LLP

20070158862 - Vacuum jacketed electrode for phase change memory element: A memory device having a vacuum jacket around the first electrode element for improved thermal isolation. The memory unit includes a first electrode element; a phase change memory element in contact with the first electrode element; a dielectric fill layer surrounding the phase change memory element and the first electrode... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070158863 - Liquid crystal cells with uniform cell gap and methods of manufacture: A laminate structure and method of manufacture, such as a processed silicon wafer with an overlying layer or cover, includes a first layer or substrate which has a generally-planar region and a peripheral contoured region with falloff from a planar region of the first layer, and a second layer which... Agent: Roetzel & Andress

20070152205 - Semiconductor memory device, phase change memory device, and method of fabricating the same: A phase change memory (PCM) device includes a substrate, bottom electrodes disposed in the substrate, a first dielectric layer disposed on the substrate, second dielectric layers, third dielectric layers, cup-shaped thermal electrodes, top electrodes, and PC material spacers. In the PCM device, each cup-shaped thermal electrode contacts with each bottom... Agent: Jianq Chyun Intellectual Property Office

20070152210 - Organic thin film transistor and method for manufacturing the same: An organic thin film transistor and a method for manufacturing the same is disclosed, which can improve the device properties by decreasing a contact resistance which occurs in a contact area between an organic semiconductor layer and source/drain electrodes. The organic thin film transistor includes a gate electrode formed on... Agent: Brinks Hofer Gilson & Lione

20070152218 - Active component array substrate: Scan lines and data lines are disposed in a display region of a substrate, and multiple pixel regions are divided thereon. Switch components are disposed in the pixel regions, and each switch component is electrically connected to the scan line and data line. Pixel electrodes are disposed in the pixel... Agent: J C Patents, Inc.

20070152220 - Tft array substrate and method for fabricating the same: A four-mask process thin film transistor (TFT) array substrate and a method for fabricating the same is disclosed, which prevents a semiconductor tail from being formed. An open area is thus obtained and wavy noise is prevented from occurring. The method of fabricating a TFT array substrate comprises: forming a... Agent: Mckenna Long & Aldridge LLP

20070152219 - Thin film transistor array substrate and manufacturing method thereof: A thin film transistor array substrate includes a gate line and a data line intersecting each other on a substrate with a gate insulating film therebetween, a thin film transistor at an intersection of the gate line and the data line, the thin film transistor including a gate electrode electrically... Agent: Seyfarth Shaw, LLP

20070152222 - Organic electro-luminescence display device and method of manfacturing the same: Provided is an organic electro-luminescence display device. Because TFTs and organic light-emitting diode devices are formed on two different substrates, respectively, and the two substrates are attached to each other, so that productivity improves and manufacturing costs can be reduced. Also, because a pad portion exposed to the outside is... Agent: Song K. Jung Mckenna Long & Aldridge LLP

20070152227 - Cmos image sensor: Embodiments relate to a CMOS image sensor and a manufacturing a CMOS image sensor, that may be capable of enhancing a focusing function of light by forming a reflective layer between a micro lens and a photodiode, and may improve a sensitivity of an image sensor. According to embodiments, the... Agent: Sherr & Nourse, PLLC

20070152228 - Method of manufacturing a cmos image sensor: A CMOS image sensor may include at least one of: a semiconductor substrate over which a photodiode and transistors are formed; passivation layers formed over a semiconductor substrate; and color PRs buried in trenches formed in the passivation layers and formed to be higher than the trenches.... Agent: Sherr & Nourse, PLLC

20070152204 - Pcram device with switching glass layer: A memory device, such as a PCRAM, including a chalcogenide glass backbone material with germanium telluride glass and methods of forming such a memory device.... Agent: Dickstein Shapiro LLP

20070152206 - Device for manipulating particles using dielectrophoresis employing metal-post electrode structure and method of manipulating particles using the device at high flow rate: A device and method for manipulating particles using dielectrophoresis are disclosed. The device comprises a chamber comprising an inlet port, an outlet port, and metal post electrodes, and a power supply, wherein the metal post electrodes are arranged in at least two rows in a vertical position with respect to... Agent: Cantor Colburn, LLP

20070152207 - Semiconductor light-emitting device and manufacturing method thereof: A semiconductor light-emitting device comprises a substrate; and an active layer formed over the substrate comprising a well layer having an unintentionally-doped impurities; a first barrier layer; and a second barrier layer, wherein the well layer is disposed between the first barrier layer and the second barrier layer, the first... Agent: Bacon & Thomas, PLLC

20070152209 - Devices using polymers based on 3,6- and 2,7-conjugated poly(phenanthrene): A device having at least one layer including poly(p-phenylene)s based on 3,6-conjugated and 2,7-conjugated phenanthrene moietie having been synthesized by polycondensation using Ni(O)-mediated Yamamoto-type cross coupling are described as the charge transport layer or as the host for a dopant.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070152213 - Methods and structures for reducing lateral diffusion through cooperative barrier layers: A covered substrate is described, which comprises: (a) a flexible substrate layer; and (b) a plurality of cooperative barrier layers disposed on the substrate layer. The plurality of cooperative barrier layers further comprise one or more planarizing layers and one or more high-density layers. Moreover, at least one high-density layer... Agent: Mayer & Williams PC

20070152208 - Optimised method for preparing anellated, polycyclic and polyheterocyclic aromatic compounds: The invention relates to a method for producing anellated carbo- or heterocyclic aromatic compounds, which is based on the reduction of the corresponding diketone as starting compound. The reduction agent is thereby used in a strong molar excess, which represents a significant simplification in implementation of the method relative to... Agent: Millen, White, Zelano & Branigan, P.C.

20070152212 - Organic light emitting device and method of manufacturing the same: Disclosed is an organic light emitting device which includes a substrate; a encapsulation substrate, an organic light emitting unit interposed between the substrate and the encapsulation substrate. A water vapor absorption material-containing transparent sealant layer covers the organic light emitting unit. The sealant layer includes a transparent sealant having a... Agent: Knobbe Martens Olson & Bear LLP

20070152211 - Organic thin film transistor and method for manufacturing the same: An organic thin film transistor includes a buffer layer on a substrate, a source and drain electrodes on the buffer layer, wherein each of the source and drain electrodes is in an island shape, a tunneling barrier layer on the source and drain electrodes, an organic semiconductor layer on the... Agent: Seyfarth Shaw, LLP

20070152214 - Semiconductor device: One exemplary embodiment includes a semi-conductor device. The semi-conductor device can include a channel including that includes one or more compounds of the formula AxBxCxOx, wherein each A is selected from the group of Zn, Cd, each B is selected from the group of Ga, In, each C is selected... Agent: Hewlett Packard Company

20070152216 - Interconnection in an insulating layer on a wafer: An interconnection in an insulating layer on a wafer is described herein. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive lines waiting to... Agent: Jianq Chyun Intellectual Property Office

20070152215 - Test pads on flash memory cards: A semiconductor package is disclosed including test pads formed of solder bumps affixed to the semiconductor package during fabrication. When the package is encapsulated, due to the pressure exerted on the package during the encapsulation process, portions of the solder bumps get flattened out to be generally flush with and... Agent: Vierra Magen/sandisk Corporation

20070152221 - Liquid crystal display apparatus and manufacturing method therefor: A liquid crystal apparatus is provided wherein the liquid crystal layer comprises a section formed by polymerizing a polymerizable compound in the presence of a liquid crystal by selectively irradiating active energy rays onto the substrate surface when no voltage is applied, or alignment control layers and bumps are formed... Agent: Patrick G. Burns, Esq. Greer, Burns & Crain, Ltd.

20070152217 - Pixel structure of active matrix organic light-emitting diode and method for fabricating the same: A pixel structure of an active matrix organic light-emitting diode (AMOLED) includes an organic light-emitting diode (OLED), a data line, at least one scan line, at least one switch thin film transistor (TFT), at least one driving TFT and at least one storage capacitor with two transparent electrodes. Since both... Agent: Jianq Chyun Intellectual Property Office

20070152224 - Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films: A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor... Agent: Macpherson Kwok Chen & Heid LLP

20070152223 - Organic thin film transistor and organic light emitting display device including the same: An organic thin film transistor (OTFT) having a patterned organic semiconductor layer on top of an electrode wiring layer. In order to avoid damage to the underlying electrode wiring layer, the organic semiconductor layer is patterned so that none of the organic semiconductor layer is removed off the electrode wiring... Agent: Robert E. Bushnell Suite 300

20070152225 - Optical broadband emitters and methods of making the same: An optical broadband emitter and the method of making such a broadband emitter are described. Intermixing of closely coupled multiple quantum wells, especially carrier tunneled coupled quantum wells, is described using nano-imprinting of a gel like dielectric layer such as a sol-gel derived SiO2 layer into multiple stepped or graded... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070152226 - Led lamps: A high power LED lamp has a GaN chip placed over an AlGaInP chip. A reflector is placed between the two chips. Each of the chips has trenches diverting light for output. The chip pair can be arranged to produce white light having a spectral distribution in the red to... Agent: Dykema Gossett PLLC

20070152229 - Light emitting apparatus method for producing it and assembly incorporating it: A light emitting apparatus including a substrate, at least one light emitting diode chip mounted on the substrate, a light-transmitting member disposed on the substrate to form a space between the light-transmitting member and the substrate, and a resin disposed in the space to seal the light emitting diode chip,... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20070152230 - Separate optical device for directing light from an led: Embodiments of the present invention provide separate optical devices operable to couple to a separate LED, the separate optical device comprising an entrance surface to receive light from a separate LED when the separate optical device is coupled to the separate LED, an exit surface opposite from and a distance... Agent: SprinkleIPLaw Group

20070152231 - Led with compound encapsulant lens: An LED light source includes an LED emitter and an encapsulant that at least partially surrounds the emitter. The encapsulant includes an inner lens and an outer lens, the inner lens having a refractive index less than, and in some cases about 70 to 80% of, the refractive index of... Agent: 3m Innovative Properties Company

20070152232 - Gallium nitride-based semiconductor device: A gallium nitride-based semiconductor device has a p-type layer that is a gallium nitride (GaN) compound semiconductor layer containing a p-type impurity and exhibiting p-type conduction. The p-type layer includes a top portion and an inner portion located under the top portion. The inner portion contains the p-type impurity and,... Agent: Sughrue Mion, PLLC

20070152234 - Light emitting device: A light emitting device includes an active layer including atoms A of a matrix semiconductor having a tetrahedral structure, a heteroatom D substituted for the atom A in a lattice site, and a heteroatom Z inserted into an interstitial site positioned closest to the heteroatom D, the heteroatom D having... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070152233 - Manufacture method for zno based compound semiconductor crystal and zno based compound semiconductor substrate: A manufacture method that can manufacture ZnO based compound semiconductor crystal of good quality. A ZnO substrate is prepared to have a principal surface made of a plurality of terraces of (0001) planes arranged stepwise along an m-axis direction, the envelop of the principal surface being inclined relative to the... Agent: Masao Yoshimura Chen Yoshimura LLP

20070152235 - Laminated cell, junction terminal, pack battery, and method of manufacturing pack battery: Laminated cell (1) according to the present invention has a structure wherein a stacked electrode assembly comprising pole plate (61) of first polarity and pole plate (62) of second polarity is sealed by lamination sheets (7). Junction terminal (90) is of a unitary structure produced by covering connector junction (22)... Agent: Sughrue Mion, PLLC

20070152236 - Semiconductor nanocrystal heterostructures: A semiconductor nanocrystal can have a barbell shape. The nanocrystal can include two semiconductor materials selected so that upon excitation, one charge carrier is substantially confined to the one semiconductor material and the other charge carrier is substantially confined to the other semiconductor material.... Agent: Steptoe & Johnson LLP

20070152237 - Optical system for detecting the concentration of combustion products: Optical system for detecting the concentration of combustion products operating in situ and at high temperature based on measurement of the optical absorption of a gaseous mixture of combustion products through a photodetecting sensor based on gallium nitride (GaN), aluminium nitride (AlN), indium nitride (InN) and corresponding alloys. The operating... Agent: Venable LLP

20070152238 - Heterostructure field effect transistor and associated method: A device including a first layer having a first material, and the first material having a hexagonal crystal lattice structure defining a first bandgap and one or more non-polar planes is provided. The device further includes a second layer that is adjacent to the first layer having a second material.... Agent: Shawn A. Mcclintic General Electric Global Research

20070152239 - Semiconductor device: A semiconductor device has a semiconductor layer, and a first electrode (Schottky electrode or MIS electrode) and a second electrode (ohmic electrode) which are formed on the semiconductor layer apart from each other. The first electrode has a cross section in the shape of a polygon. A second electrode-side corner... Agent: Birch Stewart Kolasch & Birch

20070152240 - Bipolar junction transistor and manufacturing method thereof: An improved bipolar junction transistor and a method for manufacturing the same are provided. The bipolar junction transistor includes: a buried layer and a high concentration N-type collector region in a P-type semiconductor substrate; a low concentration P-type base region in the semiconductor substrate above the buried layer; a first... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070152241 - Gate capacitor having horizontal structure and method for manufacturing the same: A gate capacitor having a horizontal structure and a method for manufacturing the same is provided. The gate capacitor having a horizontal structure can be formed on a semiconductor substrate and used as a MOS transistor. The gate capacitor includes at least two adjacent gate electrodes and a capacitor dielectric... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070152242 - Thin film transistor array substrate and method of manufacturing the same: A thin film transistor array substrate includes a gate pattern on a substrate. The gate pattern includes a gate electrode, a gate line connected to the gate electrode, and a lower gate pad electrode connected to the gate line. A source/drain pattern includes a source electrode and a drain electrode,... Agent: Morgan Lewis & Bockius LLP

20070152243 - Standard cell, cell library using a standard cell and method for arranging via contact: According to an aspect of the present invention, there is provided a standard cell, including a cell frame having a rectangular region, a power supply interconnection, a center line of the power supply interconnection overlapping with a side line along a first direction of the cell frame, a via contact,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070152244 - Narrow width metal oxide semiconductor transistor: Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070152245 - Semiconductor device and method for manufacturing the same: Disclosed is a semiconductor device. The semiconductor device includes; a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on both sidewalls of the trench region; a gate formed in the trench region; and a source... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070152246 - Complementary metal oxide silicon image sensor and method of fabricating the same: Disclosed is a method of fabricating a CMOS (Complementary Metal Oxide Silicon) image sensor. The method includes the steps of: forming a device protective layer and a metal interconnection on a substrate formed with a light receiving device; forming an inner micro-lens on the metal interconnection; coating an interlayer dielectric... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070152247 - Cmos image sensor with wide dynamic range: The present invention relates a CMOS (Complementary Metal Oxide Semiconductor) image sensor capable of improving dynamic range by using an additional driver transistor. The CMOS image sensor according to the present invention has a pixel array which has a plurality of unit pixels each of which includes a photodiode and... Agent: Morgan Lewis & Bockius LLP

20070152248 - Complementary metal oxide semiconductor image sensor and method for fabricating the same: Provided are a CMOS image sensor and a method for fabricating the same. A nanopillar is plurally formed at an upper end of a light receiving element.... Agent: Foley And Lardner LLP Suite 500

20070152249 - Method for fabricating cmos image sensor: There is provided a method of manufacturing a CMOS image sensor, in which an anti-reflection coating layer is additionally formed on a pad electrode so that it is possible to prevent the pad electrode from being corroded by development solution of a sequential photolithography process and to bond an external... Agent: Sherr & Nourse, PLLC

20070152250 - Cmos image sensor with backside illumination and method for manufacturing the same: A CMOS image sensor includes a plurality of pixel regions formed under a front surface of a substrate, and having photodiodes separated from each other by a field oxide, a multi-layered metal interconnection formed over the pixel regions of the front of the substrate, a bump connected to an uppermost... Agent: Morgan Lewis & Bockius LLP

20070152251 - Image sensor and manufacturing method for the same: An image sensor including a first region where a pad is to be formed, and a second region where a light-receiving element is to be formed. A pad is formed over a substrate of the first region. A passivation layer is formed over the substrate of the first and second... Agent: Morgan Lewis & Bockius LLP

20070152253 - Ferroelectric oxide artificial lattice, method for fabricating the same and ferroelectric storage medium for ultrahigh density data storage device: The present invention is related to a ferroelectric storage medium for ultrahigh density data storage device and a method for fabricating the same. A supercell having high anisotropy is formed by controlling crystal structure and symmetry of unit structure (supercell) of artificial lattice by using an ordered alignment of predetermined... Agent: Schmeiser Olsen & Watts

20070152254 - Magnetic transistor structure: A magnetic transistor includes a first magnetic section, a second magnetic section, a conductive section, a first metal terminal, and a second metal terminal. The conductive section is disposed between and is in direct contact with both the first and second magnetic section. The first metal terminal is disposed on... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070152252 - Reducing aluminum dissolution in high ph solutions: A method for reducing the dissolution of aluminum gate electrodes in a high pH clean chemistry comprises modifying the high pH clean chemistry to include a silanol-based chemical. The silanol-based chemical causes a protective layer to form on a top surface of the aluminum gate electrode. The protective layer substantially... Agent: Intel Corporation C/o Intellevate, LLC

20070152255 - Semiconductor memory device having vertical channel transistor and method for fabricating the same: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the... Agent: Mills & Onello LLP

20070152256 - Method for fabricating a metal insulator-metal (mim) capacitor having capacitor dielectric layer formed by atomic layer deposition (ald): A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source... Agent: Young & Thompson

20070152257 - Semiconductor device having recessed landing pad and its method of fabrication: A semiconductor device having a recessed landing pad includes a semiconductor substrate and a lower interlayer dielectric layer disposed on the semiconductor substrate. A first landing pad is disposed through the lower interlayer dielectric layer to be in contact with the semiconductor substrate. A second landing pad is disposed through... Agent: Marger Johnson & Mccollom, P.C.

20070152259 - Method of forming inside rough and outside smooth hsg electrodes and capacitor structure: A container capacitor and method of forming the container capacitor are provided. The container capacitor comprises a lower electrode fabricated by forming a layer of doped polysilicon within a container in an insulative layer disposed on a substrate; forming a barrier layer over the polysilicon layer within the container; removing... Agent: Whyte Hirschboeck Dudek S.c.

20070152258 - Semiconductor device with a capacitor: Embodiments relate to a semiconductor having a capacitor and a method of fabricating the same, that may be capable of simplifying a manufacturing process and increasing a capacitance of a capacitor. In embodiments, a method of forming a capacitor may use a dual damascene process and may be simplified by... Agent: Sherr & Nourse, PLLC

20070152260 - Memory structure and method of manufacturing a memory array: A memory structure formed between two doping regions in a semiconductor substrate includes two conductive blocks functioning as floating gates formed at two sides of a first conductive line functioning as a select gat and insulated from the first conductive line with two first dielectric spacers therebetween, wherein the two... Agent: North America Intellectual Property Corporation

20070152261 - Nonvolatile semiconductor memory device having element isolating region of trench type: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070152263 - Dynamic random access memory cell layout and fabrication method thereof: A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is... Agent: Quintero Law Office, PC

20070152262 - Non-volatile memory device: Provided is a non-volatile memory device that can repetitively perform data write and erase operations in an embedded semiconductor device. In the non-volatile memory device, a device isolation region isolates a first active region and a second active region formed on a semiconductor substrate. A transistor electrode is formed on... Agent: Morgan Lewis & Bockius LLP

20070152264 - Nonvolatile memory device and method for fabricating the same: A nonvolatile (e.g., flash) memory device includes a substrate having a plurality of isolation areas and active areas; a trench formed on the isolation area; a first electrode layer formed on an inner wall of the trench; a first gate oxide layer formed between the inner wall of the trench... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070152265 - Semiconductor memory device and method for manufacturing the same: A semiconductor memory device includes: a memory cell array region formed in a semiconductor region of a first conductivity type and having a plurality of memory cells arranged in rows and columns; a plurality of word lines each of which collectively connects ones of the plurality of memory cells aligned... Agent: Mcdermott Will & Emery LLP

20070152266 - Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers: The fabrication of a tri-gate transistor formed with a replacement gate process is described. A nitride dummy gate, in one embodiment, is used allowing the growth of epitaxial source and drain regions immediately adjacent to the dummy gate. This reduces the external resistance.... Agent: Blakely Sokoloff Taylor & Zafman

20070152267 - Recess gate type transistor and method for fabricating the same: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the... Agent: Marshall, Gerstein & Borun LLP

20070152268 - Semiconductor component and method: A semiconductor component and method of making a semiconductor component is disclosed. In one embodiment, the semiconductor component includes a drift region of a first conductivity type, a body region of a second conductivity type, and a trench extending into the body region. A semiconductor region of the first conductivity... Agent: Dicke, Billig & Czaja

20070152269 - Vertical dmos device in integrated circuit: An integrated circuit that includes at least one vertical conduction DMOS device and other semiconductor devices.... Agent: Ostrolenk Faber Gerb & Soffen

20070152270 - Transistors and manufacturing methods thereof: Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region of the semiconductor substrate, a gate formed on the gate insulating film, a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070152271 - Gate electrode having a capping layer: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.... Agent: Jennifer Hayes Blakely, Sokoloff, Taylor & Zafman LLP

20070152272 - Method for fabricating a transistor using a soi wafer: Embodiments relate to a method for fabricating a transistor by using a SOI wafer. A gate insulation layer and a first gate conductive layer on a silicon-on-insulator substrate of a substrate to form a first gate conductive pattern, a gate insulation layer pattern, and a silicon layer pattern. A device... Agent: Sherr & Nourse, PLLC

20070152273 - High performance circuit with metal and polygate electrodes: A semiconductor structure and a method of fabricating the same wherein the structure includes at least one nFET device and a least one pFET device, where at least one of the devices is a thinned Si-containing gated device and the other device is a metal gated device are provided. That... Agent: Scully Scott Murphy & Presser, PC

20070152274 - Semiconductor device: A semiconductor device, including: a semiconductor substrate of a first conduction type; an active region used as a function-element-forming region on the semiconductor substrate; a low-resistance region of a second conduction type formed on an outermost periphery of the active region to surround the active region and having contact with... Agent: Rabin & Berdo, PC

20070152275 - Devices without current crowding effect at the finger's ends: ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and... Agent: Birch Stewart Kolasch & Birch

20070152276 - High performance cmos circuits, and methods for fabricating the same: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a... Agent: Scully Scott Murphy & Presser, PC

20070152277 - Mos field-effect transistor and manufacturing method thereof: To provide a manufacturing method of a MOS field-effect transistor in which such a structure is adopted that SiGe having a large lattice constant is embedded immediately below a channel and distortion is effectively introduced in a channel Si layer so that mobility of electrons or holes are drastically improved,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070152278 - Semiconductor device: A semiconductor device features connecting gate patterns of all transistors to a N+ or +P junction by the first connected wiring layer to prevent degradation of characteristics of the semiconductor device which results from plasma damages during a process. In order to connect a junction to a gate layer weak... Agent: Townsend And Townsend And Crew, LLP

20070152280 - Semiconductor memory device with triple well structure and method of manufacturing the same: A semiconductor memory device may include a semiconductor substrate that may have a first conductivity type. A first buried layer may be formed in the semiconductor substrate and may have a second conductivity type opposite to the first type conductivity. A first well may be formed on the first buried... Agent: Harness, Dickey & Pierce, P.L.C

20070152279 - Sram device: In a disclosed SRAM device, a contact connected to a source of an NMOS transistor is formed along a straight portion of an active region, rather than in a bent part. An NMOS source contact may be positioned along the same line as that of a corresponding PMOS drain contact,... Agent: Sherr & Nourse, PLLC

20070152281 - Narrow width metal oxide semiconductor transistor having a supplemental gate conductor pattern: A MOS transistor may include at least one of: a channel having a width W0 and a length L0; an active area with a channel between a source area and a drain area; a gate insulating layer formed over a channel; and/or a gate conductor formed over a gate insulating... Agent: Sherr & Nourse, PLLC

20070152282 - Semiconductor device and fabrication method thereof: A semiconductor device is provided. An embodiment of the semiconductor device includes: P-type source/drain regions formed in a semiconductor substrate; a gate insulation layer formed on a channel between the P-type source/drain regions; an N-type gate electrode formed on the gate insulation layer; and spacers with an ON structure formed... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070152283 - Semiconductor device and method of manufacturing the same: A semiconductor device and a manufacturing method thereof for preventing gate electrode degradation and gate current leakage. The semiconductor device includes a gate insulating layer including an H-k (high dielectric) material on a semiconductor substrate, a barrier metal layer including a metal alloy on the gate insulating layer, and a... Agent: Cantor Colburn, LLP

20070152284 - Transistor device and method for manufacturing the same: A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located over the substrate adjacent the recess.... Agent: Sherr & Nourse, PLLC

20070152285 - Cmos image sensor: A complementary metal oxide semiconductor (CMOS) image sensor is provided. The CMOS image sensor can include a photodiode, a transfer transistor (Tx), a reset transistor (Rx), a drive transistor (Dx), and a select transistor (Sx). The CMOS image sensor includes a floating diffusion region between the transfer transistor (Tx) and... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070152286 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a method for manufacturing the same are provided. The CMOS image sensor may be capable of improved thickness uniformity form microlenses formed at a reduced distance from the photodiodes. The CMOS image sensor can include: a semiconductor substrate on which a pixel array is formed,... Agent: Jeff Lloyd Saliwanchik, Lloyd & Saliwanchik

20070152288 - Dual-sided microstructured, position-sensitive detector: Abstract of the Disclosure The invention relates to a detector for determining the position and/or energy of photons and/or charged particles. Said detector comprises a plurality of diodes made of a semi-conductor material, n-contacts (1) and p-contacts (4), the n-contacts being provided by dividing an n-layer into individual segments. Said... Agent: Schweitzer Cornman Gross & Bondell LLP

20070152287 - Photonic diode: An element for interacting with electromagnetic radiation is disclosed, including a first self-resonant body, a second self-resonant body, and a directional device interposed between the first self-resonant body and the second self-resonant body. The directional device is adapted to inhibit propagation of electromagnetic radiation from the second self-resonant body to... Agent: Searete LLC Clarence T. Tegreene

20070152289 - Avalanche photodetector with reflector-based responsivity enhancement: An avalanche photodetector is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor. The first type of semiconductor material has a graded doping concentration of a dopant material within the absorption region. A multiplication region is proximate to and... Agent: Blakely Sokoloff Taylor & Zafman

20070152291 - Cmos image sensor: Disclosed is a CMOS image sensor including a gate electrode of a finger type transfer transistor for controlling the saturation state of a floating diffusion region according to the luminance level (i.e. low luminance or high luminance). The CMOS image sensor includes first and second photodiode regions for generating electrons... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070152290 - Thin film light-activated power switches, photovoltaic devices and methods for making micro-fluid ejected electronic devices: Thin film light-activated power switches, photovoltaic devices and methods for making a micro-fluid ejected electronic device. One such thin film light-activated power switch includes a micro-fluid ejected photoactive device having a first electrode, a second electrode, and a P-N junction between the first electrode and second electrode provided by an... Agent: Lexmark International, Inc. Intellectual Property Law Department

20070152292 - Method and apparatus for removing electrons from cmos sensor photodetectors: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.... Agent: Ess Technology, Inc C/o Haynes Beffel & Wolfeld LLP

20070152293 - Method for manufacturing semiconductor device: A semiconductor device is provided. The semiconductor device according to the present invention includes a semiconductor substrate, a second insulation layer, a buffer insulation layer adjacent to the second insulation layer, a third insulation layer and transistors. A high voltage device region and a low voltage device region are defined... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070152294 - Robust shallow trench isolation structures and a method for forming shallow trench isolation structures: In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A... Agent: Hitt Gaines, PC Lsi Corporation

20070152296 - Capacitor in semiconductor device and manufacturing method: The capacitor in a semiconductor device includes a substrate, a lower electrode formed over the substrate, a diffusion barrier formed over the lower electrode, a plurality of agglomerates formed over the diffusion barrier, a dielectric layer formed over the surface of the agglomerates to form an uneven surface, and an... Agent: Sherr & Nourse, PLLC

20070152295 - Metal-insulator-metal capacitor structure having low voltage dependence: A semiconductor capacitor device. A dielectric layer is on a substrate. A stack capacitor structure is disposed in the dielectric layer and comprises first and overlying second MIM capacitors electrically connected in parallel. The first and second MIM capacitors have individual upper and lower electrode plates and different compositions of... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070152297 - Fuse box reducing damage caused by laser blowing and cross talk, and method of manufacturing the same: Provided are a fuse box that simultaneously prevents damage caused by laser blowing and cross talk between the fuses and a method of manufacturing the same. In a fuse box having an open region in which fuses are opened by laser blowing and a bundle region in which fuse opens... Agent: Mills & Onello LLP

20070152299 - Inductor for semiconductor device and method of fabricating the same: The inductor for a semiconductor device includes at least one dielectric pattern selectively formed on a top of the interlayer dielectric, at least one first metal wire formed on a top of the interlayer dielectric, at least one second metal wire formed on a top of the dielectric pattern, and... Agent: Mayer, Brown, Rowe & Maw LLP

20070152300 - Inductor for semiconductor device and method of fabricating the same: The inductor for a semiconductor device comprises a first interlayer dielectric formed on a top of a silicon substrate, at least one first metal wire formed on a top of the first interlayer dielectric, a second interlayer dielectric formed on a top of the first interlayer dielectric to cover the... Agent: Mayer, Brown, Rowe & Maw LLP

20070152298 - Inductor structure of a semiconductor device: Embodiments relate to and inductor structure of a semiconductor device and a manufacturing method of the same, that may be capable of reducing a parasitic capacitance occurring between an inductor metallic interconnection and a silicon substrate. Support insulating layer patterns may be formed on a top of the silicon substrate... Agent: Sherr & Nourse, PLLC

20070152301 - Array capacitors for broadband decoupling applications, and methods of operating same: An integrated broadband array capacitor includes at least two regions with varying capacitance and response times. The broadband array capacitor is disposable on a socket or is integral with a socket. A method of operating the broadband array capacitor includes responding to load transients from each of the at least... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070152302 - Resistor of semiconductor device and method for fabricating the same: A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070152303 - Wafer with optical control modules in exposure fields: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprising a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and four control module fields (A1, A2, A3, A4,... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070152304 - Method of fabricating passivation: Embodiments relate to a passivation fabricating method. In the passivation fabricating method according to embodiments, a first oxide film may be formed by repeating deposition and etching of an oxide film on a silicon substrate in which an upper metal pad may be formed and a second oxide film may... Agent: Sherr & Nourse, PLLC

20070152305 - Method for forming a mask pattern for ion-implantation: A method for forming a mask pattern for ion-implantation comprises: forming a gate line pattern over a semiconductor substrate; forming a coating layer on the surface of gate line pattern; performing a plasma treatment on the top portion of the gate line pattern; forming a photoresist layer over the resulting... Agent: Townsend And Townsend And Crew, LLP

20070152306 - Semiconductor device and fabrication method thereof: A semiconductor device and fabrication method thereof. The semiconductor device comprises a substrate, an electroactive organic layer with conformal step coverage and uniform thickness, and a metal layer. The substrate is a conductive substrate or a nonconductive substrate with a conductive layer formed thereon. The electroactive organic layer and the... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070152307 - Semiconductor intergrated circuit: A semiconductor device comprising a signal transmission line of a microstrip structure, capable of increasing the characteristic impedance of the signal transmission line and reducing coupling between a plurality of signal lines. In a signal transmission line of a microstrip structure composed of a signal line and a ground plate,... Agent: Sughrue Mion, PLLC

20070152308 - Multichip leadframe package: A multichip package has a leadframe including peripheral leads arranged about a centrally situated die paddle. A first (“upper”) die is attached to a first (“top”) side of the leadframe die paddle, which can be generally flat. The second (“bottom”) side of the leadframe is partially cut away (such as... Agent: Haynes Beffel & Wolfeld LLP

20070152309 - Light emitting diode: A light emitting diode comprises: at least two electrodes; a first encapsulant layer; at least a chip; and a second encapsulant layer. The electrodes are fixed by the first encapsulant layer. The chip is electrically connected to the electrodes. The chip and the electrodes are covered with the second encapsulant... Agent: Troxell Law Office PLLC

20070152311 - Chip-packaging compositions including bis-maleimides, packages made therewith, and methods of assembling same: A chip-packaging composition includes a polymer of a bis-maleimide. A process includes formation of the chip-packaging composition including adding particulate fillers to achieve a coefficient of thermal expansion of about 20 ppm/K. A method includes assembly of the chip-packaging composition with a die or a mounting substrate. A computing system... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070152310 - Electrical ground method for ball stack package: A microelectronic package including a dielectric element with at least one conductive ground pad. The package may also include a microelectronic element with at least one ground contact exposed at a rear surface of the element. The ground pad and the ground contact are electrically connected to each other by... Agent: Tessera Lerner David Et Al.

20070152315 - Multi-die package and method for fabricating same: A multi-die package and a method of fabrication is discloses. The multi-die package includes a package substrate, a first semiconductor die bonded directly on the package substrate and connected electrically with the package substrate, and a second semiconductor die having a groove providing a receiving space, bonded directly on the... Agent: Cha & Reiter, LLC

20070152312 - Dual die package with high-speed interconnect: Embodiments of the invention relate to the construction of a dual die package with a high-speed interconnect. A package is created having a first die on a first side of a base substrate and a second die on a second side of the base substrate in opposed relation to the... Agent: Blakely Sokoloff Taylor & Zafman

20070152316 - Interposer pattern with pad chain: Provided is an interposer pattern having a conductive material for forming a pad chain that can reduce a wafer test time. The interposer pattern includes one or more interposers and an external conductive material for the pad chain. Each of the interposers includes a plurality of pad pairs internally interconnected.... Agent: Mills & Onello LLP

20070152314 - Low stress stacked die packages: A stacked die package comprises a first die on a substrate, a die attach layer superjacent to the first die, and a second die on the die attach layer. The die attach layer comprises a die attach material having a glass transition temperature substantially in the range of 150-180° C.... Agent: Blakely Sokoloff Taylor & Zafman

20070152313 - Stacked die semiconductor package: In one embodiment, the present invention includes a semiconductor package including a first semiconductor die with first active circuitry and a second semiconductor die with second active circuitry. An intermediate substrate may be located in the package between the first and second semiconductor dies to provide power to at least... Agent: Trop Pruner & Hu, PC

20070152317 - Stacked-type chip package structure: A stacked-type chip package structure including a substrate, a first chip, bonding wires, a second chip and B-stage conductive bumps is provided. The first chip is disposed on the substrate, and it has first bonding pads disposed on an active surface thereof. Besides, the first bonding pads are electrically connected... Agent: J.c. Patents

20070152318 - Structure and process of chip package: The present invention provides a chip package structure, which includes a chip and a buffering compound, wherein the chip has an active surface, a back surface opposite to the active surface and a plurality of side surfaces joining the active surface and the back surface. The buffering compound is disposed... Agent: Jianq Chyun Intellectual Property Office

20070152319 - Hidden plating traces: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate... Agent: Vierra Magen/sandisk Corporation

20070152320 - Semiconductor device, package structure thereof, and method for manufacturing the semiconductor device: A semiconductor device includes a plurality of insulating layers laminated on a substrate to cover passive elements such as a capacitor, an inductor, and the like, and to fix an IC chip in a face up state in one of the insulating layers. The insulating layers have similar structures in... Agent: Frommer Lawrence & Haug

20070152321 - Fluxless heat spreader bonding with cold form solder: The formation of electronic assemblies including a heat spreader coupled to at least one die is described. One embodiment relates to a method including positioning a solder on a heat spreader. The method also includes forming a solid state diffusion bond between the solder and the heat spreader. The solid... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20070152323 - Integrated heat spreader lid: A heat spreader lid includes an outer periphery region having a lip for bonding to an underlying substrate board, a center region, and one or more strain isolation regions. The strain isolation regions are located between the center region and the outer periphery region and may comprise a number of... Agent: Buchalter Nemer

20070152322 - Semiconductor device and method of manufacturing the same: A heatsink plate is to be fixed to a substrate with sufficient strength, so as to prevent the heatsink plate from being stripped off, to thereby secure reliability on the performance of the semiconductor chip. The heatsink plate has both the upper and lower surfaces of the fixing section sandwiched... Agent: Young & Thompson

20070152324 - Forced heat transfer apparatus for heating stacked dice: An apparatus and method are provided for effectively heating a first die stacked above a second die attached onto a substrate during wire bonding conducted on the first die. A gas outlet positionable adjacent to the first die is configured to project a hot gas onto bond pads of the... Agent: Ostrolenk Faber Gerb & Soffen

20070152325 - Chip package dielectric sheet for body-biasing: A chip package includes a thermal interface material disposed between a die backside and a heat sink. A dielectric sheet is also disposed between the die backside and the heat sink. The dielectric sheet diminishes overall heat transfer from the die to the heat sink by a small fraction of... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070152326 - Encapsulated external stiffener for flip chip package: The present invention relates to an external stiffener featuring reinforcing bars and a polymer and a method to make the same. In an embodiment, the stiffener may be used to decrease warpage in the package substrate caused by high temperature processing. In an embodiment, the reinforced bars are disposed over... Agent: Intel Corporation C/o Intellevate, LLC

20070152327 - Super high density module with integrated wafer level packages: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment,... Agent: Whyte Hirschboeck Dudek S.c.

20070152328 - Fluxless chip attached processes and devices: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a plurality of first metal bumps on a first surface, and a plurality of second metal bumps on a second surface, wherein at least one of (i) the plurality of first metal bumps, and (ii) the... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20070152329 - Heat-radiating semiconductor chip, tape wiring substrate and tape package using the same: A semiconductor chip, a tape package of the chip and a tape wiring substrate of the chip may be configured so as to effectively radiate heat generated from the chip externally through certain wiring patterns connected to certain pads. In an example, the chip may include a plurality of input... Agent: Harness, Dickey & Pierce, P.L.C

20070152331 - Tin-bismuth (sn-bi) family alloy solder and semiconductor device using the same: The formation of a relatively large amount of AuSn4 intermetallic compound may be inhibited in the junction because gold (Au) may not easily diffuse into a tin-bismuth (Sn—Bi) family alloy solder of a liquid state during a reflow process for connecting the semiconductor chip and substrate. Therefore, most of the... Agent: Harness, Dickey & Pierce, P.L.C

20070152330 - Package structure and manufacturing method thereof: A package structure and a manufacturing method thereof are provided. The package structure includes a chip, a substrate and a solder. The chip includes a bump disposed on the surface of the chip. The substrate includes a pad and a solder resistor layer. The pad is disposed on the surface... Agent: Birch Stewart Kolasch & Birch

20070152332 - Single or dual damascene via level wirings and/or devices, and methods of fabricating same: The present invention relates to integrated circuits that comprise via-level wirings and/or devices. Specifically, an integrate circuit of the present invention comprises a first line level and a second line level spaced apart from each other, with a via level therebetween. The first and second line levels both comprise metal... Agent: Scully Scott Murphy & Presser, PC

20070152333 - Metal interconnection of semiconductor device and method of fabricating the same: Disclosed are a metal interconnection of a semiconductor device and a method of fabricating the same. The metal interconnection includes an interlayer dielectric layer formed having a trench on a semiconductor layer, a first TaN layer formed at an inner wall of the trench, a second TaN layer formed on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070152334 - Semiconductor device and manufacturing method: A semiconductor device includes a semiconductor substrate, an interlayer insulating film formed over the substrate, a trench formed in the interlayer insulating film, a cover film formed over the inside surface of the trench, a barrier layer formed over the cover film; and a metal line formed over the barrier... Agent: Sherr & Nourse, PLLC

20070152335 - Metal interconnection of semiconductor device and method for forming the same: Disclosed are a metal interconnection of a semiconductor device and a method for manufacturing the same, capable of improving the reliability of the semiconductor device. The metal interconnection of the semiconductor device includes a first metal interconnection formed on a semiconductor substrate; an interlayer dielectric layer formed on the semiconductor... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070152338 - Method of forming fpga of multi-parallel structure and fpga structure thereof: A method of forming a field programmable gate array (FPGA) structure of a semiconductor device capable of reducing manufacturing cost through simpler processes includes forming a contact parallel connection structure in which contacts connected to a gate electrode and a source/drain by way of a first amorphous silicon pattern are... Agent: Mayer, Brown, Rowe & Maw LLP

20070152337 - Semiconductor device and manufacturing method therefor: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a conducting layer, a first insulating film formed on the semiconductor substrate and having a via hole formed therein, a lower barrier film formed on an inside wall of the via hole, a first metal wiring formed... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070152336 - Semiconductor device and method of manufacturing the same: A semiconductor device and method of manufacturing same, capable of preventing the material of a barrier metal layer from penetrating into an intermetallic insulating layer are provided. In an embodiment, the device can include: a first metal interconnection formed in a lower insulating layer on a semiconductor substrate; an intermetallic... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070152339 - Method for testing component built in circuit board: A method is provided for testing a built-in component including multiple terminals in a multi-layered circuit board. At least one signal pad is provided on a top surface of the multi-layered circuit board for signal transmission. Each of the signal pads are electrically connected to one of the multiple terminals.... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070152340 - Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (dram) circuitry: Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In... Agent: Wells St. John P.s.

20070152341 - Copper wiring protected by capping metal layer and method for forming for the same: A method for forming a copper metal wiring by using a damascene process, which includes the steps of: forming a damascene pattern on an interlayer insulating film on a semiconductor substrate; forming a barrier metal layer inside the damascene pattern; forming a copper layer in the damascene pattern; and forming... Agent: Mayer, Brown, Rowe & Maw LLP

20070152343 - Semiconductor device comprising a contact structure with increased etch selectivity: By providing additional etch stop layers and/or etch protection layers, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. Consequently, conductive line erosion and/or penetration into extension regions may be significantly reduced, thereby improving the... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070152342 - Via structure and process for forming the same: Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070152345 - Stacked chip packaging structure: A stacked chip packaging structure (10) includes a substrate (20), a first chip (40), a second chip (70), and a cover (80). The first chip is mounted on the substrate and is electrically connected with the substrate via a first plurality of wires (50a). The second chip is mounted above... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070152344 - Engine with cable direct to outboard memory: A device includes a first semiconductor die having a first surface and a second surface, a cable coupled to the first semiconductor die, and at least one memory device coupled to the cable. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070152347 - Face down type semiconductor device and manufacturing process of face down type semiconductor device: A semiconductor device of the present invention includes a circuit board, a semiconductor element, a resin and a level display pad. On the circuit board substrate electrodes are provided. The semiconductor element is mounted on the circuit board via the substrate electrodes. The resin fills the gap between the semiconductor... Agent: Mcginn Intellectual Property Law Group, PLLC

20070152346 - Silicon carrier having increased flexibility: An apparatus and method providing flexibility to a silicon chip carrier which, in at least one embodiment, comprises multiple chips and a silicon chip carrier having thinned regions between some adjacent chips, thus, allowing for increased flexibility and reduced package warpage.... Agent: Ference & Associates LLC

20070152348 - Array circuit substrate and wire bonding process using the same: An array circuit substrate including a plurality of substrate units, a plurality of non-stick test circuits, and a plurality of etching windows is provided. Each of the substrate units has a plurality of wire-bond pads and a plurality of plated wires. One of the plated wires is connected to one... Agent: Jianq Chyun Intellectual Property Office

20070152350 - Wiring substrate having variously sized ball pads, semiconductor package having the wiring substrate, and stack package using the semiconductor package: A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have... Agent: Marger Johnson & Mccollom, P.C.

20070152349 - Wafer level package having a stress relief spacer and manufacturing method thereof: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes... Agent: Mills & Onello LLP

20070152351 - Topographically indexed support substrates: The present invention provides an indexed support substrate. The support substrate comprises at least one set of indexing features that are distinguishable from one another and from the surrounding substrate. The support substrate also comprises a set of useful domains. The indexing features are positioned on the substrate in such... Agent: Michael Best & Friedrich, LLP

20070152352 - Micro-fabricated device with thermoelectric device and method of making: A micro-fabricated device, includes a support structure having an aperture formed therein, and a device substrate disposed within the aperture. The micro-fabricated device further includes a thermally isolating structure thermally coupling the device substrate to the support structure. The thermally isolating structure includes at least one n-doped region and at... Agent: Hewlett Packard Company

20070152353 - Nitride-based light emitting devices and methods of manufacturing the same: A light emitting device may include an n-clad layer formed on a crystalline wafer; a porous layer formed by processing the n-clad layer in a mixed gas atmosphere of HCl and NH3. The light emitting device may further include an active layer and a p-clad layer formed on the porous... Agent: Harness, Dickey & Pierce, P.L.C