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Active solid-state devices (e.g., transistors, solid-state diodes) June archive of inventions by patent app class 06/07

20070145345 - Non-volatile switching element, method for manufacturing the same, and integrated circuit having non-volatile switching elements: The present invention provides a non-volatile switching element having a novel structure that operates at a high speed and enables high integration, and an integrated circuit that includes such non-volatile switching elements. The switching element includes: a switching film formed on a substrate, made of a material causing a 10... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070145344 - Resistance-change nanocrystal memory: A resistance-change nanocrystal memory is proposed, which includes at least one memory unit. The memory unit further includes a channel and nanocrystals embedded in the channel. Electric charges in the nanocrystals are accessed, by applying a voltage to the channel. Then, conductivity of the channel is altered by the electric... Agent: Birch Stewart Kolasch & Birch

20070145348 - Quantum information processing device and method: Quantum information processing device includes resonator incorporating material containing physical systems, each of physical systems having at least four energy states, transition between two energy states of at least four energy states, and transition energy between at least two energy states of at least four energy states, at least four... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070145382 - Semiconductor light emitting diode and method for manufacturing the same: A high-efficiency semiconductor light emitting diode and a method for manufacturing the same are provided. The semiconductor LED has high internal quantum efficiency and can reduce the bad effect caused by the crystal defect. In the semiconductor light emitting diode, a conductive substrate has a three-dimensional top surface, and a... Agent: Mcdermott Will & Emery LLP

20070145390 - Nitride-based semiconductor device: A nitride-based semiconductor device includes a diode provided on a semiconductor substrate. The diode contains a first nitride-based semiconductor layer made of non-doped AlXGa1-XN (0≦X<1); a second nitride-based semiconductor layer made of non-doped or n-type AlYGa1-YN (0≦Y≦1, X<Y) having a lattice constant smaller than that of the first nitride-based semiconductor... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070145391 - Vertical type nitride semiconductor light emitting device and method of manufacturing the same: A vertical nitride semiconductor light emitting device and a manufacturing method thereof are provided. In the device, an ohmic contact layer, a p-type nitride semiconductor layer, an active layer, an n-type nitride semiconductor layer and an n-electrode are sequentially formed on a conductive substrate. At least one of a surface... Agent: Mcdermott Will & Emery LLP

20070145393 - Light emitting device package and method of manufacturing the same: A light emitting device package including a transparent cover having an electrode pattern formed on a bottom surface thereof; a light emitting device installed below the transparent cover and electrically connected to an external circuit via the electrode pattern; a fixing resin which fixes the light emitting device onto the... Agent: Sughrue Mion, PLLC

20070145395 - Light emitting module and surface light source device: A light emitting module including a light source set and a light guide member is provided. The light source set is suitable for providing a light and the light guide member is disposed above the light source set. The light guide member has a top surface, an opposite light incident... Agent: Jianq Chyun Intellectual Property Office

20070145394 - Semiconductor light-emitting material and light emitting device: A semiconductor light-emitting material includes a semiconductor substance including a matrix semiconductor whose constituent atoms are bonded to form a tetrahedral structure, an impurity atom S substituted for an atom in a lattice site of the matrix semiconductor, and an impurity atom I inserted in a interstitial site of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070145346 - Connection electrode for phase change material, associated phase change memory element, and associated production process: The present disclosure relates to a connection electrode for phase change materials, to an associated phase change memory element and to an associated production process, wherein a plurality of separate insulation regions are formed in an electrode material at least at a connection surface. This reduces the overall size of... Agent: Brinks Hofer Gilson & Lione Infineon

20070145347 - Coupled quantum well devices (cqwd) containing two or more direct selective contacts and methods of making same: The present invention relates to a device structure that contains two or more conducting layers, two peripheral insulating layers, one or more intermediate insulating layers, and two or more conductive contacts. The two or more conducting layers are sandwiched between the two peripheral insulating layers, and they are spaced apart... Agent: Scully Scott Murphy & Presser, PC

20070145350 - Display apparatus: A display apparatus that includes: a plurality of light-emitting devices disposed on a substrate with an accumulation of, in this or inverse order, a light transmissive electrode layer, a functional layer including a light-emitting layer, and an opposing electrode layer; and a color conversion layer that is provided on a... Agent: Robert J. Depke Lewis T. Steadman

20070145349 - Light emitting device: A light emitting device includes a first light emitting diode (LED) emitting a first light emission of at least a first wavelength, and a second light emitting diode emitting a second light emission of at least a second wavelength. The second LED is placed in close proximity to the first... Agent: Alexander R Schlee SchleeIPInternational P.C.

20070145351 - Semiconductor device with anisotropy-relaxed quantum dots: A semiconductor quantum dot device includes: an inclined InP substrate whose principal surface normal is inclined from a [0 0 1] direction to a [1 −1 0] direction in a (0 0 1) plane; and semiconductor quantum dots made of InAs1-xSbx (0<x<1) and disposed above the principal surface of the... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070145356 - Carbon nanotube interdigitated sensor: A carbon nanotube sensor (30), for determining the degree of the presence of an unwanted environmental agent, includes a plurality of carbon nanotubes (18). The sensor (30) comprises first and second conducting layers (32, 34) having alternatively interdigitated fingers (36, 38). The plurality of carbon nanotubes (18) having a material... Agent: Ingrassia Fisher & Lorenz, P.C.

20070145355 - Doped organic semiconductor material: The present invention relates to a doped organic semiconductor material comprising an organic matrix material which is doped with at least one heteromonocyclic and/or heteropolycyclic compound, the compound having at least one nitrogen atom with a free electron pair.... Agent: Sutherland Asbill & Brennan LLP

20070145352 - Endohedral fullerene derivative, proton conductor and fuel cell: With regard to a solid polymer based fuel cell, an electrolyte membrane for conducting proton between a fuel electrode and an air electrode is conventionally made from a material obtained by chemically modifying a hollow fullerene such as C60 by means of a proton dissociable group. However, this fuel cell... Agent: Young & Thompson

20070145359 - Materials for organic thin film transistors: The invention provides organic thin film transistors including quinacridone derivatives with formula (I). These OTFTs are useful in making flat panel displays, photovoltaic devices and sensors. In the present invention, the disclosed quinacridone derivatives exhibit as p-type organic semiconductors in OTFTs.... Agent: Cooper & Dunham, LLP

20070145360 - Organic electronic device having dual emitter dopants: Electronic devices comprising an anode, buffer layer, hole transport layer, photoactive layer, electron transport layer, electron injection layer, and cathode are provided, where the photoactive layer comprises a dual dopant in a metallic complex. The dopants are selected so that their emitting wavelengths are essentially the same, while their ionization... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070145361 - Organic semiconductor material and organic electronic device: An organic semiconductor material comprising a compound which has a generalized porphyrin skeleton and which has a molecular structure such that the distance from the generalized porphyrin ring plane to the center of each atom forming the generalized porphyrin skeleton, is not more than 1 Å... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070145354 - Organic thin-film transistors: A novel barrier layer which protects electronic devices from adverse environmental effects such as exposure to light, especially white light, is described. The barrier layer comprises a copolymer having an acrylate unit and an acrylate unit with a pendant dye group. Also disclosed are processes for producing such electronic devices.... Agent: Richard M. Klein, Esq. Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070145353 - Phenanthroline derivative and light emitting element and light emitting device using the same: An aspect of the present invention is an electron injecting material represented by a general formula (2). In the general formula (2), R6 is selected from the group consisting of an alkyl group having 1 to 4 carbon atoms, an alkenyl group having 1 to 4 carbon atoms, and an... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070145357 - Thin-film transistor: There is provided herein a performance-enhancing composition comprising inorganic nanoparticles dispersed in a polymer selected from the group consisting of polysiloxane, polysilsesquioxane, and mixtures thereof. This composition, when applied to a thin-film transistor, such as a bottom-gate thin-film transistor, as an overcoat or top layer, improves the carrier mobility and... Agent: Richard M. Klein, Esq. Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070145358 - Transparent conductor and transparent conductive material: The transparent conductor of the present invention comprises a conductive layer containing a conductive particle, a binder, a polymerization initiator, and a radical scavenger. In the transparent conductor of the present invention, the conductive layer contains the radical scavenger in addition to the conductive particle. Therefore, even when the conductive... Agent: Oliff & Berridge, PLC

20070145362 - Passive electronic devices: A passive electronic device includes layers of a layered structure on a support surface. The device can include a first layer part that includes electrically conductive or semiconductive material and that has a contact surface. The device can also include second layer parts that include electrically conductive material and are... Agent: Leading Edge Law Group, PLC/xerox-parc

20070145365 - Image sensor: Embodiments relate to and image sensor. In embodiments, the image sensor may include a semiconductor substrate, a photodiode region, a gate electrode, a dummy gate, and an interlayer dielectric layer. The semiconductor substrate includes a field oxide layer. The photodiode region may be formed on the semiconductor substrate. The gate... Agent: Sherr & Nourse, PLLC

20070145366 - Semiconductor structures: A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate . A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed... Agent: Duane Morris LLPIPDepartment (tsmc)

20070145364 - Test pattern for analyzing delay characteristic of interconnection line and method for analyzing delay characteristic of interconnection line using the same: A test pattern for analyzing a delay characteristic of an interconnection line and a method of analyzing a delay characteristic of an interconnection line using the test pattern are provided. The test pattern for analyzing a delay characteristic of an interconnection line includes: a first metal line formed as a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145363 - Testing memory integrated circuits: A memory device may include a controller and a plurality of flash memory dice. The controller is provided for read and write access and communications with a host. However, the controller may also be utilized to test one or more of the flash memory dice mounted on the device. In... Agent: Trop Pruner & Hu, PC

20070145367 - Three-dimensional integrated circuit structure: The preferred embodiments of the present invention provide a three-dimensional (3D) semiconductor structure and a method of forming the same. The 3D semiconductor structure includes a first substrate bonded to a second substrate. The first substrate includes substantially all NMOS devices. The second substrate includes substantially all PMOS devices. The... Agent: Slater & Matsil, L.L.P.

20070145368 - Two-frequency switchover type crystal oscillator: The present invention relates to a two-frequency switchover type crystal oscillator in which first and second IC chips and first and second crystal resonators are connected to wiring patterns of a circuit substrate to form first and second oscillation circuits, and the first and second oscillation circuits are selectively operated... Agent: Edwards Angell Palmer & Dodge LLP

20070145369 - Array substrate for liquid crystal display device and method of fabricating the same: An array substrate for a liquid crystal display device includes a substrate having a display area and a driving circuit area, a first semiconductor layer formed on the substrate in the display area, the first semiconductor layer having an active region and source and drain regions at opposing sides of... Agent: Morgan Lewis & Bockius LLP

20070145370 - Electro-optic device, method for manufacturing the same, and electronic apparatus: An electro-optic device includes data lines and scanning lines extending to cross each other on a substrate, pixel electrodes disposed on the substrate for respective pixels defined corresponding to the data lines and the scanning lines in a plan view of the substrate, thin film transistors electrically connected to the... Agent: Oliff & Berridge, PLC

20070145373 - Epitaxial imprinting: The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar... Agent: Scully, Scott, Murphy & Presser, P.C.

20070145372 - Semiconductor device, and electronic apparatus: An object of the present invention is to provide a technique for improving characteristics of a TFT and realizing the structure of the TFT optimal for driving conditions of a pixel section and a driving circuit, using a smaller number of photo masks. A semiconductor device has a semiconductor film,... Agent: Nixon Peabody, LLP

20070145371 - Thin-film transistor: A thin-film transistor, such as a top-gate thin-film transistor, is provided herein. The thin-film transistor has a performance-enhancing layer, such as a performance-enhancing bottom layer, comprising a polymer other than a polyimide. In specific embodiments, the polymer is selected from the group consisting of polysiloxane, polysilsesquioxane, and mixtures thereof. In... Agent: Richard M. Klein, Esq. Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070145374 - Thin film transistor for display panel: A thin film transistor substrate includes a base substrate, a gate electrode, a gate insulating layer, a surface treating layer, an active layer, a source electrode and a drain electrode. The gate electrode is formed on the base substrate. The gate insulating layer is formed on the base substrate to... Agent: Macpherson Kwok Chen & Heid LLP

20070145375 - Method of manufacturing nanowire, method of manufacturing a semiconductor apparatus including nanowire and semiconductor apparatus formed from the same: A method of manufacturing a nanowire, a method of manufacturing a semiconductor apparatus including a nanowire and a semiconductor apparatus formed from the same are provided. The method of manufacturing a semiconductor apparatus may include forming a material layer pattern on a substrate, forming a first insulating layer on the... Agent: Harness, Dickey & Pierce, P.L.C

20070145376 - Gallium nitride crystal substrate, semiconductor device, method of manufacturing semiconductor device, and method of identifying gallium nitride crystal substrate: Affords GaN crystal substrates that can reduce the occurring of cracks and fractures in the GaN crystal substrates when the semiconductor devices are manufactured, semiconductor devices including them, methods of manufacturing the semiconductor devices, and methods of identifying the GaN crystal substrates. A gallium nitride crystal substrate has a surface... Agent: Judge & MurakamiIPAssociates

20070145377 - Semiconductor device and method for manufacturing same: A semiconductor device of a double diffused MOS structure employing a silicon carbide semiconductor substrate. The semiconductor device comprises a silicon carbide semiconductor epitaxial layer provided on a surface of the silicon carbide semiconductor substrate and having a first conductivity which is the same conductivity as the silicon carbide semiconductor... Agent: Rabin & Berdo, PC

20070145378 - Silicon carbide bipolar junction transistors having a silicon carbide passivation layer on the base region thereof, and methods of fabricating same: A bipolar junction transistor (BJT) includes a silicon carbide (SiC) collector layer of first conductivity type, an epitaxial silicon carbide base layer of second conductivity type on the silicon carbide collector layer, and an epitaxial silicon carbide emitter mesa of the first conductivity type on the epitaxial silicon carbide base... Agent: Myers Bigel Sibley & Sajovec

20070145383 - High luminance light emitting diode and liquid crystal display device using the same: A light emitting diode (LED) is provided with a base substrate, a plurality of light emitting chips disposed on the upper surface of the base substrate and electrically coupled in parallel to one another, and a fluorescent material layer for covering the light emitting chips.... Agent: Macpherson Kwok Chen & Heid LLP

20070145384 - Iii-nitride light emitting device with double heterostructure light emitting region: In a device, a III-nitride light emitting layer is disposed between an n-type region and a p-type region. A first spacer layer, which is disposed between the n-type region and the light emitting layer, is doped to a dopant concentration between 6×1018 cm3 and 5×1019 cm−3. A second spacer layer,... Agent: Patent Law Group LLP

20070145380 - Low optical loss electrode structures for leds: An electrode structure is disclosed for enhancing the brightness and/or efficiency of an LED. The electrode structure can have a metal electrode and an optically transmissive thick dielectric material formed intermediate the electrode and a light emitting semiconductor material. The electrode and the thick dielectric cooperate to reflect light from... Agent: Macpherson Kwok Chen & Heid LLP

20070145379 - Optimized contact design for thermosonic bonding of flip-chip devices: A light emitting device (A) includes a semiconductor die (100). The semiconductor die includes: an epitaxial structure (120) arranged on a substrate (160), the epitaxial structure forming an active light generating region (140) between a first layer (120n) on a first side of the active region and having a first... Agent: Fay Sharpe LLP

20070145386 - Semiconductor light emitting device and method of manufacturing the same: Provided are a semiconductor light emitting device having a nano pattern and a method of manufacturing the semiconductor light emitting device. The semiconductor light emitting device includes: a semiconductor layer comprising a plurality of nano patterns, wherein the plurality of nano patterns are formed inside the semiconductor layer; and an... Agent: Buchanan, Ingersoll & Rooney PC

20070145385 - Semiconductor light emitting device and semiconductor light emitting apparatus: A first semiconductor light emitting device comprises: a transparent substrate; a light emitting layer; and a roughened region. The transparent substrate has a first major surface and a second major surface, and is translucent to light in a first wavelength band. The light emitting layer is selectively provided in a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070145381 - Semiconductor light-emitting device: A light-emitting diode has: a substrate; a light-emitting layer having a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer stacked sequentially on a front side of the substrate; a first current-blocking portion partially formed in the middle on the light-emitting layer; a current-conducting... Agent: Mcginn Intellectual Property Law Group, PLLC

20070145387 - Led housing and fabrication method thereof: The invention relates to an LED housing and its fabrication method. In the LED housing, a heat conducting part has a chip mounting area, a heat connecting area opposed to the chip mounting area and a groove formed adjacent to the heat connecting area. An electrical connecting part has a... Agent: Lowe Hauptman Berner, LLP

20070145388 - Semiconductor component: A surface emitting semiconductor component (1) with an emission direction which comprises a semiconductor body (2). The semiconductor body comprises a plurality of active regions (4a, 4b) which are suitable for the generation of radiation and are arranged in a manner spaced apart from one another, a frequency-selective element (6)... Agent: Cohen Pontani Lieberman & Pavane LLP

20070145389 - Light emitting device: A light emitting device firstly includes a light emitting diode (LED) structure, having a top surface with a light emitting region. The device also has a heterojunction within the device structure, the heterojunction having a p-type and an n-type semiconductor layer, and a plurality of electrodes positioned on the top... Agent: Alexander R Schlee SchleeIPInternational P.C.

20070145392 - Light emitting devices having current blocking structures and methods of fabricating light emitting devices having current blocking structures: Light emitting devices and methods of fabricating light emitting devices having a current blocking mechanism below the wire bond pad are provided. The current blocking mechanism may be a reduced conduction region in an active region of the device. The current blocking mechanism could be a damage region of a... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070145397 - High efficiency light emitting diode (led): An (Al, Ga, In)N light emitting diode (LED), wherein light extraction from chip and/or phosphor conversion layer is optimized. By novel shaping of LED and package optics, a high efficiency light emitting diode is achieved.... Agent: Gates & Cooper LLP Howard Hughes Center

20070145398 - Light emission diode and method of fabricating thereof: Provided is a light emission diode package and a fabricating method thereof. The light emission diode package includes a heat sink having a groove, a printed circuit board on the heat sink, a light emission diode on the groove, a reflector coupled to the heat sink, a lead frame included... Agent: Birch Stewart Kolasch & Birch

20070145399 - Light emitting diode package: An LED package is improved in heat radiating performance. The LED package includes a package substrate having heat radiating means; a heat radiating layer arranged on the package substrate with an area at least larger than a mounting area of a light emitting diode chip to provide a horizontal heat... Agent: Mcdermott Will & Emery LLP

20070145402 - Semiconductor component which emits radiation, and method for producing the same: This invention describes a radiation-emitting semiconductor component with the a multilayered structure that contains a radiation-emitting active layer, and a window transparent to radiation that has a first principal face and a second principal face opposite the first principal face, and whose first principal face adjoins the multilayered structure. At... Agent: Fish & Richardson PC

20070145400 - Semiconductor device and method for manufacturing the same: There is provided a semiconductor device mounted with a light emitting element, which can be downsized easily, improve light emitting efficiency and be formed easily, and a method for manufacturing the semiconductor device effectively. The semiconductor device includes a substrate, a light emitting element mounted on the substrate by flip... Agent: Drinker Biddle & Reath (dc)

20070145396 - Semiconductor light emitting device and method of manufacturing the same: A semiconductor light emitting device having high reflectivity and a high electrical contact property between a light reflection layer and a semiconductor layer is provided. The semiconductor light emitting device is formed by laminating a semiconductor layer, a light reflection layer and a protective layer on a substrate in this... Agent: Sonnenschein Nath & Rosenthal LLP

20070145401 - Semiconductor light emitting device, semiconductor element, and method for fabricating the semiconductor light emitting device: In the semiconductor light emitting device of the present invention, a reflective layer for reflecting light emitted by a semiconductor light emitting element is formed on a Cu wiring pattern, and a bonding section is formed on a light-emitting-element-mounting area on the Cu wiring pattern, to which an electrode of... Agent: Morrison & Foerster LLP

20070145403 - Luminescent device and method for manufacturing the same: A luminescent device including a die pad lead composed of an inner lead and an outer lead, a case for uniting the inner lead, a light emitting diode chip mounted on a first predetermined position of one main surface of the inner lead, and a transparent sealing material portion for... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070145404 - Semicondcutor device and manufacturing method of semiconductor device: A semiconductor device made by mounting a light emitting element on a substrate, where an optically-transparent cover with a flat plate shape is installed on the light emitting element and a groove part for suppressing reflection of light emission of the light emitting element is formed in the cover.... Agent: Drinker Biddle & Reath (dc)

20070145406 - Nitride semiconductor light emitting device: Disclosed herein is a nitride semiconductor light emitting device, which is improved in luminance and reliability. The light emitting device, comprises an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer sequentially formed on a substrate, an n-side electrode formed on a portion of an upper... Agent: Mcdermott Will & Emery LLP

20070145405 - Light emitting device and method of fabricating the same: Disclosed is a light-emitting device (100) has a light-emitting layer portion (24) which is composed of a group III-V compound semiconductor and a transparent thick-film semiconductor layer (90) with a thickness of not less than 40 μm which is formed on at least one major surface side of the light-emitting... Agent: Snider & Associates

20070145408 - Hf control bidirectional switch: An HF control bi-directional switch component of the type having its gate referenced to the rear surface formed in the front surface of a peripheral well of the component, including two independent gate regions intended to be respectively connected to terminals of a transformer having a midpoint connected to the... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070145407 - Thyristor and method of manufacture: A thyristor and a method for manufacturing the thyristor that includes a gate region extending from the first major surface into a semiconductor substrate and an anode region extending from the second major surface into the semiconductor substrate. A cathode region extends into a portion of the gate region. Optionally,... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070145409 - Five channel fin transistor and method for fabricating the same: A semiconductor device comprises a substrate defining a recessed active region; a fin active region connected to the recessed active region and extending above the recessed active region. The fin active region includes first, second, third, fourth, and fifth sides, the first and second sides being proximate the recessed active... Agent: Townsend And Townsend And Crew, LLP

20070145410 - Jfet with drain and/or source modificaton implant: The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a... Agent: Koppel, Patrick & Heybl

20070145411 - Trench polysilicon diode: Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a N− (P−) type epitaxial region on a N+ (P+) type substrate and forming a trench in the N− (P−) type epitaxial region. The method further includes forming a insulating layer in... Agent: Wagner, Murabito & Hao LLP Third Floor

20070145412 - Heterojunction bipolar transistor and manufacturing method thereof: The object of the present invention is to provide a heterojunction bipolar transistor with high breakdown tolerance which can be manufactured at a high reproducibility and a high yield, the heterojunction bipolar transistor includes: a sub-collector layer; a collector layer formed on the sub-collector layer; a base layer formed on... Agent: Greenblum & Bernstein, P.L.C

20070145413 - Isolated power domain core regions in platform asics: A platform application specific integrated circuit (ASIC) including a base layer. The base layer generally comprises a predefined input/output (I/O) region and a predefined core region. The predefined input/output (I/O) region may comprise a plurality of pre-diffused regions disposed in the platform ASIC. The predefined core region may comprise one... Agent: Lsi Logic Corporation

20070145414 - Ultrafast recovery diode: An ultrafast recovery diode. In a first embodiment, a rectifier device comprises a substrate of a first polarity, a lightly doped layer of the first polarity coupled to the substrate and a metallization layer disposed with the lightly doped layer. The ultrafast recovery diode includes a plurality of wells, separated... Agent: Morgan, Lewis & Bockius, LLP.

20070145418 - Devices without current crowding effect at the finger's ends: ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and... Agent: Birch Stewart Kolasch & Birch

20070145417 - High voltage semiconductor device having a lateral channel and enhanced gate-to-drain separation: A semiconductor device having a lateral channel with contacts on opposing surfaces thereof. The semiconductor device includes a conductive substrate having a source contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes an isolation layer above the conductive substrate, a lateral channel above the... Agent: Slater & Matsil, L.L.P.

20070145415 - High-frequency semiconductor device: A semiconductor device operating at a frequency between 0.8 GHz and 300 GHz includes an active region that is positioned on a semi-insulating GaAs substrate; a gate electrode that is positioned in the active region; and a source electrode and a drain electrode that are positioned on the surface of... Agent: Leydig Voit & Mayer, Ltd

20070145416 - Semiconductor device: A semiconductor device comprises on a surface of a first semiconductor layer of the first conduction type a second semiconductor layer of the first conduction type. A semiconductor base layer of the second conduction type is formed on the second semiconductor layer, and a semiconductor diffusion layer of the first... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070145419 - Method of manufacturing cmos image sensor: A CMOS image sensor and a method of manufacturing the same are provided. The method is capable of reducing a distance between a micro-lens and a photodiode and simplifying the manufacturing process for the CMOS image sensor. In an embodiment, the interlayer dielectric layers of high level metal lines (e.g.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145420 - Semiconductor device: The invention provides a semiconductor device that solves a problem of reflection of a pattern of a wiring formed on a back surface of a semiconductor substrate on an output image. A reflection layer is formed between a light receiving element and a wiring layer, that reflects an infrared ray... Agent: Morrison & Foerster LLP

20070145421 - Circuit and method for controlling internal voltage of semiconductor memory apparatus: A circuit for controlling an internal voltage of a semiconductor memory apparatus including a deep power down signal input unit, which receives a deep power down signal indicating that a deep power down mode is starting, and supplies the received signal to a level shifter; and one or more level... Agent: Venable LLP

20070145422 - Cmos image sensor and manufacturing method thereof: A CMOS image sensor and method of manufacturing same is provided. The CMOS image sensor can include: photodiodes formed on a semiconductor substrate for generating a charge according to an amount of incident light; a first planarization layer formed on the semiconductor substrate; a plurality of color filter layers formed... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145425 - Cmos image sensor: Embodiments relate to a complementary metal oxide semiconductor (CMOS) image sensor. According to embodiments, the CMOS image sensor may include a semiconductor substrate, an interlayer insulating layer, a color filter layer, an overcoat layer, and a plurality of microlenses. The semiconductor substrate may include a plurality of photodiodes and transistors... Agent: Sherr & Nourse, PLLC

20070145423 - Cmos image sensor and manufacturing method thereof: A CMOS (complementary metal oxide semiconductor) image sensor and method of fabricating the same is provided. The CMOS image sensor can include: a semiconductor substrate in which an active region and a device isolation region are defined; a photodiode region including a first region and a second region extending from... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145424 - Image sensor, controlling method of the same, x-ray detector and x-ray ct apparatus: The present invention provides always stably sampling a high quality image irrespective of the displacement of a subject, with a simpler arrangement. The image sensor in accordance with the present invention includes a plurality of photodiodes arranged in a two-dimensional array and a plurality of read out gate circuits for... Agent: Patrick W. Rasche Armstrong Teasdale LLP

20070145426 - Image sensor: Embodiments relate to an image sensor. In embodiments, the image sensor may include a semiconductor substrate formed with a plurality of photodiodes, an interlayer dielectric layer formed on the semiconductor substrate, a color filter layer formed on the interlayer dielectric layer, a planar layer formed on the color filter layer,... Agent: Sherr & Nourse, PLLC

20070145427 - Solid-state image sensor: A solid-state image sensor capable of suppressing generation of cross talk or a dark current and improving transfer efficiency of electrons (signal charge) can be obtained. This solid-state image sensor includes a plurality of pixels and a transfer gate electrode arranged in each of the plurality of pixels. An OFF-state... Agent: Ditthavong Mori & Steiner, P.C.

20070145428 - Isolation trench of a semiconductor device: Embodiments relate to a method for forming an isolation trench of a semiconductor device. In embodiments, a method for forming an isolation trench of a semiconductor device may include forming a mask layer pattern on a semiconductor substrate, forming an organic material layer on the semiconductor substrate and the mask... Agent: Sherr & Nourse, PLLC

20070145429 - Structure and method for a fast recovery rectifier structure: An apparatus and method for a fast recovery rectifier structure. Specifically, the structure includes a substrate of a first dopant. A first epitaxial layer lightly doped with the first dopant is coupled to the substrate. A first metallization layer is coupled to the first epitaxial layer. A plurality of trenches... Agent: Morgan, Lewis & Bockius, LLP.

20070145431 - Fin-fet having gaa structure and methods of fabricating the same: Example embodiments of the present invention relate to a semiconductor device and methods of fabricating the same. Other example embodiments of the present invention relate to a fin-field effect transistor (Fin-FET) having a fin-type channel region and methods of fabricating the same. A Fin-FET having a gate all around (GAA)... Agent: Harness, Dickey & Pierce, P.L.C

20070145430 - Cmos device with asymmetric gate strain: The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain is obtained through non symmetric placement of stress inducing structures as part of the gate electrode. Silicon nitride layers may... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070145435 - Mos varactor: Embodiments relate to a MOS varactor and a method for manufacturing the same, in which an ion implantation process for adjusting a threshold voltage may be omitted so as to lower the surface density of an N type well, thereby expanding a tuning range. The MOS varactor may include a... Agent: Sherr & Nourse, PLLC

20070145432 - Semiconductor device: Embodiments relate to a semiconductor device that may include a gate stack formed on an upper portion of an active region in a semiconductor substrate, the gate stack including a gate insulating layer and a gate, a first shallow impurity region formed on both sides of the gate in the... Agent: Sherr & Nourse, PLLC

20070145433 - Semiconductor device: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, a semiconductor device may include an active area defined on a semiconductor substrate by a first isolation layer and a second isolation layer, a diode in the active area placed at one side of... Agent: Sherr & Nourse, PLLC

20070145434 - Semiconductor device: Embodiments relate to a method for manufacturing a semiconductor substrate. According to embodiments, a gate oxide layer may be formed on a semiconductor substrate. Also, a well region may be formed in the semiconductor substrate including the gate oxide layer. Then, after forming a gate electrode on the semiconductor substrate,... Agent: Sherr & Nourse, PLLC

20070145436 - Thin film transistor substrate of liquid crystal display and method for fabricating same: An exemplary thin film transistor substrate (200) includes a substrate (201), a gate (212), a gate insulating layer (203), an amorphous silicon layer (214), a pixel electrode (216), a drain (217), and a source (218). The gate is formed at the gate. The gate insulating layer is formed at the... Agent: Wei Te Chung Foxconn International, Inc.

20070145437 - Image sensor and method of manufacturing the same: An image sensor may include at least one of: a semiconductor substrate including a plurality of photodiodes and a pad section; a protective layer formed over a semiconductor substrate including a trench pattern; an interlayer dielectric layer formed over a cell area of a protective layer; a color filter layer... Agent: Sherr & Nourse, PLLC

20070145438 - Pixel sensor cell having reduced pinning layer barrier potential and method thereof: A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.... Agent: Ibm Microelectronics Intellectual Property Law

20070145442 - Cmos image sensor: Embodiments relate to a vertical-type CMOS image sensor, a method of manufacturing the same, and a method of gettering the same, in which source and drain regions are expanded to improve grounding and gettering effects. In embodiments, the vertical-type CMOS image sensor may include a silicon substrate, a first photodiode... Agent: Sherr & Nourse, PLLC

20070145440 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes a semiconductor substrate having a photodiode region and a transistor region defined therein, first and second gate electrodes formed on the photodiode region of the semiconductor substrate with a gate insulating layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145439 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and method of manufacturing the same are provided. In one embodiment, the CMOS image sensor includes: an interlayer dielectric layer formed on a semiconductor substrate including a plurality of photodiodes and transistors; a plurality of color filter isolation layers formed on the interlayer dielectric layer; a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145441 - Cmos image sensor and method for manufacturing the same: Provided is a CMOS image sensor. The CMOS image sensor can include a semiconductor substrate, a blue photodiode region, a red photodiode region, a green photodiode region, an overcoat layer, and microlenses. The substrate can have a first photodiode region, a second photodiode region, and a transistor region. The blue... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145444 - Cmos image sensor and method for manufacturing the same: Disclosed are a CMOS image sensor and a method for manufacturing the same. The CMOS image sensor includes a photodiode area and a floating diffusion area formed on a semiconductor substrate, a transistor formed on the semiconductor substrate between the photodiode area and the floating diffusion area, an isolation layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145443 - Cmos image sensor and method of manufacturing the same: A CMOS image sensor is provided. The CMOS image sensor includes: a photodiode region formed in an active region of a substrate; a transistor formed on a transistor region of the active region of the substrate; a low-concentration diffusion region formed on the photodiode region while being spaced apart from... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145446 - Cmos image sensor: A CMOS image sensor includes a photodiode, and a plurality of transistors for transferring charges accumulated at the photodiode to one column line, wherein at least one transistor among the plurality of transistors has a source region wider than a drain region, for increasing a driving current.... Agent: Morgan Lewis & Bockius LLP

20070145445 - Cmos image sensor and method for manufacturing the same: A method for manufacturing a CMOS image sensor is provided. The method includes: forming a photodiode on a semiconductor sustrate; forming a color filter layer on the photodiode; forming a planar layer on the color filter layer; forming a first microlens on the planar layer; and forming a second microlens... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145447 - Pixel and cmos image sensor including the same: A pixel which may prevent the voltage of a floating diffusion region of the pixel from being outside a desired or predetermined driving voltage range by adjusting the equivalent capacitance of the floating diffusion region may be provided. The pixel may include a photodiode which may convert light energy into... Agent: Harness, Dickey & Pierce, P.L.C

20070145449 - Capacitor to be incorporated in wiring substrate, method for manufacturing the capacitor, and wiring substrate: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a... Agent: Sughrue-265550

20070145448 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device includes: a first semiconductor region having first conductivity; a channel formation region in which a channel inversion layer having second conductivity is formed; a second semiconductor region having the second conductivity; a third semiconductor region having the second conductivity; a laminated insulating film formed on... Agent: Robert J. Depke Lewis T. Steadman

20070145450 - Dram cell design with folded digitline sense amplifier: The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active... Agent: Williams, Morgan & Amerson

20070145451 - Semiconductor device having vertical-type channel and method for fabricating the same: A semiconductor device includes an active region including a surface region and a first recess formed below the surface region, the active region extending along a first direction; a device isolation structure provided on an edge of the active region; a gate line traversing over the surface region of the... Agent: Townsend And Townsend And Crew, LLP

20070145452 - Integrated circuit devices including a capacitor: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer... Agent: Myers Bigel Sibley & Sajovec

20070145453 - Dielectric layer for electronic devices: A dielectric layer for electronic devices is disclosed herein. The dielectric layer comprises inorganic nanoparticles dispersed in a polymer selected from the group consisting of polysiloxane, polysilsesquioxane, and mixtures thereof. The layer improves the carrier mobility and current on/off ratio of an electronic device incorporating it, especially a thin film... Agent: Richard M. Klein Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070145454 - Scalable integrated logic and non-volatile memory: A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers.... Agent: Leffert Jay & Polglaze , P.A. Attn: Kenneth W. Bolvin

20070145459 - Eeprom devices and methods of operating and fabricating the same: In one aspect, an electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite... Agent: Volentine Francos, & Whitt PLLC

20070145456 - Flash memory device and method of manufacturing the same: A non-volatile memory device includes a semiconductor substrate having an active region defined by isolation films that extend along a first direction. A control gate line extends along in a second direction perpendicular to the first direction. First and second floating gates are formed on the active region and below... Agent: Townsend And Townsend And Crew, LLP

20070145460 - Flash memory device and method of manufacturing the same: Disclosed are a flash memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) structure and a method of manufacturing the same. The flash memory device includes source and drain diffusion regions separated from each other on opposite sides of a trench in an active region of a semiconductor substrate, a control gate inside... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070145461 - Floating gate of flash memory device and method of forming the same: Disclosed is a floating gate of a flash memory device, wherein a tunneling oxide layer is formed on a semiconductor substrate, and a floating gate is formed in the shape of a lens having a convex top surface.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070145462 - Low tunnel barrier insulators: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070145455 - Non-volatile semiconductor device and method of fabricating embedded non-volatile semiconductor memory device with sidewall gate: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor.... Agent: Miles & Stockbridge PC

20070145463 - Pcram device with switching glass layer: A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method.... Agent: Dickstein Shapiro LLP

20070145464 - Random access memory device utilizing a vertically oriented select transistor: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely... Agent: Dickstein Shapiro LLP

20070145458 - Semiconductor device and manufacturing method thereof: A semiconductor device which is formed in a self-aligned manner without causing a problem of misalignment in forming a control gate electrode and in which a leak between the control gate electrode and a floating gate electrode is not generated, and a manufacturing method of the semiconductor device are provided.... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070145457 - System and method of forming a split-gate flash memory structure: A method for forming a split-gate flash memory structure includes etching a first gate layer to form one or more floating gates and forming an isolation layer over the floating gates. An insulation layer is deposited over the isolation layer and planarized.... Agent: Haynes And Boone, LLP

20070145467 - Eeproms with trenched active region structures and methods of fabricating and operating same: An EEPROM includes a semiconductor substrate and a device isolation region defining first, second and third active regions in the semiconductor substrate. The EEPROM also includes at least one first insulation region in at least one first trench in the first active region. A floating gate insulation layer is disposed... Agent: Myers Bigel Sibley & Sajovec

20070145466 - Flash memory device and method for manufacturing the same: A flash memory device and a method of manufacturing the same, wherein a silicon layer having a micro grain is formed between a tunnel oxide layer and a floating gate using a hemi-spherical grain (HSG) method, thereby preventing the dopant of the floating gate from being diffused into the tunnel... Agent: Marshall, Gerstein & Borun LLP

20070145465 - Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof: Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof. The non-volatile floating gate memory cell comprises a semiconductor substrate of a first conductivity type. A first region of a second conductivity type different from the first conductivity type is formed in the semiconductor substrate. A second... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070145468 - Quantum dot nonvolatile transistor: Some embodiments of the present invention include apparatuses and methods relating to nonvolatile memory transistors.... Agent: Intel Corporation C/o Intellevate, LLC

20070145470 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070145469 - Split gate type non-volatile memory device: Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active... Agent: Sherr & Nourse, PLLC

20070145471 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070145472 - Flash memory cell including dual tunnel oxide layer and method of manufacturing the same: A flash memory cell may include a tunnel oxide layer over a semiconductor substrate with a first tunnel having a first thickness and a second tunnel having a second thickness. A charge storage layer may be formed over a tunnel oxide layer, an insulating layer may be formed over a... Agent: Sherr & Nourse, PLLC

20070145473 - Semiconductor device and electronic control unit using the same: A semiconductor device with enhanced heat releasability and low-cost manufacturability is disclosed. This device has a substrate with an electronic circuit disposed on a first principal surface, a semiconductor element which is provided at the first surface of the substrate and electrically connected by wire bonding to the electronic circuit,... Agent: Crowell & Moring LLP Intellectual Property Group

20070145474 - Vertical-gate mos transistor for high voltage applications with differentiated oxide thickness: A vertical-gate MOS transistor is integrated in a semiconductor chip of a first conductivity type having a main surface, and includes an insulated trench gate extending into the semiconductor chip from the main surface to a gate depth. The trench gate includes a control gate and an insulation layer for... Agent: Seed Intellectual Property Law Group PLLC

20070145475 - Semiconductor device: A semiconductor device is discloses that includes an n-type semiconductor substrate; an alternating conductivity type layer on semiconductor substrate, the alternating conductivity type layer including n-type drift regions and p-type partition regions arranged alternately; p-type channel regions on the alternating conductivity type layer; and trenches formed from the surfaces of... Agent: Rossi, Kimms & Mcdowell LLP.

20070145476 - Semiconductor device: Embodiments relate to a semiconductor device. In embodiments, a semiconductor device may include a semiconductor substrate having isolation layers and a well region, a gate electrode formed within a trench having a predetermined depth in the well region, source/drain regions formed at both sides of the trench, respectively, an interlayer... Agent: Sherr & Nourse, PLLC

20070145477 - Transistor having a protruded drain: A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is... Agent: Mills & Onello LLP

20070145478 - High voltage semiconductor device and method of manufacturing the same: A high voltage semiconductor device includes a semiconductor substrate having a high voltage well region; a device isolation film to define an active region of the semiconductor substrate; a drift region formed at an outer periphery of the device isolation film; an impurities region formed under the bottom of the... Agent: Mayer, Brown, Rowe & Maw LLP

20070145479 - Semiconductor device having super junction structure: A semiconductor device includes: two main electrodes; multiple first regions; and multiple second regions. The first region having a first impurity concentration and a first width and the second region having a second impurity concentration and a second width are alternately repeated. A product of the first impurity concentration and... Agent: Posz Law Group, PLC

20070145481 - Silicon-on-insulator chip having multiple crystal orientations: A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070145482 - Thin film transistor and manufacturing method thereof, and liquid crystal display device having thin film transistor and manufacturing method thereof: A liquid crystal display device includes a substrate, a gate line and a data line intersected with each other to define a pixel region on the substrate, a thin film transistor having a nanowire channel layer in an intersection region of the gate line and the data line, and a... Agent: Brinks Hofer Gilson & Lione

20070145480 - Thin film transistor, electrode thereof and method of fabricating the same: A method of forming an electrode of a semiconductor device is provided. A material layer comprising an organo-metallic compound is first formed on a substrate. Thereafter, an electrode is formed by irradiating the material layer through utilizing the heating property of laser. Next, the material layer is patterned by utilizing... Agent: Jianq Chyun Intellectual Property Office

20070145483 - Semiconductor device: A highly-integrated, high-performance semiconductor device with a simplest possible structure can be provided. This semiconductor device comprises a semiconductor element that includes: a first semiconductor region of a first conductivity type provided in a plate-like form on a semiconductor substrate; a first ferroelectric insulating film provided on a first side... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070145484 - Regulator circuit and semiconductor device therewith: A regulator circuit including an output-stage transistor for supplying a current to an external circuit has an electrostatic protection transistor formed in parallel with the output-stage transistor. The base of the electrostatic protection transistor is connected to, for example, the base of the output-stage transistor, or alternatively to a ground... Agent: Birch Stewart Kolasch & Birch

20070145485 - Integrated circuit devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate: Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on... Agent: Myers Bigel Sibley & Sajovec

20070145486 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device has a memory cell and a peripheral transistor formed on a substrate. The memory cell is provided with a select transistor formed on the substrate and a capacitor connected to the select transistor. A diffusion layer of the peripheral transistor is connected to an upper layer... Agent: Young & Thompson

20070145487 - Multigate device with recessed strain regions: Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby improving performance of the device.... Agent: Intel Corporation C/o Intellevate, LLC

20070145488 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a substrate, a p-channel MIS transistor formed on the substrate, the p-channel MIS transistor having a first gate electrode, and an n-channel MIS transistor formed on the substrate separately from the p-channel MIS transistor, the n-channel MIS transistor having a second gate electrode. Each of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070145489 - Design of high-frequency substrate noise isolation in bicmos technology: A high-frequency noise isolation structure and a method for forming the same are provided. The noise isolation structure isolates a first device region and a second device region over a semiconductor substrate. The noise isolation structure preferably includes a sinker region substantially encircling a first device region, a buried layer... Agent: Slater & Matsil, L.L.P.

20070145490 - Semiconductor device and method for manufacturing the same: Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device. In embodiments, a transistor including the gate electrode and a source/drain may be formed between isolation layers and a contact may be connected to the source/drain. A barrier layer may be formed at a boundary between... Agent: Sherr & Nourse, PLLC

20070145491 - Semiconductor device and method of manufacture: A semiconductor device includes a substrate in which at least one transistor is formed; an interlayer insulating layer formed over the entire surface of the substrate including the transistor, the interlayer insulating layer having contact holes to expose the electrodes of the transistor; and contact insulating layers formed over the... Agent: Sherr & Nourse, PLLC

20070145492 - Semiconductor device and method of manufacture: A method of manufacturing a semiconductor device includes forming an insulating layer over the semiconductor substrate and the gate electrode. An insulating layer may have a via hole connected to the semiconductor substrate or the gate electrode and a trench connected to the via hole. A first barrier layer and... Agent: Sherr & Nourse, PLLC

20070145493 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070145494 - Semiconductor device and method for manufacturing the same: Gate length is 110 nm±15 nm or shorter (130 nm or shorter in a design rule) or an aspect ratio of an area between adjacent gate electrode structures thereof (ratio of the height of the gate electrode structure to the distance between the gate electrode structures) is 6 or higher.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070145495 - Method of fabricating a mosfet transistor having an anti-halo for modifying narrow width device performance: A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing a performance of a narrow width transistor with respect to a wide width transistor by introducing a dopant into the... Agent: Blakely Sokoloff Taylor & Zafman

20070145496 - Semiconductor device and method of manufacturing the same: according to embodiments, a semiconductor device may include a semiconductor substrate in which source and drain regions may be formed, a gate insulating layer formed on the semiconductor substrate, a gate electrode formed on the gate insulating layer, a first sidewall insulating layer formed on the side of the gate... Agent: Sherr & Nourse, PLLC

20070145497 - Semiconductor device: Embodiments relate to a semiconductor device including an impurity region formed in the semiconductor device; an insulating layer formed on the impurity region; and a contact formed to have a certain step difference in the impurity region through the insulating layer.... Agent: Sherr & Nourse, PLLC

20070145498 - Device with scavenging spacer layer: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen-scavenging spacer layer on side walls of the high-k gate dielectric layer and metal gate may reduce such oxidation during high... Agent: Intel Corporation C/o Intellevate, LLC

20070145500 - Cmos image sensor and manufacturing method thereof: A CMOS image sensor capable of improving characteristics of the image sensor by preventing damage to a photodiode region and a method for manufacturing the same are provided. The CMOS image sensor includes: a semiconductor substrate on which a device isolation region and an active region are defined; a photodiode... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145499 - Photovoltaic ultraviolet sensor: A photovoltaic ultraviolet sensor comprises a zinc oxide single crystal substrate. On the +c face of the zinc oxide single crystal substrate, an ultraviolet receiver is formed. The exemplary ultraviolet receiver includes a Schottky electrode which, when receiving ultraviolet rays, produces a voltage in cooperation with the zinc oxide single... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070145501 - Semiconductor device having a suspended micro-system: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.

20070145502 - Spin polarization amplfying transistor: An embodiment of the invention is a transistor formed in part by a ferromagnetic semiconductor with a sufficiently high ferromagnetic transition temperature to coherently amplify spin polarization of a current. For example, an injected non-polarized control current creates ferromagnetic conditions within the transistor base, enabling a small spin-polarized signal current... Agent: Intel/blakely

20070145503 - Pixel structure with improved charge transfer: An active pixel is described comprising a semiconductor substrate and a radiation sensitive source of carriers in the substrate, such as for instance, a photodiode. A non-carrier storing, carrier collecting region in the substrate is provided for attracting carriers from the source as they are generated. At least one doped... Agent: Daniel E. Ovanezian Blakely, Sokoloff, Taylor & Zafman LLP

20070145504 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor is provided. The CMOS image sensor can include: a plurality of photodiodes formed on a semiconductor substrate; an interlayer dielectric layer formed on an entire surface of the semiconductor substrate having the plurality of photodiodes; color filter layers including multi-layered blue color filter layers formed on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145505 - Image sensor and method for manufacturing the same: Disclosed are an image sensor and a method for manufacturing the same, capable of increasing a light absorbing coefficient by forming a rough surface on a photodiode. The image sensor includes a semiconductor substrate with a plurality of photodiodes thereon having rough upper surfaces, a dielectric layer on the semiconductor... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070145506 - Assembly of image-sensing chip and circuit board with inward wire bonding: An assembly of image-sensing chip and circuit boardwith inward wire bonding, including an image-sensing chip, a circuit board and a glass board. The circuit board is formed with a window and several wire bonding slots. An image-sensing chip is adhered to the circuit board. A wire bonding area is defined... Agent: Rosenberg, Klein & Lee

20070145507 - Contact layers for thin film solar cells employing group ibiiiavia compound absorbers: The present invention provides methods and apparatus for deposition of contact layers for Group IBIIIAVIA solar cells using electrodeposition and/or electroless deposition approaches, and solar cells that result therefrom. In one aspect of the invention, the solar cell that results includes a substrate, a stacked contact layer that includes a... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070145508 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a fabrication method thereof are provided. The CMOS image sensor includes a semiconductor substrate having an active area and an isolation area; a photodiode area and a transistor area defined on the active area; a plurality of semiconductor patterns formed on the photodiode area; a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145511 - Cmos image sensor: A CMOS image sensor is provided. The CMOS image sensor includes: a semiconductor substrate having a photodiode region and a floating diffusion region defined thereon; a gate electrode formed inside the photodiode region of the semiconductor substrate; a low concentration impurity region formed on the photodiode region at one side... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145509 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a fabrication method thereof is provided. The CMOS image sensor includes a semiconductor substrate having an active area and an isolation area; a photodiode area and a transistor area formed on the active area; a gate electrode formed on the transistor area where the gate... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145510 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and method for fabricating same are provided. The CMOS image sensor can include a gate electrode formed on an active area of a first conductive type semiconductor substrate, on which a photodiode area and a transistor area are defined; a low-density second conductive type diffusion region... Agent: Jeff Lloyd Saliwanchik, Lloyd & Saliwanchik

20070145512 - Photogate stack with nitride insulating cap over conductive layer: A photogate structure having increased quantum efficiency, especially for low wavelength light such as blue light. The photogate is formed of a thin conductive layer, such as a layer of doped polysilicon. A nitride insulating cap is formed over the conductive layer. The nitride layer reduces the reflections at the... Agent: Dickstein Shapiro LLP

20070145513 - Semiconductor device, an electronic device and an electronic apparatus: A gate insulating film 3 is formed of an insulative inorganic material containing silicon and oxygen as a main material. The gate insulating film 3 contains hydrogen atoms. A part of the absorbance of infrared radiation of which wave number is in the range of 830 to 900 cm−1 is... Agent: Harness, Dickey & Pierce, P.L.C

20070145514 - Trench field plate termination for power devices: In accordance with an embodiment of the invention, a semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. A first silicon region of a first conductivity type... Agent: Townsend And Townsend And Crew, LLP

20070145516 - Cmos image sensor and method for manufacturing the same: Embodiments relate to a CMOS image sensor. In embodiments, the CMOS image sensor may include a semiconductor substrate, a photodiode, a first conduction type impurity region, a first insulating layer, a conduction layer, and a second insulating layer. The semiconductor substrate may have a trench in which a device isolation... Agent: Sherr & Nourse, PLLC

20070145517 - Method of manufacturing a semiconductor device: A method for manufacturing a semiconductor device includes forming an insulation film over a semiconductor substrate having a conduction layer; forming a trench pattern over the insulation film; etching an upper portion of the insulation film by using the trench pattern as a mask to form a trench; removing the... Agent: Sherr & Nourse, PLLC

20070145518 - Circuit board, semiconductor device, and manufacturing method of circuit board: A circuit board includes a semiconductor substrate which has a plurality of through holes passing from an upper surface to a lower surface thereof. A plurality of wiring lines are provided on the upper surface of the semiconductor substrate and have bottomed cylindrical portions located within regions corresponding to the... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070145515 - Metal electrical fuse structure: An electrical fuse and a method for forming the same are provided. The electrical fuse includes a dielectric layer over a shallow trench isolation region and a contact plug extending from a top surface of the dielectric layer to the shallow trench isolation region, wherein the contact plug comprises a... Agent: Slater & Matsil, L.L.P.

20070145519 - Butted contact structure: A semiconductor structure and a method of forming the same using replacement gate processes are provided. The semiconductor structure includes a butted contact coupling a source/drain region, or a silicide on the source/drain region, of a first transistor and a gate extension. The semiconductor structure further includes a contact pad... Agent: Slater & Matsil, L.L.P.

20070145520 - Semiconductor device and manufacturing method of the same: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions... Agent: Morrison & Foerster LLP

20070145521 - Semiconductor device and method of manufacturing the same: embodiments relate to a semiconductor device that may include a continuously formed pad oxide layer and a field oxide layer. The device may include a semiconductor substrate having a trench, an insulating material formed in the trench, a pad oxide layer formed at the active region of the semiconductor substrate... Agent: Sherr & Nourse, PLLC

20070145522 - Semiconductor device and method of manufacturing the same: A semiconductor device includes an element isolation insulating film provided in a semiconductor substrate between first and second element regions, a gate electrode running over the element isolation insulating film, first and second element regions, a first stopper film formed on the gate electrode and first element region to cover... Agent: Foley And Lardner LLP Suite 500

20070145523 - Integrateable capacitors and microcoils and methods of making thereof: Method for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A variable capacitors may employ stops between a moveable electrode and a fixed electrode to reduce and/or prevent electrical shorting between the moveable and fixed electrode. A capacitor may employ a split bottom... Agent: Oliff & Berridge, PLC

20070145524 - Fpga structure provided with multi parallel structure and method for forming the same: In an FPGA of a semiconductor device and a method of forming the FPGA, a first pattern having a voltage selectable conductivity is formed to connect first vias of the semiconductor device in parallel.... Agent: Mayer, Brown, Rowe & Maw LLP

20070145526 - Mim capacitor and method for manufacturing the same: Disclosed are an MIM (Metal-Insulator-Metal) capacitor and a method of manufacturing the same. The MIM capacitor includes: a lower metal layer and a lower metal interconnection on a substrate; a barrier metal layer on the lower metal layer; an insulating layer on the barrier metal layer; an upper metal layer... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070145525 - Mim capacitor structure and method of manufacturing the same: A metal-insulator-insulator (MIM) capacitor structure is provided. The MIM capacitor includes a top electrode, a bottom electrode and a dielectric layer. The dielectric layer is disposed between the top electrode and the bottom electrode. The main feature for this kind of MIM capacitor is that the bottom electrode includes a... Agent: Jianq Chyun Intellectual Property Office

20070145528 - Power dissipation-optimized high-frequency coupling capacitor and rectifier circuit: A power dissipation-optimized high-frequency coupling capacitor is provided for a rectifier circuit as well as a power dissipation-optimized high-frequency rectifier circuit. The elements of the rectifier stages of the inventive high-frequency rectifier circuit are disposed in an optimized manner regarding space such that the coupling capacitors are connected directly to... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070145527 - Semiconductor device: A semiconductor device has an electrode pad, a capacitor and a substrate. The substrate has a given area on which the electrode pad and the capacitor are arranged. The electrode pad and the capacitor are arranged on the substrate so that each of at least two sides of the capacitor... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070145531 - Semiconductor device and method for manufacturing the same: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate including first and second well areas doped with second conductive ions, a third well area in the first well and doped with the second conductive ions, a base area in the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070145533 - Bipolar transistor with isolation and direct contacts: A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides... Agent: Greenblum & Bernstein, P.L.C

20070145532 - High voltage bicmos device and method for manufacturing the same: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICOMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070145529 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers... Agent: Fish & Richardson P.C.

20070145530 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation... Agent: Morrison & Foerster LLP

20070145534 - Reference voltage generating circuit and semiconductor integrated circuit using the reference voltage generating circuit: A reference voltage generating circuit is disclosed. The reference voltage generating circuit includes a collector layer where collectors of transistors are disposed, a base layer where bases of the transistors are disposed and which base layer is formed on the surface of the collector layer, and plural emitter layers in... Agent: Cooper & Dunham, LLP

20070145535 - Semiconductor device and method of manufacturing the same: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high... Agent: Foley And Lardner LLP Suite 500

20070145536 - Compliant terminal mountings with vented spaces and methods: A compliant structure is provided on a semiconductor wafer. The compliant structure includes cavities. The compliant structure and the wafer seal the cavities during process steps used to form conductive elements on the compliant structure. After processing, vents are opened to connect the cavities to the exterior of the assembly.... Agent: Tessera Lerner David Et Al.

20070145537 - Semiconductor device and method for manufacturing the same: Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device that may be capable of improving a step coverage of main chip and scribe lane regions during a formation of an interlayer dielectric are provided. In embodiments, the semiconductor device may include metal layers formed on... Agent: Sherr & Nourse, PLLC

20070145538 - Cmp apparatus for polishing dielectric layer and method of controlling dielectric layer thickness: A CMP apparatus has a CMP unit for polishing a dielectric layer, a thickness monitoring unit for monitoring a thickness index of the polished dielectric layer, and a thickness correcting unit for further reducing the thickness of the polished dielectric layer in accordance with the thickness index by etching. The... Agent: North America Intellectual Property Corporation

20070145540 - Semiconductor device having semiconductor element, insulation substrate and metal electrode: A semiconductor device includes: first and second metal electrodes having inner surfaces facing each other; a semiconductor element sandwiched between the electrodes; and first and second insulation substrates disposed on the electrode and opposite to the semiconductor element, respectively. Each of the insulation substrates is made of ceramics. At least... Agent: Posz Law Group, PLC

20070145539 - Method and system for providing an integral radio frequency shield in a molded array package: A method and system for fabricating an electromagnetic radiation shield for an electronics package is disclosed. The electronics package includes a substrate, at least one ground contact feature, and a protective layer. The electronics package is physically coupled to at least one additional electronics package through at least the substrate.... Agent: Sawyer Law Group LLP

20070145542 - Nano-wire electrode structure: An electronic device such as a sensor or a NEMS. The electronic device comprises at least one substrate; a plurality of electrodes disposed on the substrate; and at least one nano-wire growing from an edge of a first electrode to an edge of a second electrode. A method for making... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20070145541 - Stack type surface acoustic wave package, and method for manufacturing the same: Disclosed herein is a stack type surface acoustic wave package. The surface acoustic wave package comprises a first bare chip having a plurality of electrodes formed thereon, a second bare chip having a plurality of electrodes and via-holes formed thereon, a connecting portion electrically connecting the first bare chip to... Agent: Lowe Hauptman Berner, LLP

20070145545 - Integrated circuit with at least one integrated transmission line: An integrated circuit is disclosed that includes at least one integrated transmission line for the transmission of a high-frequency differential signal with a number of at least two series-connected line arrangements, each of which has a differential input, a differential output, a first trace, connected to a first terminal of... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070145544 - Method for producing a grid cap with a locally increased dielectric constant: A method for producing a semiconductor product. Semiconductor product components are formed in a semiconductor product region of the substrate. A layer made of low-k material is subsequently formed on the substrate. Electrically conductive interconnects are formed in and/or on the layer made of low-k material. The layer of low-k... Agent: Brinks Hofer Gilson & Lione

20070145543 - Plating bar design for high speed package design: A method including modifying a characteristic impedance along a length of a plating bar of a substrate package. An apparatus including a package substrate including a plurality of transmission lines therethrough, a portion of the plurality of transmission lines each including a plating bar coupled thereto, wherein the plating bar... Agent: Blakely Sokoloff Taylor & Zafman

20070145546 - Thermal interface material and solder preforms: A solder preform having multiple layers including a solder layer filled with additives interposed between two unfilled layers for improved wettability. A solder preform having a sphere which contains a solder material filled with additives, and an unfilled surface layer for improved wettability. A thermal interface material having a bonding... Agent: Senniger Powers

20070145547 - Package having exposed integrated circuit device: A package (10) includes an integrated circuit device (12) having an electrically active surface (16) and an opposing backside surface (14). A dielectric molding resin (26) at least partially encapsulates the integrated circuit die and the plurality of electrically conductive leads (20) with the backside surface (14) and the plurality... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20070145551 - Semiconductor package and manufacturing method therefor: A semiconductor package that has a superior high frequency characteristics and that can obtain a large area for an internal wiring pattern is provided. According to the present invention, a semiconductor package includes: a multilayer printed wiring board 12, and an IC chip, mounted on the obverse face of the... Agent: Robert L. Williams IBM Corporation, Dept. 917

20070145553 - Flip-chip mounting substrate and flip-chip mounting method: A solder resist and a central pad to which a central Au bump provided on a semiconductor chip is flip-chip bonded are formed on a substrate main body. In a flip-chip mounting substrate where an underfill resin is provided after the semiconductor chip is mounted, a central opening portion for... Agent: Rankin, Hill, Porter & Clark LLP

20070145549 - Hermetically sealed integrated circuits and method: A semiconductor device includes an integrated circuit die, wherein a layer of photoresist is permanently disposed on and permanently hermetically seals an active circuit area of a top surface of the inductor die. In one embodiment, the semiconductor device includes a lead frame including a conductive pad and a plurality... Agent: Texas Instruments Incorporated

20070145557 - Method for fabricating a semiconductor device and semiconductor device: The present invention discloses a method for fabricating a semiconductor device, comprising: providing a translucent portion; forming a covering layer comprised of one or more metals on the translucent portion by vapor deposition; providing kinetic energy to the covering layer for forming a periodic mask; forming a periodic structure on... Agent: Yokoi & Co., U.s.a., Inc.

20070145550 - Microelectronic elements with compliant terminal mountings and methods for making the same: A dielectric structure is formed by a molding process, so that a first surface of a dielectric structure is shaped by contact with the mold. The opposite second surface of the dielectric structure is applied onto the front surface of a wafer element. The dielectric layer may include protruding bumps... Agent: Tessera Lerner David Et Al.

20070145552 - Semiconductor component including semiconductor chip and method for producing the same: A semiconductor component includes at least one semiconductor chip arranged on a mounting substrate and connected thereto via bonding wires. For effective dissipation of heat, a solderable interlayer is arranged on the active upper side of the semiconductor chip and a heat sink is soldered onto the solderable interlayer. A... Agent: Edell, Shapiro & Finnan, LLC

20070145559 - Semiconductor device: In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070145554 - Semiconductor device and its manufacture method capable of preventing short circuit of electrodes when semiconductor device is mounted on sub-mount substrate: A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first surface. Openings are formed through the levee... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070145555 - Semiconductor structure with a plastic housing and separable carrier plate: A semiconductor structure includes: a carrier plate; a thermosensitive adhesive coupled to a top surface of the carrier plate, which is removable from the carrier plate at a predetermined, defined temperature at which the thermosensitive adhesive loses its adhesive action; semiconductor chips having active top surfaces and back surfaces, where... Agent: Edell, Shapiro & Finnan, LLC

20070145548 - Stack-type semiconductor package and manufacturing method thereof: A stack-type semiconductor package includes a first semiconductor package upon which a second semiconductor package is stacked. A layer of a hardened, insulative material, e.g., a no-flow underfill (NUF) material, is disposed between, and mechanically couples the stacked first and second semiconductor packages. The NUF layer covers portions of the... Agent: Gunnison Mckay & Hodgson, LLP Garden West Office Plaza, Suite 220

20070145558 - Super high density module with integrated wafer level packages: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment,... Agent: Whyte Hirschboeck Dudek S.c.

20070145556 - Techniques for packaging multiple device components: Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dices coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant.... Agent: Michael G. Fletcher Fletcher Yoder

20070145561 - Electronic carrier board and package structure thereof: An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove... Agent: Edwards Angell Palmer & Dodge LLP

20070145560 - Packaged chip having features for improved signal transmission on the package: A packaged chip is provided which includes a package element on which a signal-bearing conductive trace has an edge laterally adjacent to an edge of a reference conductive trace (e.g., ground trace) on the same face of a dielectric element, the two traces together functioning as a capacitor. In a... Agent: Tessera Lerner David Et Al.

20070145562 - Method and system for increasing circuitry interconnection and component capacity in a multi-component package: A method and system for fabricating a interconnect substrate for a multi-component package is disclosed. The multi-component package includes at least one die and a package substrate. The method and system include providing an insulating base and providing at least one conductive layer. The at least one conductive layer provides... Agent: Sawyer Law Group LLP

20070145563 - Stacked packages with interconnecting pins: A system may include a first integrated circuit package including a first integrated circuit die and a first integrated circuit package substrate defining a first plurality of openings, a second integrated circuit package including a second integrated circuit die and a second integrated circuit package substrate defining a second plurality... Agent: Buckley, Maschoff & Talwalkar LLC

20070145566 - Method and system of tape automated bonding: A tape automated bonding (TAB) structure which includes a flex tape having a conductive lead pattern formed thereon. The conductive lead pattern includes a plurality of leads configured to form an inner lead bond (ILB) portion of the TAB structure. At least one of the plurality of leads is internally... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070145565 - Semiconductor chip and semiconductor device: A semiconductor chip according to the present invention is a semiconductor chip having a circuit forming region, in which an internal circuit including a function element is formed, on the middle portion of the surface thereof, and having the surface thereof opposed to and joined to the surface of a... Agent: Rabin & Berdo, PC

20070145564 - Sequential fabrication of vertical conductive interconnects in capped chips: A method is provided of forming a capped chip which includes a conductive interconnect exposed through an opening in the cap. A cap having openings extending between outer and inner surfaces is aligned and joined to a chip. A mass of fusible conductive material is positioned through a first such... Agent: Tessera Lerner David Et Al.

20070145567 - Seal ring structures with unlanded via stacks: Techniques for an integrated circuit device are provided. The integrated circuit device includes a semiconductor substrate, an integrated circuit, a dielectric layer, and a sealing structure. The sealing structure surrounds the integrated circuit and is disposed within the dielectric layer to prevent damage to the integrated circuit. The sealing structure... Agent: Townsend And Townsend And Crew, LLP

20070145568 - Multi-layer interconnection circuit module and manufacturing method thereof: The present invention is directed to a multi-layer interconnection circuit module in which plural unit wiring layers are interlayer-connected to each other through a large number of via holes so that they are laminated and formed, wherein respective unit wiring layers (8) to (12) are adapted so that photo-lithographic processing... Agent: Robert J. Depke Lewis T. Steadman

20070145569 - Image sensor module with passive component: An image sensor module with passive component includes a flexible print circuit board having an upper surface, which is formed with a plurality of electrically circuits, and a lower surface. At least a passive component is arranged on the upper surface of the flexible circuit board. A substrate has a... Agent: Pro-techtor International Services

20070145570 - Semiconductor device: A semiconductor device has an improved mounting reliability and has external terminals formed by exposing portions of leads from a back surface of a resin sealing member. End portions on one side of the leads are fixed to a back surface of a semiconductor chip, and portions of the leads... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070145571 - Semiconductor package structure with constraint stiffener for cleaning and underfilling efficiency: A semiconductor package structure with a heat dissipating stiffener and method of fabricating the same are provided. In one embodiment, the package structure comprises a substrate having a front side and a back side; a semiconductor chip mounted on the front surface of the substrate; a thermally-conductive stiffener mounted over... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070145572 - Heat dissipation device: A heat dissipation device (1) includes a heat sink (10), a fan (20), and a cooling member (30). The heat sink includes a base, a plurality of fins extending from the base and at least one heat pipe thermally connecting the base and the fins. The cooling member is provided... Agent: North America Intellectual Property Corporation

20070145573 - Semiconductor device and method for producing the same: A semiconductor device (1) has a semiconductor component (2), a first electrode (6) and a control electrode (7) being arranged on the top side (4). The semiconductor device (1) furthermore has a circuit carrier (3) having a chip island (9) and a plurality of flat conductors (10). The rear side... Agent: Baker Botts, L.L.P.

20070145574 - High performance reworkable heatsink and packaging structure with solder release layer and method of making: A method of making and a high performance reworkable heatsink and packaging structure with solder release layer are provided. A heatsink structure includes a heatsink base frame. A selected one of a heatpipe or a vapor chamber, and a plurality of parallel fins are soldered to the heatsink base frame.... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070145578 - Multi-chip package sharing temperature-compensated self-refresh signal and method thereof: A multi-chip package sharing a temperature-compensated self-refresh (TCSR) signal and method thereof is disclosed. The multi-chip package may include a plurality of chips. At least one of the plurality of chips may generate a TCSR signal. A remainder of the plurality of chips may be configured to receive the TCSR... Agent: Harness, Dickey & Pierce, P.L.C

20070145577 - Structure with semiconductor chips embeded therein and method of fabricating same: An embedded semiconductor chip structure and a method for fabricating the same are proposed. The structure comprises: a carrier board, therewith a plurality of through openings formed in the carrier board, and through trenches surrounding the through openings in the same; a plurality of semiconductor chips received in the through... Agent: Sawyer Law Group LLP

20070145575 - Circuit board and method for mounting chip component: A circuit board includes a substrate including electrode patterns formed thereon, first chip components mounted on the substrate and a second chip component mounted on a side of electrodes of the first chip components opposite from the substrate. The second chip component is bonded at one electrode to an electrode... Agent: Wenderoth, Lind & Ponack L.L.P.

20070145576 - Power semiconductor circuit and method of manufacturing a power semiconductor circuit: The power semiconductor circuit has a power semiconductor module (2) provided in the form of a flat module. In order to utilize the design possibilities resulting therefrom and to provide a power semiconductor circuit that has an automatable production and a particularly space-saving design, the flat module, with its substrate... Agent: Baker Botts L.L.P. Patent Department

20070145580 - Semiconductor device: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the... Agent: Miles & Stockbridge PC

20070145579 - Semiconductor device and method of manufacturing the same: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center... Agent: Wagner, Murabito & Hao LLP

20070145581 - Control unit: A control unit having a package in which at least a part of components of a control system controlling specified controlling objects is housed, wherein a pair of protrusions is provided on each of opposite side surfaces of the package, and supporting members which operate as a vibration proof material... Agent: Pearne & Gordon LLP

20070145582 - Vertical power semiconductor component, semiconductor device and methods for the production thereof: A vertical power semiconductor component (1) having a top side (3) and a rear side (4) is provided. The top side (3) has at least one first electrode contact area (8) and at least one control electrode area (9) and the rear side (4) has a second electrode contact area... Agent: Ralf Otremba

20070145583 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: multiple kinds of interlayer insulating films formed on a semiconductor substrate and having different elastic moduli, respectively; a metal pad arranged on said multiple kinds of interlayer insulating films; the interlayer insulating film of a low elastic modulus having the lowest elastic modulus and having an... Agent: Mcdermott Will & Emery LLP

20070145584 - Printed wiring board, method for manufacturing same, and circuit device: The printed wiring board comprises, on at least one surface of an insulating film, a base metal layer and a conductive metal layer formed on the base metal layer, and is characterized in that in a section of the wiring board the bottom width of the conductive metal layer is... Agent: The Webb Law Firm, P.C.

20070145585 - Conductive particles for anisotropic conductive interconnection: e

20070145586 - Metal thin film for interconnection of semiconductor device, interconnection for semiconductor device, and their fabrication method: More specifically, a metal thin film for use as an interconnection of a semiconductor device comprising a Cu alloy containing N at a content of not less than 0.4 at % to not more than 2.0 at %; and an interconnection for a semiconductor device fabricated by forming the metal... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070145588 - Method for fabricating a metal interconnection using a dual damascene process and resulting semiconductor device: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films... Agent: Sherr & Nourse, PLLC

20070145590 - Semiconductor device and manufacturing method of the same: This invention provides a semiconductor device that solves a problem that a pattern of a wiring formed on a back surface of a semiconductor substrate is reflected on an output image. A light receiving element (e.g. a CCD, an infrared ray sensor, a CMOS sensor, or an illumination sensor) is... Agent: Morrison & Foerster LLP

20070145591 - Semiconductor device and manufacturing method therof: The semiconductor device manufacturing method includes the steps of: applying a first wire including a barrier metal film, a seed film, and a wiring material film in a first wire trench formed in a first interlayer dielectric film; after a second interlayer dielectric film is formed on the first interlayer... Agent: Mcdermott Will & Emery LLP

20070145589 - Semiconductor device and method of forming intermetal dielectric layer: There is provided a semiconductor device in which extension units are formed in the ends of a slit that constitutes a slit pattern to relieve stress transmitted between interconnect layers. The embodiments relate to a semiconductor device which includes a first metal layer included on a semiconductor substrate, an interlayer... Agent: Sherr & Nourse, PLLC

20070145587 - Substrate with multi-layer interconnection structure and method of manufacturing the same: The invention provides a substrate with multi-layer interconnection structure, which includes a substrate and a multi-layer interconnection structure formed on the substrate. The multi-layer interconnection structure is adhered to the substrate in partial areas. The invention also provides a method of manufacturing and recycling such substrate and a method of... Agent: Pai Patent & Trademark Law Firm

20070145592 - Semiconductor device and method of manufacturing the same: Provided are a semiconductor device and a method for manufacturing the same. The method can include: forming a gate electrode and a source/drain region on a semiconductor substrate; forming a pre metal dielectric insulation layer on the semiconductor substrate, the pre metal dielectric insulation layer including a first insulation layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145593 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate, the interlayer dielectric layer having a hole with a taper angled at the hole's upper portion; a diffusion... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145594 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a first metal layer formed on a semiconductor substrate and an interlayer insulating layer formed on the first metal layer, wherein a via hole is formed in the interlayer insulating layer. The semiconductor device further includes a second metal filled into the via hole at a... Agent: Mayer, Brown, Rowe & Maw LLP

20070145595 - High speed interconnect: In some embodiments a high speed interconnect includes a layer of FR4 material, a trench in the layer of FR4 material, and a pair of transmission lines located near the trench. The trench is filled with a homogenous material. Other embodiments are described and claimed.... Agent: Intel Corporation C/o Intellevate, LLC

20070145597 - Semiconductor device and method for manufacturing the same: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, the semiconductor device may include a semiconductor substrate formed with a metal interconnection, a first interlayer dielectric layer formed on the metal interconnection and having a first contact plug, a second interlayer dielectric layer... Agent: Sherr & Nourse, PLLC

20070145601 - Forming ultra dense 3-d interconnect structures: Methods of forming a microelectronic structure are described. Embodiments of those methods include bonding at least one bond pad of a device side of a first substrate to at least one bond pad of a device side of a second substrate, forming at least one via to connect to at... Agent: Blakely Sokoloff Taylor & Zafman

20070145596 - Interconnect structure and method of fabricating same: An improved interconnect structure and method of making such a device The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process.... Agent: Slater & Matsil, L.L.P.

20070145599 - Metal-insulator-metal (mim) capacitor and methods of manufacturing the same: A method of manufacturing a Metal-Insulator-Metal (MIM) capacitor and an MIM capacitor formed by the method are described. The method comprises sequentially forming a dielectric film and an interlayer insulating film on a silicon substrate on which lower copper wiring is formed, forming via holes by selectively etching the interlayer... Agent: Mayer, Brown, Rowe & Maw LLP

20070145598 - Method of forming a metal interconnection in a semiconductor device: A method includes at least one of: forming a metal interconnection in a semiconductor device; forming an inter-metal dielectric layer over a substrate and/or a lower metal layer; forming a photoresist pattern over an inter-metal dielectric layer; forming a via hole by selectively etching an inter-metal dielectric layer using a... Agent: Sherr & Nourse, PLLC

20070145600 - Semiconductor device and manufacturing method thereof: A semiconductor device includes an embedded wire in a first wire trench formed in a first interlayer dielectric film, the embedded wire having a barrier metal, a first seed film, a second seed film, and a copper film. The first seed film is formed by a copper film containing metal,... Agent: Mcdermott Will & Emery LLP

20070145602 - Structure combining an ic integrated substrate and a carrier, and method of manufacturing such structure: The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The interface between the IC integrated substrate and the carrier has a specific area at which the interface adhesion is different from that... Agent: Pai Patent & Trademark Law Firm

20070145603 - Semiconductor chip, mounting structure thereof, and methods for forming a semiconductor chip and printed circuit board for the mounting structure thereof: A semiconductor chip for flip chip bonding, a mounting structure for the semiconductor chip, and methods for forming a semiconductor chip for flip chip bonding and for fabricating a printed circuit board for a mounting structure of a semiconductor chip are provided which may improve connection between a solder bump... Agent: Harness, Dickey & Pierce, P.L.C

20070145604 - Chip structure and chip manufacturing process: A chip manufacturing process is disclosed. A wafer having a passivation layer and at least one bonding pad is provided. The surface of the bonding pad is exposed to a first opening of the passivation layer. A first metal layer is formed on the bonding pad exposed by the first... Agent: J C Patents, Inc.

20070145605 - Chip packaging structure without leadframe: A chip packaging structure without leadframe includes a bare chip having one surface provided with a plurality of contacts, and an adhesive and a fixing layer sequentially attached to the surface of the bare chip with the contacts, and a plurality of lead wires sandwiched between the adhesive and the... Agent: Rosenberg, Klein & Lee

20070145606 - Semiconductor device with semiconductor device components embedded in a plastic housing composition: A semiconductor device includes semiconductor device components, an adhesion promoter structure and a plastic housing composition. The semiconductor device components are embedded in the plastic housing composition with the adhesion promoter structure being disposed between the device components and the housing composition. The adhesion promoter structure includes first and second... Agent: Edell, Shapiro & Finnan, LLC

20070145607 - System to wirebond power signals to flip-chip core: A system may include an integrated circuit die defining a plurality of inner apertures, and a conductive element disposed on two or more of the plurality of inner apertures and electrically connected to an electrical conductor through the two or more inner apertures. In some embodiments, the integrated circuit die... Agent: Buckley, Maschoff & Talwalkar LLC

20070145608 - Cmos image sensor and method of fabricating the same: Provided is a method of fabricating a CMOS image sensor. According to an embodiment method, an insulating layer can be formed on a semiconductor substrate, and a metal pad can be formed on the insulating layer. A first overcoat layer can be formed on the insulating layer including the metal... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070145609 - Semiconductor package having improved thermal performance: A composite semiconductor package is disclosed. The package includes a lead frame having first and second die bonding pads, the first and second die bonding pads having a large lateral separation therebetween, a first device bonded to the first die bonding pad, a second device bonded to the second die... Agent: Fortune Law Group LLP

20070138480 - Semiconductor display device and manufacturing method thereof: A highly reliable semiconductor display device is provided. The semiconductor display device has a channel forming region, an LDD region, and a source region and a drain region in a semiconductor layer, and the LDD region overlaps with a first gate electrode, sandwiching a gate insulating film.... Agent: Fish & Richardson P.C.

20070138481 - Thin film transistor array panel and manufacturing method thereof: Gate lines are formed on a substrate. A gate insulating layer, a semiconductor layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited, and the upper film and the lower film are patterned to form... Agent: Cantor Colburn, LLP

20070138476 - Thin film transistor array substrate and fabricating method thereof: A thin film transistor array substrate is provided. The thin film transistor array substrate includes a substrate; a gate pattern of a gate electrode and a gate line connected to the gate electrode on the substrate; a main gate insulating film formed of an organic material to cover the gate... Agent: Morgan Lewis & Bockius LLP

20070138482 - Silicon carbide semiconductor device and method for producing the same: A silicon carbide semiconductor device, includes: 1) a silicon carbide substrate; 2) a silicide electrode configured to be formed by depositing a contact parent material on the silicon carbide substrate in such a manner as to cause a solid phase reaction, the silicide electrode being a lower carbon content silicide... Agent: Foley And Lardner LLP Suite 500

20070138519 - Production process for a semiconductor component with a praseodymium oxide dielectric: The invention concerns a semiconductor component and an associated production process having a silicon-bearing layer, a praseodymium oxide layer and a mixed oxide layer arranged between the silicon-bearing layer and the praseodymium oxide layer and containing silicon, praseodymium and oxygen. It is possible because of the mixed oxide layer on... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070138527 - Access transistor for memory device: An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.... Agent: Dickstein Shapiro LLP

20070138525 - Mechanical memory device and method of manufacturing the same: A memory device that performs writing and reading operations using a mechanical movement of a nanowire, and a method of manufacturing the memory device are provided. The memory device includes a source electrode, a drain electrode, and a gate electrode, each of which is formed on an insulating substrate. A... Agent: Robert E. Bushnell

20070138526 - Pitch reduced patterns relative to photolithography features: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the... Agent: Knobbe Martens Olson & Bear LLP

20070138544 - Field plate trench transistor and method for producing it: A field plate trench transistor having a semiconductor body is disclosed. In one embodiment, the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070138546 - Semiconductor device: A semiconductor device includes: a semiconductor layer, a first semiconductor region provided on a major surface of the semiconductor layer, a second semiconductor region provided in a surface portion of the first semiconductor region, a trench extending through the second semiconductor region and the first semiconductor region to the semiconductor... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070138545 - Semiconductor device having a trench gate and method of fabricating the same: A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped... Agent: Quintero Law Office, PC

20070138547 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a semiconductor region of the first conduction type. A first main electrode is connected to the semiconductor region. A base region of the second conduction type is formed on the semiconductor region. A diffused region of the first conduction type is formed on the base region.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070138548 - Power ldmos transistor: A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is... Agent: Duane Morris, LLPIPDepartment

20070138549 - Gate layouts for transistors: A transistor and a method of fabricating the transistor are provided. The transistor includes a semiconductor material comprising drain regions and source regions formed in alternating rows or columns. The transistor also includes polysilicon chains overlaying the top of the semiconductor material, disconnected from and substantially parallel to one another,... Agent: Sawyer Law Group LLP

20070138550 - Semiconductor device and method for manufacturing semiconductor device: Semiconductor device exhibiting higher breakdown voltage and method for manufacturing the same. A power MOSFET includes: a p-type first base region; a p-type second base region, formed in the first base region and containing a higher impurity concentration than the first base region; and an n-type source region, formed in... Agent: Young & Thompson

20070138551 - High voltage semiconductor device and method for fabricating the same: There is provided a high voltage semiconductor device comprising: a semiconductor substrate of a first conductivity type, including a first region, a second region relatively lower than the first region, and a sloped region between the first region and the second region; a drift region of a second conductivity type,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070138552 - Method to produce high voltage device: A high-voltage semiconductor device includes a silicon substrate having a main surface, a gate on the main surface of the silicon substrate, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070138622 - Electronic device and semiconductor device: An electronic device has a substrate, a conductive layer and a substrate mounted portion. The substrate has a circuit portion used from 60 GHz to 80 GHz. The conductive layer is provided directly on a face of the substrate that is opposite side of the circuit portion. The face having... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070138621 - Low temperature phase change thermal interface material dam: A method, apparatus and system with a semiconductor package including a thermal interface material dam enclosing a volume of thermal interface material.... Agent: Intel Corporation C/o Intellevate, LLC

20070138624 - Semiconductor device: One of the aspects of the present invention is to provide a semiconductor device, which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070138623 - Carbon nanotube micro-chimney and thermo siphon die-level cooling: A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die.... Agent: Intel Corporation C/o Intellevate, LLC

20070131922 - Thin film fuse phase change cell with thermal isolation pad and manufacturing method: A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070131923 - Infrared detector: At least one or more dark current reducing layers having a quantum well structure are provided at an end portion in a stacking direction of an infrared detecting section in which quantum dot layers are stacked.... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070131924 - Nanowire light sensor and kit with the same: Disclosed is a nanowire light sensor using a phenomenon that, resistance of the nanowire is reduced by light with speific wavelength. In addition, provided is a rapid test kit for immunoassay using the nanowire light sensor and an immunoassay principle using chemifluorescence and chemiluminescence. In addition, provided are a nanowire... Agent: Darby & Darby P.C.

20070131929 - Novel imidazoquinazoline derivative, process for preparing the same, and organic electronic device using the same: The present invention relates to a novel imidazoquinazoline derivative, a process for preparing the same, and an organic electronic device using the same. The imidazoquinazoline derivative according to the present invention serves as hole injecting, hole transporting, electron injecting, electron transporting, or a light emitting material in an organic electronic... Agent: Mckenna Long & Aldridge LLP

20070131925 - Organic light-emitting diode: An organic light-emitting diode comprising a substrate having a first opposing surface and a second opposing surface; a first electrode layer overlying the first opposing surface; a lightemitting element overlying the first electrode layer, the light-emitting element comprising a hole-transport layer and an emissive/electron-transport layer, wherein the hole-transport layer and... Agent: Dow Corning Corporation Co1232

20070131928 - Organic light-emitting display device: An organic light-emitting display device includes: a light-emitting element located between a first substrate and a second substrate, and adapted to emit light; a phase difference plate disposed on the first substrate or the second substrate in a path through which the light emitted from the light-emitting element is propagated,... Agent: Christie, Parker & Hale, LLP

20070131926 - Organic thin film transistor and flat display device having the same: An organic thin film transistor in which source and drain electrodes have a double layer structure to aid patterning of an organic semiconductor layer using a laser beam, and a flat display device having the organic thin film transistor. The organic thin film transistor includes: a gate electrode; a source... Agent: Stein, Mcewen & Bui, LLP

20070131927 - Thin film transistor and manufacturing method thereof: An OTFT is formed by forming a pair of recesses, one being a groove and another being groove or a hole. A source electrode is formed by filling one of the recesses. A drain electrode is formed by filling the other one of the recesses. A film of organic semiconductor... Agent: Rossi, Kimms & Mcdowell LLP.

20070131930 - Semiconductor device and method for fabricating the same: The following steps are carried out: forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween, forming a dummy gate electrode on the semiconductor substrate with a dummy gate insulating film interposed therebeweeen and forming another dummy gate electrode on the semiconductor substrate with an... Agent: Mcdermott Will & Emery LLP

20070131931 - Semiconductor wafer and semiconductor device, and method for manufacturing same: There is a room for improvement in conventional semiconductor devices in terms of reducing the chip area. A semiconductor device 1 comprises an evaluation transistor 10 (first characteristic evaluation device), an evaluation transistor (second characteristic evaluation device), measurement pads 30 (first measurement pads) and measurement pads 40 (second measurement pads).... Agent: Mcginn Intellectual Property Law Group, PLLC

20070131932 - Static electricity preventing assembly for display device and method of manufacturing the same: A static electricity preventing assembly for an electronic device, may include a substrate, a buffer layer on the substrate, the buffer layer including a plurality of contact holes exposing respective regions of the substrate, a shorting bar on the buffer layer, pad electrodes on the buffer layer, metal wiring lines... Agent: Lee & Morse, P.C.

20070131933 - Polycrystalline silicon layer, flat panel display using the same, and methods of fabricating the same: A polycrystalline silicon layer, a flat panel display using the polycrystalline silicon layer, and methods of fabricating the same are provided. An amorphous silicon layer is formed on a substrate. A first pattern layer, a second pattern layer, and a metal catalyst layer are formed on the amorphous silicon layer.... Agent: Robert E. Bushnell

20070131934 - Polycrystalline silicon layer, flat panel display using the same, and method of fabricating the same: A polycrystalline silicon layer, a flat panel display using the polycrystalline silicon layer, and a method of fabricating the same are provided. The polycrystalline silicon layer is formed by crystallizing a seed region of an amorphous silicon layer using a super grain silicon (SGS) crystallization technique. The crystallinity of the... Agent: Robert E. Bushnell

20070131935 - Capacitor and method of manufacturing same: A capacitor comprises: a lower electrode formed of a foil made of a polycrystalline metal; an upper conductor layer; and a dielectric layer disposed between the lower electrode and the upper electrode layer. Grain boundaries of the polycrystalline metal appear at the top surface of the lower electrode. The capacitor... Agent: Oliff & Berridge, PLC

20070131937 - Display device and method of manufacturing thereof: According to an embodiment of the present invention, a display device includes a substrate, at least one nano-emitting body disposed on the substrate where each nano-emitting body includes at least one shell and has a coaxial structure, at least one light source disposed on at least one of a lower... Agent: Macpherson Kwok Chen & Heid LLP

20070131936 - Liquid crystal display device and fabricating method thereof: A liquid crystal display panel and a fabricating method thereof comprising an image sensing capability, image scanning, and touch inputting. In the liquid crystal display device, a gate line and a data line are formed to intersect each other on a substrate to define a pixel area in which a... Agent: Mckenna Long & Aldridge LLP

20070131938 - Merged and isolated power mesfet devices: A first type of merged power MESFET device includes two monolithically integrated MESFETS. The MESFETS share common sources and gates, and are sized so that one MESFET may be used as a power device while the other is used as a current-sense device. A second type of merged power MESFET... Agent: Advanced Analogic Technologies

20070131942 - Ac light emitting assembly and ac light emitting device: An alternating current (AC) light emitting assembly and an AC light emitting device are disclosed. The AC light emitting assembly includes a substrate; a rectifier unit comprising a plurality of rectifier components arranged in a Wheatstone Bridge, for rectifying an AC signal into a direct current (DC) signal, each of... Agent: Wpat, PC Intellectual Property Attorneys

20070131943 - Active matrix electroluminescence device having a metallic protective layer and method for fabricating the same: An active matrix electroluminescence display device and a method for fabricating the same, whereby damage caused by UV light rays during the fabrication process can be prevented, are disclosed. The active matrix electroluminescence display device includes a plurality of transistors formed on a substrate having an emissive area and a... Agent: Ked & Associates, LLP

20070131940 - Color-mixing led: A color-mixing LED is disclosed. Fluorescent powders are mixed with an adhesive to form a thin plate. A segmentation process is then performed on the thin plate. A chip is coupled to a concave bracing frame, and then the segmented thin plate is mounted in the concave bracing frame against... Agent: Troxell Law Office PLLC

20070131941 - Light emitting device having high optical output efficiency: A light emitting device includes a lower semiconductor layer of a first conductivity type; an optical emission layer formed on said lower semiconductor layer; an upper semiconductor layer of a second conductivity type opposite to said first conductivity type, said upper semiconductor layer being formed on said optical emission layer;... Agent: Masao Yoshimura Chen Yoshimura LLP

20070131939 - Semiconductor laser and method for manufacturing the same: A semiconductor lamination portion (9) including an active layer (4) is formed on a substrate (1). The semiconductor lamination portion is made of, for example, a nitride material having a cleavage plane not parallel to a cleavage plane of the substrate (1) and has a resonance cavity end faces (6)... Agent: Rabin & Berdo, PC

20070131944 - Dual organic electroluminescent display and method of making same: A dual display unit comprising two OLED displays separately fabricated on two substrates. Each of the substrates has a peripheral area surrounding the respective display. A getter element is provided on one or both peripheral areas, substantially surrounding both the displays, for absorbing harmful gaseous elements in the display unit.... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070131945 - Light-emitting semiconductor device with open-bypass function: This invention discloses a light-emitting semiconductor device with open-bypass function, which comprises two terminals providing a current, at least one LED unit and a bypass switch. Electrodes of the LED unit and the bypass switch are properly connected to the terminals, so that the bypass switch will provide an alternative... Agent: Crockett & Crockett

20070131946 - Self-aligning optical sensor package: One embodiment relates to an optical navigation device. The device includes a lead frame having reference features, a laser, a detector array, and an optical component having alignment features. The laser is attached to the lead frame and positioned in reference to the reference features of the lead frame. The... Agent: Okamoto & Benedicto, LLP

20070131947 - Light-emitting device: A light-emitting device is provided. The light-emitting device includes a first conductive cladding layer, an active layer, a second conductive cladding layer, a second conductive electrode, and a short block barrier. The first conductive cladding layer is on a substrate. The active layer is on the first conductive cladding layer.... Agent: Birch Stewart Kolasch & Birch

20070131948 - Light emitting device: Light-emitting elements have a problem that their light-extraction efficiency is low due to scattered light or reflected light inside the light-emitting elements. The light-extraction efficiency of the light-emitting elements needs to be enhanced by a new method. According to the present invention, a light-emitting element includes a first layer generating... Agent: Eric Robinson

20070131949 - Color tunable light-emitting devices and method of making the same: A color tunable light-emitting device is provided which comprises a first light-emitting element, a second light-emitting element, an active light transformative element disposed between the first light-emitting element and the second light-emitting element; and at least one light transmissive element, wherein the first and second light-emitting elements emit light at... Agent: Andrew J. Caruso General Electric Global Research

20070131950 - Light emitting element array and image forming apparatus: A light emitting element array including an active layer commonly used for light emitting element regions, carrier injection layers which are electrically isolated from each other and which are provided in the respective light emitting element regions, and a resistive layer which has a resistance higher than that of the... Agent: Fitzpatrick Cella Harper & Scinto

20070131951 - Light-emitting element and making method thereof: A light-emitting element having: a gallium oxide substrate on a front surface of which a crystal of a semiconductor material having a light-emitting element part is grown; and a substrate protection layer formed on a back surface of the gallium oxide substrate. A method of making a light-emitting element having... Agent: Mcginn Intellectual Property Law Group, PLLC

20070131953 - Nitride semiconductor light emitting device and method for fabricating the same: Disclosed is a nitride semiconductor light emitting device. The nitride semiconductor light emitting device comprises a buffer layer having a super-lattice layer on a silicon substrate, a first conductive clad layer on the buffer layer, an active layer on the first conductive clad layer, and a second conductive clad layer... Agent: Birch Stewart Kolasch & Birch

20070131952 - Semiconductor device integrated with heat sink and method of fabricating the same: The present invention is to provide a semiconductor device which includes a mounting base and a light-emitting device. The mounting base includes a substrate of a first semiconductor material and a first layer of a material with high thermal conductivity formed over the substrate. Furthermore, the light-emitting device is a... Agent: Birch Stewart Kolasch & Birch

20070131954 - Light emitting device: A light emitting device comprises a light emitting element, and a light conversion member including a phosphor material that is capable of absorbing light emitted from the light emitting element at least partially and emitting light in different wavelength. The light emitting device further comprises a heat dissipation member in... Agent: Ditthavong Mori & Steiner, P.C.

20070131955 - Optical transceiver module: Provided is an optical transceiver module of an optical transceiver, which is used for optical communications. The optical transceiver module prevents electrical crosstalk between a light source and a light receiver. Additionally, the optical transceiver module includes an optical transceiver unit including a light source and a light receiver together... Agent: Ladas & Parry LLP

20070131956 - Reflection efficiency improved light emitting element: A reflection efficiency improved light emitting element comprises a first electrode and a second electrode respectively provided on the partial surface of the first material layer and the second material layer of a light emitting diode; a light transparent electrical conductive layer provided on the partial surface of the second... Agent: Rosenberg, Klein & Lee

20070131957 - Radiation-emitting and/or radiation-receiving semiconductor component and method for the production thereof: A radiation-emitting and/or radiation-receiving semiconductor component comprising a radiation-emitting and/or radiation-receiving semiconductor chip, a molded plastic part which is transparent to an electromagnetic radiation to be emitted and/or received by the semiconductor component and by which the semiconductor chip is at least partially overmolded, and external electrical leads that are... Agent: Fish & Richardson PC

20070131958 - Single chip with multi-led: A single chip with multi-LED comprises a substrate on which an N-type semiconductor layer, an active layer and a P-type semiconductor layer are successively stacked. At least one N-type electrode is connected to the N-type semiconductor layer, and is exposed to an opening through the active layer and the P-type... Agent: Oliff & Berridge, PLC

20070131961 - Alingap led having reduced temperature dependence: To increase the lattice constant of AlInGaP LED layers to greater than the lattice constant of GaAs for reduced temperature sensitivity, an engineered growth layer is formed over a substrate, where the growth layer has a lattice constant equal to or approximately equal to that of the desired AlInGaP layers.... Agent: Patent Law Group LLP

20070131959 - Compound semiconductor light-emitting device having pn-junction type hetero structure and forming method thereof: A pn-heterojunction compound semiconductor light-emitting device includes a crystalline substrate 101, a lower cladding layer 102 formed on a surface of the crystalline substrate and composed of an n-type Group III-V compound semiconductor, a light-emitting layer 103 formed on a surface of the lower cladding layer and composed of an... Agent: Sughrue Mion, PLLC

20070131962 - Display panel and method for manufacturing the same: A display panel includes an insulating substrate, a pixel portion, a gate driver circuit portion, and a drain driver circuit portion. The pixel portion, gate driver circuit portion and drain driver circuit portion are formed out of thin film transistors on the insulating substrate, and the thin film transistors forming... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070131960 - Nitride semiconductor laser element and fabrication method thereof: On a nitride semiconductor layered portion formed on a substrate, there are formed an insulating film and a p-side electrode in this order. Furthermore, an end portion electrode protection layer is formed above the p-side electrode, around a position where cleavage will take place.... Agent: Harness, Dickey & Pierce, P.L.C

20070131963 - Thyristor which can be triggered electrically and by radiation, and methods for making contact with it: A thyristor has a radiation-sensitive breakdown structure (20), a gate electrode (92) that is placed at a distance from the latter in a lateral direction and an ignition stage structure having at least one ignition stage (51, 91) equipped with an n-doped auxiliary emitter (51), which forms a pn-junction (55)... Agent: Baker Botts, L.L.P.

20070131964 - Semiconductor device and method for manufacturing the same: Embodiments relate to a semiconductor device and a method of manufacturing the same. According to embodiments, a semiconductor device may include a gate insulating layer and a gate electrode formed on a semiconductor substrate with an isolation layer, a low-density junction region formed at both sides of the gate electrode,... Agent: Sherr & Nourse, PLLC

20070131965 - Triple-well low-voltage-triggered esd protection device: An ESD protection device with a silicon controlled rectifier (SCR) structure which is applied to a nano-device-based high-speed I/O interface circuit and semiconductor substrate operated by a low power voltage. The triple-well low-voltage-triggered ESD protection device includes: a deep n-type well formed on a p-type substrate; n- and p-type wells... Agent: Mayer, Brown, Rowe & Maw LLP

20070131966 - Programmable memory cell in an integrated circuit chip: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070131967 - Self-standing gan single crystal substrate, method of making same, and method of making a nitride semiconductor device: A self-standing gallium nitride-based semiconductor single crystal substrate has a surface (Ga-face) mirror-polished, and a rear surface (N-face) having an arithmetic mean roughness Ra of 1 micrometer or more and 10 micrometers or less. A nitride semiconductor device is fabricated such that, before the gallium nitride-based semiconductor single crystal substrate... Agent: Foley And Lardner LLP Suite 500

20070131968 - Field effect transistor: A material of a gate electrode is a conductive oxide having a higher work function than that of conventionally used Pd and so on, thereby achieving a normally-off transistor without reducing the sheet carrier concentration of a heterojunction. It is thus possible to achieve a normally-off operation while reducing an... Agent: Steptoe & Johnson LLP

20070131969 - Semiconductor device and method of manufacturing the same: On a semiconductor substrate having a lamination structure in which Si and SiGe are stacked together, a gate electrode is formed, with a gate insulating film interposed between the semiconductor substrate and the gate electrode. Further, a channel region is provided in a surface of the semiconductor substrate, which is... Agent: Foley And Lardner LLP Suite 500

20070131970 - Silicon nitride passivation with ammonia plasma pretreatment for improving reliability of aigan/gan hemts: This invention pertains to an electronic device and to a method for making it. The device is a heterojunction transistor, particularly a high electron mobility transistor, characterized by presence of a 2 DEG channel. Transistors of this invention contain an AlGaN barrier and a GaN buffer, with the channel disposed,... Agent: Naval Research Laboratory Associate Counsel (patents)

20070131971 - Hetero junction bipolar transistor and method of manufacturing the same: Provided are a hetero-junction bipolar transistor (HBT) that can increase data processing speed and a method of manufacturing the hetero-junction bipolar transistor. The HBT includes a semi-insulating compound substrate, a sub-collector layer formed on the semi-insulating compound substrate, a pair of collector electrodes disposed at a predetermined distance apart from... Agent: Ladas & Parry LLP

20070131973 - Flash memory device and method of manufacturing the same: Disclosed is a flash memory device. The flash memory device includes a plurality of trench lines in an isolation region of a semiconductor device, a common source region along a word line (WL) direction under a surface portion of the semiconductor substrate, a plurality of gate lines along a vertical... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070131972 - Semiconductor devices and methods of manufacture thereof: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of... Agent: Slater & Matsil LLP

20070131974 - Solid-state imaging device: A solid-state imaging device includes a transfer element line for transferring an electric charge that is photoelectrically converted in a photoelectric conversion element line formed of a plurality of photoelectric conversion elements, and a charge detector for detecting an electric charge that is transferred by the transfer element line. The... Agent: Young & Thompson

20070131975 - Field effect transistor: A transistor has a source electrode (22) on the opposite side of a semiconductor body layer (10) to a gate electrode (4) insulated from the body layer (10) by gate insulator (8). The source electrode (22) has a potential barrier to the semiconductor body layer (10), for example a Schottky... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070131976 - Semiconductor element, method for manufacturing the same, liquid crystal display device, and method for manufacturing the same: In case that a conventional TFT is formed to have an inversely staggered type, a resist mask is required to be formed by an exposing, developing, and droplet discharging in forming an island-like semiconductor region. It resulted in the increase in the number of processes and the number of materials.... Agent: Nixon Peabody, LLP

20070131977 - Low dark current photodiode for imaging: A photodiode and method of forming a photodiode has a substrate. An absorption layer is formed on the substrate to absorb lightwaves of a desired frequency range. A multiplication structure is formed on the absorption layer. The multiplication layer uses a low dark current avalanching material. The absorption layer and... Agent: Weiss & Moy PC

20070131978 - Solid-state imaging device and method for manufacturing the same: Channel stop sections are formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges... Agent: David R. Metzger Sonnenschein Nath & Rosenthal LLP

20070131979 - Nonvolatile semiconductor memory device and method for manufacturing the same: A memory cell array of a NOR type flash memory is constructed by arranging memory cell transistors in a matrix, each of the memory cell transistors includes a contact connecting a semiconductor substrate to an overlayer wire. Columns of the memory cell transistors are isolated from one another by shallow... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070131980 - Vacuum jacket for phase change memory element: A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line electrode in contact with the upper... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070131982 - Memory cell structure and method for fabricating the same: A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers and a gate structure positioned at least... Agent: Oliff & Berridge, PLC

20070131981 - Patterning method and field effect transistors: Patterning method, and field effect transistors An explanation is given of, inter alia, a patterning method, in which a filling material (22) with a T-shaped cross section is used as a mask during patterning in order to produce structures having sublithographic dimensions, in particular a double-fin field effect transistor.... Agent: Brinks Hofer Gilson & Lione Infineon

20070131984 - Semiconductor device and method for fabricating the same: A semiconductor device includes a first MIS transistor of a non-salicide structure and a second MIS transistor of a salicide structure which are both formed on a substrate of silicon. The first MIS transistor includes a first gate electrode of silicon, first sidewalls, a first source and drain, and plasma... Agent: Mcdermott Will & Emery LLP

20070131985 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same are provided, in which the work function of a gate electrode being in contact with a gate insulating film can be efficiently adjusted while depletion of the gate electrode is suppressed. An SOI substrate is composed of a p-type silicon... Agent: Mcdermott Will & Emery LLP

20070131986 - Semiconductor device and method of manufacturing the same: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, a semiconductor device may include an LDD which may include a space having a first width and may be formed in a semiconductor substrate, a channel area which may be formed in the semiconductor... Agent: Sherr & Nourse, PLLC

20070131983 - Tri-gate integration with embedded floating body memory cell using a high-k dual metal gate: Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, and NMOS transistors. An insulative layer is formed overlying the silicon... Agent: Blakely Sokoloff Taylor & Zafman

20070131987 - Vertical image sensor and method for manufacturing the same: Disclosed are a vertical color filter detector group (image sensor) and a method for manufacturing the same, capable of simplifying a manufacturing process by reducing the number of ion implantations and masks for connecting a green sensitive layer and a red sensitive layer to a sensor on a surface of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070131988 - Cmos image sensor devices and fabrication method thereof: CMOS image sensor devices and fabrication methods thereof. A CMOS image sensor device comprises an array of photo-sensing pixels in a first region of a substrate. Each photo-sensing pixel comprises a fully non-salicide transistor and a pinned photodiode. A logic circuit comprises a complementary metal oxide semiconductor (CMOS) transistor in... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070131990 - System for manufacturing flat panel display: A system for manufacturing a flat panel display includes a substrate storage part for storing a plurality of substrates; a first chamber including a substrate loading part for loading the plurality of substrates; a substrate transfer part, disposed between the substrate storage part and the first chamber, including an end... Agent: Bacon & Thomas, PLLC

20070131989 - Thin film transistor array substrate for reducing electrostatic discharge damage: A thin film transistor (TFT) array substrate for reducing electrostatic discharge damage includes a substrate, a plurality of pixel units, scan lines and data lines. The substrate has a pixel area and a peripheral area adjacent to the pixel area. The pixel units are disposed in the pixel area. The... Agent: J.c. Patents, Inc. Suite 250

20070131993 - Imaging device: Adjacent pixels in a pixel circuit of an imaging device use a primary capacitance, an amplifying transistor, a reset switch and a selection switch in common. Each pixel has a photodiode and a transfer switch having first and second gates provided on the photodiode side and the primary capacitance side,... Agent: Crowell & Moring LLP Intellectual Property Group

20070131992 - Multiple photosensor pixel image sensor: A color multiple sensor pixel image sensor includes multiple photo-sensing devices, a combined photosensing and charge storage device, and multiple triggering switches. Each of the multiple photo-sensing devices is structured for conversion of photons of one differentiated color component to photoelectrons. The combined photosensing and charge storage device is structured... Agent: George O. Saile

20070131991 - Solid-state imaging device, line sensor and optical sensor and method of operating solid-state imaging device: A solid-state imaging device, a line sensor and an optical sensor for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio... Agent: Foley And Lardner LLP Suite 500

20070131994 - Ferroelectric memory and method for manufacturing ferroelectric memory: A ferroelectric memory includes a ferroelectric capacitor formed from a lower electrode, an upper electrode and a ferroelectric layer interposed between the lower electrode and the upper electrode; and a metal wiring provided in an interlayer dielectric film, wherein a portion of the metal wiring that may otherwise come in... Agent: Harness, Dickey & Pierce, P.L.C

20070131996 - Non-volatile memory device and fabricating method thereof: The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070131995 - Reduced cell-to-cell shorting for memory arrays: Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The container housing the capacitor is filled with photoresist and then planarized. The TiN layer... Agent: Knobbe Martens Olson & Bear LLP

20070131997 - Semiconductor device and method for fabricating the same: A semiconductor device includes a capacitor formed by successively stacking a lower electrode, a capacitor dielectric film and an upper electrode on a substrate. The lower electrode includes a first conducting layer and a second conducting layer formed on the first conducting layer and having higher resistivity than the first... Agent: Mcdermott Will & Emery LLP

20070131998 - Vertical transistor device and fabrication method thereof: A vertical transistor device and fabrication method thereof are provided, the vertical transistor device comprising a substrate having a deep trench. A capacitor is disposed in a lower portion of the deep trench. A conductive structure is disposed on the capacitor inside the deep trench. An epitaxial layer, having an... Agent: Quintero Law Office, PC

20070131999 - Gated diode nonvolatile memory process: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070132005 - Electrically erasable and programmable read only memories including variable width overlap regions and methods of fabricating the same: An electrically erasable and programmable read only memory (EEPROM) is fabricated by forming isolation patterns defining active regions in predetermined regions of a semiconductor substrate including a memory transistor region and a selection transistor region. A gate insulating layer having tunnel regions is formed on the active regions. A first... Agent: Myers Bigel Sibley & Sajovec

20070132000 - Memory cell and method for manufacturing the same: The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the... Agent: J.c. Patents, Inc.

20070132002 - Method and structure of an one time programmable memory device in an embedded eeprom: A structure and a manufacturing method for an OTP-EPROM in an embedded EEPROM integrated circuit structure. The structure has a substrate that includes a surface region. The structure has a gate dielectric is overlying the surface region. The structure also a first OTP-EPROM gate overlying the gate dielectric layer in... Agent: Townsend And Townsend And Crew, LLP

20070132001 - Non-volatile memory and manufacturing method and operating method thereof: A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of the floating gates... Agent: Jianq Chyun Intellectual Property Office

20070132004 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an example of the present invention includes source/drain diffusion layers, a first insulation film on a channel between the source/drain diffusion layers, a floating gate electrode on the first insulation film and composed of first electrically conductive layers, a second insulation film on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070132003 - Semiconductor memory device: A semiconductor memory device includes a semiconductor substrate, a first insulating film which is formed on the semiconductor substrate, a floating gate electrode which is formed on the first insulating film and made of a conductive metal oxide, a second insulating film which is formed on the floating gate electrode,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070132008 - High voltage integration circuit with freewheeling diode embedded in transistor: A high voltage integrated circuit contains a freewheeling diode embedded in a transistor. It further includes a control block controlling a high voltage transistor and a power block—including the high voltage transistor—isolated from the control block by a device isolation region. The high voltage transistor includes a semiconductor substrate of... Agent: Sidley Austin Brown & Wood LLP

20070132007 - Nonvolatile semiconductor memory and fabrication method for the same: A nonvolatile semiconductor memory includes active regions . . . AAj-1, AAj, AAj-1, . . . formed in a semiconductor substrate; a plurality of word lines WL0, WL1, . . . in the row direction; memory cell transistors, each including a floating gate provided on the semiconductor substrate via a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070132006 - Nonvolatile semiconductor memory and its manufacturing method: According to an aspect of the invention, a nonvolatile semiconductor memory comprises: a semiconductor substrate; a trench formed in the semiconductor substrate; a first insulating film being formed on a wall surface of the trench; a floating gate electrode formed on the first insulating film inside the trench; a source... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070132009 - Semiconductor device and method for producing the same: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the... Agent: Dickstein Shapiro LLP

20070132010 - Enhanced multi-bit non-volatile memory device with resonant tunnel barrier: A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or LaAlO3. A charge trapping layer is formed over the tunnel barrier. A high-k charge blocking layer is formed over the charge trapping layer. A control... Agent: Attn: Kenneth W. Bolvin Leffert Jay & Polglaze, P.A.

20070132011 - Semiconductor device and method of fabricating the same background: A semiconductor device includes a semiconductor layer formed on a semiconductor substrate by epitaxial growth, a first embedded insulating layer embedded in a first region between the semiconductor substrate and the substrate layer, and a second embedded insulating layer embedded in a second region between the semiconductor substrate and the... Agent: Advantedge Law Group, LLC

20070132012 - Semiconductor device: A semiconductor device includes: a semiconductor layer of a first conductivity type; a plurality of first cylindrical semiconductor pillar regions of the first conductivity type periodically provided on a major surface of the semiconductor layer; a plurality of second cylindrical semiconductor pillar regions of a second conductivity type provided on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070132013 - High-voltage vertical transistor with a multi-gradient drain doping profile: A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer.... Agent: The Law Offices Of Bradley J. Bereznak

20070132014 - Trench insulated gate field effect transistor: The invention relates to a trench MOSPET with drain (8), sub-channel region (10) body (12) and source (14). The sub-channel region is doped to be the same conductivity type as the body (12), but of lower doping density. A field plate electrode (34) is provided adjacent to the sub-channel region... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070132017 - Semiconductor device and manufacturing method of same: The characteristic of the semiconductor device of this invention is that the device has a piercing hole 10 formed in the semiconductor layer to touch a first metal film 18, a insulating film 12 formed on the side wall of the piercing hole 10, a second metal film 13 disposed... Agent: Morrison & Foerster LLP

20070132015 - Semiconductor device and manufacturing method thereof: A semiconductor device includes, on a semiconductor substrate, an active region surrounded by an STI region, a gate trench formed in one direction transverse to the active region, a gate insulating film formed on a side surface of the gate trench, an insulating film formed on a bottom of the... Agent: Young & Thompson

20070132016 - Trench ld structure: A lateral conduction MOSFET has a trench between and separating surface source and drain electrodes. A gate insulation lines one vertical wall of the trench and a polysilicon gate mass is disposed adjacent the gate insulator and fills a portion of the width of the trench. The conduction path from... Agent: Ostrolenk Faber Gerb & Soffen

20070132019 - Dmos transistor with optimized periphery structure: A lateral DMOS transistor is disclosed that includes a first region of a first conductivity type, which is surrounded on the sides by a second region of a second conductivity type, whereby a boundary line between both regions has opposite straight sections and curved sections linking the straight sections, and... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070132018 - Semiconductor device and method for producing the same: A semiconductor device, including a first MIS-type transistor formed in a first region of a semiconductor region, the first region being of a first conductivity type, the first MIS-type transistor including: a first gate insulating film formed on the first region; a first gate electrode formed on the first gate... Agent: Mcdermott Will & Emery LLP

20070132020 - Superjunction power mosfet: Methods and apparatus are provided for TMOS devices, comprising multiple N-type source regions, electrically in parallel, located in multiple P-body regions separated by N-type JFET regions at a first surface. The gate overlies the body channel regions and the JFET region lying between the body regions. The JFET region communicates... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070132021 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device includes a substrate having a recess, a gate electrode in the recess in the substrate, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. An insulating film is on at least on a surface of the gate electrode and a... Agent: Leydig Voit & Mayer, Ltd

20070132025 - Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device: A method for manufacturing a semiconductor substrate comprises: forming a silicon on insulator (SOI) area and an element isolation film on a semiconductor base; forming a first semiconductor layer on the semiconductor base in the SOI structure area; forming a second semiconductor layer having an etching selection ratio smaller than... Agent: Advantedge Law Group, LLC

20070132026 - Method for manufacturing semiconductor substrate, method for manufacturing semiconductor device, and semiconductor device: A method for manufacturing a semiconductor substrate includes forming a first semiconductor layer on a semiconductor base; forming a second semiconductor layer having a lower etching selection ratio than the first semiconductor layer on the first semiconductor layer; removing a part of the second semiconductor layer and a part of... Agent: Advantedge Law Group, LLC

20070132023 - Organic thin film transistor, method of manufacturing the same, and organic light emitting display device having the same: Provided is an organic thin film transistor that can prevents damage to source and drain electrodes when patterning an organic semiconductor layer, and a method of manufacturing an organic light emitting display device having the organic thin film transistor. The organic thin film transistor includes a source electrode and a... Agent: Knobbe Martens Olson & Bear LLP

20070132022 - Semiconductor device and method of manufacturing the same: First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state... Agent: Volentine Francos, & Whitt PLLC

20070132024 - Thin film transistor array panel and method of manufacturing the same: The present invention provides a thin film transistor array panel which includes a substrate, gate lines formed on the substrate, polycrystalline semiconductors formed on the gate lines, data lines formed on the polycrystalline semiconductors and including first electrodes, second electrodes formed on the polycrystalline semiconductors and facing the first electrodes,... Agent: Cantor Colburn, LLP

20070132028 - Semiconductor device and method of manufacturing the same: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070132027 - Transistor device containing carbon doped silicon in a recess next to mdd to create strain in channel: A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral... Agent: Texas Instruments Incorporated

20070132030 - Esd protection circuits and related techniques: An electro-static discharge, ESD, protection circuit is disclosed. While protecting an ESD event between a given pad and a ground pad, the ESD protection circuit triggers a clamp for ESD protection according to a voltage difference between the given pad and a power pad. Generally, chips already have capacitance between... Agent: North America Intellectual Property Corporation

20070132029 - Esd protection for passive integrated devices: Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070132031 - Semiconductor device having stressors and method for forming: N channel and P channel transistors are enhanced by applying stressor layers of tensile and compressive, respectively, over them. A previously unknown problem was discovered concerning the two stressor layers, which both may conveniently be nitride but made somewhat differently. The two stressors have different etch rates which results in... Agent: Freescale Semiconductor, Inc. Law Department

20070132032 - Selective stress relaxation of contact etch stop layer through layout design: A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen... Agent: William Stoffel

20070132033 - High voltage cmos devices: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent... Agent: Slater & Matsil, L.L.P.

20070132034 - Isolation body for semiconductor devices and method to form the same: A semiconductor device and method for its fabrication are described. An isolation body may be formed prior to formation of an active region. In one embodiment, the isolation body is void-free.... Agent: Intel/blakely

20070132035 - Transistor mobility improvement by adjusting stress in shallow trench isolation: A method of improving the carrier mobility of a transistor is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. After the step of forming the... Agent: Slater & Matsil, L.L.P.

20070132036 - Method of manufacturing semiconductor device: A method for manufacturing a semiconductor device, includes sequentially forming a first insulation film and a dummy gate electrode on a semiconductor substrate; forming a lightly doped junction region by using the dummy gate electrode as a mask, forming a first spacer on a side wall of the dummy gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070132037 - Semiconductor device having ohmic recessed electrode: The present invention provides a semiconductor device having a recess-structured ohmic electrode, in which the resistance is small and variation in the resistance value caused by manufacturing irregularities is small. In the semiconductor device of the present invention, a two-dimensional electron gas layer is formed on the interface between a... Agent: Venable LLP

20070132038 - Embedded stressor structure and process: An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide... Agent: William Stoffel

20070132039 - Method and structure for strained finfet devices: A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.... Agent: Mcginn Intellectual Property Law Group, PLLC

20070132040 - Semiconductor device and method for manufacturing the same: A semiconductor device comprising a silicon substrate, a gate insulator provided on the silicon substrate, a gate electrode provided on the gate insulator, a first sidewall insulator provided on the side of the gate electrode, a second sidewall insulator provided on the first sidewall insulator, and source and drain diffusion... Agent: Sughrue Mion, PLLC

20070132041 - Method for forming gate dielectric layers: A method for forming gate dielectric layers having different thicknesses is provided, The method includes forming a lower oxide layer, a nitride layer, and an upper oxide layer on a semiconductor substrate; performing a first deglaze process to the semiconductor substrate keeping the lower oxide layer, the nitride layer, and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070132042 - Passivation film of semiconductor device: Disclosed are a method of manufacturing a semiconductor device and a structure of a semiconductor device. A method of forming a passivation film of a semiconductor device comprises the steps of forming metal wires on a semiconductor substrate, forming a buffer oxide film being a first passivation film on the... Agent: Marshall, Gerstein & Borun LLP

20070132043 - Nano-electronic sensors for chemical and biological analytes, including capacitance and bio-membrane devices: Embodiments of nanoelectronic sensors are described, including sensors for detecting analytes inorganic gases, organic vapors, biomolecules, viruses and the like. A number of embodiments of capacitive sensors having alternative architectures are described. Particular examples include integrated cell membranes and membrane-like structures in nanoelectronic sensors.... Agent: O'melveny & Myers LLP

20070132044 - Piezolectric micro electro-mechanical system switch, array of the switches, and method of fabricating the same: A piezoelectric micro electro-mechanical system switch (MEMS), an array of piezoelectric MEMS switches, and a method of fabricating the switch, which are capable of improving low voltage and switching characteristics while securing high signal isolation, are provided. The piezoelectric MEMS switch includes a semiconductor substrate including a groove, a support... Agent: Ladas & Parry LLP

20070132045 - Semiconductor dynamic sensor and method of manufacturing the same: A semiconductor sensor includes an adhesive film for suppressing thermal stress transfer to a semiconductor sensor chip. More specifically, the adhesive film includes a first layer and a second layer. An elasticity modulus of the first layer is lower than that of the second layer, and the second layer has... Agent: Posz Law Group, PLC

20070132047 - Method for manufacturing a microelectromechanical component, and a microelectromechanical component: The invention relates to microelectromechanical components, like microelectromechanical gauges used in measuring e.g. acceleration, angular acceleration, angular velocity, or other physical quantities. The microelectromechanical component, according to the invention, comprises, suitably bonded to each other, a microelectromechanical chip part sealed by a cover part, and at least one electronic circuit... Agent: Squire, Sanders & Dempsey L.L.P.

20070132046 - Nanotube based nonvolatile memory device and a method of fabricating and operating the same: Provided are a nonvolatile memory device and methods of fabricating and operating the same. The memory device may include a substrate, at least a first and a second electrode on the substrate to be spaced a distance from each other, a conductive nanotube between the first and second electrodes and... Agent: Harness, Dickey & Pierce, P.L.C

20070132048 - Multi-layer device: A multi-layer device includes a first layer with a micro-mechanical component formed thereon. The device also includes first and second sealing layers, with the first layer sandwiched between the first and second sealing layers and anodically bonded thereto such that a cavity is defined therein. An electrode is provided within... Agent: Edell, Shapiro & Finnan, LLC

20070132049 - Unipolar resistance random access memory (rram) device and vertically stacked architecture: One embodiment of the present invention includes a low-cost unipolar rewritable variable-resistance memory device, made of cross-point arrays of memory cells, vertically stacked on top of one another and compatible with a polycrystalline silicon diode.... Agent: Maryam Imam, Esq. Law Offices Of Imam

20070132050 - Photoelectric surface and photodetector: Disclosed is a photoelectric surface including: a first group III nitride semiconductor layer that produces photoelectrons according to incidence of ultraviolet rays; and a second group III nitride semiconductor layer provided adjacent to the first group III nitride semiconductor layer and made of a thin-film crystal having c-axis orientation in... Agent: Drinker Biddle & Reath (dc)

20070132051 - Solid-state imaging device and manufacturing method for the same: A solid-state imaging device is provided and has: a plurality of photoelectric conversion elements; and a plurality of gapless microlenses formed above the plurality of photoelectric conversion elements. The focal length of each of the plurality of microlenses is determined according to a color detected by a photoelectric conversion element... Agent: Birch Stewart Kolasch & Birch

20070132052 - Electronic and optoelectronic devices with quantum dot films: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070132053 - Integrated circuit on corrugated substrate: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges... Agent: Bever, Hoffman & Harms, LLP

20070132054 - Memory cell having stressed layers: A memory cell comprises a p-doped substrate with a pair of spaced apart n-doped regions on the substrate that form a source and drain about the channel. A stack of layers on the channel comprises, in sequence, (i) a tunnel oxide layer, (ii) a floating gate, (iii) an inter-gate dielectric,... Agent: Janah & Associates, P.C.

20070132055 - Semiconductor device and manufacturing method thereof: A semiconductor device may include at least one of: a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed over a semiconductor substrate; a lower inter-metal dielectric (IMD) layer (e.g. having first and second contact holes) formed over an interlayer dielectric layer; a metal interconnection and a MIM... Agent: Sherr & Nourse, PLLC

20070132057 - Active region spacer for semiconductor devices and method to form the same: A semiconductor device and method for its fabrication are described. An active region spacer may be formed on a top surface of an isolation region and adjacent to a sidewall of an active region. In one embodiment, the active region spacer may suppress the formation of metal pipes in the... Agent: Intel/blakely

20070132058 - Adjuvant for controlling polishing selectivity and chemical mechanical polishing slurry comprising the same: Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, which forms an adsorption layer on the cationically charged material in order to increase polishing selectivity of the anionically charged material, wherein the adjuvant comprises a polyelectrolyte salt containing: (a) a... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070132056 - Isolation structures for semiconductor integrated circuit substrates and methods of forming the same: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of... Agent: Silicon Valley Patent Group LLP

20070132060 - Electronic component: The invention provides an electronic component which has an improved breakdown limit value of withstand voltage and improved insulation properties and which can be made compact and provided with a multiplicity of layers and a great capacity. The electronic component includes a first conductor having a bottom conductor formed on... Agent: Oliff & Berridge, PLC

20070132059 - Laser fuse with efficient heat dissipation: A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structure includes a laser fuse and a connection structure connecting the fuse... Agent: Slater & Matsil, L.L.P.

20070132062 - Electronic apparatus interconnect routing and interconnect routing method for minimizing parasitic resistance: Method and apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26,... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070132063 - Integrated thin film capacitors with adhesion holes for the improvement of adhesion strength: In an embodiment, a substrate includes a thin film capacitor embedded within. In an embodiment, a plurality of adhesion holes extend through the thin film capacitor. These adhesion holes may improve the adhesion of the capacitor to other portions of the substrate.... Agent: Intel Corporation C/o Intellevate, LLC

20070132061 - Mim capacitor in a copper damascene interconnect: A metal-insulator-metal capacitor formed in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper... Agent: Duane Morris LLPIPDepartment (tsmc)

20070132064 - Stacked electrical resistor pad for optical fiber attachment: An electrical resistor structure overlies a substrate and comprises a composite resistor having a first resistor of relatively low resistance and a second resistor of relatively high resistance overlying the first resistor. First and second electrodes make contact with the composite resistor at spaced locations, and a bond pad overlies... Agent: Casey Toohey Emcore Corporation

20070132065 - Paraelectric thin film structure for high frequency tunable device and high frequency tunable device with the same: Provided are a paraelectric thin film structure and a high frequency tunable device with the paraelectric thin film structure. The paraelectric thin film structure has a large dielectric constant tuning rate and a low dielectric loss at a high frequency. The paraelectric thin film structure includes a perovskite ABO3 type... Agent: Ladas & Parry LLP

20070132066 - Substrate having minimum kerf width: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.... Agent: Vierra Magen/sandisk Corporation

20070132067 - Wafer-to-wafer alignments: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other... Agent: Schmeiser, Olsen & Watts

20070132068 - Large-sized substrate and method of producing the same: A large-sized substrate having a diagonal length of not less than 500 mm and a ratio of flatness/diagonal length of not more than 6×10−6 is disclosed. By use of the large-sized substrate for exposure of the present invention, the exposure accuracy, particularly the register accuracy and resolution are enhanced, so... Agent: Birch Stewart Kolasch & Birch

20070132069 - Semiconductor chip and shielding structure thereof: A semiconductor chip including a substrate, a metal interconnection structure and a circuit is provided. The substrate has at least one dielectric ring on a substrate surface of the substrate. The metal interconnection structure is disposed on the substrate surface and has at least one guard ring. The circuit lies... Agent: J.c. Patents, Inc.

20070132070 - Microstrip spacer for stacked chip scale packages, methods of making same, methods of operating same, and systems containing same: A chip package includes a microstrip spacer disposed between a first die and a second die. The microstrip spacer includes electrically conductive planes that are ground planes for at least one of the first die and the second die. A method includes operating the first die at a first clock... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070132072 - Chip package and coreless package substrate thereof: A chip package includes a coreless package substrate and a chip. The coreless package substrate includes an interconnection structure and a ceramic stiffener. The interconnection structure has a first inner circuit, a carrying surface and a corresponding contact surface. The first inner circuit has multiple contact pads disposed on the... Agent: J C Patents, Inc.

20070132073 - Device and method for assembling a top and bottom exposed packaged semiconductor: A packaged semiconductor device includes a two piece lead assembly having vertically separated top and bottom lead frames. A semiconductor die is between the two lead frames and makes electrical and thermal contact to the two lead frames. The lower lead frame is generally flat while the upper lead frame... Agent: Hiscock & Barclay, LLP

20070132071 - Package module with alignment structure and electronic device with the same: A package module with an alignment structure is provided by this invention. The package module comprises a package substrate having a die region and a die disposed thereon. At least one pair of conductive alignment protrusions is disposed in the die region and is separated from each other by the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070132074 - Chip package structure: An improved chip package structure includes a chip carrier, a chip, a plurality of pins, a plurality of leads, a package body and a heat spreader. The chip is fixed on the chip carrier. The leads are electrically connected between the chip and the pins. The package body is packaged... Agent: Rosenberg, Klein & Lee

20070132077 - Flip chip mlp with conductive ink: The invention provides a flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a taped leadframe with a plurality of leads and a non-conducting tape placed thereon. The electrical paths are printed on the tape to connect the features of the semiconductor device... Agent: Hiscock & Barclay, LLP

20070132076 - High temperature package flip-chip bonding to ceramic: A sensor package apparatus and method are disclosed in which a sensor die is provided and based on a substrate. An integrated circuit is generally associated with the sensor die. A leadframe is also provided, which is connected by at least one weld to the integrated circuit and the substrate.... Agent: Kris T. Fredrick Honeywell International Inc.

20070132075 - Structure and method for thin single or multichip semiconductor qfn packages: A semiconductor device (100) has one or more semiconductor chips (110) with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments (111) separated from the chip by gaps (120); the segments have first and second surfaces, wherein the second... Agent: Texas Instruments Incorporated

20070132078 - Underfill film having thermally conductive sheet: An underfill film for an electronic device includes a thermally conductive sheet. The electronic device may include a printed circuit board, an electrical component, an underfill, and the thermally conductive sheet. The underfill is situated between the circuit board and the component. The thermally conductive sheet is situated within the... Agent: Law Offices Of Michael Dryja

20070132079 - Power semiconductor component with semiconductor chip stack in a bridge circuit and method for producing the same: A power semiconductor component (30) with power semiconductor chip stack (14) has a base power semiconductor chip (16) and a power semiconductor chip (17) stacked on the rear side of the base power semiconductor chip (16), a rewiring structure for the electrical coupling of the power semiconductor chips being arranged... Agent: Baker Botts, L.L.P.

20070132082 - Copper plating connection for multi-die stack in substrate package: An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another and have copper plated segments for die interconnection. The dice are interconnected using copper... Agent: Blakely Sokoloff Taylor & Zafman

20070132084 - Multichip stacking structure: A multichip stacking structure is provided, including a chip carrier; a plurality of semiconductor chips stacked on the chip carrier in a stepped manner that an overlying chip mounted on an underlying chip of the plurality of semiconductor chips has a suspended portion free of being in contact with the... Agent: Edwards Angell Palmer & Dodge LLP

20070132081 - Multiple stacked die window csp package and method of manufacture: A semiconductor package including a first substrate having a die receiving area, a first adhesive layer, a window opening, and a plurality of conductive traces, a first semiconductor die having two sides and with an electrically active side mounted to the substrate through the first adhesive layer, a second adhesive... Agent: Greenblum & Bernstein, P.L.C

20070132080 - Semiconductor chip mounted interposer, semiconductor device, semiconductor chip interposer fabrication method, bare chip mounted interposer, and interposer sheet: A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor... Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP

20070132083 - Semiconductor package having increased resistance to electrostatic discharge: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to... Agent: Lsi Logic Corporation

20070132085 - Stacked semiconductor device: As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number... Agent: Young & Thompson

20070132086 - Integrated circuit devices including compliant material under bond pads and methods of fabrication: An integrated circuit device includes a die having an interconnect structure formed over a surface thereof. A volume of compliant material located within the interconnect structure underlies one or more bond pads disposed on an uppermost layer of the interconnect structure. The compliant material may absorb stresses exerted on the... Agent: Intel Corporation C/o Intellevate, LLC

20070132088 - Printed circuit board: A printed circuit board including a conductor portion, an insulating layer formed over the conductor portion, a thin-film capacitor formed over the insulating layer and including a first electrode, a second electrode and a high-dielectric layer interposed between the first electrode and the second electrode, and a via-hole conductor structure... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070132087 - Via hole having fine hole land and method for forming the same: Disclosed herein are a via hole having a fine hole land with which the density of circuit patterns can be increased and a method for forming the same. The method comprises: step 1 of forming a via hole in a copper clad laminate, coating an etching resist over the copper... Agent: Staas & Halsey LLP

20070132089 - Microelectronic devices and methods for manufacturing microelectronic devices: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a device includes a support member and a flexed microelectronic die mounted to the support member. The flexed microelectronic die has a plurality of terminals electrically coupled to the support member and an integrated circuit operably... Agent: Perkins Coie LLP Patent-sea

20070132090 - Semiconductor device: A semiconductor device (20) in which a semiconductor element (2) is mounted on one of a front side and a back side of a wiring board (3), and a plurality of lands (9)(23) for external connection are provided on the other side of the wiring board, the land (9)(23) including... Agent: Steptoe & Johnson LLP

20070132091 - Thermal enhanced upper and dual heat sink exposed molded leadless package: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar... Agent: Hiscock & Barclay, LLP

20070132092 - Light-emitting diode assembly and method of fabrication: An LED assembly includes a packaged LED module (30) and a heat dissipation device (50). The LED module includes at least an LED die therein and a plurality of conductive pins (32, 34) extending downwardly from a bottom portion thereof. The heat dissipation device is thermally and electrically connected with... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070132093 - System-in-package structure: A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the... Agent: North America Intellectual Property Corporation

20070132094 - Circuit module: In a circuit module for a high frequency, a resistance film is formed on a side of a semiconductor circuit chip, mounted above a dielectric substrate through ground metal layers, opposite to the dielectric substrate. A distance from the ground metal layer to the resistance film is a ¼ wavelength... Agent: Bingham Mccutchen LLP

20070132095 - Integrated circuit chip with external pads and process for fabricating such a chip: An integrated circuit chip has a dielectric surface layer and, below this layer, internal pads. The chip is fabricated by producing multiplicities of vias made of an electrically conducting material which pass through said surface layer and are positioned respectively above the internal pads. Projecting external contact pads are formed... Agent: Jenkens & Gilchrist, PC

20070132096 - Semiconductor device and method of manufacturing the same: A conductive region electrically connected to a buffer coat film is formed on at least one corner of a semiconductor substrate, so that electricity charged on a package seal resin or a surface of the buffer coat film is allowed to flow toward the conductive region through a conductive path.... Agent: Steptoe & Johnson LLP

20070132098 - Elastic conductive resin, and electronic device including elastic conductive bumps made of the elastic conductive resin: An electronic device includes an electronic part including at least one first electrode, a substrate including at least one second electrode, and at least one bump formed on the at least one first electrode and formed from an elastic conductive resin including a resin having rubbery elasticity, and an acicular... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070132097 - Projected contact structures for engaging bumped semiconductor devices: A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder ball of a bumped integrated circuit (IC) device, such as a bumped die and a bumped packaged IC device. The projections are... Agent: Trask Britt, P.C./ Micron Technology

20070132099 - Semiconductor device and method of manufacture thereof, circuit board and electronic instrument: A semiconductor device, including a semiconductor chip having electrodes, a substrate having an interconnect pattern, and an adhesive, the adhesive having a first portion and a second portion, the first portion interposed between a surface of the substrate on which the interconnect pattern is formed and a surface of the... Agent: Oliff & Berridge, PLC

20070132100 - Semiconductor device and method for fabricating the same: A semiconductor device includes an insulation film 6 formed on a silicon substrate 1, a buried interconnect 10 formed in the insulation film 6, and a barrier metal film A1 formed between the insulation film 6 and the buried interconnect 10. The barrier metal film A1 is formed of a... Agent: Mcdermott Will & Emery LLP

20070132101 - Semiconductor device and method of manufacturing a semiconductor device: A semiconductor device may include the following. A diffusion barrier formed over a semiconductor substrate having a conductive layer. An etching stop layer formed over a diffusion barrier. Inter-metal dielectric (IMD) layers (e.g. having via holes formed over an etching stop layer and trenches wider than the via holes). Metal... Agent: Sherr & Nourse, PLLC

20070132102 - Relay board provided in semiconductor device, semiconductor device, and manufacturing method of semiconductor device: A relay board provided in a semiconductor device, including an entire main surface that is made of a conductive material. The relay board may further include a substrate made of the same material as at least one semiconductor element provided in the semiconductor device. The main surface of the relay... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070132103 - Semiconductor device, and method and apparatus for inspecting appearance thereof: A semiconductor device includes a first wiring layer having a first wiring, a second wiring layer having a second wiring formed over the first wiring layer, and a first insulating layer interposed between the first and second wiring layers, wherein the second wiring layer or an upper layer thereof has... Agent: Harness, Dickey & Pierce, P.L.C

20070132105 - Selective activation of aluminum, copper, and tungsten structures: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure... Agent: Trask Britt, P.C./ Micron Technology

20070132104 - Semiconductor component having plate, stacked dice and conductive vias: A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20070132107 - Chip package structure and process for fabricating the same: A chip package structure comprises a carrier, a chip and an underfill. The chip has an active surface on which a plurality of bumps is formed. The chip is flip-chip bonded onto the carrier with the active surface facing the carrier, and is electrically connected to the carrier through the... Agent: Jianq Chyun Intellectual Property Office

20070132106 - Forming compliant contact pads for semiconductor packages: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and... Agent: Trop Pruner & Hu, PC

20070132108 - Method for manufacturing a wafer level chip scale package: A semiconductor wafer with semiconductor chips having chip pads and a passivation layer is provided. First and second dielectric layers are sequentially formed on the passivation layer. The first and second dielectric layers form a ball pad area that includes an embossed portion, i.e., having a non-planar surface. A metal... Agent: Marger Johnson & Mccollom, P.C.

20070132109 - Electrical microfilament to circuit interface: Devices and methods for electrical interconnection for microelectronic circuits are disclosed. One method of electrical interconnection includes forming a bundle of microfilaments, wherein at least two of the microfilaments include electrically conductive portions extending along their lengths. The method can also include bonding the microfilaments to corresponding bond pads of... Agent: Thorpe North & Western, LLP.

20070132111 - Fine-sized chip package structure: A fine-sized chip package structure is disclosed to include a memory chip, a leadframe having a plurality of leads bilaterally arranged on the bottom surface of the memory chip, gold wires connected between respective bonding pads at the middle part of the bottom surface of the memory chip and respective... Agent: Optimum Care International Tech. Inc.

20070132112 - Semiconductor device and mold for resin-molding semiconductor device: A semiconductor device includes a pair of power chips, an IC chip, a plurality of leads one of which having a die pad on which the power chips are mounted and another one having a die attach portion on which the IC chip is mounted, a resin sheet firmly adhered... Agent: Buchanan, Ingersoll & Rooney PC

20070132110 - Semiconductor device having a molded package: A semiconductor device having a molded package includes a semiconductor chip, a thick-film lead electrode to which the semiconductor chip is die-bonded, a thin-film lead electrode having a thickness smaller than that of the thick-film lead electrode, a wire which electrically connects the semiconductor chip to the thin-film lead wire,... Agent: Leydig Voit & Mayer, Ltd

20070132113 - Alkyl-phenyl silsesquioxane resins compositions: Compositions comprising a powder and an alkyl-phenyl silsesquioxane resin are disclosed. These compositions are particularly useful in a variety of personal or medical care compositions to enhance the durability and substantivity of powders after topical application.... Agent: Dow Corning Corporation Co1232

20070125995 - Horizontal emitting, vertical emitting, beam shaped, distributed feedback (dfb) lasers fabricated by growth over a patterned substrate with multiple overgrowth: A structure using integrated optical elements is comprised of a substrate, a buffer layer grown on the substrate, one or more first patterned layers deposited on top of the buffer layer, wherein each of the first patterned layers is comprised of a bottom lateral epitaxial overgrowth (LEO) mask layer and... Agent: Gates & Cooper LLP Howard Hughes Center

20070125996 - Crystal firm, crystal substrate, and semiconductor device: A crystal foundation having dislocations is used to obtain a crystal film of low dislocation density, a crystal substrate, and a semiconductor device. One side of a growth substrate (11) is provided with a crystal layer (13) with a buffer layer (12) in between. The crystal layer (13) has spaces... Agent: Rader Fishman & Grauer PLLC

20070125997 - Light-controlling structure and display device employing the same: Provided are a light-controlling structure having a simple structure and a short response time and a display device employing the structure, wherein the structure includes a first electrode; a second electrode which is disposed apart from the first electrode; at least one heat-emitting unit which is electrically connected to the... Agent: Knobbe Martens Olson & Bear LLP

20070125999 - Configurable power segmentation using a nanotube structure: Configurable power segmentation using a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer in an integrated circuit, and coupling a power region in the transistor layer to at least one power source based on a state of the nanotube... Agent: Lsi Logic Corporation

20070125998 - Manufacture of resins: A method of forming a powder and/or discrete gel particles of a compound selected from the group of a metallic oxide, a metalloid oxide, a mixed oxide, an organometallic oxide, an organometalloid oxide, an organomixed oxide resin, and/or an organic resin from one or more respective organometallic precursor(s), organometalloid precursor(s)... Agent: Howard & Howard Attorneys, P.C.

20070126000 - Organic light emitting diode (oled) display panel and method of forming polysilicon channel layer thereof: An organic light emitting diode (OLED) display panel and a method of forming a polysilicon channel layer thereof are provided. In the method, firstly, a substrate having a polysilicon layer disposed thereon is provided. Then, a dopant atom not selected from the IIIA group and the VA group is doped... Agent: Rabin & Berdo, PC

20070126001 - Organic semiconductor device and method of fabricating the same: An organic semiconductor device and a method of fabricating the same are provided. The device includes: a first electrode; an electron channel layer formed on the first electrode; and a second electrode formed on the electron channel layer, wherein the electron channel layer comprises: a lower organic layer formed on... Agent: Ladas & Parry LLP

20070126003 - Thin film transistor, display device and their production: The present method prevents malfunctions in switching caused by a light leakage current in an active matrix type thin film transistor substrate for a liquid crystal display and prevents display failures, by selectively disposing a self assembled monolayer film in a gate electrode-projected region of the surface of an insulator... Agent: Hogan & Hartson L.L.P.

20070126002 - Thin-film transistor, electronic circuit, display unit, and electronic device: A thin-film transistor includes a gate electrode, a source electrode, a drain electrode, a semiconductor layer, and a gate insulating layer for insulating the source electrode and the drain electrode from the gate electrode, wherein the gate insulating layer includes composite particles in which a hydrophobic compound is provided on... Agent: Harness, Dickey & Pierce, P.L.C

20070126004 - Lamp with multi-colored oled elements: Solid-state area illumination stems and method for forming such systems are provided. The illumination system comprises: a plurality of OLED devices each device formed on a separate substrate and each device emitting light at a plurality of angles relative to the substrate, the emitted light having different ranges of frequencies... Agent: Mark G. Bocchetti Patent Legal Staff

20070126005 - Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same: A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a... Agent: F. Chau & Associates, LLC

20070126006 - Thin film transistor liquid crystal display: A display includes a thin film transistor, a repair structure for repairing a defect in a signal line coupled to the thin film transistor, the repair structure including a first repair metal layer and a second repair metal layer. The transistor includes a gate electrode, a source electrode, and a... Agent: Fish & Richardson PC

20070126007 - Sic semiconductor device and method of fabricating same: A SiC semiconductor device and method of fabricating a SiC semiconductor device is provided. The method includes forming a source region and a drain region over a silicon carbide layer which is activated at a high temperature. A gate oxide layer is formed over the silicon carbide layer and is... Agent: Patrick S. Yoder Fletcher Yoder

20070126008 - Gallium nitride-based compound semiconductor light-emitting device, positive electrode for the device, light-emitting diode and lamp using the device: An object of the present invention is to provide a flip-chip-type gallium nitride compound semiconductor light-emitting device exhibiting excellent ohmic characteristics, excellent bonding characteristics, and high emission output. The inventive flip-chip-type gallium nitride compound semiconductor light-emitting device comprises a positive electrode which has a three-layer structure comprising an ohmic electrode... Agent: Sughrue Mion, PLLC

20070126009 - Group-iii nitride semiconductor device: The inventive Group III nitride semiconductor element comprises a substrate; a first nitride semiconductor layer composed of AlN which is provided on the substrate; a second nitride semiconductor layer composed of Alx1Ga1-x1N (0≦x1≦0.1) which is provided on the first nitride semiconductor layer; and a third nitride semiconductor layer composed of... Agent: Sughrue Mion, PLLC

20070126010 - Photonic device with integrated hybrid microlens array: A microlens structure is mounted directly onto the upper surface of a packaged VCSEL device and positioned to locate microlenses directly over corresponding VCSEL elements. The microlens structure includes a block-like pedestal having a lower surface that faces the upper surface of the VSCEL device. The microlenses are formed in... Agent: Bever, Hoffman & Harms, LLP

20070126012 - Light-emitting element and display device: A combined thickness of an optical distance between an anode and a cathode together with a red-light-emitting layer, a blue-light-emitting layer, and the like of a light-emitting element and the anode is set to a thickness by which red and blue light can be intensified by interference. Thus, light of... Agent: Cantor Colburn, LLP

20070126011 - White light emitting diode: The present invention relates to a white light emitting diode comprising a blue light emitting diode chip; a green light emitting diode chip; and a molding member that encapsulates the blue light emitting diode chip and a green light emitting diode chip, the molding member containing a red fluorescent substance.... Agent: Macpherson Kwok Chen & Heid LLP

20070126013 - Light emitting device and method for fabricating the same: A light emitting device and a method for fabricating the same are disclosed, whereby a thin mask film is changed to agglomerates by a simple thermal treatment process, and a plurality of nano openings, each opening spaced a distance apart, are formed in the agglomerates, a light emitting structure exposed... Agent: Mckenna Long & Aldridge LLP

20070126014 - Light-emitting element with heterojunction structure: A method for manufacturing a light-emitting element with a heterojunction of group IV is provided. The method comprises at least the steps of: (1) providing a silicon substrate having a first and a second surfaces; (2) forming a germanium layer on the first surface; (3) forming a cap layer on... Agent: Volpe And Koenig, P.C.

20070126016 - Light emitting device and manufacture method thereof: A flip-chip LED including a light emitting structure, a first dielectric layer, a first metal layer, a second metal layer, and a second dielectric layer is provided. The light emitting structure includes a first conductive layer, an active layer, and a second conductive layer. The active layer is disposed on... Agent: Ingrassia Fisher & Lorenz, P.C.

20070126015 - Semi-insulating bulk zinc oxide single crystal: A semi-insulating zinc-oxide (ZnO) single crystal. The crystal has resistivity of at least 1.5×103 ohm-centimeter (Ω-cm). The ZnO crystal can be produced from a melt contained by solid-phase ZnO to prevent introduction of undesired impurities into the crystal. The crystal can be a bulk single crystal that is cut and... Agent: Alston & Bird LLP

20070126018 - Light-emitting device using voltage switchable dielectric material: A voltage switchable dielectric material (VSD) material as part of a light-emitting component, including LEDs and OLEDs.... Agent: Shemwell Mahamedi LLP

20070126017 - Luminescent ceramic element for a light emitting device: A semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region is attached to a compound substrate including a host which provides mechanical support to the device and a ceramic layer including a luminescent material. In some embodiments the compound substrate includes a crystalline... Agent: Patent Law Group LLP

20070126019 - Light emitting device: A light emitting element (100) comprising an element chip (100C) provided, at least in a partial section in the thickness direction thereof, with a part of reduced cross-section where the cross sectional area decreases continuously or stepwise in the direction perpendicular to the thickness direction from the first major surface... Agent: Snider & Associates

20070126020 - High-power led chip packaging structure and fabrication method thereof: A packaging structure and a related fabrication method for high-power LED chip are provided herein, which mainly contains a base made of a metallic material and an electrically insulating material integrated into a single object. The metallic material forms a heat sinking seat in the middle of the base, which... Agent: Lin & Associates Intellectual Property

20070126023 - Growth of reduced dislocation density non-polar gallium nitride: Lateral epitaxial overgrowth (LEO) of non-polar gallium nitride (GaN) films results in significantly reduced defect density.... Agent: Gates & Cooper LLP Howard Hughes Center

20070126021 - Metal oxide semiconductor film structures and methods: Layered and film structures for improving the performance of semiconductor devices include single and multiple quantum wells and double heterostructures and superlattice structures.... Agent: Jacobs & Kim LLP

20070126022 - Vertical gallium-nitride based light emitting diode and manufacturing of the same: A vertical GaN-based LED and a method of manufacturing the same are provided. The vertical GaN-based LED can prevent the damage of an n-type GaN layer contacting an n-type electrode, thereby stably securing the contact resistance of the n-electrode. The vertical GaN-based LED includes: a support layer; a p-electrode formed... Agent: Mcdermott Will & Emery LLP

20070126024 - Over charge protection device: An over-voltage protection device includes a substrate including an upper surface and a lower surface; a first electrode provided on the upper surface of the substrate; a second electrode provided on the lower surface on the substrate; a first conductive layer overlying the lower surface of the substrate, the first... Agent: Townsend And Townsend And Crew, LLP

20070126026 - Semiconductor device: A semiconductor device includes: a first group-III nitride semiconductor layer formed on a substrate; a second group-III nitride semiconductor layer made of a single layer or two or more layers, formed on the first group-III nitride semiconductor layer, and acting as a barrier layer; a source electrode, a drain electrode,... Agent: Mcdermott Will & Emery LLP

20070126025 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate, a plurality of first wirings disposed above the semiconductor substrate along a first direction, a diffusion layer that is disposed on the surface of the semiconductor substrate so as to extend along a second direction perpendicular to the first direction and which includes... Agent: Rabin & Berdo, PC

20070126027 - Super luminescent diode and manufacturing method thereof: To provide a superluminescent diode capable of emitting high output super luminescent light having a central wavelength within a range of 0.95 μm to 1.2 μm and an undistorted beam cross section, having a long element life. The super luminescent diode is constituted by: an n-type GaAs substrate; an optical... Agent: Sughrue Mion, PLLC

20070126028 - Low resistance void-free contacts: A plug is formed by depositing a first material to partially fill an opening, leaving an unfilled portion with a lower aspect ratio than the original opening. A second material is then deposited to fill the remaining portion of the opening. The first material has good filling characteristics but has... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070126029 - Integrated circuit devices having fuse structures including buffer layers: An integrated circuit device is provided including an integrated circuit substrate having a fuse region. A window layer is provided on the integrated circuit substrate that defines a fuse region. The window layer is positioned at an upper portion of the integrated circuit device and recessed beneath a surface of... Agent: Myers Bigel Sibley & Sajovec

20070126030 - Semiconductor device and method for manufacturing same, and semiconductor wafer: Disclosed herein is a semiconductor device including: a semiconductor chip; a first insulating layer covering the semiconductor chip in a condition where at least a portion of a terminal electrode of the semiconductor chip is exposed; a second insulating layer formed over the first insulating layer; and a rewiring layer... Agent: Robert J. Depke Lewis T. Steadman

20070126032 - Fin field effect transistor and method for manufacturing fin field effect transistor: The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the... Agent: J.c. Patents

20070126031 - Semiconductor integrated circuit and method of manufacturing the same: Conventional capacitors constituted of a FET incur degradation in frequency response. A semiconductor integrated circuit includes a semiconductor substrate, an N-type FET, a P-type FET, and capacitors. The N-type FET includes N-type impurity diffusion layers, a P-type impurity-implanted region, a gate insulating layer, and a gate electrode. The P-type FET... Agent: Mcginn Intellectual Property Law Group, PLLC

20070126033 - Dual-gate device and method: A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material... Agent: Macpherson Kwok Chen & Heid LLP

20070126037 - Electric device having nanowires, manufacturing method thereof, and electric device assembly: An electric device having a plurality of nanowires, in which at least one of the nanowires is cut or changed in its electric characteristics so as to have a desired characteristic value of the electric device.... Agent: Morgan & Finnegan, L.L.P.

20070126035 - Field-effect microelectronic device, capable of forming one or several transistor channels: The invention relates to a field-effect microelectronic device, as well as the method of production thereof. The device includes a substrate (700) as well as at least one improved structure (702) capable of forming one or more transistor channels. This structure, formed by a plurality of bars stacked on the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070126036 - Semiconductor device and semiconductor device manufacturing method: A semiconductor device is configured so that there is formed a stressor film 4 covering the first field effect transistor and the second field effect transistor, formed with openings from which the originating area and the terminating area of each of the first field effect transistor and the second field... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070126034 - Semiconductor substrate, semiconductor device and process for producing semiconductor substrate: An opening 35 is formed on an assembly having a silicon germanium layer 32, a silicon layer 33, and a silicon oxide layer 34 sequentially formed on a silicon basis material 31. An additional silicon oxide layer 36 is formed so as to cover the silicon oxide layer 34 and... Agent: Squire, Sanders & Dempsey L.L.P.

20070126038 - Small-sized semiconductor device featuring protection circuit for mosfet: In a semiconductor device, a metal oxide semiconductor field effect transistor (MOSFET) is formed in a semiconductor substrate, and an isolation layer is formed on the semiconductor substrate so as to extend along a side of the semiconductor substrate. A first conductive layer is formed on the isolation layer along... Agent: Young & Thompson

20070126039 - Solid state imaging apparatus: A 3Tr-operated CMOS solid-state imaging apparatus comprises a plurality of pixels including adjacent first and second pixels 230 and 231 including photodiodes 201 for converting light into signal charges and transfer transistors for reading out the signal charges accumulated in the photodiodes, respectively. The first pixel 230 further includes a... Agent: Mcdermott Will & Emery LLP

20070126041 - Dielectric film capacitor and method of manufacturing the same: A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070126042 - Transistor type ferroelectric memory and method of manufacturing the same: A transistor type ferroelectric memory including: a substrate; a gate electrode formed above the substrate; a ferroelectric layer formed above the substrate to cover the gate electrode; a source electrode formed above the ferroelectric layer; a drain electrode formed above the ferroelectric layer and apart from the source electrode; and... Agent: Harness, Dickey & Pierce, P.L.C

20070126040 - Vacuum cell thermal isolation for a phase change memory device: A memory device with improved thermal isolation. The memory cell includes a first electrode element, having an upper surface; an insulator stack formed on the first electrode element, including first, second and third insulating members, all generally planar in form and having a central cavity formed therein and extending therethrough,... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070126043 - Storage node having a metal-insulator-metal structure, non-volatile memory device including a storage node having a metal-insulator-metal structure and method of operating the same: A storage node having a metal-insulator-metal structure, a non-volatile memory device including a storage node having a metal-insulator-metal (MIM) structure and a method of operating the same are provided. The memory device may include a switching element and a storage node connected to the switching element. The storage node may... Agent: Harness, Dickey & Pierce, P.L.C

20070126044 - Circuit device having capacitor and field effect transistor, and display apparatus therewith: In a circuit device having a field effect transistor and a capacitor, the capacitor is connected to at least one of a gate electrode, a source electrode and a drain electrode of a field effect transistor, the field effect transistor has a channel comprised of a first nano-wire, and the... Agent: Morgan & Finnegan, L.L.P.

20070126045 - Memory devices including dielectric thin film and method of manufacturing the same: A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different... Agent: Ladas & Parry LLP

20070126047 - Non-volatile semiconductor memory device and method for manufacturing the same: In a non-volatile semiconductor memory device having a MONOS structure, a memory cell section for storing information, and a periphery circuitry section for writing and reading the information with respect to the memory cell section are formed in the surface region of a silicon substrate. A plurality of memory cells... Agent: Volentine Francos, & Whitt PLLC

20070126046 - Nonvolatile semiconductor memory and method of fabricating the same: According to the invention, there is provided a nonvolatile semiconductor memory having: a floating gate electrode formed on a gate insulating film on an element region isolated by an element isolation region on a semiconductor substrate; an inter-gate insulating film formed to cover a portion from an upper surface to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070126048 - Semiconductor device and method of forming the same: There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.... Agent: Mills & Onello LLP

20070126050 - Flash memory cell and fabrication method thereof: A flash memory cell transistor is presented that includes a stacked structure of successively formed tunnel oxide layer, floating gate, inter-gate insulating layer and control gate on a semiconductor substrate, an insulating thin film formed on a first sidewall of the stacked structure, and an access gate formed on the... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070126049 - Memory cells for read only memories: The present invention discloses a ROM memory cell that has significantly less total area than previously known ROM memory cells. Instead of using only one layer in the manufacturing process to program the memory cells, the present invention uses at least two layers to program the memory cells. This flexibility... Agent: Nixon & Vanderhye, PC

20070126051 - Semiconductor memory device and its manufacturing method: A semiconductor memory device having a stable characteristic and high reliability is achieved with formation of nano-dots with excellent interface stability. Source/drain diffusion layers are formed on a P-type silicon substrate to form a silicon oxide film. On this silicon oxide film, a silicon-rich oxide film is formed in a... Agent: Townsend And Townsend And Crew, LLP

20070126052 - Method and apparatus for strapping the control gate and the bit line of a monos memory array: A method of manufacturing a non-volatile semiconductor memory. The method includes forming a word gate poly layer on a substrate, wherein an upper surface of the substrate defines a plane of the substrate. The method also includes forming a first dielectric layer coupled to the word gate poly layer and... Agent: Townsend And Townsend And Crew, LLP

20070126053 - Non-volatile memory array structure: A memory array having a smaller active area pitch is provided. In accordance with embodiments of the present invention, active regions are formed in a substrate and transistors are formed between adjacent active regions such that the active regions form the source/drain regions of the transistors. Word lines are formed... Agent: Slater & Matsil, L.L.P.

20070126054 - Nonvolatile memory devices having insulating spacer and manufacturing method thereof: A nonvolatile memory device that effectively prevents the occurrence of the hump phenomenon as well as a manufacturing method for fabricating the same, is presented. In one embodiment, the nonvolatile memory device includes an insulating spacer formed at interface between the active region and isolation layer, and a charge trapping... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070126055 - Trench insulated gate field effect transistor: The invention relates to a trench MOSFET with drain (8), drift (10) body (12) and source (14) regions. The drift region is doped to have a high concentration gradient. A field plate electrode (34) is provided adjacent to the drift region (10) and a gate electrode (32) next to the... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070126056 - Trench structure semiconductor device and method for producing it: A trench structure semiconductor device is disclosed. In one embodiment, field electrode devices are arranged in a trench structure, in direct spatial proximity in comparison with essentially planar or smooth conditions, have an enlarged common interface region with an insulation material in between, whereby a comparatively stronger electrical coupling of... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070126057 - Lateral dmos device insensitive to oxide corner loss: In a lateral DMOS device which has a drain diffusion region, an insulator is provided on the drain diffusion region. The insulator is helpful to reduce the lateral electric field under silicon surface. The gate of the DMOS does not overlap with the insulator over the drain diffusion region such... Agent: Rosenberg, Klein & Lee

20070126059 - Semiconductor device: An object is to provide a semiconductor device which includes an anti-collision function during or after production of an IC chip just by a change of a program, even when there is a change of a specification of a product accompanying a change of the kind or standard of a... Agent: Eric Robinson

20070126058 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from an edge on a channel formation... Agent: Nixon Peabody, LLP

20070126060 - Sram cell with improved layout designs: A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-up transistor and a second pull-down transistor serially coupled... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070126061 - Structure for and method of using a four terminal hybrid silicon/organic field effect sensor device: A four terminal field effect device comprises a silicon field effect device with a silicon N-type semiconductor channel and an N+ source and drain region. An insulator is deposited over the N-type semiconductor channel. An organic semiconductor material is deposited over the insulator gate forming a organic semiconductor channel and... Agent: Kelly K. Kordzik Winstead Sechrest & Minick P.C.

20070126062 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting of a nitride of a predetermined metal in contact with... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070126063 - Semiconductor device and semiconductor device manufacturing method: A semiconductor device includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a silicide gate electrode of an n-type MISFET formed on the gate insulation film; and a silicide gate electrode of a p-type MISFET formed on the gate insulation film and having a thickness smaller... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070126064 - Transistor structure with high input impedance and high current capability and manufacturing process thereof: An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to... Agent: Seed Intellectual Property Law Group PLLC

20070126065 - Semiconductor device and method of manufacturing the same: Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same. The method of the present invention includes: preparing a semiconductor substrate having a isolation layer to define an active region; forming a gate insulation layer on the semiconductor substrate; sequentially forming a polysilicon layer,... Agent: Ladas & Parry LLP

20070126066 - Semiconductor cell with power layout not contacting sides of its rectangular boundary and semiconductor circuit utilizing semiconductor cells: A semiconductor cell and a semiconductor circuit utilizing semiconductor cells. The semiconductor cell includes a rectangular boundary and a power layout, where the power layout does not contact any pair of opposite sides of the rectangular boundary. Additionally, the semiconductor circuit includes a plurality of semiconductor cells. Each semiconductor cell... Agent: North America Intellectual Property Corporation

20070126067 - Angled implantation for removal of thin film layers: Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then... Agent: Intel Corporation C/o Intellevate, LLC

20070126068 - Microcomponent comprising a hermetically-sealed cavity and a plug, and method of producing one such microcomponent: The microcavity is delineated by a cover which is formed on a sacrificial layer and in which at least one hole is formed for removal of the sacrificial layer. A plug covers the hole and part of the cover along the periphery of the hole. The plug is made from... Agent: Oliff & Berridge, PLC

20070126069 - Micromechanical device and method for producing a micromechanical device: A micromechanical device and a method for producing this device are provided, the device having a sensor pattern that includes a spring pattern and a seismic mass. The seismic mass may be connected to the substrate material via the spring pattern, and a clearance may be provided in a direction... Agent: Kenyon & Kenyon LLP

20070126070 - Semiconductor devices with electric current detecting structure: A semiconductor device is provided with a main electrode of main switching elements region, a sensor electrode of sensor switching elements region, and a protective device formed between the main electrode and the sensor electrode. The protective device electrically connects the main electrode and the sensor electrode when a predetermined... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070126071 - Process for manufacturing thick suspended structures of semiconductor material: A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front face and delimiting, with the front face, a surface region... Agent: Graybeal Jackson Haley LLP

20070126072 - Surface acoustic wave pressure sensors: Improved SAW pressure sensors and manufacturing methods thereof. A SAW wafer including a number of SAW transducers disposed thereon may be provided. A cover wafer may also be provided, with a glass wall situated between the cover wafer and the SAW wafer. The cover wafer may be secured to the... Agent: Honeywell International Inc.

20070126073 - Novel poly diode structure for photo diode: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer,... Agent: Berkeley Law & Technology Group, LLP

20070126074 - Optical sheet: An optical sheet includes an substrate having a first surface and a second surface opposite to the first surface, a light gathering layer formed on the first surface of the substrate, and an light diffusion layer formed on the second surface of the substrate. The light diffusion layer includes a... Agent: Townsend And Townsend And Crew, LLP

20070126075 - Method for packaging semiconductor device and package structure thereof: A method for packaging an semiconductor device includes following steps. First, a first substrate including at least one first pattern is provided. At least one semiconductor device is disposed on the surface of the first substrate. Next, a spacer with at least one aperture and at least one through hole... Agent: Birch Stewart Kolasch & Birch

20070126076 - Semiconductor optical devices and method for forming: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the... Agent: Freescale Semiconductor, Inc. Law Department

20070126077 - Semiconductor device and method of manufacturing the same: A semiconductor device includes an interlayer insulating film on a substrate. A runner part includes a plurality of runner lines spaced apart from each other by a regular interval under the interlayer insulating film. A fuse cut part includes a plurality of fuse lines spaced apart from each other by... Agent: Marger Johnson & Mccollom, P.C.

20070126078 - Interdigitized capacitor: An interdigitized capacitor comprising first and second electrodes. The first electrode comprises two combs symmetrical to a first mirror plane. The fingers of the combs extend toward the first mirror plane. The second electrode comprises two combs and a linear plate. The combs are symmetrical to a second mirror plane... Agent: Birch Stewart Kolasch & Birch

20070126079 - Nano-wire capacitor and circuit device therewith: A capacitor comprises a first electrode comprised of an electroconductive nano-wire, a dielectric layer partly covering the peripheral face of the first electrode, and a second electrode covering the peripheral face of the dielectric layer. In a circuit device employing the capacitor, a plurality of the capacitors are arranged roughly... Agent: Morgan & Finnegan, L.L.P.

20070126080 - Bipolar junction transistors (bjts) with second shallow trench isolation (sti) regions, and methods for forming same: The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends between the first STI region and the collection region and... Agent: Scully Scott Murphy & Presser, PC

20070126081 - Digital camera module: A digital camera module (200) includes a carrier (20), an image sensor chip (30), a number of wires (50), a holder (60), and a lens module (70). The carrier includes a base (21) and a leadframe (23) embedded in the base. The base includes a board (211), a sidewall (213)... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070126082 - Bipolar transistor, semiconductor apparatus having the bipolar transistor, and methods for manufacturing them: A task is to provide a simple method for obtaining a bipolar transistor being free of current gain dispersion and having a lowered base resistance. The method of the present invention comprises forming a base layer on a semiconductor substrate, and then forming in an insulating film stacked on the... Agent: Rader Fishman & Grauer PLLC

20070126083 - Semiconductor device: The semiconductor device provided assures stable communication processes. For example, a varactor diode for adjusting the reference frequency is comprised within a digital crystal-controlled oscillating circuit provided as an internal circuit of the front-end circuit for generating the reference oscillation signal of a PLL circuit or the like. The varactor... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070126084 - Semiconductor device including fuse focus detector, fabrication method thereof and laser repair method using the fuse detector: Provided are a semiconductor device including a fuse focus detector, a fabrication method thereof and a laser repair method. In a chip region, fuses may be formed at a first level. A fuse focus detector including first and second conductive layers may be formed in a scribe line region. The... Agent: Harness, Dickey & Pierce, P.L.C

20070126085 - Semiconductor device and method of manufacturing the same: A semiconductor device includes an interconnect member, a first semiconductor chip, a second semiconductor chip, a resin layer, an inorganic insulating layer, and a through electrode. The first semiconductor chip is mounted in a face-down manner on the interconnect member. The resin layer covers the side surface of the first... Agent: Mcginn Intellectual Property Law Group, PLLC

20070126086 - Semiconductor devices and manufacturing method thereof: A semiconductor device is provided with a semiconductor substrate having circuit elements formed therein, and an insulating protective film formed on the semiconductor substrate. Hydroxyl groups (OH) are attached to a surface of the protective film. As a result, the contact angle between surface of the protective film and a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070126087 - Electronic component: An electronic component includes a package having a cavity formed therein by providing an annular protrusion on a substrate as well as having a metallized layer on a bottom surface of the cavity, and an element disposed on the bottom surface of the cavity via the metallized layer and housed... Agent: Oliff & Berridge, PLC

20070126088 - Chip on lead frame for small package speed sensor: A sensor package apparatus includes a lead frame substrate that supports one or more electrical components, which are connected to and located on the lead frame substrate. A plurality of wire bonds are also provided, which electrically connect the electrical components to the lead frame substrate, wherein the lead frame... Agent: Honeywell International Inc. Intellectual Property

20070126089 - Method of manufacturing a semiconductor package using lead frame having through holes or hollows therein: A lead frame comprises a stage for mounting a semiconductor chip thereon, a plurality of leads arranged in the periphery of the stage, and a plurality of lead interconnection members (e.g., dam bars) for interconnecting the leads, wherein a plurality of through holes are formed to penetrate through the lead... Agent: Dickstein Shapiro LLP

20070126090 - Tape carrier package and display device including tape carrier package: Heat dissipation, is improved, of a semiconductor device on a tape carrier package, in which the number of outputs of the semiconductor device has been increased for implementing a multi-channel configuration and narrower pitches are employed. There are included a tape carrier 20 having lead patterns 21 to 24 formed... Agent: Sughrue Mion, PLLC

20070126091 - Semiconductor components having through wire interconnects (twi): A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20070126092 - Leadless semiconductor package and method of manufacture: A package to encase a semiconductor package is manufactured by the following steps. First, an electrically conductive frame is provided. This frame has a plurality of leadframes arranged in a matrix with each leadframe having a plurality of spaced leads extending outwardly from a central aperture. The electrically conductive frame... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20070126093 - High thermal conducting circuit substrate and manufacturing process thereof: A manufacturing process of a high thermal conducting circuit substrate is provided. First, a metal core substrate is provided and then the metal core substrate is etched at different etching speeds. Afterwards, two insulating layers are formed respectively on two sides of the etched metal core substrate. In addition, as... Agent: J C Patents, Inc.

20070126094 - Microelectronic package having a stiffening element and method of making same: A method of forming a leadframe package, a leadframe package formed according to the method, and a system incorporating the leadframe package. The leadframe package includes: a metallization layer comprising a paddle portion and a contact portion including contact leads; a die mounted onto the paddle portion; wirebonds connected between... Agent: Intel Corporation C/o Intellevate, LLC

20070126095 - Semiconductor device and manufacturing method thereof: A semiconductor device has a semiconductor package with a semiconductor element is mounted on a mounting substrate. The mounting substrate has at least two anisotropic areas which are located at both sides of a semiconductor package mounting area in a way to sandwich it and have an anisotropic linear expansion... Agent: Townsend And Townsend And Crew, LLP

20070126096 - Leadframe comprising tin plating or an intermetallic layer formed therefrom: A method of producing a leadframe is provided comprising the steps of providing a substrate, plating the substrate with a layer of tin, plating a layer of nickel over the layer of tin, and thereafter plating one or more protective layers over the layer of nickel. The leadframe may thereafter... Agent: Ostrolenk Faber Gerb & Soffen

20070126097 - Chip package structure: A chip package structure including a first chip, a circuit substrate, and a two-stage thermosetting adhesive layer is provided. The first chip has a first upper surface, a first side surface, and a first bottom surface. The circuit substrate has an upper surface and a bottom surface. The first chip... Agent: J.c. Patents, Inc. Suite 250

20070126098 - Surface-mountable light-emitting diode structural element: A surface-mountable light emitting diode structural element in which an optoelectronic chip is attached to a chip carrier part of a lead frame, is described. The lead frame has a connection part disposed at a distance from the chip carrier part, and which is electrically conductively connected with an electrical... Agent: Fish & Richardson PC

20070126099 - Memory card: To provide a memory card advantageous for coping with an increase of storage capacity. As an embodiment of the present invention, a memory card is formed in a rectangular thin-plate form, by a housing that is made of an insulated material and in that a recessed part is formed on... Agent: Bell, Boyd & Lloyd, LLP

20070126101 - Memory card module: A memory card module includes a first circuit board, and a second circuit board. On one surface of the first circuit board, there are flash memories and a controller. The second circuit board is installed at one end of the first circuit board and is electrically connected with the first... Agent: Rabin & Berdo, PC

20070126100 - Semiconductor device and ic card including supply voltage wiring lines formed in different areas and having different shapes: Wiring lines for the supply of a voltage to feed a drive voltage to an integrated circuit formed in a semiconductor chip are disposed so as to cover a main surface of the semiconductor chip, so that, if the wiring lines are removed for the purpose of analyzing information stored... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070126104 - Method of assembling a carriage assembly and assembling apparatus: A method of assembling a carriage assembly and an assembling apparatus that uses the same are capable of suppressing fluctuation in the crimped (deformed) states of spacer portions when suspensions are attached to carriage arms. The method of assembling a carriage assembly aligns fitting holes 10a provided in carriage arms... Agent: Staas & Halsey LLP

20070126103 - Microelectronic 3-d package defining thermal through vias and method of making same: An IC chip, a three dimensional microelectronic package including the IC chip, a system including the microelectronic package, and a method of forming the package. The microelectronic package comprises: a bonding substrate comprising external circuitry; a plurality of IC chips secured in a stack, the plurality comprising a bottom IC... Agent: Intel Corporation C/o Intellevate, LLC

20070126106 - Multi-chip semiconductor connector and method: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.L.C.

20070126107 - Multi-chip semiconductor connector assembly method: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070126102 - Stacked microelectronic packages: A microelectronic assembly including a first and second microelectronic elements. Each of the microelectronic elements have oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first... Agent: Tessera Lerner David Et Al.

20070126105 - Stacked type semiconductor memory device and chip selection circuit: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a... Agent: Mcdermott Will & Emery LLP

20070126110 - Circuit film with bump, film package using the same, and related fabrication methods: A circuit film having film bumps is provided for a film package. An IC chip is mechanically joined and electrically coupled to the circuit film through the film bumps instead of conventional chip bumps. In a fabrication method, a base film is partially etched by a laser to create an... Agent: Marger Johnson & Mccollom, P.C.

20070126108 - External connection structure for semiconductor package, and method for manufacturing the same: Conductive posts to be connected with external connection terminals are formed on a conductive pattern formed on a substrate, and an insulating resin sheet is laminated on the conductive pattern having the conductive posts formed thereon, so as to be flush with the end faces of the conductive posts 3... Agent: Rankin, Hill, Porter & Clark LLP

20070126109 - Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit board, and electronic device: A semiconductor device, includes: a semiconductor substrate having an active face; a first electrode provided on or above the active face of the semiconductor substrate; an external connection terminal electrically connected to the first electrode and provided on or above the active face of the semiconductor substrate; and a connection... Agent: Harness, Dickey & Pierce, P.L.C

20070126112 - Metal core, package board, and fabricating method thereof: A metal core and a package board having the metal core are disclosed. A package board, which comprises a metal core having a plurality of protrusions formed in a lengthwise direction on its surface, an insulation layer stacked on the metal core, and an inner layer circuit formed on the... Agent: Staas & Halsey LLP

20070126111 - Microelectronic packaging and components: The present invention is for substrates for use in interposes for electronic packaging purposes. One preferred embodiment of the present invention is a substrate for use in a Spring Connector Matrix (SCM) interposer having an array of electrically insulated spring connectors each having a fixed end portion and a floating... Agent: Eitan Law Group C/o Landonip, Inc.

20070126113 - Semiconductor device: It is concerned in conventional semiconductor devices that a presence of a heat sink promotes propagating noise through the semiconductor chip. A semiconductor device includes a substrate, interconnects (first interconnects), interconnects (second interconnect), a semiconductor chip and a heat sink (electroconductive member). The interconnect is the interconnect that is electrically... Agent: Mcginn Intellectual Property Law Group, PLLC

20070126114 - Heat-dissipating member, method of manufacturing the same, semiconductor module having the heat-dissipating member, and method of manufacturing the semiconductor module: In one embodiment, a heat-dissipating member includes a heat-dissipating body, a heat-transferring body and an attaching member. The heat-dissipating body externally dissipates heat originating in a heat source. The heat-transferring member is interposable between the heat-dissipating body and the heat source. The attaching member is placed on a surface of... Agent: Marger Johnson & Mccollom, P.C.

20070126115 - Package substrate: A package substrate has a substrate body on which an electronic component is mounted. The substrate body is formed at its top or back surface with a diamond film, a diamond-like carbon film or a carbon film.... Agent: Mcdermott Will & Emery LLP

20070126116 - Integrated circuit micro-cooler having tubes of a cnt array in essentially the same height over a surface: Heat sink structures employing carbon nanotube or nanowire arrays to reduce the thermal interface resistance between an integrated circuit chip and the heat sink, where the nanotubes are cut to essentially the same length over the surface of the structure, are disclosed. Carbon nanotube arrays are combined with a thermally... Agent: Glenn Patent Group

20070126117 - Semiconductor module and manufacturing method thereof: A center of a substrate having peripheral circuit components mounted thereon is hollowed in a size maintaining a distance for establishing a connection with a semiconductor chip through a conductor such that the semiconductor chip is bonded to a heatsink and the peripheral circuit components are arranged near the semiconductor... Agent: Steptoe & Johnson LLP

20070126118 - Mounting flexible circuits onto integrated circuit substrates: A substrate may receive an integrated circuit and a flex circuit on the same side in the same vertical direction. In addition, in some embodiments, a flex circuit adapter and the integrated circuit may be surface mounted in one operation.... Agent: Trop Pruner & Hu, PC

20070126119 - Semiconductor element, production process thereof, semiconductor laser and production process thereof: An object of the present invention is to provide a semiconductor production technology capable of preventing the peeling of the electrode which occurs in die bonding or wire bonding. There is provided a semiconductor element having an electrode in a surface or in a rear face of a semiconductor substrate,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070126120 - Semiconductor device: Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070126122 - Semiconductor device with a wiring substrate and method for producing the same: A semiconductor device with a wiring substrate as a stacking element for a semiconductor device stack is described herein. The wiring substrate includes a plastic frame of a first plastic compound and a central region of a second plastic compound. A semiconductor chip is embedded with its back side and... Agent: Edell, Shapiro & Finnan, LLC

20070126121 - Via structure with improved reliability: A via structure having improved reliability and performance and methods of forming the same are provided. The via structure includes a first-layer conductive line, a second-layer conductive line, and a via electrically coupled between the first-layer conductive line and the second-layer conductive line. The via has a substantially tapered profile... Agent: Slater & Matsil, L.L.P.

20070126124 - Memory module system and method: A circuit module is provided in which two secondary substrates or cards or the rigid portions of a rigid flex assembly are populated with integrated circuits (ICs). The secondary substrates are connected with flexible circuitry. One side of the flexible circuitry exhibits contacts adapted for connection to an edge connector.... Agent: Fish & Richardson P.C.

20070126125 - Memory module system and method: A circuit module is provided in which two secondary substrates or cards or the rigid portions of a rigid flex assembly are populated with integrated circuits (ICs). The secondary substrates are connected with flexible circuitry. One side of the flexible circuitry exhibits contacts adapted for connection to an edge connector.... Agent: Fish & Richardson P.C.

20070126123 - Wiring board and wiring board connecting apparatus: The present invention provides a wiring board including a first board provided with a first wiring pattern and a second board provided with a second wiring pattern while the first wiring pattern and the second wiring pattern are electrically connected, wherein the first board includes: a board insertion opening in... Agent: Sughrue Mion, PLLC

20070126126 - Solder bonding structure using bridge type pattern: Disclosed is a solder bonding structure for flip chip connection. Particularly, this invention relates to a solder bonding structure, in which the shape of a connection pad on which solder is applied is changed to thus increase the size of the solder bond that is formed using a reflow process,... Agent: Staas & Halsey LLP

20070126127 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070126128 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070126129 - Die bonding adhesive tape: Disclosed is a die bonding adhesive tape, which eliminates the requirement for additional adhesive tape for attaching a ring frame, decreases the curing time period upon die bonding, essentially prevents the transfer and diffusion of low-molecular-weight compounds between an adhesive film and an adhesive layer on a base substrate to... Agent: Rothwell, Figg, Ernst & Manbeck, P.C.

20070126130 - Sensor module and method for manufacturing same: A sensor module has a carrier substrate having a bottom side and a top side, a sensor chip arranged on the top side of the carrier substrate and having a pressure-sensitive active area, a signal-processing chip arranged on the top side of the carrier substrate next to the sensor chip... Agent: Baker Botts, L.L.P.

20070126131 - Sensor system having a substrate and a housing, and method for manufacturing a sensor system: A sensor system having a substrate and a housing and a method for manufacturing a sensor system are provided, the housing essentially completely enclosing the substrate in a first substrate region, the housing in a second substrate region being provided at least partially open via an opening, the second substrate... Agent: Kenyon & Kenyon LLP