Active solid-state devices (e.g., transistors, solid-state diodes) inventions 05/07

20070120103 - Switch circuit and method of switching radio frequency signals: An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by... Agent: Jaquez & Associates

20070120104 - Phase change material and non-volatile memory device using the same: The present invention provides a phase change memory cell comprising (GeASbBTeC)1−x(RaSbTeC)x solid solution, the solid solution being formed from a Ge—Sb—Te based alloy and a ternary metal alloy R—S—Te sharing same crystal structure as the Ge—Sb—Te based alloy. A nonvolatile phase change memory cell in accordance with the present invention... Agent: David A. Einhorn, Esq. Anderson Kill Olick, P.C.

20070120105 - Lateral phase change memory with spacer electrodes and method of manufacturing the same: A lateral phase change memory with spacer electrodes and method of manufacturing the same are provided. The memory is formed by connecting the conductive electrodes with lower resistivity and the spacer electrodes with higher resistivity, and filling the phase change material between the spacer electrodes. Therefore, the area that the... Agent: Rabin & Berdo, PC

20070120106 - Phase-change memory device and method of manufacturing same: A phase-change memory device has a phase-change layer, a heater electrode having an end held in contact with the phase-change layer, a contact plug of different kinds of material having a first electrically conductive material plug made of a first electrically conductive material and held in contact with the other... Agent: Sughrue Mion, PLLC

20070120107 - Phase-change memory device and method of manufacturing same: A phase-change memory device has a phase-change layer, a heater electrode having an end held in contact with the phase-change layer, a contact plug of different kinds of material having a first electrically conductive material plug made of a first electrically conductive material and held in contact with the other... Agent: Sughrue Mion, PLLC

20070120108 - Light emitting device: A light emitting device includes a laminate of a lower electrode layer, an organic light-emitting layer, and an upper transparent electrode layer. In the light emitting device, an auxiliary electrode layer is formed of colloidal nano-sized particles of a conductive metal between the lower electrode layer and the organic light-emitting... Agent: Brinks Hofer Gilson & Lione

20070120109 - Surface light-source device using light-emitting elements: A surface light-source device is composed of a light guide plate, luminescent panels and reflector sheets. The light guide plate is composed of three light guide units respectively formed in a rectangular plate-like shape having a rectangular light emission surface, a thick portion, a thin side portion, an incline rear... Agent: Sughrue Mion, PLLC

20070120110 - Thin-film transistors based on tunneling structures and applications: A hot electron transistor includes an emitter electrode, a base electrode, a collector electrode, and a first tunneling structure disposed and serving as a transport of electrons between the emitter and base electrodes. The first tunneling structure includes at least a first amorphous insulating layer and a different, second insulating... Agent: Pritzkau Patent Group

20070120120 - Aromatic enediyne derivatives, organic semiconductor thin films using the same and manufacturing methods thereof, and electronic devices incorporating such films: Disclosed are aromatic enediyne derivatives, methods of manufacturing organic semiconductor thin films from such aromatic enediyne derivatives, and methods of fabricating electronic devices incorporating such organic semiconductor thin films. Aromatic enediyne derivatives according to example embodiments provide improved chemical and/or electrical stability which may improve the reliability of the resulting... Agent: Harness, Dickey & Pierce, P.L.C

20070120114 - Composite material with conductive structures of random size, shape, orientation, or location: A composite material with at least one of a negative effective permittivity and a negative effective permeability for incident radiation of at least one wavelength is described. The composite material comprises conductive structures that are substantially random with respect to at least one of size, shape, orientation, and location.... Agent: Hewlett Packard Company

20070120121 - Compound for molecular electronic device having thiol anchoring group, method of synthesizing the compound, and molecular electronic device having molecular active layer obtained from the compound: In the formula, R1 and R2 are each a thioacetyl group or a hydrogen atom, at least one of R1 and R2 is a thioacetyl group, and m and n are each integers from 0 to 20. The molecular active layer, which is formed by self-assembling the compound on an... Agent: Mayer, Brown, Rowe & Maw LLP

20070120112 - Electrode for energy storage device and process for producing the same: R1 and R2 independently represent a hydrogen atom, a hydroxyl group, a C1-C10 alkyl group, a C1-C10 alkoxy group or the like, R3 and R4 independently represent a hydrogen atom, a halogen atom, a cyano group, a nitro group, an amino group, a C1-C10 alkyl group, a C1-C10 alkoxy group... Agent: Birch Stewart Kolasch & Birch

20070120119 - Light emitting device: A light emitting device includes a laminate of a lower electrode layer, an organic light-emitting layer, and an upper transparent electrode layer. In the light emitting device, an auxiliary electrode layer is formed of colloidal nano-sized particles of a conductive metal between the lower electrode layer and the organic light-emitting... Agent: Brinks Hofer Gilson & Lione

20070120118 - Light-emitting device and electronic apparatus: A light-emitting device includes a drive transistor for controlling the quantity of current supplied to a light-emitting element, a capacitor element electrically connected to a gate electrode of the drive transistor, and an electrical continuity portion for electrically connecting the drive transistor and the light-emitting element, these elements being disposed... Agent: Oliff & Berridge, PLC

20070120122 - Optical device: An optical device comprising an anode, a cathode, an organic semiconducting material between the anode and the cathode, and an electron transport layer between the cathode and the organic semiconducting material wherein the organic semiconducting material comprises sulfur and the electron transport layer containing barium.... Agent: Marshall, Gerstein & Borun LLP

20070120115 - Organic light-emitting element, method of manufacturing organic light-emitting element, light-emitting device, and electronic apparatus: An organic light-emitting element comprises: an anode;an organic light-emitting layer formed on one surface of the anode, an electron transportation layer formed on the organic light-emitting layer; and a cathode formed on a side being opposite to the organic light-emitting layer with respect to the electron transportation layer. A main... Agent: Oliff & Berridge, PLC

20070120116 - Organic semiconductor thin film transistor and method of fabricating the same: A substrate having a thin film transistor includes a buffer layer on a substrate, source and drain electrodes on the buffer layer, a portion of the buffer layer exposed between the source and drain electrodes, a small organic semiconductor layer on the source electrode and the drain electrode, the organic... Agent: Seyfarth Shaw, LLP

20070120111 - Organic thin film transistor: A thin film transistor comprising at least three terminals consisting of a gate electrode, a source electrode and a drain electrode; an insulating layer and an organic semiconductor layer on a substrate, which controls its electric current flowing between the source and the drain by applying a electric voltage across... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070120123 - Photodetector using nanoparticles: The present invention relates to a photodetector using nanoparticles, and more particularly, to a novel photodetector wherein surfaces of nanoparticles synthesized by a wet colloidal process are capped with organic materials which then serve as channels for electron migration, or nanoparticles, from which organic materials capped on the surfaces of... Agent: Buchanan, Ingersoll & Rooney PC

20070120117 - Semiconductor element and method of manufacturing the same: The present invention provides a semiconductor element having a semiconductor layer that has high carrier mobility and is easy to form. This semiconductor element includes a semiconductor layer made of TeI4, which has a clustering structure.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070120113 - Supramolecular structures and method for forming the same: A primary supramolecular structure is described. The primary supramolecular structure has a shape of ring-like disk. The shape of ring-like disk has a diameter of about 10 nanometers to about 60 nanometers. The mentioned primary supramolecular structure is formed by self-assembly of amphiphilic conjugate molecules. Moreover, a secondary supramolecular structure... Agent: Rosenberg, Klein & Lee

20070120124 - Resistance-switching oxide thin film devices: Resistance-switching oxide films, and devices therewith, are disclosed. Resistance-switching oxide films, according to certain preferred aspects of the present invention, include at least about 75 atomic percent of an insulator oxide matrix having a conducting material dopant in an amount up to about 25 atomic percent. The matrix and dopant... Agent: Woodcock Washburn LLP

20070120125 - Semiconductor integrated circuit device and method of testing the same: Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the... Agent: Hogan & Hartson L.L.P.

20070120126 - Organic light emitting display device and method for manufacturing the same: An organic light emitting display device and method for manufacturing the same is disclosed. The organic light emitting display device includes a driving circuit unit, a light emitting unit, and a common electric line. The driving circuit unit includes first and second thin film transistors arranged in a subpixel area... Agent: Knobbe Martens Olson & Bear LLP

20070120127 - Semiconductor device and semiconductor device production system: It is a problem to provide a semiconductor device production system using a laser crystallization method capable of preventing grain boundaries from forming in a TFT channel region and further preventing conspicuous lowering in TFT mobility due to grain boundaries, on-current decrease or off-current increase. An insulation film is formed... Agent: Eric Robinson

20070120128 - Semiconductor memory device: A semiconductor memory device includes a plurality of active regions, and a gate electrode in a fish bone shape arranged on each active region. In each active region, a plurality of source regions and a plurality of drain regions are arranged in a matrix manner. The source regions are commonly... Agent: Mcdermott Will & Emery LLP

20070120132 - Manufacturing method of light emitting device and manufacturing device thereof: The present invention provides a structure in which a pixel region 13 is surrounded by a first sealing material (having higher viscosity than a second sealing material) 16 including a spacer (filler, minute particles and/or the like) which maintains a gap between the two substrates, filled with a few drops... Agent: Eric Robinson

20070120129 - Rare earth doped layer or substrate for light conversion: A solid state light emitting device comprising an emitter structure having an active region of semiconductor material and a pair of oppositely doped layers of semiconductor material on opposite sides of the active region. The active region emits light at a predetermined wavelength in response to an electrical bias across... Agent: Koppel, Patrick & Heybl

20070120131 - Semiconductor device: In a photodetector where a circuit section, in which an interconnection is formed, is formed adjacent to a light receiving section, photo sensitivity within a light receiving surface is prevented from being nonuniform due to an interlayer insulating film at a periphery of the light receiving section being increased in... Agent: Oliff & Berridge, PLC

20070120130 - Thin-film device and method of manufacturing same: A thin-film device comprises: a substrate; a flattening film made of an insulating material and disposed on the substrate; and a capacitor provided on the flattening film. The capacitor incorporates: a lower conductor layer disposed on the flattening film; a dielectric film disposed on the lower conductor layer; and an... Agent: Oliff & Berridge, PLC

20070120133 - Semiconductor light emitting apparatus: Disclosed herein is a semiconductor light emitting apparatus that includes: a semiconductor light emitting device having a first semiconductor laminate structure including a light emitting region, and a light outgoing window permitting the light emitted from the light emitting region to go out therethrough in the lamination direction; a light... Agent: Robert J. Depke Lewis T. Steadman

20070120134 - Stem for optical element and optical semiconductor device using the same: A stem for an optical element includes a base-like portion located on a portion of a package side surface of an eyelet, higher than the package side surface. A block is located on a surface of the base-like portion of the eyelet. An optical element mounting surface of the block... Agent: Leydig Voit & Mayer, Ltd

20070120135 - Coated led with improved efficiency: An LED device including an LED chip and a lens positioned apart from the chip and coated with a uniform thickness layer of fluorescent phosphor for converting at least some of the radiation emitted by the chip into visible light. Positioning the phosphor layer away from the LED improves the... Agent: Fay Sharpe LLP

20070120136 - Light-emitting device and organic electroluminescence light-emitting device: In conventional organic EL light-emitting devices, the ITO used for a transparent electrode has a refractive index of about 2.0 larger than the refractive index of 1.5 of a transparent glass substrate. As a result, the mode of most of light traveling from the transparent electrode toward the glass substrate... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070120137 - Semiconductor-based lighting systems and lighting system components for automotive use: A modular semiconductor light source assembly includes a semiconductor light source, such as a light emitting diode, which is mounted on a substrate which supplies electricity to the light source and which assists in removing waste heat therefrom. Substantially all of the light emitted by the LED is transferred to... Agent: Warn, Hoffmann, Miller & Lalone, .p.c

20070120138 - Multi-layer light emitting device with integrated thermoelectric chip: A LED package having an LED chip and a thermoelectric device. The thermoelectric device a has a first side in thermal communication with the LED chip and a second side in thermal communication with a heat sink to create a thermal gradient between the LED chip and the heat sink.... Agent: Visteon

20070120140 - Semiconductor apparatus with thin semiconductor film: A semiconductor apparatus includes a substrate having at least one terminal, a thin semiconductor film including at least one semiconductor device, the thin semiconductor film being disposed and bonded on the substrate; and an individual interconnecting line formed as a thin conductive film extending from the semiconductor device in the... Agent: Rabin & Berdo, PC

20070120139 - Semiconductor light emitting device: A semiconductor light emitting device includes a mold resin having a cup shape portion on an upper surface of the mold resin. One or more holes penetrate through the cup shape portion to outside of the mold resin and/or one or more trenches extend from the cup-shaped portion to outside... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070120142 - Nitride semiconductor light-emitting device and method for manufacturing the same: There are provided a nitride semiconductor light-emitting device and a method for manufacturing the same. The nitride semiconductor light-emitting device includes a buffer layer on a sapphire substrate, wherein the buffer layer includes a plurality of layers having different lattice constants, a first n-type nitride semiconductor layer on the buffer... Agent: Birch Stewart Kolasch & Birch

20070120141 - Optical devices featuring textured semiconductor layers: A semiconductor sensor, solar cell or emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate. The textured layers enhance light extraction or absorption. Texturing in the region of multiple quantum wells greatly enhances internal quantum efficiency if the semiconductor is... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20070120143 - Organic light emitting diode display and method for manufacturing the same: In one embodiment, an organic light emitting diode (OLED) display is provided. The OLED display includes a substrate, a first signal line formed on the substrate, a second signal line intersecting the first signal line, a first thin film transistor connected to the first and second signal lines, a second... Agent: Macpherson Kwok Chen & Heid LLP

20070120144 - Semiconductor device having group iii nitride buffer layer and growth layers: An epitaxial growth system comprises a housing around an epitaxial growth chamber. A substrate support is located within the growth chamber. A gallium source introduces gallium into the growth chamber and directs the gallium towards the substrate. An activated nitrogen source introduces activated nitrogen into the growth chamber and directs... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20070120145 - Gate turn-off thyristor: A mesa-type wide-gap semiconductor gate turn-off thyristor has a low gate withstand voltage and a large leakage current. Since the ionization rate of P-type impurities greatly increases at high temperatures when compared with that at room temperature, the hole implantation amount increases and the minority carrier lifetime becomes longer. Consequently,... Agent: Nixon & Vanderhye, PC

20070120146 - Differential input/output device including electro static discharge (esd) protection circuit: A differential input/output device including an electro static discharge protection circuit is provided. The differential input/output device includes a P-type differential pair. The P-type differential pair includes two P-type transistors. The gate of each P-type transistor is coupled to an N-type transistor to protect the P-type transistor when CDM ESD... Agent: Jianq Chyun Intellectual Property Office

20070120147 - Gallium nitride material transistors and methods associated with the same: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission... Agent: Wolf Greenfield & Sacks, P.C.

20070120148 - Hetero-junction bipolar transistor: A hetero-junction bipolar transistor includes a sub-collector layer formed on a substrate and having conductivity, a first collector layer formed on the sub-collector layer and a second collector layer formed on the first collector layer and having the same conductive type as a conductive type of the sub-collector layer. In... Agent: Mcdermott Will & Emery LLP

20070120149 - Package stiffener: Arrangements are used to supply power to a semiconductor package.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070120151 - Non-volatile memory: A NVM including a substrate, a control gate layer, a charge storage layer, a tunneling layer, a charge barrier layer, a gate dielectric layer and a first doping region is described. The control gate layer is disposed in a first trench of the substrate; the charge storage layer is disposed... Agent: Jianq Chyun Intellectual Property Office

20070120150 - Semiconductor component arrangement and method for fabricating it: A semiconductor component arrangement is disclosed. In one embodiment, the semiconductor component arrangement includes a power transistor formed within a semiconductor layer in at least one first region and further semiconductor components formed at least in a second region, an effective thickness of the semiconductor layer being smaller in the... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070120152 - Gate-in-panel type liquid crystal display device and method of fabricating the same: A liquid crystal display device comprises: a first substrate and a second substrate facing and spaced apart from each other, the first substrate and the second substrate including an active area, a signal input area and a pad area, the signal input area and the pad area being disposed at... Agent: Mckenna Long & Aldridge LLP

20070120153 - Rugged mesfet for power applications: A rugged MESFET for power applications includes a drain region surrounded by a ring shaped gate. The gate is surrounded, in turn by a source region. This eliminates the high-field point between gate and drain along the device's etched mesa surface and results in improved avalanche capability.... Agent: Advanced Analogic Technologies

20070120155 - Colors only process to reduce package yield loss: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical... Agent: Duane Morris, LLPIPDepartment

20070120156 - Enhanced segmented channel mos transistor with multi layer regions: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges... Agent: Silcon Valley Patent Group LLP

20070120154 - Finfet structure with multiply stressed gate electrode: A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress which is different than... Agent: Scully Scott Murphy & Presser, PC

20070120159 - Cmos image sensor having duble gate insulator therein and method for manufacturing the same: A method for manufacturing a CMOS image sensor includes: preparing a semiconductor substrate incorporating therein a p-type epitaxial layer by epitaxially growing up an upper portion of the semiconductor substrate; forming a pixel array in one predetermined location of the semiconductor substrate, the pixel array having a plurality of transistors... Agent: Blakely Sokoloff Taylor & Zafman

20070120158 - High dynamic range image sensor: A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a dual purpose, acting as both a leaking transistor and either a transfer gate or a reset gate. Alternatively, the HDR transistor may... Agent: Dickstein Shapiro LLP

20070120157 - Organic light emitting display device: Disclosed is an organic light emitting display, which includes a large quantity of a hydroscopic layer having a good hydroscopic ability by changing a mounting structure of the hydroscopic layer. An organic light emitting display includes a first substrate. An organic emission portion is formed at one surface of the... Agent: Knobbe Martens Olson & Bear LLP

20070120161 - Method and structure to reduce optical crosstalk in a solid state imager: Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away and disposed of as waste during fabrication are left as conserved sections. These conserved sections are used to amend the properties and performance of the imager... Agent: Dickstein Shapiro LLP

20070120160 - Semiconductor device having enhanced photo sensitivity and method for manufacture thereof: Provided are a semiconductor device and a method for its manufacture. In one example, the method includes forming an isolation structure having a first refraction index over a sensor embedded in a substrate. A first layer having a second refraction index that is different from the first refraction index is... Agent: Haynes And Boone, LLP

20070120163 - Complementary metal oxide semiconductor image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same is disclosed, to enhance the image-sensing efficiency by forming a concave lens area for improving the light-condensing efficiency in a planarization layer formed before a micro-lens array, in which the CMOS image sensor includes a plurality of photosensitive devices... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070120162 - Method and apparatus for blocking light to peripheral circuitry of an imager device: Methods and apparatuses are disclosed which provide imager devices having a light blocking material layer formed over peripheral circuitry outside a pixel cell array.... Agent: Dickstein Shapiro LLP

20070120164 - Film forming method and oxide thin film element: The invention provides a method of forming, on a substrate, a thin film of a perovskite type oxide in which at least either of a site A and a site B is constituted of plural elements and the plural elements in at least either site include elements different in valence... Agent: Fitzpatrick Cella Harper & Scinto

20070120167 - Large-area nanoenabled macroelectronic substrates and uses therefor: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor... Agent: Nanosys Inc.

20070120166 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a semiconductor substrate. Active regions are formed on the surface of the substrate, separated from one another by element separating regions and extend in a first direction. A first word line and a second word line extend in a second direction crossing the first... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070120165 - Semiconductor device with ferroelectric capacitor and fabrication method thereof: A semiconductor device fabrication method includes the steps of forming a conductive plug in an insulating layer on a semiconductor substrate so as to be connected to an element on the substrate; forming a titanium aluminum nitride (TiAlN) oxygen barrier film over the conductive plug; forming a titanium (Ti) film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070120168 - Metal semiconductor field effect transistors (mesfets) having channels of varying thicknesses and related methods: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The unit cell includes a MESFET having a source, a drain and a gate. The gate is between the source and the drain and on a channel layer of the MESFET. The channel layer has a first thickness on... Agent: Elizabeth A. Stanek Myers Bigel Sibley & Sajovec, P.A.

20070120169 - Trench capacitor: A trench capacitor including a substrate, at least a group of capacitor units, an isolation structure and a conductive layer is described. The substrate includes a first trench and a second trench. The group of capacitor units is disposed in the substrate. The group of capacitor units includes a first... Agent: Jianq Chyun Intellectual Property Office

20070120170 - Vertical semiconductor device: A vertical semiconductor device comprises a semiconductor body, a first contact and a second contact, wherein a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and a third semiconductor region of a second conductivity type are formed in the semiconductor body... Agent: Maginot, Moore & Beck Chase Tower

20070120175 - Eeprom: An EEPROM having a nonvolatile memory cell is provided. The nonvolatile memory cell has: a first well formed in a substrate; a floating gate formed on the substrate through a gate insulating film to overlap a first region of the first well; first and second diffusion layers formed in the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070120172 - Logic compatible non-volatile memory cell: A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a semiconductor substrate, a floating gate over the semiconductor substrate, a first, a second, and a third capacitor each having a first plate and sharing a common floating gate as a second... Agent: Slater & Matsil, L.L.P.

20070120173 - Non-volatile memory cell with high current output line: A memory cell having a low current memory device and a relatively high current output amplifier device, all built in the areawise footprint occupied by the memory device only. The low current memory device is a layered n-MOS or p-MOS lateral device having laterally spaced source and drain electrodes in... Agent: Schneck & Schneck

20070120171 - Nonvolatile memory cell with multiple floating gates and a connection region in the channel: A memory cell (110) has a plurality of floating gates (120L, 120R). The channel region (170) comprises a plurality of sub-regions (220L, 220R) adjacent to the respective floating gates, and a connection region (210) between the floating gates. The connection region has the same conductivity type as the source/drain regions... Agent: Macpherson Kwok Chen & Heid LLP

20070120174 - Sram devices based on resonant tunneling: The present invention discloses a resonant tunneling device. Further, the present invention discloses a memory storage device utilizing a resonant tunneling barrier. Moreover, the present invention teaches an SRAM circuit utilizing a resonant tunneling device. Additionally, the present invention teaches an NROM and NAND device utilizing a resonant tunneling barrier.... Agent: Perkins Coie LLP

20070120176 - Eeprom: An EEPROM having a nonvolatile memory cell is provided. The nonvolatile memory cell has: a first well formed in a substrate; a floating gate formed on the substrate through a gate insulating film to overlap a first region of the first well; and first and second diffusion layers formed in... Agent: Mcginn Intellectual Property Law Group, PLLC

20070120177 - Electrochemical cell structure and method of fabrication: A method of forming a metal oxide layer having metal oxide particles and a binder for an electrochemical cell, comprises: depositing a layer of metal oxide; and depositing a polymeric linking agent onto the layer of metal oxide. Additionally, a method of forming an electrochemical cell comprises forming a metal... Agent: Oliff & Berridge, PLC

20070120178 - Electrochemical cell structure and method of fabrication: A method of forming a metal oxide layer for an electrochemical cell is provided. The method includes: forming a plurality of adjacent metal oxide cells, spaced from one another; and performing localised heating of the plurality of adjacent metal oxide cells. A method of forming an electrochemical cell is also... Agent: Oliff & Berridge, PLC

20070120179 - Sonos type non-volatile memory devices having a laminate blocking insulation layer and methods of manufacturing the same: A SONOS type non-volatile memory device includes a substrate having source/drain regions doped with impurities and a channel region between the source/drain regions. A tunnel insulation layer including silicon oxide is formed on the channel region of the substrate. A charge-trapping insulation layer including silicon nitride is formed on the... Agent: Myers Bigel Sibley & Sajovec

20070120180 - Transition areas for dense memory arrays: A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory... Agent: Eitan Law Group C/o Landonip, Inc.

20070120181 - Power igbt with increased robustness: A power IGBT includes a semiconductor body having an emitter zone of a first conduction type and a drift zone of a second conduction type proximate to the emitter zone. The IGBT further includes a cell array, each transistor cell of the array having a source zone, a body zone... Agent: Maginot, Moore & Beck Chase Tower

20070120183 - Integrated circuit devices having active regions with expanded effective widths: An integrated circuit device includes a substrate having a trench formed therein. An isolation layer is disposed in the trench so as to cover a first sidewall portion of the trench and an entire bottom of the trench without covering a second sidewall portion of the trench. A buffer layer... Agent: D. Scott Moore Myers Bigel Sibley & Sajovec, P.A.

20070120182 - Transistor having recess gate structure and method for fabricating the same: A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches;... Agent: Marshall, Gerstein & Borun LLP

20070120184 - Enhanced resurf hvpmos device with stacked hetero-doping rim and gradual drift region: An HV PMOS device formed on a substrate having an HV well of a first polarity type formed in an epitaxial layer of a second polarity type includes a pair of field oxide regions on the substrate and at least partially over the HV well. Insulated gates are formed on... Agent: Hiscock & Barclay, LLP

20070120185 - Semiconductor device manufacturing method and semiconductor device: A method for manufacturing a semiconductor device includes forming an isolation region on a semiconductor substrate; forming an impurity diffusion layer in a region which includes an end of an active area adjacent to the isolation region; depositing a metal film on the semiconductor substrate; removing at least part of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070120186 - Engineered barrier layer and gate gap for transistors with negative differential resistance: A negative differential resistance (NDR) transistor includes a gate stack formed from a gate, a barrier layer, and a dielectric layer formed between the gate and barrier layer. To enable the NDR characteristic of the transistor, the barrier layer is configured to dynamically transfer charge carriers to and from the... Agent: Bever, Hoffman & Harms, LLP

20070120189 - Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. An amorphous semiconductor thin film is irradiated with ultraviolet light or infrared light, to obtain a crystalline semiconductor thin film (102). Then, the crystalline semiconductor thin film (102) is... Agent: Eric Robinson

20070120187 - Lateral soi semiconductor device: This invention is generally concerned with semiconductor-on-insulator devices, particularly for high voltage applications. A lateral semiconductor-on-insulator device is described, comprising: a semiconductor substrate; an insulating layer on said semiconductor substrate; and a lateral semiconductor device on said insulator; said lateral semiconductor device having: a first region of a first conductivity... Agent: Tarolli, Sundheim, Covell & Tummino L.L.P.

20070120188 - Light-emitting device and electronic apparatus: A light-emitting device includes a drive transistor that controls a current to be supplied to a light-emitting element from a power supply line, an electrical continuity portion that electrically connects the drive transistor with the light-emitting element, an initializing transistor that is turned ON to diode-connect the drive transistor, and... Agent: Oliff & Berridge, PLC

20070120190 - Electrostatic discharge (esd) protection structure and a circuit using the same: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure comprises an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the... Agent: Sawyer Law Group LLP

20070120191 - High trigger current electrostatic discharge protection device: An electrostatic discharge protection device with a high trigger current includes a semiconductor layer, a well region formed in the semiconductor layer, an anode region formed in the well region, a cathode region formed in the semiconductor layer, a bridging region bridging a junction between the semiconductor layer and the... Agent: Kinney & Lange, P.A.

20070120192 - Method and apparatus that provides differential connections with improved esd protection and routing: The present invention provides a single ESD device package that can be used to provide ESD protection to multiple high-speed lines, in particular multiple high-speed differential lines. The present invention has various aspects. Minute parasitic matching is achieved within a single package, and TMDS signal discontinuities are reduced by allowing... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070120193 - Esd protection device: An ESD protection device includes: a semiconductor substrate of a first conductivity type having a first major surface and a second major surface; a signal input electrode formed on the first major surface of the semiconductor substrate; a base region of a second conductivity type formed on a surface region... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070120194 - Semiconductor device and a method of manufacturing the same: A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as... Agent: Stanley P. Fisher Reed Smith LLP

20070120195 - Cmos circuits incorporating passive elements of low contact resistance, and methods of forming same: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end... Agent: Scully Scott Murphy & Presser, PC

20070120197 - Method and structure for enhancing both nmosfet and pmosfet performance wth a stressed film: A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or... Agent: International Business Machines Corporation Dept. 18g

20070120196 - Prevention of latch-up among p-type semiconductor devices: This invention discloses a semiconductor device with latch-up prevention mechanisms. According to one embodiment, it comprises a first N-type region, wherein one or more P-type metal-oxide-semiconductor (PMOS) devices are disposed therein, a second N-type region adjacent to the first N-type region, wherein one or more PMOS devices are also disposed... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070120198 - Latch-up prevention in semiconductor circuits: This invention discloses a semiconductor device with latch-up prevention mechanisms. According to one embodiment, it comprises a first N-type region, wherein one or more P-type metal-oxide-semiconductor (PMOS) devices are disposed therein, a second N-type region adjacent to the first N-type region, wherein one or more PMOS devices are also disposed... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070120199 - Low resistivity compound refractory metal silicides with high temperature stability: Compound refractory metal suicides are formulated to exhibit low resistivity and high temperature stability. Embodiments include various types of semiconductor devices comprising source/drain regions with a compound refractory metal silicide layer thereon, having a resistivity of 1 ohm.μ to 10 ohm.μ and stable at temperatures up to 1100° C.... Agent: Mcdermott Will & Emery LLP

20070120200 - Mos transistor having double gate and manufacturing method thereof: There are provided a MOS transistor having a double gate and a manufacturing method thereof. The MOS transistor includes a substrate on which an insulating layer is formed, a first gate embedded in the insulating layer, in which the top surface of the first gate is exposed, a first gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070120201 - Semiconductor device having super junction mos transistor and method for manufacturing the same: A semiconductor device having a super junction MOS transistor includes: a semiconductor substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; a channel forming region on a first surface portion of the second semiconductor layer; a source region on a first surface... Agent: Posz Law Group, PLC

20070120202 - Semiconductor integrated circuit device and method of testing the same: Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the... Agent: Hogan & Hartson L.L.P.

20070120203 - Semiconductor device and method for manufacturing the semiconductor devices: A semiconductor device includes a semiconductor substrate on which a source region and a drain region are formed, an insulating film formed on the semiconductor substrate and interposed between the source region and the drain region, a gate electrode formed on the insulating film, metal-bearing particles formed on the interface... Agent: Mcdermott Will & Emery LLP

20070120204 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor substrate containing silicon, a p-type semiconductor active region formed on the semiconductor substrate, a first gate insulating film containing at least one of Zr and Hf and formed on the p-type semiconductor active region, a first gate electrode formed on the first gate insulating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070120205 - Physical quantity sensor having multiple through holes: A semiconductor physical quantity sensor includes: a substrate; a semiconductor layer supported on the substrate; a trench disposed in the semiconductor layer; and a movable portion disposed in the semiconductor layer and separated from the substrate by the trench. The movable portion includes a plurality of through-holes, each of which... Agent: Posz Law Group, PLC

20070120206 - Semiconductor optical device having current-confined structure: Provided is a semiconductor optical device having a current-confined structure. The device includes a first semiconductor layer of a first conductivity type which is formed on a semiconductor substrate and includes one or more material layers, a second semiconductor layer which is formed on the first semiconductor layer and includes... Agent: Blakely Sokoloff Taylor & Zafman

20070120207 - Torsion spring for mems structure: A torsion spring for a micro-electro-mechanical system (MEMS) structure is provided. The torsion spring is connected between a pivoting member and a fixed member and supports the pivoting member so that the pivoting member can pivot about the torsion spring. The torsion spring includes: a horizontal beam; at least one... Agent: Sughrue Mion, PLLC

20070120208 - Wide bandgap semiconductor based field effect transistors: A field effect transistor includes a wide bandgap semiconductor substrate including a source region, a drain region, and an intermediate region situated between the source region and the drain region. The intermediate region forms a gate channel of the field effect transistor upon application of a stimulus to the intermediate... Agent: General Electric Company Global Research

20070120211 - Magnetic elements with spin engineered insertion layers and mram devices using the magnetic elements: A method and system for providing a magnetic element are described. The method and system include providing a single pinned layer, a free layer, and a spacer layer between the pinned and free layers. The spacer layer is nonmagnetic. The magnetic element is configured to allow the free layer to... Agent: Sawyer Law Group LLP

20070120209 - Magnetic field shaping conductor: The present invention provides an integrated circuit arrangement having at least one electrical conductor (40) which, when a current flows through it, produces a magnetic field which acts on at least a further part of the circuit arrangement. The electrical conductor (40) has a first side oriented towards the at... Agent: Philips Intellectual Property & Standards

20070120210 - Spacer structure in mram cell and method of its fabrication: Methods are presented for fabricating an MTJ element having a precisely controlled spacing between its free layer and a bit line and, in addition, having a protective spacer layer formed abutting the lateral sides of the MTJ element to eliminate leakage currents between MTJ layers and the bit line. Each... Agent: George O. Saile

20070120212 - Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers: Microelectronic imagers with shaped image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device comprises an imaging die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry... Agent: Dickstein Shapiro LLP

20070120213 - Wire under dam package and method for packaging image-sensor: An wire under dam package and method for packaging image-sensor. The image-sensor package includes: a substrate having a first surface and a second surface, a sensing chip being laid on the first surface, the sensing chip having multiple soldering pads; multiple inner electric contacts arranged on the first surface, the... Agent: Rosenberg, Klein & Lee

20070120214 - Method and structure to reduce optical crosstalk in a solid state imager: Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away and disposed of as waste during fabrication are left as conserved sections. These conserved sections are used to amend the properties and performance of the imager... Agent: Dickstein Shapiro LLP

20070120215 - Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same: Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at... Agent: Hiscock & Barclay, LLP

20070120216 - Low cost bonding pad and method of fabricating same: A structure and a method of forming the structure. The structure including: an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene, dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric... Agent: Schmeiser, Olsen & Watts

20070120217 - Circuit arrangement for buck converters and method for producing a power semiconductor component: A circuit arrangement for buck converters has a multiplicity of half bridges (10, 11). Each half bridge (10, 11) contains a first chip (HS1, HS2, HS3, HS4) and a second chip (LS1, LS2, LS3, LS4) , the first chip (HS1, HS2, HS3, HS4) and the second chip (LS1, LS2, LS3,... Agent: Baker Botts, L.L.P.

20070120218 - Cmos compatible shallow-trench efuse structure and method: A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopant region that is located within the semiconductor substrate. The present invention... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070120219 - Conductive layer, manufacturing method of the same, and signal transmission substrate: There is provided a method of manufacturing a conductive layer of in a signal transmission substrate. The method includes sewing conductive thread in sheet-like material having an insulating property so as to form one of a plurality of low resistance regions using the conductive thread in a high resistance region... Agent: Greenblum & Bernstein, P.L.C

20070120221 - Electronically programmable antifuse and circuits made therewith: An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state,... Agent: Downs Rachlin Martin PLLC

20070120220 - Methods of compensating for an alignment error during fabrication of structures on semiconductor substrates: In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows... Agent: Myers Bigel Sibley & Sajovec

20070120222 - Method for manufacturing semiconductor silicon substrate and apparatus for manufacturing the same: This invention provides a method for manufacturing a semiconductor silicon substrate by use of carbon dioxide in a supercritical state, which method is capable of making the semiconductor silicon substrate highly reliable one. Specifically, this invention provides a method for manufacturing a semiconductor silicon substrate including at least two of:... Agent: Mcdermott Will & Emery LLP

20070120223 - Circuit and method for suppression of electromagnetic coupling and switching noise in multilayer printed circuit boards: Apparatus for suppressing noise and electromagnetic coupling in the printed circuit board of an electronic device includes an upper conductive plate and an array of conductive coplanar patches positioned a distance t2 from the upper conductive plate. The distance t2 is chosen to optimize capacitance between the conductive coplanar patches... Agent: Brinks Hofer Gilson & Lione

20070120224 - Passivation structure with voltage equalizing loops: A semiconductor device which includes a passivation structure formed with a conductive strip of resistive material that crosses itself once around the active region of the device to form a first closed loop, a continuous strip that loops around the first closed loop without crossing itself which crosses itself a... Agent: Ostrolenk, Faber, Gerb & Soffen, LLP

20070120225 - Packaging having an array of embedded capacitors for power delivery and decoupling in the mid-frequency range and methods of forming thereof: One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz comprising installing in said package an array of embedded discrete ceramic capacitors, and optionally planar capacitor layers. A further embodiment... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070120226 - Avalanche photodiode: An avalanche photodiode has improved low-noise characteristics, high-speed response characteristics, and sensitivity. The avalanche photodiode includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, a semiconductor multiplication layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a semiconductor... Agent: Leydig Voit & Mayer, Ltd

20070120227 - Heating device of the light irradiation type: To devise a heating device of the light irradiation type in which costs can reduced by reducing the number of filament lamps and current source parts without adversely affecting the illuminance distribution with respect to a wafer, in a heating device of the light irradiation type that has a light... Agent: Roberts, Mlotkowski & Hobbes

20070120228 - Semiconductor wafer and manufacturing method therefor: A plurality of IC regions are formed on a semiconductor wafer, which is cut into individual chips incorporating ICs, wherein wiring layers and insulating layers are sequentially formed on a silicon substrate. In order to reduce height differences between ICs and scribing lines, a planar insulating layer is formed to... Agent: Dickstein Shapiro LLP

20070120229 - Wet etched insulator and electronic circuit component: The present invention relates to an insulator as an insulating layer in a laminate which can inhibit dusting at the time of use, more particularly an electronic circuit component to which the insulator has been applied, particularly a wireless suspension. The insulator comprises a laminate of one or more insulation... Agent: Oliff & Berridge, PLC

20070120230 - Layer structure, method of forming the layer structure, method of manufacturing a capacitor using the same and method of manufacturing a semiconductor device using the same: In a layer structure, a method of forming the layer structure, a method of manufacturing a capacitor having the layer structure and a method of manufacturing a semiconductor device having the capacitor, a structure may be formed on a substrate. A first insulation layer including at least one kind of... Agent: Harness, Dickey & Pierce, P.L.C

20070120231 - Transmission cable and method for manufacturing the same: A transmission cable and method for manufacturing same are provided. A plurality of signal lines are formed on one side of an insulating layer and ground lines are formed between the signal lines. The ground lines are electrically connected with a shield layer formed on a back surface of the... Agent: Bell, Boyd & Lloyd, LLP

20070120232 - Laser fuse structures for high power applications: The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b), at least one conductive fusible link (14), first and second connection elements (20a, 20b), and first and second metal... Agent: Scully, Scott, Murphy & Presser, P.C.

20070120233 - Leadframes for improved moisture reliability and enhanced solderability of semiconductor devices: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (302) and a plurality of lead segments (303). Covering the base metal are, consecutively, a continuous nickel layer (201) on the base metal, a layer of... Agent: Texas Instruments Incorporated

20070120234 - Side view light emitting diode package: A side view LED package for a backlight unit includes a package body having a cavity with an inclined inner sidewall, first and second lead frames arranged in the package body, the cavity of the package body exposing a portion of at least one of the first and second lead... Agent: Mcdermott Will & Emery LLP

20070120235 - Wiring board and method for manufacturing the same, and semiconductor device: A wiring board according to the present invention includes: an insulating base 22; a plurality of first conductor wirings 23a aligned in an inner region on the insulating base; bumps 24 formed on the respective first conductor wirings; and a protective film 25a that is formed on the insulating base... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070120236 - Semiconductor device: To minimize distance from a power supply or ground line of a semiconductor integrated circuit of a semiconductor device to electrodes of a printed board, a power supply electrode or ground line of the semiconductor integrated circuit is connected to a metal film through openings provided in a protective film... Agent: Sughrue Mion, PLLC

20070120237 - Semiconductor integrated circuit: To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070120238 - Semiconductor/printed circuit board assembly, and computer system: A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die... Agent: Dinsmore & Shohl LLP

20070120239 - Method and apparatus for full-chip thermal analysis of semiconductor chip designs: A method and apparatus for full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal analysis of a semiconductor chip design comprises receiving at least one input relating to a semiconductor chip design to be analyzed. The input is then processed to... Agent: Moser, Patterson & Sheridan, LLP

20070120240 - Circuit substrate and method of manufacture: An aspect of the present invention comprises a method of producing a circuit substrate comprising providing a substrate, coating the substrate with a conductive layer, patterning the conductive layer to form at least two circuits joined by a buss-line and forming a slot in the substrate beneath the buss-line. Another... Agent: 3m Innovative Properties Company

20070120243 - Assembly jig and manufacturing method of multilayer semiconductor device: There are provided a base member 14, a position restriction mechanism 15, a height restriction mechanism 17, an evenness holding mechanism, and an alignment mechanism 20, 22. A plurality of semiconductor modules is serially layered on the base member. Each semiconductor module comprises a semiconductor chip 7 mounted on a... Agent: Robert J. Depke Lewis T. Steadman

20070120241 - Pin-type chip tooling: An apparatus for use with multiple chips having multiple posts as to engage at least a portion of a surface of one of the multiple chips, a frame configured to releasably constrain each of the posts so that, when unconstrained, each individual post can contact an individual chip and, when... Agent: Morgan & Finnegan, L.L.P.

20070120242 - Semiconductor device and method of fabricating the same: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a lower wire, an interlayer insulating film formed on the lower wire and having a via hole exposing the upper surface of the lower wire, a diffusion barrier formed on the inner wall of... Agent: Mills & Onello LLP

20070120245 - Semiconductor device: Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070120244 - Semiconductor device having electrostatic breakdown protection element: A semiconductor device (1) comprises a semiconductor substrate (2) on which an integrated circuit (3, 4) is formed, a first ground terminal (7) and a second ground terminal (8) for electrically connecting the integrated circuit (3, 4) to an external ground electrode, and an electrostatic breakdown protection element (5) for... Agent: Ratnerprestia

20070120246 - Interposer and stacked chip package: An interposer may include a base substrate supporting an array of conductive lands. The conductive land may have an identical shape and size. The conductive lands may be provided at regular intervals on the base substrate. The conductive land pitch may be determined such that adjacent conductive lands may be... Agent: Harness, Dickey & Pierce, P.L.C

20070120247 - Semiconductor packages having leadframe-based connection arrays: Methods of forming a semiconductor assembly are described which include a leadframe with leads having offset portions exposed at an outer surface of a material package to form a grid array. An electrically conductive compound, such as solder, may be disposed or formed on the exposed lead portions to form... Agent: Trask Britt, P.C./ Micron Technology

20070120248 - Semiconductor device: There is disclosed a semiconductor device comprising at least two substrates, at least one wiring being provided in each of the substrates, the substrates being stacked such that major surfaces on one side of each thereof oppose each other and the wirings being connected between the major surfaces, and a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070120249 - Circuit substrate and manufacturing method thereof: A circuit substrate includes a plurality of dielectric members and a plurality of wiring patterns. The plurality of wiring patterns are stacked on one another through the plurality of dielectric members. The plurality of dielectric members includes a mount dielectric member. A first wiring pattern of the plurality of wiring... Agent: Posz Law Group, PLC

20070120250 - Thermal conductive electronics substrate and assembly: An electronics assembly is provided including a circuit board substrate having a top surface and a bottom surface and a plurality of thermal conductive vias extending from the top surface to the bottom surface. At least one electronics package is mounted to the top surface of the substrate. A heat... Agent: Delphi Technologies, Inc.

20070120252 - Nano-wire electronic device: An electronic device such as a sensor or a NEMS. The electronic device comprises at least one substrate; a plurality of electrodes disposed on the substrate; and at least one nano-wire growing from an edge of a first electrode to an edge of a second electrode. A method for making... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20070120251 - Semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment: A semiconductor wafer includes a redistribution layer which is electrically connected with a pad which is an end portion of an interconnect, a first resin layer which is formed over the redistribution layer, a second resin layer which is formed over the first resin layer and covers the side surface... Agent: Oliff & Berridge, PLC

20070120253 - Core substrate and multilayer printed circuit board using paste bumps and manufacturing method thereof: A core substrate and multilayer printed circuit board using paste bumps and manufacturing method thereof are disclosed. With the method of manufacturing a core substrate using paste bumps comprising: (a) aligning a pair of paste bump boards, each of which has a plurality of paste bumps joined to its surface,... Agent: Staas & Halsey LLP

20070120254 - Semiconductor device comprising a pn-heterojunction: An electric device is disclosed comprising a pn-heterojunction (4) formed by a nanowire (3) of 111-V semiconductor material and a semiconductor body (1) comprising a group IV semiconductor material. The nanowire (3) is positioned in direct contact with the surface (2) of the semiconductor body (1) and has a first... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070120255 - Semiconductor chip having island dispersion structure and method for manufacturing the same: The present invention has an object to provide a semiconductor chip of high reliability with less risk of breakage. Specifically, the present invention provides a semiconductor chip having a semiconductor silicon substrate including a semiconductor device layer and a porous silicon domain layer, the semiconductor device layer being provided in... Agent: Mcdermott Will & Emery LLP

20070120259 - Detection of residual liner materials after polishing in damascene process: A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070120261 - Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device: A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are... Agent: Blakely Sokoloff Taylor & Zafman

20070120256 - Reinforced interconnection structures: Reinforced interconnection structures are provided. A reinforced interconnection structure comprises a first conductive layer formed in a first dielectric layer. A second conductive layer is formed in a second dielectric layer which overlies the first dielectric layer. A third conductive layer formed in a third dielectric layer which overlies the... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070120258 - Semiconductor device: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad... Agent: Miles & Stockbridge PC

20070120260 - Semiconductor integrated circuit wiring design method and semiconductor integrated circuit: The facility of operation in a manufacturing process and the reliability of the finished product can be improved by making a design based on two basic wiring pattern layers in which wiring traces are formed with regularity, and a basic via array layer inserted between the two basic wiring pattern... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070120257 - Semiconductor integrated circuit with improved power supply system: Cells are formed on a substrate. First and second cell power wiring lines extend in a first direction on the substrate. First and second intermediate layer power wiring lines are formed on the first and second cell power lines. First upper layer power wiring lines are formed on the first... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070120262 - Semiconductor device and method for manufacturing the same: Embodiments relate to a semiconductor device and a method for manufacturing the same. Embodiments may include forming a lower porous oxide layer on a semiconductor substrate having a conductive layer, forming a pyrolytic polymer layer on the lower porous oxide layer, forming an upper porous oxide layer on the pyrolytic... Agent: Sherr & Nourse, PLLC

20070120263 - Conductor track arrangement and associated production method: A conductor track arrangement includes a substrate, at least two conductor tracks, a cavity and a resist layer that covers the conductor tracks and closes off the cavity. By forming carrier tracks with a width less than a width of the conductor tracks, air gaps can also be formed laterally... Agent: Brinks Hofer Gilson & Lione

20070120264 - A semiconductor having a copper-based metallization stack with a last aluminum metal line layer: By replacing, in an otherwise copper-based metallization stack, copper with aluminum in the very last metal line layer, the respective terminal metal layer of conventional semiconductor devices may be omitted. Consequently, an enormous gain in production cost savings may be achieved, since a plurality of process steps may be omitted,... Agent: Williams, Morgan & Amerson

20070120265 - Semiconductor device and its manufacturing method: A semiconductor device comprises at least one first electrode 11b provided on the front surface of a semiconductor chip and electrically connected to at least one of electrodes that constitute a transistor, a second electrode 9 provided on the back surface of the semiconductor chip and electrically connected to one... Agent: Harness, Dickey & Pierce, P.L.C

20070120266 - Chip resistor: Format data is subjected to the last memory function for each of one or more external inputs, and when the same input is re-selected in the next time or the power is turned on again, the data already subjected to the last memory function is output as an image with... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070120267 - Multi chip module: The present invention provides a multi chip module which realizes high functions or high performances thereof. A multi chip module is constituted by stacking a first semiconductor chip on which a digital signal processing circuit is mounted, a second semiconductor chip which constitutes a dynamic random access memory, a third... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070120270 - Flip chip hermetic seal using pre-formed material: A flip chip architecture providing a hermetic seal. A flip chip die is assembled so as to be in contact with a package substrate. A pre-form of seal material is placed such that it surrounds the flip chip die and is in contact with the package substrate. The pre-form material... Agent: Smith, Gambrell & Russell

20070120269 - Flip chip package and manufacturing method of the same: A flip chip package including a chip structure, a substrate and an under-fill is provided. The chip structure includes a base, a number of pads, a first passivation layer, a second passivation layer and a number of bumps. The pads are formed on the base. The first passivation layer is... Agent: Birch Stewart Kolasch & Birch

20070120268 - Intermediate connection for flip chip in packages: An electronic component includes a substrate having contacts and a chip having contacts and a passivation layer disposed on an active side of the chip. The active side of the chip is mounted on a first surface of the substrate by flip chip technology such that the contacts of the... Agent: Slater & Matsil LLP

20070120271 - Dicing and die bonding adhesive tape: A dicing and die bonding tape, comprising a substrate 1, a pressure sensitive adhesive layer (A) 2 superimposed on the substrate 1, a substrate 3 superimposed on the pressure sensitive adhesive layer (A) 2, a pressure sensitive adhesive layer (B) 4 superimposed on the substrate 3, and an adhesive layer... Agent: Birch Stewart Kolasch & Birch

20070120272 - Electronic component and manufacturing method of the electronic component: In an electronic component in which a semiconductor device such as a light emitting diode is encapsulated by an encapsulation resin and a manufacturing method of the same, formation of flash on occasion of filling a resin is prevented. The semiconductor device (SIC) is mounted in a reception concavity of... Agent: Greenblum & Bernstein, P.L.C

20070120273 - Method for disposing a conductor structure on a substrate, and substrate comprising said conductor structure: A separable connection is created between at least one transfer support and the conductor structure. The transfer support including the conductor structure and the substrate are joined together such that a connection that is stronger than the separable connection between the transfer support and the conductor structure is created between... Agent: Staas & Halsey LLP

20070114508 - Reversible resistivity-switching metal oxide or nitride layer with added metal: A layer of resistivity-switching metal oxide or nitride can attain at least two stable resistivity states. Such a layer may be used in a state-change element in a nonvolatile memory cell, storing its data state, for example a “0” or a “1”, in this resistivity state. Including additional metal atoms... Agent: Patent Dept., Sandisk 3d LLC(matrix)

20070114509 - Memory cell comprising nickel-cobalt oxide switching element: Oxides of both nickel and cobalt have lower resistivity than either nickel oxide or cobalt oxide. Nickel oxide and cobalt oxide can be reversibly switched between two or more stable resistivity states by application of suitable electrical pulses. It is expected that oxides including both nickel and cobalt, or (NixCoy)O,... Agent: Patent Dept., Sandisk 3d LLC(matrix)

20070114510 - Electrically rewritable non-volatile memory element: A non-volatile semiconductor memory device includes a plurality of lower electrodes arranged in a matrix manner, a plurality of recording layer patterns, each being arranged on the lower electrode, that contain a phase change material, and an interlayer insulation film that is provided between the lower electrode and the recording... Agent: Mcdermott Will & Emery LLP

20070114514 - Light emitting device: A light emitting device includes: a light emitting element; and a substantially rectangular package body in which the light emitting element is contained and a concave portion is formed. The concave portion has a bottom surface on which the light emitting element is disposed, and is filled with a transparent... Agent: Morrison & Foerster LLP

20070114512 - Light emitting element and light emitting device using the same: An object of the prevent invention is to provide a light emitting element having slight increase in driving voltage with accumulation of light emitting time. Another object of the invention is to provide a light emitting element having slight increase in resistance value with increase in film thickness. A light... Agent: Eric Robinson

20070114511 - Lll-nitride compound semiconductor light emiting device: The present invention relates to a HI-nitride semiconductor light-emitting device having high external quantum efficiency, provides a HI-nitride compound semiconductor light-emitting device including an active layer generating light by recombination of electrons and holes and containing gallium and nitrogen, an n-type Al(x)ln(y)Ga(1-x-y)N layer epitaxially grown before the active layer is... Agent: Blackwell Sanders Peper Martin LLP

20070114515 - Nitride semiconductor device having a silver-base alloy electrode: An LED is disclosed which comprises a nitride-made main semiconductor region formed on a substrate for generating light, and an electrode formed on the main semiconductor region to a thickness sufficiently small to transmit the light from the main semiconductor region. The electrode is made from a silver-base alloy, rather... Agent: Woodcock Washburn LLP

20070114513 - Semiconductor laser and method for manufacturing semiconductor laser: A back-surface-electrode type semiconductor laser of GaN-based compound has low electric resistance and high light emitting efficiency, and includes negative electrodes made of Al having a contact surface that contacts with the n-type GaN substrate. The back-surface-electrode type semiconductor laser has GaN-based compound layers laminated on an n-type GaN substrate... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20070114516 - Dielectric media including surface-treated metal oxide particles: Briefly, the present invention provides an electronic device, typically a transistor or a capacitor, comprising at least one electrically conductive electrode and, adjacent to the electrode, a dielectric layer; wherein the dielectric layer comprises a polymeric matrix and, dispersed in the polymeric matrix, metal oxide particles; wherein the metal oxide... Agent: 3m Innovative Properties Company

20070114525 - Display device and manufacturing method: Embodiments of a display device comprises an insulating substrate; a source electrode and a drain electrode on the insulating substrate and separated from one another to define a channel region; a wall having one or more openings to expose the channel region, at least a portion of the source electrode,... Agent: Macpherson Kwok Chen & Heid LLP

20070114524 - Display device and manufacturing method thereof: According to an embodiment of the present invention, a manufacturing method of a display device includes forming a plurality of gate wires comprising a gate electrode on an insulating substrate, forming an electrode layer comprising a source electrode and a drain electrode spaced apart from each other to define a... Agent: Macpherson Kwok Chen & Heid LLP

20070114522 - Double sided emission organic light emitting diode display: An organic light-emitting diode display which can display independent images on both sides is described. This display can be driven with passive matrix or active matrix schemes. The invention combines a unique stacked organic diode structure and special driving schemes involving time-sequential reversed fields.... Agent: Cooper & Dunham, LLP

20070114523 - Electroluminescence element and display device using the same: In an EL element including a light emitting layer sandwiched between upper and lower electrodes, of light emitted therefrom, light totally reflected at a light emitting layer interface is not taken out, so there is a problem in that light emission efficiency reduces. Therefore, a light scattering layer in which... Agent: Bruce L. Adams, Esq.

20070114518 - Gan heterojunction bipolar transistor with a p-type strained ingan base layer and fabricating method thereof: A gallium nitride heterojunction bipolar transistor with a p-type strained InGaN base layer is provided. The gallium nitride heterojunction bipolar transistor includes a substrate, a highly doped collector contact layer located over the substrate, a low doped collector layer located over the collector contact layer, a p-type base layer located... Agent: Jianq Chyun Intellectual Property Office

20070114519 - Light-emitting device and electronic apparatus: A light-emitting device includes: a substrate; a plurality of light-emitting elements which is formed on the substrate and each of which has an anode partitioned by an insulating pixel partition wall, a cathode, and an organic light-emitting layer interposed therebetween and emits light by an electric field generated by the... Agent: Oliff & Berridge, PLC

20070114521 - Light-emitting device and electronic apparatus: A light-emitting device includes: a plurality of light-emitting elements each of which has an anode, a thin organic light-emitting layer, and a cathode sequentially stacked on a substrate and emits light by excitation due to an electric field, the anode being separated from another anode by an insulating pixel partition... Agent: Oliff & Berridge, PLC

20070114526 - Light-emitting device, method of manufacturing the same, and display unit: Light-emitting devices capable of preventing separation or alteration of a first electrode to obtain high performance, methods of manufacturing the light-emitting device, and display units are provided. A first electrode as an anode, an insulating film, an organic layer including a light-emitting layer, and a second electrode as a cathode... Agent: Bell, Boyd & Lloyd, LLP

20070114517 - Programmable power management using a nanotube structure: Programmable power management using a nanotube structure is disclosed. In one embodiment, a method includes coupling a nanotube structure of an integrated circuit to a conductive surface when a command is processed, and enabling a group of transistors of the integrated circuit based on the coupling the nanotube structure to... Agent: Lsi Logic Corporation Ms: D-106 Legal

20070114520 - Radiation emitting device and method of manufacturing the same: A radiation emitting electronic device (1) comprising a substrate (5), a radiation emitting functional area (10A, 10B, 15) on the substrate (5) and a radiation out-coupling material (20) comprising polysilsesquioxane (20D) and inorganic nanoparticles (20C) arranged in the optical path (100) of the radiation emitting functional area (10A, 10B, 15).... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20070114527 - Light-emitting element: In the present invention, a light-emitting element operating at low driving voltage, consuming low power, emitting light with good color purity and manufactured in high yields can be obtained. A light-emitting element is disclosed with a configuration composed of a fist layer containing a light-emitting material, a second layer, a... Agent: Eric Robinson

20070114528 - Rectifying contact to an n-type oxide material or a substantially insulating oxide material: A rectifying contact to an n-type oxide material and/or a substantially insulating oxide material includes a p-type oxide material. The p-type oxide material includes a copper species and a metal species, each of which are present in an amount ranging from about 10 atomic % to about 90 atomic %... Agent: Hewlett Packard Company

20070114529 - Scan testing system, method and apparatus: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to... Agent: Texas Instruments Incorporated

20070114530 - Display device: In view of the problem that a reduced thickness of an EL film causes a short circuit between an anode and a cathode and malfunction of a transistor, the invention provides a display device that has a light emitting element including an electrode and an electroluminescent layer, a wire electrically... Agent: Eric Robinson

20070114532 - Semiconductor display device: To provide a semiconductor display device capable of displaying an image having clarity and a desired color, even when the speed of deterioration of an EL layer is influenced by its environment. Display pixels and sensor pixels of an EL display each have an EL element, and the sensor pixels... Agent: Fish & Richardson P.C.

20070114531 - Wires for liquid crystal display and liquid crystal display having the same: A wire for a liquid crystal display has a dual-layered structure comprising a first layer made of molybdenum or molybdenum alloy, and a second layer made of molybdenum nitride or molybdenum alloy nitride. To manufacture the wire, a layer made of either a molybdenum or a molybdenum alloy, and another... Agent: Macpherson Kwok Chen & Heid LLP

20070114533 - Thin film transistor including a lightly doped amorphous silicon channel layer: A thin film transistor (TFT) is provided. The thin film transistor (TFT) comprises a substrate, a gate, an inter-gate dielectric layer, a channel layer and source/drain regions. A gate is formed over the substrate. An inter-gate dielectric layer is formed over the substrate covering the gate. A doped amorphous silicon... Agent: Jianq Chyun Intellectual Property Office

20070114534 - Polycrystalline silicon thin film, fabrication method thereof, and thin film transistor without directional dependency on active channels fabricated using the same: A polycrystalline silicon thin film to be used in display devices, the thin film having adjacent primary grain boundaries that are not parallel to each other, wherein an area surrounded by the primary grain boundaries is larger than 1 μm2, a fabrication method of the polycrystalline silicon thin film, and... Agent: Stein, Mcewen & Bui, LLP

20070114537 - Electro-optical device and manufacturing method thereof: A semiconductor device that uses a high reliability TFT structure is provided. The gate electrode of an n-channel type TFT is formed by a first gate electrode and a second gate electrode that covers the first gate electrode. LDD regions have portions that overlap the second gate electrode through a... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070114536 - Front substrate of plasma display panel and fabrication method thereof: A front substrate for a plasma display panel (PDP) and an associated fabrication method are provided. An upper dielectric layer of the front substrate includes a colorant, which causes the dielectric layer to also act as a color filter. The resulting front substrate enhances at least one of color temperature,... Agent: Ked & Associates, LLP

20070114535 - Thin film transistor, thin film transistor substrate, and methods for manufacturing the same: A thin film transistor includes a channel layer of a specific shape, a thermal gradient inducer body, a gate insulating film, a gate electrode and an interlayer insulating film, a source electrode and a drain electrode. The channel layer is formed on a substrate. The channel layer has a nucleation... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070114538 - Light-emitting semiconductor devices having variable emission wavelengths: An inventive semiconductor device for emitting light when applying a voltage comprises: a first semiconductor region (3) whose conductivity is based on charge carriers of a first type of conductivity, e.g. electrons; a second semiconductor region (5) whose conductivity is based on charge carriers of a second type of conductivity,... Agent: Rothwell, Figg, Ernst & Manbeck, P.C.

20070114542 - Light emitting device: A light emitting device having a plastic substrate is capable of preventing the substrate from deterioration with the transmission of oxygen or moisture content can be obtained. The light emitting device has light emitting elements formed between a lamination layer and an inorganic compound layer that transmits visual light, where... Agent: Nixon Peabody, LLP

20070114541 - Light emitting diode wth degenerate coupling structure: An electronic device includes a conductive n-type substrate, a Group III nitride active region, an n-type Group III-nitride layer in vertical relationship to the substrate and the active layer, at least one p-type layer, and means for providing a non-rectifying conductive path between the p-type layer and the n-type layer... Agent: Summa, Allan & Additon, P.A.

20070114540 - Nitride semiconductor light emitting device: Disclosed herein is a nitride semiconductor light emitting device, which comprises plural active layers emitting light of different wavelengths. The device comprises p-type and n-type nitride layers, and a plurality of active layers sequentially stacked between the p-type and n-type nitride layers to emit light having different wavelengths. The active... Agent: Mcdermott Will & Emery LLP

20070114539 - Semiconductor light-emitting device and producing method for the same: A semiconductor light-emitting device includes: a first semiconductor layer; a light-emitting layer being disposed on the first semiconductor layer; a second semiconductor layer being disposed on the light-emitting layer, and metal electrodes connected to the first semiconductor layer and the second semiconductor layer. The light-emitting layer is lower in refractive... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070114543 - Electronic systems using optical waveguide interconnects formed through a semiconductor wafer: An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070114544 - Light emitting device: An object of the present invention is to provide a light emitting element or a light emitting device that can be formed without any regard for a work function of an electrode. Another object of the invention is to provide a light emitting element or a light emitting device in... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070114545 - Vertical gallium-nitride based light emitting diode: A vertical GaN-based LED includes: an n-type bonding pad; an n-electrode formed under the n-type bonding pad; an n-type transparent electrode formed under the n-electrode; an n-type GaN layer formed under the n-type transparent electrode; an active layer formed under the n-type GaN layer; a p-type GaN layer formed under... Agent: Mcdermott Will & Emery LLP

20070114546 - Light emitting devices: Light-emitting devices, and related components, systems and methods are disclosed.... Agent: Wolf Greenfield & Sacks, PC

20070114548 - Charge compensated nitride phosphors for use in lighting applications: Disclosed are phosphor compositions having the formulas Ca1−a−bCeaEubAl1+aSi1−aN3, where 0<a≦0.2, 0≦b≦0.2; Ca1−c−dCecEudAl1−c(Mg,Zn)cSiN3, where 0c≦0.2, 0≦d≦0.2; Ca1−2e−fCee(Li,Na)eEufAlSiN3, where 0≦e≦0.2, 0≦f≦0.2, g+h>0; and Ca1−g−h−iCeg(Li,Na)hEuiAl1+g−hSi1−g+hN3 where 0≦g≦0.2, 0<h≦0.4, 0≦i≦0.2,g+i>0. When combined with radiation from a blue or UV light source, these phosphors can provide light sources with good color quality having high CRI... Agent: Scott A. Mccollister, Esq. Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070114549 - Light-emitting diode: A light-emitting diode (20) includes a base (22), an LED chip (24) and a single-piece enclosure (26). The LED chip is electrically mounted on the base configured for emitting light beams. The single-piece enclosure attaches to the base and encloses the LED chip therein. The enclosure includes a central convergent... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070114547 - Optical element sealing structure, optical coupler, and optical element sealing method: A sealing structure includes a lead frame having a light transmitting section, an optical element having an optical surface which is directed to the light transmitting section and is mounted on the lead frame in such a state that the optical element blocks the light transmitting section at its one... Agent: Edwards & Angell, LLP

20070114553 - Optical module and method of manufacturing the same: An optical module including: a housing formed of ceramics and having a base portion and a frame portion provided on the base portion; an optical element provided inside the frame portion; a cover member for the housing, the cover member being formed of a transparent substrate; and a connector with... Agent: Oliff & Berridge, PLC

20070114550 - Semiconductor light emitting device: A semiconductor light emitting device has a transparent layer having a first main surface and a second main surface at a side opposite to the first main surface, a plurality of light emitting sections arranged in at least one line on the first main surface of the transparent layer, each... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070114552 - Vertical gallium-nitride based light emitting diode: A vertical GaN-based LED includes: an n-electrode; a light-emitting structure in which an n-type GaN layer, an active layer, and a p-type GaN layer are sequentially formed under the n-electrode; a p-electrode formed under the light-emitting structure; a passivation layer formed to cover the side and bottom surfaces of the... Agent: Mcdermott Will & Emery LLP

20070114551 - White led illumination device: A white LED illumination device can include a white LED that has unevenness in tone and is used as a light source. The white LED illumination device can emit white light with high color rendering properties without unevenness in tone and can include the above noted white LED located adjacent... Agent: Cermak & Kenealy, LLP

20070114557 - Flip-chip light emitting diode device without sub-mount: A light emitting diode (10) has a backside and a front-side with at least one n-type electrode (14) and at least one p-type electrode (12) disposed thereon defining a minimum electrodes separation (delectrodes). A bonding pad layer (50) includes at least one n-type bonding pad (64) and at least one... Agent: Fay Sharpe LLP

20070114555 - Light emitting element, production method thereof, backlight unit having the light emitting element, and production method thereof: A light emitting element includes: A light emitting element, includes: at least one LED chip provided on an installation surface of a substrate; a metallic reflecting plate, provided upright in a light projecting direction of the LED chip on the installation surface so as to surround an entire periphery of... Agent: Morrison & Foerster LLP

20070114554 - Power line control circuit of semiconductor device: A power line control circuit of a semiconductor device in which a width of a power line can be selectively controlled. The power line control circuit of the semiconductor device according to the present invention can selectively control the width of the power line employing the dummy power line. It... Agent: Mayer, Brown, Rowe & Maw LLP

20070114556 - Semiconductor apparatus with thin semiconductor film: A semiconductor apparatus includes a substrate having at least one terminal, a thin semiconductor film including at least one semiconductor device, the thin semiconductor film being disposed and bonded on the substrate; and an individual interconnecting line formed as a thin conductive film extending from the semiconductor device in the... Agent: Rabin & Berdo, PC

20070114558 - Led module: An LED module to realize light source performance as desire is comprised of multiple LEDs, a light-emitting chip of each LED being disposed in a carrier on a substrate; conduction circuits with different polarities being provided perimeter to the carrier on the substrate; golden plate wire connecting the chip and... Agent: Troxell Law Office PLLC Suite 1404

20070114559 - Light emitting diode device having a shield and/or filter: A light emitting diode device capable of shielding or filtering the light in a manner to provide high-gradient edges or regions within the beam pattern. The LED device is also capable of providing selective coloring, thereby cost effectively improving the adaptability and number of applications which can utilize the LED... Agent: Visteon

20070114560 - Semiconductor and method of semiconductor fabrication: The present invention discloses a semiconductor, includes one or more luminescent layers; and one or more electron gas layers with two-dimensional electron gases that are distributed parallel to the luminescent layers.... Agent: Yokoi & Co., U.s.a.,inc

20070114561 - High efficiency phosphor for use in leds: Phosphor compositions having the formula (Sr,Ca,Ba)1−xEuxAl2−yMzO4−3/2yFz, where M is Mg and/or Zn; 0.001<x<0.15, 0≦y≦0.3, and 0<z≦0.2; and light emitting devices including a light source and the above phosphor. Also disclosed are blends of (Sr,Ca,Ba)1−xEuxAl2−yMzO4−3/2yFz and one or more additional phosphors and light emitting devices incorporating the same.... Agent: Scott A. Mccollister, Esq. Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070114562 - Red and yellow phosphor-converted leds for signal applications: There is provided yellow and red illumination systems, including a semiconductor light emitter, and a luminescent material. The systems have an emission falling within the respective ITE red and yellow color bins having specified color coordinates on the CIE chromaticity diagram. The luminescent material may include one or more phosphors.... Agent: Scott A. Mccollister, Esq. Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070114563 - Semiconductor device and method of fabricating the same: Provided are semiconductor devices having improved surface morphology characteristics, and a method of fabricating the same. The semiconductor device includes: an r-plane sapphire substrate; an AlxGa(1-x)N(0≦×<1) buffer layer epitaxially grown on the r-plane sapphire substrate to a thickness in the range of 100-20000 Å in a gas atmosphere containing nitrogen... Agent: Buchanan, Ingersoll & Rooney PC

20070114564 - Vertical gallium nitride based light emitting diode: A vertical GaN-based LED includes an n-type bonding pad; an n-electrode formed under the n-type bonding pad; a light-emitting structure formed by sequentially laminating an n-type GaN layer, an active layer, and a p-type GaN layer under the n-electrode; a p-electrode formed under the light-emitting structure; and a support layer... Agent: Mcdermott Will & Emery LLP

20070114565 - Integrated field-effect transistor-thyristor device: An integrated FET-thyristor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type formed in the substrate proximate an upper surface of the substrate, and a second semiconductor region of the second conductivity type formed in the substrate proximate a bottom... Agent: Ryan, Mason & Lewis, LLP

20070114566 - Method for making free-standing algan wafer, wafer produced thereby, and associated methods and devices using the wafer: A method for making a free-standing, single crystal, aluminum gallium nitride (AlGaN) wafer includes forming a single crystal AlGaN layer directly on a single crystal LiAlO2 substrate using an aluminum halide reactant gas, a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal AlGaN... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070114568 - Semiconductor device and circuit having multiple voltage controlled capacitors: An improved solution for performing switching, routing, power limiting, and/or the like in a circuit, such as a radio frequency (RF) circuit, is provided. A semiconductor device that includes at least two electrodes, each of which forms a capacitor, such as a voltage-controlled variable capacitor, with a semiconductor channel of... Agent: Hoffman Warnick & D'alessandro, LLC

20070114567 - Vertical heterostructure field effect transistor and associated method: A vertical heterostructure field effect transistor including a first layer having a first material, and the first material having a hexagonal crystal lattice structure defining a first bandgap and one or more non-polar planes is provided. The transistor further includes a second layer that is adjacent to the first layer... Agent: General Electric Company Global Research

20070114569 - Robust transistors with fluorine treatment: A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing... Agent: Koppel, Patrick & Heybl

20070114570 - Power semiconductor device: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070114572 - Gate structure including multi-tunneling layer and method of fabricating the same, non-volatile memory device and method of fabricating the same: Provided is a gate structure including a multi-tunneling layer and method of fabricating the same. Also provided is a nanodot semiconductor memory device including such gate structure and method of fabricating the same. The gate structure may include a first insulation layer, a second insulation layer, a charge storage layer... Agent: Harness, Dickey & Pierce, P.L.C

20070114571 - Semiconductor chip and semiconductor device: A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according... Agent: Sughrue Mion, PLLC

20070114573 - Sensor device with heated nanostructure: A nanostructure sensing device includes a substrate, a nanotube disposed over the substrate, and at least two conductive elements electrically connected to the nanotube. A electric current on the order of about 10 μA, or greater, is passed through the conductive elements and the nanotube. As a result, the nanotube... Agent: O'melveny & Myers LLP

20070114574 - Semiconductor device: An object of the present invention is to achieve both the high withstand voltage and the low on-resistance in a polycrystalline Si embedded gate SiC junction FET. n+ —SiC is formed as a drain layer; and n− —SiC which contacts an n+ drain layer is formed as a drift layer.... Agent: Miles & Stockbridge PC

20070114575 - Oil immersed transistor: The invention is directed to develop for the higher performance of the transistor as well as the semi-conductor by means of immersing into the high voltage of oil solution to be circulated in and out of the housing to cool down the heat of the conductor and to lower the... Agent: Yoshioki Tomoyasu

20070114576 - Surround gate access transistors with grown ultra-thin bodies: A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short... Agent: Knobbe Martens Olson & Bear LLP

20070114577 - Semiconductor device: One of the aspects of the present invention is to provide a semiconductor device, which includes a semiconductor substrate, a surface electrode on the semiconductor substrate, and a gate wiring on the semiconductor substrate, the gate wiring being spaced from the surface electrode. It also includes a metal layer on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070114578 - Layout structure of ball grid array: A layout structure of ball grid array is provided. The layout structure includes: a substrate having a margin area; a plurality of solder ball pads laid on the substrate; a plurality of interconnection vias each electrically coupled to a corresponding one of the plurality of solder ball pads; and at... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070114579 - Method for integrally forming a damascene gate structure and a resistive device: A method for integrally forming a damascene gate structure and a resistive device on a semiconductor substrate is disclosed. A first dielectric layer having a first opening and a second opening is formed on the semiconductor substrate. One or more sidewall spacers are formed on inner sides of the first... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070114580 - Nonvolatile semicondutor storage device and manufacturing method thereof: A nonvolatile semiconductor storage device includes a plurality of memory cells, each including a drain formed above a substrate, a source formed at a bottom of a groove in the substrate, a floating gate formed above the substrate between the drain and a side surface of the groove, and a... Agent: Mcginn Intellectual Property Law Group, PLLC

20070114581 - Transistor of semiconductor device and method for manufacturing the same: A transistor of a semiconductor device capable of improving the device reliability, and a method for manufacturing the same are provided. The transistor includes an active portion having a first height from a semiconductor substrate surface and having a line-shaped cross-section; a device isolation layer in which a round portion... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070114584 - Active photosensitive structure with buried depletion layer: An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a resistance characteristic that changes depending on the level of accumulated charge in the accumulation region. During an integration period, incident light causes electrons to be accumulated... Agent: Dickstein Shapiro LLP

20070114585 - Active photosensitive structure with buried depletion layer: An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a resistance characteristic that changes depending on the level of accumulated charge in the accumulation region. During an integration period, incident light causes electrons to be accumulated... Agent: Dickstein Shapiro LLP

20070114583 - Complementary metal-oxide-silicon (cmos) image sensor and method of forming the same: A complementary metal-oxide silicon (CMOS) image sensor includes a semiconductor layer of a first conductivity type, a plurality of pixels located in the semiconductor layer, a photoelectric converter located in each of the plurality of pixels in the semiconductor layer and includes a region doped with impurities of a second... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070114582 - Polydiode structure for photo diode: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer,... Agent: Berkeley Law & Technology Group, LLP

20070114586 - Electrical contact for high dielectric constant capacitors and method for fabricating the same: An electrical contact includes a non-conductive spacer surrounding conductive plug material along the full height of the contact. The spacer inhibits oxide and other diffusion through the contact. In the illustrated embodiment, the contact includes metals or metal oxides which are resistant to oxidation, and additional conductive barrier layers. The... Agent: Knobbe Martens Olson & Bear LLP

20070114587 - Nonvolatile memory device comprising one switching device and one resistant material and method of manufacturing the same: A nonvolatile memory device including one transistor and one resistant material and a method of manufacturing the nonvolatile memory device are provided. The nonvolatile memory device includes a substrate, a transistor formed on the substrate, and a data storage unit connected to a drain of the transistor. The data storage... Agent: Buchanan, Ingersoll & Rooney PC

20070114588 - Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same: A DRAM is provided that can reduce the parasitic capacitance between trench-type stacked cell capacitors in a memory cell region and suppress malfunction caused by noise. The trench-type stacked cell includes a number of capacitors having the same shape. The capacitors are formed in such a manner that storage nodes,... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070114590 - Semiconductor device and method of manufacturing the same: There are contained first and second conductive plugs formed in first insulating layer, an island-like oxygen-barrier metal layer for covering the first conductive plug, an oxidation-preventing insulating layer formed on the first insulating layer to cover side surfaces of the oxygen-barrier metal layer, a capacitor having a lower electrode formed... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070114589 - Semiconductor integrated circuit device and method for fabricating the same: A semiconductor integrated circuit device includes: a semiconductor layer having a principal surface on which a source electrode, a drain electrode and a gate electrode are formed and having a first through hole; an insulating film formed in contact with the semiconductor layer and having a second through hole; a... Agent: Mcdermott Will & Emery LLP

20070114591 - Integrated circuit devices having a resistor pattern and plug pattern that are made from a same material: An integrated circuit device is formed by forming a resistor pattern on a substrate. An interlayer dielectric layer is formed on the resistor pattern. The interlayer dielectric layer is patterned to form at least one opening that exposes the resistor pattern. A plug pattern is formed that fills the at... Agent: D. Scott Moore Myers Bigel Sibley & Sajovec, P.A.

20070114592 - Method of forming non-volatile memory cell using spacers and non-volatile memory cell formed according to the method: A method of forming a microelectronic non-volatile memory cell, a non-volatile memory cell made according to the method, and a system comprising the non-volatile memory cell. The method comprises: providing a substrate; providing a pair of spaced apart isolation regions in the substrate, providing the pair comprising providing a buffer... Agent: Intel Corporation C/o Intellevate, LLC

20070114594 - Non-volatile semiconductor memory element and method of manufacturing the same, and semiconductor integrated circuit device including the non-volatile semiconductor memory element: A non-volatile semiconductor memory element includes: a semiconductor region of a first conductivity type formed in a plate-like form on a semiconductor substrate; a first insulating film formed on a first side face of the semiconductor region; a first charge accumulating layer formed on a face of the first insulating... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070114593 - Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric: A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube... Agent: Blakely Sokoloff Taylor & Zafman

20070114595 - Transistor of a semiconductor device: Disclosed are a semiconductor device and a method of manufacturing the same. According to the present invention, the transistor of the semiconductor device comprises a stack type gate in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are sequentially stacked on a semiconductor... Agent: Marshall, Gerstein & Borun LLP

20070114596 - Integrated electronic circuit incorporating a capacitor: A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer (13) of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element... Agent: Jenkens & Gilchrist, PC

20070114597 - Twin insulator charge storage device operation and its fabrication method: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be... Agent: Saile Ackerman LLC

20070114601 - Gate contact structure for a power device: A gate contact structure for a power device comprises a substrate having a trench, a gate conductor in the trench and striding over a side of the trench, a first insulator between the gate conductor and the trench, a second insulator covering the gate conductor, a contact window in the... Agent: Rosenberg, Klein & Lee

20070114599 - High density trench mosfet with reduced on-resistance: A method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) cell includes the steps of opening a gate trench in a semiconductor substrate and implanting ions of a first conductivity type same as a conductivity type of a source region with at least two levels of implanting... Agent: Bo-in Lin

20070114602 - Semiconductor device: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a first semiconductor region of the first conductivity type and a second semiconductor region of a second conductivity type alternately arranged in a lateral direction on the first semiconductor layer of the first conductivity type; a third... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070114598 - Trench gate field effect devices: The present invention relates to a technique for reducing the on-voltage of the semiconductor device by increasing the concentration of minority carriers in the deep region (26) and the intermediate region (28). A semiconductor device according to the invention comprises an electrode, a top region (36) of a second conductivity... Agent: Kenyon & Kenyon LLP

20070114600 - Trench transistor and method for fabricating a trench transistor: A trench transistor having a semiconductor body, in which a trench structure and an electrode structure embedded in the trench structure is disclosed. The electrode structure is electrically insulated from the semiconductor body by an insulation structure. The electrode structure has a gate electrode structure and a field electrode structure... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070114603 - Semiconductor device and manufacturing method of the same: When an STI element isolation structure is formed, it is formed in such a manner that its upper portion protrudes further than the surface of a substrate than by a normal STI method, and a dummy electrode pattern is formed in a gate electrode forming portion. After a source/drain is... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070114604 - Double-extension formation using offset spacer: A MOS transistor structure is disclosed. A gate electrode is disposed on a semiconductor substrate. A first extension of a predetermined impurity type is substantially aligned with the gate electrode in the substrate. A second extension of the predetermined impurity type overlaps with the first extension in the substrate. The... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070114605 - Ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation: A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the substrate aside from the stack at a maximum energy less... Agent: International Business Machines Corporation Dept. 18g

20070114606 - Semiconductor device and a method of manufacturing the same: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070114607 - Drain-extended mos transistors with diode clamp and methods for making the same: High side extended-drain MOS driver transistors (T2) are presented in which an extended drain (108, 156) is separated from a first buried layer (120) by a second buried layer (130), wherein an internal or external diode (148) is coupled between the first buried layer (120) and the extended drain (108,... Agent: Texas Instruments Incorporated

20070114608 - Lateral thin-film soi device having a field plate with isolated metallic regions: In a lateral thin-film Silicon-On-Insulator (SOI) device, a field plate is provided to extend substantially over a lateral drift region to protect the device from package and surface charge effects. In particular, the field plate comprises a layer of plural metallic regions which are isolated laterally from one another by... Agent: Philips Intellectual Property & Standards

20070114609 - Semiconductor substrate and method of manufacturing the same: A method of manufacturing a semiconductor substrate can effectively prevent a chipping phenomenon and the production of debris from occurring in part of the insulation layer and the semiconductor by removing a outer peripheral portion of the semiconductor substrate so as to make the outer peripheral extremity of the insulation... Agent: Fitzpatrick Cella Harper & Scinto

20070114610 - Semiconductor device and method of fabricating the same: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an isolation layer on a semiconductor substrate, and an active area which protrudes from the isolation layer (and the substrate) and which has rounded edge portions; a gate insulating layer and a gate electrode... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070114611 - Structure and method for mosfet with reduced extension resistance: The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of... Agent: Scully Scott Murphy & Presser, PC

20070114612 - Method of fabricating semiconductor devices having mcfet/finfet and related device: In a method of fabricating a semiconductor device having both a MCFET and a finFET on a common substrate, a first hard mask pattern and a second hard mask pattern are formed on a substrate, the second hard mask pattern having a width in a horizontal direction that is less... Agent: Mills & Onello LLP

20070114613 - Programmable nanotube interconnect: Programmable nanotube interconnect is disclosed. In one embodiment, a method includes forming a interconnect layer using a plurality of nanotube structures, and automatically altering a route of an integrated circuit based on an electrical current applied to at least one of the plurality of nanotube structures in the interconnect layer.... Agent: Lsi Logic Corporation

20070114614 - Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070114615 - Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device: A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered doped conductor creates a high dopant concentration in the active area close to the channel region. The rich dopant layer created by... Agent: Dinsmore & Shohl LLP

20070114616 - Field effect transistor and method of manufacturing the same: A field effect transistor, which is arranged in a semiconductor device, comprises a first and a second doped source/drain region, both regions being arranged within a semiconductor substrate on either side of a gate electrode, and a channel region formed within the substrate between both doped source/drain regions beneath said... Agent: Slater & Matsil LLP

20070114617 - Semiconductor memory device: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070114618 - Semiconductor device and method of manufacturing the same: It is made possible to provide a highly-reliable, high-performance semiconductor device that reduces the intensity of the electric field in the gate insulating film, has a higher current driving force, and can operate at a high speed. A semiconductor device includes: a semiconductor region provided on a substrate; source and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070114619 - Sidewall mosfets with embedded strained source/drain: Structures and methods for forming the same. The semiconductor structure includes (a) a substrate having a top substrate surface; (b) a channel region on the top substrate surface; (c) a gate dielectric region on the top substrate surface; and (d) a gate electrode region on the top substrate surface. The... Agent: Schmeiser, Olsen & Watts

20070114622 - Damascene copper wiring optical image sensor: A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a inner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a... Agent: Scully, Scott, Murphy & Presser, P.C.

20070114620 - Package and electronic apparatus using the same: An upper sealing ring and a lower sealing ring are adhered by sealing solder. The width of tip end of sealing projection is narrower than the width of the lower sealing ring. Therefore, the sealing solder is placed on lower sealing ring and on the side surface of upper sealing... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070114621 - Wirelessly powered flexible tag: A wirelessly powered flexible tag configured to be in contact with a substrate is provided. The tag includes a coupling layer configured to couple the tag to the substrate. An electrical circuit disposed on the coupling layer and configured to interact wirelessly with an external stimulus. The tag further includes... Agent: General Electric Company Global Research

20070114623 - Method for manufacturing a microelectromechanical component, and a microelectromechanical component: The invention relates to microelectromechanical components, like microelectromechanical gauges used in measuring e.g. acceleration, angular acceleration, angular velocity, or other physical quantities. The microelectromechanical component, according to the invention, comprises a microelectromechanical chip part, sealed by means of a cover part, and an electronic circuit part, suitably bonded to each... Agent: Squire, Sanders & Dempsey L.L.P.

20070114624 - Moisture resistant differential pressure sensors: A differential pressure sensor has a semiconductor wafer having a top and bottom surface. The top surface of the wafer has a central active area containing piezoresistive elements. These elements are passivated and covered with a layer of silicon dioxide. Each element has a contact terminal associated therewith. The semiconductor... Agent: Plevy & Howard & Darcy P.C.

20070114625 - Image tft array of a direct x-ray image sensor and method of fabricating the same: A method of fabricating an image TFT array of a direct X-ray image sensor includes forming a first transparent conductive layer on a substrate; forming a gate line including a gate electrode, a common line, and a common electrode jutting out from the common line; forming an insulation layer; forming... Agent: North America Intellectual Property Corporation

20070114627 - Photodetector with an improved resolution: A photodetector made in monolithic form in a lightly-doped substrate of a first conductivity type. This photodetector comprises at least two photodiodes and comprises a first region of the first conductivity type more heavily doped than the substrate extending at least between the two photodiodes; and a second region of... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070114626 - Photodiode device and photodiode array for optical sensor using the same: The invention relates a photodiode device and a photodiode array using the same capable of detecting short and long wavelengths of visible light at a high efficiency. The photodiode device includes: a first conductivity type semiconductor substrate; a second conductivity type buried layer, an intrinsic semiconductor layer and a first... Agent: Lowe Hauptman Berner, LLP

20070114628 - Light emitting slot-waveguide device: An electroluminescent material slot waveguide generates light in response to current injection. In one embodiment, the waveguide is formed as part of an optical resonator, such as ring resonator waveguide or distributed Bragg reflector with an anode and cathode for electrical stimulation. A compact, electrically-driven resonant cavity light emitting devices... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070114629 - Pinned photodiode (ppd) pixel with high shutter rejection ratio for snapshot operating cmos sensor: A pixel image sensor has a high shutter rejection ratio that prevents substrate charge leakage to a floating diffusion storage node of the pixel image sensor and prevents generation of photoelectrons within the floating diffusion storage node and storage node control transistor switches of the pixel image sensor. The pixel... Agent: George O. Saile

20070114630 - Semiconductor device: A semiconductor device having a substrate that contains an insulating layer and a semiconductor layer provided on the insulating layer. The semiconductor also has an optical waveguide that is formed along a predetermined path. This optical waveguide is formed by making the semiconductor layer non-uniformed in thickness thereof. The semiconductor... Agent: David R. Metzger Sonnenschein Nath & Rosenthal LLP

20070114631 - Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070114632 - Transistor having dielectric stressor elements at different depths from a semiconductor surface for applying shear stress: A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region,... Agent: International Business Machines Corporation Dept. 18g

20070114633 - Integrated circuit device with a circuit element formed on an active region having rounded corners: An integrated circuit device has a substrate with first and second portions. One or more first active regions are formed in the first portion of the substrate. Each of the one or more first active regions has rounded corners. One or more first circuit elements are formed on the one... Agent: Leffert Jay & Polglaze, P.A.

20070114634 - Integrated passive device system: An integrated passive device system is disclosed including forming a first dielectric layer over a semiconductor substrate, depositing a metal capacitor layer and a silicide layer on the first dielectric layer, forming a second dielectric layer over the metal capacitor layer and the silicide layer, and depositing a metal layer... Agent: Ishimaru & Zahrt LLP

20070114635 - Integrated circuit devices having corrosion resistant fuse regions and methods of fabricating the same: Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth spaced apart lower interconnects are parallel to the first and second lower interconnects. A first fuse is provided on the first and second... Agent: Myers Bigel Sibley & Sajovec

20070114636 - Electronic device contact structures: Electronic devices involving contact structures, and related components, systems and methods associated therewith are described. Contact structures (also referred to as electrical contact structures or electrodes) are features on a device that are electrically connected to a power source. The power source can provide current to the device via the... Agent: Wolf Greenfield & Sacks, PC

20070114637 - Article with protective film: An article includes a substrate, a transition layer, and a diamond like carbon film. The transition layer is directly formed on a surface of the substrate. The diamond like carbon film is deposited on the transition layer, in contact therewith. The diamond like carbon film includes a nitrogen-doped diamond like... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070114639 - Integrated circuit package system with bump pad: An integrated circuit package system includes an integrated circuit, and forming a patterned redistribution pad over the integrated circuit.... Agent: Ishimaru & Zahrt LLP

20070114638 - Printed circuit board with quartz crystal oscillator: A printed circuit board with a quartz crystal oscillator includes a mounting area for receiving the quartz crystal oscillator, two first vias, and two second vias. A copper foil is arranged on the mounting area. Pins of the quartz crystal oscillator are inserted into the first vias. The second vias... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070114640 - Semiconductor devices including voltage switchable materials for over-voltage protection: Semiconductor devices are provided that employ voltage switchable materials for over-voltage protection. In various implementations, the voltage switchable materials are substituted for conventional die attach adhesives, underfill layers, and encapsulants. While the voltage switchable material normally functions as a dielectric cmaterial, during an over-voltage event the voltage switchable material becomes... Agent: Carr & Ferrell LLP

20070114642 - Semiconductor device having a heat spreader exposed from a seal resin: A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070114641 - Ultra-thin quad flat no-lead (qfn) package: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and... Agent: Stmicroelectronics, Inc.

20070114646 - Die package having an adhesive flow restriction area: A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element. A second embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches that extend from one... Agent: Dickstein Shapiro LLP

20070114645 - Integrated circuit package system configured for singulation: An integrated circuit package system includes forming lead structures including a dummy tie bar having an intersection with an outer edge of the integrated circuit package system, and connecting an integrated circuit die to the lead structures.... Agent: Ishimaru & Zahrt LLP

20070114643 - Mems flip-chip packaging: Packaging of MEMS and other devices, and in some cases, devices that have vertically extending structures. Robust packaging solutions for such devices are provided, which may result in superior vacuum performance and/or increased protection in some environments such as high-G environments, while also providing high volume throughput and low cost... Agent: Honeywell International Inc.

20070114644 - Scaling of functional assignments in packages: A family of package substrates adapted to receive a family of integrated circuits having different sizes and provide electrical connections between the integrated circuits and a circuit board. Each package substrate in the family includes a package substrate having a die side and a circuit board side. The package substrate... Agent: Lsi Logic Corporation

20070114647 - Carrier board structure with semiconductor chip embedded therein: A carrier board structure with a semiconductor chip embedded therein is provided, which includes a carrier board having a first surface with at least one opening and a second surface. Allowing a semiconductor chip to be embedded in the opening in a manner that the active surface of the semiconductor... Agent: Mr. Joseph A. Sawyer, Jr. Sawyer Law Group LLP

20070114649 - Low profile stacking system and method: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method is stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder past that includes higher temperature solder paste alloy is... Agent: Fish & Richardson P.C.

20070114648 - Semiconductor stacked multi-package module having inverted second package: A semiconductor multi-package module has stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding, and in which the upper package is inverted. Also, a method for making a semiconductor multi-package module, by providing... Agent: Haynes Beffel & Wolfeld LLP

20070114651 - Integrated circuit stacking system with integrated passive components: An integrated circuit stacking system is provided including fabricating an integrated passive device including: providing a semiconductor substrate, forming an integrated inductor, a resistor block, or an integrated capacitor integrated on the semiconductor substrate, and forming contact pads, on the semiconductor substrate, coupled to the integrated inductor, the resistor block,... Agent: Ishimaru & Zahrt LLP

20070114650 - Non-leaded integrated circuit package system: A non-leaded integrated circuit package system is provided providing a die paddle of a lead frame, forming a dual row of terminals including outer terminal pads and inner terminal pads, and selectively fusing an extension between the die paddle and instances of the inner terminal pads.... Agent: Ishimaru & Zahrt LLP

20070114652 - Surface-mount packaging for chip: A chip includes a plurality of pins; and a plurality of symbols defined on a surface of the chip, wherein the symbols are arranged as a graduated scale corresponding with the pins. It becomes very easy to find a initial pin from among the plurality of pins of the chip.... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070114653 - Wiring glass substrate for connecting a semiconductor chip to a printed wiring substrate and a semiconductor module having the wiring glass substrate: A wiring glass substrate includes a glass substrate formed of glass and having a plurality of holes formed at predetermined positions, bumps so formed as to be connected to a conductive material filling the holes and wirings formed on a surface opposite to a surface having the bumps formed thereon... Agent: Dickstein Shapiro LLP

20070114654 - Stackable semiconductor package and method for its fabrication: A stackable semiconductor package includes a board having first electrical connections, an integrated circuit chip fixed on a front face of the board, second electrical connections which connect the chip to the first electrical connections of the board and front electrical contact terminals arranged beyond at least one edge of... Agent: Jenkens & Gilchrist, PC

20070114655 - Apparatus for cooling: A cooling apparatus is disclosed that has a first cooling structure, in thermal contact with a heat source having a temperature greater than a cool structure, comprising a channel through which a cooling fluid is passed, an isolator between the heat source and the cool structure, the isolator in thermal... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070114656 - Fluid cooled encapsulated microelectronic package: An encapsulated microelectronic package includes a fluid conducting cooling tube directly coupled to one or more semiconductor chips, with the encapsulant being molded over the semiconductor chips and portions of the cooling tube in proximity to the semiconductor chips. The encapsulant immobilizes the cooling tube with respect to the semiconductor... Agent: Delphi Technologies, Inc.

20070114657 - Integrated circuit micro-cooler having multi-layers of tubes of a cnt array: Heat sink structures employing mutli-layers of carbon nanotube or nanowire arrays to reduce the thermal interface resistance between an integrated circuit chip and the heat sink are disclosed. In one embodiment, the nanotubes are cut to essentially the same length over the surface of the structure. Carbon nanotube arrays are... Agent: Glenn Patent Group

20070114658 - Integrated circuit micro-cooler with double-sided tubes of a cnt array: Heat sink structures employing carbon nanotube or nanowire arrays exposed from both opposite surfaces of the structure to reduce the thermal interface resistance between an integrated circuit chip and the heat sink are disclosed. In one embodiment, the nanotubes are cut to essentially the same length over the surface of... Agent: Glenn Patent Group

20070114659 - Rotary chip attach: A rotary chip attach process and manufacturing approach takes chips (e.g., integrated circuits (ICs)) from a wafer in a rotary process. A chip wafer with a positioning unit is placed over the top of a sprocketed wheel that picks the ICs directly from the wafer and moves them in a... Agent: Caesar, Rivise, Bernstein, Cohen & Pokotilow, Ltd.

20070114660 - Memory module: A memory module comprises a base plate and one or more IC embedding seats formed thereon to provide IC memory chip being installed in detachable manner taking the advantage of easy installation, convenient maintenance or replacement of IC memory chip, particularly no longer using SMT, soldering paste, or flux for... Agent: Bacon & Thomas, PLLC

20070114663 - Alloys for flip chip interconnects and bumps: The present invention provides alloys for forming sputtered under bump metallization seed layers and electroplated or otherwise deposited bump metallurgy. The alloys of the present invention are comprised of silver with gold or palladium, copper with gold, or gold with nickel or palladium which provide suitable sputtering and electrical characteristics... Agent: Phillips Lytle LLP Intellectual Property Group

20070114662 - Interconnecting element between semiconductor chip and circuit support and method: One aspect of the invention relates to an interconnecting element between a semiconductor chip of a semiconductor wafer and a circuit support and to a method for producing and using the interconnecting element. Such interconnecting elements are arranged between contact areas of a semiconductor chip of a semiconductor wafer and... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070114661 - Semiconductor package and method of fabricating the same: Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a... Agent: Hiscock & Barclay, LLP

20070114664 - Packaged device and method of forming same: A method of packaging an integrated circuit die (12) includes the steps of loading an array of soft conductive balls into recesses formed in a platen and locating the platen in a first part of a mold cavity. A second part of the mold is pressed against the balls to... Agent: Freescale Semiconductor, Inc. Law Department

20070114665 - Power semiconductor circuit: A power semiconductor circuit has a power semiconductor module (2) embodied as a flat assembly. A particularly compact and space-saving production of a power semiconductor circuit may be achieved with the possibilities provided by an embodiment of the power semiconductor module, whereby the power semiconductor module (2) is arranged directly... Agent: Baker Botts, L.L.P.

20070114666 - Capture of residual refractory metal within semiconductor device: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and... Agent: Buchanan, Ingersoll & Rooney PC

20070114667 - Alternate pad structures/passivation inegration schemes to reduce or eliminate imc cracking in post wire bonded dies during cu/low-k beol processing: Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide... Agent: Lsi Logic Corporation

20070114669 - Plasma display panel: The plasma display panel includes a first substrate and a second substrate that are disposed substantially in parallel with each other with a predetermined distance therebetween; a plurality of address electrodes disposed on the first substrate; a first dielectric layer disposed covering the address electrodes; a plurality of barrier ribs... Agent: Knobbe Martens Olson & Bear LLP

20070114668 - Semiconductor device: A semiconductor device is equipped with a semiconductor chip which has at least one layer of first insulating film formed on a substrate, and a plurality of pads arranged on a layer higher than the first insulating film. The plurality of pads on the semiconductor chip are arranged parallel to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070114670 - Corrosion-resistant aluminum conductive material and process for producing the same: This invention relates to a corrosion-resistant aluminum conductive material comprising an aluminum material consisting of aluminum or an aluminum alloy and a conductive film formed on the surface of said aluminum material wherein defects in the conductive film are substantially sealed off by a hot water treatment or a steam... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070114671 - Interconnect structure and fabricating method thereof: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is disposed on the substrate covering the conductive part. The composite plug is disposed in the dielectric layer electrically connecting with... Agent: Jianq Chyun Intellectual Property Office

20070114672 - Semiconductor device and method of manufacturing the same: The miniaturization of the system in package which laminates a plurality of semiconductor chips on a wiring substrate via a die attach film is promoted. In the system in package (SiP) which laminates memory chips and microcomputer chip via die attach film on wiring substrate, by forming metal plate in... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070114673 - Wiring substrate and electronic parts packaging structure: In a wiring substrate of the present invention in which a bump of an electronic parts is bonded to a connection pad of a wiring pattern provided on an insulating film by an ultrasonic flip-chip packaging, a via hole into which a via post acting as a strut to support... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070114674 - Hybrid solder pad: The solder pad interface includes a soldermask defined (SMD) interface between a solder pad (202) and the substrate, and a non-soldermask defined (NSMD) interface between the solder pad and the solder joint. The SMD interface can include a layer of insulating material (208) configured as an overlaid stencil with apertures... Agent: Motorola Inc

20070114675 - Integrated circuit package with improved power signal connection: An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further... Agent: Buckley, Maschoff & Talwalkar LLC

20070114676 - Semiconductor package structure and method of manufacture: In one embodiment, a semiconductor package is formed by adding a layer of particles to desired portions of a packing substrate. The layer of particles forms a matrix of crevices that provides a micro-lock feature for mechanically locking or engaging encapsulating materials.... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070114677 - Semiconductor package with heat sink, stack package using the same and manufacturing method thereof: A semiconductor package may include a heat sink. The heat sink may be disposed above and spaced apart from a substrate, which may support a semiconductor chip. The heat sink may have a hole. A liquid molding compound may be provided through the hole of the heat sink to form... Agent: Harness, Dickey & Pierce, P.L.C

20070114678 - Binary sinusoidal sub-wavelength gratings as alignment marks: The present invention relates to alignment marks for use on substrates, the alignment marks consisting of periodic 2-dimensional arrays of structures, the spacing of the structures being smaller than an alignment beam but larger than an exposure beam and the width of the structures varying sinusoidally from one end of... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070114679 - Multi-terminal hybrid switching device: A multi-terminal electromechanical nanoscopic switching device which may be used as a memory device, a pass gate, a transmission gate, or a multiplexer, among other things.... Agent: Stephen L. King

20070108429 - Pipe shaped phase change memory: A memory cell device includes a bottom electrode, pipe shaped member comprising phase change material and a top electrode in contact with the pipe-shaped member. An electrically and thermally insulating material is inside the pipe-shaped member. An integrated circuit including an array of pipe-shaped phase change memory cells is described.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070108432 - Damascene phase change memory: A phase change material may include a pore formed of a relatively smaller phase change material and a relatively larger resistance heater. As a result, the relatively smaller portion of phase change material may have improved properties.... Agent: Trop Pruner & Hu, PC

20070108431 - I-shaped phase change memory cell: A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the first electrode; a lower phase change member, having a contact... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070108433 - Semiconductor memory device and method of fabricating the same: In a semiconductor memory device and a method of fabricating the same, a semiconductor memory device having a transistor and a data storing portion includes a heating portion interposed between the transistor and the data storing portion and a metal interconnection layer connected to the data storing portion, wherein the... Agent: Lee & Morse, P.C.

20070108430 - Thermally contained/insulated phase change memory device and method (combined): A memory device with improved heat transfer characteristics. The device first includes a dielectric material layer; first and second electrodes, vertically separated and having mutually opposed contact surfaces. A phase change memory element is encased within the dielectric material layer, including a phase-change layer positioned between and in electrical contact... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070108435 - Method of making nanowires: A novel technique for manufacturing nanostructures and nanostructure is disclosed. The invention exploits techniques to deposit a second semiconductor material on a first semiconductor material with incomplete coverage of the second layer, and forming the nanostructures by filling the holes in the second semiconductor layer with a third semiconductor material.... Agent: Dave Garrod, Ph.d., Esq. Goodwin-procter

20070108434 - Quantum dot based pressure switch: A semiconductor heterostructure based pressure switch comprising: first and second small bandgap material regions separated by a larger bandgap material region; a third small bandgap material region within the region of larger bandgap material, the third material region and larger bandgap material region defining at least one quantum dot; and,... Agent: Plevy & Howard & Darcy P.C.

20070108436 - Semiconductor light-emitting device and surface light source using the same: A semiconductor light-emitting device can include high heat dissipation properties and a high degree of mounting flexibility. Also a surface light source can be configured to use the above-noted semiconductor light-emitting device. The semiconductor light-emitting element can be mounted on a package obtained by insert-molding lead frames with a resin.... Agent: Cermak & Kenealy, LLP

20070108437 - Method of fabrication of high temperature superconductors based on new mechanism of electron-electron interaction: The present invention is a superconducting tunnel junction comprising two thin films characterized in that the thin films have an indented surface facing each other and are separated by an insulator layer. Typically, the depth of the indents is in the range of 5 to 10 nm, the width of... Agent: Borealis Technical Limited

20070108442 - Display device and method for manufacturing the same: A display device includes an insulating substrate; a plurality of gate wires formed on the insulating substrate, the plurality of gate wires including a gate electrode; a gate insulating layer covering the plurality of gate wires; a transparent electrode layer formed on the gate insulating layer, the transparent electrode layer... Agent: Macpherson Kwok Chen & Heid LLP

20070108440 - Emissive device and electronic apparatus: An emissive device includes a substrate; a switching element disposed on a surface of the substrate; an insulating layer covering the switching element; a contact hole disposed in the insulating layer; a first electrode disposed on a surface of the insulating layer and electrically connected to the switching element via... Agent: Oliff & Berridge, PLC

20070108438 - Multypodal tethers for high-density attachment of redox-active moieties to substrates: This invention provides redox-active molecules attached to polypodal (e.g., bipodal, tripodal, quadrapodal, pentapodal, etc.) tethers that can be used for attachment of the redox-active molecules to a substrate (e.g., an electrode). The tethered redox-active molecules are useful for the fabrication of memory devices.... Agent: Quine Intellectual Property Law Group, P.C.

20070108439 - Nanotube based multi-level memory structure: A network of electronic devices is provided. The network comprises an organized matrix of armchair nanotubes and zigzag nanotubes.... Agent: Silverbrook Research Pty Ltd

20070108443 - Organic light emitting display device: An organic light emitting display device, which may maximize aperture ratio of a pixel while also reducing the perception of a dark spot when a sub-pixel is partially short-circuited. The organic light emitting display device includes a plurality of pixels having sub-pixels. Some of the sub-pixels may have a thin... Agent: Christie, Parker & Hale, LLP

20070108441 - Switching device: A switching device is discloses that exhibits two stable resistance values to a voltage applied between electrodes. The switching device comprises thin films of a first electrode layer, an organic bistable material layer and a second electrode layer sequentially formed on a substrate, and the organic bistable material is a... Agent: Rossi, Kimms & Mcdowell LLP.

20070108444 - Semiconductor substrate and manufacturing method thereof: In order to suppress deterioration in charge balance and maintain excellent withstand voltage characteristics after forming a super junction structure on a semiconductor substrate, a plurality of columnar first epitaxial layers are respectively formed on a surface of a substrate main body at predetermined intervals, and a plurality of second... Agent: Reed Smith, LLP Attn: Patent Records Department

20070108445 - Electronic ink display device: An electronic ink display device with a frontplane laminate and a TFT array substrate is provided. In the TFT array substrate, a first metal layer and a dielectric layer are disposed on a first substrate. The dielectric layer covers the first metal layer. A second metal layer is disposed on... Agent: Daniel R. Mcclure Thomas, Kayden, Horstemeyer & Risley, L.L.P.

20070108446 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode.... Agent: Nixon Peabody, LLP

20070108447 - Thin film transistor and liquid crystal display: The present invention relates to a thin film transistor and a liquid crystal display. A gate electrode is formed to include at least one portion extending in a direction perpendicular to a gain growing direction in order to make electrical charge mobility of TFTs uniform without increasing the size of... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070108448 - Display device and fabrication method thereof: The present invention provides a display device which forms thin film transistor circuits differing in characteristics from each other on a substrate in mixture and a fabrication method of the display device. On a glass substrate having a background layer which is formed by stacking an SiN film and an... Agent: Stanley P. Fisher Reed Smith LLP

20070108449 - Display device and fabrication method thereof: The present invention provides a fabrication method of a display device which aims at the reduction of fabricating man-hours. In a fabrication method of a display device having a thin film transistor in which a gate electrode includes a first gate electrode and a second gate electrode which is overlapped... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070108450 - Reduction of carrot defects in silicon carbide epitaxy: Single crystal silicon carbide epitaxial layer on an off-axis substrate are manufactured by placing the substrate in an epitaxial growth reactor, growing a first layer of epitaxial silicon carbide on the substrate, interrupting the growth of the first layer of epitaxial silicon carbide, etching the first layer of epitaxial silicon... Agent: Myers Bigel Sibley & Sajovec

20070108451 - Image forming apparatus: On the peripheral edge of a front side substrate of an FED, a rectangular frame shaped sealing surface is formed for sealing a sidewall. On the sealing surface, an indium layer is formed through a base layer. At the four corners of the indium layer, an electrode for applying an... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070108452 - Growth of a semiconductor layer structure: A method of growing a semiconductor layer structure comprises growing a first semiconductor layer and incorporating hydrogen into the first semiconductor layer. One or more further semiconductor layers are then grown over the first semiconductor layer to form a semiconductor layer structure. A selected portion of the first semiconductor layer... Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP

20070108453 - N-type ohmic electrode for n-type group iii nitride semiconductor, semiconductor light-emitting device with the electrode, and method for forming n-type ohmic electrode: The present invention provides a constitution of n-type ohmic electrode suitable for n-type group III nitride semiconductor, and a forming method thereof for providing low contact resistivity. The n-type ohmic electrode is provided to comprise an alloy of aluminum and lanthanum or comprises lanthanum at the junction interface with the... Agent: Sughrue Mion, PLLC

20070108454 - Display device and electronic device: A display device and an electronic device in which more sophistication and a high added value are realized by obtaining a read function by incorporating an imaging device, and by using a panel with small volume can be provided. A display device and an electronic device according to the invention... Agent: Fish & Richardson P.C.

20070108455 - Three wavelength led structure: A three wavelength light emitting diode (LED) structure utilizes a blue light LED chip and a green light LED chip as light sources, and a red fluorescent layer is used as a light transition layer. By adjusting the number of the blue light LED chip and the green light LED... Agent: Charles E. Baxley, Esq.

20070108457 - Gan-series light emitting diode with high light efficiency and the manufacturing method: A GaN-series light emitting diode with high light efficiency utilizes a p-type semiconductor layer having a textured surface structure. The optical waveguide effect can be interrupted and formation of hexagonal shaped pits defect can be reduced due to the textured structure. The p-type semiconductor layer is formed on a light... Agent: Rosenberg, Klein & Lee

20070108456 - Superlattice strain relief layer for semiconductor devices: A GaN/AlN superlattice is formed over a GaN/sapphire template structure, serving in part as a strain relief layer for growth of subsequent layers (e.g., deep UV light emitting diodes). The GaN/AlN superlattice mitigates the strain between a GaN/sapphire template and a multiple quantum well heterostructure active region, allowing the use... Agent: Jonathan A. Small JasIPConsulting

20070108458 - Gallium nitride-based compound semiconductor light-emitting device and negative electrode thereof: An object of the present invention is to provide a negative electrode which attains excellent Ohmic contact with an n-type gallium nitride-based compound semiconductor layer and which resists deterioration in characteristics which would be caused by heating. Another object of the invention is to provide a gallium nitride-based compound semiconductor... Agent: Sughrue Mion, PLLC

20070108462 - Fabrication method of light emitting diode incorporating substrate surface treatment by laser and light emitting diode fabricated thereby: The present invention relates to a fabrication method of LEDs incorporating a step of surface-treating a substrate by a laser and an LED fabricated by such a fabrication method. The present invention can use a laser in order to implement finer surface treatment to an LED substrate over the prior... Agent: Lowe Hauptman Berner, LLP

20070108460 - Led package: An LED package is provided. A light emitting chip generates light when current is applied. A frame is electrically connected to the light emitting chip via a wire, and has the light emitting chip mounted thereon. A molding fixes the frame thereto, and has a cavity surrounding the light emitting... Agent: Mcdermott Will & Emery LLP

20070108459 - Methods of manufacturing light emitting devices: Light emitting devices (LED) and methods of fabricating such, comprising a substrate, a light extraction structure, and an emitting layer sandwiched between a plurality of semiconductor layers of the first and the second type. The said extraction structure is processed into preferred geometric shapes using preferred methods.... Agent: Zhenghao Jason Lu

20070108461 - Semiconductor device and manufacturing method of semiconductor device: A semiconductor device made by mounting alight emitting element in a substrate, characterized in that an optically-transparent cover with a flat plate shape is installed on the light emitting element and a fluorescent substance film is formed on the cover.... Agent: Drinker Biddle & Reath (dc)

20070108464 - Led package with improved heat dissipation and led assembly incorporating the same: An LED package with improved heat dissipation and an LED assembly incorporating the same. The LED package includes a base made of a thermally conductive polymer; a pair of terminals formed on an upper side of the base; a LED chip electrically connected to the terminals; and a transparent encapsulant... Agent: Sughrue Mion, PLLC

20070108463 - Light-emitting diode with uv-blocking nano-particles: A light-emitting device has an encapsulated light-emitter. Nano-particles substantially transparent to visible light block UV light.... Agent: Agilent Technologies Inc.

20070108466 - Group iii-nitrides on si substrates using a nanostructured interlayer: A layered group III-nitride article includes a single crystal silicon substrate, and a highly textured group III-nitride layer, such as GaN, disposed on the silicon substrate. The highly textured group III-nitride layer is crack free and has a thickness of at least 10 μm. A method for forming highly textured... Agent: Akerman Senterfitt

20070108465 - Porous microstructure multi layer spectroscopy and biosensing: A preferred embodiment biosensor is a multi-layer micro-porous thin film structure. Pores in a top layer of the micro-porous thin film structure are sized to accept a first molecule of interest. Pores in a second layer of the micro-porous thin film structure are smaller than the pores in the top... Agent: Greer, Burns & Crain

20070108467 - Vertical gan-based light emitting diode: A vertical GaN-based LED is provided. The vertical GaN-based LED includes an n-type bonding pad, an n-type reflective electrode formed under the n-type bonding pad, an n-type transparent electrode formed under the n-type reflective electrode, an n-type GaN layer formed under the n-type transparent electrode, an active layer formed under... Agent: Mcdermott Will & Emery LLP

20070108468 - Semiconductor device and method of manufacturing the same: A semiconductor device, including: a semiconductor substrate of a first conductivity type having a first and second major surfaces; a first conductivity type semiconductor layer formed on the first major surface of the semiconductor substrate; a base layer of a second conductivity type formed on the first major surface of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070108469 - Semiconductor device having separation region: A semiconductor device includes: a semiconductor substrate; a separation region in the substrate; an embedded layer; a channel forming region; a source region; a drain region; a first electrode for the source region; a second electrode for the channel forming region; a third electrode for the drain region; a trench... Agent: Posz Law Group, PLC

20070108470 - Semiconductor device and manufacturing method thereof: A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second... Agent: Jianq Chyun Intellectual Property Office

20070108471 - Semiconductor device: A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor region, the MIS transistors including a plurality of gate electrodes which extend in a first direction and are provided on the semiconductor... Agent: Foley And Lardner LLP Suite 500

20070108472 - Thin film transistor and method of manufacturing the same: A thin film transistor (TFT) and a method of manufacturing the same, and more particularly, a TFT for reducing leakage current and a method of manufacturing the same are provided. The TFT includes a flexible substrate, a diffusion preventing layer formed on the flexible substrate, a buffer layer formed of... Agent: Knobbe Martens Olson & Bear LLP

20070108474 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate formed with a plurality of trenches, a plurality of trench capacitor type DRAM unit cells including capacitors formed in the trenches and cell transistors formed to be adjacent to the trenches respectively, a plurality of impurity doped regions including boundaries connecting the trenches... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070108473 - Semiconductor optical sensors: An optical sensor and method for forming the same. The optical sensor structure includes (a) a semiconductor substrate, (b) first, second, third, fourth, fifth, and sixth electrodes and (c) first, second, and third semiconducting regions. The first and fourth electrodes are at a first depth. The second and fifth electrodes... Agent: Schmeiser, Olsen & Watts

20070108476 - Imager with reflector mirrors: Embodiments of the invention provide an imager pixel comprising a reflective layer formed over a substrate. There is a semiconductor layer over the reflective layer. A photo-conversion device is formed at a surface of the semiconductor layer. The reflective layer serves to reflect incident light not initially absorbed into the... Agent: Dickstein Shapiro LLP

20070108475 - Photon amplification for image sensors: A pixel cell having a substrate, photo-conversion device, and at least one dielectric layer over the photo-conversion device. The at least one dielectric layer includes one or more rare earth elements for amplifying the number of photons capable of being converted to charge by the photo-conversion device.... Agent: Dickstein Shapiro LLP

20070108477 - Semiconductor structure: A semiconductor structure comprising a first conductive type substrate, a first conductive type well, an integrated circuit region, an isolation structure and a second conductive type doped region is described. The first conductive type well is disposed in the first conductive type substrate. The integrated circuit region is disposed in... Agent: Jianq Chyun Intellectual Property Office

20070108478 - Cell electro-physiological sensor and method of manufacturing the same: A cell electro-physiological sensor includes a sensor chip including a partition board having a first surface and a second surface opposite to the first surface, a member for forming a first region provided on the first surface of the partition board, and a member for forming a second region provided... Agent: Ratnerprestia

20070108479 - Resistance element having reduced area: A semiconductor device having reduced area occupied by the semiconductor elements that constitute the semiconductor device, and its manufacturing method. Insulating film 12 is formed on substrate 10. First resistance element 18b is formed on insulating film 12. Second resistance element 21b is laminated on first resistance element i8b. In... Agent: Texas Instruments Incorporated

20070108481 - Electronic devices including a semiconductor layer and a process for forming the same: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the... Agent: Larson Newman Abel Polansky & White, LLP

20070108480 - Field effect transistor and method of fabricating the same: A field effect transistor according to the present invention has a semiconductor layer through which carriers injected from a source region travel toward a drain region, the semiconductor layer being formed from a composite material including an organic semiconductor material and nanotubes. The nanotubes may be nanotubes including plural ones... Agent: Mcdermott Will & Emery LLP

20070108482 - Non-volatile electromechanical field effect devices and circuits using same and methods of forming same: Under one aspect, a field effect device includes a gate, a source, and a drain, with a conductive channel between the source and the drain; and a nanotube switch having a corresponding control terminal, said nanotube switch being positioned to control electrical conduction through said conductive channel. Under another aspect,... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070108483 - Thin film transistor and method of fabricating the same: A thin film transistor having an offset or a lightly doped drain (LDD) structure by self alignment and a method of fabricating the same comprises a substrate, a silicon layer disposed on the substrate and including a channel region, a source region and a drain region at both sides of... Agent: Cantor Colburn, LLP

20070108484 - Optical sensor: An optical sensor is characterized by comprising a photoconductive material (1) which generates a carrier (4) inside when irradiated with a light or an electromagnetic wave (3), and carbon nanotube (2), and by sensing the carrier (4), which is generated within the photoconductive material (1) by irradiation of the light... Agent: Crowell & Moring LLP Intellectual Property Group

20070108486 - Image pickup element performing image detection of high resolution and high image quality and image pickup apparatus including the same: In a pixel part, in a first active region, a photodiode and a transferring transistor are formed. In a second active region, a resetting transistor is formed. In a pixel part, in a first active region, a photodiode and a transferring transistor are formed. In a second active region, an... Agent: Buchanan, Ingersoll & Rooney PC

20070108485 - Image sensor cells: A structure (and method for forming the same) for an image sensor cell. The method includes providing a semiconductor substrate. Then, a charge collection well is formed in the semiconductor substrate, the charge collection well comprising dopants of a first doping polarity. Next, a surface pinning layer is formed in... Agent: Schmeiser, Olsen & Watts

20070108487 - Cmos (complementary metal oxide semiconductor) type solid-state image pickup device using n/p+ substrate in which n-type semiconductor layer is laminated on p+ type substrate main body: A solid-state image pickup device includes a semiconductor substrate including a substrate main body having P-type impurities and a first N-type semiconductor layer provided on the substrate main body, an image pickup area including a plurality of photoelectric converters in which the plurality of photoelectric converters include second N-type semiconductor... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070108489 - Semiconductor device and method for fabricating the same: The semiconductor device according to the present invention comprises: a ferroelectric capacitor 42 formed above a semiconductor substrate 10 and including a lower electrode 36, a ferroelectric film 38 formed on the lower electrode 36 and an upper electrode 40 formed on the ferroelectric film 38; a silicon oxide film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070108488 - Storage node, phase change memory device and methods of operating and fabricating the same: A storage node, a phase change memory device, and methods of operating and fabricating the same are provided. The storage node may include a lower electrode, a phase change layer on the lower electrode and an upper electrode on the phase change layer, and the lower electrode and the upper... Agent: Harness, Dickey & Pierce, P.L.C

20070108490 - Film capacitors with improved dielectric properties: A film capacitor including a first electrode is provided. The film capacitor also includes a first dielectric layer having a first dielectric constant disposed upon a first electrode and a second dielectric layer having a second dielectric constant disposed upon the first dielectric layer, wherein the second dielectric constant is... Agent: General Electric Company Global Research

20070108491 - Semiconductor memory device having high electrical performance and mask and photolithography friendliness: A semiconductor memory device includes a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a... Agent: F. Chau & Associates, LLC

20070108492 - Semiconductor device and method for producing the same: A semiconductor device including a lower electrode formed in a groove portion, a capacitor insulating film provided so as to cover the lower electrode, and an upper electrode provided so as to cover a plurality of lower electrodes with the capacitor insulating film, wherein a stress buffering portion, being an... Agent: Mcdermott Will & Emery LLP

20070108493 - Capacitor and process for manufacturing the same: The present invention aims at solving the problem caused when forming a crown-structure capacitor in a trench which is formed in an insulating film, in particular, the problem of having difficulty in electrical connecting a first upper electrode formed on the inside wall of the trench and a second upper... Agent: Young & Thompson

20070108494 - Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070108495 - Mnos memory devices and methods for operating an mnos memory devices: A split-gate MNOS memory device comprises a thin dielectric layer between the memory gate and the silicon nitride trapping layer. The thin dielectric layer can block charge loss at low electric field and can allow hole injection at high electric fields. P-type polysilicon gates can be used to increase hole... Agent: Baker & Mckenzie LLP Patent Department

20070108496 - Nonvolatile semiconductor storage device and method of manufacture thereof: In a nonvolatile semiconductor storage device, memory cell units of two-transistor structure are arranged in rows and columns and adjacent rows of memory cell units are isolated by a trench-type device isolation region. The spacing between the control gate electrode of a cell transistor and the gate electrode of a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070108497 - Low hydrogen concentration charge-trapping layer structures for non-volatile memory and methods of forming the same: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070108498 - Non-volatile memory devices having floating gates and related methods of forming the same: A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell... Agent: Myers Bigel Sibley & Sajovec

20070108500 - Nrom storage devices based on resonant tunneling: The present invention discloses a resonant tunneling device. Further, the present invention discloses a memory storage device utilizing a resonant tunneling barrier. Moreover, the present invention teaches an SRAM circuit utilizing a resonant tunneling device. Additionally, the present invention teaches an NROM and NAND device utilizing a resonant tunneling barrier.... Agent: Perkins Coie LLP

20070108499 - Sonos-based nand devices based on resonant tunneling: The present invention discloses a resonant tunneling device. Further, the present invention discloses a memory storage device utilizing a resonant tunneling barrier. Moreover, the present invention teaches an SRAM circuit utilizing a resonant tunneling device. Additionally, the present invention teaches an NROM and NAND device utilizing a resonant tunneling barrier.... Agent: Perkins Coie LLP

20070108501 - Sram circuit having a sonos-based nand device: The present invention discloses a resonant tunneling device. Further, the present invention discloses a memory storage device utilizing a resonant tunneling barrier. Moreover, the present invention teaches an SRAM circuit utilizing a resonant tunneling device. Additionally, the present invention teaches an NROM and NAND device utilizing a resonant tunneling barrier.... Agent: Perkins Coie LLP

20070108505 - Gate structure, semiconductor memory device having the gate structure and methods of fabricating the same: A gate structure using nanodots as a trap site, a semiconductor device having the gate structure and methods of fabricating the same are provided. The gate structure may include a tunneling layer, a plurality of nanodots on the tunneling layer, and a control insulating layer including a high-k dielectric layer... Agent: Harness, Dickey & Pierce, P.L.C

20070108502 - Nanocrystal silicon quantum dot memory device: A nanocrystal silicon (Si) quantum dot memory device and associated fabrication method have been provided. The method comprises: forming a gate (tunnel) oxide layer overlying a Si substrate active layer; forming a nanocrystal Si memory film overlying the gate oxide layer, including a polycrystalline Si (poly-Si)/Si dioxide stack; forming a... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070108503 - Non-volatile memory and manufacturing method and operating method thereof: A non-volatile memory is provided. At least two bit lines are disposed in a substrate. The two bit lines are arranged in parallel and extend in a first direction. A plurality of select gate structures is disposed on the substrate between the two bit lines respectively. The select gate structures... Agent: Jianq Chyun Intellectual Property Office

20070108504 - Non-volatile memory and manufacturing method and operating method thereof: A non-volatile memory having a plurality of gate structures, a plurality of charge storage layers and two doped regions is provided. The gate structures are disposed on the substrate and connected in series. The charge storage layers are disposed between every two neighboring gate structures respectively. The gate structures and... Agent: Jianq Chyun Intellectual Property Office

20070108506 - Storage devices based on resonant tunneling: The present invention discloses a resonant tunneling device. Further, the present invention discloses a memory storage device utilizing a resonant tunneling barrier. Moreover, the present invention teaches an SRAM circuit utilizing a resonant tunneling device. Additionally, the present invention teaches an NROM and NAND device utilizing a resonant tunneling barrier.... Agent: Perkins Coie LLP

20070108507 - Non-volatile memory: A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive... Agent: Jianq Chyun Intellectual Property Office

20070108509 - Semiconductor memory and method for manufacturing the same: A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and... Agent: Mcdermott Will & Emery LLP

20070108508 - Single-poly non-volatile memory device: A single-poly, P-channel non-volatile memory (NVM) cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layers on... Agent: North America Intellectual Property Corporation

20070108510 - Process for production of soi substrate and process for production of semiconductor device: A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor... Agent: Nixon Peabody, LLP

20070108512 - Power semiconductor component with charge compensation structure and method for the fabrication thereof: The invention relates to a power semiconductor component (1) with charge compensation structure (3) and a method for the fabrication thereof. For this purpose, the power semiconductor component (1) has a semiconductor body (4) having a drift path (5) between two electrodes (6, 7). The drift path (5) has drift... Agent: Baker Botts, L.L.P.

20070108511 - Semiconductor structure, method for operating a semiconductor structure and method for producing a semiconductor structure: A semiconductor structure has a substrate with a first main surface and a second main surface, the substrate comprising a gate electrode region, a channel region, wherein a conductive channel can be generated, and a gate electrode insulation between the gate electrode region and the channel region. Further, a field... Agent: Maginot, Moore & Beck Chase Tower

20070108513 - Method for fabricating a semiconductor component: The fabrication of a semiconductor component having a semiconductor body in which is arranged a very thin dielectric layer having sections which run in the vertical direction and which extend very deeply into the semiconductor body is disclosed. In one method a trench is formed in a drift zone region... Agent: Maginot, Moore & Beck Chase Tower

20070108514 - Semiconductor device and method of fabricating the same: A semiconductor device according to the present invention, which comprises a MISFET, has a semiconductor layer (3) having a recessed portion (101) formed in the surface thereof, the recessed portion (101) having an opening the outer circumference of which is closed, a gate insulating film (13) formed so as to... Agent: Mcdermott Will & Emery LLP

20070108516 - Semiconductor device and method of manufacturing the same: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction.... Agent: Marger Johnson & Mccollom, P.C.

20070108515 - Trench mosfet: The invention relates to a trench MOSFET with drain (8), dπ ft region (10) body (12) and source (14). In order to improve the figure of meπt for use of the MOSFET as control and sync FETs, the trench (20) is partially filled with dielectric (24) adjacent to the drift... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070108517 - Ldmos with independently biased source: A power metal-oxide semiconductor device provides an P-type base region that includes the N+ device source and is biased differently than the P-type substrate by application of an electrical load. In one embodiment, an LDMOS device with a NPN configuration is used but the coupling of the device source to... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070108518 - Semiconductor device: A gate electrode is formed on a gate insulator above a semiconductor substrate. Diffused regions are formed in a surface of the semiconductor substrate as sandwiching the gate electrode therebetween. A high-resistance layer is formed in the surface of the semiconductor substrate as electrically connected to the diffused region. A... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070108519 - Semiconductor light emitting device and method for manufacturing the same: A semiconductor lamination portion (6) is formed by laminating at least an n-type layer (3) and a p-type layer (5) made of gallium nitride based compound semiconductor so as to form a light emitting portion, and a light transmitting conductive layer (7) is formed on a surface of the semiconductor... Agent: Rabin & Berdo, PC

20070108520 - Laterally double-diffused metal oxide semiconductor transistor and method for fabricating the same: The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant... Agent: Birch Stewart Kolasch & Birch

20070108521 - Flexible semiconductor device and identification label: Provided is a flexible device (100) having an integrated circuit (5) and an antenna (6) which is incorporated or directly coupled to the interconnect structure of the integrated circuit (5). The interconnect structure extends outside of the active area. An electrically insulating or dielectric layer (4) is present as support... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070108523 - Semiconductor device and fabrication method for the same: In a semiconductor device including a monocrystalline thin film transistor 16a that has been formed on a monocrystalline Si wafer 100 and then is transferred to a insulating substrate 2, LOCOS oxidization is performed with respect to the element-isolation region of the monocrystalline Si wafer 100 so as to create... Agent: Nixon & Vanderhye, PC

20070108522 - Soi substrate and method of manufacturing the same: The SOI substrate includes a supporting substrate, an insulating layer (first insulating layer), another insulating layer (second insulating layer), and a silicon layer (silicon active layer). On a surface of the supporting substrate, which is the surface on the side of the silicon layer, the first insulating layer is provided.... Agent: Young & Thompson

20070108524 - Low threshold voltage pmos apparatus and method of fabricating the same: A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter and an outer perimeter. The inner... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070108526 - Strained silicon cmos devices: Improved ways of controlling the boundaries between the compressive and tensile portions of a dual-stress liner in a semiconductor device are described. The boundaries may be appropriately designed to be located by a predetermined distance as measured from a PFET feature, such as the channel or the active area boundary,... Agent: Banner & Witcoff, Ltd.

20070108525 - Structure and method to increase strain enhancement with spacerless fet and dual liner process: A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be... Agent: Scully Scott Murphy & Presser, PC

20070108527 - Novel method for four direction low capacitance esd protection: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding... Agent: Thomas, Kayden, Hostemeyer & Risley LLP

20070108528 - Sram cell: Disclosed is an SRAM cell on an SOI, bulk or HOT wafer with two pass-gate n-FETs, two pull-up p-FETs and two pull-down n-FETs and the associated methods of making the SRAM cell. The pass-gate FETs and pull-down FETs are non-planar fully depleted finFETs or trigate FETs. The pull-down FETs comprise... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070108529 - Strained gate electrodes in semiconductor devices: Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an... Agent: Slater & Matsil, L.L.P.

20070108530 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a MIS transistor formed in a region of a semiconductor region. The MIS transistor includes a gate insulating film formed on the region, a gate electrode formed on the gate insulating film and fully silicided with metal, source/drain regions formed in parts of the region on... Agent: Mcdermott Will & Emery LLP

20070108531 - Rotational shear stress for charge carrier mobility modification: A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first stress is located in the isolation trench. A second isolation region having a second stress different than the first stress is... Agent: Scully Scott Murphy & Presser, PC

20070108532 - Semiconductor device: It is possible to realize the following package structure. That is, a structure for applying a stress to a channel region is provided for a semiconductor chip itself. In a package manufacturing process, a low thermal expansion coefficient film is formed on a circuit face of an Si chip. Thus,... Agent: Steptoe & Johnson LLP

20070108533 - Integrated circuit having a multipurpose resistor for suppression of a parasitic transistor or other purposes: A composite integrated circuit incorporating two LDMOSFETs of unlike designs, with the consequent creation of a parasitic transistor. A multipurpose resistor is integrally built into the composite integrated circuit in order to prevent the parasitic transistor from accidentally turning on. In an intended application of the composite integrated circuit to... Agent: Woodcock Washburn LLP

20070108534 - Schottky barrier diode and method of forming a schottky barrier diode: Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type or p-type dopant, one area is lightly-doped with... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070108535 - Semiconductor device: A semiconductor device having a field effect transistor formed on a semiconductor layer on an insulator, comprising: a drain electrode wiring formed over a drain region of the field effect transistor; a source electrode wiring formed over a source region of the field effect transistor; first contact plugs connecting the... Agent: Foley And Lardner LLP Suite 500

20070108537 - Corner dominated trigate field effect transistor: Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070108536 - Quasi self-aligned source/drain finfet process: A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins... Agent: Scully, Scott, Murphy & Presser, P.C.

20070108538 - Semiconductor device and method for manufacturing the same: A semiconductor device is provided that has MIS transistors with metal gates that can prevent an increase in the number of manufacturing steps as much as possible and also restrain difficulties in the manufacturing conditions. This semiconductor device has a substrate; and an n-channel MIS transistor including: a p-type semiconductor... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070108540 - Micro-electromechanical switch, method of manufacturing an integrated circuit including at least one such switch, and an integrated circuit: Integrated circuit obtained by a CMOS process and comprising circuit components and at least one micro-electromechanical switch comprising a layered structure, comprising an actuator electrode corresponding to a first conductive layer, at least one contact electrode corresponding to a second conductive layer, and a displaceable conductive element corresponding to a... Agent: Harness, Dickey & Pierce, P.L.C

20070108539 - Stable organic devices: Stable organic devices, as well as related components, systems, and methods, are disclosed.... Agent: Fish & Richardson PC

20070108541 - Integrated electronic microphone and a method of manufacturing: The present invention provides an integrated electronic microphone formed as part of a semiconductor device, and a manufacturing method therefor. The microphone is formed with a sensing electrode as part of a sensing membrane, and the sensing electrode is connected to the gate of a sensing transistor to provide an... Agent: Buchanan, Ingersoll & Rooney PC

20070108542 - Thermally isolated membrane structure: An MEMS device including a semiconductor substrate having an upper and lower surface, and a support structure disposed at least partially in the semiconductor substrate. The support structure includes a plurality of support members oriented to define a plurality of cells in the semiconductor substrate. A thermally isolated membrane is... Agent: Delphi Technologies, Inc.

20070108543 - Semiconductor device and method of manufacturing the same: A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070108544 - Image sensor with a compound structure: An image sensor with a compound layer includes a substrate, a chip, wires, a compound layer, and a transparent layer. The substrate has an upper surface, which is formed with a central region and first electrodes arranged at the each side of the central region, and a lower surface, which... Agent: Pro-techtor International Services

20070108545 - Infrared-blocking encapsulant with organometallic colloids: Organometallic colloid(s) is dispersed in a polymer matrix to form an infrared-blocking encapsulant.... Agent: Agilent Technologies Inc.

20070108546 - Photoelectric converter and imaging system including the same: A photoelectric converter includes a substrate, photoelectric converting elements formed in the substrate and each having a light-receiving surface, an antireflection film arranged above at least a part of the light-receiving surface of each photoelectric converting element, an element isolation region including an insulator, a plurality of transistors including read... Agent: Canon U.s.a. Inc. Intellectual Property Division

20070108547 - Second schottky contact metal layer to improve gan schottky diode performance: A Schottky contact is disposed atop a surface of a semiconductor. A first Schottky contact metal layer is disposed atop a first portion of the semiconductor surface. A second Schottky contact metal is disposed atop a second portion of the surface layer and adjoins the first Schottky contact metal layer.... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20070108548 - Optical scanner and method of fabricating the same: An optical scanner and a fabricating method thereof are provided. The optical scanner includes a base substrate, a frame, a H-shaped stage, supporters, and a stage driving structure. An interconnection layer having a predetermined pattern is formed on the base substrate. The frame has a rectangular frame shape which is... Agent: Buchanan, Ingersoll & Rooney PC

20070108550 - Semiconductor device and method of fabricating the same: The semiconductor device has a semiconductor substrate; an electric fuse provided on the semiconductor substrate, and having a first fuse link and a second fuse link connected in series; and a terminal provided between the first fuse link and the second fuse link, wherein the first fuse link and the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070108549 - Semiconductor structure: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, a bond pad, a fuse structure and a protection layer. The substrate has a pad region and a fuse region. The bond pads are disposed in the pad region of the substrate. The fuse structure is disposed in the... Agent: Jianq Chyun Intellectual Property Office

20070108551 - High performance system-on-chip inductor using post passivation process: A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.... Agent: Saile Ackerman LLC

20070108554 - De-coupling capacitors produced by utilizing dummy conductive structures integrated circuits: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a... Agent: Duane Morris, LLPIPDepartment

20070108552 - Design of low inductance embedded capacitor layer connections: The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070108553 - Thin-film device and method of manufacturing same: A thin-film device comprises a substrate and a capacitor provided on the substrate. The capacitor incorporates: a lower conductor layer; a dielectric film a portion of which is disposed on the lower conductor layer; and an upper conductor layer disposed on the dielectric film. The lower conductor layer has a... Agent: Oliff & Berridge, PLC

20070108555 - Integrated circuit comprising a gradually doped bipolar transistor and corresponding fabrication process: An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4a of the collector.... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070108556 - Columnar electric device and its manufacturing method: A sensor whose size can be decreased without marring the performance and which can be installed in a narrow place, an electric device, and a method for easily manufacturing the electric device. By vacuum deposition of semiconductor on a columnar body or by applying a melt, solution, or gel of... Agent: Young & Thompson

20070108557 - Integrated circuit system with wafer trimming: An integrated circuit system includes an integrated circuit wafer, forming a trimmed edge on the integrated circuit wafer, and applying a thinning process on the integrated circuit wafer with the trimmed edge.... Agent: Ishimaru & Zahrt LLP

20070108558 - Semiconductor device and method of manufacturing the same: A semiconductor device formed by decreasing thickness of a substrate by grinding, and performing ion implantation. In a diode in which a P anode layer and an anode electrode are formed at a side of a right face of an N− drift layer, and an N+ cathode layer and a... Agent: Rabin & Berdo, PC

20070108561 - Image sensor chip package: An image sensor chip package (200) includes a carrier (20), an image sensor chip (30), a number of wires (50) and a holder (60). The carrier includes a base (21) and a leadframe (23) embedded in the base. The base includes a board (211), a sidewall (213) and a cavity... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070108559 - Integrated circuit package system with integrated circuit support: An integrated circuit package system including an integrated circuit die, a leadframe and an integrated circuit support. The integrated circuit support between the integrated circuit die and the leadframe with the electrical interconnects connected to the leadframe.... Agent: Ishimaru & Zahrt LLP

20070108562 - Semiconductor chip having bond pads: A semiconductor package includes a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern, The pad-rearrangement pattern includes a... Agent: Marger Johnson & Mccollom, P.C.

20070108560 - Stackable power semiconductor package system: The present invention provides a stackable power semiconductor package system comprising forming a lower lead frame, having an upward bent source lead and an upward bent gate lead, mounting a power semiconductor device on the lower lead frame utilizing interconnect structures and forming an upper lead frame wherein the upper... Agent: Ishimaru & Zahrt LLP

20070108563 - Semiconductor device: A semiconductor device which permits reduction in the number of pins and in size thereof is provided. The semiconductor device comprises a sealing body formed of an insulating resin, the sealing body having an upper surface, a lower surface opposite to the upper surface, and side faces which connect the... Agent: Miles & Stockbridge PC

20070108564 - Thermally enhanced power semiconductor package system: The present invention provides a thermally enhanced power semiconductor package system comprising providing a power semiconductor die, forming an upper lead frame on the power semiconductor die and forming a lower lead frame below the power semiconductor die, wherein the upper lead frame and the lower lead frame are provided... Agent: Ishimaru & Zahrt LLP

20070108565 - Etched leadframe flipchip package system: The present invention provides an etched leadframe flipchip package system comprising forming a leadframe comprises forming contact leads and etching a plurality of multiple dotted grooves on the contact leads, and attaching a flipchip integrated circuit having solder interconnects on the contact leads between each of the plurality of the... Agent: Ishimaru & Zahrt LLP

20070108567 - Integrated circuit leadless package system: An integrated circuit leadless package system is presented comprising forming a QFN leadframe comprises providing a die pad, forming a fishtail tie-bar on the die pad, forming a row of an outer contact pad around the die pad, forming an additional outer contact pad around the fishtail tie-bar, and forming... Agent: Ishimaru & Zahrt LLP

20070108569 - Integrated circuit package system with interconnect support: An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the... Agent: Ishimaru & Zahrt LLP

20070108566 - Integrated circuit package system with multi-planar paddle: An integrated circuit package system includes a multi-planar paddle having an uplift rim and an attached integrated circuit over the uplift rim of the multi-planar paddle.... Agent: Ishimaru & Zahrt LLP

20070108568 - Integrated circuit package to package stacking system: An integrated circuit package to package stacking system is provided including providing a first integrated circuit package, having a configured leadframe, providing a second integrated circuit package, having the configured leadframe, and forming an integrated circuit package pair by electrically connecting the configured leadframe of the first integrated circuit package... Agent: Ishimaru & Zahrt LLP

20070108571 - Method for fabricating semiconductor package with stacked chips: A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the... Agent: Edwards & Angell, LLP

20070108570 - Semiconductor device and method of manufacturing the same: There is provided a semiconductor device 100 by which flexibility in interconnection design may be improved. The semiconductor device 100 includes: a lead frame 102 provided with an island 101 and a plurality of lead units 104; a first chip 109 which is mounted on the island 101 at the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070108574 - Chip stack package and manufacturing method thereof: A chip stack package may include a package substrate, a plurality of semiconductor chips mounted on the package substrate, bonding wires electrically connecting the semiconductor chips to the package substrate, and spacers interposed between the adjacent semiconductor chips. Each of the spacers may include a plurality of metal bumps. The... Agent: Harness, Dickey & Pierce, P.L.C

20070108575 - Semiconductor package that includes stacked semiconductor die: A semiconductor package that includes at least two semiconductor devices that are coupled to one another through a conductive clip.... Agent: Ostrolenk Faber Gerb & Soffen

20070108572 - Structure for reducing stress for vias and fabricating method thereof: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating... Agent: Harness, Dickey & Pierce, P.L.C

20070108573 - Wafer level package having redistribution interconnection layer and method of forming the same: A wafer level package may include a semiconductor substrate supporting an electrode pad. A first insulating layer may be provided on the semiconductor substrate. The first insulating layer may include a first opening through which the electrode pad may be exposed. A seed metal layer may be provided on an... Agent: Harness, Dickey & Pierce, P.L.C

20070108576 - Packaging structure of rsmmc memory card: The present invention provides a packaging structure of a RSMMC memory card. The packaging structure comprises a substrate having a plurality of integrated circuit (IC) devices and passive devices located therein. A frame engaging with the substrate is surrounded with the IC devices and the passive devices. A metal cover... Agent: Dykema Gossett, PLLC

20070108577 - Image sensor module with a protection layer and a method for manufacturing the same: An image sensor module with a protection layer and a method for manufacturing the same includes a substrate with an upper surface and a lower surface, a chip is mounted on the upper surface of the substrate, a plurality of wires are electrically connected the bonding pads of the chip... Agent: Pro-techtor International Services

20070108579 - Methods of fabrication of package assemblies for optically interactive electronic devices and package assemblies therefor: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer... Agent: Trask Britt, P.C./ Micron Technology

20070108578 - Semiconductor device and manufacturing method of the same: A semiconductor device includes a semiconductor element, a transparent member separated from the semiconductor element by a designated length and facing the semiconductor element, a sealing member sealing an edge surface of the transparent member and an edge part of the semiconductor element, and a shock-absorbing member provided between the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070108582 - Integrated circuit package system including shield: An integrated circuit package system, which includes providing a substrate and attaching a first device to the substrate. Attaching a shield to the substrate. Processing the shield to form apertures and configuring the shield to block electromagnetic energy.... Agent: Ishimaru & Zahrt LLP

20070108583 - Integrated circuit package-on-package stacking system: An integrated circuit package-on-package stacking system is provided including providing a first integrated circuit package, mounting a metalized interposer substrate over the first integrated circuit package and attaching a second integrated circuit package on the metalized interposer substrate.... Agent: Ishimaru & Zahrt LLP

20070108581 - Offset integrated circuit package-on-package stacking system: An offset integrated circuit package-on-package stacking system is provided including providing a base substrate, forming a contact pad on the base substrate, mounting a first integrated circuit on the base substrate, forming a base package body around the first integrated circuit, providing an offset substrate, mounting a second integrated circuit... Agent: Ishimaru & Zahrt LLP

20070108580 - Semiconductor wafer, panel and electronic component with stacked semiconductor chips, and also method for producing same: A semiconductor wafer, a panel, and an electronic component, and also methods for producing them is disclosed. In this context, the electronic component has a stack of two semiconductor chips. The top stacked semiconductor chip is thin-ground and is arranged using flip-chip technology on a central regions of the bottom... Agent: Dicke, Billig & Czaja, PLLC

20070108586 - Composite wiring board and manufacturing method thereof: A composite wiring board includes a ceramic substrate, a resin layer in contact with at least one surface of the ceramic substrate and a sintered metal conductor piercing through the resin layer. The composite wiring board is manufactured by a method including the steps of forming a through hole in... Agent: Kanesaka Berner And Partners LLP

20070108585 - Semiconductor package including a semiconductor die having redistributed pads: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.... Agent: Ostrolenk Faber Gerb & Soffen

20070108584 - Transmitter module with improved heat dissipation: A transmitter module for mobile radio applications includes a multilayer module substrate with levels of metallization and intervening dielectric stacks in which a circuit is implemented by structuring the levels of metallization. In or on the module substrate, at least one HF filter or adjustment network is implemented. On the... Agent: Fish & Richardson PC

20070108587 - Integrated circuit package system with a heat sink: An integrated circuit package system is provided forming a substrate having an integrated circuit die thereon, thermally connecting a heat slug and a resilient thermal structure to the integrated circuit die, and encapsulating the resilient thermal structure.... Agent: Ishimaru & Zahrt LLP

20070108588 - Multilayer wiring board, manufacturing method thereof, semiconductor device, and wireless electronic device: A multilayer wiring board exhibiting excellent moldability and having a capacitor where variation of capacitance is suppressed, its producing method, a semiconductor device mounting a semiconductor chip on the multilayer wiring board, and a wireless electronic device mounting the semiconductor device.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070108589 - Integrated circuit package system: An integrated circuit package system includes providing a substrate having a first plurality of conductive traces having a first width. An integrated circuit die is attached to the substrate. A mold clamp line is identified on the substrate. A critical area around the mold clamp line is determined. A plurality... Agent: Ishimaru & Zahrt LLP

20070108591 - Interposer and method for producing the same and electronic device: An interposer includes a substrate made of an inorganic material; a through wiring including conductors embedded in through holes; and an upper wiring and (or)a lower wiring. The through wiring, the upper wiring and the lower wiring are respectively formed on preliminary wiring patterns that are additionally simultaneously or sequentially... Agent: Drinker Biddle & Reath (dc)

20070108592 - Method for fabricating semiconductor package: A semiconductor package and a fabrication method thereof are proposed. A lead frame is provided between a chip and a substrate in a window ball grid array semiconductor package, wherein an active surface of the chip is electrically connected to the lead frame via bonding wires formed in an opening... Agent: Edwards & Angell, LLP

20070108590 - Semiconductor package system with thermal die bonding: A semiconductor package system includes providing a substrate having a plurality of thermal vias extending through the substrate. A solder mask is positioned over the plurality of thermal vias. A plurality of thermally conductive bumps is formed on at least some of the plurality of thermal vias using the solder... Agent: Ishimaru & Zahrt LLP

20070108593 - Zeolite sol and method for preparing the same, composition for forming porous film, porous film and method for forming the same, interlevel insulator film, and semiconductor device: The present invention provides a zeolite sol which can be formed into a porous film that can be thinned to an intended thickness by a method used in the ordinary semiconductor process, that excels in dielectric properties, adhesion, film consistency and mechanical strength, and that can be easily thinned; a... Agent: Myers Bigel Sibley & Sajovec

20070108594 - Semiconductor apparatus: A semiconductor apparatus that comprises a semiconductor chip having a first surface including an external connection terminal and a second surface opposing the first surface, a cap having a recessed part that accommodates the semiconductor chip, and a bonding member for bonding the second surface of the semiconductor chip with... Agent: Young & Thompson

20070108596 - Integrated circuit package system using heat slug: An integrated circuit package system includes providing a substrate having an integrated circuit die thereon. A support is provided on the substrate. A heat slug having a tie bar is positioned by the tie bar on the support. The substrate and the integrated circuit die are encapsulated with an encapsulant,... Agent: Ishimaru & Zahrt LLP

20070108597 - Integrated circuit package system with heat dissipation enclosure: An integrated circuit package system is provided providing an integrated circuit die, and enclosing the integrated circuit die in a heat dissipation enclosure comprises mounting the integrated circuit die on a die paddle attaching a heat block ring to the die paddle around the integrated circuit die, and attaching a... Agent: Ishimaru & Zahrt LLP

20070108595 - Semiconductor device with integrated heat spreader: A semiconductor device includes a die, a substrate, a heat spreader and a plurality of signal interconnects extending from the die. The heat spreader has a base and a plurality of fins. The heat spreader is mounted on the substrate in such a way that the base of the head... Agent: Attn: Matthew Zischka Smart & Biggar

20070108598 - Low voltage drop and high thermal performance ball grid array package: An apparatus and method for a low voltage drop and thermally enhanced integrated circuit (IC) package are described. A substantially planar substrate having a plurality of contact pads on a first surface is electrically connected through the substrate to a plurality of solder ball pads on a second surface of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070108599 - Semiconductor chip package with a metal substrate and semiconductor module having the same: A semiconductor chip package includes: a metal substrate having a core; a semiconductor chip mounted on the metal substrate; and a heat sink extending from the core.... Agent: Harness, Dickey & Pierce, P.L.C

20070108600 - Semiconductor device: A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G1, a... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070108605 - Bump chip carrier semiconductor package system: A bump chip carrier semiconductor package system is provided including providing a lead frame, forming circuit sockets in the lead frame, mounting a semiconductor die on the lead frame, wherein the semiconductor die have electrical interconnects that connects to the circuit sockets, and encapsulating a molding compound to cover the... Agent: Ishimaru & Zahrt LLP

20070108601 - Integrated circuit package system including ribbon bond interconnect: An integrated circuit package system including a ribbon bond interconnect is provided, having a semiconductor device with at least one pad thereon. An external connection is provided. A heavy ribbon is provided and bonded to the external connection and to the pad on the semiconductor device.... Agent: Ishimaru & Zahrt LLP

20070108603 - Method of putting isolated metallic interconnections onto a metallic substrate: A method and substrate are provided for supporting one or more electronic devices including a first layer having a plurality of interconnected metallic frames laid out in a predetermined pattern. Each frame includes a frame member surrounding at least a portion of each frame, one or more metal pads and... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070108602 - Mos device with a high voltage isolation structure: The present invention discloses a semiconductor structure. A buried layer of a first polarity type is constructed on a semiconductor substrate. A first epitaxial layer of a second polarity type is formed on the buried layer. A second epitaxial layer of the second polarity type is formed on the buried... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070108608 - Multi-chip package semiconductor device and method of detecting a failure thereof: A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output... Agent: Harness, Dickey & Pierce, P.L.C

20070108606 - Semiconductor device: A semiconductor device includes a semiconductor substrate, an electrode pad electrically connected to a circuit element formed on the semiconductor substrate, a connection wiring electrically connected to the electrode pad and extending on the semiconductor substrate, and a post electrode formed on the connection wiring. The semiconductor device further includes... Agent: Rabin & Berdo, PC

20070108607 - Semiconductor device: A semiconductor device including: a semiconductor chip having a rectangular surface on which a plurality of electrodes are formed; a plurality of resin protrusions formed on the surface of the semiconductor chip; and a plurality of interconnects each of which is electrically connected to one of the electrodes and includes... Agent: Harness, Dickey & Pierce, P.L.C

20070108604 - Stacked integrated circuit leadframe package system: A stacked integrated circuit leadframe package system including forming a leadframe, packaging a top integrated circuit on a one side of the leadframe, packaging a bottom integrated circuit on an opposite side of the leadframe, and forming external electrical interconnects on the leadframe.... Agent: Ishimaru & Zahrt LLP

20070108609 - Bumped chip carrier package using lead frame and method for manufacturing the same: A bumped chip carrier (BCC) package may include a semiconductor chip on which at least one bonding pad is formed, at least one lead frame terminal arranged close to the semiconductor chip, wherein a lower portion of the lead frame terminal is located beneath a bottom side of the semiconductor... Agent: Lee & Morse, P.C.

20070108610 - Embedded semiconductor device substrate and production method thereof: An embedded semiconductor device substrate having a semiconductor device integrated therein is formed by disposing a semiconductor device in an opening provided on an insulating resin, and sandwiching the semiconductor device and the insulating resin with a front surface wiring layer and a rear surface wiring layer and performing heat... Agent: Morgan & Finnegan, L.L.P.

20070108612 - Chip structure and manufacturing method of the same: A chip structure and a manufacturing method of the same. The chip structure includes a base, a pad, a first passivation layer, a second passivation layer and a bump. The pad is formed on the base. The first passivation layer is formed on the base exposing the pad. The second... Agent: Birch Stewart Kolasch & Birch

20070108613 - Microelectronic connection component: A microelectronic connection component includes a substrate having a first surface, a second surface and a peripheral edge. First and second terminals are exposed at the first surface of the substrate. Wire bond pads are exposed proximate the peripheral edge of the substrate at the first surface. First conductive paths... Agent: Tessera Lerner David Et Al.

20070108611 - Stacking method and stacked structure for attaching memory components to associated device: A stacking method and structure for attaching memory components to a ball grid array (BGA) device are provided. A specialized carrier includes multiple memory devices such as memory die, or chip scale packaging (CSP) memory. The specialized carrier is attached to a mating supporting carrier to form a stacked structure.... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070108614 - Semiconductor device and method for manufacturing the same: At least a laminate of a gate insulating film 6 and a gate electrode 7 and an active region 13 are formed on a silicon substrate 1, and an underlying interlayer insulating film 10 is further formed. Then, a conductor 11a connected to the gate electrode 7, and a conductor... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070108615 - Integrated circuit system with metal-insulator-metal circuit element: An integrated circuit system is provided including forming a substrate, forming a first contact having multiple conductive layers over the substrate and a layer of the multiple conductive layers on other layers of the multiple conductive layers, forming a dielectric layer on the first contact, and forming a second contact... Agent: Ishimaru & Zahrt LLP

20070108616 - Semiconductor device and method for fabricating the same: A semiconductor device includes an insulation film 6 formed on a silicon substrate 1, a buried metal interconnect 8 formed in the insulation film 6, and a barrier metal film 7 formed between the insulation film 6 and the metal interconnect 8. The barrier metal film 7 is a metal... Agent: Mcdermott Will & Emery LLP

20070108617 - Semiconductor component comprising interconnected cell strips: A semiconductor component comprises a semiconductor body including a front side and a number of cell strips. Each of the cell strips includes a terminal zone of a first type arranged on the front side of the semiconductor body and a terminal zone of a second type arranged on the... Agent: Maginot, Moore & Beck Chase Tower

20070108618 - Semiconductor device: A semiconductor device is disclosed, which includes at least two layers superposed on each other in a stacking direction above a substrate, each of the layers including an insulating film a conductive layer films, a conductive plug electrically connected to the conductive layer, and at least one dummy via chain... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070108619 - Bonding pad with high bonding strength to solder ball and bump: A bonding pad with high bonding strength to a solder ball and a bump includes a carrier, a wiring layer formed on the carrier, a protection layer formed on top of the wiring layer and a solder mask layer surrounded around the protection layer and the wiring layer to form... Agent: Lin & Associates Intellectual Property

20070108620 - Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.... Agent: Sughrue Mion, PLLC

20070108621 - Integrated circuit package system with arched pedestal: An integrated circuit package system includes an arched pedestal integrated circuit die including an active surface, a die mounting surface, a pedestal portion including an arch intersecting the die mounting surface and having an arch height, and the arch under a portion of the active surface and having an arch... Agent: Ishimaru & Zahrt LLP

20070108622 - Semiconductor device having several assembled integrated-circuit chips and method of assembling and electrically connecting the integrated-circuit chips: A semiconductor device includes several assembled integrated-circuit chips. A main integrated-circuit chip has at least one cavity in which electrical contacts are provided. A secondary integrated-circuit chip includes an edge which engages in the cavity of the main chip and has electrical contacts. When the secondary integrated-circuit chip is inserted... Agent: Jenkens & Gilchrist, PC

20070108623 - Chip and package structure: The invention is directed to a chip comprising a substrate having a plurality of pads located thereon and a passivation layer located over the substrate, wherein the passivation layer has a plurality of openings and recesses formed therein and the openings expose the pads respectively. During the later performed packaging... Agent: Jianq Chyun Intellectual Property Office

20070108626 - Flip-chip integrated circuit packaging method: A flip-chip integrated circuit (IC) packaging method includes providing a carrier which has a top surface and a bottom surface and providing a plurality of IC dies, each die having a back side and being mounted on the top surface of carrier by flip chip bonding. The method further includes... Agent: North America Intellectual Property Corporation

20070108624 - Integrated circuit package system with downset lead: An integrated circuit package system includes an integrated circuit package having a downset terminal lead, a planar recessed lead surface of the downset terminal lead, and an attached integrated circuit over the planar recessed lead surface.... Agent: Ishimaru & Zahrt LLP

20070108628 - Mounting substrate and semiconductor device: A mounting substrate for mounting a semiconductor chip in a flip chip manner, having a plurality of connection pads to which the semiconductor chip is connected, an insulating pattern formed so as to cover a part of the connection pads, and a plurality of dummy patterns for controlling a flow... Agent: Rankin, Hill, Porter & Clark LLP

20070108625 - Package and package module of the package: A package includes a carrier, a first chip, a first dielectric layer and at least one first connecting part. The carrier has a first surface and a second surface, and at least one first pad is disposed on the second surface. The first chip is disposed on the first surface.... Agent: Birch Stewart Kolasch & Birch

20070108627 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a wiring board having a plurality of conductive wires aligned on an insulating base material and a board bump with a plated metal formed on each conductive wire so as to cover an upper surface and both sides of the conductive wire; and a semiconductor chip... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070108629 - Wafer level chip scale packaging structure and method of fabricating the same: A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer... Agent: Birch Stewart Kolasch & Birch

20070108630 - Article having island structure and producing method thereof: A producing method according to the invention of an article having an island structure fundamentally includes a step of coating a forming material having the fluidity on a substrate, a step of facing the substrate and a forming mold with the forming material having the fluidity interposed therebetween to pressurize,... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20070108631 - Wired circuit board and method for manufacturing wired circuit board and mounting electronic component thereon: A wired circuit board is provided having a high-reliability conductive pattern formed thereon and mounting an electronic component thereon with high accuracy, and a method is provided for manufacturing the wired circuit board and mounting the electronic component thereon. An insulating layer including a mounting portion is formed on a... Agent: Akerman Senterfitt

20070108632 - Semiconductor chip having bond pads: In one embodiment, a semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on at least a part of the peripheral region of the semiconductor... Agent: Marger Johnson & Mccollom, P.C.

20070108633 - Semiconductor chip having bond pads: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a... Agent: Marger Johnson & Mccollom, P.C.

20070108635 - Integrated circuit package system: An integrated circuit package system is provided forming an integrated circuit die having a non-active side and an active side, elevating a die paddle above an external interconnect, attaching the active side on a bottom side of the die paddle, and partially encapsulating the integrated circuit die, the die paddle,... Agent: Ishimaru & Zahrt LLP

20070108634 - Packaged electronic element and method of producing electronic element package: A first container member (9, 109, 212) mounting an electronic device (71, 171, 261) thereon and a second container member (2, 102, 202) are bonded with an adhesive (3, 103) or a metal layer (103, 251). Thus an inner space (90, 190, 211) is formed and the electronic device can... Agent: Wenderoth, Lind & Ponack L.L.P.

20070108636 - Semiconductor device: A semiconductor device including a substrate having a main surface including a first area, a second area surrounding the first area, and a third area surrounding the second area; a first insulating protective film that is provided in the first area and formed in a shape having no angles; a... Agent: Nixon Peabody, LLP

20070108637 - Semiconductor device and method for producing it, and use of an electrospinning method: A semiconductor device and a method for producing it, and the use of the electrospinning method is disclosed. In one embodiment, delamination of the plastic housing composition from the circuit carrier can occur under loading, which can lead to the failure of the semiconductor device. For better adhesion, an adhesion-promoting... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070108638 - Alignment mark with improved resistance to dicing induced cracking and delamination in the scribe region: A robust alignment mark used in semiconductor processing to help deter the expansion of cracks and delamination caused by the cutting of a dicing blade. A cross-shaped structure is used as a line site for alignment of the dicing blade. A plurality of rectangular elements is situated about the periphery... Agent: Law Office Of Delio & Peterson, LLC.

20070108639 - Semiconductor device and method for fabricating the same: A spacer layer is formed on a single-crystal substrate and an epitaxially grown layer composed of a group III-V compound semiconductor layer containing a nitride or the like is further formed on the spacer layer. The epitaxially grown layer is adhered to a recipient substrate. The back surface of the... Agent: Mcdermott Will & Emery LLP

20070102691 - Silver-selenide/chalcogenide glass stack for resistance variable memory: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one... Agent: Dickstein Shapiro LLP

20070102692 - Semiconductor light emitting device: A semiconductor light emitting device includes a semiconductor light emitting portion, a front surface electrode provided on one side of the semiconductor light emitting portion, an electrically conductive substrate provided on the other side of the semiconductor light emitting portion, the electrically conductive substrate being transparent to a wavelength of... Agent: Rabin & Berdo, PC

20070102693 - Semiconductor light emitting device, lighting module, lighting apparatus, display element, and manufacturing method for semiconductor light emitting device: In an LED array chip (2), LEDs (6) are connected together in series by a bπ dging wire (30) The LEDs (6) each have a semiconductor multilayer structure (8-18) including a light emitting layer (14) Here, the semiconductor multilayer structure (8-18) is epitaxially grown on a front surface of an... Agent: Snell & Wilmer L.L.P. (matsushita)

20070102694 - Polymer-nanocrystal quantum dot composites and optoelectronic devices: Disclosed are compositions including semiconducting polymers and quantum dot nanocrystals. Also disclosed are optoelectronic devices prepared from semiconducting polymers and quantum dot nanocrystals. Also are disclosed methods of increasing the quantum efficiency in optoelectronic devices and methods of generating a photocurrent.... Agent: Woodcock Washburn LLP

20070102695 - Crosslinkable substituted fluorene compounds and conjugated oligomers or polymers based thereon: Crosslinkable substituted fluorene compounds; oligomers and polymers prepared from such crosslinkable compounds; films and coatings; and multilayer electronic devices comprising such films are disclosed.... Agent: Sughrue Mion, PLLC

20070102697 - Junction structure of organic semiconductor device, organic thin film transistor and fabricating method thereof: A junction structure of an organic semiconductor device including an organic semiconductor layer, a conductive layer and a modifying layer is provided. The modifying layer is formed between the organic semiconductor layer and the conductive layer, wherein the modifying layer includes an inorganic compound or an organic complex compound. An... Agent: Jianq Chyun Intellectual Property Office

20070102698 - Organic electronic device: where EF1 is a Fermi energy level of the conductive layer of the first electrode, EnL is an LUMO energy level of the n-type organic compound layer of the first electrode, and EpH is an HOMO energy level of the p-type organic compound layer forming the NP junction together with... Agent: Mckenna Long & Aldridge LLP

20070102696 - Organic semiconducting layers: An organic semiconducting layer formulation, which comprises: an organic binder which has a permittivity, ∈, at 1,000 Hz of 3.3 or less; and a polyacene compound of Formula: A: wherein: each of R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11 and (R12, which may be the same... Agent: Millen, White, Zelano & Branigan, P.C.

20070102699 - Organic thin film transistor, flat panel display apparatus having the same, and a method of manufacturing organic thin film transistor: An organic thin film transistor (TFT) that allows an organic semiconductor layer to be easily patterned includes a gate electrode, source and drain electrodes insulated from the gate electrode, a self-assembly monolayer formed on the source and drain electrodes, an organic semiconductor layer which is insulated from the gate electrode... Agent: Stein, Mcewen & Bui, LLP

20070102700 - Electrical open/short contact alignment structure for active region vs. gate region: An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070102701 - Structure and method for parallel testing of dies on a semiconductor wafer: In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a... Agent: Townsend And Townsend And Crew, LLP

20070102703 - Semiconductor device and method of manufacturing the same: In a semiconductor device and a method of manufacturing the semiconductor device, the source wires 126 of a pixel portion 205 are formed of material having low resistance (representatively, aluminum, silver, copper). The source wires of a driving circuit are formed in the same process as the gate wires 162... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070102702 - Semiconductor device including active matrix circuit: There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin... Agent: Nixon Peabody, LLP

20070102704 - Semiconductor device and manufacturing method: A method for manufacturing a semiconductor device having a circuit made up by a TFT (Thin Film Transistor) having GOLD (Gate-Drain Overlapped LDD) structure, which an LDD region overlaps which a portion of a gate electrode, wherein the formation of a concentration depth profile peak of hydrogen in a semiconductor... Agent: Fish & Richardson P.C.

20070102705 - Thin film transistors and semiconductor constructions: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer... Agent: Wells St. John P.s.

20070102707 - Array substrate for liquid crystal display device and method of fabricating the same: An array substrate for an LCD device and a method of fabricating the same are disclosed. The array substrate includes: a substrate defining a display area and a non-display area; an n-type driving and a p-type driving TFT in the non-display area; a switching TFT in the display region; a... Agent: Mckenna Long & Aldridge LLP

20070102706 - Semiconductor device and manufacturing method thereof: Provided is a semiconductor device and a manufacturing method thereof. The method includes the steps of: forming a thin film transistor including a substrate having a semiconductor layer and silicon, a gate insulation layer formed on the semiconductor layer, a gate electrode formed on the gate insulation layer, and source... Agent: Blakely Sokoloff Taylor & Zafman

20070102708 - Semiconductor device provided by silicon carbide substrate and method for manufacturing the same: A semiconductor device includes a first field effect transistor including a source and a gate and disposed in a silicon carbide substrate; and a second field effect transistor including a drain and a gate and disposed in the substrate. The drain of the second field effect transistor connects to the... Agent: Posz Law Group, PLC

20070102709 - P-type group ii-vi semiconductor compounds: A persistent p-type group II-VI semiconductor material is disclosed. The group II-VI semiconductor includes atoms of group II elements, atoms of group VI elements, and one or more p-type dopants. The p-type dopant concentration is sufficient to render the group II-VI semiconductor material in a single crystal form. The semiconductor... Agent: Kirton And Mcconkie

20070102711 - Led having a reflector layer of improved contact ohmicity and method of fabrication: An LED has a light-generating semiconductor region formed on a baseplate via an electroconductive reflector layer. The light-generating semiconductor region has an active layer sandwiched between a pair of claddings of opposite conductivity types for generating light. For good ohmic contact with the light-generating semiconductor region without any substantive diminution... Agent: Woodcock Washburn LLP

20070102710 - Lighting device and method: A lighting device having a light emitting diode (LED). The device includes a metal substrate having a surface. A dielectric coating layer is superimposed on the surface of the metal substrate. A light emitting diode (LED) is supported on the dielectric coating layer. The metal substrate serves as a heat... Agent: Rankin, Hill, Porter & Clark, LLP

20070102712 - Optical semiconductor device and method for manufacturing the same: An optical semiconductor device includes a first set of lead frames having a first set of element mounting beds, a second set of lead frames having a second set of element mounting beds, which are arranged substantially on a same plane as the first set of element mounting beds. A... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070102713 - Semiconductor device and manufacturing method thereof: OFF current of a TFT is reduced. There is provided a semiconductor device comprising: a substrate; a shielding film formed so as to be in contact with the substrate; a planarization insulating film formed on the substrate so as to cover the shielding film; and a semiconductor layer formed so... Agent: Fish & Richardson P.C.

20070102714 - Display device and manufacturing method thereof: The present invention discloses a display device having a substrate; a light emitting layer arranged on the substrate; a first electrode arranged on the light emitting layer; and a second electrode facing the first electrode, where the light emitting layer is arranged between the second electrode and the first electrode.... Agent: H.c. Park & Associates, PLC

20070102715 - Semiconductor light emitting device: The invention relates to a high-quality semiconductor light emitting device which suppresses current concentration. The semiconductor light emitting device includes an n-type semiconductor layer, an active layer and a p-type semiconductor layer sequentially formed on a substrate. The semiconductor light emitting device further includes a p-electrode formed on the p-type... Agent: Mcdermott Will & Emery LLP

20070102716 - Image sensor and fabricating method thereof: An image sensor and fabricating method thereof enable total photoelectric conversion without light loss by enhancing surface uniformity of a microlens in each area of the microlens. The method includes the steps of forming a sublayer including a photodiode, a thin film transistor and metal lines on a substrate including... Agent: Mckenna Long & Aldridge LLP

20070102721 - High light extraction efficiency light emitting diode (led): An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED) combined with a shaped plastic optical element, in which the directional light from the ZnO cone, or from any high refractive index material in contact with the LED surface, entering the shaped plastic optical element is extracted... Agent: Gates & Cooper LLP Howard Hughes Center

20070102717 - Led packaging: An LED packaging construction has a chip embedded on a recessed carrier on substrate; conduction circuits with different electrodes being disposed to the peripheral of the carrier; electrode layer of chip being connected to conduction circuits with golden plated wire; fluorescent powder being filled in the carrier before mounting the... Agent: Troxell Law Office PLLC

20070102718 - Lens in light emitting device: In an embodiment, there is disclosed an opto-electronic package, comprising a substrate, a plurality of light emitting diode (LED) dice, and at least one lens disposed between the cavity-defining walls and having a maximum height remaining within an aperture of an elongate cavity of the substrate. In an embodiment, there... Agent: Avago Technologies, Ltd.

20070102719 - Light emitting diode: A light emitting diode (10, 20, 30, 40) includes an illuminant element (12) and a package (14, 24, 34, 44). The illuminant element defines an optical axis (OO′, O1O1′, O2O2′, O3O3′). The package has a transparent surface (141, 241, 341, 441) oblique to the optical axis. The illuminant element is... Agent: Morris Manning Martin LLP

20070102720 - Light-emitting module and backlight unit having the same: A light-emitting module is provided. The light-emitting module comprises a printed circuit board, a plurality of light-emitting devices, and at least one module lens. The plurality of light-emitting devices are formed on the printed circuit board. At least one module lens is supported by the printed circuit board and reflects... Agent: Birch Stewart Kolasch & Birch

20070102722 - Light emitting diode unit: A light emitting diode unit including a base (100) made of anodized aluminum and a printed board (101) attached to the base (100) and the printed board (101) including a predetermined conductive pattern (102) and an opening (101a) having an area for die-bonding at least one LED chip (113) to... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20070102723 - Zinc-oxide-based light-emitting diode: A light-emitting zinc oxide based compound semiconductor device of a double-heterostructure. The double-heterostructure includes a light-emitting layer formed of a low-resistivity Mg1-x-yCdxZnyO; 0≦x<1, 0<y≦1, and x+y=0.1 to 1 compound semiconductor doped with p-type and/or n-type impurity. A first clad layer is joined to one surface of the light-emitting layer and... Agent: Alston & Bird LLP

20070102724 - Vertical diode doped with antimony to avoid or limit dopant diffusion: Use of antimony as an n-type conductivity-enhancing dopant in semiconductor structures having a vertical dopant profile is described. Dopants tend to diffuse, and steep dopant gradients can be difficult to maintain. Specifically, when a silicon layer is doped with phosphorus or arsenic, both n-type dopants, dopant atoms tend to seek... Agent: Patent Dept., Sandisk 3d LLC(matrix)

20070102725 - Insulated gate planar integrated power device with co-integrated schottky diode and process: A process for integrating a Schottky contact inside the apertures of the elementary cells that constitute the integrated structure of the insulated gate power device in a totally self-alignment manner does not requires a dedicated masking step. This overcomes the limits to the possibility of increasing the packing density of... Agent: Graybeal, Jackson, Haley LLP

20070102727 - Field-effect transistor: A field-effect transistor in the present invention has a source, a first gate, a second gate and a drain, which are formed in this order at positions away from each other on a semiconductor layer along the surface of the semiconductor layer and each of which has a metal electrode.... Agent: Birch Stewart Kolasch & Birch

20070102726 - Semiconductor device for improving channel mobility: A semiconductor device includes a substrate, a gate electrode formed on the substrate, a source region and a drain region formed in the substrate, the source region and the drain region formed located on the both side of the gate electrode, a first insulating film formed on the substrate, the... Agent: SprinkleIPLaw Group

20070102728 - Method and system for controlled oxygen incorporation in compound semiconductor films for device performance enhancement: A method and system for providing a bipolar transistor is described. The method and system include providing a compound base region, providing an emitter region coupled with the compound base region, and providing a collector region coupled with the compound base region. The bipolar transistor may also include at least... Agent: Sawyer Law Group LLP

20070102729 - Method and system for providing a heterojunction bipolar transistor having sige extensions: A method and system for providing a bipolar transistor is described. The method and system include providing a compound base region including includes a compound box extension, providing an emitter region, and providing a collector region. The emitter region is coupled with the base region. The SiGe base region is... Agent: Sawyer Law Group LLP

20070102730 - Switching circuit and semicondcutor device: An RF switching circuit according to the present invention includes: a plurality of input/output terminals for inputting and outputting an RF signal; and a switch for opening and closing an electrical connection between the input/output terminals. The switch is constituted by a multi-gate field effect transistor including a plurality of... Agent: Mcdermott Will & Emery LLP

20070102731 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes first and second element isolation insulating films, first and second gate insulating films, first and second gate wiring and first and second mask layer. First and second upper surfaces of the first and second element isolation insulating films are higher than an upper surface of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070102732 - Metal oxide semiconductor device: A MOS device includes: a semiconductor substrate; an insulator layer formed on the semiconductor substrate, and including a fluorine-containing titanium dioxide film that has grain boundary defects passivated by fluorine; and upper and lower electrodes formed on the insulator layer and the semiconductor substrate, respectively.... Agent: Christie, Parker & Hale, LLP

20070102733 - Multi-chip assembly with optically coupled die: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die... Agent: Intel Corporation C/o Intellevate, LLC

20070102735 - Semiconductor device and method for manufacturing the semiconductor device: A semiconductor device includes: a semiconductor substrate; a well formed on the semiconductor substrate; a semiconductor layer formed by epitaxial growth avoiding the well; a buried insulating layer embedded between the semiconductor substrate and the semiconductor layer; a first gate electrode formed on the semiconductor layer, the first gate electrode... Agent: Oliff & Berridge, PLC

20070102734 - Semiconductor device and method of fabricating the same: Disclosed is a semiconductor device and method of fabricating the same. The semiconductor device is applicable to various electronic devices such as transistors or memories with transistors. A MOS transistor of the semiconductor device includes a first region and a second region, different in impurity concentration, which are formed in... Agent: Mills & Onello LLP

20070102736 - Image sensor device and method for manufacturing the same: The invention is directed to a method for manufacturing an image sensor device. The method comprises steps of forming a photodiode and a transistor on a substrate. A salicide block is formed over a photo-sensing region of the photodiode. An interconnects processes is performed several times to forming a plurality... Agent: Jianq Chyun Intellectual Property Office

20070102737 - Display unit, method of manufacturing same, organic light emitting unit, and method of manufacturing same: A display unit capable of being simply designed and manufactured by using more simplified light emitting device structure while capable of high definition display and display with superior color reproducibility and a manufacturing method thereof are provided. The display unit is a display unit (1), wherein a plurality of organic... Agent: Bell, Boyd & Lloyd, LLP

20070102739 - Cmos image sensor: A CMOS image sensor includes a semiconductor substrate; a pinned photodiode formed in a light-sensing region of the semiconductor substrate, the pinned photodiode comprising a charge-accumulating diffusion region and a surface pinning diffusion region overlying the charge-accumulating diffusion region; a transfer transistor, wherein the transfer transistor has a transfer gate... Agent: North America Intellectual Property Corporation

20070102740 - Deep trench contact and isolation of buried photodetectors: The invention provides vertically-stacked photodiodes buried in a semiconductor material that are isolated and selectively contacted by deep trenches. One embodiment of the invention provides a pixel sensor comprising: a plurality of photosensitive elements formed in a substrate, each photosensitive element being adapted to generate photocharges in response to electromagnetic... Agent: Hoffman, Warnick & D'alessandro LLC

20070102738 - Light shield for cmos imager: The present invention provides a light shield for shielding the floating diffusion of a complementary metal-oxide semiconductor (CMOS) imager. In accordance with an embodiment of the present invention, there is provided a pixel sensor cell including: a device region formed on a substrate; and a first layer of material forming... Agent: Hoffman, Warnick & D'alessandro LLC

20070102742 - Capacitor and method for fabricating the same: A capacitor includes a lower electrode, a dielectric structure over the lower electrode, the dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer, and an upper electrode formed over the dielectric structure. A method for fabricating a capacitor includes... Agent: Blakely Sokoloff Taylor & Zafman

20070102743 - Switchable memory diode - a new memory device: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an... Agent: Amin, Turocy & Calvin, LLP

20070102741 - Thin film capacitor-embedded printed circuit board and method of manufacturing the same: Disclosed herein is a printed circuit board with an embedded thin-film capacitor, and a method of manufacturing the same. Specifically, the present invention relates to a printed circuit board with an embedded thin-film capacitor, comprising a lower electrode formed on an insulating substrate; an amorphous paraelectric film formed on the... Agent: Mcdermott Will & Emery LLP

20070102744 - Semiconductor device and method of manufacturing the same: A method of manufacturing semiconductor devices is provided. The device includes a trench capacitor formed in a semiconductor substrate for configuring a DRAM cell together with a cell transistor. The method comprises forming a trench in a semiconductor substrate; forming a collar insulation film on sidewalls of the trench, the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070102745 - Capacitor structure: A capacitor structure is described, including a first capacitor and a second capacitor. The first capacitor includes a first electrode, a second electrode and a first insulating layer, wherein the second electrode is disposed under the first electrode and the first insulating layer between the first electrode and the second... Agent: Jianq Chyun Intellectual Property Office

20070102746 - Semiconductor integrated circuit devices and methods of forming the same: A semiconductor integrated circuit device includes a first interlayer insulation film having a contact therein. The contact has an upper surface and including a void therein having an open upper portion. The device further includes a plasma damage reduction unit including a lower electrode conformably on the void of the... Agent: Myers Bigel Sibley & Sajovec

20070102750 - Charge trap flash memory device, fabrication method thereof, and write/read operation control method thereof: In one aspect, a charge trap flash memory device is provided which includes a semiconductor substrate, source and drain regions which are spaced apart in an active region of the semiconductor substrate to define a channel region therebetween, a tunneling dielectric layer located on the channel region, an organic polymer... Agent: Volentine Francos, & Whitt PLLC

20070102747 - Complementary carbon nanotube triple gate technology: Disclosed is a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs. One embodiment of the invention provides either a stable p-type CNTFET or a stable n-type CNTFET. Another embodiment of the invention provides a complementary CNT device. In order to overcome the ambipolar properties of a CNTFET, source/drain... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070102748 - Gate electrode and mos transistor including gate and method of fabricating the same: A gate electrode. The gate electrode includes a substrate, a gate dielectric layer formed thereon, and a gate conductive layer comprising a stack of polysilicon grains formed on the gate dielectric layer, wherein the average size of the polysilicon grains decreases gradually in a direction away from the substrate. The... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070102749 - Semiconductor memory device and method of fabricating the same: A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070102751 - Non-volatile memory device and method of manufacturing the same: A non-volatile memory device and a method of manufacturing the same where the non-volatile memory device is easily applicable to higher integration of a semiconductor device by reducing a cell size while assuring storage capacities required for operations of a device. The non-volatile memory device includes a semiconductor substrate in... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070102753 - cross diffusion barrier layer in gate structure: Various embodiments include a substrate having including a first doped region and a second doped region located on a first side of the substrate, and a third doped region and a fourth doped region located on a second side of the substrate, an insulation layer overlying the substrate, a gate... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070102752 - Flash memory device and method of fabricating the same: A flash memory device includes trenches that are formed at regions on a semiconductor substrate spaced apart from one another at predetermined distances, buried floating gates buried into the trenches, a plurality of isolation structures formed between the buried floating gates, and a dielectric film and a control gate formed... Agent: Townsend And Townsend And Crew, LLP

20070102755 - Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or... Agent: Larson Newman Abel Polansky & White, LLP

20070102754 - Non-volatile memory device: A single-poly non-volatile memory device invented to integrate into logic process is disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS access transistor that is serially connected to a PMOS storage transistor formed in a cell array area, and, in a peripheral circuit area, a high-voltage... Agent: North America Intellectual Property Corporation

20070102756 - Finfet transistor fabricated in bulk semiconducting material: A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from bulk semiconductor wafers, as opposed to silicon-on-insulator (SOI) or separation by implantation of oxygen (SIMOX) wafers, in a highly uniform and reproducible manner. The method facilitates formation of... Agent: Schneck & Schneck

20070102757 - Semiconductor device and a method of manufacturing the same: To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070102758 - Semiconductor device and method for manufacturing the same: A semiconductor device may include a semiconductor substrate having a recessed surface, a gate insulating layer formed on the recessed surface of the semiconductor substrate, a gate electrode formed on the gate insulating layer, and a source/drain area formed at both sides of the gate electrode, according to embodiments.... Agent: Sherr & Nourse, PLLC

20070102759 - Method for forming an integrated circuit with high voltage and low voltage devices: A method is disclosed for integrally forming at least one low voltage device and at least one high voltage device. According to the method, a first gate structure and a second gate structure are formed on a semiconductor substrate, wherein the first and second gate structures are isolated from one... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070102760 - Inhibiting radiation hardness of integrated circuits: A system and method for inhibiting radiation hardness of Silicon on Insulator (SOI) integrated circuits is described. An electrical connection is used to connect a substrate below a buried oxide layer to the topside above the buried oxide layer. A bias is then applied to the substrate. The bias may... Agent: Honeywell International Inc.

20070102761 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate, a channel region formed above the semiconductor substrate, a first gate electrode formed above the channel region via a first gate insulating film, a second gate electrode formed below the channel region via a second gate insulating film to face the first gate... Agent: Foley And Lardner LLP Suite 500

20070102762 - Semiconductor device, and semiconductor package and circuit device using the same: A first semiconductor element and a second semiconductor element each have an electrode forming surface with an electrode pad thereon. The first semiconductor element and the second semiconductor element are stacked to expose each electrode pad and bonded while facing the electrode forming surfaces each other. The electrode pads of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070102763 - Multiple-gate transistors formed on bulk substrates: In one aspect, the present invention teaches a multiple-gate transistor 130 that includes a semiconductor fin 134 formed in a portion of a bulk semiconductor substrate 132. A gate dielectric 144 overlies a portion of the semiconductor fin 134 and a gate electrode 146 overlies the gate dielectric 144. A... Agent: Slater & Matsil, L.L.P.

20070102764 - Multiple-gate transistors formed on bulk substrates: According to one embodiment, an information storage medium, and the program comprises referring to a manifest from a playlist that manages playback presentation of a playback presentation object, referring to one of a markup and a script from the manifest, monitoring defining of a name corresponding to an event in... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070102765 - Layout structure of electrostatic discharge protection circuit: A layout structure of electrostatic discharge (ESD) protection circuit cooperated with an ESD protection device includes a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer is disposed on the ESD protection device and electrically connected to the ESD protection device. The second electrically... Agent: Birch Stewart Kolasch & Birch

20070102767 - Method of forming dual gate dielectric layer: A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer is formed on a first region. The semiconductor device also includes a second... Agent: Marger Johnson & Mccollom, P.C.

20070102766 - Semiconductor transistors with contact holes close to gates: A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the... Agent: Schmeiser, Olsen & Watts

20070102768 - Semiconductor device and a method of manufacturing the same: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070102769 - Dual soi structure: A semiconductor structure having a hybrid crystal orientation is provided. The semiconductor structure includes an insulator layer, e.g., a buried oxide (BOX), on a first semiconductor layer, and a second semiconductor layer on the buried oxide, wherein the first and second semiconductor layers have a first and a second crystal... Agent: Slater & Matsil, L.L.P.

20070102770 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a... Agent: F. Chau & Associates, LLC

20070102771 - Metal oxide semiconductor device: The invention is directed to a gate conductive layer, wherein the gate conductive layer straddles over an isolation region and an active region in the isolation region. The gate conductive layer comprises a first portion and a second portion. The first portion is located over the active region and at... Agent: Jianq Chyun Intellectual Property Office

20070102772 - Self-aligned nanometer-level transistor defined without lithography: A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates formation of FinFET devices with improved and reproducible fin height control while providing isolation between... Agent: Schneck & Schneck

20070102773 - Semiconductor device and method of manufacturing same: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided on the major surface of the semiconductor layer,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070102774 - Gate structure and method of fabricating the same: A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases... Agent: Jianq Chyun Intellectual Property Office

20070102775 - Methods of fabricating semiconductor devices and structures thereof: Methods of forming spacers on sidewalls of features of semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece and at least one feature disposed over the workpiece. A first spacer is disposed on the sidewalls of the at least one feature, the... Agent: Slater & Matsil LLP

20070102776 - Replacement metal gate transistors with reduced gate oxide leakage: Thin effective gate oxide thickness with reduced leakage for replacement metal gate transistors is achieved by forming a protective layer between the gate oxide layer and metal gate electrode, thereby reducing stress. Embodiments include forming a protective layer of amorphous carbon containing metal carbides decreasing in concentration from the metal... Agent: Mcdermott Will & Emery LLP

20070102777 - Electronic packaging for optical emitters and sensors: A VCSEL die is packaged so that its optical axis is at a predetermined non-perpendicular and nonparallel angle relative to the plane of a PCB to which the packaged die will be mounted. The die is packaged to form an emitting component which is shaped to orient the VCSEL optical... Agent: Banner & Witcoff, Ltd. Attorneys For Client Nos. 003797 & 013797

20070102778 - Photoreceiver cell with color separation: A photoreceiver cell with separation of color components of light incident to its surface, formed in a silicon substrate of the conductivity of the first type with an ohmic contact and comprising: the first, second and third regions, which have mutual positioning and configuration, which provide formation of the first... Agent: Macpherson Kwok Chen & Heid LLP

20070102779 - Differential mechanical stress-producing regions for integrated circuit field effect transistors: Integrated circuit field effect transistors include a substrate, an isolation region in the substrate that defines an active region in the substrate, spaced apart source/drain regions in the active region, a channel region in the active region between the spaced apart source/drain regions and an insulated gate on the channel... Agent: Myers Bigel Sibley & Sajovec

20070102780 - Low dark current cmos image sensor pixel having a photodiode isolated from field oxide: A low dark current CMOS image sensor pixel comprises a photodiode that is isolated from the field oxide by forming a relatively small photodiode within a relatively large active area such that the field oxide is substantially separated from the photodiode. The active area should be large enough such that... Agent: Frank Pincelli, Patent Legal Staff Eastman Kodak Company

20070102781 - Split transfer gate for dark current suppression an imager pixel: A pixel with a photosensor and a transfer transistor having a split transfer gate. A first section of the transfer gate is connectable to a first voltage source while a second section of the transfer gate is connectable to a second voltage source. Thus, during a charge integration period of... Agent: Dickstein Shapiro LLP

20070102782 - Triple operation voltage device: A triple operation voltage device including a first type substrate, a high voltage (HV) first type well, a second type well, a low voltage (LV) device well, and a middle voltage (MV) device well is provided. The HV first type well is disposed inside the first type substrate. The second... Agent: J.c. Patents, Inc.

20070102783 - Insultating structures: An electrical insulator comprises an elongate shank and one or more sheds disposed along the length of the shank. The surface of the insulator comprises longitudinally extending flutes, the depth of which are varied along the length of the insulator such that the circumferential distance of all transverse sections along... Agent: Gordon & Jacobson, P.C.

20070102784 - Electronic component: An electronic component includes a substrate, a capacitor, and a wiring. The capacitor has a multilayer structure including a first electrode film provided on the substrate, a second electrode film of 2 to 4 μm in thickness disposed to face the first electrode film, and a dielectric film interposed between... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070102786 - Semiconductor device: A semiconductor device of the present invention comprises: a substrate; a plurality of wiring layers formed over the substrate; a fuse formed in an uppermost one of the plurality of wiring layers; a first insulating film made up of a single film and formed on the uppermost wiring layer such... Agent: Buchanan, Ingersoll & Rooney PC

20070102785 - Semiconductor device with fuse and method of fabricating the same: A semiconductor device having a fuse and a method of fabricating the same are provided. An embodiment of he semiconductor device includes a fuse pattern having a fuse conductive pattern disposed on a semiconductor substrate and a fuse capping pattern disposed on the fuse conductive pattern. An upper insulating layer... Agent: Marger Johnson & Mccollom, P.C.

20070102787 - Capacitor integrated in a structure surrounding a die: An integrated circuit comprises a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip. The integrated circuitry is disposed within the circuit area. No active circuit is disposed within the peripheral area. A barrier is disposed within the peripheral... Agent: Slater & Matsil LLP

20070102788 - Multi-terminal capacitor: A multi-terminal capacitor includes a first capacitor plate, a second capacitor plate in parallel with the first capacitor plate, and a third capacitor plate in parallel with the first and second capacitor plates. The first, second and third capacitor plates are separated from each other by dielectric material, such that... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070102789 - Bipolar transistor and back-gated transistor structure and method: A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor... Agent: Hoffman, Warnick & D'alessandro LLC

20070102790 - Process for deposition of semiconductor films: Chemical vapor deposition processes utilize higher order silanes and germanium precursors as chemical precursors. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, trisilane is employed to deposit SiGe-containing films that are useful... Agent: Knobbe Martens Olson & Bear LLP

20070102791 - Structure of multi-layer crack stop ring and wafer having the same: A multi-layer crack stop ring structure disposed between a die seal ring and a scribe line or disposed between a dual die seal ring is provided. The multi-layer crack stop ring structure does not occupy the space of the scribe line. In addition, the multi-layer crack stop ring structure is... Agent: Jianq Chyun Intellectual Property Office

20070102792 - Multi-layer crack stop structure: A multi-layer crack stop structure is described, disposed entirely in a die, entirely in a scribe line region outside the die, or partially in the die and partially in the scribe line region. The multi-layer crack stop structure is formed by stacking multiple layers of hollow crack stop units. The... Agent: Jianq Chyun Intellectual Property Office

20070102793 - Semiconductor chip and method of fabricating the same: A semiconductor chip may include a semiconductor substrate that may have a semiconductor device pattern. A passivation layer may be provided on a surface of the semiconductor substrate. At least one elastic protecting layer may be provided on the passivation layer. The elastic protecting layer may have a pattern composed... Agent: Harness, Dickey & Pierce, P.L.C

20070102794 - Lead arrangement and chip package using the same: A lead arrangement applied to the leadframe of a chip package is provided. The lead arrangement includes at least a pair of differential signal leads and at least a non-differential signal lead. The pair of differential signal leads includes a first differential signal lead and a second differential signal lead.... Agent: J.c. Patents, Inc.

20070102795 - Radiator plate and semiconductor device: A radiator plate 20 is mounted on a back surface of a semiconductor element 11 on a substrate 10 so that heat is radiated from the semiconductor element 11. The radiator plate 20 includes first radiating fins 20b formed on the one side which is opposite to the surface facing... Agent: Rankin, Hill, Porter & Clark LLP

20070102797 - Electrode package for semiconductor device: A plurality of isolated metal layers having the same shapes as electrodes are arranged in a matrix, and molded in a resin plate. The metal layers are exposed from both upper and lower surfaces of the resin plate. A cross-sectional area of each metal layer is increased with depth from... Agent: Reising, Ethington, Barnes, Kisselle, P.C.

20070102796 - Power semiconductor module: A power semiconductor module is presented. The power semiconductor module has a substrate, a composite film, and a power semiconductor component between the substrate and the composite film. The composite film has a thin circuit-structured logic metal layer and a thick circuit-structured power metal layer and between them a thin... Agent: Cohen, Pontani, Lieberman & Pavane

20070102798 - Ic card: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected... Agent: Miles & Stockbridge PC

20070102799 - Ic card: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected... Agent: Miles & Stockbridge PC

20070102803 - Method for making stacked integrated circuits (ics) using prepackaged parts: A method of making a stacked assembly of integrated circuits (ICs) from prepackaged semiconductor chips is disclosed. The method involves the steps of first starting with a commercially available prepackaged semiconductor chip (e.g. a thin small outline package (TSOP)), that contains bare silicon die within an encapsulant and removing at... Agent: Mcdermott Will & Emery LLP

20070102800 - Pad redistribution chip for compactness, method of manufacturing the same, and stacked package using the same: A substrate includes a substrate; a number of pad redistribution chips stacked on the substrate and on one another after being rotated 90° in a predetermined direction relative to one another, the pad redistribution chips having a number of center pads positioned at the center thereof, a number of (+)... Agent: Ladas & Parry LLP

20070102802 - Single chip and stack-type chip semiconductor package and method of manufacturing the same: A semiconductor package comprises a substrate having connection pads disposed thereon, a semiconductor chip attached to the substrate such that an active surface of the semiconductor chip faces the substrate, and external bonding pads electrically connected to the active surface of the semiconductor chip. The external bonding pads may be... Agent: Marger Johnson & Mccollom, P.C.

20070102801 - Stack-type semiconductor device and method of manufacturing the same: A stack-type semiconductor device according to the present invention includes a circuit board with bonding pads; a first semiconductor chip which includes first electrode pads and is mounted on the circuit board; a second semiconductor chip which includes second electrode pads and is mounted on the first semiconductor chip; a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070102805 - Chip type electric device and method, and display device including the same: A chip type electric device and a display device including the same is capable of preventing a bonding defect caused by a deviation in height between external electrodes. The chip type electric device includes a body in which a plurality of dielectric layers is stacked, a contact hole penetrating at... Agent: Cantor Colburn, LLP

20070102804 - Multilayered printed wiring board and manufacturing method thereof: An object of the present invention is to provide a multi-layered printed wiring board which does not require roughening such as black oxide treatment and the like on inner layer circuits. For the purpose of achieving this object, there is adopted a multi-layered printed wiring board characterized by comprising a... Agent: Rothwell, Figg, Ernst & Manbeck, P.C.

20070102806 - Power distribution for high-speed integrated circuits: An improved technique for power distribution for use by high speed integrated circuit devices. A mixture of high dielectric constant, Er and low Er materials are used in a dielectric layer sandwiched between the voltage and ground planes of a printed circuit board that is used to fixture one or... Agent: Brooks Kushman P.C. / Sun / Stk

20070102807 - Coupling substrate for semiconductor components and method for producing the same: A coupling substrate for semiconductor components includes a patterned metal layer on a topside of an insulating carrier. Metal tracks project beyond the insulating carrier, the metal tracks being angled away at the lateral edges of the carrier in the direction of the underside of the carrier and projecting beyond... Agent: Edell, Shapiro & Finnan, LLC

20070102808 - Semiconductor module and radiator plate: A semiconductor module 10 in which respective upper surfaces of semiconductor elements 17, 17 on both sides of a rectangular circuit board 11 are covered with radiator plates 12a, 12b attached to both sides of the circuit board 11 so that their outer peripheral edges are not projected from the... Agent: Rankin, Hill, Porter & Clark LLP

20070102809 - Methods of fabricating a composite carbon nanotube thermal interface device: Embodiments of a composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a matrix comprised of a metal or a metal oxide. The composite carbon nanotube structures may be used as a thermal interface device in a packaged integrated circuit device.... Agent: Blakely Sokoloff Taylor & Zafman

20070102810 - Sensor block: A sensor block that includes a plurality of sensor chips in combination. Each sensor chip includes a semiconductor substrate having a detection unit formed therein, and two glass substrates bonded to both sides of the semiconductor substrate. One of the glass substrates is shared among the sensor chips and serves... Agent: Rankin, Hill, Porter & Clark LLP

20070102811 - Package having an array of embedded capacitors for power delivery and decoupling of high speed input/output circuit and methods of forming thereof: One embodiment of the present invention provides advice for providing a low noise power supply package to an integrated circuit comprising a semiconductor die, input/output power supply terminals, and an array of embedded ceramic capacitors selected from discrete, planar and combinations thereof wherein said capacitors are placed in the locations... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070102812 - Reduction of macro level stresses in copper/low-k wafers by altering aluminum pad/passivation stack to reduce or eliminate imc cracking in post wire bonded dies: A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 μm aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the... Agent: Lsi Logic Corporation

20070102814 - Semiconductor device and method of manufacturing the same: In a method of manufacturing a semiconductor package, a semiconductor chip including a circuit unit that has a first circuit and a second circuit spaced apart from each other, a first conductive member for electrically connecting the first circuit to the second circuit and a cut-out portion for disconnecting the... Agent: Harness, Dickey & Pierce, P.L.C

20070102813 - Semiconductor device, method of manufacturing a semiconductor device and substrate to be used to manufacture a semiconductor device: A semiconductor device comprises a first electrode-lead having a first Au film, a first Ni film, a Cu film, a second Au film and a second Ni film stacked in order, a second electrode-lead having a first Au film, a first Ni film, a Cu film, a second Au film... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070102816 - Board structure, a ball grid array (bga) package and method thereof, and a solder ball and method thereof: A board structure, a ball grid array (BGA) package and method thereof and a solder ball and method thereof. The example solder ball may include a solder portion and a grooved connection portion, formed through a partitioning process, configured to fit a corresponding protruding portion on a board. The example... Agent: Harness, Dickey & Pierce, P.L.C

20070102815 - Bumping process with self-aligned a1-cap and the elimination of 2nd passivation layer: The present invention provides a simplified process end flow for a flip chip device. This process flow, beginning with the deposition of a final metal layer for the IC, also includes the deposition of the UBM layer on top of the metal layer. The UBM layer and IC final metal... Agent: Garlick Harrison & Markison

20070102817 - Method and apparatus for reducing electrical interconnection fatigue: A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric... Agent: Schwabe, Williamson & Wyatt, P.C.

20070102818 - Wiring, tft substrate using the same, manufacturing method of tft substrate, and lcd.: A gate electrode (wiring) (40) having a Cu layer (40a) surrounded by a coating film (40b) made of titanium or titanium oxide; a TFT substrate (31) comprising the gate electrode (wiring) (40) and a LCD comprising a pair of opposing substrates and a liquid crystal disposed between the opposing substrates,... Agent: Morgan Lewis & Bockius LLP

20070102819 - Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement: A method is disclosed for producing an integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement. The invention also relates to a method for producing aligning marks. During the method, a planarization is carried out before material is removed from an auxiliary indentation.... Agent: Brinks Hofer Gilson & Lione

20070102820 - Semiconductor integrated circuit: A semiconductor integrated circuit having a multilayer wiring structure is provided which includes: a top metal wiring layer (MTOP) including a plurality of top layer power supply wirings and a next-to-top metal wiring layer (MTOP-1) directly below the top metal wiring layer MTOP including a plurality of next-to-top layer power... Agent: Oliff & Berridge, PLC

20070102821 - Use of supercritical fluid for low effective dielectric constant metallization: An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions... Agent: Texas Instruments Incorporated

20070102822 - Aluminum base target and process for producing the same: An object of the present invention is to provide an aluminum-based target having a large area which has internal defects such as blow holes reduced to a minimum and has no warp. The aluminum-based target consisting of a plurality of aluminum alloy target members has a joint in which the... Agent: Roberts & Roberts, LLP Attorneys At Law

20070102823 - Semiconductor device, electronic device and electronic apparatus: An semiconductor device (1) of the invention includes a semiconductor substrate provided with a channel region (21), a source region (22) and a drain region (23), a gate insulating film (3) laminated on the channel region (21), and a gate electrode (5). The gate insulating film (3) is formed of... Agent: Harness, Dickey & Pierce, P.L.C

20070102825 - Semiconductor package and method of fabricating same: A semiconductor package of this invention achieves higher wiring densities and increases the degree of freedom of the wiring design. The semiconductor package includes a first substrate having first and second faces, and first wiring provided on the first face of the first substrate. The semiconductor package also includes a... Agent: Rabin & Berdo, PC

20070102824 - Tungsten plug structure of semiconductor device and method for forming the same: A tungsten plug structure of a semiconductor device wherein a method for forming the same is performed at least twice to form a tungsten plug having a low aspect ratio, thereby obtaining an overlap margin between the tungsten plug and a metal line and minimizing contact resistance between the tungsten... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070102826 - Electronic component having at least one semiconductor chip and flip-chip contacts, and method for producing the same: An electronic component has a semiconductor chip and microscopically small flip-chip contacts belonging to a rewiring plate, on which macroscopically large elastic external contacts are arranged. The rewiring plate has a wiring support made of polycrystalline silicon, amorphous glass, or metal. Furthermore, the present invention relates to a method for... Agent: Edell, Shapiro & Finnan, LLC

20070102827 - Solvent assisted burnishing of pre-underfilled solder-bumped wafers for flipchip bonding: The present invention relates to a method for connecting an integrated circuit chip to a circuit substrate. The method includes the step of pre-applying adhesive directly to a bumped side of an integrated circuit chip. The method also includes the steps of removing portions of the adhesive from the tips... Agent: 3m Innovative Properties Company

20070102829 - Chip structure with solder bump and method for producing the same: A chip structure with solder bumps and the method for producing the same are disclosed. The chip structure with solder bumps includes a chip, a plurality of pads arranged on one surface of the chip, a protection layer formed on the surface of the chip and exposing the pads, a... Agent: Lowe Hauptman Berner, LLP

20070102828 - Fine pitch interconnect and method of making: Fine pitch contacts are achieved by using traces that extend to the contacts without requiring capture pads at the contact pads. Capture pads are desirably avoided because they have a diameter greater than the line to which they are attached. Preferably, adjacent contact pads are present in the same opening... Agent: Freescale Semiconductor, Inc. Law Department

20070102830 - Flexible printed circuit board: A flexible printed circuit board has an insulation layer, a first signal wiring layer including a microstrip line, a second signal wiring layer including a signal connection terminal for allowing the microstrip line to connect the exterior connector electrically, and a ground conductive section having a ground connection terminal for... Agent: Robert J. Depke Lewis T. Steadman

20070102831 - Device and method of manufacturing the same: The present invention has a object to enhance the yield and facilitate bonding in a device provided with micro-mechanical elements formed by a MEMS technique. According to the inveniton, when a first wafer having a plurality of areas in which micro-mechanical elements and pads are formed and a second wafer... Agent: Reed Smith LLP

20070102832 - Plastic semiconductor package having improved control of dimensions: A device with a semiconductor chip assembled on a planar substrate and encapsulation compound surrounding the assembled chip and a portion of the substrate near the chip; the compound has a planar top area. The encapsulation compound has a plurality of side areas reaching from the substrate to the top... Agent: Texas Instruments Incorporated

20070102833 - Integrated circuit device: An integrated circuit device having a semiconductor device and an encapsulating material on at least a portion of the semiconductor device and a method for encapsulating an integrated circuit device is disclosed. The encapsulating material includes a plurality of nanoparticles.... Agent: Mh2 Technology Law Group

20070102834 - Strain-compensated metastable compound base heterojunction bipolar transistor: A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si... Agent: Schneck & Schneck

20070096072 - Lateral phase change memory: A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a... Agent: Seed Intellectual Property Law Group PLLC

20070096071 - Multi-terminal phase change devices: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created... Agent: Thelen Reid Brown Raysman & Steiner LLP

20070096073 - Increasing phase change memory column landing margin: A phase change memory with higher column landing margin may be formed. In one approach, the column landing margin may be increased by increasing the height of an electrode. For example, the electrode being made of two disparate materials, one of which includes nitride and the other of which does... Agent: Trop Pruner & Hu, PC

20070096074 - Electrically rewritable non-volatile memory element and method of manufacturing the same: A non-volatile memory element includes a first interlayer insulation layer 11 having a first through-hole 11a, a second interlayer insulation layer 12 having a second through-hole 12a formed on the first interlayer insulation layer 11, a bottom electrode 13 provided in the first through-hole 11, recording layer 15 containing phase... Agent: Mcdermott Will & Emery LLP

20070096075 - Field emission display device and method of operating the same: A field emission device includes a substrate, a first conductive layer formed over the substrate biased at a first voltage level, a second conductive layer formed over the substrate biased at a second voltage level different from the first voltage level, emitters formed on the first conductive layer and the... Agent: Akin Gump Strauss Hauer & Feld LLP One Commerce Square

20070096076 - Light emitting device and method of manufacturing light emitting device: A light emitting device includes: a light emitting layer; an n-type contact layer made of a compound provided on the light emitting layer; a composition modulation layer provided on the n-type contact layer; and a transparent electrode provided on the composition modulation layer. The composition modulation layer consists of a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070096077 - Nitride semiconductor device: A nitride semiconductor device having excellent ESD tolerance, by preventing uneven distribution of the electric current in the p-side nitride semiconductor layer. The p-side nitride semiconductor layer (40) comprises, from the active layer (30) side, (a) a p-side wide band gap layer (12) containing a p-type impurity and (b) a... Agent: Birch Stewart Kolasch & Birch

20070096078 - Organic-inorganic hybrid nanocomposite thin films for high-powered and/or broadband photonic device applications and methods for fabricating the same and photonic device having the thin films: An organic-inorganic hybrid nanocomposite thin film for a high-powered and/or broadband photonic device having an organic ligand-coordinated semiconductor quantum dot layer, a photonic device having the same, and a method of fabricating the same are provided. The organic-inorganic hybrid nanocomposite thin film is composed of a stack structure comprising a... Agent: Ladas & Parry LLP

20070096082 - Crosslinkable arylamine compounds and conjugated oligomers or polymers based thereon: Crosslinkable arylamine compounds; oligomers and polymers prepared from such crosslinkable arylamine compounds; films and coatings; and multilayer electronic devices comprising such films are disclosed.... Agent: Sughrue Mion, PLLC

20070096087 - Effect of the plasmonic dispersion relation on the transmission properties of subwavelength holes: Using a realistic plasmonic model, an optically thick electrically conductive film with subwavelength hole or holes therein is shown to always support propagating modes near the surface plasmon frequency, where cross-sectional dimensions of the hole or holes are less than about λ/2nh, λ being the wavelength of the light and... Agent: Parsons Hsue & De Runtz LLP

20070096079 - Field effect transistor and production process thereof: (R1, R2 and R3 each represent hydrogen atom, halogen atom, hydroxymethyl group, alkyl group having 1 to 12 carbon atoms, alkenyl group, alkinyl group, alkoxyl group, alkylthio group, or alkyl ester group, X1 and X2 each represent hydrogen atom, alkyl group having 1 to 12 carbon atoms, alkenyl group, alkinyl... Agent: Fitzpatrick Cella Harper & Scinto

20070096081 - High-heat-resistant semiconductor device: In a wide gap semiconductor device of SiC or the like used at a temperature of 150 degrees centigrade or higher, the insulation characteristic of a wide gap semiconductor element is improved and a high-voltage resistance is achieved. For these purposes, a synthetic high-molecular compound, with which the outer surface... Agent: Crowell & Moring LLP Intellectual Property Group

20070096086 - Hole injection electrode: There is provided an electrode having a first layer of a metallic material having a work function greater than 4.0 eV and a second layer of an organic material having an electron affinity greater than 4.0 eV. The second layer has a thickness in the range of 0.5 to 5... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070096084 - N-type semiconductor materials for thin film transistors: A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide naphthalene-based compound having, attached to each of the imide nitrogen atoms, an aromatic moiety, at least one of which moieties is substituted with at least one electron donating group. Such transistors can further comprise spaced... Agent: Paul A. Leipold Patent Legal Staff

20070096085 - Organic photovoltaic cells utilizing ultrathin sensitizing layer: A photosensitive device includes a series of organic photoactive layers disposed between two electrodes. Each layer in the series is in direct contact with a next layer in the series. The series is arranged to form at least one donor-acceptor heterojunction, and includes a first organic photoactive layer comprising a... Agent: Kenyon & Kenyon LLP

20070096089 - Organic semiconductor diode: The present invention relates to organic semiconductor diodes, in particular, to the diodes with nonlinear current-voltage characteristics, which are used for power switching, rectifying variable signals, and frequency mixing. The organic semiconductor diode with the p-n junction comprises an anode, cathode, a hole transport layer in contact with the anode,... Agent: Dorsey & Whitney LLP

20070096088 - Organic transistor and display device: An organic transistor including a stacked insulating film in which an insulating layer and a wettability control layer are stacked in order is provided, wherein the wettability control layer includes a material whose surface energy can be changed by irradiation with an ultraviolet ray and a transmittance of the ultraviolet... Agent: Cooper & Dunham, LLP

20070096080 - Rectifying diodes: A rectifying diode comprising a semiconducting layer, a first electrode, and a second electrode, wherein the width of the region of closest contact between the two electrodes is on the order of the thickness of the semiconducting layer.... Agent: Sughrue Mion, PLLC

20070096083 - Substrate core polymer nanocomposite with nanoparticles and randomly oriented nanotubes and method: Embodiments of substrate core polymer nanocomposite with nanoparticles and randomly oriented nanotubes and method for making the substrate core are generally described herein. Other embodiments may be described and claimed. In some embodiments, a nanotube suspension is combined with nanoparticle-impregnated polymer.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070096090 - Forming a phase change memory with an ovonic threshold switch: A phase change memory may include an ovonic threshold switch formed over an ovonic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.... Agent: Trop Pruner & Hu, PC

20070096093 - Calibration technique for measuring gate resistance of power mos gate device at wafer level: This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the... Agent: Bo-in Lin

20070096091 - Layer structure and removing method thereof and mehod of testing semiconductor machine: A method of testing a semiconductor machine is provided. A wafer is provided and a removable auxiliary layer is formed on the wafer. A low dielectric constant dielectric layer with an expected thickness is formed on the removable auxiliary layer. The actual thickness of the low dielectric constant dielectric layer... Agent: Jianq Chyun Intellectual Property Office

20070096094 - Methods and apparatus for designing and using micro-targets in overlay metrology: Methods and apparatus for fabricating a semiconductor die including several target structures. A first layer is formed that includes one or more line or trench structures that extend in a first direction. A second layer is formed that includes one or more line or trench structures that extend in a... Agent: Beyer Weaver & Thomas LLP

20070096092 - Semiconductor device fault detection system and method: An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact... Agent: Slater & Matsil, L.L.P.

20070096095 - Test pattern for semiconductor device and method for measuring pattern shift: There are provided a test pattern for a semiconductor device includes a buried layer formed on a surface of a substrate; a semiconductor layer formed on an entire surface of the substrate; and first and second high-concentration impurity regions formed in the surface of the semiconductor layer and electrically connected... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070096098 - Conductive structure, manufacturing method for conductive structure, element substrate, and manufacturing method for element substrate: A conductive structure includes a laminated structure of an upper layer and a lower layer. The lower layer is formed of an aluminum alloy containing at least one kind of Group 8 elements in periodic table. The upper layer is laminated on the lower layer and formed of an aluminum... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070096099 - Display device, device for driving the display device and method of driving the display device: A display device including a plurality of pixels is disclosed. Each of the pixels includes a switching transistor, a plurality of scanning lines connected to the switching transistors and a plurality of data lines connected to the switching transistors. The scanning lines transmit a gate turn-on voltage that turns on... Agent: H.c. Park & Associates, PLC

20070096096 - Electronic device and semiconductor device and method for manufacturing the same: In the present invention, after forming a base layer 11 (or base pretreatment) which enhances adhesiveness over a substrate in advance and forming an insulating film, a mask having a desired pattern shape is formed, and a desired depression is formed by using the mask. A metal material is filled... Agent: Nixon Peabody, LLP

20070096102 - Liquid crystal display panel: An LCD panel includes a plurality of gate lines and gate electrodes formed on a substrate and a gate insulating film formed on the substrate including the gate lines and the gate electrodes. A semiconductor film is formed in a region on the gate insulating film and an ohmic contact... Agent: Mckenna Long & Aldridge LLP

20070096101 - Method of manufacturing semiconductor light emitting device: A semiconductor light emitting device includes a multi-layered semiconductor layer having at least a first conductive type cladding layer, an active layer, a second conductive type first cladding layer, an etching stop layer, and a second conductive type second cladding layer on a substrate. An upper section of a ridge... Agent: Sonnenschein Nath & Rosenthal LLP

20070096100 - Thin film transistors: A thin film transistor according to an embodiment of the present invention includes: a substrate; a control electrode disposed on the substrate; a gate insulating layer disposed on the control electrode; a semiconductor member disposed on the gate insulating layer, overlapping the control electrode, and including a first portion of... Agent: Macpherson Kwok Chen & Heid LLP

20070096097 - Thin-film transistor, method of manufacturing the same, liquid crystal display panel having the same and electro-luminescence display panel having the same: A TFT includes a gate electrode, an active layer, a source electrode, a drain electrode, and a buffer layer. The gate electrode is formed on the substrate; the active layer is formed on the gate electrode. The source and drain electrodes, formed on the active layer, are separated by a... Agent: Macpherson Kwok Chen & Heid LLP

20070096103 - Semiconductor device, annealing method, annealing apparatus and display apparatus: The semiconductor device according to the present invention has a semiconductor layer having not smaller than two types of crystal grains different in size within a semiconductor circuit on a same substrate.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070096104 - Semiconductor device having a mis-type fet, and methods for manufacturing the same and forming a metal oxide film: [Means for solving Problems] A MIS-type field-effect-transistor (FET) including: a silicon substrate (1); an insulating film (6) formed on the silicon substrate and containing silicon and at least one of nitrogen and oxygen; a metal oxide film formed on the insulating film and containing silicon and hafnium; and a gate... Agent: Foley And Lardner LLP Suite 500

20070096105 - Methods of fabricating a semiconductor device using angled implantation: Methods of fabricating structures, such as memory cell structures by exposing at least one edge portion of an intermediate nitride layer arranged between a polysilicon layer and a tungsten layer and performing an angled implant at the at least one edge portion to form a doped region through the at... Agent: Michael G. Fletcher Fletcher Yoder

20070096106 - Semiconductor display device and method of manufacturing the same: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer... Agent: Nixon Peabody, LLP

20070096108 - Etch stop layer for a metallization layer with enhanced etch selectivity and hermeticity: By providing a barrier layer stack including a silicon nitride layer for confining a copper-based metal region, thereby also effectively avoiding any diffusion of oxygen and moisture into the copper region, and a nitrogen-enriched silicon carbide layer, the total relative permittivity may be maintained at a low level, since the... Agent: Williams, Morgan & Amerson

20070096107 - Semiconductor devices with dielectric layers and methods of fabricating same: A SiC semiconductor device with a SiC layer and an insulating layer is provided. The insulating layer may include glass or ceramic. The thermal expansion coefficient of the insulating layer may be matched to that of SiC to reduce stress at the interface. A method of processing the SiC semiconductor... Agent: Patrick S. Yoder Fletcher Yoder

20070096109 - Semiconductor material, production method thereof and semiconductor device: A semiconductor material having a stepwise surface structure of (0001)-plane terraces and (11-2n)-plane steps [n≧0] on the SiC substrate, a semiconductor device using the same and a method of producing the semiconductor material in which a carbon-rich surface is formed on the SiC substrate prior to epitaxial growth of an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070096112 - Area light emitting device: Provided is an area light emitting device, including: an EL element which is provided with a structure in which a first electrode layer, a thin film layer including a light-emitting layer, and a second electrode layer are stacked on a substrate in a stated order, which has a predetermined area... Agent: Morgan & Finnegan, L.L.P.

20070096113 - Led device: An LED device includes; an LED chip, a first layer provided on the LED chip, a second layer provided on the first layer, and a third layer provided on the second layer. The first layer has a refractive index n1. The second layer has a refractive index n2, and includes... Agent: Ndq&m Watchstone LLP

20070096114 - Light emitting apparatus: A light emitting apparatus which has a high output power and does not experience a decrease in the emission output power is provided. The light emitting apparatus comprises a light emitting element which has one of main surfaces thereof being used as a light emitting surface and a plurality of... Agent: Birch Stewart Kolasch & Birch

20070096111 - Light emitting display: The present disclosure provides a light emitting display device including a first substrate and a second substrate and a light emitting part disposed therebetween. The first substrate includes an active layer, source and drain electrodes, an insulating layer, and a gate electrode. The active layer is doped with first dopant... Agent: Brinks Hofer Gilson & Lione

20070096117 - Nitride semiconductor wafer: A nitride semiconductor substrate having properties preferable for the manufacture of various nitride semiconductor devices is made available, by specifying or controlling the local variation in the off-axis angle of the principal surface of the nitride semiconductor substrate. In a nitride semiconductor single-crystal wafer having a flat principal surface, the... Agent: Judge & MurakamiIPAssociates

20070096115 - Nitride-based semiconductor light emitting diode: A nitride-based semiconductor LED comprises a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer formed on a predetermined region of the n-type nitride semiconductor layer; a p-type nitride semiconductor layer formed on the active layer; a current spreading layer formed on the p-type nitride semiconductor... Agent: Mcdermott Will & Emery LLP

20070096110 - Semiconductor light emitting device and apparatus: A semiconductor light emitting device comprises: a semiconductor laminated body including a light emitting layer and having a light extraction surface for light emitted from the light emitting layer, a conductive film provided on the light extraction surface of the semiconductor laminated body and being translucent to the light emitted... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070096116 - Semiconductor light emitting device and method of manufacturing same and semiconductor light emitting apparatus: A semiconductor light emitting device comprises: a semiconductor laminated body; an electrode provided on the first major surface of the semiconductor laminated body; and a reflecting layer provided on the second major surface side of the semiconductor laminated body. The semiconductor laminated body includes a light emitting layer and having... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070096119 - Electrode structure and optical semiconductor element: An electrode structure includes a first conductive layer, an insulation layer that covers at least a portion of a marginal area of an upper surface of the first conductive layer and has a first sloped section that slopes down toward the upper surface of the first conductive layer, a first... Agent: Harness, Dickey & Pierce, P.L.C

20070096118 - Synthetic jet cooling system for led module: An LED assembly is provided herein. The assembly comprises a thermally conductive housing (201), wherein a portion of said housing is equipped with a plurality of fins (203); an LED (205) disposed in said housing; and a synthetic jet actuator (207) adapted to direct a synthetic jet onto said portion... Agent: Fortkort Grether & Kelton LLP

20070096120 - Lateral current gan flip chip led with shaped transparent substrate: An LED device (90) includes: an epitaxial structure (100) having a plurality of layers of semiconductor material and forming an active light-generating region (120) which generates light in response to electrical power being supplied to the LED device (90); and, a substrate (200) that is substantially transparent in a wavelength... Agent: Scott A. Mccollister, Esq. Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070096121 - Light emitting diode and method for manufacturing the same: A light emitting diode and a method for manufacturing the same are provided. The light emitting diode includes: a transparent substrate made of AlxGa1-xAs; a light emitting layer made of AlGaInP, stacked on the transparent substrate, and having a multiple layered epitaxially growing structure; a window layer made of GaP,... Agent: Lin & Associates Intellectual Property

20070096123 - Nitride semiconductor light-emitting element and manufacturing method thereof: A nitride semiconductor light-emitting element, including a first-conductivity-type nitride semiconductor layer, an active layer, and a second-conductivity-type nitride semiconductor layer successively stacked on a substrate, in which a light extraction surface located above the second-conductivity-type nitride semiconductor layer has a conical or pyramidal projecting portion, as well as a method... Agent: Morrison & Foerster LLP

20070096122 - Surface-emitting type semiconductor laser and method for manufacturing the same: A surface-emitting type semiconductor laser includes: an upper mirror and a lower mirror each composed of alternately formed first semiconductor layers and second semiconductor layers; an active layer disposed between the upper mirror and the lower mirror, wherein the surface-emitting laser emits laser light in a direction in which the... Agent: Harness, Dickey & Pierce, P.L.C

20070096124 - Array substrate for a display panel, method of manufacturing the same, display panel having the same and liquid crystal display device having the same: An array substrate for a display panel includes a base substrate, a signal-applying module, a first electrode, a second electrode, and a protective layer. The signal-applying module is disposed on the base substrate and includes an output terminal to output a data signal. The first electrode is disposed on the... Agent: Macpherson Kwok Chen & Heid LLP

20070096125 - Illumination device: An illumination device has a plurality of main illumination areas subdivided into at least a first and a second sub-illumination area, wherein a luminous element for outputting radiation is arranged on each sub-illumination area, and wherein a beam deflection unit is associated with each main illumination area, which is designed... Agent: Gardner Groff Santos & Greenwald, P.C.

20070096126 - Gallium nitride-based compound semiconductor light-emitting device and negative electrode thereof: An object of the present invention is to provide a negative electrode which attains excellent Ohmic contact with an n-type gallium nitride-based compound semiconductor layer, which resists deterioration in characteristics which would be caused by heating, and which can be produced at high efficiency. Another object of the invention is... Agent: Sughrue Mion, PLLC

20070096130 - Led assembly having maximum metal support for laser lift-off of growth substrate: Described is a process for forming an LED structure using a laser lift-off process to remove the growth substrate (e.g., sapphire) after the LED die is bonded to a submount. The underside of the LED die has formed on it anode and cathode electrodes that are substantially in the same... Agent: Patent Law Group LLP

20070096129 - Light emitting diode package and method of manufacturing the same: A light emitting diode (LED) package is provided. The LED package includes a printed circuit board (PCB), an electrode pad, an LED, a wire, and first and second moldings. The electrode pad and the LED are formed on the PCB. The wire electrically connects the LED with the electrode pad.... Agent: Birch Stewart Kolasch & Birch

20070096127 - Semiconductor micro-cavity light emitting diode: A spontaneously light emitting nitride-based active region placed within a micro-cavity bounded by a first mirror and a second mirror, wherein the micro-cavity has been thinned to a resonant thickness within a micro-cavity regime.... Agent: Gates & Cooper LLP Howard Hughes Center

20070096128 - Wavelength converter, lighting system, and lighting system assembly: In a wavelength converter converting a wavelength of light emitted from a light source and outputting an output light containing light whose wavelength is converted, which comprises a fluorescent substance dispersed in a transparent matrix, the fluorescent substance has semiconductor fine particles containing at least one univalent metal element selected... Agent: Hogan & Hartson L.L.P.

20070096136 - Cladding layer structure of a led package structure: A cladding layer structure of a LED (light emitting diode) package structure comprises a printed circuit layer arranged on a substrate, a cladding layer having a through hole is located on the printed circuit layer, a chip is received in the through hole and is in electrical contact with the... Agent: Charles E. Baxley, Esq.

20070096132 - Coaxial led lighting board: A lighting board is fabricated with. the use of coaxial light device inserted in a socket plate, the convenience of assembly and disassembly of the coaxial light device with its coaxial lead makes the product easily to be maintained for changing different color of the coaxial light device, changing different... Agent: Lowe Hauptman Berner, LLP

20070096135 - Display panel: A drive current line which supplies power to an EL element includes a branch line which is provided in a display region and a trunk line having a larger cross sectional area than the branch line and which is provided along two or more sides of a peripheral portion of... Agent: Cantor Colburn, LLP

20070096131 - Laminating encapsulant film containing phosphor over leds: A process is described for wavelength conversion of LED light using phosphors. LED dies are tested for correlated color temperature (CCT), and binned according to their color emission. The LEDs in a single bin are mounted on a single submount to form an array of LEDs. Various thin sheets of... Agent: Patent Law Group LLP

20070096134 - Light emitting diode fixture and heat sink: A housing for a plurality of light emitting diodes includes a housing providing a heat sink, where the heat sink includes a plurality of protrusions. A control board can be removably coupled to the heat sink and the control board can provide an aperture to receive a lens housing and... Agent: Akerman Senterfitt

20070096137 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device includes: a semiconductor element; a wiring board including a connection terminal to be electrically connected to the semiconductor element; and a metal plate disposed between the semiconductor element and the wiring board; wherein the metal plate is provided with an opening for exposing the connection terminal to... Agent: Rader Fishman & Grauer PLLC

20070096138 - Semiconductor laser device and fabrication method thereof: A semiconductor laser device aimed to be reduced in size and that can maintain high position accuracy, and a fabrication method of such a semiconductor laser device are achieved. A semiconductor laser device includes a stem as a base member, and a cap member. The stem includes a main unit... Agent: Nixon & Vanderhye, PC

20070096133 - System and method for led manufacturing: An LED is formed using terminal leads that are rolled instead of die-set formed. Using this process, the terminal leads can end in several terminals thereby allowing higher heat dissipation. The LED can be produced using an LED chip that has light coming only from the top or with light... Agent: Avago Technologies, Ltd.

20070096139 - Light emitting diode encapsulation shape control: A semiconductor optical device is encapsulated by disposing the semiconductor optical device in a cavity defined by a cavity wall. The cavity wall is coated with a coating material having a first surface energy. An encapsulant having a second surface energy is introduced into the cavity adjacent to the light... Agent: 3m Innovative Properties Company

20070096140 - Sealing structure for a white light led: A sealing structure for a white light LED comprises a printed circuit layer located on a base, a cladding layer having a through hole is arranged on the printed circuit layer. A chip is received in the through hole and is electrically connected to the printed circuit layer by a... Agent: Charles E. Baxley, Esq.

20070096141 - Light source structure: A light source structure (100) for providing backlights to an LCD panel is provided. The light source structure includes a cathode layer (10), a semiconductor layer (20) disposed on the cathode layer, for emitting electrons when applied with electric field, a dielectric layer (30), disposed on the semiconductor layer a... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070096143 - Nitride semiconductor light emitting device and method for manufacturing the same: The invention relates to a nitride semiconductor light emitting device having a high light emission efficiency, low operating voltage and high resistance to electrostatic discharge. The nitride semiconductor light emitting device includes an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer formed in their order... Agent: Mcdermott Will & Emery LLP

20070096142 - Semiconductor device: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070096144 - Integrated circuit using complementary junction field effect transistor and mos transistor in silicon and silicon alloys: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The... Agent: Ronald Craig Flsh, A Law Corporation

20070096145 - Switching semiconductor devices and fabrication process: A switching semiconductor device is provided, in which a negative gate voltage can be applied to the semiconductor device in an OFF state so as to increase a breakdown voltage of the gate junction without impairing a normally-off function of the semiconductor device and the ON-resistance. The switching semiconductor device... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070096146 - Iii-v power field effect transistors: A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured... Agent: Agere Lerner, David Et Al.

20070096147 - Nitride-based semiconductor substrate and method of making the same: A nitride-based semiconductor substrate having a diameter of 25 mm or more, a thickness of 250 micrometers or more, and an optical absorption coefficient of less than 7 cm−1 to light with a wavelength of 380 nm or more. The nitride-based semiconductor substrate is made by the HVPE method that... Agent: Mcginn Intellectual Property Law Group, PLLC

20070096148 - Embedded strain layer in thin soi transistors and a method of forming the same: By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.C.

20070096149 - Implant damage control by in-situ c doping during sige epitaxy for device applications: Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain... Agent: William Stoffel<