Active solid-state devices (e.g., transistors, solid-state diodes) inventions 03/07

20070069192 - Thermal switching element and method for manufacturing the same: The present invention provides a thermal switching element that has a quite different configuration from that of a conventional technique and can control heat transfer by the application of energy, and a method for manufacturing the thermal switching element. The thermal switching element includes a first electrode, a second electrode,... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070069193 - Metal-insulator transition switching transistor and method for manufacturing the same: Provided is a metal-insulator-transition switching transistor with a gate electrode on a silicon substrate (back-gate structure) and a metal-insulator-transition channel layer of VO2 that changes from an insulator phase to a metal phase, or vice versa, depending on a variation of an electric field, and a method for manufacturing the... Agent: Ladas & Parry LLP

20070069194 - Fabrication of nanowires: This disclosure relates to a system and method for creating nanowires. A nanowire can be created by exposing layers of material in a superlattice and dissolving and transferring material from edges of the exposed layers onto a substrate. The nanowire can also be created by exposing layers of material in... Agent: Hewlett Packard Company

20070069195 - Silicon germanium semiconductive alloy and method of fabricating same: A silicon germanium (SiGe) semiconductive alloy is grown on a substrate of single crystalline Al2O3. A {111} crystal plane of a cubic diamond structure SiGe is grown on the substrate's {0001} C-plane such that a <110> orientation of the cubic diamond structure SiGe is aligned with a <1,0,−1,0> orientation of... Agent: National Aeronautics And Space Administration Langley Research Center

20070069196 - Epitaxial wafer for led and light emitting diode: An epitaxial wafer for a light emitting diode has: a light-emitting portion having a n-type cladding layer, a p-type cladding layer and an active layer formed between the n-type cladding layer and the p-type cladding layer, the light-emitting portion being formed on a n-type substrate; and a p-type GaP current... Agent: Mcginn Intellectual Property Law Group, PLLC

20070069206 - Flat panel display device having an organic thin film transistor and method of manufacturing the same: Provided are an organic TFT that reduces contact resistance between a source and drain electrode and an organic semiconductor layer and that can be easily manufactured, a flat panel display device having the organic TFT, and methods of manufacturing the organic TFT and the flat panel display device having the... Agent: Knobbe Martens Olson & Bear LLP

20070069199 - Interface conditioning to improve efficiency and lifetime of organic electroluminescence devices: In at least one embodiment of the invention, an OLED device is disclosed in which the surface of one or more layers of the OLED are conditioned with metal nano-particles such that they are disposed along the interface between adjacent layers.... Agent: Fish & Richardson P.C.

20070069202 - Light-emitting device comprising semiconductor nanocrystal layer free of voids and method for producing the same: A light-emitting device including a semiconductor nanocrystal layer and a method for producing the light-emitting device are provided. The light-emitting device includes a semiconductor nanocrystal layer whose voids are filled with a filling material. According to the light-emitting device, since voids formed between nanocrystal particles of the semiconductor nanocrystal layer... Agent: Cantor Colburn, LLP

20070069204 - Liquid crystal display panel and method of fabricating the same: An LCD panel includes a first substrate including a first substrate material, a plurality of thin film transistors (“TFTs”) formed on the first substrate material each having a drain electrode, and an organic layer formed on the plurality of TFTs which further includes a color filter layer, a second substrate... Agent: Cantor Colburn, LLP

20070069197 - Monomers, oligomers and polymers of 2-functionalized and 2,7-difunctionalized carbzoles: The present invention relates to 2-functionalized and 2,7-difunctionalized carbazoles and 2,7-carbazolenevinylene oligomers and polymers. More specifically, the present invention relates to a compound of Formula (I): wherein R1 is selected from the group consisting of H, alkyl, and aryl; and wherein R2 and R3 are independently selected from the group... Agent: Fulbright & Jaworski L.L.P.

20070069200 - Oled separating structures: Techniques are described for forming a separating structure on an OLED device that is free from deformation. The separating structure prevents adjacent electrodes from contacting one another.... Agent: Fish & Richardson P.C.

20070069201 - Organic bistable device and method for manufacturing the same: An organic bistable device includes a first electrode, a second electrode, and an organic mixture layer, wherein the organic mixture layer is located between the first electrode and the second electrode. While a bias is applied between the first electrode and the second electrode of the bistable device, the doped... Agent: Jianq Chyun Intellectual Property Office

20070069205 - Organic electroluminescent display device: The invention prevents a photocurrent due to external light and a variation in characteristics of transistors or a failure by a short circuit due to the influence of a back channel. A light shield film made of a nonconductive material is formed on an insulation substrate. A back gate insulation... Agent: Morrison & Foerster LLP

20070069203 - Pyrene derivatives and organic electronic device using pyrene derivatives: The present invention provides an organic electronic device using the compound of the formula (1) and a pyrene derivative having a new structure.... Agent: Mckenna Long & Aldridge LLP

20070069198 - Synthesis of phenyl-substituted fluoranthenes by a diesel-alder reaction and the use thereof: with the proviso that R1, R2, R3 and X are not at the same time phenyl when R4 and R5 are hydrogen. Furthermore, the invention relates to a process for preparing them and the use of fluoranthene derivatives as emitter molecule in organic light-emitting diodes (OLEDs), a light-emitting layer comprising... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070069208 - Lsi design support apparatus and lsi design support method: An LSI design support apparatus includes a data acquisition section and an equal processing section. The data acquisition section acquires first position data concerning positions of a plurality of first electrodes provided along a side of a first substrate, and second position data concerning positions of a plurality of second... Agent: Young & Thompson

20070069207 - Method and system of trace pull test: The present invention provides an efficient test method and system for testing the IC package, such as BGA types of packages. With the present invention, manufacturer can have an easier way in testing various types of packages, including newer types. Manufacturer also can get the testing outcome which is more... Agent: Kusner & Jaffe Highland Place Suite 310

20070069209 - Transparent thin film transistor (tft) and its method of manufacture: A transparent thin film transistor (TFT) and a method of fabricating the same are provided. The transparent TFT includes transparent source and drain electrodes formed of transparent material, a transparent semiconductor activation layer that contacts the source and drain electrodes, that is formed of transparent semiconductor, and in which source... Agent: Robert E. Bushnell

20070069211 - Display apparatus and manufacturing method thereof: According to an aspect of the present invention, there is provided a display apparatus including a TFT array substrate on which TFTs are formed in an array, a counter substrate disposed so as to face the TFT array substrate, and a sealing pattern for adhering the TFT array substrate and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070069212 - Flat panel display and method for manufacturing the same: The present invention relates to a flat panel display having high picture quality, high flexibility and high flex-resistance. Specifically, the present invention provides a flat panel display having a plurality of pixels arranged in a matrix shape on a substrate, each of the plurality of pixels comprising a thin film... Agent: Greenblum & Bernstein, P.L.C

20070069210 - Liquid crystal display device and method for manufacturing the same: As a substrate gets larger, time of manufacture is increased due to the repetition of film formations and etchings; waste disposal costs of etchant and the like are increased; and material efficiency is significantly reduced. A base film for improving adhesion between a substrate and a material layer formed by... Agent: Nixon Peabody, LLP

20070069213 - Flexible adjustment of on-die termination values in semiconductor device: A termination value for a pin of a semiconductor device is set to a first value if a pin signal has a first logic state at an edge of a control signal, and to a second value if the pin signal has a second logic state at the edge of... Agent: Law Office Of Monica H Choi

20070069215 - Array substrate of liquid crystal display device and method of fabricating the same: An array substrate of a liquid crystal display device includes a substrate, a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel area, a common line parallel to the gate line, a common electrode extending from... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070069214 - Liquid crystal display and method of driving the same: A liquid crystal display with reduced power consumption and a method of driving the same, in which a liquid crystal display includes a liquid crystal panel including a lower substrate and an upper substrate. The lower substrate has a display region with liquid crystal cells formed at intersections of a... Agent: F. Chau & Associates, LLC

20070069217 - P-i-n diode crystallized adjacent to a silicide in series with a dielectric anitfuse: A method is described for forming a nonvolatile one-time-programmable memory cell having reduced programming voltage. A contiguous p-i-n diode is paired with a dielectric rupture antifuse formed of a high-dielectric-constant material, having a dielectric constant greater than about 8. In preferred embodiments, the high-dielectric-constant material is formed by atomic layer... Agent: Vierra Magen/sandisk Corporation

20070069216 - Substrate for compound semiconductor device and compound semiconductor device using the same: A substrate for compound semiconductor device and a compound semiconductor device using the substrate are provided which allow a breakdown voltage to be high, cause little energy loss, and are suitably used for a high-electron mobility transistor etc. An n-type 3C—SiC single crystal buffer layer 3 having a carrier concentration... Agent: Foley And Lardner LLP Suite 500

20070069220 - Composite semiconductor light-emitting device: A composite semiconductor light-emitting device includes a first semiconductor element portion made of a first semiconductor material and a second semiconductor element portion made of a second semiconductor material different from the first semiconductor material. The first semiconductor element portion has a first semiconductor layered structure, and the second semiconductor... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070069219 - Light emitting device: A light emitting device is proposed, which emits light while connected to the power. The light emitting device includes a light emitting element having at least two electrodes disposed at the side of the light output surface thereof; and a base member having a recess and lead portions corresponding to... Agent: Birch Stewart Kolasch & Birch

20070069218 - Light-emitting diode chip: A light-emitting diode chip (LED chip) including a substrate, an electrostatic conducting layer, a first type doped semiconductor layer, an active layer, a second type doped semiconductor layer, a first electrode and a second electrode is provided. The electrostatic conducting layer is disposed on the substrate, while the first type... Agent: Jianq Chyun Intellectual Property Office

20070069221 - Semiconductor laser diode and method of fabricating the same: A semiconductor laser diode capable of further improving temperature characteristics while sufficiently preventing a laser beam emission end surface portion from thermal destruction through a window structure is obtained. This semiconductor laser diode comprises an active layer having a window structure on a laser beam emission end surface portion and... Agent: Ndq&m Watchstone LLP

20070069222 - Gallium nitride based semiconductor light emitting diode and method of manufacturing the same: A GaN based LED and a method of manufacturing the same are provided. The GaN based semiconductor LED can have an improved heat dissipation capability of a sapphire substrate, thereby preventing device characteristic from being degraded by heat and improving the luminous efficiency of the device. In the GaN based... Agent: Mcdermott Will & Emery LLP

20070069223 - Light emitting diode element and driving method thereof: A light emitting diode (LED) element includes a substrate, a first light emitting unit, a second light emitting unit, a first electrode couple and a second electrode couple. The first light emitting unit is disposed on the substrate. The second light emitting unit is disposed on the first light emitting... Agent: Jianq Chyun Intellectual Property Office

20070069224 - Light-emitting device, production method thereof, and electronic apparatus: In a light-emitting device in which light-emitting elements that emit light having the same color are arrayed in a matrix on a pixel-forming surface of a substrate and the light emitted from the light-emitting elements is emitted from a surface of the substrate opposite to the pixel-forming surface, the light-emitting... Agent: Oliff & Berridge, PLC

20070069226 - Fabrication method of nitride semiconductor light emitting device and nitride semiconductor light emitting device thereby: A method for fabricating a nitride semiconductor light emitting device, and a nitride semiconductor light emitting device fabricated thereby are provided. The method includes: forming a first conductive nitride semiconductor layer on a substrate; forming an active layer on the first conductive nitride semiconductor layer; forming a second conductive nitride... Agent: Birch Stewart Kolasch & Birch

20070069225 - Iii-v light emitting device: A semiconductor structure includes an n-type region, a p-type region, and a III-nitride light emitting layer disposed between the n-type region and the p-type region. The III-nitride light emitting layer has a lattice constant greater than 3.19 Å. Such a semiconductor structure may be grown on a substrate including a... Agent: Patent Law Group LLP

20070069228 - Edge-emitting led assembly: A light-emitting diode (LED) in accordance with the invention includes an edge-emitting LED stack having an external emitting surface from which light is emitted, and a reflective element that is located adjacent to at least one external surface of the LED stack other than the external emitting surface. The reflective... Agent: Avago Technologies, Ltd.

20070069227 - Housing for a radiation-emitting component, method for the production thereof, and radiation-emitting component: The invention relates to a housing for at least two radiation-emitting components, especially LEDs, comprising a system carrier (1) and a reflector arrangement (2) arranged on said system carrier (1). Said reflector arrangement comprises a number of reflectors that are respectively used to receive at least one radiation-emitting component and... Agent: Fish & Richardson PC

20070069230 - Light-emitting diode and light source device having same: A light-emitting diode (10) includes a light-emitting chip (12) and a light-permeable cover (16) arranged over the light-emitting chip. The cover has a central convex portion (162) and a peripheral portion (164) surrounding the convex portion. The convex portion is positioned above the light-emitting chip. The peripheral portion has an... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070069229 - Photodetector with charge-carrier reflector: A photodetector includes a charge carrier collector and a charge carrier concentrator that redirects onto the collector charge carriers that are not initially headed towards the collector.... Agent: Koppel, Patrick & Heybl

20070069232 - Semiconductor device with a resin-sealed optical semiconductor element: To provide a semiconductor device 10, which is thin, compact, and excellent in mechanical strength and humidity resistance. Semiconductor device 10A has a configuration such that in semiconductor device 10A, wherein an optical semiconductor element 14, having a light receiving part or a light emitting part, is sealed in a... Agent: Fish & Richardson P.C.

20070069231 - Semiconductor light-emitting device and method: A semiconductor light-emitting device can include a submount on which a semiconductor light-emitting element is mounted. The device can have a high light utilization efficiency with high reliability and can achieve a reduction in manufacturing cost as well as a decrease in size. The submount can have a reverse trapezoidal... Agent: Cermak & Kenealy, LLP

20070069233 - Multilayer device and method of making: The invention relates to composite articles comprising a substrate and additional layers on the substrate. According to one example, the layers are selected so that the difference in the coefficient of thermal expansion (CTE) between the substrate and a first layer on one side of the substrate is substantially equal... Agent: General Electric Company Global Research

20070069234 - Nitride semiconductor device: A nitride semiconductor device is provided. In the device, first and second conductivity type nitride layers are formed. An active layer is formed between the first and second conductivity type nitride layers. The active layer includes at least one quantum barrier layer and at least one quantum well layer. Also,... Agent: Mcdermott Will & Emery LLP

20070069235 - Light-emitting element: A light-emitting element (1) includes a light-emitting layer (2) including a phosphor, and at least two electrodes (6, 7). The light-emitting element (1) includes at least two kinds of electrically insulating layers (2, 9) with different dielectric constants. One of the electrically insulating layers (2, 9) is the light-emitting layer... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070069236 - Control circuit and method for driving a half-bridge circuit: A method is disclosed for controlling a first transistor in a half-bridge circuit which also includes a second transistor. The transistors can be controlled by applying drive voltages to their gates. During a switch-off operation of the second transistor, the amplitude of the drive voltage of the second transistor is... Agent: Maginot, Moore & Beck Chase Tower

20070069237 - Systems for providing electrostatic discharge protection: Systems for providing electrostatic discharge (ESD) protection. One of the Systems has a plurality of first-type thin film diode elements coupled to each other in series, and a plurality of second-type thin film diode elements coupled to each other in series. The first-type thin film elements are electrically connected to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070069238 - Solid-state image pickup device and method for producing the same: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation... Agent: Robert J. Depke Lewis T. Steadman

20070069239 - Electronic device containing group-iii elements based nitride semiconductors: An electronic device includes a substrate; a single-crystalline first buffer layer, disposed on the substrate, containing a semiconductor represented by the formula AlxGa1-xN; a non-single-crystalline second buffer layer, disposed on the first buffer layer, containing a semiconductor represented by the formula AlyGa1-yN; and an undoped base layer, disposed on the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070069240 - Iii-v compound semiconductor heterostructure mosfet device: A III-V based, implant free MOS heterostructure field-effect transistor device comprises a gate insulator layer overlying a compound semiconductor substrate; ohmic contacts coupled to the compound semiconductor substrate proximate opposite sides of an active device region defined within the compound semiconductor substrate; and a gate metal contact electrode formed on... Agent: Freescale Semiconductor, Inc. Law Department

20070069241 - Memory with high dielectric constant antifuses and method for using at low voltage: A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using antifuse materials having higher dielectric constant and higher acceleration factor than silicon dioxide, and by using diodes having lower band gaps than silicon. Such memory arrays can... Agent: Matrix Semiconductor, Inc.

20070069242 - Semiconductor chip and semiconductor device, and method for manufacturing semiconductor device: A semiconductor chip is provided comprising a semiconductor substrate on which an integrated circuit is formed. The semiconductor chip, which is provided on the semiconductor substrate in an area array, further comprises a plurality of electrodes electrically coupled with the inside of the semiconductor substrate, wherein the electrodes are arranged... Agent: Harness, Dickey & Pierce, P.L.C

20070069243 - Forming closely spaced electrodes: The present invention provides an apparatus and a method of fabricating the apparatus. The apparatus comprises a substrate having a planar surface and first and second electrodes located on the planar surface. The first electrode has a top surface and a lateral surface, and the lateral surface has an edge... Agent: Hitt Gaines, PC Lucent Technologies Inc.

20070069244 - Transistor including paramagnetic impurities and having anti-parallel ferromagnetic contacts: A transistor device may comprise a source having a first ferromagnetic contact thereto, a drain having a second ferromagnetic contact thereto, an electrically conductive gate positioned over a channel region separating the source and the drain, and an electrically insulating layer disposed between the gate and the channel region. The... Agent: Barnes & Thornburg LLP

20070069245 - Protective plate for a plasma display and a method for producing the same: A protective plate for a plasma display comprises conductive substrate for protecting a plasma display and an electrode in electrical contact with the conductive substrate.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070069247 - Electro-optic displays, and components for use therein: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes... Agent: David J Cole E Ink Corporation

20070069246 - Hybrid devices: Hybrid devices, such as optically erasable memory cells and light sensors, and related methods are disclosed. In some embodiments, a device includes a structure capable of converting between a first resistance state and a second resistance state, and a light source configured to convert the structure from the first resistance... Agent: William J. Uhl

20070069248 - Solid-state image pickup device: Provided is a solid-state image pickup device which comprises well contacts and well wirings for supplying a reference voltage to a well and can suppress a reduction in an amount of light received even when a pixel area is decreased. As a well wiring, used is a well main-wiring 4... Agent: Mcdermott Will & Emery LLP

20070069249 - Phase change memory device and method of manufacturing the device: The invention provides a novel structure of a phase change memory device. In the phase change memory device of the invention, an electrode acting as a radiating fin does not exit immediately above a phase change area of a phase change layer (115). A heater electrode (111) and landing electrode... Agent: Mcdermott Will & Emery LLP

20070069250 - Integrated circuit with depletion mode jfet: An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device... Agent: Docket Administrator Agere Systems Inc.

20070069251 - Touch panel: A touch panel including a substrate body having a wave plate, a first elastic layer and a first substrate, a second substrate facing to the substrate body, a first conductive layer, a second conductive layer, a second elastic layer and a polarizing plate. A first conductive layer is formed at... Agent: Ratnerprestia

20070069252 - Insulated gate semiconductor device having a clamping element to clamp gate-emitter voltage and method of manufacturing thereof: The gate of an IGBT is connected to a gate terminal. One end of a clamping element is connected to an anode terminal. A voltage higher than a clamping voltage is applied between the gate and the emitter, to thereby test the dielectric breakdown voltage of a gate insulating film... Agent: Mcdermott Will & Emery LLP

20070069253 - Epitaxial substrate for field effect transistor: An epitaxial crystal for a field effect transistor which has a nitride-based III-V group semiconductor epitaxial crystal grown on a SiC single crystal base substrate having micropipes by use of an epitaxial growth method, wherein at least a part of the micropipes spreading from the SiC single crystal base substrate... Agent: Birch Stewart Kolasch & Birch

20070069255 - Mos transistors having optimized channel plane orientation, semiconductor devices including the same, and methods of fabricating the same: MOS transistors having an optimized channel plane orientation are provided. The MOS transistors include a semiconductor substrate having a main surface of a (100) plane. An isolation layer is provided in a predetermined region of the semiconductor substrate to define an active region. A source region and a drain region... Agent: Marger Johnson & Mccollom, P.C.

20070069254 - Multiple-gate mos transistor using si substrate and method of manufacturing the same: Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an... Agent: Ladas & Parry LLP

20070069257 - Power semiconductor component having a field electrode and method for producing this component: A power semiconductor component includes a semiconductor body and a field electrode. The semiconductor body has a drift zone of a first conduction type and a further component defining a junction therebetween. The junction is configured to cause a space charge zone to propagate when a reverse voltage is applied... Agent: Maginot, Moore & Beck Chase Tower

20070069256 - Semiconductor device comprising at least one mos transistor having an etch stop layer, and corresponding fabrication process: A semiconductor device includes at least one MOS transistor, each transistor being provided with a source region and a drain region formed in a semiconductor substrate, along with a gate region and spacers. The transistor is covered with a unitary etch stop layer that includes at least a first zone... Agent: Jenkens & Gilchrist, PC

20070069258 - Pixel having two semiconductor layers, image sensor including the pixel, and image processing system including the image sensor: An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor. The bottom patterned semiconductor layer contains transistors for detecting, resetting, amplifying and transmitting signals charges received from the photoelectric elements. The top and bottom... Agent: F. Chau & Associates, LLC

20070069259 - Cmos image sensor and method of manufacturing the same: A CMOS image sensor, and method for manufacturing the same is provided. The CMOS image sensor includes a device isolation film formed in a device isolation region of a semiconductor substrate to define an active region and a device isolation region, a gate insulation film formed on the semiconductor substrate.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070069261 - Cmos image sensor and a method for manufacturing the same: A CIS and a method for manufacturing the same are provided. The CIS includes a photodiode formed on a substrate; an interlayer insulation layer formed on an entire surface of the substrate including the photodiode; a color filter layer formed on the interlayer insulation layer to pass light in a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070069262 - Multi-layer interconnect with isolation layer: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation... Agent: Knobbe Martens Olson & Bear LLP

20070069260 - Photodetector structure for improved collection efficiency: An image sensor with an image area having a plurality of photodetectors of a first conductivity type includes a substrate of the second conductivity type; a first layer of the first conductivity type substantially spanning an area of each photodetector; wherein the first layer abuts each photodetector and is between... Agent: Pamela R. Crocker Patent Legal Staff

20070069263 - Electric switch and memory device using the same: An electric switch includes a ferroelectric substrate to which metal is added, a pair of electrodes provided on the ferroelectric substrate, and an electric field applying portion for changing the direction of polarization in part of the ferroelectric substrate.... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070069264 - Ferroelectric varactors suitable for capacitive shunt switching and wireless sensing: A ferroelectric varactor suitable for capacitive shunt switching is disclosed. High resistivity silicon with a SiO2 layer and a patterned metallic layer deposited on top is used as the substrate. A ferroelectric thin-film layer deposited on the substrate is used for the implementation of the varactor. A top metal electrode... Agent: Dinsmore & Shohl LLP

20070069266 - Memory device: Conventionally, the layer of the insulator between a cathode and an anode is formed by a droplet discharge method, vapor deposition, or the like separately from an interlayer insulating film formed over a thin film transistor, which creates problems of increase in cost and the number of manufacturing steps. A... Agent: Eric Robinson

20070069265 - Recess transistor (tr) gate to obtain large self-aligned contact (sac) open margin: A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the... Agent: Lee & Morse, P.C.

20070069268 - Recessed gate transistor structure and method of forming the same: Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance... Agent: Marger Johnson & Mccollom, P.C.

20070069267 - Semiconductor device and manufacturing method thereof: A semiconductor device comprises static random access memory (SRAM) cells formed in a semiconductor substrate, first deep trenches isolating each boundary of an n-well and a p-well of the SRAM cells, second deep trenches isolating the SRAM cells into each unit bit cell, and at least one or more contacts... Agent: Foley And Lardner LLP Suite 500

20070069269 - Stacked capacitor and method of fabricating same: The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor... Agent: Texas Instruments Incorporated

20070069270 - Top electrode in a strongly oxidizing environment: An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in... Agent: Knobbe Martens Olson & Bear LLP

20070069271 - Methods for manufacturing capacitors for semiconductor devices: Capacitors for semiconductor devices and methods of fabricating such capacitors are provided The disclosed capacitor comprises an interlayer dielectric layer (ILD) pattern having an opening exposing a portion of the underlying semiconductor substrate, a silicide pattern formed on the exposed substrate, and a lower electrode covering an inner wall and... Agent: Harness, Dickey & Pierce, P.L.C

20070069272 - Semiconductor device comprising a plurality of semiconductor constructs: A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper layer insulating film is provided on the first semiconductor construct and insulating... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070069273 - Microelectronic device with storage elements and method of producing the same: The micro electronic device comprises a substrate with a surface and a plurality of storage elements in serial connection formed at the surface of the substrate, a plurality of transistors, each transistor being connected parallel to one of the plurality of storage elements. Each storage element comprises a storing material... Agent: Morrison & Foerster LLP

20070069274 - Varactor design using area to perimeter ratio for improved tuning range: Parallel plate tunable varactors having a bulk capacitance contribution to a total capacitance increased compared to a fringing capacitance contribution are disclosed. The contribution of the bulk capacitance to the total capacitance of an exemplary BST varactor is increased by increasing the area/perimeter ratio of the active region, thereby improving... Agent: Fenwick & West LLP

20070069275 - Bi-directional read/program non-volatile floating gate memory array, and method of formation: A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070069276 - Multi-use memory cell and memory array: A multi-use memory cell and memory array are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein... Agent: Brinks Hofer Gilson & Lione

20070069278 - Non-volatile reprogrammable memory: A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped,... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070069280 - Semiconductor device and method for fabricating the same: A semiconductor device includes a P-channel metal-oxide semiconductor (PMOS) transistor and an N-channel metal-oxide semiconductor (NMOS) transistor formed in three or more fin active regions in a vertical stack structure, an input metal line contacting gates of the PMOS transistor and NMOS transistor, a power supply voltage metal line contacting... Agent: Morgan Lewis & Bockius LLP

20070069279 - Semiconductor memory and method of manufacturing same: The present invention provides a semiconductor memory which has sense amplifiers, each including a pair of MOSFETs having complete symmetry in regard to not only the shape but also to the impurity profile in a diffusion layer, and the present invention is also capable of reducing variations in electric characteristics,... Agent: Mcginn Intellectual Property Law Group, PLLC

20070069277 - Sram cell with asymmetrical transistors for reduced leakage: A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on... Agent: Texas Instruments Incorporated

20070069281 - Ultra high density flash memory: Various aspects related to a method of reading a non-volatile memory cell adapted to store a first bit and a second bit. Various method embodiments comprise reading the first bit, including applying a first voltage level to a first node of the memory cell and a second voltage level to... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070069282 - Semiconductor device having gate insulating layers with differing thicknesses: Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second... Agent: Myers Bigel Sibley & Sajovec

20070069284 - Method and apparatus for operating a string of charge trapping memory cells: A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070069283 - Method of forming bottom oxide for nitride flash memory: A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070069285 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed in the upper part of the semiconductor substrate so as to be spaced; a channel region formed in a part of the semiconductor substrate between the source region and the drain region; a first dielectric... Agent: Mcdermott Will & Emery LLP

20070069287 - Insulated gate transistor incorporating diode: A p-type base layer shaped like a well is formed for each of IGBT cells, and a p+-type collector layer and an n+-type cathode layer are formed on a surface opposite to a surface on which the p-type base layer is formed so as to be situated just below the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070069286 - Semiconductor device having an interconnect with sloped walls and method of forming the same: A semiconductor device having at least one lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes... Agent: Slater & Matsil, L.L.P.

20070069289 - Method and apparatus for driving a power mos device as a synchronous rectifier: A synchronous rectifier comprising a MOSFET device, and a gate driver for driving the gate of the MOSFET device, the MOSFET device comprising first and second MOSFET transistors coupled with their drain-source paths in parallel to receive an alternating current waveform for rectification by the drain-source paths of the MOSFET... Agent: Ostrolenk Faber Gerb & Soffen

20070069288 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device for preventing a parasitic bipolar transistor from operating while reducing the ON resistance of a double-diffused MOS transistor. Boron having a relatively high solid solubility limit in silicon and indium having a relatively low solid solubility limit in silicon are diffused as p-type impurities into a body... Agent: Mcdermott Will & Emery LLP

20070069290 - Sram cell with asymmetrical pass gate: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed... Agent: Texas Instruments Incorporated

20070069291 - Method and apparatus improving gate oxide reliability by controlling accumulated charge: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in... Agent: Martin J. Jaquez, Esq. Jaquez & Associates

20070069292 - Semiconductor device having ldmos transistor and method for manufacturing the same: A semiconductor device includes: a semiconductor substrate having a first semiconductor layer, an insulation layer and a second semiconductor layer, which are stacked in this order; a LDMOS transistor disposed on the first semiconductor layer; and a region having a dielectric constant, which is lower than that of the first... Agent: Posz Law Group, PLC

20070069293 - Process for integrating planar and non-planar cmos transistors on a bulk substrate and article made thereby: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.... Agent: Intel/blakely

20070069296 - High-density high current device cell: A cell design and methods for reducing the cell size of cells in high-current devices, such as MRAM, by increasing the effective width of a transistor in the cell to be greater than the actual width of the active area of the cell are described. This permits the cell size... Agent: Slater & Matsil LLP

20070069295 - Process to integrate fabrication of bipolar devices into a cmos process flow: A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the... Agent: Mendelsohn & Associates, P.C.

20070069294 - Stress engineering using dual pad nitride with selective soi device architecture: A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of... Agent: Scully Scott Murphy & Presser, PC

20070069297 - Tri-states one-time programmable memory (otp) cell: A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using... Agent: Bo-in Lin

20070069298 - Mobility enhancement by strained channel cmosfet with single workfunction metal-gate and fabrication method thereof: The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively.... Agent: Quintero Law Office, PC

20070069299 - Thin film resistors integrated at a single metal interconnect level of die: An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the... Agent: Texas Instruments Incorporated

20070069300 - Planar ultra-thin semiconductor-on-insulator channel mosfet with embedded source/drain: A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater... Agent: International Business Machines Corporation Dept. 18g

20070069301 - Power transistor: A power transistor has a source region, a drain region, a semiconductor body arranged between the source region and the drain region, and a plurality of nanotubes. The plurality of nanotubes are connected in parallel and disposed in the semiconductor body such that the plurality of nanotubes are electrically insulated... Agent: Maginot, Moore & Beck Chase Tower

20070069306 - Apparatus and method for improving drive-strength and leakage of deep submicron mos transistors: An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased... Agent: Glenn Patent Group

20070069302 - Method of fabricating cmos devices having a single work function gate electrode by band gap engineering and article made thereby: A method utilizing a common gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby.... Agent: Intel/blakely

20070069304 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a first element region and a second element region formed on a substrate to be adjacent to each other with an isolation region interposed therebetween; a first gate insulating film formed on the first element region; a second gate insulating film formed on the second element... Agent: Mcdermott Will & Emery LLP

20070069303 - Semiconductor device and method of fabricating the same: According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising: forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate, and forming a second gate electrode via a second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070069305 - Single-event-effect tolerant soi-based inverter, nand element, nor element, semiconductor memory device and data latch circuit: Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected... Agent: Stephen M. De Klerk Blakely, Sokoloff, Taylor & Zafman LLP

20070069307 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a trench formed in a surface of a semiconductor substrate and defining a device region. A MOSFET includes a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and a source/drain diffusion area sandwiching a channel region below... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070069308 - Ldmos device and method for manufacturing the same: Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070069309 - Buried well for semiconductor devices: A substrate having a buried well is provided. The substrate may be formed by implanting ions in a surface well of a first substrate and subsequently forming a semiconductor layer, such as an epitaxial layer, over the surface well. In this manner, the surface well becomes a buried well having... Agent: Slater & Matsil LLP

20070069310 - Semiconductor controlled rectifiers for electrostatic discharge protection: A silicon controlled rectifier (SCR) may include a first well and a second well formed within a substrate. A first junction region and a second junction region may be formed within the first well. A third junction region may include a first portion formed within the first well and a... Agent: Harness, Dickey & Pierce, P.L.C

20070069311 - Electronic device with a gate electrode having at least two portions and a process for forming the electronic device: A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate... Agent: Larson Newman Abel Polansky & White, LLP

20070069312 - Semiconductor device and method for fabricating the same: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region formed in the semiconductor substrate and surrounded by the isolation region; a fully-silicided gate line formed on the isolation region and the active region; and an insulating sidewall continuously covering a side face of the... Agent: Mcdermott Will & Emery LLP

20070069313 - Hydrogen gas sensitive semiconductor sensor: A hydrogen gas sensitive semiconductor sensor including a catalytic metal layer, a semiconductor layer and an insulator layer arranged between the catalytic metal layer and the semiconductor layer. The catalytic metal layer includes an outer surface and an inner surface including at least one hydrogen atom adsorption surface portion. Each... Agent: Venable LLP

20070069314 - Magnetoresistive random access memory with improved layout design and process thereof: A MRAM memory and process thereof is described. A GMR magnetic layer is patterned to form a memory bit layer and an intermediate conductive layer. The intermediate conductive layer is disposed between two conductive layers such that shallow metal plugs can be utilized to interconnect the intermediate conductive layer and... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070069316 - Image sensor having dual gate pattern and method of manufacturing the same: An image sensor capable of improving the performance of a transistor of a peripheral circuit region while maintaining high picture quality, and a method of manufacturing the same are disclosed. The image sensor may include a semiconductor substrate having an active pixel region and a peripheral circuit region, a first... Agent: Harness, Dickey & Pierce, P.L.C

20070069317 - Optoelectronics processing module and method for manufacturing thereof: An optoelectronics processing module includes a transparent substrate and at least one optoelectronics component. One surface of the transparent substrate is formed with a plurality of first pads and a plurality of second pads. The optoelectronics component mounted on the transparent substrate has a plurality of connecting pads, which is... Agent: Birch Stewart Kolasch & Birch

20070069315 - Photodetector and n-layer structure for improved collection efficiency: An image sensor with an image area having a plurality of photodetectors of a first conductivity type includes a substrate of the second conductivity type; a first layer of the first conductivity type spanning the image area; a second layer of the second conductivity type; wherein the first layer is... Agent: Pamela R. Crocker Patent Legal Staff

20070069318 - Physical quantity sensor having optical part and method for manufacturing the same: A method for manufacturing a physical quantity sensor having a movable portion, a support portion and an optical part is provided. The method includes steps of: etching a silicon substrate so that a movable-portion-to-be-formed portion, a support-portion-to-be-formed portion, and an optical-part-to-be-formed portion having a plurality of columns and trenches are... Agent: Posz Law Group, PLC

20070069319 - Solid-state imaging device and method for producing the same: A solid-state imaging device includes: a base made of an insulation material and having a frame form in planar shape with an aperture formed at an inner region; a plurality of wirings provided on one surface of the base and extending toward an outer periphery of the base from a... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070069320 - Wiring structure of a semiconductor package and method of manufacturing the same, and wafer level package having the wiring structure and method of manufacturing the same: A wiring structure may include a pad, a conductive pattern and an insulating photoresist structure. The pad may be provided on a body and electrically connected to a circuit unit of the body. The conductive pattern may be provided on the body and may be electrically connected to the pad.... Agent: Harness, Dickey & Pierce, P.L.C

20070069321 - Cmos image sensor and method for manufacturing the same: A CIS and a method of manufacturing the same are provided. The CIS includes a device isolation layer formed on a device isolation region of a substrate of a first conductive type, the substrate including an active region and the device isolation region, the active region including a photodiode region... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070069322 - Cmos image sensor and method for manufacturing the same: Provided is a CMOS image sensor and method of manufacturing same. The CMOS image sensor includes a photodiode, a transfer transistor, a reset transistor, a drive transistor, and a select transistor. A device isolation layer is formed on a first conductive type substrate. Gate electrodes of the transfer transistor, the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070069323 - Semiconductor device: A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070069324 - Semiconductor device production method and semiconductor device: A production method for a semiconductor device, including the steps of: forming a semiconductor layer of the first conductivity on the semiconductor substrate; forming a trench in the semiconductor layer, the trench penetrating through the semiconductor layer to reach the semiconductor substrate; filling a filling material in a predetermined bottom... Agent: Rabin & Berdo, PC

20070069325 - Multilayer substrate for digital tuner and multilayer substrate: Mounting components such as LSIs, which emit noise to the outside and are subjected to the influence of external noise, on the top-most layer and the bottom-most layer respectively, a co-existing layer of the ground region and the power source region has been employed, where a ground region has been... Agent: Yokoi & Co., U.s.a., Inc.

20070069326 - Semiconductor device and a method of manufacturing the same: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over... Agent: Miles & Stockbridge PC

20070069327 - Method for manufacturing an integrated semiconductor device: In a method for manufacturing an integrated semiconductor device with low capacitive coupling between a conductive member and a via, a semiconductor substrate with a surface is provided. The conductive member is formed on the surface of the substrate wherein the conductive member is provided for conducting a current in... Agent: Morrison & Foerster LLP

20070069328 - Split gate flash devices: A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying... Agent: Thomas, Kayden, Hostemeyer & Risley LLP

20070069329 - Apparatus and method for reducing parasitic capacitance in a semiconductor device: A semiconductor device exhibiting low parasitic resistance comprises a first substrate characterized by a first resistivity; a second substrate characterized by a second resistivity, a third substrate and a metal element. These substrates form a multi-layer semiconductor device where the second substrate is formed on the first substrate; the third... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20070069330 - Fuse structure for a semiconductor device: A fuse structure on a peripheral region of a substrate, the fuse structure comprising a plurality of fuses disposed on a plane and parallel to each other, wherein each fuse has a melting block and the melting blocks are arranged in a staggered form. Because of the fuse structure with... Agent: J.c. Patents

20070069331 - Methods of forming electromigration and thermal gradient based fuse structures: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least... Agent: Intel/blakely

20070069332 - Energy coupled superlattice structures for silicon based lasers and modulators: A waveguide structure includes a SOI substrate. A core structure is formed on the SOI substrate comprising a plurality of multilayers having alternating or aperiodically distributed thin layers of either Si-rich oxide (SRO), Si-rich nitride (SRN) or Si-rich oxynitride (SRON). The multilayers are doped with a rare earth material so... Agent: Gauthier & Connors LLP

20070069333 - Integrated inductor structure and method of fabrication: An inductor structure comprised of a magnetic section and a single turn solenoid The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section.... Agent: Blakely Sokoloff Taylor & Zafman

20070069334 - Thin film resistors integrated at two different metal interconnect levels of single die: An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer.... Agent: Texas Instruments Incorporated

20070069335 - Bonded wafer and its manufacturing method: The bonding surfaces of an active layer wafer and a supporting wafer have fitting surfaces each comprising a part of a spherical surface of the same curvature, and they are to be bonded together with their bonding surfaces superposed with each other. As a result, an area left as not-bonded... Agent: Greenblum & Bernstein, P.L.C

20070069336 - Seal ring corner design: Techniques for an integrated circuit device are provided. The integrated circuit device includes a substrate, an active circuit area, and a dielectric layer. A seal ring surrounds the active circuit area. At least one corner area of the integrated circuit includes a plurality of corner band stacks. Each of the... Agent: Townsend And Townsend And Crew, LLP

20070069337 - Semiconductor structure and fabricating method thereof: A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each... Agent: Jianq Chyun Intellectual Property Office

20070069338 - Metal oxide dispersion for dye-sensitized solar cells, photoactive electrode and dye-sensitized solar cell: (1) A metal oxide dispersion for a dye-sensitized solar cell, which contains metal oxide fine particles, a binder composed of a polymer compound having an action to bind to the fine particles and a solvent; (2) a method for producing a photoactive electrode for a dye-sensitized solar cell by coating... Agent: Sughrue Mion, PLLC

20070069339 - Superconducting system, superconducting circuit chip, and high-temperature superconducting junction device with a shunt resistor: A superconducting system that includes an interface circuit capable of making the best use of a high-speed superconducting circuit and a high-speed semiconductor circuit. A multi-chip module in which an Nb superconducting circuit having Josephson junctions formed by the use of Nb and an oxide high-temperature superconducting latch interface circuit... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070069340 - Pickup device and pickup method: It is an object of the present invention to provide a device which can pick up a chip from an adhesive film while preventing damage to the chip. In addition, a device which can pick up a chip over an adhesive film with a high yield is provided. A pickup... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070069342 - Mems element and manufacturing method: A first electrode is formed on a semiconductor substrate. A second electrode is formed separately at a predetermined interval from the first electrode, and has at least one opening. An actuator layer is connected to the second electrode, and drives the second electrode.... Agent: Foley And Lardner LLP Suite 500

20070069343 - Molded semiconductor package: A molded semiconductor package has a lead frame to which an LSI is bonded, inner lead frames located on opposing sides of the lead frame, and wires. Each wire is connected between the LSI and a corresponding one of the inner lead frames. A distance between an edge of the... Agent: Leydig Voit & Mayer, Ltd

20070069341 - Radio recognition semiconductor device and its manufacturing method: A plurality of radio semiconductor chips each having a plurality of electrodes on a surface thereof is provided. By establishing connection between the respective electrodes of the semiconductor chips by wires in a chain form, continuous manufacture of inlets becomes possible. The effect of reducing the cost of a radio... Agent: Reed Smith LLP

20070069344 - Semiconductor module: To prevent any uneven solder wetting in a main surface of electrodes of a semiconductor connected with a main surface of a planar lead and any displacement of the lead vis-a-vis the electrodes due to the reflow of the solder in a semiconductor module having the semiconductor element mounted on... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070069345 - Package of leadframe with heatsinks: The present invention relates to a package of a leadframe with heatsinks. The package of the invention comprises a leadframe, a die, a first heatsink and a second heatsink. The leadframe has a die pad and a plurality of leads, and the leads are disposed around the die pad. The... Agent: Volentine Francos, & Whitt PLLC

20070069346 - Integrated circuit solder bumping system: An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the... Agent: Ishimaru & Zahrt LLP

20070069347 - Semiconductor chip and process for forming the same: A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures,... Agent: North America Intellectual Property Corporation

20070069348 - Dual-sided substrate integrated circuit package including a leadframe having leads with increased thickness: An integrated circuit package includes a first non-conductive substrate having a first inner surface and a second non-conductive substrate having a second inner surface. A die having a first thickness is disposed between the first and second inner surfaces. A leadframe includes a member having a proximal end and a... Agent: Delphi Technologies, Inc.

20070069350 - Method and apparatus for stacking electrical components using via to provide interconnection: An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on... Agent: Stout, Uxa, Buyan & Mullins LLP

20070069349 - Method for micro-electro mechanical system package: A method of manufacturing a multi-substrate semiconductor package. The method includes providing a first substrate with a plurality of first dies present thereon and forming a plurality of electrical contacts on an upper surface of a lateral extension portion of at least one of the plurality of first dies on... Agent: Townsend And Townsend And Crew, LLP

20070069352 - Bumpless chip package and fabricating process thereof: A bumpless chip package comprising a supporting component, a chip, a metal-filled layer and an interconnection structure is provided. The supporting component has a supporting surface and a cavity. The chip is disposed within the cavity and has a plurality of chip pads formed on an active surface of the... Agent: J.c. Patents, Inc.

20070069355 - Package with barrier wall and method for manufacturing the same: A ball grid array (BGA) package that may suppress flash contamination may include a flash contamination barrier wall. The barrier wall may be a portion of a copper pattern provided on a substrate. During a molding process, the flash contamination barrier may prevent a flash from contaminating a ball land.... Agent: Harness, Dickey & Pierce, P.L.C

20070069353 - Semiconductor device with plastic housing composition and method for producing the same: A semiconductor device with plastic housing composition includes an internal wiring that is electrically insulated from the plastic housing composition by an insulation layer. The plastic housing composition has a high thermal conductivity and a low coefficient of expansion, the coefficient of expansion being adapted to the semiconductor chip of... Agent: Edell, Shapiro & Finnan, LLC

20070069354 - Semiconductor sensor device with sensor chip and method for producing the same: A semiconductor sensor device includes a sensor chip. The sensor chip includes a sensor region and contact areas on its upper side and is further arranged in a cavity housing. The cavity housing includes side walls, a housing bottom, a cavity, external contacts on the outside of the cavity and... Agent: Edell, Shapiro & Finnan, LLC

20070069351 - Substrate carrier: The invention relates to a carrier for a substrate, wherein at least parts of the carrier are comprised of a material with a coefficient of thermal expansion which is higher than the coefficient of thermal expansion of the substrate. In order to avoid, or at least decrease, the nonuniform coating... Agent: Fulbright & Jaworski, LLP

20070069356 - Optical parts cap and method of manufacturing the same: An optical parts cap of the present invention includes a metal frame having an upper frame portion in which an opening portion is provided to a center portion and an upright frame portion provided to be connected to a lower peripheral portion of the upper frame portion, the metal frame... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070069357 - Device for thermal transfer and power generation: A system is provided. The system includes a device that includes top and bottom thermally conductive substrates positioned opposite to one another, wherein a top surface of the bottom thermally conductive substrate is substantially atomically flat and a thermal blocking layer disposed between the top and bottom thermally conductive substrates.... Agent: Patrick S. Yoder Fletcher Yoder

20070069358 - Gel package structural enhancement of compression system board connections: A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached to a system board and held together by... Agent: Lynn L. Augspurger IBM Corporation

20070069359 - Plasma display panel and the method of manufacturing the same: Provided are a plasma display panel and a method of manufacturing the same. The plasma display panel includes a plurality of substrates; a plurality of discharge electrode pairs formed on an inner surface of one of the substrates; a dielectric layer burying the discharge electrode pairs; barrier ribs disposed between... Agent: Knobbe Martens Olson & Bear LLP

20070069361 - Chip package and substrate thereof: A chip package coupled to a circuit board includes a substrate and at least one chip. The substrate includes a plurality of first pads, a plurality of second pads and at least one first interconnecting structure. The first pads and the chip are located on a first surface of the... Agent: Birch Stewart Kolasch & Birch

20070069360 - Semiconductor package substrate having different thicknesses between wire bonding pad and ball pad and method for fabricating the same: Disclosed herein are a semiconductor package substrate and a method for fabricating the same. In the semiconductor package substrate, the circuit layer of the wire bonding pad side differs in thickness from that of the ball pad side to which a half etching process is applied. In addition, a connection... Agent: Staas & Halsey LLP

20070069362 - Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same: Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to... Agent: Mcdermott Will & Emery LLP

20070069364 - Semiconductor device and method for manufacturing same: A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device 100 includes: a silicon substrate 101; a through electrode 129 extending through the silicon substrate 101; and a first insulating ring 130 provided in a circumference... Agent: Young & Thompson

20070069363 - Semiconductor ic-embedded substrate and method for manufacturing same: A semiconductor IC-embedded substrate suitable for embedding a semiconductor IC in which the electrode pitch is extremely narrow. The substrate comprises a semiconductor IC 120 in which stud bumps 121 are provided to the principal surface 120a, a first resin layer 111 for covering the principal surface 120a of the... Agent: Wolff Law Office, PLLC

20070069366 - Novel constraint stiffener design: A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070069365 - Semiconductor with damage detection circuitry: Disclosed herein are novel damage detection circuitries implemented on the periphery of a semiconductor device. The circuitries disclosed herein enable the easy identification of cracks and deformation, and other types of damage that commonly occur during test and assembly processes of semiconductor devices.... Agent: Hitt Gaines, PC Agere Systems Inc.

20070069367 - Reduced stress on saw die with surrounding support structures: A die structural support apparatus and method are disclosed, in which a die component is provided. A support element can be configured for use with the die component, wherein said support element surrounds said die component, thereby strengthening said die component to provide a surrounding die support structure thereof. The... Agent: Bryan Anderson Attorney, Intellectual Property

20070069371 - Cavity chip package: A package for an IC includes a carrier with a cavity formed on one of the major surfaces. Bumps of a semiconductor die are mated to contact pads located on the bottom of the cavity. The die is attached to the major surface of the carrier. The major surface creates... Agent: HorizonIPPte Ltd

20070069369 - Heat dissipation device and method for making the same: A heat dissipation device includes a chip unit and a heat dissipation unit thermally attached to the chip unit. The chip unit includes a carrier substrate and a chip in electrical contact with the carrier substrate. The heat dissipation unit includes a heat spreader thermally contacting with the chip and... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070069368 - Integrated circuit device incorporating metallurigacal bond to enhance thermal conduction to a heat sink: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a... Agent: Hitt Gaines, PC Agere Systems Inc.

20070069370 - Semiconductor device: A semiconductor device 1 includes a substrate 10, a semiconductor chip 20 (first semiconductor chip), semiconductor chips 30 (second semiconductor chips) and a heat sink 40. Semiconductor chips 20 and 30 are mounted on the substrate 10. The level of the top surface of the semiconductor chip 20 on the... Agent: Young & Thompson

20070069372 - Packaged die on pcb with heat sink encapsulant and methods: An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob... Agent: Trask Britt, P.C./ Micron Technology

20070069373 - Device with surface cooling and method of making: An electrical or mechanical device which tends to heat up during operation, which bears on its surface a roughening coating comprised of thermally conductive material which aids in cooling the device.... Agent: Edell, Shapiro & Finnan, LLC

20070069374 - Flash memory card: A Flash memory card is disclosed comprising a substrate, a Flash memory die on top of the substrate, a controller die on top of the Flash memory die, and an interposer coupled to with the controller die and on top of the Flash memory die wherein the interposer results in... Agent: Sawyer Law Group LLP

20070069375 - Semiconductor device having shield structure: A semiconductor device of the present invention has a base plate, a digital circuit section provided on a side of an upper surface of the base plate and having a plural