Active solid-state devices (e.g., transistors, solid-state diodes) inventions 03/07

20070069192 - Thermal switching element and method for manufacturing the same: The present invention provides a thermal switching element that has a quite different configuration from that of a conventional technique and can control heat transfer by the application of energy, and a method for manufacturing the thermal switching element. The thermal switching element includes a first electrode, a second electrode,... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070069193 - Metal-insulator transition switching transistor and method for manufacturing the same: Provided is a metal-insulator-transition switching transistor with a gate electrode on a silicon substrate (back-gate structure) and a metal-insulator-transition channel layer of VO2 that changes from an insulator phase to a metal phase, or vice versa, depending on a variation of an electric field, and a method for manufacturing the... Agent: Ladas & Parry LLP

20070069194 - Fabrication of nanowires: This disclosure relates to a system and method for creating nanowires. A nanowire can be created by exposing layers of material in a superlattice and dissolving and transferring material from edges of the exposed layers onto a substrate. The nanowire can also be created by exposing layers of material in... Agent: Hewlett Packard Company

20070069195 - Silicon germanium semiconductive alloy and method of fabricating same: A silicon germanium (SiGe) semiconductive alloy is grown on a substrate of single crystalline Al2O3. A {111} crystal plane of a cubic diamond structure SiGe is grown on the substrate's {0001} C-plane such that a <110> orientation of the cubic diamond structure SiGe is aligned with a <1,0,−1,0> orientation of... Agent: National Aeronautics And Space Administration Langley Research Center

20070069196 - Epitaxial wafer for led and light emitting diode: An epitaxial wafer for a light emitting diode has: a light-emitting portion having a n-type cladding layer, a p-type cladding layer and an active layer formed between the n-type cladding layer and the p-type cladding layer, the light-emitting portion being formed on a n-type substrate; and a p-type GaP current... Agent: Mcginn Intellectual Property Law Group, PLLC

20070069206 - Flat panel display device having an organic thin film transistor and method of manufacturing the same: Provided are an organic TFT that reduces contact resistance between a source and drain electrode and an organic semiconductor layer and that can be easily manufactured, a flat panel display device having the organic TFT, and methods of manufacturing the organic TFT and the flat panel display device having the... Agent: Knobbe Martens Olson & Bear LLP

20070069199 - Interface conditioning to improve efficiency and lifetime of organic electroluminescence devices: In at least one embodiment of the invention, an OLED device is disclosed in which the surface of one or more layers of the OLED are conditioned with metal nano-particles such that they are disposed along the interface between adjacent layers.... Agent: Fish & Richardson P.C.

20070069202 - Light-emitting device comprising semiconductor nanocrystal layer free of voids and method for producing the same: A light-emitting device including a semiconductor nanocrystal layer and a method for producing the light-emitting device are provided. The light-emitting device includes a semiconductor nanocrystal layer whose voids are filled with a filling material. According to the light-emitting device, since voids formed between nanocrystal particles of the semiconductor nanocrystal layer... Agent: Cantor Colburn, LLP

20070069204 - Liquid crystal display panel and method of fabricating the same: An LCD panel includes a first substrate including a first substrate material, a plurality of thin film transistors (“TFTs”) formed on the first substrate material each having a drain electrode, and an organic layer formed on the plurality of TFTs which further includes a color filter layer, a second substrate... Agent: Cantor Colburn, LLP

20070069197 - Monomers, oligomers and polymers of 2-functionalized and 2,7-difunctionalized carbzoles: The present invention relates to 2-functionalized and 2,7-difunctionalized carbazoles and 2,7-carbazolenevinylene oligomers and polymers. More specifically, the present invention relates to a compound of Formula (I): wherein R1 is selected from the group consisting of H, alkyl, and aryl; and wherein R2 and R3 are independently selected from the group... Agent: Fulbright & Jaworski L.L.P.

20070069200 - Oled separating structures: Techniques are described for forming a separating structure on an OLED device that is free from deformation. The separating structure prevents adjacent electrodes from contacting one another.... Agent: Fish & Richardson P.C.

20070069201 - Organic bistable device and method for manufacturing the same: An organic bistable device includes a first electrode, a second electrode, and an organic mixture layer, wherein the organic mixture layer is located between the first electrode and the second electrode. While a bias is applied between the first electrode and the second electrode of the bistable device, the doped... Agent: Jianq Chyun Intellectual Property Office

20070069205 - Organic electroluminescent display device: The invention prevents a photocurrent due to external light and a variation in characteristics of transistors or a failure by a short circuit due to the influence of a back channel. A light shield film made of a nonconductive material is formed on an insulation substrate. A back gate insulation... Agent: Morrison & Foerster LLP

20070069203 - Pyrene derivatives and organic electronic device using pyrene derivatives: The present invention provides an organic electronic device using the compound of the formula (1) and a pyrene derivative having a new structure.... Agent: Mckenna Long & Aldridge LLP

20070069198 - Synthesis of phenyl-substituted fluoranthenes by a diesel-alder reaction and the use thereof: with the proviso that R1, R2, R3 and X are not at the same time phenyl when R4 and R5 are hydrogen. Furthermore, the invention relates to a process for preparing them and the use of fluoranthene derivatives as emitter molecule in organic light-emitting diodes (OLEDs), a light-emitting layer comprising... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070069208 - Lsi design support apparatus and lsi design support method: An LSI design support apparatus includes a data acquisition section and an equal processing section. The data acquisition section acquires first position data concerning positions of a plurality of first electrodes provided along a side of a first substrate, and second position data concerning positions of a plurality of second... Agent: Young & Thompson

20070069207 - Method and system of trace pull test: The present invention provides an efficient test method and system for testing the IC package, such as BGA types of packages. With the present invention, manufacturer can have an easier way in testing various types of packages, including newer types. Manufacturer also can get the testing outcome which is more... Agent: Kusner & Jaffe Highland Place Suite 310

20070069209 - Transparent thin film transistor (tft) and its method of manufacture: A transparent thin film transistor (TFT) and a method of fabricating the same are provided. The transparent TFT includes transparent source and drain electrodes formed of transparent material, a transparent semiconductor activation layer that contacts the source and drain electrodes, that is formed of transparent semiconductor, and in which source... Agent: Robert E. Bushnell

20070069211 - Display apparatus and manufacturing method thereof: According to an aspect of the present invention, there is provided a display apparatus including a TFT array substrate on which TFTs are formed in an array, a counter substrate disposed so as to face the TFT array substrate, and a sealing pattern for adhering the TFT array substrate and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070069212 - Flat panel display and method for manufacturing the same: The present invention relates to a flat panel display having high picture quality, high flexibility and high flex-resistance. Specifically, the present invention provides a flat panel display having a plurality of pixels arranged in a matrix shape on a substrate, each of the plurality of pixels comprising a thin film... Agent: Greenblum & Bernstein, P.L.C

20070069210 - Liquid crystal display device and method for manufacturing the same: As a substrate gets larger, time of manufacture is increased due to the repetition of film formations and etchings; waste disposal costs of etchant and the like are increased; and material efficiency is significantly reduced. A base film for improving adhesion between a substrate and a material layer formed by... Agent: Nixon Peabody, LLP

20070069213 - Flexible adjustment of on-die termination values in semiconductor device: A termination value for a pin of a semiconductor device is set to a first value if a pin signal has a first logic state at an edge of a control signal, and to a second value if the pin signal has a second logic state at the edge of... Agent: Law Office Of Monica H Choi

20070069215 - Array substrate of liquid crystal display device and method of fabricating the same: An array substrate of a liquid crystal display device includes a substrate, a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel area, a common line parallel to the gate line, a common electrode extending from... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070069214 - Liquid crystal display and method of driving the same: A liquid crystal display with reduced power consumption and a method of driving the same, in which a liquid crystal display includes a liquid crystal panel including a lower substrate and an upper substrate. The lower substrate has a display region with liquid crystal cells formed at intersections of a... Agent: F. Chau & Associates, LLC

20070069217 - P-i-n diode crystallized adjacent to a silicide in series with a dielectric anitfuse: A method is described for forming a nonvolatile one-time-programmable memory cell having reduced programming voltage. A contiguous p-i-n diode is paired with a dielectric rupture antifuse formed of a high-dielectric-constant material, having a dielectric constant greater than about 8. In preferred embodiments, the high-dielectric-constant material is formed by atomic layer... Agent: Vierra Magen/sandisk Corporation

20070069216 - Substrate for compound semiconductor device and compound semiconductor device using the same: A substrate for compound semiconductor device and a compound semiconductor device using the substrate are provided which allow a breakdown voltage to be high, cause little energy loss, and are suitably used for a high-electron mobility transistor etc. An n-type 3C—SiC single crystal buffer layer 3 having a carrier concentration... Agent: Foley And Lardner LLP Suite 500

20070069220 - Composite semiconductor light-emitting device: A composite semiconductor light-emitting device includes a first semiconductor element portion made of a first semiconductor material and a second semiconductor element portion made of a second semiconductor material different from the first semiconductor material. The first semiconductor element portion has a first semiconductor layered structure, and the second semiconductor... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070069219 - Light emitting device: A light emitting device is proposed, which emits light while connected to the power. The light emitting device includes a light emitting element having at least two electrodes disposed at the side of the light output surface thereof; and a base member having a recess and lead portions corresponding to... Agent: Birch Stewart Kolasch & Birch

20070069218 - Light-emitting diode chip: A light-emitting diode chip (LED chip) including a substrate, an electrostatic conducting layer, a first type doped semiconductor layer, an active layer, a second type doped semiconductor layer, a first electrode and a second electrode is provided. The electrostatic conducting layer is disposed on the substrate, while the first type... Agent: Jianq Chyun Intellectual Property Office

20070069221 - Semiconductor laser diode and method of fabricating the same: A semiconductor laser diode capable of further improving temperature characteristics while sufficiently preventing a laser beam emission end surface portion from thermal destruction through a window structure is obtained. This semiconductor laser diode comprises an active layer having a window structure on a laser beam emission end surface portion and... Agent: Ndq&m Watchstone LLP

20070069222 - Gallium nitride based semiconductor light emitting diode and method of manufacturing the same: A GaN based LED and a method of manufacturing the same are provided. The GaN based semiconductor LED can have an improved heat dissipation capability of a sapphire substrate, thereby preventing device characteristic from being degraded by heat and improving the luminous efficiency of the device. In the GaN based... Agent: Mcdermott Will & Emery LLP

20070069223 - Light emitting diode element and driving method thereof: A light emitting diode (LED) element includes a substrate, a first light emitting unit, a second light emitting unit, a first electrode couple and a second electrode couple. The first light emitting unit is disposed on the substrate. The second light emitting unit is disposed on the first light emitting... Agent: Jianq Chyun Intellectual Property Office

20070069224 - Light-emitting device, production method thereof, and electronic apparatus: In a light-emitting device in which light-emitting elements that emit light having the same color are arrayed in a matrix on a pixel-forming surface of a substrate and the light emitted from the light-emitting elements is emitted from a surface of the substrate opposite to the pixel-forming surface, the light-emitting... Agent: Oliff & Berridge, PLC

20070069226 - Fabrication method of nitride semiconductor light emitting device and nitride semiconductor light emitting device thereby: A method for fabricating a nitride semiconductor light emitting device, and a nitride semiconductor light emitting device fabricated thereby are provided. The method includes: forming a first conductive nitride semiconductor layer on a substrate; forming an active layer on the first conductive nitride semiconductor layer; forming a second conductive nitride... Agent: Birch Stewart Kolasch & Birch

20070069225 - Iii-v light emitting device: A semiconductor structure includes an n-type region, a p-type region, and a III-nitride light emitting layer disposed between the n-type region and the p-type region. The III-nitride light emitting layer has a lattice constant greater than 3.19 Å. Such a semiconductor structure may be grown on a substrate including a... Agent: Patent Law Group LLP

20070069228 - Edge-emitting led assembly: A light-emitting diode (LED) in accordance with the invention includes an edge-emitting LED stack having an external emitting surface from which light is emitted, and a reflective element that is located adjacent to at least one external surface of the LED stack other than the external emitting surface. The reflective... Agent: Avago Technologies, Ltd.

20070069227 - Housing for a radiation-emitting component, method for the production thereof, and radiation-emitting component: The invention relates to a housing for at least two radiation-emitting components, especially LEDs, comprising a system carrier (1) and a reflector arrangement (2) arranged on said system carrier (1). Said reflector arrangement comprises a number of reflectors that are respectively used to receive at least one radiation-emitting component and... Agent: Fish & Richardson PC

20070069230 - Light-emitting diode and light source device having same: A light-emitting diode (10) includes a light-emitting chip (12) and a light-permeable cover (16) arranged over the light-emitting chip. The cover has a central convex portion (162) and a peripheral portion (164) surrounding the convex portion. The convex portion is positioned above the light-emitting chip. The peripheral portion has an... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070069229 - Photodetector with charge-carrier reflector: A photodetector includes a charge carrier collector and a charge carrier concentrator that redirects onto the collector charge carriers that are not initially headed towards the collector.... Agent: Koppel, Patrick & Heybl

20070069232 - Semiconductor device with a resin-sealed optical semiconductor element: To provide a semiconductor device 10, which is thin, compact, and excellent in mechanical strength and humidity resistance. Semiconductor device 10A has a configuration such that in semiconductor device 10A, wherein an optical semiconductor element 14, having a light receiving part or a light emitting part, is sealed in a... Agent: Fish & Richardson P.C.

20070069231 - Semiconductor light-emitting device and method: A semiconductor light-emitting device can include a submount on which a semiconductor light-emitting element is mounted. The device can have a high light utilization efficiency with high reliability and can achieve a reduction in manufacturing cost as well as a decrease in size. The submount can have a reverse trapezoidal... Agent: Cermak & Kenealy, LLP

20070069233 - Multilayer device and method of making: The invention relates to composite articles comprising a substrate and additional layers on the substrate. According to one example, the layers are selected so that the difference in the coefficient of thermal expansion (CTE) between the substrate and a first layer on one side of the substrate is substantially equal... Agent: General Electric Company Global Research

20070069234 - Nitride semiconductor device: A nitride semiconductor device is provided. In the device, first and second conductivity type nitride layers are formed. An active layer is formed between the first and second conductivity type nitride layers. The active layer includes at least one quantum barrier layer and at least one quantum well layer. Also,... Agent: Mcdermott Will & Emery LLP

20070069235 - Light-emitting element: A light-emitting element (1) includes a light-emitting layer (2) including a phosphor, and at least two electrodes (6, 7). The light-emitting element (1) includes at least two kinds of electrically insulating layers (2, 9) with different dielectric constants. One of the electrically insulating layers (2, 9) is the light-emitting layer... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070069236 - Control circuit and method for driving a half-bridge circuit: A method is disclosed for controlling a first transistor in a half-bridge circuit which also includes a second transistor. The transistors can be controlled by applying drive voltages to their gates. During a switch-off operation of the second transistor, the amplitude of the drive voltage of the second transistor is... Agent: Maginot, Moore & Beck Chase Tower

20070069237 - Systems for providing electrostatic discharge protection: Systems for providing electrostatic discharge (ESD) protection. One of the Systems has a plurality of first-type thin film diode elements coupled to each other in series, and a plurality of second-type thin film diode elements coupled to each other in series. The first-type thin film elements are electrically connected to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070069238 - Solid-state image pickup device and method for producing the same: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation... Agent: Robert J. Depke Lewis T. Steadman

20070069239 - Electronic device containing group-iii elements based nitride semiconductors: An electronic device includes a substrate; a single-crystalline first buffer layer, disposed on the substrate, containing a semiconductor represented by the formula AlxGa1-xN; a non-single-crystalline second buffer layer, disposed on the first buffer layer, containing a semiconductor represented by the formula AlyGa1-yN; and an undoped base layer, disposed on the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070069240 - Iii-v compound semiconductor heterostructure mosfet device: A III-V based, implant free MOS heterostructure field-effect transistor device comprises a gate insulator layer overlying a compound semiconductor substrate; ohmic contacts coupled to the compound semiconductor substrate proximate opposite sides of an active device region defined within the compound semiconductor substrate; and a gate metal contact electrode formed on... Agent: Freescale Semiconductor, Inc. Law Department

20070069241 - Memory with high dielectric constant antifuses and method for using at low voltage: A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using antifuse materials having higher dielectric constant and higher acceleration factor than silicon dioxide, and by using diodes having lower band gaps than silicon. Such memory arrays can... Agent: Matrix Semiconductor, Inc.

20070069242 - Semiconductor chip and semiconductor device, and method for manufacturing semiconductor device: A semiconductor chip is provided comprising a semiconductor substrate on which an integrated circuit is formed. The semiconductor chip, which is provided on the semiconductor substrate in an area array, further comprises a plurality of electrodes electrically coupled with the inside of the semiconductor substrate, wherein the electrodes are arranged... Agent: Harness, Dickey & Pierce, P.L.C

20070069243 - Forming closely spaced electrodes: The present invention provides an apparatus and a method of fabricating the apparatus. The apparatus comprises a substrate having a planar surface and first and second electrodes located on the planar surface. The first electrode has a top surface and a lateral surface, and the lateral surface has an edge... Agent: Hitt Gaines, PC Lucent Technologies Inc.

20070069244 - Transistor including paramagnetic impurities and having anti-parallel ferromagnetic contacts: A transistor device may comprise a source having a first ferromagnetic contact thereto, a drain having a second ferromagnetic contact thereto, an electrically conductive gate positioned over a channel region separating the source and the drain, and an electrically insulating layer disposed between the gate and the channel region. The... Agent: Barnes & Thornburg LLP

20070069245 - Protective plate for a plasma display and a method for producing the same: A protective plate for a plasma display comprises conductive substrate for protecting a plasma display and an electrode in electrical contact with the conductive substrate.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070069247 - Electro-optic displays, and components for use therein: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes... Agent: David J Cole E Ink Corporation

20070069246 - Hybrid devices: Hybrid devices, such as optically erasable memory cells and light sensors, and related methods are disclosed. In some embodiments, a device includes a structure capable of converting between a first resistance state and a second resistance state, and a light source configured to convert the structure from the first resistance... Agent: William J. Uhl

20070069248 - Solid-state image pickup device: Provided is a solid-state image pickup device which comprises well contacts and well wirings for supplying a reference voltage to a well and can suppress a reduction in an amount of light received even when a pixel area is decreased. As a well wiring, used is a well main-wiring 4... Agent: Mcdermott Will & Emery LLP

20070069249 - Phase change memory device and method of manufacturing the device: The invention provides a novel structure of a phase change memory device. In the phase change memory device of the invention, an electrode acting as a radiating fin does not exit immediately above a phase change area of a phase change layer (115). A heater electrode (111) and landing electrode... Agent: Mcdermott Will & Emery LLP

20070069250 - Integrated circuit with depletion mode jfet: An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device... Agent: Docket Administrator Agere Systems Inc.

20070069251 - Touch panel: A touch panel including a substrate body having a wave plate, a first elastic layer and a first substrate, a second substrate facing to the substrate body, a first conductive layer, a second conductive layer, a second elastic layer and a polarizing plate. A first conductive layer is formed at... Agent: Ratnerprestia

20070069252 - Insulated gate semiconductor device having a clamping element to clamp gate-emitter voltage and method of manufacturing thereof: The gate of an IGBT is connected to a gate terminal. One end of a clamping element is connected to an anode terminal. A voltage higher than a clamping voltage is applied between the gate and the emitter, to thereby test the dielectric breakdown voltage of a gate insulating film... Agent: Mcdermott Will & Emery LLP

20070069253 - Epitaxial substrate for field effect transistor: An epitaxial crystal for a field effect transistor which has a nitride-based III-V group semiconductor epitaxial crystal grown on a SiC single crystal base substrate having micropipes by use of an epitaxial growth method, wherein at least a part of the micropipes spreading from the SiC single crystal base substrate... Agent: Birch Stewart Kolasch & Birch

20070069255 - Mos transistors having optimized channel plane orientation, semiconductor devices including the same, and methods of fabricating the same: MOS transistors having an optimized channel plane orientation are provided. The MOS transistors include a semiconductor substrate having a main surface of a (100) plane. An isolation layer is provided in a predetermined region of the semiconductor substrate to define an active region. A source region and a drain region... Agent: Marger Johnson & Mccollom, P.C.

20070069254 - Multiple-gate mos transistor using si substrate and method of manufacturing the same: Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an... Agent: Ladas & Parry LLP

20070069257 - Power semiconductor component having a field electrode and method for producing this component: A power semiconductor component includes a semiconductor body and a field electrode. The semiconductor body has a drift zone of a first conduction type and a further component defining a junction therebetween. The junction is configured to cause a space charge zone to propagate when a reverse voltage is applied... Agent: Maginot, Moore & Beck Chase Tower

20070069256 - Semiconductor device comprising at least one mos transistor having an etch stop layer, and corresponding fabrication process: A semiconductor device includes at least one MOS transistor, each transistor being provided with a source region and a drain region formed in a semiconductor substrate, along with a gate region and spacers. The transistor is covered with a unitary etch stop layer that includes at least a first zone... Agent: Jenkens & Gilchrist, PC

20070069258 - Pixel having two semiconductor layers, image sensor including the pixel, and image processing system including the image sensor: An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor. The bottom patterned semiconductor layer contains transistors for detecting, resetting, amplifying and transmitting signals charges received from the photoelectric elements. The top and bottom... Agent: F. Chau & Associates, LLC

20070069259 - Cmos image sensor and method of manufacturing the same: A CMOS image sensor, and method for manufacturing the same is provided. The CMOS image sensor includes a device isolation film formed in a device isolation region of a semiconductor substrate to define an active region and a device isolation region, a gate insulation film formed on the semiconductor substrate.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070069261 - Cmos image sensor and a method for manufacturing the same: A CIS and a method for manufacturing the same are provided. The CIS includes a photodiode formed on a substrate; an interlayer insulation layer formed on an entire surface of the substrate including the photodiode; a color filter layer formed on the interlayer insulation layer to pass light in a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070069262 - Multi-layer interconnect with isolation layer: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation... Agent: Knobbe Martens Olson & Bear LLP

20070069260 - Photodetector structure for improved collection efficiency: An image sensor with an image area having a plurality of photodetectors of a first conductivity type includes a substrate of the second conductivity type; a first layer of the first conductivity type substantially spanning an area of each photodetector; wherein the first layer abuts each photodetector and is between... Agent: Pamela R. Crocker Patent Legal Staff

20070069263 - Electric switch and memory device using the same: An electric switch includes a ferroelectric substrate to which metal is added, a pair of electrodes provided on the ferroelectric substrate, and an electric field applying portion for changing the direction of polarization in part of the ferroelectric substrate.... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070069264 - Ferroelectric varactors suitable for capacitive shunt switching and wireless sensing: A ferroelectric varactor suitable for capacitive shunt switching is disclosed. High resistivity silicon with a SiO2 layer and a patterned metallic layer deposited on top is used as the substrate. A ferroelectric thin-film layer deposited on the substrate is used for the implementation of the varactor. A top metal electrode... Agent: Dinsmore & Shohl LLP

20070069266 - Memory device: Conventionally, the layer of the insulator between a cathode and an anode is formed by a droplet discharge method, vapor deposition, or the like separately from an interlayer insulating film formed over a thin film transistor, which creates problems of increase in cost and the number of manufacturing steps. A... Agent: Eric Robinson

20070069265 - Recess transistor (tr) gate to obtain large self-aligned contact (sac) open margin: A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the... Agent: Lee & Morse, P.C.

20070069268 - Recessed gate transistor structure and method of forming the same: Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance... Agent: Marger Johnson & Mccollom, P.C.

20070069267 - Semiconductor device and manufacturing method thereof: A semiconductor device comprises static random access memory (SRAM) cells formed in a semiconductor substrate, first deep trenches isolating each boundary of an n-well and a p-well of the SRAM cells, second deep trenches isolating the SRAM cells into each unit bit cell, and at least one or more contacts... Agent: Foley And Lardner LLP Suite 500

20070069269 - Stacked capacitor and method of fabricating same: The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor... Agent: Texas Instruments Incorporated

20070069270 - Top electrode in a strongly oxidizing environment: An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in... Agent: Knobbe Martens Olson & Bear LLP

20070069271 - Methods for manufacturing capacitors for semiconductor devices: Capacitors for semiconductor devices and methods of fabricating such capacitors are provided The disclosed capacitor comprises an interlayer dielectric layer (ILD) pattern having an opening exposing a portion of the underlying semiconductor substrate, a silicide pattern formed on the exposed substrate, and a lower electrode covering an inner wall and... Agent: Harness, Dickey & Pierce, P.L.C

20070069272 - Semiconductor device comprising a plurality of semiconductor constructs: A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper layer insulating film is provided on the first semiconductor construct and insulating... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070069273 - Microelectronic device with storage elements and method of producing the same: The micro electronic device comprises a substrate with a surface and a plurality of storage elements in serial connection formed at the surface of the substrate, a plurality of transistors, each transistor being connected parallel to one of the plurality of storage elements. Each storage element comprises a storing material... Agent: Morrison & Foerster LLP

20070069274 - Varactor design using area to perimeter ratio for improved tuning range: Parallel plate tunable varactors having a bulk capacitance contribution to a total capacitance increased compared to a fringing capacitance contribution are disclosed. The contribution of the bulk capacitance to the total capacitance of an exemplary BST varactor is increased by increasing the area/perimeter ratio of the active region, thereby improving... Agent: Fenwick & West LLP

20070069275 - Bi-directional read/program non-volatile floating gate memory array, and method of formation: A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070069276 - Multi-use memory cell and memory array: A multi-use memory cell and memory array are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein... Agent: Brinks Hofer Gilson & Lione

20070069278 - Non-volatile reprogrammable memory: A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped,... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070069280 - Semiconductor device and method for fabricating the same: A semiconductor device includes a P-channel metal-oxide semiconductor (PMOS) transistor and an N-channel metal-oxide semiconductor (NMOS) transistor formed in three or more fin active regions in a vertical stack structure, an input metal line contacting gates of the PMOS transistor and NMOS transistor, a power supply voltage metal line contacting... Agent: Morgan Lewis & Bockius LLP

20070069279 - Semiconductor memory and method of manufacturing same: The present invention provides a semiconductor memory which has sense amplifiers, each including a pair of MOSFETs having complete symmetry in regard to not only the shape but also to the impurity profile in a diffusion layer, and the present invention is also capable of reducing variations in electric characteristics,... Agent: Mcginn Intellectual Property Law Group, PLLC

20070069277 - Sram cell with asymmetrical transistors for reduced leakage: A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on... Agent: Texas Instruments Incorporated

20070069281 - Ultra high density flash memory: Various aspects related to a method of reading a non-volatile memory cell adapted to store a first bit and a second bit. Various method embodiments comprise reading the first bit, including applying a first voltage level to a first node of the memory cell and a second voltage level to... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070069282 - Semiconductor device having gate insulating layers with differing thicknesses: Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second... Agent: Myers Bigel Sibley & Sajovec

20070069284 - Method and apparatus for operating a string of charge trapping memory cells: A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070069283 - Method of forming bottom oxide for nitride flash memory: A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070069285 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed in the upper part of the semiconductor substrate so as to be spaced; a channel region formed in a part of the semiconductor substrate between the source region and the drain region; a first dielectric... Agent: Mcdermott Will & Emery LLP

20070069287 - Insulated gate transistor incorporating diode: A p-type base layer shaped like a well is formed for each of IGBT cells, and a p+-type collector layer and an n+-type cathode layer are formed on a surface opposite to a surface on which the p-type base layer is formed so as to be situated just below the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070069286 - Semiconductor device having an interconnect with sloped walls and method of forming the same: A semiconductor device having at least one lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes... Agent: Slater & Matsil, L.L.P.

20070069289 - Method and apparatus for driving a power mos device as a synchronous rectifier: A synchronous rectifier comprising a MOSFET device, and a gate driver for driving the gate of the MOSFET device, the MOSFET device comprising first and second MOSFET transistors coupled with their drain-source paths in parallel to receive an alternating current waveform for rectification by the drain-source paths of the MOSFET... Agent: Ostrolenk Faber Gerb & Soffen

20070069288 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device for preventing a parasitic bipolar transistor from operating while reducing the ON resistance of a double-diffused MOS transistor. Boron having a relatively high solid solubility limit in silicon and indium having a relatively low solid solubility limit in silicon are diffused as p-type impurities into a body... Agent: Mcdermott Will & Emery LLP

20070069290 - Sram cell with asymmetrical pass gate: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed... Agent: Texas Instruments Incorporated

20070069291 - Method and apparatus improving gate oxide reliability by controlling accumulated charge: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in... Agent: Martin J. Jaquez, Esq. Jaquez & Associates

20070069292 - Semiconductor device having ldmos transistor and method for manufacturing the same: A semiconductor device includes: a semiconductor substrate having a first semiconductor layer, an insulation layer and a second semiconductor layer, which are stacked in this order; a LDMOS transistor disposed on the first semiconductor layer; and a region having a dielectric constant, which is lower than that of the first... Agent: Posz Law Group, PLC

20070069293 - Process for integrating planar and non-planar cmos transistors on a bulk substrate and article made thereby: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.... Agent: Intel/blakely

20070069296 - High-density high current device cell: A cell design and methods for reducing the cell size of cells in high-current devices, such as MRAM, by increasing the effective width of a transistor in the cell to be greater than the actual width of the active area of the cell are described. This permits the cell size... Agent: Slater & Matsil LLP

20070069295 - Process to integrate fabrication of bipolar devices into a cmos process flow: A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the... Agent: Mendelsohn & Associates, P.C.

20070069294 - Stress engineering using dual pad nitride with selective soi device architecture: A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of... Agent: Scully Scott Murphy & Presser, PC

20070069297 - Tri-states one-time programmable memory (otp) cell: A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using... Agent: Bo-in Lin

20070069298 - Mobility enhancement by strained channel cmosfet with single workfunction metal-gate and fabrication method thereof: The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively.... Agent: Quintero Law Office, PC

20070069299 - Thin film resistors integrated at a single metal interconnect level of die: An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the... Agent: Texas Instruments Incorporated

20070069300 - Planar ultra-thin semiconductor-on-insulator channel mosfet with embedded source/drain: A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater... Agent: International Business Machines Corporation Dept. 18g

20070069301 - Power transistor: A power transistor has a source region, a drain region, a semiconductor body arranged between the source region and the drain region, and a plurality of nanotubes. The plurality of nanotubes are connected in parallel and disposed in the semiconductor body such that the plurality of nanotubes are electrically insulated... Agent: Maginot, Moore & Beck Chase Tower

20070069306 - Apparatus and method for improving drive-strength and leakage of deep submicron mos transistors: An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased... Agent: Glenn Patent Group

20070069302 - Method of fabricating cmos devices having a single work function gate electrode by band gap engineering and article made thereby: A method utilizing a common gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby.... Agent: Intel/blakely

20070069304 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a first element region and a second element region formed on a substrate to be adjacent to each other with an isolation region interposed therebetween; a first gate insulating film formed on the first element region; a second gate insulating film formed on the second element... Agent: Mcdermott Will & Emery LLP

20070069303 - Semiconductor device and method of fabricating the same: According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising: forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate, and forming a second gate electrode via a second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070069305 - Single-event-effect tolerant soi-based inverter, nand element, nor element, semiconductor memory device and data latch circuit: Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected... Agent: Stephen M. De Klerk Blakely, Sokoloff, Taylor & Zafman LLP

20070069307 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a trench formed in a surface of a semiconductor substrate and defining a device region. A MOSFET includes a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and a source/drain diffusion area sandwiching a channel region below... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070069308 - Ldmos device and method for manufacturing the same: Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070069309 - Buried well for semiconductor devices: A substrate having a buried well is provided. The substrate may be formed by implanting ions in a surface well of a first substrate and subsequently forming a semiconductor layer, such as an epitaxial layer, over the surface well. In this manner, the surface well becomes a buried well having... Agent: Slater & Matsil LLP

20070069310 - Semiconductor controlled rectifiers for electrostatic discharge protection: A silicon controlled rectifier (SCR) may include a first well and a second well formed within a substrate. A first junction region and a second junction region may be formed within the first well. A third junction region may include a first portion formed within the first well and a... Agent: Harness, Dickey & Pierce, P.L.C

20070069311 - Electronic device with a gate electrode having at least two portions and a process for forming the electronic device: A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate... Agent: Larson Newman Abel Polansky & White, LLP

20070069312 - Semiconductor device and method for fabricating the same: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region formed in the semiconductor substrate and surrounded by the isolation region; a fully-silicided gate line formed on the isolation region and the active region; and an insulating sidewall continuously covering a side face of the... Agent: Mcdermott Will & Emery LLP

20070069313 - Hydrogen gas sensitive semiconductor sensor: A hydrogen gas sensitive semiconductor sensor including a catalytic metal layer, a semiconductor layer and an insulator layer arranged between the catalytic metal layer and the semiconductor layer. The catalytic metal layer includes an outer surface and an inner surface including at least one hydrogen atom adsorption surface portion. Each... Agent: Venable LLP

20070069314 - Magnetoresistive random access memory with improved layout design and process thereof: A MRAM memory and process thereof is described. A GMR magnetic layer is patterned to form a memory bit layer and an intermediate conductive layer. The intermediate conductive layer is disposed between two conductive layers such that shallow metal plugs can be utilized to interconnect the intermediate conductive layer and... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070069316 - Image sensor having dual gate pattern and method of manufacturing the same: An image sensor capable of improving the performance of a transistor of a peripheral circuit region while maintaining high picture quality, and a method of manufacturing the same are disclosed. The image sensor may include a semiconductor substrate having an active pixel region and a peripheral circuit region, a first... Agent: Harness, Dickey & Pierce, P.L.C

20070069317 - Optoelectronics processing module and method for manufacturing thereof: An optoelectronics processing module includes a transparent substrate and at least one optoelectronics component. One surface of the transparent substrate is formed with a plurality of first pads and a plurality of second pads. The optoelectronics component mounted on the transparent substrate has a plurality of connecting pads, which is... Agent: Birch Stewart Kolasch & Birch

20070069315 - Photodetector and n-layer structure for improved collection efficiency: An image sensor with an image area having a plurality of photodetectors of a first conductivity type includes a substrate of the second conductivity type; a first layer of the first conductivity type spanning the image area; a second layer of the second conductivity type; wherein the first layer is... Agent: Pamela R. Crocker Patent Legal Staff

20070069318 - Physical quantity sensor having optical part and method for manufacturing the same: A method for manufacturing a physical quantity sensor having a movable portion, a support portion and an optical part is provided. The method includes steps of: etching a silicon substrate so that a movable-portion-to-be-formed portion, a support-portion-to-be-formed portion, and an optical-part-to-be-formed portion having a plurality of columns and trenches are... Agent: Posz Law Group, PLC

20070069319 - Solid-state imaging device and method for producing the same: A solid-state imaging device includes: a base made of an insulation material and having a frame form in planar shape with an aperture formed at an inner region; a plurality of wirings provided on one surface of the base and extending toward an outer periphery of the base from a... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070069320 - Wiring structure of a semiconductor package and method of manufacturing the same, and wafer level package having the wiring structure and method of manufacturing the same: A wiring structure may include a pad, a conductive pattern and an insulating photoresist structure. The pad may be provided on a body and electrically connected to a circuit unit of the body. The conductive pattern may be provided on the body and may be electrically connected to the pad.... Agent: Harness, Dickey & Pierce, P.L.C

20070069321 - Cmos image sensor and method for manufacturing the same: A CIS and a method of manufacturing the same are provided. The CIS includes a device isolation layer formed on a device isolation region of a substrate of a first conductive type, the substrate including an active region and the device isolation region, the active region including a photodiode region... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070069322 - Cmos image sensor and method for manufacturing the same: Provided is a CMOS image sensor and method of manufacturing same. The CMOS image sensor includes a photodiode, a transfer transistor, a reset transistor, a drive transistor, and a select transistor. A device isolation layer is formed on a first conductive type substrate. Gate electrodes of the transfer transistor, the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070069323 - Semiconductor device: A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070069324 - Semiconductor device production method and semiconductor device: A production method for a semiconductor device, including the steps of: forming a semiconductor layer of the first conductivity on the semiconductor substrate; forming a trench in the semiconductor layer, the trench penetrating through the semiconductor layer to reach the semiconductor substrate; filling a filling material in a predetermined bottom... Agent: Rabin & Berdo, PC

20070069325 - Multilayer substrate for digital tuner and multilayer substrate: Mounting components such as LSIs, which emit noise to the outside and are subjected to the influence of external noise, on the top-most layer and the bottom-most layer respectively, a co-existing layer of the ground region and the power source region has been employed, where a ground region has been... Agent: Yokoi & Co., U.s.a., Inc.

20070069326 - Semiconductor device and a method of manufacturing the same: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over... Agent: Miles & Stockbridge PC

20070069327 - Method for manufacturing an integrated semiconductor device: In a method for manufacturing an integrated semiconductor device with low capacitive coupling between a conductive member and a via, a semiconductor substrate with a surface is provided. The conductive member is formed on the surface of the substrate wherein the conductive member is provided for conducting a current in... Agent: Morrison & Foerster LLP

20070069328 - Split gate flash devices: A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying... Agent: Thomas, Kayden, Hostemeyer & Risley LLP

20070069329 - Apparatus and method for reducing parasitic capacitance in a semiconductor device: A semiconductor device exhibiting low parasitic resistance comprises a first substrate characterized by a first resistivity; a second substrate characterized by a second resistivity, a third substrate and a metal element. These substrates form a multi-layer semiconductor device where the second substrate is formed on the first substrate; the third... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20070069330 - Fuse structure for a semiconductor device: A fuse structure on a peripheral region of a substrate, the fuse structure comprising a plurality of fuses disposed on a plane and parallel to each other, wherein each fuse has a melting block and the melting blocks are arranged in a staggered form. Because of the fuse structure with... Agent: J.c. Patents

20070069331 - Methods of forming electromigration and thermal gradient based fuse structures: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least... Agent: Intel/blakely

20070069332 - Energy coupled superlattice structures for silicon based lasers and modulators: A waveguide structure includes a SOI substrate. A core structure is formed on the SOI substrate comprising a plurality of multilayers having alternating or aperiodically distributed thin layers of either Si-rich oxide (SRO), Si-rich nitride (SRN) or Si-rich oxynitride (SRON). The multilayers are doped with a rare earth material so... Agent: Gauthier & Connors LLP

20070069333 - Integrated inductor structure and method of fabrication: An inductor structure comprised of a magnetic section and a single turn solenoid The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section.... Agent: Blakely Sokoloff Taylor & Zafman

20070069334 - Thin film resistors integrated at two different metal interconnect levels of single die: An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer.... Agent: Texas Instruments Incorporated

20070069335 - Bonded wafer and its manufacturing method: The bonding surfaces of an active layer wafer and a supporting wafer have fitting surfaces each comprising a part of a spherical surface of the same curvature, and they are to be bonded together with their bonding surfaces superposed with each other. As a result, an area left as not-bonded... Agent: Greenblum & Bernstein, P.L.C

20070069336 - Seal ring corner design: Techniques for an integrated circuit device are provided. The integrated circuit device includes a substrate, an active circuit area, and a dielectric layer. A seal ring surrounds the active circuit area. At least one corner area of the integrated circuit includes a plurality of corner band stacks. Each of the... Agent: Townsend And Townsend And Crew, LLP

20070069337 - Semiconductor structure and fabricating method thereof: A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each... Agent: Jianq Chyun Intellectual Property Office

20070069338 - Metal oxide dispersion for dye-sensitized solar cells, photoactive electrode and dye-sensitized solar cell: (1) A metal oxide dispersion for a dye-sensitized solar cell, which contains metal oxide fine particles, a binder composed of a polymer compound having an action to bind to the fine particles and a solvent; (2) a method for producing a photoactive electrode for a dye-sensitized solar cell by coating... Agent: Sughrue Mion, PLLC

20070069339 - Superconducting system, superconducting circuit chip, and high-temperature superconducting junction device with a shunt resistor: A superconducting system that includes an interface circuit capable of making the best use of a high-speed superconducting circuit and a high-speed semiconductor circuit. A multi-chip module in which an Nb superconducting circuit having Josephson junctions formed by the use of Nb and an oxide high-temperature superconducting latch interface circuit... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070069340 - Pickup device and pickup method: It is an object of the present invention to provide a device which can pick up a chip from an adhesive film while preventing damage to the chip. In addition, a device which can pick up a chip over an adhesive film with a high yield is provided. A pickup... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070069342 - Mems element and manufacturing method: A first electrode is formed on a semiconductor substrate. A second electrode is formed separately at a predetermined interval from the first electrode, and has at least one opening. An actuator layer is connected to the second electrode, and drives the second electrode.... Agent: Foley And Lardner LLP Suite 500

20070069343 - Molded semiconductor package: A molded semiconductor package has a lead frame to which an LSI is bonded, inner lead frames located on opposing sides of the lead frame, and wires. Each wire is connected between the LSI and a corresponding one of the inner lead frames. A distance between an edge of the... Agent: Leydig Voit & Mayer, Ltd

20070069341 - Radio recognition semiconductor device and its manufacturing method: A plurality of radio semiconductor chips each having a plurality of electrodes on a surface thereof is provided. By establishing connection between the respective electrodes of the semiconductor chips by wires in a chain form, continuous manufacture of inlets becomes possible. The effect of reducing the cost of a radio... Agent: Reed Smith LLP

20070069344 - Semiconductor module: To prevent any uneven solder wetting in a main surface of electrodes of a semiconductor connected with a main surface of a planar lead and any displacement of the lead vis-a-vis the electrodes due to the reflow of the solder in a semiconductor module having the semiconductor element mounted on... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070069345 - Package of leadframe with heatsinks: The present invention relates to a package of a leadframe with heatsinks. The package of the invention comprises a leadframe, a die, a first heatsink and a second heatsink. The leadframe has a die pad and a plurality of leads, and the leads are disposed around the die pad. The... Agent: Volentine Francos, & Whitt PLLC

20070069346 - Integrated circuit solder bumping system: An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the... Agent: Ishimaru & Zahrt LLP

20070069347 - Semiconductor chip and process for forming the same: A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures,... Agent: North America Intellectual Property Corporation

20070069348 - Dual-sided substrate integrated circuit package including a leadframe having leads with increased thickness: An integrated circuit package includes a first non-conductive substrate having a first inner surface and a second non-conductive substrate having a second inner surface. A die having a first thickness is disposed between the first and second inner surfaces. A leadframe includes a member having a proximal end and a... Agent: Delphi Technologies, Inc.

20070069350 - Method and apparatus for stacking electrical components using via to provide interconnection: An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on... Agent: Stout, Uxa, Buyan & Mullins LLP

20070069349 - Method for micro-electro mechanical system package: A method of manufacturing a multi-substrate semiconductor package. The method includes providing a first substrate with a plurality of first dies present thereon and forming a plurality of electrical contacts on an upper surface of a lateral extension portion of at least one of the plurality of first dies on... Agent: Townsend And Townsend And Crew, LLP

20070069352 - Bumpless chip package and fabricating process thereof: A bumpless chip package comprising a supporting component, a chip, a metal-filled layer and an interconnection structure is provided. The supporting component has a supporting surface and a cavity. The chip is disposed within the cavity and has a plurality of chip pads formed on an active surface of the... Agent: J.c. Patents, Inc.

20070069355 - Package with barrier wall and method for manufacturing the same: A ball grid array (BGA) package that may suppress flash contamination may include a flash contamination barrier wall. The barrier wall may be a portion of a copper pattern provided on a substrate. During a molding process, the flash contamination barrier may prevent a flash from contaminating a ball land.... Agent: Harness, Dickey & Pierce, P.L.C

20070069353 - Semiconductor device with plastic housing composition and method for producing the same: A semiconductor device with plastic housing composition includes an internal wiring that is electrically insulated from the plastic housing composition by an insulation layer. The plastic housing composition has a high thermal conductivity and a low coefficient of expansion, the coefficient of expansion being adapted to the semiconductor chip of... Agent: Edell, Shapiro & Finnan, LLC

20070069354 - Semiconductor sensor device with sensor chip and method for producing the same: A semiconductor sensor device includes a sensor chip. The sensor chip includes a sensor region and contact areas on its upper side and is further arranged in a cavity housing. The cavity housing includes side walls, a housing bottom, a cavity, external contacts on the outside of the cavity and... Agent: Edell, Shapiro & Finnan, LLC

20070069351 - Substrate carrier: The invention relates to a carrier for a substrate, wherein at least parts of the carrier are comprised of a material with a coefficient of thermal expansion which is higher than the coefficient of thermal expansion of the substrate. In order to avoid, or at least decrease, the nonuniform coating... Agent: Fulbright & Jaworski, LLP

20070069356 - Optical parts cap and method of manufacturing the same: An optical parts cap of the present invention includes a metal frame having an upper frame portion in which an opening portion is provided to a center portion and an upright frame portion provided to be connected to a lower peripheral portion of the upper frame portion, the metal frame... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070069357 - Device for thermal transfer and power generation: A system is provided. The system includes a device that includes top and bottom thermally conductive substrates positioned opposite to one another, wherein a top surface of the bottom thermally conductive substrate is substantially atomically flat and a thermal blocking layer disposed between the top and bottom thermally conductive substrates.... Agent: Patrick S. Yoder Fletcher Yoder

20070069358 - Gel package structural enhancement of compression system board connections: A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached to a system board and held together by... Agent: Lynn L. Augspurger IBM Corporation

20070069359 - Plasma display panel and the method of manufacturing the same: Provided are a plasma display panel and a method of manufacturing the same. The plasma display panel includes a plurality of substrates; a plurality of discharge electrode pairs formed on an inner surface of one of the substrates; a dielectric layer burying the discharge electrode pairs; barrier ribs disposed between... Agent: Knobbe Martens Olson & Bear LLP

20070069361 - Chip package and substrate thereof: A chip package coupled to a circuit board includes a substrate and at least one chip. The substrate includes a plurality of first pads, a plurality of second pads and at least one first interconnecting structure. The first pads and the chip are located on a first surface of the... Agent: Birch Stewart Kolasch & Birch

20070069360 - Semiconductor package substrate having different thicknesses between wire bonding pad and ball pad and method for fabricating the same: Disclosed herein are a semiconductor package substrate and a method for fabricating the same. In the semiconductor package substrate, the circuit layer of the wire bonding pad side differs in thickness from that of the ball pad side to which a half etching process is applied. In addition, a connection... Agent: Staas & Halsey LLP

20070069362 - Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same: Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to... Agent: Mcdermott Will & Emery LLP

20070069364 - Semiconductor device and method for manufacturing same: A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device 100 includes: a silicon substrate 101; a through electrode 129 extending through the silicon substrate 101; and a first insulating ring 130 provided in a circumference... Agent: Young & Thompson

20070069363 - Semiconductor ic-embedded substrate and method for manufacturing same: A semiconductor IC-embedded substrate suitable for embedding a semiconductor IC in which the electrode pitch is extremely narrow. The substrate comprises a semiconductor IC 120 in which stud bumps 121 are provided to the principal surface 120a, a first resin layer 111 for covering the principal surface 120a of the... Agent: Wolff Law Office, PLLC

20070069366 - Novel constraint stiffener design: A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070069365 - Semiconductor with damage detection circuitry: Disclosed herein are novel damage detection circuitries implemented on the periphery of a semiconductor device. The circuitries disclosed herein enable the easy identification of cracks and deformation, and other types of damage that commonly occur during test and assembly processes of semiconductor devices.... Agent: Hitt Gaines, PC Agere Systems Inc.

20070069367 - Reduced stress on saw die with surrounding support structures: A die structural support apparatus and method are disclosed, in which a die component is provided. A support element can be configured for use with the die component, wherein said support element surrounds said die component, thereby strengthening said die component to provide a surrounding die support structure thereof. The... Agent: Bryan Anderson Attorney, Intellectual Property

20070069371 - Cavity chip package: A package for an IC includes a carrier with a cavity formed on one of the major surfaces. Bumps of a semiconductor die are mated to contact pads located on the bottom of the cavity. The die is attached to the major surface of the carrier. The major surface creates... Agent: HorizonIPPte Ltd

20070069369 - Heat dissipation device and method for making the same: A heat dissipation device includes a chip unit and a heat dissipation unit thermally attached to the chip unit. The chip unit includes a carrier substrate and a chip in electrical contact with the carrier substrate. The heat dissipation unit includes a heat spreader thermally contacting with the chip and... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070069368 - Integrated circuit device incorporating metallurigacal bond to enhance thermal conduction to a heat sink: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a... Agent: Hitt Gaines, PC Agere Systems Inc.

20070069370 - Semiconductor device: A semiconductor device 1 includes a substrate 10, a semiconductor chip 20 (first semiconductor chip), semiconductor chips 30 (second semiconductor chips) and a heat sink 40. Semiconductor chips 20 and 30 are mounted on the substrate 10. The level of the top surface of the semiconductor chip 20 on the... Agent: Young & Thompson

20070069372 - Packaged die on pcb with heat sink encapsulant and methods: An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob... Agent: Trask Britt, P.C./ Micron Technology

20070069373 - Device with surface cooling and method of making: An electrical or mechanical device which tends to heat up during operation, which bears on its surface a roughening coating comprised of thermally conductive material which aids in cooling the device.... Agent: Edell, Shapiro & Finnan, LLC

20070069374 - Flash memory card: A Flash memory card is disclosed comprising a substrate, a Flash memory die on top of the substrate, a controller die on top of the Flash memory die, and an interposer coupled to with the controller die and on top of the Flash memory die wherein the interposer results in... Agent: Sawyer Law Group LLP

20070069375 - Semiconductor device having shield structure: A semiconductor device of the present invention has a base plate, a digital circuit section provided on a side of an upper surface of the base plate and having a plurality of external connection electrodes, an insulating layer provided on the base plate around the digital circuit section and on... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070069377 - Clock distribution networks and conductive lines in semiconductor integrated circuits: A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on one side of the interposer, and output terminals (130) of the clock distribution network are formed on the opposite side... Agent: Macpherson Kwok Chen & Heid LLP

20070069376 - Component with chip through-contacts: A panel for the production of electronic components is disclosed. The components have a substantially planar semiconductor chip with chip through-contacts which are provided with electrically conductive material. A rewiring region is subdivided into an insulating layer and also a first rewiring arranged therein, the rewiring projecting laterally beyond the... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070069378 - Semiconductor module and method of forming a semiconductor module: In one embodiment, a semiconductor module includes at least one semiconductor chip package, a board having functional pads and dummy pads, and at least one solder joint electrically connecting the semiconductor chip package and one of the functional pads of the board. Furthermore, at least one supporting solder bump is... Agent: Harness, Dickey & Pierce, P.L.C

20070069379 - Lead-free solder ball: A Sn—Ag—Cu based lead-free solder ball which does not undergo yellowing of its surface when formed into a solder bump on an electrode of an electronic part such as a BGA package. The solder ball has excellent wettability and does not form voids at the time of soldering, even when... Agent: Michael Tobias

20070069380 - Ohmic contact on p-type gan: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of... Agent: Avago Technologies, Ltd.

20070069381 - Interconnect structure with polygon cell structures: Interconnect structures with polygonal cell structures. An exemplary interconnect structure comprises a substrate and a first dielectric layer, overlying the substrate and exposing a conductive feature formed therethrough and connected with the substrate, wherein the first dielectric layer includes a plurality of polygon cell structures with hollow interior.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070069382 - Semiconductor device: The invention includes a layer having an integrated circuit, a first terminal which is formed over the layer having the integrated circuit and is electrically connected to the layer having the integrated circuit, a conductive layer which functions as an antenna, which is formed over the first terminal and is... Agent: Eric Robinson

20070069383 - Semiconductor device containing a ruthenium diffusion barrier and method of forming: A semiconductor device containing a ruthenium diffusion barrier and a method of forming and integrating the ruthenium diffusion barrier with bulk Cu. The method includes forming the Ru diffusion barrier by depositing a first Ru layer onto a substrate in a first CVD process, modifying the first Ru layer by... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070069386 - Memory circuit: A memory circuit includes a first resistor composed of chalcogenide, a second resistor composed of chalcogenide, and electrically connected in series to the first resistor, and an inverter having an input terminal electrically connected to a node through which the first and second resistors are electrically connected to each other.... Agent: Sughrue Mion, PLLC

20070069385 - Mim capacitor integrated into the damascene structure and method of making thereof: This invention provides for the integration of metal-insulator-metal (MIM) capacitors with the damascene interconnect structure and process. The method includes forming a damascene interconnect structure and a MIM capacitor damascene structure wherein a diffusion barrier material forms the capacitor electrodes. The method includes forming a MIM capacitor damascene structure through... Agent: Slater & Matsil, L.L.P.

20070069384 - Semiconductor device: A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A , a second metal layer 113 formed in the hole 112A... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070069387 - Semiconductor device and method of forming the same: Provided is a method of forming a contact hole. The method includes: depositing an interlayer insulating layer on a semiconductor substrate on which a dummy region and an active region are defined; coating a photoresist film on the interlayer insulating layer; patterning the photoresist film using a mask having a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070069388 - Semiconductor device featuring large reinforcing elements in pad area, and pattern design apparatus therefor: In a semiconductor device, a plurality of interconnections are formed in an interconnection formation insulating interlayer, and a plurality of reinforcing elements are substantially evenly formed in blank areas of the interconnection insulating interlayer in which no interconnection is formed. A wire-bonding electrode pad is provided above the interconnection formation... Agent: Young & Thompson

20070069390 - Flash memory card: A memory card comprising a substrate, a memory die on top of the memory die, a controller die on top of the memory die; and a interposer surrounding the controller die and on top of the memory die wherein the interposer allows for wire bonding to the substrate to be... Agent: Sawyer Law Group LLP

20070069389 - Stackable device, device stack and method for fabricating the same: The present invention generally relates to a method for fabricating a stackable packaged device and a method for producing a packaged device stack utilizing stackable packaged devices. The present invention further refers to a stackable packaged device and a packaged device stack.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070069391 - Stacked die semiconductor package: A stacked die semiconductor package includes: a substrate, having a first surface and an opposite surface thereto; a plurality of dice, structured for being stacked one on top of the other on the first surface of the substrate, including at least a first die which is mounted closest to the... Agent: Seed Intellectual Property Law Group PLLC

20070069392 - Modular bonding pad structure and method: A semiconductor die includes a plurality of drivers and a plurality of bonding pads. Each driver is formed by a plurality of interconnected modules and has an associated bonding pad to which at least one of the modules of the driver is electrically connected. The modules of some of the... Agent: Avago Technologies, Ltd.

20070069395 - Image sensor module, camera module using the same, and method of manufacturing the camera module: The present invention relates to an image sensor module including a flexible printed circuit board (FPCB) having a window; and an image sensor that is formed to have the same size as the width of the FPCB and is attached on one surface of the FPCB, the image sensor including... Agent: Staas & Halsey LLP

20070069394 - Solder bump structure for flip chip semiconductor devices and method of manufacture therefore: The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump... Agent: Hitt Gaines, PC Agere Systems Inc.

20070069393 - Wiring board embedded with spherical semiconductor element: A double-sided or multilayer wiring board having high-density wiring is obtained by embedding a spherical semiconductor element in an electrically insulating substrate which composes the wiring board, and a thin electronic device can be provided using such a wiring board. Furthermore, a flexible double-sided or multilayer wiring board which is... Agent: Wenderoth, Lind & Ponack L.L.P.

20070069396 - Semiconductor package, method of manufacturing the same, stacked semiconductor package including the same and method of manufacturing the stacked semiconductor package: Example embodiments relate to a semiconductor package, a method of manufacturing the semiconductor package, a stacked semiconductor package including the semiconductor package, and a method of manufacturing the stacked semiconductor package. Other example embodiments relate to a semiconductor package having a structure that allows at least two packages to be... Agent: Harness, Dickey & Pierce, P.L.C

20070069397 - Coil construction: A coil comprises a layer of permeable material (4) deposited in a chip (CH) of an integrated circuit (IC) in a plane substantially parallel to a surface (A) of a substrate (1) of the chip (CH). A first conductor element (6a, 6b; BW10, BWI 1; 60a, 60b) is arranged at... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070069400 - Alignment mark, alignment apparatus and method, exposure apparatus, and device manufacturing method: An alignment mark including a first mark usable for both coarse alignment measurement in a first direction and fine alignment measurement in the first direction, and a second mark usable for coarse alignment measurement in a second direction different from the first direction.... Agent: Fitzpatrick Cella Harper & Scinto

20070069399 - Overlay mark: An overlay mark is provided. A first material layer is formed on a substrate, and then a first trench serving as a trench type outer mark is formed in the first material layer. The first trench is partially filled with the first deposition layer. A second material is formed over... Agent: Jianq Chyun Intellectual Property Office

20070069398 - Overlay metrology mark: An overlay metrology mark for determining the relative position between two or more layers of an integrated circuit structure comprising a first mark portion associated with and in particular developed on a first layer and a second mark portion associated with and in particular developed on the surface of a... Agent: Perkins Coie LLP Patent-sea

20070069401 - Semiconductor device, manufacturing method thereof, liquid crystal display device, rfid tag, light emitting device, and electronic device: There is provided a semiconductor device, in which characteristics of the semiconductor device are improved by thinning a gate insulating film and a leak current can be reduced, and a manufacturing method thereof. An aluminum film which is a metal film is formed over a polycrystalline semiconductor film, and plasma... Agent: Eric Robinson

20070069402 - Lateral phase change memory: A lateral phase change cell may be formed over a semiconductor substrate. The lateral cell, in some embodiments, may be exposed to light so that the same cell may be addressed by both optical and electrical signals.... Agent: Trop Pruner & Hu, PC

20070063180 - Electrically rewritable non-volatile memory element and method of manufacturing the same: A non-volatile memory element includes a recording layer that includes a phase change material, a lower electrode provided in contact with the recording layer, an upper electrode provided in contact with a portion of the upper surface of the recording layer, a protective insulation film provided in contact with the... Agent: Mcdermott Will & Emery LLP

20070063181 - Memory device and method of making same: A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a first area of electrical communication with the phase-change material. A second electrode in electrical communication with the phase-change material, the second electrode having a second area of... Agent: Rader, Fishman & Grauer PLLC

20070063182 - Enhancement mode single electron transistor: A transistor having a bottom dielectric layer, a first layer, a second layer, a top dielectric layer, and a gate electrode. The first layer and the second layer form a composite quantum well between the bottom dielectric layer and the top dielectric layer. The first layer, the second layer, and... Agent: Naval Research Laboratory Associate Counsel (patents)

20070063183 - Substrate having silicon dots: A substrate having silicon dots wherein at least one insulating layer and at least one group of silicon dots are formed on a substrate selected from a non-alkali glass substrate and a substrate made of a polymer material.... Agent: Rader Fishman & Grauer PLLC

20070063184 - Phase modulation device, phase modulation device fabrication method, crystallization apparatus, and crystallization method: A phase shifter which modulates the phase of incident light has a light-transmitting substrate such as a glass substrate, and a phase modulator such as a concavity and convexity pattern which is formed on the laser beam incident surface of the light-transmitting substrate and modules the phase of incident light.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070063186 - Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer: A method for making a semiconductor device may include forming a stress layer on a back surface of a semiconductor substrate and forming a strained superlattice layer adjacent a front surface of the semiconductor substrate. More particularly, the stress layer may include a material different than the semiconductor substrate. Also,... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070063185 - Semiconductor device including a front side strained superlattice layer and a back side stress layer: A semiconductor device may include a semiconductor substrate having front and back surfaces, a strained superlattice layer adjacent the front surface of the semiconductor substrate and comprising a plurality of stacked groups of layers, and a stress layer on the back surface of the substrate and comprising a material different... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070063190 - Aromatic compound: wherein, Ar1 and Ar3 represent a tetra-valent aromatic hydrocarbon group or a tetra-valent heterocyclic group, and Ar2, Ar4, Ar5, Ar6 and Ar7 represent a tri-valent aromatic hydrocarbon group or a tri-valent heterocyclic group, A1 represents -Z1-, -Z2-Z3- or -Z4=Z5-, wherein Z1, Z2 and Z3 represent O, S or the like... Agent: Sughrue Mion, PLLC

20070063189 - Compounds based on fluoranthene and use thereof: in which R1, R2, R3 and a are each defined according to the description, with the proviso that at least one of the R1 or R2 radicals is not hydrogen, to processes for their preparation and to the use of the fluoranthene derivatives as emitter molecules in organic light-emitting diodes... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070063191 - Crosslinkable substituted fluorene compounds: Novel 2,7-di(arylamino)-substituted fluorenes that are further substituted at the 9-position with one or more crosslinkable moieties, oligomers or polymers formed by crosslinking of said crosslinkable moieties, methods for their preparation, and use thereof in forming solvent resistant films having use as interlayers in electronic devices, especially electroluminescent devices.... Agent: Sughrue Mion, PLLC

20070063195 - Flat panel display and manufacturing method of flat panel display: The present disclosure relates to a display device comprising an insulating substrate; a source electrode and a drain electrode on the insulating substrate and separated by a channel area; an organic semiconductor layer formed in the channel area and on at least a portion of the source electrode and at... Agent: Macpherson Kwok Chen & Heid LLP

20070063196 - Light emitting device: By doping an organic compound functioning as an electron donor (hereinafter referred to as donor molecules) into an organic compound layer contacting a cathode, donor levels can be formed between respective LUMO (lowest unoccupied molecular orbital) levels between the cathode and the organic compound layer, and therefore electrons can be... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070063188 - Low-k dielectric material: The present invention relates to thin films suitable as dielectrics in integrated circuits and for other similar applications and to methods for the production thereof. In particular, the invention concerns thin films comprising at least partially cross-linked siloxane structures obtainable by hydrolysis of one or more silicon compounds of the... Agent: Kubovcik & Kubovcik

20070063194 - Organic electroluminescent display device for applying to the field of full-color display and method for manufacturing the same: The present invention relates to an organic electroluminescent display device for applying to the field of full-color display. The device includes a first electrode provided on the surface of a color filter. A first organic light emitting unit for generating a first light and a fourth organic light emitting unit... Agent: Rosenberg, Klein & Lee

20070063193 - Organic memory device having memory active region formed by embossing structure: An organic memory device having a memory active region formed by an embossing structure. This invention provides an organic memory device including a substrate, a first electrode formed on the substrate, an organic memory layer formed on the first electrode, a second electrode formed on the organic memory layer and... Agent: Cantor Colburn, LLP

20070063187 - Switching element: The present invention provides a switching element that has a stable bistable characteristic and a high transition voltage and demonstrates excellent cyclic performance. The switching element has two stable resistance values with respect to the voltage applied between electrodes, wherein a first electrode layer, an organic bistable material layer, and... Agent: Rossi, Kimms & Mcdowell LLP.

20070063192 - Systems for emitting light incorporating pixel structures of organic light-emitting diodes: Systems for emitting light incorporating pixel structures of organic light-emitting diodes (OLEDs) are provided. A representative system comprises: a first sub-pixel area including a first OLED; and a second sub-pixel area including a second OLED and a second control circuit, wherein said second control circuit includes electronic components for controlling... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070063197 - Adaptive input-cell circuitry useful in configurable electronic controllers: A method for operating an input-cell comprises: receiving a sensor input signal, a digital-bias first control input and a second control input and, using a first resistor network to apply an analog pull-up bias to the sensor input signal when the bias of the first control input is in a... Agent: Mark G. Bocchetti Patent Legal Staff

20070063199 - Semiconductor apparatus having semiconductor circuits made of semiconductor devices, and method of manufacture thereof: A semiconductor device comprises a first insulating film provided over a substrate and heat-treated, a second insulating film provided over the first insulating film, and a semiconductor film provided over the second insulating film, the second insulating film and the semiconductor film being formed successively without exposing them to the... Agent: Nixon Peabody, LLP

20070063198 - Semiconductor device: A semiconductor device capable of preventing the occurrence of stress in a field region, and to prevent dislocation, caused by the stress, in the active region is provided. The semiconductor device includes a support substrate; an active island region having single crystal silicon being formed on the support substrate; a... Agent: GlobalIPCounselors, LLP

20070063200 - Sequential lateral solidification device and method of crystallizing silicon using the same: A sequential lateral solidification (SLS) device and a method of crystallizing silicon using the same is disclosed, wherein alignment keys are formed on a substrate with one mask having a plurality of different patterns, and a crystallization process is progressed in parallel to an imaginary line connecting the alignment keys... Agent: Birch Stewart Kolasch & Birch

20070063201 - Optical module having a lens formed without contacting a reflector and method of making the same: An optical module includes a substrate, a chip, a reflector and a lens. The chip is disposed on the substrate for emitting light. The reflector is disposed on the substrate for reflecting light emitted by the chip. The lens is formed on the substrate using resin. The lens covers the... Agent: North America Intellectual Property Corporation

20070063202 - Method for producing electronic components: In order to achieve an integration of functional structures into the housing of electronic components, provision is made of a method for producing an electronic component comprising at least one semiconductor element having at least one sensor-technologically active and/or emitting device on at least one side, the method comprising the... Agent: Charles N. J. Ruggiero Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20070063203 - Method for producing electronic components: A diode is formed by an N+ diffusion layer and a P-type semiconductor substrate. In an N-well, a diode is formed by a P+ diffusion layer and an N+ diffusion layer. The N+ diffusion layer is connected to power supply wiring. A fuse is connected to the N+ diffusion layer... Agent: Foley And Lardner LLP Suite 500

20070063206 - Electrical connection structure, liquid ejection head, method of manufacturing same, and image forming apparatus: The electrical connection structure includes: a first substrate which has a first electrode part; a second substrate which has a second electrode part opposing the first electrode part, and a wiring pattern connected to the second electrode part; an insulating cavity substrate which is disposed between the first substrate and... Agent: Birch Stewart Kolasch & Birch

20070063205 - Organic light emitting display device: A laser induced thermal imaging (LITI) apparatus and a method of making an electronic device using the same are disclosed. The LITI apparatus includes a chamber, a substrate support, a contact frame, and a laser source or oscillator. The LITI apparatus transfers a transferable layer from a film donor device... Agent: Knobbe Martens Olson & Bear LLP

20070063204 - Surface mounting led substrate and led: An LED and a surface mounting LED substrate for use in production of multi-faced surface mounting LEDs can include a resist layer on a conductor pattern that runs from an LED chip-mounted upper surface along a side portion and to a lower surface of the LED substrate. The resist layer... Agent: Cermak & Kenealy, LLP

20070063207 - Nitride semiconductor device: According to the nitride semiconductor device with the active layer made of the multiple quantum well structure of the present invention, the performance of the multiple quantum well structure can be brought out to intensify the luminous output thereof thereby contributing an expanded application of the nitride semiconductor device. In... Agent: Volentine Francos, & Whitt PLLC

20070063208 - Nanocrystal/photonic crystal composites: The present invention is directed to composite photonic crystal materials of a photonic crystal structure having voids throughout, where the photonic crystal structure includes a colloidal nanocrystal-doped composite infiltrated within the voids, the colloidal nanocrystal-doped composite including a sol-gel or polymeric host/matrix material.... Agent: Los Alamos National Security, LLC

20070063210 - Backlight module and a light-emitting-diode package structure therefor: The LED package structure includes a substrate, an LED chip, a plastic package body, and two leading legs. In addition, the LED chip is arranged on the substrate and covered by the packaging plastic body. Moreover, the plastic package body contains a light-converging part and a light-scattering part, in which... Agent: Jianq Chyun Intellectual Property Office

20070063209 - Led reflecting plate and led device: A recess is formed in a land (2) of an LED reflecting plate (1) formed of a metal plate. The recess comprises a flat LED chip mounting portion (7) and a reflecting portion (8) inclined with respect to the LED chip mounting portion (7). The LED reflecting plate (1) is... Agent: Blakely Sokoloff Taylor & Zafman

20070063211 - Thin-film transistor and thin-film diode having amorphous-oxide semiconductor layer: A thin-film transistor including a channel layer being formed of an oxide semiconductor transparent to visible light and having a refractive index of nx, a gate-insulating layer disposed on one face of the channel layer, and a transparent layer disposed on the other face of the channel layer and having... Agent: Fitzpatrick Cella Harper & Scinto

20070063213 - Led package: A package allowing agile deployment of the location of each LED chip includes a heat slug to secure multiple LED chips, two lead frames, a conducting area extending along the edge of the heat slug, and a non-conductive material that connects the heat slug and the lead frame for those... Agent: Troxell Law Office PLLC

20070063214 - Light emitting diode package and method for manufacturing the same: The invention relates to a light emitting diode package that can prevent deterioration of phosphor and a method of manufacturing the same. The light emitting diode package includes a package body having a recessed part, a light emitting diode chip mounted on a floor surface of the recessed part and... Agent: Mcdermott Will & Emery LLP

20070063212 - Semiconductor laser device and manufacturing method thereof: In a semiconductor laser device 10 including a semiconductor laser element 14, a frame 12 having a front face on which the semiconductor laser element 14 is placed, and a resin molded portion 15 that covers the front and back faces of the frame 12, on a front face side... Agent: Mcdermott Will & Emery LLP

20070063215 - Manufacturing method for nitride semiconductor device and nitride semiconductor light emitting device obtained with the same: Processed traces are formed on at least a part of intended cutting lines A along which a wafer (10) where a nitride semiconductor lamination portion (6) is formed on a GaN based substrate (1) is divided into chips, by irradiating with a laser beam LB having a wavelength which is... Agent: Rabin & Berdo, PC

20070063216 - Semiconductor package: A semiconductor package including a bidirectional compound semiconductor component and two power semiconductor devices connected in a cascode configuration.... Agent: Ostrolenk Faber Gerb & Soffen

20070063217 - Bonded-wafer superjunction semiconductor device: A bonded-wafer semiconductor device includes a semiconductor substrate, a buried oxide layer disposed on a first main surface of the semiconductor substrate and a multi-layer device stack. The multi-layer device stack includes a first device layer of a first conductivity disposed on the buried oxide layer, a second device layer... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070063218 - Semiconductor device and electrostatic discharge protection device: A semiconductor device is provided. The semiconductor device is suitable for an electrostatic discharge protection circuit. The semiconductor device includes a gate structure, an N-type source region, an N-type well region, an N-type drain region, and an N-doped region. Wherein, the gate structure comprises a gate and a gate oxide... Agent: Jianq Chyun Intellectual Property Office

20070063219 - Voltage tunable integrated infrared imager: An integrated thermal imager for detecting combined passive LWIR or MWIR radiation of a scene and active SWIR radiation of a laser source is described The imager includes a two-dimensional focal plane array (2D-FPA) constituted by an assembly of voltage tunable photodetectors. Each voltage tunable photodetector integrates a quantum well... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20070063220 - Field-effect transistor: A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. The channel is formed near the interface between the channel layer and... Agent: Mcginn Intellectual Property Law Group, PLLC

20070063221 - Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon mos transistors: A partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600... Agent: Townsend And Townsend And Crew, LLP

20070063222 - Semiconductor device and method for manufacturing the same: In a semiconductor film having a heterojunction structure, for example a semiconductor film (11) including a SiGe layer (2) and a Si layer (3) formed on the SiGe layer (2), impurity concentration is controlled in such a manner that the concentration of impurity in the lower, SiGe layer (2) becomes... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070063223 - Semiconductor device having pattern-dummy and method for manufacturing the same using pattern-dummy: A semiconductor device includes a main pattern disposed to overlap with an active region that is surrounded by a device isolating region, and the dummy pattern disposed on the device isolating region to be spaced apart from the active region by a predetermined distance. A distance between the dummy pattern... Agent: Townsend And Townsend And Crew, LLP

20070063224 - Metal insulator semiconductor field effect transistor having fin structure: A semiconductor device includes a fin-shaped semiconductor layer, a gate electrode section formed in a widthwise direction of the semiconductor layer with a gate insulation film interposed therebetween, the gate electrode section including a plurality of electrode materials having different work functions and stacked one another, and a channel section... Agent: Foley And Lardner LLP Suite 500

20070063225 - Semiconductor device, and method for manufacturing semiconductor device: A semiconductor device includes a substrate, a fuse that can be blown by the radiation of light formed above the substrate, and insulating films formed on the fuse and on the substrate. One of the insulating films includes a flat portion formed on the substrate and the surface thereof is... Agent: Mcdermott Will & Emery LLP

20070063226 - Laser irradiation apparatus and laser irradiation method: It is an object of the present invention to provide a laser irradiation apparatus and a laser irradiation method which can conduct a laser process homogeneously to the whole surface of a semiconductor film. A laser beam oscillated from a laser crystal having a wide wavelength range and a beam... Agent: Eric Robinson

20070063227 - Transistor and cvd apparatus used to deposit gate insulating film thereof: In a transistor adapted to suppress characteristic degradation resulting from fluorine contained in a deposited film, the concentration of fluorine contained in a gate insulating film (3) is reduced to 1.0×1020 atoms/cm3 or less. As a result, the transistor can provide excellent reliability even when it is continuously driven for... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20070063228 - Thin film transistor, semiconductor device, display, crystallization method, and method of manufacturing thin film transistor: An object of the present invention is to provide a thin film transistor having a high mobility and having fewer fluctuations in the mobility or threshold voltage characteristics. A non-single-crystal semiconductor thin film having a thickness of less than 50 nm and disposed on an insulating substrate is irradiated with... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070063229 - Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area... Agent: Trask Britt, P.C./ Micron Technology

20070063230 - Asymmetrically stressed cmos finfet: A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region over the source region and the drain region and partitioning... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070063231 - Power semiconductor device with integrated passive component: A power semiconductor device that includes a passive component, e.g., a capacitor, mechanically and electrically coupled to at least one pole thereof.... Agent: Ostrolenk Faber Gerb & Soffen

20070063233 - Array substrate and display device having the same: An array substrate includes a base substrate, a plurality of gate lines, a plurality of data lines and a pixel matrix. The plurality of gate lines and the plurality of data lines define pixel areas. The pixel matrix is formed on each pixel area, and includes a plurality of pixel... Agent: F. Chau & Associates, LLC

20070063232 - Solid-state imaging device: An energy ray sensitive region 11 is divided in its horizontal direction into m columns with the vertical direction as the longitudinal direction, divided in its vertical direction into n rows with the horizontal direction as the longitudinal direction, and is thereby provided with m×n photoelectric conversion portions 13 that... Agent: Drinker Biddle & Reath (dc)

20070063234 - Solid-state imaging device, production method thereof and camera: A solid-state imaging device and the production method capable of effectively suppressing color mixture between sensor portions, and a camera provided with the solid-state imaging device are provided: wherein the solid-state imaging device includes a first conductivity type semiconductor substrate, a second conductivity type epitaxial layer formed on the first... Agent: Robert J. Depke Lewis T. Steadman

20070063235 - Cmos image sensor and method of manufacturing the same: In a CMOS image sensor manufacturing process, heavily doped p type impurity ions (for example, B) are implanted in a dummy moat region when the heavily doped p type impurity ions is implanted in a PMOS transistor region, so that metal ion contamination is removed. Accordingly, a CMOS image sensor... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070063237 - Magnetic device having multilayered free ferromagnetic layer: Magnetic multilayer structures, such as magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves, having a magnetic biasing layer formed next to and magnetically coupled to the free ferromagnetic layer to achieve a desired stability against fluctuations caused by, e.g., thermal fluctuations and astray fields. Stable MTJ cells with low... Agent: Fish & Richardson, PC

20070063236 - Magnetic device having stabilized free ferromagnetic layer: Magnetic multilayer structures, such as magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves, having a magnetic biasing layer formed next to and magnetically coupled to the free ferromagnetic layer to achieve a desired stability against fluctuations caused by, e.g., thermal fluctuations and astray fields. Stable MTJ cells with low... Agent: Fish & Richardson, PC

20070063239 - Semiconductor device: A semiconductor device includes: a substrate; a first insulating layer formed on the substrate; a groove formed in the first insulating layer; a barrier layer formed on at least a side surface and a bottom surface of the groove; a second insulating layer formed on the barrier layer; a first... Agent: Harness, Dickey & Pierce, P.L.C

20070063238 - Semiconductor memory and driving method for the same: A semiconductor memory includes a conducting film formed on a substrate; a ferroelectric film formed above or below the conducting film; a source electrode and a drain electrode disposed in positions opposing the conducting film with the ferroelectric film sandwiched therebetween and spaced from each other; and an insulating film... Agent: Mcdermott Will & Emery LLP

20070063242 - High density semiconductor memory and method of making: A memory cell, array and device include cross-shaped active areas and polysilicon gate areas disposed over arm portions of adjacent cross-shaped active areas. The polysilicon gate areas couple word lines with capacitors associated with each arm portion of the cross-shaped active areas. Buried digit lines are coupled to body portions... Agent: Trask Britt, P.C./ Micron Technology

20070063240 - Integrated electronic circuit incorporating a capacitor: An integrated electronic circuit includes electrical connections located in metallization layers superposed on top of a substrate. The circuit further incorporates a capacitor having two plates that are placed in two adjacent metallization layers. Each of the metallization layers containing a capacitor plate further contains electrical connections. The capacitor is... Agent: Jenkens & Gilchrist, PC

20070063241 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a capacitor formed over a semiconductor substrate 10 and including a lower electrode 32, a dielectric film 34 formed over the lower electrode and an upper electrode 36 formed over the dielectric film, a first insulation film 42 formed over the semiconductor substrate and the capacitor,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070063243 - Structure of embedded capacitors and fabrication method thereof: A new structure is provided to replace the existing common planar capacitor structure used in printed circuit boards. The conventional common planar capacitor structure utilizes a single dielectric layer and embedded capacitors with different capacitances are achieved by adjusting the sizes of the embedded capacitors' conductive terminals. Since general applications... Agent: Lin & Associates Intellectual Property, Inc.

20070063245 - Metal plating using seed film: A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each layer of the one or more noble metal layers is no greater than a monolayer. The seed film also includes either one or more... Agent: Mueting, Raasch & Gebhardt, P.A.

20070063244 - Trench metal-insulator-metal (mim) capacitors and method of fabricating same: The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET). The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the... Agent: Scully Scott Murphy & Presser, PC

20070063246 - Solid capacitor and manufacturing method thereof: A solid capacitor and the manufacturing method thereof are disclosed. The solid capacitor consists of a dielectric layer and two electrodes. A plurality of holes formed by an opening process is disposed on surface of the dielectric layer. The two electrodes connect with the dielectric layer by the holes. By... Agent: Rosenberg, Klein & Lee

20070063247 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold... Agent: Harness, Dickey & Pierce, P.L.C

20070063248 - High write and erase efficiency embedded flash cell: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating... Agent: Slater & Matsil, L.L.P.

20070063260 - Floating gate and fabricating method thereof: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on... Agent: Alessandro Steinfl C/o Ladas & Parry

20070063259 - Floating-gate memory cell: A floating-gate memory cell has a tunnel dielectric layer that overlies a silicon-containing semiconductor substrate and that is adjacent a trench formed in the semiconductor substrate. A floating-gate layer, having at least one silicon-containing layer, overlies the tunnel dielectric layer. An intergate dielectric layer overlies the floating-gate layer, and a... Agent: Leffert Jay & Polglaze, P.A.

20070063258 - Isolation trenches for memory devices: Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has... Agent: Leffert Jay & Polglaze, P.A.

20070063252 - Non-volatile memory and sram based on resonant tunneling devices: The present invention discloses a resonant tunneling device. Further, the present invention discloses a memory storage device utilizing a resonant tunneling barrier. Moreover, the present invention teaches an SRAM circuit utilizing a resonant tunneling device. Additionally, the present invention teaches an NROM and NAND device utilizing a resonant tunneling barrier.... Agent: Perkins Coie LLP

20070063255 - Non-volatile memory device and method of manufacturing the same: In non-volatile memory devices and methods of manufacturing the non-volatile memory devices, a barrier layer having an upper portion of silicon nitride and a lower portion of silicon oxide is formed on a substrate by providing a silicon oxide layer on the substrate and performing a radical nitridation process on... Agent: Mills & Onello LLP

20070063254 - Nonvolatile memory device and method for fabricating the same: A nonvolatile memory device including a floating gate formed on a tunnel oxide layer that is formed on a semiconductor substrate. The device also includes a drain region formed in the substrate adjacent to one side of the floating gate, a source region formed in the substrate adjacent to another... Agent: Heong Jin Kim

20070063257 - Nonvolatile memory devices including high-voltage mos transistors with floated drain-side auxiliary gates and methods of fabricating the same: High-voltage MOS transistors with a floated drain-side auxiliary gate are provided. The high-voltage MOS transistors include a source region and a drain region provided in a semiconductor substrate. A main gate electrode is disposed over the semiconductor substrate between the drain region and the source region. A lower drain-side auxiliary... Agent: Mills & Onello LLP

20070063256 - Nonvolatile semiconductor memory device, semiconductor device and method of manufacturing nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed... Agent: Mcdermott Will & Emery LLP

20070063253 - Semiconductor device and method of manufacturing the same: A semiconductor device and a method of manufacturing the same can satisfy a design rule reduction in a peripheral region. The semiconductor device includes a silicon substrate having an activation region formed by recessing a center portion of the silicon substrate lengthwise. A device isolation layer is formed on the... Agent: Ladas & Parry LLP

20070063251 - Semiconductor product including logic, non-volatile memory and volatile memory devices and method for fabrication thereof: A semiconductor product and a method for fabricating the semiconductor product employ a semiconductor substrate. The semiconductor substrate has a logic region having a logic device formed therein, a non-volatile memory region having a non-volatile memory device formed therein and a volatile memory device having a volatile memory device formed... Agent: Tung & Associates

20070063250 - Split gate field effect transistor device with aligned gate electrode sidewalls: A split gate field effect transistor is fabricated with a sidewall of a control gate electrode aligned with a sidewall of a floating gate electrode. The aligned sidewalls are on a side of the split gate field effect transistor device opposite the control gate electrode channel of the split gate... Agent: Thomas, Kayden, Hostemeyer & Risley LLP

20070063249 - Swivel cap for flash memory device: A flash memory device is disclosed. The flash memory device includes a housing enclosing a memory board, a serial port extending from the housing and electrically coupled to the memory board, and a swivel cap rotatably coupled and removably attached to the housing. In this regard, the swivel cap is... Agent: Attention: Eric D. Levinson Imation Corp.

20070063262 - Nand memory arrays: A NAND memory array has a plurality of rows of memory cells and a plurality of columns of NAND strings of memory cells. Each NAND string is selectively connected to a bit line through a drain select gate of the respective column. Each of the drain select gates has a... Agent: Leffert Jay & Polglaze, P.A.

20070063261 - Necked finfet device: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has... Agent: Haynes And Boone, LLP

20070063263 - Non-volatile memory devices and method for forming the same: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are... Agent: Mills & Onello LLP

20070063264 - A non-volatile memory array: A non-volatile memory array including memory units which are arranged in a row/column array is provided. Source lines are arranged in parallel in the column direction and connect to the source regions of the memory units in the same column. Bit lines are arranged in parallel in the row direction... Agent: Jianq Chyun Intellectual Property Office

20070063265 - Non-volatile semiconductor memory devices and methods of fabricating the same: Nonvolatile memory devices and related methods of fabricating nonvolatile memory devices are disclosed. A nonvolatile memory device includes a tunnel insulation film on a semiconductor substrate, a charge-trapping layer on the tunnel insulation film, a block insulation film on the charge-trapping layer, and a gate electrode on the blocking insulation... Agent: Myers Bigel Sibley & Sajovec

20070063267 - Self aligned 1 bit local sonos memory cell: A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer... Agent: Lee & Morse, P.C.

20070063266 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor region; a first high dielectric constant insulating film provided on the semiconductor region, the first high dielectric constant insulating film being a film other than alumina; a second high dielectric constant insulating film provided on the first high dielectric constant insulating film, the second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070063271 - Lateral double-diffused field effect transistor and integrated circuit having same: In a lateral double-diffused field effect transistor of the present invention, a gate insulating film includes a first gate insulating film covering a source diffusion layer up to a region beyond the pattern of a body diffusion layer and a second gate insulating film having a film thickness larger than... Agent: Birch Stewart Kolasch & Birch

20070063268 - Non-volatile memory, and operation and fabrication of the same: A non-volatile memory cell is described, including a semiconductor substrate with a trench therein, a charge-trapping layer in the trench, a gate disposed in the trench and separated from the substrate by at least the charge-trapping layer, and S/D regions in the substrate beside the trench. The gate includes a... Agent: J C Patents, Inc.

20070063272 - Semiconductor power device with insulated gate formed in a trench, and manufacturing process thereof: A semiconductor power device has a semiconductor body with a first conductivity type. A trench extends in the semiconductor body and accommodates an insulating structure, which extends along the side walls and bottom of the trench. The insulating structure surrounds a conductive region, arranged on the bottom of the trench,... Agent: Seed Intellectual Property Law Group PLLC

20070063270 - Transistors including laterally extended active regions and methods of fabricating the same: A transistor includes a substrate and an isolation region disposed in the substrate. The isolation regions defines an active region comprising upper and lower active regions, the upper active region having a first width and the lower active region having a second width greater than the first width. An insulated... Agent: Myers Bigel Sibley & Sajovec

20070063269 - Trench igbt with increased short circuit capability: A trench type IGBT has a gate oxide lining the side walls and bottom of the trench which have a thickness greater than 1500Å and in the range of 1800Å to 2500Å, and preferably 2000Å to increase the device short circuit capability.... Agent: Ostrolenk Faber Gerb & Soffen

20070063273 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a gate insulating film formed on a semiconductor substrate, and a gate electrode formed on the gate insulating film. Nitrogen is introduced into the gate insulating film, and the nitrogen concentration distribution thereof has a peak near the surface of the gate insulating film or near... Agent: Nixon Peabody, LLP

20070063274 - Semiconductor device: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element... Agent: Fish & Richardson P.C.

20070063275 - Semiconductor device and method for fabricating the same: Into a channel formation region of a semiconductor substrate of p-type silicon, indium ions are implanted at an implantation energy of about 70 keV and a dose of about 5×1013/cm2, thereby forming a p-doped channel layer. Next, germanium ions are implanted into the upper portion of the semiconductor substrate at... Agent: Mcdermott Will & Emery LLP

20070063276 - Dense chevron finfet and method of manufacturing same: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal... Agent: Schmeiser, Olsen & Watts

20070063278 - Highly manufacturable sram cells in substrates with hybrid crystal orientation: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially... Agent: Scully Scott Murphy & Presser, PC

20070063279 - Insulation layer for silicon-on-insulator wafer: A method of forming a silicon-on-insulator wafer begins by providing a silicon wafer having a first surface. An ion implantation process is then used to implant oxygen within the silicon wafer to form an oxygen layer that is buried within the silicon wafer, thereby forming a silicon device layer that... Agent: Blakely Sokoloff Taylor & Zafman

20070063277 - Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive current: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i.e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying... Agent: Scully Scott Murphy & Presser, PC

20070063281 - Semiconductor device and manufacturing method thereof, soi substrate and display device using the same, and manufacturing method of the soi substrate: A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si... Agent: Nixon & Vanderhye, PC

20070063282 - Soi-like structures in a bulk semiconductor substrate: Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the... Agent: Slater & Matsil, L.L.P.

20070063280 - Thin film transistor array substrate: A thin film transistor array substrate having a display area and a non-display area is provided. Pixel units, scan lines and data lines are disposed within the display area, and the scan line and data line are electrically connected to the corresponding pixel units. The non-display region has first chip... Agent: J.c. Patents, Inc.

20070063283 - Thin film transistor, liquid crystal display using thin film transistor, and method of manufacturing thin film transistor: A semiconductor film, which is located over a gate electrode for forming a channel region between a source electrode and a drain electrode, has a width greater than a width of the source electrode and a width of the drain electrode located over the gate electrode. Irregularities are formed in... Agent: Mcginn Intellectual Property Law Group, PLLC

20070063284 - Semiconductor device and semiconductor integrated circuit using the same: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used... Agent: Miles & Stockbridge PC

20070063285 - Power supply apparatus: In a power supply apparatus in which a source of a MOSFET is connected to a node of a rectifier diode and a choke coil through a resonance coil, a series circuit including a capacitor and a MOSFET i s connected to a series circuit including the resonance coil and... Agent: Ostrolenk Faber Gerb & Soffen

20070063286 - Semiconductor device and method for manufacturing the same: In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS... Agent: Mcdermott Will & Emery LLP

20070063287 - Semiconductor device: To achieve a stable reading operation in a memory cell having a gain-cell structure, a write transistor is configured, which has a source and a drain that are formed on the insulating layer, a channel formed on the insulating layer and between the source and the drain and made of... Agent: Miles & Stockbridge PC

20070063288 - Semiconductor device: A semiconductor device according to an embodiment of the invention includes: a plurality of field effect transistors; and a plurality of logic circuits composed of the field effect transistors, the field effect transistors each including: first and second drain regions formed away from each other; at least one source region... Agent: Foley And Lardner LLP Suite 500

20070063289 - Semiconductor circuit device and display data line driver: An N-type diffusion layer fixed at a potential equal to or above 0V is provided in a segregating region between terminals, and a P-type diffusion layer having a potential equal to that of the N-type diffusion layer on an N-type well constitute a drain of a transistor.... Agent: Mcdermott Will & Emery LLP

20070063290 - Metal oxide semiconductor transistor: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate... Agent: Jianq Chyun Intellectual Property Office

20070063291 - Semiconductor device with dummy electrode: A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact portion extending, when viewed from above, parallel to the... Agent: Mcdermott Will & Emery LLP

20070063292 - Semiconductor apparatus integrating an electrical device under an electrode pad: A semiconductor apparatus includes a device, two metal-wiring layers, and an insulation film. The device includes first and second electrodes. The two metal-wiring layers include uppermost and next-uppermost metal-wiring layers. The insulation film is formed on the uppermost metal-wiring layer and includes first and second pad openings. The uppermost metal-wiring... Agent: Cooper & Dunham, LLP

20070063293 - Semiconductor device: A semiconductor device that can prevent an unnecessary current path from being formed so that a normal signal is transmitted is provided. The semiconductor device comprises an N− region formed in a surface region of a P type substrate, a P region formed in the surface region, the P region... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070063294 - Semiconductor device having a fully silicided gate electrode and method of manufacture therefor: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located... Agent: Texas Instruments Incorporated

20070063295 - Gate electrode, method of forming the same, transistor having the gate electrode, method of manufacturing the same, semiconductor device having the gate electrode and method of manufacturing the same: Example embodiments relate to a gate electrode, a method of forming the gate electrode, a transistor having the gate electrode, a method of manufacturing the transistor, a semiconductor device having the transistor and a method of manufacturing the semiconductor device. The gate electrode may include an embossing structure including a... Agent: Harness, Dickey & Pierce, P.L.C

20070063296 - Methods of modulating the work functions of film layers: Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where the second metal layer modulated the work function of... Agent: Fulbright & Jaworski L.L.P.

20070063297 - Displacement detection device: In a displacement detection device having an IC chip for a regulation plate, silicon broken pieces might drop from loose chippings during assembling or using the device and affect properties of the displacement detection device. By setting an angle of grinding traces on an IC chip wafer of chip with... Agent: Sughrue Mion, PLLC

20070063298 - Magneto-resistance transistor and method thereof: A magneto-resistance transistor including a magneto-resistant element which may function as an emitter and a passive element which may function as a collector. The base may be interposed between the passive element and the magneto-resistant element, thereby coupling the passive element with the magneto-resistant element. A magnetic field of a... Agent: Rabin & Berdo, PC

20070063300 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are provided. The CMOS Image sensor includes a semiconductor substrate having a photodiode and transistors. An interlayer insulating layer is formed on the entire surface of the semiconductor substrate. First, second, and third color filter layers are formed at... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070063299 - Cmos image sensor and method of manufacturing the same: A CMOS image sensor and a method of manufacturing the same, in which photodiodes of different colors have different depths considering the penetration depth of light into a silicon lattice structure, may also improve characteristics of the image sensor. The CMOS image sensor includes a second conductivity type blue photodiode... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070063301 - Barrier regions for image sensors: Embodiments of the invention provide an image sensor that includes a barrier region for isolating devices. The image sensor comprises a substrate and an array of pixel cells formed on the substrate. Each pixel cell comprises a photo-conversion device. The array comprises a first pixel cell having a first configuration,... Agent: Dickstein Shapiro LLP

20070063302 - Electronic assembly that includes pads having a bowl shaped upper section: Some embodiments relate to an electronic assembly that includes a substrate and a plurality of pads. Each of the pads includes a lower section that is embedded in the substrate and a bowl-shaped upper section that is on top of the lower section. The bowl-shaped upper section protrudes from the... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070063303 - Cmos image sensor and method for manufacturing the same: Provided are a CMOS image sensor and a manufacturing method thereof. The CMOS image sensor includes a gate insulating layer and a gate electrode, a low-density diffusion region of a second conductive type, a high-density diffusion region of the second conductive type, and a high-density diffusion region of a first... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070063304 - Field-effect transistor, single-electron transistor and sensor using the same: o

20070063305 - Ignition circuit: A component formed in a substrate of a first conductivity type, having two inputs and two outputs and: a first diode having its anode connected to a first input and having its cathode connected to a first output; a second diode having its anode connected to a second output and... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070063306 - Multiple crystal orientations on the same substrate: Embodiments of the invention provide a substrate with a surface having different crystal orientations in different areas. Embodiments of the invention provide a substrate with a portion having a <100> crystal orientation and another portion having a <110> crystal orientation. N— and P-type devices may both be formed on the... Agent: Intel Corporation C/o Intellevate, LLC

20070063307 - Semiconductor device including power mos field-effect transistor and driver circuit driving thereof: A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070063308 - Integrated circuit with partly silicidated silicon layer: The integrated circuit (1) comprises an electric device (2) such as a resistor which comprises a first silicon layer (120) having a silicidated part (122) and a non-silicidated part (123), and a further electric device (3) such as, e.g. a capacitor, a field effect transistor or a non-volatile memory gate... Agent: Philips Intellectual Property & Standards

20070063309 - Integrated circuitry and method for manufacturing the same: The integrated circuitry on a semiconductor substrate includes an integrated circuit arranged in a circuit area of the semiconductor substrate and a stress-sensitive structure on the semiconductor substrate for detecting a mechanical stress component in the semiconductor substrate, wherein the stress-sensitive structure is implemented to provide an output signal depending... Agent: Baker Botts, L.L.P.

20070063310 - A metal fuse for semiconductor devices and methods of manufacturing thereof: Described is a metal fuse in a semiconductor device that can be readily blown up without compromising device reliability, as well as methods of manufacturing thereof. In one embodiment, a metal fuse structure according to the disclosed principles comprises a semiconductor substrate, and an interconnect layers located on the semiconductor... Agent: Baker & Mckenzie On Behalf Of Tsmc

20070063313 - Electronic circuit arrangement: An electronic circuit arrangement has a substrate which has at least one metallization layer. At least one electrical interconnect and/or at least one via are formed in the metallization layer such that the electrical interconnect and the via are in the form of an electrical fuse link. In addition, the... Agent: Brinks Hofer Gilson & Lione Infineon

20070063311 - Rewiring substrate strip having a plurality of semiconductor component positions: A rewiring substrate strip (100) has a plurality of semiconductor component positions (2) for semiconductor components (3). The semiconductor component positions are arranged in rows and columns. A plurality of semiconductor component positions (2) can be combined to form a component group (5). The semiconductor components (3) of a component... Agent: Baker Botts, L.L.P.

20070063312 - Semiconductor device having fuse element: In a semiconductor device including a switching element and a fuse element which is connected in series with the switching element and which melts and blows out as a result of an electric current flowing therethrough when the switching element is placed in an electrically conducting state, in which an... Agent: Cantor Colburn, LLP

20070063314 - Integrated circuit bipolar transistor: A bipolar transistor having a base region resting by its lower surface on a collector region and surrounded with a first insulating layer, a base contact conductive region in contact with an external upper peripheral region of the base region, a second insulating region in contact with an intermediary upper... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070063315 - Semiconductor integrated circuit device and process for manufacturing the same: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070063316 - Flip chip semiconductor device and process of its manufacture: A semiconductor die and method of making it are provided. The die includes a first via extending through the entire thickness of the die and a first via electrode disposed inside the via electrically connecting an electrode at a top surface of the die with another electrode disposed at a... Agent: Ostrolenk Faber Gerb & Soffen

20070063317 - Overlay key, method of forming the overlay key, semiconductor device including the overlay key and method of manufacturing the semiconductor device: An overlay key formed in a scribe lane and used to align a circuit pattern may include a lower overlay mark formed on a metal silicide layer directly in contact with a silicon substrate. A method of forming an overlay key in a scribe lane may include providing a silicon... Agent: Harness, Dickey & Pierce, P.L.C

20070063318 - Semiconductor device for bonding connection: An arrangement is employed in a semiconductor device having a semiconductor body, the semiconductor body having a surface. The arrangement includes a surface portion on which a first metallization layer is arranged, and an alignment pattern arranged between the surface portion and the first metallization layer.... Agent: Maginot, Moore & Beck Chase Tower

20070063319 - Film stack and method for fabricating the same: A film stack and a method for fabricating the same. In one embodiment, a film stack comprises a semiconductor substrate with the following layers: a first layer of oxide over the substrate; a first layer of polycrystalline silicon over the first layer of oxide; a second layer of oxide over... Agent: Schneck & Schneck

20070063320 - Integrated circuit package system with adhesive restraint: An integrated circuit package system including an integrated circuit die and a lead frame with a trenched die pad. The integrated circuit die is mounted to the trenched die pad.... Agent: Ishimaru & Zahrt LLP

20070063321 - Light emitting diode package and light emitting diode system having at least two heat sinks: There is provided a light emitting diode package having at least two heat sinks. The light emitting diode package includes a main body, at least two lead terminals fixed to the main body, and at least two heat sinks of electrically and thermally conductive materials, the heat sinks being fixed... Agent: Mcdermott Will & Emery LLP

20070063325 - Chip package structure and bumping process: A chip package structure including a first substrate, a second substrate, bumps and adhesive blocks is provided. The first substrate has first bonding pads. The second substrate is disposed above the first substrate and has second bonding pads. The bumps are respectively arranged on the first bonding pads or the... Agent: J.c. Patents

20070063322 - Integrated circuit protruding pad package system: An integrated circuit package system is provided. A protruding pad is formed on a leadframe. A die is attached to the leadframe. The die is electrically connected to the leadframe. At least portions of the leadframe, the protruding pad, and the die are encapsulated in an encapsulant.... Agent: Ishimaru & Zahrt LLP

20070063323 - Led positioning structure: An improved LED positioning structure includes a retaining holder and a cover; multiple slots being disposed on one side of the retaining holder; a slope externally extending beneath each slot gradually and externally extending a slope; a hole connecting through each slot being formed on the bottom of the slope;... Agent: Troxell Law Office PLLC

20070063326 - Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area... Agent: Trask Britt, P.C./ Micron Technology

20070063327 - Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area... Agent: Trask Britt, P.C./ Micron Technology

20070063328 - Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area... Agent: Trask Britt, P.C./ Micron Technology

20070063324 - Structure and method for reducing warp of substrate: A warp reducing member is bonded to an area on one surface of the substrate corresponding to other side of an electronic part for which the warp is to be reduced with respect to a substrate. An external size of the warp reducing member is substantially same as a size... Agent: Arent Fox PLLC

20070063329 - Structure of memory card packaging and method of forming the same: A structure and a method for a memory card are provided, including a circuit substrate and an encapsulating case. The substrate is completed with chips and circuit connected, and is stamped on the circumferential borders to form a plurality of ribs or gaps. The case is formed by a burying... Agent: Jason Z. Lin Lin & Associates

20070063332 - Bga package with stacked semiconductor chips and method of manufacturing the same: A package with two or more stacked semiconductor chips and a method of manufacturing the same. In the method, an upper semiconductor chip package and a lower semiconductor chip package are prepared. Solder balls are formed on a substrate of the lower package to connect the upper and lower packages.... Agent: Harness, Dickey & Pierce, P.L.C

20070063330 - Complex laminated chip element: The present invention relates to a laminated chip element which can be manufactured to have desired electric properties by combining various elements in accordance with the desired objectives. More particularly, the present invention relates to a laminated chip element which has superior high frequency properties and can be manufactured to... Agent: Marger Johnson & Mccollom, P.C.

20070063331 - Integrated circuit package system with planar interconnects: An integrated circuit package system is provided including forming a first substrate, mounting a first integrated circuit to the first substrate, and forming first planar interconnects in contact with the first integrated circuit and electrically connecting the first integrated circuit to the first substrate.... Agent: Ishimaru & Zahrt LLP

20070063335 - Packaged microelectronic devices with interconnecting units and methods for manufacturing and using the interconnecting units: Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the invention, a packaged microelectronic device assembly includes a microelectronic die, a substrate attached to the die, a protective casing covering a portion of the substrate, and a... Agent: Perkins Coie LLP Patent-sea

20070063334 - Semiconductor device: In order to minimize a distance from a power supply line and/or a ground line of a semiconductor integrated circuit of a semiconductor device to electrodes of a printed board, at least either a power supply electrode or the ground line of the semiconductor integrated circuit is connected to a... Agent: Sughrue Mion, PLLC

20070063333 - Semiconductor package with internal shunt resistor: According to an embodiment of the invention, a semiconductor package has been provided that includes a die, a first lead pad, a second lead pad, a circuit component, a first wire bond, and a second wire bond. The die is supported on a die pad. The circuit component has a... Agent: Texas Instruments Incorporated

20070063336 - Qfn/son-compatible package: A leadless package and method for manufacturing silicon based leadless QFN/SON compatible packages are described. In addition the package allows for hermetic sealing of devices while maintaining electrical and optical access. Micro-vias with feed-through metallization through a silicon structure facilitates a surface mount technology-compatible silicon package with bottom SMT pads... Agent: Fish & Richardson P.C.

20070063338 - Bottom lighting type backlight module: A bottom lighting type backlight module includes a frame, a light diffusion plate and a plurality of light sources. The frame includes a base and a plurality of sidewalls extending from the peripheral of the base to define an opening. The base defines a plurality of heat dissipation channels therein.... Agent: Morris Manning Martin LLP

20070063337 - Chip cooling system: A chip cooling system including a semiconductor device having a bulk region, wherein at least one fluid channel extends at least partially through the bulk region, the fluid channel having an inlet and an outlet, a fluid inlet port in fluid communication with the channel inlet, and a fluid outlet... Agent: Delphi Technologies, Inc.

20070063339 - Heat dissipating assembly for heat dissipating substrate and application: In a heat dissipating assembly for heat dissipating substrate and application, a heat dissipating substrate is made of a graphite layer and a thermal conductive metal layer covered onto the surface of the graphite layer, so that when the heat dissipating substrate is placed on a heat source, the graphite... Agent: Bacon & Thomas, PLLC

20070063340 - Complete power management system implemented in a single surface mount package: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor... Agent: Wagner, Murabito & Hao LLP

20070063341 - Complete power management system implemented in a single surface mount package: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor... Agent: Vishay/siliconix C/o Wagner, Murabito & Hao LLP

20070063342 - System, method and apparatus for improved electrical-to-optical transmitters disposed within printed circuit boards: The present invention provides a system, method and apparatus for improved electrical-to-optical transmitters (100) disposed within printed circuit boards (104). The heat sink (110, 200) is a thermal conductive material disposed within a cavity (102) of the printed circuit board (104) and is thermally coupled to a bottom surface (112)... Agent: Chalker Flores, LLP

20070063343 - Substrate for semiconductor device and semiconductor device: The present invention provides to a substrate for a semiconductor device, in which electric characteristics to high-speed signals are enhanced by facilitating the mounting of a circuit component, such as a decoupling capacitor, fabricated separately from the substrate. The substrate (30) for a semiconductor device, on which the circuit component... Agent: Birch Stewart Kolasch & Birch

20070063344 - Chip package structure and bumping process: A chip package structure including a first substrate, a second substrate, bumps and adhesive blocks is provided. The first substrate has first bonding pads. The second substrate is disposed above the first substrate and has second bonding pads. The bumps are respectively arranged on the first bonding pads or the... Agent: J C Patents, Inc.

20070063346 - Display device and manufacturing method of the same: A display device includes a drive circuit chip, and a substrate on which the drive circuit chip is mounted. The drive circuit chip includes a semiconductor substrate, an insulation layer, a first conductive layer and a second conductive layer formed of metal between the semiconductor substrate and the insulation layer,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070063345 - Semiconductor device: A semiconductor device including: a semiconductor chip; a plurality of electrodes formed on the semiconductor chip and arranged along one side of the semiconductor chip; a resin protrusion formed on the semiconductor chip and extending in a direction which intersects the side; and a plurality of electrical connection sections formed... Agent: Harness, Dickey & Pierce, P.L.C

20070063347 - Packages, anisotropic conductive films, and conductive particles utilized therein: Packages, anisotropic conductive films, and conductive particles utilized therein. One embodiment of the package includes a substrate, a chip, and an anisotropic conductive film. The substrate comprises an external terminal. The chip comprises a conductive bump overlying the external terminal of the substrate. The anisotropic conductive film is disposed between... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070063348 - Method and structure of forming an interconnect including a dielectric cap having a tensile stress: An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to... Agent: International Business Machines Corporation Dept. 18g

20070063349 - Interconnect structure and method of manufacturing the same: The invention is directed to a method for manufacturing an interconnect structure suitable for a substrate having a semiconductor device formed thereon, wherein the semiconductor device possesses a metal silicide layer predetermined as an electrically connecting region. The method comprises steps of forming a conformal adhesion layer over the substrate,... Agent: J C Patents, Inc.

20070063351 - Method for the application of a protective coating to a thermally stressed component: A method for applying a heat insulation layer (11, 12, 13) or a metallic protective layer to a thermally stressed component (200) having a basic material (10) in order to eliminate local damage (14) or an untreated place in the coating, includes, in a first step, pretreating the local damage... Agent: Cermak & Kenealy LLP

20070063350 - Semiconductor device and method for designing same: A silica residue is generated, due to a presence of a step formed by a presence of the first layer metallic interconnect, and then, the residual silica is etched to form hollow portions when vias for the metallic interconnect provided in a layer above thereof is formed, and further, insulating... Agent: Sughrue Mion, PLLC

20070063352 - Routing under bond pad for the replacement of an interconnect layer: The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization... Agent: Hitt Gaines, PC Agere Systems Inc.

20070063353 - Partially bonding structure for a polymer and a chip: The present invention provides a partially bonding structure for a Polymer and a chip, comprising a substrate, a metal layer and a Polymer. The Polymer includes the characters, such as high uniformity, good flexibility, different hydrophilicity, low stress, low melting point, and high hermeticity, to be applied to the standard... Agent: John Chen

20070063354 - Wire sweep resistant semiconductor package and manufacturing method thereof: A method for manufacturing a wire sweep resistant semiconductor package provides a die attached to an interposer. The die is electrically connected to the interposer with conductive wires. A sealant is applied on the die at the conductive wires for preventing wire sweep and the sealant is free of contact... Agent: Ishimaru & Zahrt LLP

20070063355 - Multilayer circuit board and production method for same: In a multilayer circuit board of the present invention, a plurality of circuit substrates configured by forming a circuit pattern on an insulating base material are stacked via an insulating layer, a through-hole and a via hole are formed in the layering direction, and laser processability and laser processing speed... Agent: Birch Stewart Kolasch & Birch

20070063356 - Method of fabricating sram device: A method of fabricating an SRAM device is provided, by which a junction node area is stably secured in a 1T type SRAM device. The method includes forming first and second conductor patterns on a cell area of a semiconductor substrate and a third conductor pattern on a periphery area... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070057245 - Artificial band gap: A method is disclosed for the induction of a suitable band gap and electron emissive properties into a substance, in which the substrate is provided with a surface structure corresponding to the interference of electron waves. Lithographic or similar techniques are used, either directly onto a metal mounted on the... Agent: Borealis Technical Limited

20070057246 - Heterojunction bipolar transistor with improved current gain: One aspect of the present invention is directed to a heterojunction bipolar transistor (HBT) comprising: a substrate; a buffer layer of undoped semiconductor material; a sub-collector layer; a collector layer; a base layer; an emitter layer; a emitter cap layer; and a contact layer; wherein a planar doping sheet is... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20070057247 - Versatile system for charge dissipation in the formation of semiconductor device structures: The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first... Agent: Texas Instruments Incorporated

20070057248 - Superlattice nano-device and method for making same: A nanodevice (1) for a desired function includes a substrate (11), a one-dimensional nanostructure (12), a functional layer (20) having a desired function, a conductive thin film electrode (30), and an insulating layer (40). The one-dimensional nanostructure is operatively extends from the substrate. The functional layer is surrounds at least... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070057249 - Semiconductor light emitting device with lateral current injection in the light emitting region: A semiconductor light emitting device includes an active region, an n-type region, and a p-type region comprising a portion that extends into the active region. The active region may include multiple quantum wells separated by barrier layers, and the p-type extension penetrates at least one of the quantum well layers.... Agent: Patent Law Group LLP

20070057253 - Antireflective hard mask compositions: The invention includes new organic-containing compositions that can finction as. an antireflective layer for an overcoated photoresist. Compositions of the invention also can serve effectively as a hard mask layer by exhibiting a sufficient plasma etch selectivity from an undercoated layer. Preferred compositions of the invention have a high Si... Agent: Rohm And Haas Electronic Materials LLC

20070057250 - Light-emitting device, organic compound and display: There are provided an organic light-emitting device having a light output of a high emission efficiency and a high luminance and having high durability and a novel organic compound that enables the device to be attained. An organic compound of a long fluorescence lifetime represented by an organic compound having,... Agent: Fitzpatrick Cella Harper & Scinto

20070057255 - Nanomaterials with tetrazole-based removable stabilizing agents: Nanoparticles coated with tetrazole and methods for preparing them are provided. The nanoparticles can be coated onto a substrate and used in fabricating devices such as field effect transistors, switches, sensors, solar cells and spring exchange magnets.... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown Cases)

20070057254 - Organic semiconductor film, organic semiconductor element and organic electroluminescence element: The present invention provides an organic semiconductor thin film sandwiched between a pair of electrodes, wherein a composition constituting this thin film does not substantially have a localized level between the highest occupied molecular orbit (HOMO) and the lowest unoccupied molecular orbit (LUMO) of the composition.... Agent: Birch Stewart Kolasch & Birch

20070057252 - Organic thin film transistor with contact hole and method for fabricating the same: The present invention provides a method for fabricating an organic thin film transistor (OTFT) device where a vertical contact hole is produced in the insulating layer and the passivation layer thereof, so that the respective devices located below and above the OTFT would be electrically connected with each other. The... Agent: Michael W. Taylor

20070057251 - Pixel structure: A pixel structure including a control unit, an organic electro-luminescent (OEL) unit, and a filter structure is provided. The control unit is disposed on a substrate and is driven by a scan line and a data line. The OEL unit is disposed on the substrate, and includes a transparent electrode,... Agent: Jianq Chyun Intellectual Property Office

20070057256 - Element forming substrate, active matrix substrate, and method of manufacturing the same: An element forming substrate includes a substrate and a plurality of elements which are arranged in a matrix form on the substrate. Each of the elements includes a thin film transistor and contact pads connected to the transistor, and has peripheral sides separated from adjacent elements in a plane of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070057257 - Liquid crystal display: A liquid crystal display includes a substrate, a plurality of gate lines formed on the substrate, a plurality of data lines intersecting the plurality of gate lines, a plurality of thin film transistors connected to the plurality of gate lines and the plurality of data lines, and a plurality of... Agent: F. Chau & Associates, LLC

20070057258 - Display device and method for manufacturing the same: According to one aspect of the present invention, at least one or more of patterns required for manufacturing a display device, such as a conductive layer which forms a wiring or an electrode and a mask, is formed by a droplet discharging method. At that time, a portion of the... Agent: Nixon Peabody, LLP

20070057259 - Three-terminal switch array, three-terminal switch array device, combined semiconductor device, and image form appartus: An array of three-terminal switching elements such as light-emitting thyristors is formed from a thin semiconductor film. A combined semiconductor device may be formed by bonding the thin-film three-terminal switching elements to a major surface or edge surface of an integrated circuit chip including a shift register that shifts data... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070057260 - Transflective liquid crystal display device and method of fabricating the same: An array substrate for a transflective liquid crystal display device includes: a substrate; a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area;... Agent: Jenkens & Gilchrist, P.C.

20070057262 - Semicoductor device and manufacturing method thereof: In a semiconductor device having SiC vertical trench MOSFETs, it is aimed to prevent the generation of large scattering in the channel resistance without largely increasing the average value of channel resistance. A 4H-SiC substrate having a major face thereof that is generally a {0001} face and having an off... Agent: Rossi, Kimms & Mcdowell LLP.

20070057261 - Transparent thin film transistor (tft) and its method of manufacture: A transparent thin film transistor (TFT) and its method of manufacture includes: a substrate, a transparent semiconductor layer formed by coating the substrate with an oxide, a nitride, or a carbide to pattern the material, a gate insulating layer formed on the transparent semiconductor layer, a gate electrode formed on... Agent: Robert E. Bushnell

20070057263 - Quantum dot light emitting layer: An inorganic light emitting layer having a plurality of light emitting cores, each core having a semiconductor material that emits light in response to recombination of holes and electrons, each such light emitting core defining a first bandgap; a plurality of semiconductor shells formed respectively about the light emitting cores... Agent: Pamela R. Crocker Patent Legal Staff

20070057264 - Display unit and method for fabricating the same: A display unit and method of fabricating same are provided. The display unit includes a plurality of organic electroluminescent devices, each including an organic layer portion including at least a hole-transport layer and a luminescent layer which are stacked each other, and two electrodes sandwiching the organic layer portion. The... Agent: Bell, Boyd & Lloyd, LLP

20070057265 - Emitter, manufacturing method and manufacturing apparatus thereof, electro-optical apparatus and electronic apparatus: An emitter has a plurality of type of light-emitting units with different changes in emission chracteristics over time. In addition, the emitter includes a deterioration adjustment device which adjusts the deterioration of the emission characteristics over time in a predetermined type of light-emitting unit. The light-emitting units respectvely include a... Agent: Harness, Dickey & Pierce, P.L.C

20070057266 - Light emitting diode with diffraction lattice: A method of fabricating light emitting diodes (LED) with a colour purifying diffraction lattice (CPDL) is suggested, the essence of the invention is in the use of the coherent scattering of the light by the CPDL for colour purifying of the light emitted by the LED and enhancement its extraction... Agent: Rosenberg, Klein & Lee

20070057267 - Led array cooling system: A LED array cooling system including a LED array and a substrate attached to the LED array wherein the LED array includes a plurality of walls that at least in part define a plurality of passages through the LED array.... Agent: Delphi Technologies, Inc.

20070057268 - Lens-attached ligh-emitting element and method for manufacturing the same: A lens-attached light-emitting element having an improved optical availability efficiency includes a composite lens provided on an approximately U-shaped light-emitting area of the light emitting element array. Four spherical lenses are arranged in such a manner that each is centered in the neighborhood the an end of a respective one... Agent: Ratnerprestia

20070057269 - Phosphor, semiconductor light emitting device, and fabrication method thereof: A phosphor that emits white light due to excitation by a light emitting diode capable of emitting blue or ultraviolet light includes: a substrate that allows transmission of visible light; and a semiconductor layer formed on the substrate.... Agent: Greenblum & Bernstein, P.L.C

20070057273 - Diode having vertical structure and method of manufacturing the same: A light emitting diode includes a conductive layer, an n-GaN layer on the conductive layer, an active layer on the n-GaN layer, a p-GaN layer on the active layer, and a p-electrode on the p-GaN layer. The conductive layer is an n-electrode.... Agent: Mckenna Long & Aldridge LLP

20070057272 - Gallium nitride-based semiconductor light emitting device and process for its production: It is an object of the present invention to inhibit exposure of Ag in Ag-employing reflective electrodes caused by microdefects generated during the manufacturing process, and to prevent reduction in light emission output and deterioration in current-voltage characteristics resulting from shorting of the light emitting device. The semiconductor light emitting... Agent: Sughrue Mion, PLLC

20070057270 - Gan laser with refractory metal elog masks for intracavity contact: Refractory metal ELOG mask are used for GaN based VCSELs and edge emitter structures to serve as intracavity contacts. In these structures the refractory metal ELOG masks serve both as ohmic contact metals as well as masks for ELOG.... Agent: Avago Technologies, Ltd.

20070057271 - Interconnects for semiconductor light emitting devices: A semiconductor light emitting device including a light emitting layer disposed between an n-type region and a p-type region and contacts electrically connected to the n-type region and the p-type region is connected to a mount. A metal layer arbitrarily patterned to cover at least 20% of the area of... Agent: Patent Law Group LLP

20070057274 - White-light luminescent silicon-nitride component with silicon quantum dots and fabricating method thereof: The present invention provides a luminescent component with silicon quantum dots and its fabricating method, where the luminescent component includes a light-emitting device of high luminescent efficiency, large-area luminescence, cheap raw material and low producing cost.... Agent: Troxell Law Office PLLC Suite 1404

20070057276 - Nitride semiconductor growth method, nitride semiconductor substrate, and nitride semiconductor device: A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of... Agent: Sughrue Mion, PLLC

20070057275 - Vertical light-emitting diode and method for manufacturing the same: A vertical light-emitting diode and a method for manufacturing the same are described. In the method for manufacturing the vertical light-emitting diode, a sapphire substrate is provided. An illuminant epitaxial structure is formed on the sapphire substrate. Next, a first conductivity type electrode is formed on a surface of the... Agent: Daniel B. Schein

20070057277 - Tunneling gap diodes: The present invention discloses a tunneling diode having a band gap material as the collector. This increases the tunneling of electrons having greater energy than the Fermi level from emitter to collector, leading to an increase in the efficiency of heat pumping or power generation by the diode. This approach... Agent: Borealis Techincal Limited

20070057278 - Magnetic switching element and signal processing device using the same: A magnetic switching element according to an example of the present invention includes a magnetic element, first and second electrodes which put the magnetic element therebetween, a current control section which is connected to the first and second electrodes, the current control section controlling a magnetization direction of a magnetization... Agent: Nixon & Vanderhye, PC

20070057279 - Light-emitting element having pnpn-structure and light-emitting element array: A light-emitting element including a light-emitting thyristor and a Schottky barrier diode is provided. A Schottky barrier diode is formed by contacting a metal terminal to a gate layer of a three-terminal light-emitting thyristor consisting of a PNPN-structure. A self-scanning light-emitting element array may be driven at 3.0V by using... Agent: Ratnerprestia

20070057280 - Semiconductor device: A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring... Agent: Harness, Dickey & Pierce, P.L.C

20070057281 - Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection: An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active... Agent: Texas Instruments Incorporated

20070057282 - Semiconductor light-emitting device: A semiconductor light-emitting device includes: a substrate; a first conductivity type layer formed on the substrate and including a plurality of group III-V nitride semiconductor layers of a first conductivity type; an active layer formed on the first conductivity type layer; and a second conductivity type layer formed on the... Agent: Mcdermott Will & Emery LLP

20070057283 - Fed control circuit: There are provided a cathode voltage control unit 10 which controls a cathode electrode so as to uniform electron emission from the cathode electrode and a gate electrode driving unit 12 which changes a voltage of the gate electrode in response to video signals. The cathode voltage control unit 10... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070057284 - Double-sided package for power module: An electronic semiconductor package is described. The package has a wide band gap electronic semiconductor device requiring heat removal. On one side of the electronic semiconductor device is a first, thermally-conductive, electrically-insulative substrate having a predetermined electrically-conductive wire pattern affixed thereto. On the other side of the electronic semiconductor device... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20070057286 - Solid-state imaging device and method for producing the same: A method for producing a solid-state imaging device, which including: a photoelectric conversion section; a charge transfer section having a charge transfer electrode; and an antireflection film covering a light-receiving region in the photoelectric conversion section, wherein forming the antireflection film includes: forming a sidewall on a lateral wall of... Agent: Birch Stewart Kolasch & Birch

20070057285 - Wurtzite thin film, laminate containing wurtzite crystalline layer and their manufacturing methods: According to the present invention, a thin film made of a wurtzite structure compound is manufactured by a reactive sputtering using a metal material as a target, and a nitrogen gas or an oxygen gas as a reactive gas. By optimizing film-forming conditions when manufacturing the film, it is possible... Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP

20070057287 - Embedded sige stressor with tensile strain for nmos current enhancement: MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has... Agent: Slater & Matsil, L.L.P.

20070057288 - Methods of fabricating semiconductor devices with enlarged recessed gate electrodes: A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion.... Agent: Myers Bigel Sibley & Sajovec

20070057289 - Power semiconductor device and method therefor: The present invention relates to a new kind of foil bearing. The present invention relates to a bearing comprising a flexible foil with a self-aligning mechanism. The present invention furthermore relates to a foil bearing enabling a linear and/or rotary movement along/around an axis (i.e. a shaft). The present invention... Agent: Hvvi Semiconductors, Inc.

20070057290 - Field effect transistor: An object of the present invention is to provide a normally-off type field effect transistor which includes: a first semiconductor layer which is made of a first hexagonal crystal with 6 mm symmetry and has a main surface including a C-axis of the first hexagonal crystal; a second semiconductor layer... Agent: Greenblum & Bernstein, P.L.C

20070057291 - Reference voltage generation circuit, and constant voltage circuit using the reference voltage generation circuit: A reference voltage generation circuit includes: a first field-effect transistor that is an n channel-type field-effect transistor of a depletion-type, wherein one terminal of the first field-effect transistor is connected to a predetermined power source voltage; a second field-effect transistor including a concentrated n-type gate, wherein one terminal of the... Agent: Cooper & Dunham, LLP

20070057292 - Sonos type non-volatile semiconductor devices and methods of forming the same: A SONOS type non-volatile semiconductor device includes a semiconductor substrate, source/drain regions doped with impurities formed in the semiconductor substrate, a channel region formed in the semiconductor substrate between the source/drain regions, a tunnel insulation layer formed on the channel region, a charge-trapping layer formed on the tunnel insulation layer,... Agent: Myers Bigel Sibley & Sajovec

20070057293 - Ultra high voltage mos transistor device: An ultra high voltage MOS transistor device includes a substrate of a first conductivity type; a source region of a second conductivity type formed in the substrate; a first doping region of the first conductivity type formed in the substrate and bordering upon the source region; a first ion well... Agent: North America Intellectual Property Corporation

20070057294 - Current-scaling active thin film transistor circuit structure for pixel of display device: An active TFT circuit structure with current scaling function is disclosed, which includes a current source, a data line, a scan line, a direct current voltage source, capacitors and four transistors, wherein the capacitors form a cascade structure. During the ON-state, the two of the transistors are turn-on based on... Agent: Bacon & Thomas, PLLC

20070057295 - Substrate bonding method and apparatus: A substrate bonding apparatus and a substrate bonding method apply pressure according to the size of upper and lower substrates when the upper and lower substrates are bonded. The apparatus includes: an upper pressing unit having an upper plate to press an upper substrate, and a first presser to drive... Agent: Robert E. Bushnell

20070057297 - Liquid crystal display and driving method thereof: A liquid crystal display (“LCD”) includes a plurality of pixels, each including first and second liquid crystal capacitors, a first storage capacitor including a first terminal connected to the second liquid crystal capacitor and a second terminal applied with a first storage electrode signal, a second storage capacitor including a... Agent: Cantor Colburn, LLP

20070057296 - Voltage-controlled amplifier for a signal processing system: A voltage-controlled amplifier for a signal processing system includes an input voltage reception end, a first voltage-to-current converter, a reference current generator, a gain adjustment circuit, a first current mirror, and an output circuit. The voltage-controlled amplifier adjusts a gain according to a variable control voltage, so as to transfer... Agent: North America Intellectual Property Corporation

20070057298 - Pixel with strained silicon layer for improving carrier mobility and blue response in imagers: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.... Agent: Dickstein Shapiro LLP

20070057299 - Systems and methods having a metal-semiconductor-metal (msm) photodetector with buried oxide layer: Described herein is an MSM photodetector device wherein a dielectric layer is positioned between the absorbing layer and the substrate layer in order to decrease the device capacitance and thereby increasing the photodetector bandwidth. The dielectric layer increases the photodetector efficiency and blocks slow moving carriers from the high field... Agent: Dallas Office Of Fulbright & Jaworski L.L.P.

20070057300 - Semiconductor device: A semiconductor device includes a substrate, a first electrode provided above the substrate, a ferroelectric layer provided above the first electrode, a second electrode provided above the ferroelectric layer, and a dielectric side spacer that is provided above the first electrode and on a side surface of at least the... Agent: Harness, Dickey & Pierce, P.L.C

20070057301 - Method of manufacturing a transistor, a method of manufacturing a memory device and transistor: A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070057304 - Capacitor structure, memory cell and method for forming a capacitor structure: The present invention refers to a trench capacitor structure as it is used in memory cells, for example in memory cells of memory devices. Particularly, the capacitor structure may be used in a DRAM memory. Furthermore, the invention relates to a memory cell comprising a transistor and a capacitor with... Agent: Morrison & Foerster LLP

20070057303 - Method for forming trench capacitor and memory cell: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used... Agent: North America Intellectual Property Corporation

20070057305 - Mim capacitor integrated into the damascene structure and method of making thereof: This invention provides for the integration of metal-insulator-metal (MIM) capacitors with the damascene interconnect structure and process. The method includes forming a damascene interconnect structure and a MIM capacitor damascene structure wherein a diffusion barrier material forms the capacitor electrodes. The method includes forming a MIM capacitor damascene structure through... Agent: Slater & Matsil, L.L.P.

20070057302 - Trench metal-insulator-metal (mim) capacitors integrated with middle-of-line metal contacts, and method of fabricating same: The present invention relates to a semiconductor device that contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer... Agent: Scully Scott Murphy & Presser, PC

20070057306 - Semiconductor storage device and method for manufacturing the same: A semiconductor storage device is manufactured by the following steps. A cylindrical hole is formed in an interlayer insulating film. Then, a multilayer conductive layer including a first sublayer and a second sublayer is formed over the entire surface of the insulating interlayer including the internal surface of the hole.... Agent: Sughrue Mion, PLLC

20070057308 - Electrode structure and method of manufacturing the same, phase-change memory device having the electrode structure and method of manufacturing the same: Example embodiments of the present invention relate to an electrode structure, a method of manufacturing the electrode structure, a phase-change memory device having the electrode structure and a method of manufacturing the phase-change memory device. The electrode structure may include a pad, a first insulation layer pattern, a second insulation... Agent: Harness, Dickey & Pierce, P.L.C

20070057307 - Embedded flash memory devices on soi substrates and methods of manufacture thereof: Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer... Agent: Slater & Matsil LLP

20070057310 - Nonvolatile semiconductor memory device having element isolating region of trench type: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070057309 - Nonvolatile semiconductor memory devices and methods of forming the same: A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines... Agent: Myers Bigel Sibley & Sajovec

20070057311 - Conventionally printable non-volatile passive memory element and method of making thereof: A non-volatile passive memory element comprising on a single surface a first electrode system and a second electrode system together with an insulating system, unless the insulating system is the surface, wherein the first electrode system is insulated from the second electrode system, the first and the second electrode systems... Agent: Leydig Voit & Mayer, Ltd

20070057314 - Integrated circuit device and electronic instrument: A programmable ROM block provided in an integrated circuit device includes a memory cell having a single-layer-gate structure in which a floating gate used in common as gates of a write/read transistor and an erase transistor is opposite to a control gate formed of an impurity layer through an insulating... Agent: Oliff & Berridge, PLC

20070057313 - Multi-bit nonvolatile memory devices including nano-crystals and trench, and methods for fabricating the same: Nonvolatile integrated circuit memory devices having a 2-bit memory cell include a substrate, a source region and a drain region in the substrate, a step recess channel between the source region and the drain region, a trapping structure including a plurality of charge trapping nano-crystals on the step recess channel,... Agent: Myers Bigel Sibley & Sajovec

20070057312 - Transistor of semiconductor memory device and method for manufacturing the same: A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first... Agent: Marshall, Gerstein & Borun LLP

20070057315 - Nonvolatile semiconductor memory device having element isolating region of trench type: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070057316 - Semiconductor device and manufacturing method thereof: A semiconductor device, in which both a reduction in a resistivity of a gate electrode and stabilization of transistor characteristics is achieved, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a semiconductor substrate, a plurality of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070057319 - Flash memory device and a method of manufacturing the same: The present invention provides a flash memory device and a method of forming the same. The method includes: forming an isolation layer and a plurality of gate lines on a semiconductor substrate; forming a source/drain region by ion-implanting impurities into the semiconductor substrate using the gate lines as a mask;... Agent: Sung-jin Kim

20070057317 - Non-volatile memory cell and fabricating method thereof and method of fabricating non-volatile memory: A method of fabricating a non-volatile memory is provided. In the fabricating method, a plurality of stack gate structures is formed on a substrate and a plurality of doped regions is formed in the substrate beside the stack gate structures. Then, a plurality of spacers is formed on the sidewalls... Agent: J C Patents, Inc.

20070057318 - Semiconductor memory device and method of production: A semiconductor substrate is provided with a recess. A memory layer or memory layer sequence is applied to sidewalls and the bottom of the recess. The memory layer is formed into two separate portions at opposite sidewalls of the recess either by reducing the memory layer to sidewall spacers or... Agent: Slater & Matsil LLP

20070057321 - Semiconductor device: In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions,... Agent: Morrison & Foerster LLP

20070057320 - Semiconductor devices with stressed channel regions and methods forming the same: A semiconductor device includes a substrate having a semiconductor channel region therein. A gate electrode is provided on the channel region. A SiGeC stress-inducing region is provided adjacent the channel region. The SiGeC region is configured to form a semiconductor junction with the channel region and induce a net mobility-enhancing... Agent: Myers Bigel Sibley & Sajovec

20070057322 - Substrate carrier having reduced height: A first substrate carrier is provided that includes a body adapted to store one or more substrates; and either (1) a bottom surface having one or more coupling features that extend into a storage region of the body or (2) coupling features that extend alongside the body, so that the... Agent: Dugan & Dugan, PC

20070057326 - Semiconductor device and manufacturing method of the same: A semiconductor device comprises: a channel region of a transistor formed in a predetermined region of silicon layer formed on insulation film; a gate electrode formed on the channel region via gate insulation film; and source/drain regions formed in the silicon layer thicker than said channel region located out of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070057325 - Semiconductor finfet structures with encapsulated gate electrodes and methods for forming such semiconductor finfet structures: Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070057323 - Silicon-on-insulator (soi) read only memory (rom) array and method of making a soi rom: A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface... Agent: Law Office Of Charles W. Peterson, Jr. Burlington

20070057324 - Strained semiconductor device and method of making the same: In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall... Agent: Slater & Matsil LLP

20070057327 - Lcd source driver for improving electrostatic discharge: In an LCD source driver, to enhance the ESD performance thereof, there is provided a path in a device area penetrating thereacross such that an internal power wire or an internal ground wire to connect between an output pad and a power-rail ESD clamp circuit on two margins, respectively, of... Agent: Rosenberg, Klein & Lee

20070057328 - Semiconductor device and its manufacture: In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall spacers of the MIS transistor in the logic area... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070057329 - Semiconductor device having a p-mos transistor with source-drain extension counter-doping: A method for forming a semiconductor device is provided. The method includes forming a n-type well region. The method further includes forming a gate corresponding to the semiconductor device on top of the n-type well region. The method further includes forming a source-drain extension region on each side of the... Agent: Freescale Semiconductor, Inc. Law Department

20070057330 - Semiconductor device and method of fabricating semiconductor device: A semiconductor device is provided. The semiconductor device includes a substrate, a gate, spacers, and a source and a drain. The gate is formed on the substrate, has side walls, and is formed of a silicide material. The spacers are formed on the sidewalls of the gate. The source and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070057331 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a semiconductor substrate divided into a first region and a second region; a first MIS transistor formed in the first region of the semiconductor substrate and including a stack of a first gate insulating film and a fully-silicided first gate electrode; and a second MIS transistor... Agent: Mcdermott Will & Emery LLP

20070057332 - Thin film transistor and fabrication method thereof: A thin film transistor (TFT) with a self-aligned lightly-doped region and a fabrication method thereof. An active layer has a channel region, a first doped region and a second doped region, in which the first doped region is disposed between the channel region and the second doped region. A gate... Agent: Liu & Liu

20070057333 - Mos transistor and method of manufacturing the same: Example embodiments relate to a metal-oxide-semiconductor (MOS) transistor and a method of manufacturing the MOS transistor. In a MOS transistor and a method of manufacturing the same, a gate insulation layer may be formed on the channel region of the substrate, and may further include metal oxide or metal silicate.... Agent: Harness, Dickey & Pierce, P.L.C

20070057334 - Mosfet with high angle sidewall gate and contacts for reduced miller capacitance: The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such... Agent: Scully Scott Murphy & Presser, PC

20070057335 - Semiconductor device: It is made possible to control the effective work function of the gate electrode so that the transistor can have an optimum operating threshold voltage. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode provided on the gate insulating film;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070057336 - Microelectromechanical (mem) viscosity sensor and method: A MEM viscosity sensor comprises a substrate, with first and second support structures affixed to the substrate and spaced-apart. A compliant member is affixed to the support structures such that it is suspended above and can flex vertically with respect to the substrate. The member has a high density of... Agent: Koppel, Patrick & Heybl

20070057337 - Semiconductor device: A semiconductor device includes a semiconductor substrate formed of at least two kinds of group III elements and nitrogen, an active layer formed on the semiconductor substrate, and a nitride semiconductor layer formed on a surface of the semiconductor substrate and formed between the semiconductor substrate and the active layer.... Agent: Ndq&m Watchstone LLP

20070057338 - Image sensor with decreased optical interference between adjacent pixels: An image sensor with decreased optical interference between adjacent pixels is provided. An image sensor, which is divided into a pixel region and a peripheral region, the image sensor including a photodiode formed in a substrate in the pixel region, first to Mth metal lines formed over the substrate in... Agent: Morgan Lewis & Bockius LLP

20070057339 - Photoelectric conversion device and solid-state imaging device: A photoelectric conversion device comprising a photo-electric conversion part including a first electrode layer, a second electrode layer and a photoelectric conversion layer provided between the first electrode layer and the second electrode layer, wherein light is made incident from an upper part of the second electrode layer into the... Agent: Sughrue-265550

20070057340 - Semiconductor device and method of fabricating thereof: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of contact metals, and a gate electrode. The semiconductor substrate has an active region and a dummy active region, and a plurality of contact metals are formed in the active region. A gate electrode is located... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070057341 - Self-aligned process for manufacturing a phase change memory cell and phase change memory cell thereby manufactured: A process for manufacturing a phase change memory cell, comprising the steps of: forming a resistive element; forming a delimiting structure having an aperture over the resistive element; forming a memory portion of a phase change material in the aperture, the resistive element and the memory portion being in direct... Agent: Seed Intellectual Property Law Group PLLC

20070057342 - Semiconductor fuse box and method for fabricating the same: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse... Agent: Law Office Of Monica H Choi

20070057344 - Embedded capacitor with interdigitated structure: An embedded capacitors with interdigitated structure for a package carrier or a printed circuit board comprises a plurality of stacked conductive layers, at least one first via connecting structure and at least one second via connecting structure. In order to enhance the capacitance and the layout efficiency, this case fully... Agent: Birch Stewart Kolasch & Birch

20070057343 - Integration of a mim capacitor over a metal gate or silicide with high-k dielectric materials: A Metal Insulator-Metal (MIM) capacitor is formed on a semiconductor substrate with a base comprising a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. An... Agent: International Business Machines Corporation Dept. 18g

20070057345 - Resistance dividing circuit and manufacturing method thereof: A resistance dividing circuit including silicide layers respectively formed only on branch portions of a linear polysilicon resistance wiring having the branch portions. Contact plugs are connected to the resistance wiring via the silicide layers, and fetching electrodes are respectively connected to the contact plugs.... Agent: Volentine Francos, & Whitt PLLC

20070057346 - Semiconductor device having esd protection with fuse: A semiconductor device is provided having an electrostatic discharge (ESD) protection function. It includes a plurality of no-connection (NC) pads, each associated with a corresponding NC ball, and each connected to a corresponding internal circuit, an ESD protection circuit connected to each one of the plurality of NC pads, and... Agent: Volentine Francos, & Whitt PLLC

20070057347 - Field-effect transistor and method for fabricating the same: A field-effect transistor that increases the operation speeds of complementary field-effect transistors. Each of an nMOSFET and a pMODFET has a Ge channel and source and drain regions formed of an NiGe layer. The height of Schottky barriers formed at a junction between a channel region and the source region... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070057348 - Microstructure and manufacturing method thereof: A microstructure includes a substrate and a photoresist layer. The substrate has a surface, and the photoresist layer is disposed on the substrate. The photoresist layer has at least one recess, which has a sidewall, a depth and a width. An oblique angle of the sidewall is not less than... Agent: Birch Stewart Kolasch & Birch

20070057349 - Wafer having scribe lanes suitable for sawing process, reticle used in manufacturing the same, and method of manufacturing the same: A wafer that is less susceptible to chipping or peeling during a sawing process is disclosed. The wafer includes a plurality of chips, scribe lanes formed between the plurality of chips, and a passivation film, which is formed on the plurality of chips and the scribe lanes and has a... Agent: Marger Johnson & Mccollom, P.C.

20070057350 - Semiconductor component and method of assembling the same: A semiconductor component includes at least one semiconductor power switch, wherein a gate electrode and at least two source regions are disposed on the upper side of the semiconductor power switch. The component further includes a leadframe including a die pad and a number of leads disposed on one side... Agent: Edell, Shapiro & Finnan, LLC

20070057351 - Structure of ic packaging and method forming the same: A structure of IC packaging and a method forming the same are disclosed in the present invention. This structure of IC packaging comprises a substrate, a chip, and a plurality of copper connecting wires. At least a conductive structure is made on the substrate and an isolating material is coated... Agent: Birch Stewart Kolasch & Birch

20070057352 - Method and apparatus for thermally processing microelectronic workpieces: An apparatus for thermally processing a microelectronic workpiece is provided. The apparatus comprises a rotatable carousel assembly configured to support at least one workpiece. A driver is coupled to the carousel assembly and rotates the carousel assembly, moving the workpiece between a loading station, a heating station and a cooling... Agent: Perkins Coie LLP/semitool

20070057353 - Multi-part lead frame with dissimilar materials: A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame semiconductor device assembly which utilizes equipment designed... Agent: Trask Britt, P.C./ Micron Technology

20070057354 - Multi-part lead frame with dissimilar materials: A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame semiconductor device assembly which utilizes equipment designed... Agent: Trask Britt, P.C./ Micron Technology

20070057355 - Method for forming buried cavities within a semiconductor body, and semiconductor body thus made: A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the... Agent: Graybeal Jackson Haley LLP Bryan A. Santarelli

20070057356 - Image sensing chip package structure: In an image sensing chip package structure, plated through vias penetrate a substrate to electrically connect metallization traces disposed on the upper and lower surfaces of the substrate. The plated through vias can be opened from the center of the substrate instead of being located at the periphery of the... Agent: Rosenberg, Klein & Lee

20070057358 - Multi-level semiconductor module: A semiconductor module is formed by alternately stacking resin boards on which semiconductor chips are mounted and sheet members having openings larger than the semiconductor chips and bonded to the resin boards. One of the resin boards located at the bottom has a thickness larger than that of each of... Agent: Mcdermott Will & Emery LLP

20070057357 - System in package (sip) structure: A System In Package (SIP) arrangement and method of connecting a plurality of flip chips and wire bond chips with reduced wiring complexity and increase flexibility. The SIP arrangement includes at least one wire bond chip and at least one flip chip.... Agent: Slater & Matsil, L.L.P.

20070057359 - Energy conditioning circuit assembly and component carrier: The present invention is a component carrier (132) comprising of a plate of insulating material having a plurality of apertures (140) for accepting the leads of a thru-hole differential and common mode filter (130). Another embodiment comprises of a surface mount component carrier (10) comprising a disk (16) of insulating... Agent: NeifeldIPLaw, PC

20070057361 - integrated circuit package and method of manufacture thereof: An integrated circuit (IC) package that comprises a lead frame. The lead frame has a downset portion and leads. The downset portion has an exterior surface that is configured to face away from a mounting board, and an interior surface that is configured to face towards the mounting board. The... Agent: Texas Instruments Incorporated

20070057360 - Semiconductor package film having reinforcing member and related display module: Semiconductor package films and a display module comprising a packaged semiconductor device punched from a semiconductor package film are provided. In one embodiment, the invention provides a semiconductor package film comprising a base film comprising a plurality of semiconductor device regions, an intermediate region disposed on a first surface of... Agent: Volentine Francos, & Whitt PLLC

20070057362 - Area array routing masks for improved escape of devices on pcb: A method for optimizing area array device pin utilization and reducing the number of layers on a multilayered PCB comprising: preparing a package of BGA pin-out maps which anticipate the effect of existing fixed pins and derives the resulting optimum pin location assignment. Each pin-out map includes an indication of... Agent: Law Office Of Jim Zegeer

20070057363 - Multilayered wiring substrate and method of manufacturing the same: A multilayered wiring substrate constructed by staking a wiring layer 105, 108, 110, 112 and an insulating layer 104, 106, 107, 109 in predetermined number, which includes a reinforcing wiring layer 103 whose thickness is 35 to 150 μm is arranged in one layer or plural layers.... Agent: Drinker Biddle & Reath (dc)

20070057364 - Low temperature co-fired ceramic (ltcc) tape compositions, light emitting diode (led) modules, lighting devices and method of forming thereof: The present invention provides LTCC (low temperature co-fired ceramic) tape compositions and demonstrates the use of said LTCC tape(s) in the formation of Light-Emitting Diode (LED) chip carriers and modules for various lighting applications. The present invention also provides for the use of (LTCC) tape and LED modules in the... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070057365 - Device for preventing low-melting-point heat-transfer medium from oxidization: A device for preventing a low-melting point heat-transfer medium from oxidization is proposed. The device has a heat sink, a low-melting-point alloy, and an oxidization-proof layer. The low-melting-point alloy is disposed on the heat sink and serves as a heat-transfer medium to contact a heat source. The oxidization-proof layer is... Agent: Rosenberg, Klein & Lee

20070057367 - Semiconductor chip having bond pads and multi-chip package: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a... Agent: Marger Johnson & Mccollom, P.C.

20070057366 - Semiconductor ic-embedded module: A semiconductor IC-embedded module 100 comprises a multilayer substrate 101 having first and second insulating layers 101a and 101b, and a controller IC 012 and memory IC 103 that are embedded in the multilayer substrate 101. A wiring layer 104 is formed as an internal layer in the multilayer substrate... Agent: Wolff Law Office, PLLC

20070057368 - Semiconductor package having plate interconnections: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having metalized source and gate areas separated by a passivation area, a patterned source connection coupling the source lead to the semiconductor die metalized... Agent: Fortune Law Group LLP

20070057370 - Semiconductor device: A semiconductor device including: a semiconductor chip in which an integrated circuit is formed; a plurality of electrodes formed in a first region of the semiconductor chip and arranged in a plurality of rows and a plurality of columns; a plurality of resin protrusions formed in a second region of... Agent: Harness, Dickey & Pierce, P.L.C

20070057369 - Wiring board and method for manufacturing the same, and semiconductor device: A wiring board includes: an insulating base; a plurality of conductive wirings; and bumps formed on the conductive wirings, respectively. The conductive wirings can be connected with electrode pads of a semiconductor element via the bumps. The conductive wirings include a connection terminal portion at an end portion opposite to... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070057372 - External contact material for external contacts of a semiconductor device and method of making the same: An external contact material for external contacts of a semiconductor device and a method for producing the same are described. The external contact material includes a lead-free solder material. Provided in the solder material is a filler which forms a plurality of gas pores and/or has plastic particles which are... Agent: Edell, Shapiro & Finnan, LLC

20070057371 - Semiconductor device: A semiconductor device including: a semiconductor chip in which an integrated circuit is formed; a plurality of electrodes formed on the semiconductor chip and arranged in a plurality of rows and a plurality of columns; a plurality of resin protrusions formed on a surface of the semiconductor chip on which... Agent: Harness, Dickey & Pierce, P.L.C

20070057373 - Semiconductor device having metallic plate with groove: A semiconductor device includes: first and second metallic plates, each of which includes a heat radiation surface and an inner surface; a semiconductor element between the metallic plates; a block between the second metallic plate and the semiconductor element; a solder member between the second metallic plate and the block;... Agent: Posz Law Group, PLC

20070057374 - Embedded barrier for dielectric encapsulation: A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the... Agent: International Business Machines Corporation Dept. 18g

20070057375 - Multilayered wiring substrate and manufacturing method thereof: In a multilayered wiring substrate in which insulation layers 104A, 106A, wiring layers 105A, 108A and insulation layers 104B, 106B, wiring layers 105B, 108B are laminated on both side surfaces of a core layer 101A, respectively, the core layer 101A is constituted by insulation material 112 having no reinforcing member... Agent: Drinker Biddle & Reath (dc)

20070057376 - Semiconductor device and method for fabricating the same: A semiconductor device has a first metal pattern made of a first metal formed on a semiconductor substrate, an insulating film formed over the first metal pattern, and a second metal pattern made of a second metal formed on the insulating film. The insulating film has a barrier property for... Agent: Mcdermott Will & Emery LLP

20070057377 - Semiconductor memory device comprising pseudo ground pad and related method: A semiconductor memory device comprising a pseudo ground voltage pad and a method of making the semiconductor device are disclosed. The semiconductor memory device comprises a plurality of pads that are respectively adjacent to one another in a first direction. The plurality of pads comprises a plurality of ground voltage... Agent: Volentine Francos, & Whitt PLLC

20070057378 - Electronic device and manufacturing method therefor: On the back surface of the chip of which a front surface is formed with an electronic circuit, an adhesive film of a shape and dimensions corresponding to at least the back surface of the chip is adhered to obtain the semiconductor chip with the entire back surface covered with... Agent: Brinks Hofer Gilson & Lione

20070057381 - Integrated circuit die configuration for packaging: Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the corners of the die. The die is mounted on a package... Agent: Blakely Sokoloff Taylor & Zafman

20070057380 - Method for designing semiconductor apparatus, system for aiding to design semiconductor apparatus, computer program product therefor and semiconductor package: A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable... Agent: Mcdermott Will & Emery LLP

20070057379 - Method of manufacturing a semiconductor device: In connection with a memory card of a block molding type there is provided a method able to prevent the occurrence of a chip crack in transfer molding. The method includes a first step wherein a substrate having plural chips constituting plural memory cards and mounted on a surface of... Agent: Miles & Stockbridge PC

20070057382 - Electronic package with compliant electrically-conductive ball interconnect: An electronic device comprises a device substrate, a plurality of compliant electrically-conductive balls, and a plurality of solder joints that couple the compliant electrically-conductive balls to the device substrate by a reflow process.... Agent: Hewlett Packard Company

20070057383 - Semiconductor chip having bond pads and multi-chip package: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a... Agent: Marger Johnson & Mccollom, P.C.

20070057384 - Semiconductor stacked die/wafer configuration and packaging and method thereof: A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which... Agent: Freescale Semiconductor, Inc. Law Department

20070057385 - Apparatus and method for applying conductive paste onto electronic component: An apparatus and a method for applying a conductive paste, for forming electrodes, onto an electronic component, such as a micro chip device. The apparatus includes a first jig unit provided with paste holes, which are filled with the conductive paste; and a second jig unit being movable and provided... Agent: Mcdermott Will & Emery LLP

20070051935 - Phase change random access memory and method of operating the same: A phase change random access memory (PRAM), and a method of operating the PRAM are provided. In the PRAM comprising a switching element and a storage node connected to the switching element, the storage node comprises a first electrode, a second electrode, a phase change layer between the first electrode... Agent: Harness, Dickey & Pierce, P.L.C

20070051936 - Phase change memory cell with tubular heater and manufacturing method thereof: A phase change memory cell includes a phase change region of a phase change material, a heating element of a resistive material, arranged in contact with the phase change region and a memory element formed in said phase change region at a contact area with the heating element. The contact... Agent: Seed Intellectual Property Law Group Pllc

20070051937 - Optical semiconductor devices on inp substrate: Each specific layer, i.e., each ZnSe0.53Te0.47 layer (2ML) is inserted between host layers, i.e., Mg0.5Zn0.29Cd0.21Se layers (each having 10ML (atomic layer) thickness) each of which is lattice matched to an InP substrate. In this case, each specific layer in which a sufficient carrier concentration of 1×1018 cm−3 or more is... Agent: Mattingly, Stanger, Malur & Brundidge, P.c.

20070051939 - Optical semiconductor device: This invention is constructed by stacking an n-type InGaAlAs-GRIN-SCH layer 3, an MQW layer 4, a p-type InGaAlAs-GRIN-SCH layer 5, a p-type InAlAs electron-stopping layer 6, and others, in that order, on an n-type InP wafer 1; wherein the MQW layer 4 includes InGaAlAs-strained quantum well layers and InGaAlAsSb-formed barrier... Agent: Stanley P. Fisher Reed Smith LLP

20070051938 - Semiconductor device: A two-dimensional carrier is generated in the vicinity of an interface that is a hetero interface between a semiconductor layer and a semiconductor layer. Two concave portions are formed so as to extend from a primary surface as far as the interface. An electrode that is made of metal and... Agent: Wood, Herron & Evans, LLP

20070051941 - Carbon nanotubes based solar cells: The invention relates to a photovoltaic device, uses of the photovoltaic device, combinations of this photovoltaic device with circuits and to a method of generating electricity from light using this photovoltaic device.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.c.

20070051940 - Device and method for determining the physical condition of an animal: Organic memory unit and driver circuit therefor The invention relates to organic memory units and driver circuits therefor. The organic memory units have a layer of bistably switchable material or comprise a circuit in which two OFETs are connected in series and one OFET is connected in parallel with a... Agent: Carella, Byrne, Bain, Gilfillan, Cecchi, Stewart & Olstein

20070051942 - Etch masks based on template-assembled nanoclusters: Nanoscale or mesoscale structures are fabricated on the surface of a substrate (e.g. silicon) by the aggregation of atomic clusters (e.g. antimony or bismuth) into V-grooves. These structures, preferably in the form of nanowires, are used as etching masks for the subsequent etching of the substrate. In an embodiment the... Agent: Dann, Dorfman, Herrell & Skillman

20070051944 - Organic electroluminescent element: The present invention relates to the improvement of phosphorescent organic electro-luminescent devices by using materials of the formula (1), preferably triazines, pyrimidines, pyridazines and pyrazines, in the hole-blocking layer.... Agent: Connolly Bove Lodge & Hutz, LLP

20070051946 - Organic light-emitting diodes and an arrangement with several organic light-emitting diodes: Organic light-emitting diode with a layer arrangement which comprises an electrode, a counter electrode and an organic layer sequence arranged between the electrode and the counter electrode, where the organic layer sequence is arranged on a metal substrate and one or several organic transport layers containing in each case an... Agent: Sutherland Asbill & Brennan LLP

20070051945 - Organic light-light conversion device: An organic light-light conversion device excellent in device characteristics, comprising a light sensing unit having a layer including a photo-conductive organic semiconductor developing a photo-current multiplication phenomenon by light irradiation, and a light emitting unit having a layer including an electroluminescent organic semiconductor emitting light by current injection, characterized in... Agent: Sughrue Mion, Pllc

20070051947 - Semiconductor device: Provided is a semiconductor device including: a substrate; a layer containing one or more kinds of polymer compounds on the substrate; and an organic semiconductor layer in contact with the layer containing the one or more kinds of polymer compounds, in which at least one kind of the one or... Agent: Fitzpatrick Cella Harper & Scinto

20070051943 - Thin film transistor, thin film transistor array panel, and display device: A thin film transistor is provided, which includes: a gate electrode (124); a gate insulating layer (140) formed on the gate electrode; a semiconductor layer (154) formed on the gate insulating layer and disposed opposite the gate electrode; a source electrode (173) and a drain electrode (175) that are formed... Agent: Macpherson Kwok Chen & Heid LLP

20070051949 - Method and arrangment for testing a stacked die semiconductor device: A semiconductor device and related testing methods and configurations are provided to enable parallel (simultaneous) testing of multiple chips on a stacked multiple chip semiconductor device. Each chip in the device is configured to selectively output test results to one or more unique contacts on a substrate of the device.... Agent: Edell, Shapiro & Finnan, Llc

20070051950 - Method for generating test patterns utilized in manufacturing semiconductor device: A method for generating test patterns utilized in manufacturing a semiconductor device includes creating mini-data concerning a partial area pattern used in designing the semiconductor device, subjecting the mini-data to data processing in accordance with a condition of a manufacturing process of the semiconductor device, thereby creating processed mini-data, extracting... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070051951 - Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level: A test methodology is provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. A resistor is formed on a region of dielectric isolation material formed in a semiconductor substrate. The MIM capacitor is formed over the resistor and separated therefrom by dielectric material. A metal... Agent: Stallman & Pollock LLP

20070051948 - Test structure and method for detecting and studying crystal lattice dislocation defects in integrated circuit devices: A test structure (200, 200′) having an array (224) of test devices (220) for detecting and studying defects that can occur in an integrated circuit device, e.g., a transistor (144), due to the relative positioning of one component (100) of the device with respect to another component (108) of the... Agent: Downs Rachlin Martin Pllc

20070051953 - Active matrix structure for a display device and method for its manufacture: The invention relates to an active matrix structure and method for manufacturing the active matrix structure for a display device, wherein the structure includes: providing a matrix substrate with a number of row lines and a number of column lines, with each point of intersection between one of the row... Agent: Bell, Boyd & Lloyd, Llc

20070051952 - Liquid crystal display device and method for manufacturing the same, and liquid crystal television receiver: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal... Agent: Nixon Peabody, LLP

20070051954 - Tft array substrate of tft lcd having large storage capcitor and method for manufacturing same: An exemplary thin film transistor (TFT) array substrate includes a glass substrate (430), a semiconductor layer (440) formed on the glass substrate, a gate insulating layer (407) formed on the semiconductor layer, and a plurality of gate electrodes (410) and common electrodes (411) formed on the gate insulating layer. A... Agent: Wei Te Chung Foxconn International, Inc.

20070051955 - Thin film transistor array substrate and manufacturing method of the same: A thin film transistor array substrate has a gate electrode of the thin film transistor, a gate line connected to the gate electrode, and a gate pad connected to the gate line; a source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data... Agent: Song K. Jung Mckenna Long & Aldridge LLP

20070051956 - Thin film transistor: A thin film transistor having a substrate, a gate insulating layer, a double-gate structure, a first lightly doped region, and a second lightly doped region. The substrate has a source region and a drain region disposed on its opposite sides, a heavily doped region between source region and drain region,... Agent: Jianq Chyun Intellectual Property Office

20070051957 - Semiconductor device and its manufacturing method: Protrusions called ridges are formed on the surface of a crystalline semiconductor film formed by a laser crystallization method or the like. A heat absorbing layer are formed below a semiconductor film. When the semiconductor film is crystallized by laser, a temperature difference is produced between a semiconductor film 1010... Agent: Fish & Richardson P.c.

20070051958 - Display device and method for manufacturing the same, and television receiver: According to the present invention, which is a display device in which a light-emitting element where an organic substance generating luminescence referred to as electroluminescence or a medium including a mixture of an organic substance and an inorganic substance is sandwiched between electrodes is connected to a TFT, the invention... Agent: Nixon Peabody, LLP

20070051959 - Self-light-emitting device and method of manufacturing the same: Failure light emission of an EL element due to failure film formation of an organic EL material in an electrode hole 46 is improved. By forming the organic EL material after embedding an insulator in an electrode hole 46 on a pixel electrode and forming a protective portion 41b, failure... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070051960 - Backlight module for liquid crystal display: A backlight module includes a base, a plurality of point light sources distributed on the base and a light guide plate. Each of the point light sources includes a transparent cover and a light-emitting unit received in the cover. The transparent cover includes an inwardly curved light emitting top surface... Agent: Pce Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070051962 - Gallium nitride semiconductor light emitting device: The present invention is a semiconductor structure for light emitting devices that can emit light with multiple wavelengths, in particular, in the blue to ultraviolet region of the electromagnetic spectrum. The structure comprises an active portion positioned between a p-type gallium nitride (GaN) layer and an n-type gallium nitride (GaN)... Agent: Rosenberg, Klein & Lee

20070051961 - Nitride semiconductor light-emitting device: A nitride semiconductor light-emitting device wherein a substrate or nitride semiconductor layer has a defect concentration region and a low defect density region other than the defect concentration region. A portion including the defect concentration region of the nitride semiconductor layer or substrate has a trench region deeper than the... Agent: Harness, Dickey & Pierce, P.L.C

20070051963 - Semiconductor light source: A light source is based on a combination of silicon and calcium fluoride (CaF2). The silicon and the calcium fluoride need not be pure, but may be doped, or even alloyed, to control their electrical and/or physical properties. Preferably, the light source employs interleaved portions, e.g., arranged as a multilayer... Agent: Lucent Technologies Inc. Docket Administrator - Room 3j-219

20070051967 - Adapting short-wavelength led's for polychromatic, broadband, or \"white\" emission: An adapted LED is provided comprising a short-wavelength LED and a re-emitting semiconductor construction, wherein the re-emitting semiconductor construction comprises at least one potential well not located within a pn junction. The potential well(s) are typically quantum well(s). The adapted LED may be a white or near-white light LED. The... Agent: 3m Innovative Properties Company

20070051965 - Field emitting light source and method for making the same: A CNT field emitting light source (20) is provided. The light source includes an anode (202), an anode substrate (201), a cathode (214), a cathode substrate (208), a fluorescent layer (203) and a sealing means (205). The anode is configured on the anode substrate, and the cathode is configured on... Agent: Pce Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070051964 - High density led array: A dense array of semiconductor devices having an array of micro-reflectors, the micro-reflectors having characteristics that enhance dense packing of the array in balance with collection and collimation of the array's radiant output.... Agent: Ganz Law, P.c.

20070051966 - Light emitting diode and method for manufacturing the same: A light emitting diode includes an LED element, a fluorescent material provided so as to cover the LED element, a substrate on which the LED element is mounted and made of ceramics or silicon, and a pair of electrode pads which are electrically connected to the LED element on the... Agent: Rankin, Hill, Porter & Clark LLP

20070051968 - Nitride-based semiconductor light-emitting device and method of manufacturing the same: A nitride-based semiconductor light-emitting device having excellent reliability and long lifetime, and a method of manufacturing the same are provided. A nitride-based semiconductor light-emitting element chip, in which a nitride-based semiconductor layer and a first electrode are formed on a surface of an electrically conductive substrate and a second electrode... Agent: Harness, Dickey & Pierce, P.L.C

20070051969 - Group iii-v nitride-based semiconductor substrate and method of making same: A group III-V nitride-based semiconductor substrate having a group III-V nitride-based semiconductor thick film with a same composition in the entire film. The thick film has a first region with a predetermined impurity concentration and a second region with an impurity concentration lower than the first region.... Agent: Foley And Lardner LLP Suite 500

20070051970 - Nanowire electromechanical device and method of fabricating the same: A nanowire electronmechanical device with an improved structure and a method of fabricating the same prevent burning of two nanowires which are switched due to contact with each other while providing stable on-off switching characteristics. The nanowire electromechanical device comprises: an insulating substrate; first and third electrodes spaced apart from... Agent: Robert E. Bushnell

20070051971 - Method for protecting the gate of a transistor and corresponding integrated circuit: A gate of a transistor in an integrated circuit is protected against the production of an interconnection terminal for a source/drain region. The transistor includes a substrate, at least one active zone formed in the substrate, at least one insulating zone formed in the substrate and a gate, the gate... Agent: Jenkens & Gilchrist, Pc

20070051972 - Thyristor with recovery protection: A main thyristor (1) has a recovery protection which is integrated into a drive thyristor (2) whose n-doped emitter (25) is electrically connected to a main thyristor control terminal (140). Moreover, the p-doped emitter (28) of the drive thyristor (2) is electrically connected to the p-doped emitter (18) of the... Agent: Baker Botts, L.l.p.

20070051973 - Semiconductor device: A semiconductor device including: a bulk semiconductor substrate; an access transistor; a thyristor formed on the bulk semiconductor substrate connecting to the access transistor; an element separating region to separate the region for the access transistor and the region for the thyristor from each other; and a wiring layer connecting... Agent: Rader Fishman & Grauer Pllc

20070051974 - Semiconductor device and power conversion apparatus using the same: The power conversion apparatus uses the semiconductor device. Said semiconductor device includes a first group of power semiconductor elements at least one of which is electrically connected between a first potential and a third potential, a second group of power semiconductor elements at least one of which is electrically connected... Agent: Crowell & Moring LLP Intellectual Property Group

20070051975 - Semiconductor heterostructure and method for forming same: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of... Agent: Winston & Strawn LLP Patent Department

20070051976 - Radiation sensor: An energy selective radiation sensor 10 has a photodetector 11 and a transfer gate 12 for controlling transfer of charge from the photodetector to a first sense node 13. A first readout circuit 14, 15, 16 is provided for reading out charge from the first node. In use a first... Agent: Venable LLP

20070051977 - Nitride semiconductor device: A nitride semiconductor device comprises: a substrate body including a conductive substrate portion and a high resistance portion; a first semiconductor layer of a nitride semiconductor provided on the substrate body; a second semiconductor layer provided on the first semiconductor layer; a first main electrode provided on the second semiconductor... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.c.

20070051978 - Ohmic electrode, method of manufacturing ohmic electrode, field effect transistor, method of manufacturing field effect transistor, and semiconductor device: The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of... Agent: Rabin & Berdo, Pc

20070051979 - Semiconductor device: A semiconductor device includes a plurality of electrodes arranged on a compound semiconductor layer grown on a substrate, and a surface protection film that protects a surface of a semiconductor layer on the compound semiconductor layer between the electrodes. A refractive index of the surface protection film is controlled so... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.c.

20070051981 - Integrated semiconductor structure including a heterojunction bipolar transistor and a schottky diode: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer.... Agent: Mcnees Wallace & Nurick Llc

20070051980 - Silicon germanium (sige) heterojunction bipolar transistor (hbt): A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier... Agent: Law Office Of Charles W. Peterson, Jr. Burlington

20070051982 - Dense non-volatile memory array and method of fabrication: A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F2 per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile memory array which includes word lines and... Agent: Tiajoloff & Kelly

20070051983 - Driving circuit of a liquid crystal display panel: A driving circuit of a liquid crystal display panel includes a substrate, a plurality of driver IC chips located on the substrate, a current supplier, and a first conductive wire set. The first conductive wire set has a plurality of conductive wire segments for connecting the driver IC chips in... Agent: North America Intellectual Property Corporation

20070051984 - Rewiring substrates strip with several semiconductor component positions: A rewiring substrate strip and a method of producing a rewiring substrate strip is disclosed. In one embodiment, the rewiring substrate strip has several semiconductor component positions for semiconductor components. The semiconductor component positions are arranged in rows and columns. In this arrangement, several semiconductor component positions are combined to... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070051985 - Charge coupled device with high quantum efficiency: A six-phase charge coupled device (CCD) pixel includes a pixel pair, with each pixel having two adjacent control gates overlying corresponding variable potential wells, where voltages applied to the control gates enable charge to be accumulated into and transferred out of the wells. A clear window region overlies a fixed... Agent: Macpherson Kwok Chen & Heid LLP

20070051987 - Digital micromirror device and manufacturing method thereof: Provided is a digital micromirror device (DMD). The DMD includes a first metal line, a second metal line, a third metal line, and a mirror. The first metal line is formed to have a predetermined line width and a predetermined thickness, and the second metal line is formed to have... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070051986 - Image sensor and method of fabricating the same: An image sensor is provided. The image sensor includes a substrate having a plurality of cell regions, photodiodes formed in the cell regions of the substrate an antireflection layer, a color filter layer, a planarization layer, and a plurality of microlenses. The antireflection layer is formed above the substrate including... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070051988 - Solid-state imaging device, drive method of solid-state imaging device, and imaging apparatus: A solid-state imaging device that includes: a pixel array section configured by an array of a unit pixel, including an optoelectronic conversion section that subjects an incoming light to optoelectronic conversion and stores therein a signal charge, a transfer transistor that transfers the signal charge stored in the optoelectronic conversion... Agent: Robert J. Depke Lewis T. Steadman

20070051989 - Trench photosensor for a cmos imager: A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on... Agent: Dickstein Shapiro LLP

20070051990 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes: a semi conductor substrate of a first conductivity type having a photodiode region and a transistor region defined therein; a gate electrode formed above the transistor region of the semiconductor substrate with... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070051991 - Cmos image sensor and method for fabricating the same: Provided are a CMOS image sensor and a method for fabricating the same. The CMOS image sensor including: a metal pad formed on a pad region of a substrate; an insulation layer formed on the entire surface of the substrate, and having a metal pad opening part to expose a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070051992 - Cmos image sensor and method of fabricating the same: Provided are a CMOS image sensor and a fabricating method thereof. The CMOS image sensor includes a device isolation layer, a plurality of photodiode regions, an interlayer insulating layer, a refracting layer, a planarizing layer, a color filter layer, and a plurality of microlenses. The refracting layer, with a higher... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070051994 - Dual-gate dynamic random access memory device having vertical channel transistors and method of fabricating the same: A dynamic random access memory (DRAM) device has dual-gate vertical channel transistors. The device is comprised of pillar-shaped active patterns including source regions contacting with a semiconductor substrate, drain regions formed over the drain regions, and channel regions formed between the source and drain regions. The active patterns are disposed... Agent: Mills & Onello LLP

20070051996 - Method of forming a mosfet with dual work function materials: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell... Agent: International Business Machines Corporation Dept. 18g

20070051993 - Method of forming thin film transistor and poly silicon layer of low-temperature poly silicon thin film transistor: A method of forming a thin film transistor is provided. First, an amorphous silicon layer is formed on a substrate. Next, a first gate insulating layer is formed on the amorphous silicon layer. Then, an annealing process is performed so that the amorphous silicon layer is melted and re-crystallized to... Agent: J C Patents, Inc.

20070051995 - Mos transistor cell and semiconductor device: A MOS transistor cell having a salicide structure has a plurality of gate wires each formed as a straight line with a constant width. Each of the gate wires includes a P-channel gate terminal and an N-channel gate terminal. The P-side ends and the N-side ends of the gate wires... Agent: Mcdermott Will & Emery LLP

20070051997 - Semiconductor memory device: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced... Agent: Knobbe Martens Olson & Bear LLP

20070051999 - Ferroelectric capacitor having three-dimensional structure, nonvolatile memory device having the same and method of fabricating the same: A ferroelectric capacitor having a three-dimensional structure, a nonvolatile memory device having the same, and a method of fabricating the same are provided. The ferroelectric capacitor may include a trench-type lower electrode, at least one layer formed around the lower electrode, a ferroelectric layer (PZT layer) formed on the lower... Agent: Harness, Dickey & Pierce, P.L.C

20070051998 - Semiconductor memory device with dielectric structure and method for fabricating the same: A semiconductor memory device with a dielectric structure and a method for fabricating the same are provided. The dielectric structure includes: a first dielectric layer having a dielectric constant of approximately 25 or higher; a second dielectric layer including a material having a crystallization rate lower than the first dielectric... Agent: Blakely Sokoloff Taylor & Zafman

20070052000 - Nonvolatile memory device and method for fabricating the same: A nonvolatile memory device and method for fabricating the same are provided. The nonvolatile memory device includes an active region; a source region formed in the active region; a source line formed on the source region and electrically connected with the source region, to cross over the active region; word... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070052001 - Nonvolatile semiconductor memory device and method of fabricating the same: A nonvolatile semiconductor memory device and a method of fabricating the same are provided. The nonvolatile memory device may include a switching device and a storage node connected to the switching device. The storage node may comprise a lower electrode, a data storing layer, and an upper electrode. The data... Agent: Harness, Dickey & Pierce, P.L.C

20070052005 - Flash memory and a method of manufacturing the same: The present invention provides a method of manufacturing a flash memory device. The method includes forming a gate oxide layer on a semiconductor substrate, forming a floating gate including protrusions and depressions on its surface by patterning polysilicon deposited on the gate oxide layer, depositing a dielectric layer on the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070052002 - Junction leakage suppression in memory devices: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a... Agent: Harrity & Snyder, L.l.p.

20070052003 - Method for producing a memory with high coupling ratio: A method for producing a memory with high coupling ratio is provided. First, a shallow trench isolation is formed on a substrate to define an active area. Second, a spacer is formed at the sidewall of the shallow trench isolation. Third, the shallow trench isolation is etched such that the... Agent: Rosenberg, Klein & Lee

20070052004 - Method of manufacturing nano crystals and application of the same: A method of manufacturing nano crystals disclosed herein is applicable to the fabrications of memory device and solar cell. The method of manufacturing nano crystals at least comprises steps of: providing a substrate with a thin film formed thereon, and transforming the thin film into the nano crystals by laser... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070052006 - Semiconductor memory device and method for manufacturing the same: To prevent the extraction of electrons from the floating gate during a read operation. A semiconductor memory device comprises a selection gate 3a provided in a first region on a substrate 1 through an insulating film 2, a floating gate 6a provided in a second region adjacent to the first... Agent: Mcginn Intellectual Property Law Group, Pllc

20070052007 - Split gate type non-volatile memory device and method of manufacturing the same: A non-volatile memory device (e.g., a split gate type device) and a method of manufacturing the same are disclosed. The memory device includes an active region on a semiconductor substrate, a pair of floating gates above the active region, a charge storage insulation layer between each floating gate and the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20070052008 - Memory structure with high coupling ratio: A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall... Agent: Rosenberg, Klein & Lee

20070052009 - Phase change memory device and method of making same: A phase change random access memory (PRAM) element is provided that is driven by a MOSFET. The MOSFET includes, for example, a source region, a drain region, and a gate electrode disposed between the source region and the drain region. An insulator layer (e.g., oxide layer) separates the gate electrode... Agent: Vista Ip Law Group LLP

20070052010 - Memory cell and method for manufacturing the same: The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the... Agent: Jianq Chyun Intellectual Property Office

20070052011 - Scalable multi-functional and multi-level nano-crystal non-volatile memory device: A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from... Agent: Leffert Jay & Polglaze, P.a.

20070052012 - Vertical tunneling nano-wire transistor: A vertical nano-wire transistor is formed on a substrate out of a vertical pillar having active regions of opposing conductivity in opposite ends of the pillar. In one embodiment, the source region is a p+ region in the substrate under the pillar and the drain region is an n+ region... Agent: Leffert Jay & Polglaze, P.a.

20070052013 - Semiconductor device having decoupling capacitor and method of fabricating the same: A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of... Agent: Mills & Onello LLP

20070052014 - Trench semiconductor device of improved voltage strength, and method of fabrication: A trench IGBT is disclosed which includes a semiconductor substrate having formed therein a set of cell trenches formed centrally and a set of annular guard trenches concentrically surrounding the cell trenches. The cell trenches receive cell trench conductors via cell trench insulators for providing IGBT cells. The guard trenches... Agent: Woodcock Washburn LLP

20070052015 - Semiconductor device: Aiming at realizing high breakdown voltage and low ON resistance of a semiconductor device having the super-junction structure, the semiconductor device of the present invention has a semiconductor substrate having an element forming region having a gate electrode formed therein, and a periphery region formed around the element forming region,... Agent: Young & Thompson

20070052016 - Semiconductor device and manufacturing method thereof: In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the present invention, for example, a... Agent: Fish & Richardson P.c.

20070052017 - Semiconductor device and manufacturing method therefor: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration... Agent: Ingrassia Fisher & Lorenz, P.c.

20070052018 - Method of providing electrical separation in intergrated devices and related device: An integrated device includes two sections, such as a DFB laser and an EAM modulator, having a semi-insulating separation region therebetween. The separation region is of a material acting as a trap on electrons and configured to impede current flow between the two sections due to holes. The separation region... Agent: Avago Technologies, Ltd.

20070052025 - Oxide semiconductor thin film transistor and method of manufacturing the same: Provided is a thin film transistor comprising a channel layer comprised of an oxide semiconductor containing In, M, Zn, and O, M including at least one selected from the group consisting of Ga, Al, and Fe. The channel layer is covered with a protective film.... Agent: Fitzpatrick Cella Harper & Scinto

20070052026 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed, which comprises a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulating film formed on a channel region between the source/drain regions, a gate electrode formed on the gate insulating film, and a sidewall insulating film formed on a sidewall surface of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070052023 - Thin film transistor and method of fabricating the same: A thin film transistor and a method of fabricating the same are disclosed. The method includes: sequentially depositing an amorphous silicon layer, a capping layer, and a metal catalyst layer; annealing the entire layer to crystallize the amorphous silicon layer into a polysilicon layer; removing the capping layer; and, when... Agent: Knobbe Martens Olson & Bear LLP

20070052020 - Thin film transistor and method of manufacturing the same: A Thin Film Transistor comprises a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region disposed on the gate insulation layer and above the gate electrode; a doped a-Si region formed on the a-Si region; the source and drain metal... Agent: Rabin & Berdo, Pc

20070052024 - Thin film transistor having a nano semiconductor sheet and method of manufacturing the same: Provided are a nano semiconductor sheet, a thin film transistor (TFT) using the nano semiconductor sheet, and a flat panel display using nano semiconductor sheet. The nano semiconductor sheet has excellent characteristics, can be manufactured at room temperature, and has good flexibility. The nano semiconductor sheet includes: a first film... Agent: Knobbe Martens Olson & Bear LLP

20070052022 - Thin film transistor, method of fabricating the same, and a display device including the thin film transistor: A thin film transistor (TFT), a method of fabricating the same, and a display device including the TFT, are provided. In the TFT, a channel region is connected to a gate electrode so that the influence of a substrate bias is reduced or eliminated. Thus, the threshold voltage of the... Agent: Christie, Parker & Hale, LLP

20070052019 - Transistor device wiwth metallic electrodes and a method for use in forming such a device: A transistor device having a metallic source electrode, a metallic drain electrode, a metallic gate electrode and a channel in a deposited semiconductor material, the transistor device comprising: a first layer comprising the metallic gate electrode, a first metal portion of the metallic source electrode and a first metal portion... Agent: Hewlett Packard Company

20070052021 - Transistor, and display device, electronic device, and semiconductor device using the same: It is an object of an invention disclosed in the present specification to provide a transistor having low contact resistance. In the transistor, a semiconductor film including an impurity element imparting P-type or N-type conductivity, an insulating film formed thereover, and an electrode or a wiring that is electrically connected... Agent: Nixon Peabody, LLP

20070052027 - Hybrid schottky source-drain cmos for high mobility and low barrier: A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of... Agent: Slater & Matsil, L.l.p.

20070052028 - Semiconductor memory device including an soi substrate: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain... Agent: Mcdermott Will & Emery LLP

20070052030 - Electrostatic discharge device with controllable holding current: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a... Agent: J C Patents, Inc.

20070052029 - Electrostatic discharge protection structure: The invention provides an ESD protection structure, compatible with the bipolar-CMOS-DMOS (BCD) processes, which provides an enhanced protection performance and better heat dissipation performance. The design of the ESD structures in present invention takes advantage of bipolar punch characteristics of the parasitic bipolar structure to bypass the ESD current, thus... Agent: J C Patents, Inc.

20070052031 - Semiconductor device and method for manufacturing the same: It is made possible to easily set a protection voltage even when a semiconductor device to be protected includes a gate insulating film having a low dielectric breakdown voltage. A semiconductor device includes: a MOS transistor including a first gate insulating film provided on a first element region of first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070052032 - Electrostatic discharge device with latch-up immunity: An electrostatic discharge (ESD) device with latch-up immunity is provided. The ESD device has an equivalent SCR structure when a supply voltage is not applied thereto and has an equivalent PN diode structure when the supply voltage is applied thereto, thus freeing the ESD device from the latch-up phenomenon.... Agent: J C Patents, Inc.

20070052033 - Load driving device: A load driving device includes a drive control signal generation circuit generating a load drive control signal and a semiconductor buffer circuit generating an output signal in response to the load drive control signal. The buffer circuit has a pair of gate driven switching elements which are connected to each... Agent: Volentine Francos, & Whitt Pllc

20070052034 - Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors: A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate... Agent: Texas Instruments Incorporated

20070052035 - Method and apparatus for reducing optical crosstalk in cmos image sensors: An image sensor in which the metal interconnects are coated with an anti-reflective coating is disclosed. The top, bottom and sides of the metal interconnects may be coated to reduce reflection from all directions. The thickness of the coating is chosen to suppress reflection of light of certain wavelengths incident... Agent: Perkins Coie LLP

20070052037 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. A semiconductor device includes a first transistor and a second transistor. The first transistor comprises at least one first gate electrode including a first metal layer. The second transistor comprises at least one second gate electrode including the first metal layer.... Agent: Slater & Matsil LLP

20070052036 - Transistors and methods of manufacture thereof: Transistors and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having a first gate electrode comprising a first thickness, and an NMOS transistor having a first gate electrode comprising a second thickness, wherein the first thickness is greater than the second... Agent: Slater & Matsil LLP

20070052038 - Semiconductor device and method for fabricating the same: A semiconductor device that suppresses variation and a drop in the breakdown voltage of transistors. In the semiconductor device in which a logic transistor and a high-breakdown-voltage transistor are formed on one Si substrate, an insulating film which has an opening region and which is thick around the opening region... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070052039 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a silicon region including Si, and a silicide film provided on the silicon region, the silicide film comprising a compound of Si with Ni, Co, Pd, or Pt and including Er.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070052040 - Transistor with contoured channel and method for making the same: A transistor structure such as a FinFET is formed in a semiconductor substrate with a surface contour having an upper surface at least partially bounded by sidewalls of trenches in the semiconductor substrate. First and second source/drain regions are arranged along the upper surface of the surface contour, with a... Agent: Edell, Shapiro & Finnan, Llc

20070052041 - Semiconductor device and method of fabricating the same: A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on... Agent: Mcdermott Will & Emery LLP

20070052042 - Semiconductor device and method for manufacturing the same: In order to provide a semiconductor device having good quality by keeping the relative permittivity of a High-K insulation film in a high state, or to provide a method for manufacturing a semiconductor device in which the relative permittivity of the High-K insulation film can be kept in a high... Agent: Crowell & Moring LLP Intellectual Property Group

20070052043 - Multilayer gate electrode, semiconductor device having the same and method of fabricating the same: Example embodiments relate to a multilayer gate electrode, a semiconductor device having the same and methods of fabricating the same. Other example embodiments relate to a semiconductor device with a multilayer gate electrode which is relatively stable at higher temperatures, has improved resistance characteristics and improved reliability, and methods of... Agent: Harness, Dickey & Pierce, P.L.C

20070052044 - Scrolling input arrangements using capacitive sensors on a flexible membrane: Scrolling input arrangements are presented including: a flexible membrane; a number of capacitive sensors mechanically integrated with the flexible membrane, the capacitive sensors radially disposed with respect to a first axis that is perpendicular with respect to the flexible membrane; an integrated circuit mechanically coupled with the flexible membrane and... Agent: Ipsg, P.c.

20070052045 - Thin membrane alignment method using patterned nanomagnets: A passive nanomagnet alignment method is described to self-align a membrane to another surface. The membrane and the surface each have a plurality of nanomagnets patterned on it, wherein the nanomagnets are magnetized based on an applied external magnetic field. The membrane is brought into close proximity and coarse alignment... Agent: Gauthier & Connors LLP

20070052046 - Pressure sensors and methods of making the same: A pressure sensor includes a base substrate silicon fusion bonded to a cap substrate with a chamber disposed between the base substrate and the cap substrate. Each of the base substrate and the cap substrate include silicon. The base substrate includes walls defining a cavity and a diaphragm portion positioned... Agent: Cantor Colburn, LLP

20070052047 - Metal contact systems for semiconductor-based pressure sensors exposed to harsh chemical and thermal environments: Highly corrosion resistant electrically conductive contact systems suitable for semiconductor pressure sensor devices exposed to acidic, elevated temperature environments, such as automotive exhaust gas environments, are disclosed. The preferred embodiment (10) comprises a platinum top layer (26), and a tantalum lower layer (24). Both are highly electrically conductive layers and... Agent: Sensata Technologies, Inc.

20070052049 - Integrated opto-electric spr sensor: An integrated opto-electric sensor includes a wavenumber matching structure that is integrated onto a silicon substrate, and a first conductive electrode that is adjacent to one of a lightly doped and an undoped region in the silicon substrate to form a Schottky junction. A dielectric is positioned adjacent to the... Agent: Agilent Technologies Inc.

20070052048 - Strain compensated high electron mobility transistor: A semiconductor structure having a III-V substrate; a first III-V donor layer having a relatively wide bandgap disposed over the substrate; a III-V channel layer having a relatively narrow bandgap disposed on the donor layer; a second III-V donor layer disposed on the channel layer having a relatively wide bandgap.... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20070052050 - Backside thinned image sensor with integrated lens stack: A method and apparatus for a backside thinned image sensor with an integrated lens stack.... Agent: Daniel E. Ovanezian Blakely, Sokoloff, Taylor & Zafman LLP

20070052051 - Photoelectric conversion layer, photoelectric conversion device and imaging device, and method for applying electric field thereto: m

20070052052 - Use of nanoscale particles for creating scratch-resistant protective layers on semiconductor chips: Inorganic-based nanoparticles, such as nanoparticles based on silicon dioxide, are used in order to produce protective layers for semiconductor chips having scratch-resistant properties. The nanoparticles are preferably processed to form a sol, which is applied onto the semiconductor chips to be coated and subsequently converted by sintering into the protective... Agent: Edell, Shapiro & Finnan, Llc

20070052055 - Capacitor over red pixel: A red pixel having a capacitor formed over the photo-conversion region of the pixel. The capacitor can be used by other pixels as a common capacitor. The capacitor is coupled to floating diffusion region shared by a plurality of pixels. The plurality of pixels also share readout circuitry.... Agent: Dickstein Shapiro LLP

20070052054 - Cmos imager with nitrided gate oxide and method of fabrication: A CMOS imager having reduced dark current and methods of forming the same. A nitrided gate oxide layer having approximately twice the thickness of a typical nitrided gate oxide is provided over the photosensor region of a CMOS imager. The gate oxide layer provides an improved contaminant barrier to protect... Agent: Dickstein Shapiro LLP

20070052053 - Complementary metal oxide semiconductor image sensor and fabricating method thereof: A CMOS image sensor including a light-receiving element, at least one transistor, a first dielectric layer, a reflective layer, a second dielectric layer, a protective layer, a material layer, a transparent material layer, an optical filter, and a converging element is described. The light-receiving element and the transistor are disposed... Agent: Jianq Chyun Intellectual Property Office

20070052056 - Solid-state imaging device and method of manufacturing same: A solid-state imaging device includes: a semiconductor substrate; and a signal processing section provided on a backside of the semiconductor substrate. The semiconductor substrate has; a first impurity region of a first conductivity type, the first impurity region storing a signal charge produced through photoelectric conversion by a photoelectric conversion... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.c.

20070052057 - Method and schottky diode structure for avoiding intrinsic npm transistor operation: A Schottky diode includes an isolation region of a first conductivity type and an anode region of a second conductivity type isolated by the isolation region, the anode region including a lightly doped deep anode region of the second conductivity type and an increased dopant region of the second conductivity... Agent: Texas Instruments Incorporated

20070052058 - High blocking semiconductor component comprising a drift section: A semiconductor component having a drift path (2) which is formed in a semiconductor body (1), is composed of a semiconductor material of first conductance type. The drift path (2) is arranged between at least one first and one second electrode (3, 4) and has a trench structure in the... Agent: Baker Botts, L.l.p.

20070052059 - Structure for decreasing minimum feature size in an integrated circuit: A single, controlled etch step can be used to form a sharp tip feature along a sidewall of an etch feature. An etch process is used that is selective to a layer of tip material relative to the substrate upon which the layer is deposited. A lag can be created... Agent: Stallman & Pollock LLP

20070052060 - Dmos transistor with floating poly-filled trench for improved performance through 3-d field shaping: One or more vertical DMOS transistors, such as trench FETS, are formed between opposing floating poly-filled trench portions. The opposing trench portions may include two parallel trenches, rectangular trenches, hexagonal trenches, octagonal trenches, circular trenches, or other shapes. The floating trench portions are capacitively coupled to assume a potential somewhere... Agent: Patent Law Group LLP

20070052061 - Semiconductor layer with laterally variable doping, and method for producing it: A semiconductor layer with laterally variable doping, and a method for producing it are disclosed. The trenches here are no longer filled up completely with doped semiconductor material. Instead, a doped balancing layer is deposited in a sense as a lining on the walls of the trenches. The doped balancing... Agent: Lerner Greenberg Stemer LLP

20070052062 - Vertical lc tank device: An LC tank structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring... Agent: Schmeiser, Olsen & Watts

20070052063 - Semiconductor device: An electric fuse includes a wide interconnect and a narrow interconnect. The electric fuse has a juxtaposed region in which a plurality of straight line portions are juxtaposed with each other by folding the wide interconnect and the narrow interconnect has a narrower width than that of the wide interconnect,... Agent: Young & Thompson

20070052064 - Semiconductor device and programming method therefor: A semiconductor device is provided which includes a pair of metal interconnections (B, C) provided above a semiconductor substrate (10), a program layer (20) provided over the pair of metal interconnections (B, C) and in which an opening (21) may be selectively formed in the program layer (20) on the... Agent: Ingrassia Fisher & Lorenz, P.c.

20070052065 - Semiconductor device and method of manufacturing the same: A semiconductor device comprising a substrate and a ferroelectric capacitor formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film interposed between the lower and upper electrodes. The ferroelectric capacitor having sidewalls receded from sidewalls of the upper electrode.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.c.

20070052066 - Bipolar method and structure having improved bvceo/rcs trade-off made with depletable collector columns: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in... Agent: Min, Hsieh & Hack LLP

20070052067 - Semiconductor device, method of manufacturing the same, circuit board, and method of manufacturing the same: In the semiconductor device of the present invention, an active region is formed in an upper surface of a semiconductor substrate, and is surrounded by a trench filled with an oxide. A through-hole electrode electrically connected to the active region extends from the upper surface of the semiconductor substrate to... Agent: Morrison & Foerster LLP

20070052068 - Semiconductor device: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad.... Agent: Mcdermott Will & Emery LLP

20070052069 - Integrated conductor arrangement and corresponding production method: An integrated conductor arrangement comprises a substrate with a top side, at least one tubular conductor trench provided in the substrate below the top side of the substrate and a conductor. The conductor comprises at least one tubular conductor layer and is integrated in the conductor trench.... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070052070 - Die pad for semiconductor packages and methods of making and using same: A semiconductor device package comprising a semiconductor device and an electrically conductive lead frame at least partially covered by a molding compound. The electrically conductive lead frame includes a plurality of leads disposed proximate a perimeter of the package and a die pad disposed in a central region formed by... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20070052071 - Semiconductor package and manufacturing method thereof: It is configured to comprise a semiconductor chip 110, a resin member 106 for forming a cavity 109 in which this semiconductor chip 110 is installed, and wiring 105 constructed of pattern wiring 105b formed so as to be exposed to a lower surface 106a of this resin member 106... Agent: Rankin, Hill, Porter & Clark LLP

20070052072 - Resin mold type semiconductor device: A semiconductor device includes: a semiconductor element; a metallic plate having a heat radiation surface; a terminal connecting to the element; and a resin mold covering the element, the plate and the terminal. The metallic plate provides an electrode of the semiconductor element. The heat radiation surface is capable of... Agent: Posz Law Group, Plc

20070052074 - Optical coupling element, method for producing the optical coupling element, and electronic device equipped with the optical coupling element: After a light emitting element is mounted to a header of a light emitting lead frame, a light receiving element is mounted to a header of a light receiving lead frame and a power element is mounted to a header of a power lead frame, the light emitting element, the... Agent: Birch Stewart Kolasch & Birch

20070052076 - Partially patterned lead frames and methods of making and using the same in semiconductor packaging: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is disclosed, wherein the method lends itself to better automation of the manufacturing line as well as to improving the quality and reliability of the packages produced therefrom. This is... Agent: White & Case LLP Patent Department

20070052075 - Semiconductor device and method of manufacturing the same: A semiconductor device is provided including a semiconductor element having a plurality of electrodes, a plurality of bonding portions of a lead frame, a plate-like current path material which electrically connects at least one of the plurality of electrodes and one of the plurality of bonding portions, a housing which... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.c.

20070052073 - Semiconductor device, lead frame used in the semiconductor device and electronic equipment using the semiconductor device: A semiconductor chip 23 is mounted on an island section 22 in a lead frame composed of a lead having the island section 22, a ground-bonding lead section 28 and a lead 21a each continuing in sequence, and other lead terminal sections 21b to 21d, and then a grounding electrode... Agent: Birch Stewart Kolasch & Birch

20070052077 - Low height vertical sensor packaging: A system and method for packaging a magnetic sensor is described. A sensor die is constructed such that connection pads are situated on two opposing sides of the die in two vertical arrays. Bonding wires connect the connection pads on the sensor die to wire bond pads on a substrate.... Agent: Honeywell International Inc.

20070052078 - Matrix package substrate structure, chip package structure and molding process thereof: A matrix package substrate molding process is provided. First, a matrix package substrate with a plurality of package units for disposing chips on the package units is provided. Next, an encapsulation mold is disposed on each of the package units. The mold has a plurality of mold cavities arranged as... Agent: Jianq Chyun Intellectual Property Office

20070052079 - Multi-chip stacking package structure: A multi-chip stacked package structure, including a leadframe base thin package structure with two or more chips in the stacking structure, is provided that is capable of including two or more stacked chips that reduce the total stacking thickness. The package structure also reduces stacking thickness by achieving stacking of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070052084 - High density interconnect assembly comprising stacked electronic module: A microelectronic module is provided with one or more first conductive pads on at least one of the exterior surfaces of the module for electrical interconnection of the functionality of the module to one or more second conductive pads on a second surface such as printed circuit board. A high... Agent: W. Eric Boyd, Esq. Irvine Sensors Corporation

20070052082 - Multi-chip package structure: A multi-chip package structure including a carrier, a first chip having an active surface and a rear surface, multiple bumps, a second chip, multiple first bonding wires, a package unit disposed above the first chip, a spacer disposed between the package unit and the first chip, multiple second bonding wires,... Agent: Jianq Chyun Intellectual Property Office

20070052081 - Package-on-package semiconductor assembly: Disclosed are methods and devices for providing improved semiconductor packages and POP IC assemblies using the improved packages with reduced warping. According to disclosed embodiments of the inventions, a packaged semiconductor device for use in a POP assembly includes an encapsulated region generally defined by the substrate surface. The encapsulant... Agent: Texas Instruments Incorporated

20070052083 - Semiconductor package and manufacturing method thereof: A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so... Agent: Rankin, Hill, Porter & Clark LLP

20070052080 - Three-dimensional interconnect interposer adapted for use in system in package and method of making the same: A three-dimensional interconnect interposer adapted for use in system in package (SIP) includes a wafer, at least an embedded passive device and at least an interconnect pattern disposed on the front surface of the wafer, a plurality of cavities exposing the inner contact pads of the interconnect pattern formed on... Agent: North America Intellectual Property Corporation

20070052085 - Semiconductor device: In a semiconductor device, a pad metal has at least a portion located immediately under a probe region, and the portion is divided into a plurality of narrow metal layers each arranged in parallel with a traveling direction of a probe. Thus, it is possible to enhance surface flatness of... Agent: Steptoe & Johnson LLP

20070052086 - Electronic parts and method of manufacturing electronic parts packaging structure: A method of manufacturing an electronic parts packaging structure of the present invention, includes a step of mounting an electronic parts, which has a connection terminal and a passivating film to cover the connection terminal, on a mounted body to direct the connection terminal upward, a step of forming an... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070052087 - Method and apparatus for decoupling conductive portions of a microelectronic device package: A method and apparatus for decoupling conductive portions of a microelectronic device package. In one embodiment, the package can include a microelectronic substrate and a conductive member positioned at least proximate to the microelectronic substrate. The conductive member can have first and second neighboring conductive portions with at least a... Agent: Perkins Coie LLP Patent-sea

20070052088 - Integrated circuit device: To solve the problems caused by accumulation of heat generated from an integrated circuit. The integrated circuit device of the invention includes a substrate over one surface of which an integrated circuit is formed. The other surface of the substrate (a surface over which the integrated circuit is not formed)... Agent: Eric Robinson

20070052089 - Adhesive film having multiple filler distribution and method of manufacturing the same, and chip stack package having the adhesive film and method of manufacturing the same: Disclosed herein are an adhesive film having a multiple filler distribution and a method of manufacturing the same, and a chip stack package having the adhesive film and a method of manufacturing the same. The adhesive film may have an upper film layer with a high concentration of fillers with... Agent: Harness, Dickey & Pierce, P.L.C

20070052090 - Semiconductor chip package and method of manufacturing the same: A semiconductor chip package may include a circuit board and a semiconductor chip that may be attached to the circuit board so as to be electrically connected to the circuit board. An intermediate pattern for reducing stress may be provided on a surface of the semiconductor chip that may face... Agent: Harness, Dickey & Pierce, P.L.C

20070052091 - Electronic device and method of manufacturing same: The device of the invention comprises a semiconductor element, a first connection element, a first patterned electrically conductive layer and a second patterned electrically conductive layer. The device is further provided with an encapsulation that encapsulates all except the first conductive layer, which is part of the substrate. The device... Agent: Philips Intellectual Property & Standards

20070052092 - Interconnection structure: An interconnection structure for a pad region of the substrate is provided. A semiconductor circuit and a pad are disposed on the substrate of the pad region. The interconnection structure includes a first and a second dielectric layers, via plugs and contact plugs. The patterned conductive layer includes an auxiliary... Agent: J C Patents, Inc.

20070052093 - Ultrasonic transducer and manufacturing method thereof: Disclosed is an improved construction of an ultrasonic transducer, wherein a charge is not easily injected into an insulating film even when the bottom of a membrane comes in contact with a lower electrode, and a manufacturing method thereof without using the wafer laminating technique. The ultrasonic transducer includes a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070052095 - Semiconductor device and manufacturing method thereof: Provided is a technology capable of improving the reliability of a semiconductor device using WPP by preventing a short-circuit failure between uppermost-level interconnects. In the present invention, a buffer layer is formed between an uppermost-level interconnect and redistribution interconnect. The uppermost-level interconnect is made of a copper film, while the... Agent: Mattingly, Stanger, Malur & Brundidge, P.c.

20070052094 - Semiconductor wafer level chip package and method of manufacturing the same: A semiconductor chip package may include one or more conductive patterns provided on a front surface of a wafer. An encapsulation layer may cover at least the front surface of the wafer. Chip plugs may be electrically connected to the conductive patterns, and may be embedded in a rear surface... Agent: Harness, Dickey & Pierce, P.L.C

20070052096 - Semiconductor device and method for forming the same: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070052097 - Electronic device and method of manufacturing thereof: The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with an connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. It is at least partially... Agent: Philips Intellectual Property & Standards

20070052098 - Metal line for a semiconductor device and fabrication method thereof: A metal line, which can be used in a semiconductor device structure less than 65 nm in size by forming a barrier metal of an anti-diffusion layer for a copper line using CVD TiSiN, and a fabrication method thereof are provided. The metal line includes: a semiconductor substrate having a... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070052099 - Protective barrier layer for semiconductor device electrodes: A semiconductor device includes a die with at least one electrode on a surface thereof, at least one solderable contact formed on the electrode, and a passivation layer formed over the electrode and including an opening that exposes the solderable contact. The passivation layer opening may be wider than the... Agent: Ostrolenk Faber Gerb & Soffen

20070052102 - Integrated circuit chip and manufacturing process thereof: An integrated circuit chip includes a substrate, a device layer, an interconnection layer, a sealing base layer and a sealing ring stack layer. The substrate has a sealing region and a chip region. The sealing region is disposed around the chip region. The device layer is disposed within the chip... Agent: Birch Stewart Kolasch & Birch

20070052101 - Semiconductor apparatus and manufacturing method thereof: A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first... Agent: Young & Thompson

20070052100 - Spring clip for a portable electronic device: A portable electronic device spring clip including a first retention section adapted to attach the spring clip to a framework; a second retention section adapted to be located at a top side of a metal cover frame of a display module of a portable electronic device; a first contact section... Agent: Harrington & Smith, LLP

20070052103 - Tin layer structures for semiconductor devices, methods of forming the same, semiconductor devices having tin layer structures and methods of fabricating the same: TiN layer structures for semiconductor devices, methods of forming TiN layer structures, semiconductor devices having TiN layer structures and methods of fabricating semiconductor devices are disclosed. The TiN layer structure for a semiconductor device includes a TiN base layer and a conductive capping layer. The TiN base layer is formed... Agent: Harness, Dickey & Pierce, P.L.C

20070052104 - Grafted seed layer for electrochemical plating: Generally, the process includes depositing a barrier layer and seed layer on a feature formed in a dielectric layer, performing a grafting process, initiating a copper layer and then filing the feature by use of a bulk copper fill process. Copper features formed according to aspects described herein have desirable... Agent: Patterson & Sheridan, LLP

20070052105 - Metal duplex method: Methods and articles are disclosed. The methods are directed to depositing nickel duplex layers on substrates to inhibit corrosion and improve solderability of the substrates. The substrates have a gold or gold alloy finish.... Agent: John J. Piskorski Rohm And Haas Electronic Materials Llc

20070052107 - Multi-layered structure and fabricating method thereof and dual damascene structure, interconnect structure and capacitor: A dual damascene structure comprising a substrate, a dielectric layer, a metal hard mask layer, a protection layer and a conductive layer is provided. The substrate has a conductive area. The dielectric layer is disposed on the substrate. The metal hard mask layer is disposed on the dielectric layer. The... Agent: Jianq Chyun Intellectual Property Office

20070052106 - Semiconductor device and method for fabricating the same: A first mark formed simultaneously with the process step for forming a layer of metal interconnects is partly exposed at two parallel side surfaces of the separated semiconductor device or one side surface thereof to have a rectangular shape. This allows the identification of the orientation and product information of... Agent: Jack Q. Lever, Jr. Mcdermott, Will & Emery L.l.p.

20070052108 - Semiconductor package with getter formed over an irregular structure: A semiconductor package includes a substrate having a first surface portion in a cavity. The first surface portion includes an artificially formed grass structure. The package includes a getter film formed over the grass structure.... Agent: Hewlett-packard Company Intellectual Property Administration

20070052109 - Flip-chip packaging process: A flip-chip packaging process is disclosed. The present invention is featured in forming a copper pillar on a wafer, forming a solder on a substrate; and enabling the solder to substantially cover the entire externally-exposed surface of the copper pillar, thereby connecting the copper pillar to the substrate. The copper... Agent: Birch Stewart Kolasch & Birch

20070052110 - Chip structure, chip package structure and bumping process thereof: A chip structure including a chip, a passivation layer, an elastic layer and a metal layer is provided, with a bump disposed on the metal layer for electrically connecting a bonding pad of the chip. The passivation layer and the elastic layer are covering an active surface of the chip,... Agent: Jianq Chyun Intellectual Property Office

20070052111 - Land grid array interposer compressive loading system: An electronic module and a method of assembling the electronic module. A circuit board is connected to a chip substrate by an array of connectors, and a base member is on the side of the circuit board away from the chip substrate and connector array. An elastomeric structure is placed... Agent: Delio & Peterson, Llc

20070052112 - Support with solder ball elements and a method for populating substrates with solder balls: The invention relates to a support (4) with solder ball elements (1) for loading substrates (2) with ball contacts. Furthermore, the invention relates to a system for loading substrates (2) with ball contacts and to a method for loading substrates (2) with ball contacts. For this purpose, the support (4)... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070052114 - Alignment checking structure and process using thereof: The invention provides an alignment checking structure with a checkered pattern comprising a plurality of metal squares and a plurality of non-metal squares that are arranged in alternation, in a first direction and a second direction, and the first direction is perpendicular to the second direction... Agent: J C Patents, Inc.

20070052113 - Alignment marks for polarized light lithography and method for use thereof: Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second... Agent: Slater & Matsil LLP

20070052115 - Semiconductor constructions: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some... Agent: Wells St. John P.s.

20070045604 - Resistance variable memory device with nanoparticle electrode and method of fabrication: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.... Agent: Dickstein Shapiro LLP

20070045605 - Method for fabricating chalcogenide-applied memory: A chalcogenide memory cell includes a lower electrode, a chalcogenide layer, and an upper electrode. The lower electrode includes a tapered cavity. The chalcogenide layer is formed in the tapered cavity of the lower electrode. One side of the chalcogenide layer is adjacent to the lower electrode. The upper electrode... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070045606 - Shaping a phase change layer in a phase change memory cell: A phase change memory cell includes a phase change layer of a phase change material on a semiconductor body. A hard mask structure is formed on the phase change layer and a resist mask is formed on the hard mask structure. A hard mask is formed by shaping the hard... Agent: Trop Pruner & Hu, PC

20070045607 - Algainn nitride substrate structure using tin as buffer layer and the manufacturing method thereof: The present invention discloses a AlGaInN nitride substrate structure using TiN as buffer layer and the manufacturing method thereof. The present invention deposits TiN having (111) surface onto the silicon substrate having (111) surface as a buffer layer, and grows III-V AlGaInN nitride epitaxy structure having (0001) surface. The present... Agent: Rosenberg, Klein & Lee

20070045609 - Quantum wells for light conversion: A solid state light emitting device according to the present invention comprises an emitter structure having an active region of semiconductor material and a pair of oppositely doped layers of semiconductor material on opposite sides of said active region. The active region emits light at a first wavelength in response... Agent: Koppel, Patrick & Heybl

20070045608 - Window interface layer of a light-emitting diode: This invention is about a window interface layer in a light-emitting diode which comprises an n-type GaAs substrate with an n-type ohmic electrode at the bottom side thereof; an n-type AlGaInP cladding layer formed atop the substrate; an undoped AlGaInP active layer formed atop the n-type cladding layer; a p-AlGaInP... Agent: Rosenberg, Klein & Lee

20070045610 - Transistor device with strained germanium (ge) layer by selectively growth and fabricating method thereof: A transistor device with strained Ge layer by selectively growth and a fabricating method thereof are provided. A strained Ge layer is selectively grown on a substrate, so that the material of source/drain region is still the same as that of the substrate, and the strained Ge layer serves as... Agent: Birch Stewart Kolasch & Birch

20070045611 - Mosfet with laterally graded channel region and method for manufacturing same: The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a... Agent: Scully, Scott, Murphy & Pressner, P.C.

20070045620 - Dual emission organic light emitting display device and method of driving the same: A dual emission organic light emitting display device and method of driving the same. The display device includes a pixel driver and an organic light emitting diode that can display different images on a top surface and a bottom surface and/or a same image on both the top and bottom... Agent: Christie, Parker & Hale, LLP

20070045622 - N-sulfonylaminocarbonyl containing compounds: Compounds having two reactive functional groups are described that can be used to provide a connector group between a substrate and an amine-containing material. The first reactive functional group can be used to provide attachment to a surface of a substrate. The second reactive functional group is a N-sulfonylaminocarbonyl group... Agent: 3m Innovative Properties Company

20070045615 - Non-volatile organic resistance random access memory device and method of manufacturing the same: A non-volatile organic resistance memory device including a first electrode, a second electrode, and a polyimide layer interposed between the first and second electrodes. The polyimide layer has a thickness such that a resistance of the polyimide layer varies in accordance with a potential difference between the first and second... Agent: Marger Johnson & Mccollom, P.C.

20070045616 - Organic light emitting display: An organic light emitting display provided according to the invention maintains light emission efficiency and elongates its lifetime by radiating heat generated from organic light emitting elements to the outside of an encapsulated area. In the organic light emitting display, a part of a cathode is extended to the outside... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070045617 - Organic light emitting display and method of manufacturing the same: An organic light emitting display (OLED) and a method of manufacturing the OLED is disclosed. The OLED, which has a transparent metal layer substantially preventing an oxide layer from forming on a pad metal, and a method of manufacturing the OLED are disclosed. The OLED includes a substrate, a display... Agent: Knobbe Martens Olson & Bear LLP

20070045618 - Organic semiconductor material, organic semiconductor element and field effect transistor using the same:

20070045613 - Organic semiconductor material, organic semiconductor structure and organic semiconductor apparatus: The present invention is directed to the provision of a liquid crystalline organic semiconductor material, which is highly stable under a film forming environment and, at the same time, can easily form a film, for example, by coating. The liquid crystalline organic semiconductor material comprises: a thiophene skeleton comprising 3... Agent: Burr & Brown

20070045614 - Organic semiconductor material, organic semiconductor structure and organic semiconductor apparatus: wherein A1, A2, B1, B2 and X each have a skeleton structure comprising L 6 π electron rings, M 8 π electron rings, N 10 π electron rings, O 12 π electron rings, P 14 π electron rings, Q 16 π electron rings, R 18 π electron rings, S 20... Agent: Burr & Brown

20070045612 - Organic thin film transistor and fabricating method thereof: An organic thin film transistor and a method for fabricating the same are provided. A multi-dielectric layer of the organic thin-film transistor is disposed on the substrate and the gate electrode, and then the organic layers-of the organic thin film transistor, the source and drain are produced. Because of the... Agent: Harness, Dickey & Pierce, P.L.C

20070045621 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to manufacture, with high yield, semiconductor devices in each of which an element which has a layer containing an organic compound is provided over a flexible substrate. A method for manufacturing a semiconductor device includes: forming a separation layer over a substrate;... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070045619 - Silsesquioxane-based compound and organic light-emitting device including the same: wherein R1, R2, R3, R4, R5, R6, R7, and R8 are as defined in the specification. The use of the silsesquioxane-based compound enables to produce an organic light-emitting device with improvement in electrical characteristics such as brightness and efficiency. The silsesquioxane-based compound can exhibit good film smoothness and adhesion, and... Agent: Robert E. Bushnell

20070045623 - Semiconductor device that is advantageous in operational environment at high temperatures: A semiconductor device comprises an N-type insulated-gate field-effect transistor including a first insulating layer that is provided along side walls of a gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region of the N-type insulated-gate field-effect transistor. The device also comprises a... Agent: Foley And Lardner LLP Suite 500

20070045624 - Method for manufacturing a thin-film transistor: A thin-film transistor is formed on a transparent substrate and has a gate electrode film layer and a source and drain regions, and further has an alignment mark made of one and the same constituent material as a constituent material of at least one of the gate electrode film layer... Agent: Katten Muchin Rosenman LLP

20070045626 - Electro-optical device and electronic apparatus having the same: An electro-optical device includes: a substrate; a plurality of pixels provided in a pixel region on the substrate; peripheral circuits that are provided in a peripheral region surrounding the pixel region, the peripheral circuits being for controling the plurality of pixels; a plurality of signal lines that supply signals for... Agent: Oliff & Berridge, PLC

20070045625 - Thin film transistor array substrate and method for repairing the same: A thin film transistor array substrate and method for repairing the same are provided. Repairing lines are formed when the data lines on the thin film transistor array substrate are defined. Furthermore, the protruding portions and branches of common lines overlap with the repairing lines and the data lines respectively.... Agent: J C Patents, Inc.

20070045628 - Thin film transistor and method for fabricating the same: Disclosed are a thin film transistor and a method for fabricating the same. The thin film transistor is capable of a fine current control. The thin film transistor includes a semiconductor layer comprising a channel; a gate electrode overlying the semiconductor layer; a source electrode connected to a first end... Agent: Knobbe Martens Olson & Bear LLP

20070045627 - Thin film transistor substrate and method of manufacturing the same: A thin film transistor substrate with good process efficiency and a method of manufacturing the same are provided. The thin film transistor substrate includes a first conductive type MOS transistor and a second conductive type MOS transistor. The first conductive type MOS transistor includes a first semiconductor layer formed on... Agent: Macpherson Kwok Chen & Heid LLP

20070045629 - White light led: A white light LED (light emitting diode) is disclosed. The white light LED comprises: a bracing frame; at least an UV (or a blue light) chip mounted on the bracing frame; and a flat thin film stacked on the UV chip and formed by mixing a main agent and a... Agent: Troxell Law Office PLLC Suite 1404

20070045630 - Electroluminescence apparatus and manufacturing method of the same: Quadrangular prism-like EL bars are each formed by depositing a light emitting layer and a positive hole transport layer on an outer surface of a data line. The EL bars are arranged in such a manner that each of the EL bars crosses a plurality of scanning lines formed on... Agent: Harness, Dickey & Pierce, P.L.C

20070045631 - Silicon carbide semiconductor device having high channel mobility and method for manufacturing the same: A silicon carbide semiconductor device having a MOS structure includes: a substrate; a channel area in the substrate; a first impurity area; a second impurity area; a gate insulating film on the channel area; and a gate on the gate insulating film. The channel area provides an electric current path.... Agent: Posz Law Group, PLC

20070045636 - Display substrate, method of manufacturing the same and display device having the same: A display substrate includes a substrate, a first insulating layer, an undercut compensating member, a first electrode, a second insulating layer and a first conductive pattern. The first insulating layer is formed on the substrate. The undercut compensating member is formed on the first insulating layer. The undercut compensating member... Agent: Cantor Colburn, LLP

20070045634 - Light emitting diode device: A light emitting diode device includes a main substrate, a reflective layer, a joint layer, a light emitting diode layer and a diffusing layer stacked in turn from bottom to top, a material of the main substrate is silicon, a material of the reflective layer is metal alloy, the diffusing... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070045635 - Light emitting diode device: A light emitting diode device includes a substrate, a reflective layer, a joint layer and a light emitting diode layer stacked in turn from bottom to top, a material of the main substrate being Cu or Al, and a material of the reflective layer being metal Al or Ag, or... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070045637 - Low cost ingaain based lasers: A method and structure for producing lasers having good optical wavefront characteristics, such as are needed for optical storage includes providing a laser wherein an output beam emerging from the laser front facet is essentially unobstructed by the edges of the semiconductor chip in order to prevent detrimental beam distortions.... Agent: Jones, Tullar & Cooper, P.C.

20070045632 - Microelectronic imaging units and methods of manufacturing microelectronic imaging units at the wafer level: Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies including integrated circuits, external contacts electrically coupled to... Agent: Dickstein Shapiro LLP

20070045633 - Semiconductor optical device having an improved current blocking layer and manufacturing method thereof: A semiconductor optical device includes an active layer, a current blocking layer on both sides of the active layers and a cladding layer on both the active layer and the current blocking layer. The current blocking layer includes a buried layer, at least one intermediate layer of Al(Ga)InAs and a... Agent: Leydig Voit & Mayer, Ltd

20070045638 - Iii-nitride light emitting device with double heterostructure light emitting region: A III-nitride light emitting layer is disposed between an n-type region and a p-type region. The light emitting layer is a doped thick layer. In some embodiments, the light emitting layer is sandwiched between two doped spacer layers.... Agent: Patent Law Group LLP

20070045639 - Semiconductor electronic device: A semiconductor electronic device includes a buffer layer formed on a substrate, and a semiconductor operating layer that is formed on the buffer layer. The semiconductor operating layer includes a nitride-based compound semiconductor and. The buffer layer includes at least one composite layer that includes a first layer and a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070045645 - Composite phosphor powder, light emitting device using the same and method for manufacturing composite phoshpor powder: The invention provides a high quality composite phosphor powder which ensures diversity in emission spectrum, color reproduction index, color temperature and color, a light emitting device using the same and a method for manufacturing the composite phosphor powder. The composite phosphor powder comprises composite particles. Each of the composite particles... Agent: Mcdermott Will & Emery LLP

20070045640 - Light emitting devices for liquid crystal displays: Light-emitting devices, and related components, processes, systems and methods are disclosed.... Agent: Wolf Greenfield & Sacks, PC

20070045644 - Light emitting diode package with diffuser and method of manufacturing the same: The invention relates to an LED package for facilitating color mixing using a diffuser and a manufacturing method of the same. The LED package includes a substrate with an electrode formed thereon, and an LED chip mounted on the substrate. The LED package also includes an encapsulant applied around the... Agent: Mcdermott Will & Emery LLP

20070045641 - Light source with uv led and uv reflector: A lighting source capable of producing white light using a semiconductor radiation source. The semiconductor radiation source may be an ultraviolet (“UV”) light emitting diode (“LED”) device that emits light at a short wavelength, e.g., near-violet or ultraviolet light. A thin film of phosphor may be deposited or coated on... Agent: Avago Technologies, Ltd.

20070045642 - Solid-state imager and formation method using anti-reflective film for optical crosstalk reduction: Conductive lines in an imaging device are coated with an anti-reflective film to reduce crosstalk caused by light reflecting from the conductive lines. An interface results between the anti-reflective film and the surface of the conductive line surface. A second interface exists between the anti-reflective film and an overlying insulating... Agent: Dickstein Shapiro LLP

20070045643 - Substrate-based white light diode: A substrate-based white light diode construction and manufacturing process comprised of having a blue-light chip attached to a substrate; blue-light chip and substrate circuitry contact being connected with a gold plated wire; blue-light chip inlaid into cavity of a mold; and fluorescent glue powder or cake being filled and preheated... Agent: Troxell Law Office PLLC

20070045646 - Surface mount optoelectronic component with lens: The invention relates to a surface mount optoelectronic component with a lens attachment, the method for precising the lens position and the method to manufacture the whole component.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070045647 - Display panel package: A display panel package includes a first electronic member, a second electronic member and an electrically conductive structure for electrically connecting the first electronic member and the second electronic member. The electrically conductive structure has a plurality of bumps electrically and spacedly connected to the first electronic member, and a... Agent: Bacon & Thomas, PLLC

20070045649 - Light source device: A light source device including a substrate, a first LED chip, a second LED chip, a third LED chip and a light guide element is provided. The first LED chip is disposed on one side of the substrate. The second LED chip is disposed on the other side of the... Agent: Rabin & Berdo, PC

20070045648 - Package structure of light emitting diode: A package structure of a light emitting diode for outputting a target peak wavelength includes a carrier, a first die and a second die. The first die is disposed on the carrier. The first die has a first peak wavelength greater than the target peak wavelength. The second die is... Agent: Birch Stewart Kolasch & Birch

20070045650 - Phosphor and blends thereof for use in leds: Phosphor compositions having the formula EueMmAaGgQqNnXx, where M is at least one of Be, Mg, Ca, Sr, Ba, Cd, Sn, Pb or Zn; A is at least one of B, Al, Ga, In, Bi, Sc, Y, La or a rare earth element other than Eu; G is at least one... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070045651 - Epitaxial wafer for a semiconductor light emitting device, method for fabricating the same and semiconductor light emitting device: A n-type GaAs buffer layer 2, a n-type GaInP buffer layer 3, a n-type AlGaInP cladding layer 4, an undoped AlGaAs guide layer 5, an AlGaAs/GaAs multiquantum well (MQW) active layer 6, a first p-type AlGaInP cladding layer 7, a p-type GaInP etching stopper layer 8, a second p-type AlGaInP... Agent: Foley And Lardner LLP Suite 500

20070045654 - Group iii-nitride semiconductor thin film, method for fabricating the same, and group iii-nitride semiconductor light emitting device: Disclosed herein is a high-quality group III-nitride semiconductor thin film and group III-nitride semiconductor light emitting device using the same. To obtain the group III-nitride semiconductor thin film, an AlInN buffer layer is formed on a (1-102)-plane (so called r-plane) sapphire substrate by use of a MOCVD apparatus under atmospheric... Agent: Mcdermott Will & Emery LLP

20070045653 - Selective filtering of wavelength-converted semiconductor light emitting devices: A structure includes a semiconductor light emitting device including a light emitting layer disposed between an n-type region and a p-type region. The light emitting layer emits first light of a first peak wavelength. A wavelength-converting material that absorbs the first light and emits second light of a second peak... Agent: Patent Law Group LLP

20070045652 - Semiconductor device: A semiconductor device is provided that includes a semiconductor substrate, a first resistance element on a semiconductor substrate, a capacitance element over the first resistance element, and an insulating layer between the first resistance element and the capacitance element.... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070045655 - Nitride semiconductor light emitting device: The invention relates to a high-output, high-efficiency nitride semiconductor light emitting device with low operating voltage and high resistance to electrostatic discharge. The nitride semiconductor light emitting device includes an n-contact layer formed on a substrate and a current spreading layer formed on the n-contact layer. The nitride semiconductor light... Agent: Mcdermott Will & Emery LLP

20070045656 - Design of silicon-controlled rectifier by considering electrostatic discharge robustness in human-body model and charged-device model devices: A silicon-controlled rectifier apparatus, comprising a substrate upon which a low-voltage triggered silicon-controlled rectifier is configured. A plurality of triggering components (e.g., NMOS fingers) are formed upon the substrate and integrated with the low-voltage triggered silicon-controlled rectifier, wherein the plurality of triggering components are inserted into the low-voltage triggered silicon-controlled... Agent: Pete Scott, Senior Corporate Counsel Lsi Logic Corporation

20070045657 - Semiconductor substrate, semiconductor device, manufacturing method thereof, and method for designing semiconductor substrate: A semiconductor substrate, includes: a capacitance-adjusting semiconductor layer which is disposed in a predetermined region on a semiconductor substrate material and which is sufficiently thick and has a lower impurity density than that of the semiconductor substrate material; a first insulation film disposed on the capacitance-adjusting semiconductor layer; and a... Agent: Edwards & Angell, LLP

20070045658 - System and method to provide power to a motor: A system to provide power to a motor includes a multi-channel output array comprising first and second field effect transistors configured to be operable simultaneously.... Agent: Brooks Kushman P.C. / Lear Corporation

20070045659 - Integrated circuit device and electronic instrument: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. A first-conductivity-type transistor included in the high-speed I/F circuit block is formed in a second-conductivity-type well, and a second-conductivity-type transistor included... Agent: Harness, Dickey & Pierce, P.L.C

20070045660 - Heterojunction structure of nitride semiconductor and nano-device or an array thereof comprising same: A heterojunction structure composed of a nitride semiconductor thin film and nanostructures epitaxially grown thereon exhibits high luminescence efficiency property due to facilitated tunneling of electrons through the nano-sized junction, and thus can be advantageously used in light emitting devices.... Agent: David A. Einhorn, Esq. Anderson Kill & Olick, P.C.

20070045661 - Organic photosensitive optoelectronic device with an exciton blocking layer: An organic photosensitive optoelectronic device having a plurality of cells disposed between a first electrode and a second electrode. Each cell includes a photoconductive organic hole transport layer adjacent to a photoconductive organic electron transport layer. A metal or metal substitute is disposed between each of the cells. At least... Agent: Kenyon & Kenyon LLP

20070045662 - Substrate for film growth of group iii nitrides, method of manufacturing the same, and semiconductor device using the same: A substrate 10 for film growth of group III nitride is constituted which includes a substrate material 11 and an AlN thin film 12 formed on said substrate as a buffer layer, and a semiconductor device comprising group III nitride thin film is formed thereon, and the AlN thin film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070045663 - Field effect transistor: A field effect transistor according to an embodiment of the invention includes: a semiconductor substrate; a channel layer of a first conductivity type formed on the semiconductor substrate; and a semiconductor layer of a second conductivity type that is buried in a recess structure formed in a semiconductor layer on... Agent: Mcginn Intellectual Property Law Group, PLLC

20070045664 - Semiconductor device and manufacturing method of the same: A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070045665 - Cmos image sensor of preventing optical crosstalk and method of manufacturing the same: An integrated circuit device includes a CMOS image sensor and a MIM capacitor therein. The CMOS image sensor includes a transfer gate electrode on a semiconductor substrate and a P-N junction photodiode within the semiconductor substrate. The photodiode is located adjacent a first side of the transfer gate electrode. A... Agent: Myers Bigel Sibley & Sajovec

20070045666 - Method for manufacturing semiconductor device: Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, an USG (undoped silicate glass) layer is utilized during a process of forming a capacitor to leave a hard mask layer and a polysilicon layer on the top surface of a peripheral circuit region, and... Agent: Heller Ehrman White & Mcauliffe LLP

20070045667 - Nanoscopic wired-based devices and arrays: Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used... Agent: Wolf Greenfield & Sacks, PC

20070045668 - Vertical anti-blooming control and cross-talk reduction for imagers: The present invention provides a solid-state imager device having a patterned buried doped region in the substrate, preferably an n+ doped region, that collects excess electrons and thus reduces cross-talk, minimizes blooming of excess electrons, and reduces dark current in a solid-state imager device.... Agent: Dickstein Shapiro LLP

20070045669 - Image sensor: An image sensor according to an embodiment of the invention includes: a plurality of pixels arranged in line; a reading gate adjacent to the plurality of pixels; a plurality of memory gates formed adjacent to the reading gate and corresponding to the plurality of pixels; a plurality of memory control... Agent: Young & Thompson

20070045670 - Nitride-