Active solid-state devices (e.g., transistors, solid-state diodes) inventions 02/07

20070040159 - Manufacturing method and structure for improving the characteristics of phase change memory: A manufacturing method and structure for better phase change memory characteristics by improving the interface and the hole-filling properties. The present invention can reduce the power consumption needed to operate and is easy to fabricate.... Agent: Rabin & Berdo, P.C.

20070040160 - Memory array for increased bit density and method of forming the same: A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the... Agent: Dickstein Shapiro LLP

20070040162 - Highly efficient iii-nitride-based top emission type light emitting device having large area and high capacity and method of manufacturing the same: Disclosed are a nitride-based top emission type light emitting device and a method of manufacturing the same. The light emitting device includes an n-nitride-based cladding layer, a p-nitride-based cladding layer, a nitride-based active layer, and a multiple p-ohmic contact layer. The multiple p-ohmic contact layer includes at least one pair... Agent: Cantor Colburn, LLP

20070040161 - Light-emitting element and light-emitting device: It is an object of the present invention to provide a light-emitting element having a layer containing a light-emitting material and a transparent conductive film between a pair of electrodes, in which electric erosion of the transparent conductive film and metal can be prevented, and also to provide a light-emitting... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070040163 - Electronic component and method of manufacturing the same: The invention relates to a surface mount type electronic component mounted on a printed circuit board or hybrid IC (HIC) and a method of manufacturing the same and provides an electronic component which can be formed with a small size and a low height at a low cost and a... Agent: Oliff & Berridge, PLC

20070040166 - Compound eye image sensor design: A flexible image sensor having an array of lenses disposed on one surface of a substrate flexible optical polymeric substrate, and an array of organic integrated circuit photodetectors on a second surface of the substrate, each lens in the lens array being in optical correspondence with a photodetector in the... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070040165 - Method of fabricating organic fets: At least two thicknesses of dielectric are formed in the fabrication of organic field effect transistors. One thickness is formed in the active regions of the transistor for adjusting the desired threshold of the device. A second thickness is deposited in the field regions of the transistor to electrically isolate... Agent: Hogan & Hartson LLP

20070040168 - Organic electroluminescent element: wherein M11 represents a hexacoordinate transition metal ion, Y11 represents a nitrogen atom or a substituted or unsubstituted carbon atom, L11 represents a ligand, Q11 and Q12 each represents an atomic group for forming a nitrogen-containing heterocyclic ring, n11 represents an integer of 1 to 3, n12 represents an integer... Agent: Sughrue-265550

20070040169 - Organic thin film transistor and manufacturing method thereof: An organic thin film transistor includes a substrate, a gate electrode, a gate insulating layer, a first electrode, and a second electrode disposed on the substrate, a first layer disposed on the substrate, the first layer being photosensitive, a second layer disposed on the first layer, the second layer being... Agent: Lee & Morse, P.C.

20070040164 - Polymer complex compound and polymer light emitting device using the same: (wherein, Ring P and Ring Q each independently represent an aromatic ring, but Ring P may be either existent or non-existent. When Ring P is existent, two connecting bonds respectively are on Ring P and/or Ring Q, and when Ring P is non-existent, two connecting bonds respectively are on 5... Agent: Sughrue Mion, PLLC

20070040167 - Water-based synthesis of poly(tetrazoles) and articles formed therefrom: A polyvinyl(tetrazole) is formed by a water-based method. A gas generating composition 12 containing the polyvinyl(tetrazole) is contained within an exemplary gas generator 10. An article or gas generating system 200 incorporates the polyvinyl(tetrazole) therein. A vehicle occupant protection system 180 incorporates the gas generating system 200. An article or... Agent: L.c. Begin & Associates, PLLC

20070040170 - Electronic devices: An electronic device including at least first and second transistors integrated together on a substrate and each including an organic semiconductor region, wherein the first and second transistors are either both n-type or both p-type but wherein one of the first and second transistors is a normally-ON transistor and the... Agent: Sughrue Mion, PLLC

20070040171 - Organic thin film transistor array panel and method for manufacturing the same: An organic thin film transistor array panel includes; a substrate, a data line formed on the substrate, a gate line intersecting the data line and including a gate electrode, a first interlayer insulating layer formed on the gate line and the data line and including a first opening exposing the... Agent: Cantor Colburn, LLP

20070040172 - Source/drain electrodes, thin-film transistor substrates, manufacture methods thereof, and display devices: A source/drain electrode is used in a thin-film transistor substrate containing a substrate, a thin-film transistor semiconductor layer, source/drain electrodes, and a transparent picture electrode. The source/drain electrode includes a nitrogen-containing layer and a thin film of pure aluminum or an aluminum alloy. Nitrogen of the nitrogen-containing layer binds to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070040173 - Source/drain electrodes, transistor substrates and manufacture methods, thereof, and display devices: In a thin-film transistor substrate including a substrate, a thin-film transistor semiconductor layer, a source/drain electrode, and a transparent pixel electrode, the source/drain electrode includes a thin film of an aluminum alloy containing 0.1 to 6 atomic percent of nickel as an alloy element, and the aluminum alloy thin film... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070040174 - Thin film transistor substrate and fabrication thereof: A thin film transistor substrate having a semiconductor layer including a low concentration region and a source region/drain region adjacent to the low concentration region at both sides of a channel region made of polysilicon; a gate insulating layer and a conductive layer on the substrate the conductive layer patterned... Agent: Macpherson Kwok Chen & Heid LLP

20070040175 - Polysilicon thin film transistor and method of fabricating the same: A polysilicon thin film transistor (TFT) may include a substrate, at least one insulating layer, a semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a heat retaining layer formed to contact the semiconductor layer. The heat retaining layer may reduce and/or prevent a reduction in a... Agent: Lee & Morse, P.C.

20070040176 - Semiconductor device: A semiconductor device having a display unit, which is small in size, suppresses the defect caused by the mounting of IC chips and the like on the substrate, and operates at a high speed. A semiconductor display unit and other circuit blocks are integrally formed on the substrate having an... Agent: Eric Robinson

20070040177 - Multi-channel type thin film transistor and method of fabricating the same: A multi-channel type thin film transistor includes a gate electrode over a substrate extending along a first direction, a plurality of active layers parallel to and spaced apart from each other extending along a second direction crossing the first direction, and source and drain electrodes spaced apart from each other... Agent: Morgan Lewis & Bockius LLP

20070040178 - Thin film transistor substrate for display device and fabricating method thereof: A thin film transistor substrate for a display device having a plurality of thin film transistors and pixel electrodes connected to the thin film transistors, said thin film transistor substrate includes: a plurality of pad electrodes in a non-display area of the display device for applying signals to the plurality... Agent: Morgan Lewis & Bockius LLP

20070040179 - Light-emitting device, display and light-emitting method: A light-emitting device includes a light-emitting portion and an oxygen concentration control portion. The light-emitting portion includes a surface. The light-emitting portion emits light with an intensity corresponding to an oxygen concentration on the surface when receiving light energy. The oxygen concentration control portion controls the oxygen concentration on the... Agent: Oliff & Berridge, PLC

20070040180 - Integrated circuit device: An integrally packaged optronic integrated circuit device including an integrated circuit die containing at least one of a radiation emitter and radiation receiver and having a transparent packaging layer overlying a surface of the die, the transparent packaging layer having an opaque coating adjacent to edges of the layer.... Agent: Tessera Lerner David Et Al.

20070040181 - Crystalline composition, wafer, and semi-conductor structure: A crystalline composition is provided that includes gallium and nitrogen. The crystalline composition may have an amount of oxygen present in a concentration of less than about 3×1018 per cubic centimeter, and may be free of two-dimensional planar boundary defects in a determined volume of the crystalline composition. The volume... Agent: General Electric Company Global Research

20070040182 - Light emitting diode packaging structure: A light emitting diode (LED) packaging structure has a carrier having an insulating layer and a conducting layer formed thereon. A top surface of the carrier is partially depressed to form a cup portion having a raised central seat upward projected from a bottom thereof. The raised central seat has... Agent: Pro-techtor International Services

20070040183 - Gallium nitride-based compound semiconductor light-emitting device and electrode for the same: An object of the present invention is to provide a light-permeable electrode for use in a gallium nitride-based compound semiconductor light-emitting device, the electrode having improved light permeability and contact resistance. The inventive electrode comprises a light-permeable first layer which is in contact with a surface of a p-contact layer... Agent: Sughrue Mion, PLLC

20070040185 - Semiconductor device and capacitance regulation circuit: According to an embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor element having a first main electrode, a second main electrode and a control electrode, a current flowing between the first and second main electrodes being controlled by a control signal which is input between... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070040184 - Semiconductor device and capacitance regulation circuit: According to an embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor element having a first main electrode, a second main electrode and a control electrode, a current flowing between the first and second main electrodes being controlled by a control signal which is input between... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070040186 - Power semiconductor packaging method and structure: A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through... Agent: General Electric Company Global Research

20070040187 - Semiconductor device and manufacturing method of the same: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070040188 - Contact or via hole structure with enlarged bottom critical dimension: An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer,... Agent: Slater & Matsil, L.L.P.

20070040189 - Bi-directional switch, and use of said switch: A bi-directional switch has at least one first controllable semiconductor component with a first input contact, a first output contact, and a first control contact, and at least one second controllable semiconductor component with a second input contact, a second output contact, and a second control contact. The first input... Agent: Staas & Halsey LLP

20070040190 - Ink jet recording head and ink discharge method: An ink jet recording head is provided with one heat generating member in each of ink flow paths, and the discharge port thereof is arranged on the extended line extending in the normal direction from the center of the main surface of the heat generating member to the surface of... Agent: Fitzpatrick Cella Harper & Scinto

20070040191 - Nanowire structures and electrical devices: The present invention provides structures and devices comprising conductive segments and conductance constricting segments of a nanowire, such as metallic, superconducting or semiconducting nanowire. The present invention provides structures and devices comprising conductive nanowire segments and conductance constricting nanowire segments having accurately selected phases including crystalline and amorphous states, compositions,... Agent: Greenlee Winner And Sullivan P C

20070040192 - Photodiode array and production method thereof, and radiation detector: A photodiode array 1 is provided with an n-type silicon substrate 3. A plurality of photodiodes 4 are formed in array on the opposite surface side to an incident surface of light L to be detected, in the n-type silicon substrate 3. A resin film 6 for transmitting the light... Agent: Drinker Biddle & Reath (dc)

20070040193 - Semiconductor device, electro-optic device, and electric device: A semiconductor device includes a semiconductor layer, and a first transistor and a second transistor that are formed using the semiconductor layer, wherein each conductance of the first and second transistors changes complementarily to each other according to a curvature of the semiconductor layer.... Agent: Oliff & Berridge, PLC

20070040194 - Solid state imaging device: A CCD image sensor includes photodiodes, vertical transfer CCDs for transferal of signal charge of the photodiodes, and a light shielding layer for protection of the vertical transfer CCDs from light. The light shielding layer covers over recesses disposed above the photodiodes, and each of the recesses has an opening... Agent: Birch Stewart Kolasch & Birch

20070040195 - Monolithic integrated passive and active electronic devices with biocompatible coatings: A bio-compatible electrical element including a high-dielectric amorphous TixAl1-xOy oxide alloy wherein a TiO2 layer is between the bio-compatible electrical element and a biological such as human environment. A continuous and substantially pinhole free dielectric amorphous TixAl1-xOy oxide alloy wherein x is in the range of from about 0.5 to... Agent: Harry M. Levy Emrich & Dithmar, LLC

20070040196 - Semiconductor device and manufacturing method thereof, and thin film device: A manufacturing method of a semiconductor device is disclosed. The manufacturing method includes the steps of forming a contact plug in an insulation film so as to be connected to an element on a semiconductor substrate, applying PLA pretreatment to the insulation film in an NH3 atmosphere, forming a Ti... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070040197 - Non-volatile memory, manufacturing method and operating method thereof: A non-volatile memory including a memory unit, a first bit line and a second bit line is provided. The memory unit includes a first doped region, a second doped region, a first memory cell, a select gate structure, and a second memory cell. The first doped region and the second... Agent: Jianq Chyun Intellectual Property Office

20070040198 - Semiconductor device and manufacturing method thereof, and thin film device: A manufacturing method of a semiconductor device is disclosed. The manufacturing method includes the steps of forming a contact plug in an insulation film so as to be connected to an element on a semiconductor substrate, applying a PLA process to the insulation film in an NH3 atmosphere, forming a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070040199 - Semiconductor device and method for manufacturing the same: In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS... Agent: Mcdermott Will & Emery LLP

20070040200 - Trench buried bit line memory devices and methods thereof: A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit... Agent: Dinsmore & Shohl LLP

20070040202 - Semiconductor memory cell array having self-aligned recessed gate mos transistors and method for forming the same: In a semiconductor memory including an array of memory cells, each memory cell includes a trench capacitor, the trench capacitor including an inner electrode, an outer electrode and a dielectric layer disposed between the inner electrode and the outer electrode, and a selection transistor, the selection transistor including a first... Agent: Morrison & Foerster LLP

20070040201 - Trench capacitor and fabricating method thereof: A method of fabricating trench capacitors is described. A substrate having at least one isolation structure is provided. A first trench and a second trench are formed in the substrate beside the isolation structure. A first lower electrode and a second lower electrode are formed in the substrate around the... Agent: Jianq Chyun Intellectual Property Office

20070040204 - Integrating three-dimensional high capacitance density structures: Disclosed are three-dimensional dielectric structures on high surface area electrodes and fabrication methods. Exemplary structures comprise a copper foil substrate, trench electrodes or high surface area porous electrode structures formed on the substrate, a insulating thin film formed on the surface and laminating the foil on a organic substrate. A... Agent: Law Offices Of Kenneth W. Float

20070040203 - Semiconductor device capacitors with oxide-nitride layers and methods of fabricating such capacitors: Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer... Agent: D. Randal Ayers Myers Bigel Sibley & Sajovec, P.A.

20070040205 - Stud capacitor device and fabrication method: The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the substrate and the recess, depositing a filler layer so... Agent: Knobbe Martens Olson & Bear LLP

20070040207 - Electronic devices including dielectric layers with different densities of titanium: Methods of forming an electronic device include providing a fist electrode, providing a dielectric oxide layer on the first electrode, and providing a second electrode on the dielectric oxide layer so that the dielectric oxide layer is between the first and second electrodes. More particularly, a first portion of the... Agent: Myers Bigel Sibley & Sajovec

20070040206 - High dielectric material composed of sintered body of rare earth sulfide: A high-dielectric material which is especially useful as a material for a high-capacitance capacitor and which has a high dielectric constant is provided. The high-dielectric material is composed of a sintered body of a rare-earth sulfide, the high-dielectric material having a crystal structure of tetragonal β type, a chemical composition... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070040208 - Fabrication method and structure of semiconductor non-volatile memory device: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070040210 - Nonvolatile semiconductor memory and fabrication method for the same: The present invention provides a nonvolatile semiconductor memory that allows simultaneous implementation of high performance transistors in a low-voltage circuit region and transistors with high withstand voltages in a high-voltage circuit region. The nonvolatile semiconductor memory includes a cell array region that comprises aligned memory cell transistors, each including a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070040209 - Novel applications for insulated gate bipolar transistors: The amount of current flowing in the bitline during reading of a memory cell which is in the conductive state, hereinafter called the memory cell current, can be amplified manifold by changing the above mentioned select transistors to a novel device which is described in detail. The increase of the... Agent: Spadea Gregorio

20070040211 - Nonvolatile memory device and method of forming the same: A multi-bit memory cell includes a substrate; a multi-bit charge-trapping cell over the substrate, the multi-bit charge-trapping cell having a first lateral side and a second lateral side; a source region in the substrate, a portion of the source region being under the first side of the multi-bit charge-trapping cell;... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070040212 - Asymmetric hetero-doped high-voltage mosfet (ah2mos): An asymmetric heterodoped metal oxide (AH2MOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions are formed. The tub region has dopants of a... Agent: Hiscock & Barclay, LLP

20070040215 - Power semiconductor device with interconnected gate trenches: A power semiconductor device which includes a plurality of gate trenches and a perimeter trench intersecting the gate trenches.... Agent: Ostrolenk Faber Gerb & Soffen

20070040213 - Trench gate field effect devices: The present invention provides a technique for accumulating minority carriers in the body region, that is, the intermediate region interposed between the top region and the deep region, and thus increasing the concentration of minority carriers in the intermediate region. A semiconductor device has a top region (34) of a... Agent: Kenyon & Kenyon LLP

20070040214 - Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is... Agent: Hiscock & Barclay, LLP

20070040217 - Power semiconductor device: The power semiconductor device according to one embodiment of the present invention at least comprises: first pillar layers of the first conductive type and second pillar layers of a second conductive type which constitute a super-junction structure in a device section and which are arranged alternately in a horizontal direction,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070040216 - Semiconductor device used as high-speed switching device and power device: A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070040218 - Hybrid-orientation technology buried n-well design: A semiconductor structure is provided that includes a hybrid orientated substrate having at least two coplanar surfaces of different surface crystal orientations, wherein one of the coplanar surfaces has bulk-like semiconductor properties and the other coplanar surface has semiconductor-on-insulator (SOI) properties. In accordance with the present invention, the substrate includes... Agent: Scully, Scott, Murphy & Pressner

20070040219 - Iii-v group nitride system semiconductor self-standing substrate, method of making the same and iii-v group nitride system semiconductor wafer: A III-V group nitride system semiconductor self-standing substrate is made of III-V group nitride system semiconductor single crystal with a hexagonal crystal system crystalline structure. The substrate is provided with a surface that is off-oriented 0.09 degrees or more and 24 degrees or less in the a-axis or m-axis direction... Agent: Mcginn Intellectual Property Law Group, PLLC

20070040220 - An electrostatic discharge circuit: An electrostatic discharge circuit includes at least an electrostatic discharge zener diode, an NMOS transistor, and a PMOS transistor. The electrostatic discharge zener diode is used for lowering the breakdown voltage and making the electrical current discharge through it, thereby preventing the circuit device from burning out and greatly enhancing... Agent: Pai Patent & Trademark Law Firm

20070040221 - Electrostatic discharge protection element: A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has... Agent: Brinks Hofer Gilson & Lione Infineon

20070040222 - Method and apparatus for improved esd performance: The present invention provides an integrated circuit for improved ESD protection and method of forming the same. The integrated circuit comprises a substrate and an insulating layer formed over the substrate. The circuit also comprises a field effect field effect transistor (FET) formed over the insulating layer. The FET includes... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20070040223 - Lateral undercut of metal gate in soi device: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.... Agent: Intel Corporation C/o Intellevate, LLC

20070040224 - Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same: A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the... Agent: Micron Technology, Inc.

20070040225 - High performance mosfet comprising a stressed gate metal silicide layer and method of fabricating the same: The present invention relates to a semiconductor device that comprises at least one field effect transistor (FET) containing a source region, a drain region, a channel region, a gate dielectric layer, a gate electrode, and one or more gate sidewall spacers. The gate electrode of such an FET contains an... Agent: Scully Scott Murphy & Presser, PC

20070040226 - Cascode circuit: A cascode circuit in which two field effect transistors “FET”) are connected in cascode has a first FET having its source grounded, a second FET having its source connected to the drain of the first FET, and a Schottky barrier diode having an anode connected to the source of the... Agent: Leydig Voit & Mayer, Ltd

20070040227 - Reducing gate dielectric material to form a metal gate electrode extension: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have vertical portions that may be exposed to a reduction reaction. As a result of the reduction reaction, the vertical portions may be converted to metal, which adds to the existing gate electrode. In some cases, removing... Agent: Trop Pruner & Hu, PC

20070040228 - Semiconductor device utilizing a metal gate material such as tungsten and method of manufacturing the same: Known drawbacks associated with use of tungsten as a gate material in a semiconductor device are prevented. A gate oxide layer, a polysilicon layer, and a nitride layer are sequentially formed on a semiconductor substrate having a isolation layer for defining the active region. A recess is defined by etching... Agent: Ladas & Parry LLP

20070040230 - Micromechanical component: A micromechanical component has a structure such that a material flow is guided from at least one preferred direction for the purpose of uniformly enveloping the micromechanical component.... Agent: Kenyon & Kenyon LLP

20070040229 - Self-assembly microstructure with polymide thin-film elastic joint: The invention relates to a self-assembly microstructure with a polyimide thin-film elastic joint, which contains at least one stationary part of the microstructure and at least one movable part of the microstructure. An elastic joint located between the stationary part and the movable part is a photosensitive polyimide thin film... Agent: Bacon & Thomas, PLLC

20070040231 - Partially etched leadframe packages having different top and bottom topologies: A package for a micro-electromechanical (MEMS) device is described. A premolded leadframe base has opposing top and bottom surfaces. Each surface is defined by a topology having at least one electrically conductive portion and at least one electrically non-conductive portion, and the topology of the top surface differs from the... Agent: Bromberg & Sunstein LLP

20070040232 - Data download to imager chip using image sensor as a receptor: An imaging device having a CMOS photosensor array for capturing images is described in which the array is also used to input programming and/or data used to control the imaging operations. The data-input can be based upon variations in light color, value, intensity, and patterning, or any combinations of the... Agent: Dickstein Shapiro LLP

20070040233 - Photovoltaic device:

20070040234 - Data download to imager chip using image sensor as a receptor: An imaging device having a CMOS photosensor array for capturing images is described in which the array is also used to input programming and/or data used to control the imaging operations. The data-input can be based upon variations in light color, value, intensity, and patterning, or any combinations of the... Agent: Dickstein Shapiro LLP

20070040235 - Dual trench isolation for cmos with hybrid orientations: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a... Agent: Scully Scott Murphy & Presser, PC

20070040236 - Discrete on-chip soi resistors: A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench... Agent: Law Office Of Charles W. Peterson, Jr. Burlington

20070040238 - Coil structure, method for manufacturing the same and semiconductor package: A chip coil has a chip format including a rectangle substrate of an insulating resin material and a coil portion having a solenoid structure a part of which is embedded within the substrate and in which adjacent coils are insulated from each other by the substrate. The resin material contains... Agent: Rankin, Hill, Porter & Clark LLP

20070040237 - High current semiconductor device system having low resistance and inductance: A high current semiconductor device (for example QFN for 30 to 70 A) with low resistance and low inductance is encapsulated by molding compound (401, height 402 about 0.9 mm) so that the second lead surfaces 110b remain unencapsulated. A copper heat slug (404) may be attached to chip surface... Agent: Texas Instruments Incorporated

20070040239 - Integrated beol thin film resistor: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is... Agent: Ibm Microelectronics Intellectual Property Law

20070040240 - Bulk nitride mono-crystal including substrate for epitaxy: The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area... Agent: Smith Patent Office

20070040242 - Semiconductor device and method for manufacturing the same: In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line.... Agent: Hogan & Hartson L.L.P.

20070040241 - Wafer inspection device: The invention relates to a wafer inspection device. The device comprises an air-cushion stage which can be displaced in two directions (X,Y) that are perpendicular to one another. Several air nozzles are provided for this purpose. At least one valve is connected to at least one electric control unit, the... Agent: Simpson & Simpson, PLLC

20070040243 - Insulating target material, method of manufacturing insulating target material, conductive complex oxide film, and device: An insulating target material for obtaining a conductive complex oxide film represented by a general formula ABO3, the insulating target material including an oxide of an element A, an oxide of an element B, and at least one of an Si compound and a Ge compound.... Agent: Harness, Dickey & Pierce, P.L.C

20070040244 - Substrate for sensors: It is an object of the present invention to provide a substrate for sensors and a container, wherein the adhesiveness of the substrate to a thin film is improved, a physiologically active substance can be immobilized without the peeling of the thin film from a plastic substrate, and non-specific adsorption... Agent: Sughrue Mion, PLLC

20070040245 - Anisotropic conductive sheet, manufacturing method thereof, and product using the same: An anisotropically conductive sheet that can surely achieve necessary electrical connection even to an object to be connected, the arrangement pitch of electrodes to be connected of which is extremely small, a production process thereof, and applied products equipped with the anisotropically conductive sheet. The anisotropically conductive sheet according to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070040247 - Leadframe package with dual lead configurations: The invention provides a variety of leadframe packages in which signal connections and fixed voltage connections are configured differently to improve the relative performance of the connections relative to their assigned function. The signal connections incorporate one or more configurations of signal lead and corresponding signal bonding wires that tend... Agent: Harness, Dickey & Pierce, P.L.C

20070040246 - Touch pad module with electrostatic discharge protection: A touch pad module with electrostatic discharge protection is disclosed. The touch pad module comprises a casing, a metal sheet, a touch pad and a metal holder, wherein the casing covers the metal sheet and has a first opening to expose a portion of the touch pad. The metal sheet... Agent: Rabin & Berdo, P.C.

20070040250 - Semiconductor device: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070040249 - Semiconductor device: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070040248 - Semiconductor device: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070040251 - Method for connecting a die assembly to a substrate in an integrated circuit and a semiconductor device comprising a die assembly: A semiconductor device includes a substrate, a die assembly attachable to the substrate and a flexible strip extending over the substrate and the die assembly. The flexible strip has one or more routing circuits carried thereon. The die assembly and the substrate are arranged to be electrically connected through the... Agent: Slater & Matsil LLP

20070040252 - Semiconductor power component with a vertical current path through a semiconductor power chip: A semiconductor power component using flat conductor technology includes a vertical current path through a semiconductor power chip. The semiconductor power chip includes at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a flat conductor... Agent: Edell, Shapiro & Finnan, LLC

20070040253 - Chip type led: A chip type LED which is capable of laterally emitting light from the light emitting diode chip and having a relatively small thickness is provided. The chip type LED includes an insulating substrate 12, a light emitting diode chip 15 mounted on the upper surface of the insulating substrate, and... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20070040255 - Semiconductor device: A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070040254 - Semiconductor die package: A clip-less packaged semiconductor device includes at least one semiconductor die having bottom and top surfaces each having at least one electrode. A leadframe comprising a sheet of conductive material having top and bottom surfaces, the top surface being substantially planar, the bottom surface having a recessed region having a... Agent: Duane Morris, LLPIPDepartment

20070040256 - Semiconductor device, method of authentifying and system: The semiconductor device (11) of the invention comprises a circuit and a protecting structure (50). It is provided with a first and a second security element (12A, 12B) and with an input and an output (14,15). The security elements (12A, 12B) have a first and a second impedance, respectively, which... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070040257 - Chip packages with covers: This invention discloses a crystalline substrate based device including a crystalline substrate having formed thereon a microstructure; and at least one packaging layer which is sealed over the microstructure by means of an adhesive and defines therewith at least one gap between the crystalline substrate and the at least one... Agent: Tessera Lerner David Et Al.

20070040259 - Bumpless chip package: A bumpless chip package including at least a panel-shaped component, a chip, an interconnection structure and a conductive channel is provided. The chip is disposed on the panel-shaped component. The chip has a plurality of chip pads disposed on an active surface of the chip. The interconnection structure is disposed... Agent: J.c. Patents, Inc.

20070040258 - Method of packaging and interconnection of integrated circuits: A method is disclosed for packaging semiconductor chips on a flexible substrate employing thin film transfer. The semiconductor chips are placed on a temporary adhesive substrate, then covered by a permanent flexible substrate with a casting layer for planarizingly embedding the chips on the permanent substrate before removing the temporary... Agent: James Sheats

20070040260 - Power semiconductor device comprising a semiconductor chip stack and method for producing the same: A power semiconductor device has a power field effect transistors connected in a bridge circuit (16), parallel circuit or series circuit (18), the power semiconductor device (30) having a base power semiconductor chip (1) with large-area external contacts (S1, D1) on the top side (31) and rear side (32) and... Agent: Baker Botts, L.L.P.

20070040261 - Semiconductor component comprising an interposer substrate and method for the production thereof: A semiconductor component (10) has an interposer substrate (1) as stack element of a semiconductor component stack (25). The interposer substrate (1) has, on one of the interposer substrate sides (2, 4), a semiconductor chip protected by plastics composition (12) in its side edges (22). An interposer structure (3) partly... Agent: Baker Botts, L.L.P.

20070040262 - Flexible substrate capable of preventing lead thereon from fracturing: The invention discloses a flexible substrate including a flexible insulating film and a plurality of leads formed on an upper surface of the flexible insulating film. Each of the leads includes a first portion, a second portion, and a connection portion connecting the first portion and the second portion. The... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070040263 - Green data center and virtual power plant: A power system for cooling backup computer storage facilities having eight independent levels of redundancy for the power supply to allow the storage facility to survive even extreme and debilitating events and having redundant communications. If power from the existing gas or electric grid is lost, a series of back-up... Agent: Dykema Gossett PLLC

20070040264 - Underfilled semiconductor die assemblies and methods of forming the same: An apparatus and method for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide a robust, inflexible cost-effective bond. The semiconductor die is attached to the carrier substrate with a plurality of discrete adhesive elements so as to provide a gap or standoff... Agent: Trask Britt, P.C./ Micron Technology

20070040265 - Substrate support having brazed plates and resistance heater: A substrate support comprises top, middle and bottom plates which are brazed together. The top plate has a top surface with a plurality of outwardly projecting mesas dispersed across a recessed pocket, a network of recessed grooves, a vacuum port terminating in the recessed grooves, and plurality of gas ports.... Agent: Janah & Associates, P.C.

20070040266 - Heat-conducting packaging of electronic circuit units: The invention relates to a heat-conducting coating of electronic circuit assemblies (102), comprising a coating agent (100), which encloses the electronic circuit assembly (102) and which is electrically insulating, with dispersed particles in the coating agent (100) which have a high thermal conductivity, whereby the particles dispersed in the coating... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070040267 - Method and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface features: Methods, systems, and apparatuses for attaching heat sinks to integrated circuit packages using thermally conductive adhesive materials are described. The adhesive materials can be shaped to conform to surfaces of the integrated circuit package and/or heat sink, prior to hardening, such as by curing the adhesive material.... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20070040268 - Device package and methods for the fabrication and testing thereof: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second... Agent: Rohm And Haas Electronic Materials LLC

20070040269 - Thermally enhanced cavity down ball grid array package: Dummy chip 90 has a coefficient of thermal expansion (CTE) approximately equal to the coefficient of thermal expansion of the chip 40. Because the CTE of the dummy chip 90 is approximately equal to the CTE of the chip 40 and the amount of the encapsulant 60 used will be... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070040270 - Electronic device and carrier substrate: The electronic device comprises a semiconductor device (10), particularly an integrated circuit, and a carrier substrate (20) with conductive layers on the first side (21) and the second side (22), and voltage supply (62) and ground connections (61) mutually arranged according to a chessboard pattern. These connections (61,62) extend in... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070040271 - Integrated circuit package: An integrated circuit package comprising: an substrate having a first main surface and a second main surface which are opposite to each other; a first plurality of external terminals disposed on the first main surface of said interconnection substrate; and a second plurality of external terminals disposed on the second... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070040272 - Method of packaging and interconnection of integrated circuits: A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible... Agent: James Sheats

20070040273 - Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods: Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the microelectronic workpiece further includes a plurality of dies formed on the device... Agent: Perkins Coie LLP Patent-sea

20070040274 - Interconnect of group iii- v semiconductor device and fabrication method for making the same: An interconnect of the group III-V semiconductor device and the fabrication method for making the same are described. The interconnect includes a first adhesion layer, a diffusion barrier layer for preventing the copper from diffusing, a second adhesion layer and a copper wire line. Because a stacked-layer structure of the... Agent: Jianq Chyun Intellectual Property Office

20070040275 - Semiconductor device including diffusion barrier and method for manufacturing the same: Provided are a semiconductor device including a diffusion barrier and a method for manufacturing the same. In the method, an interlayer insulating layer on a semiconductor substrate is formed. The interlayer insulating layer is selectively removed, so that a via hole is formed therein. A first diffusion barrier is formed... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070040276 - Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application: An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original... Agent: Scully Scott Murphy & Presser, PC

20070040277 - Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing: A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result,... Agent: Schmeiser, Olsen & Watts

20070040278 - Multifunctional material having carbon-doped titanium oxide layer: A multifunctional material having a carbon-doped titanium oxide layer, which has carbon doped in the state of Ti—C bonds, is excellent in durability (high hardness, scratch resistance, wear resistance, chemical resistance, heat resistance) and functions as a visible light responding photocatalyst, is provided. The multifunctional material of the present invention... Agent: Sughrue Mion, PLLC

20070040280 - Multi-chip package for reducing parasitic load of pin: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The... Agent: Volentine Francos, & Whitt PLLC

20070040279 - Switching device for altering built-in function of ic chip: A switching device provided on a package substrate for altering the built-in function of an IC chip includes a first contact, a second contact, and a conductive layer. The first contact is electrically connected to a signal-receiving end of the package substrate, and the second contact is electrically connected to... Agent: Birch Stewart Kolasch & Birch

20070040281 - Semiconductor device and method of producing the same: To provide a semiconductor device configured that a micro device having a device substrate, a function element provided on the device substrate and having an oscillator or a movable part, first lands provided on a surface of the device substrate by being arranged on its outer circumference portion of the... Agent: Robert J. Depke Lewis T. Steadman

20070040282 - Printed circuit board and method thereof and a solder ball land and method thereof: A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second... Agent: Harness, Dickey & Pierce, P.L.C

20070040283 - Encapsulated chip scale package having flip-chip on lead frame structure and method: In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070040284 - Two layer substrate ball grid array design: A routing pattern for high speed signals for a package substrate. Electrically conductive bond fingers are disposed on a first surface of the package substrate. The first surface is adapted to receive an integrated circuit in an attachment zone, and the bond fingers are disposed in at least two substantially... Agent: Lsi Logic Corporation

20070040285 - Heat dissipating grease: A heat dissipating grease includes a polymer matrix and a plurality of heat conducting fillers incorporated thereinto. A thermal conductivity of the polymer matrix is 0.1˜0.2 W/mK. A thermal conductivity of the heat conducting filler is 20˜1000 W/mK. A weight ratio of the polymer matrix and the heat conducting filler... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070040286 - Structure for circuit assembly: A structure for circuit assembly is applied to positional alignment in bonding process. The structure for circuit assembly comprises a first substrate, having a plurality of first terminals and both a first alignment mark and a second alignment mark located in the vicinity of the first terminals, and a second... Agent: Birch Stewart Kolasch & Birch

20070040287 - Method for forming capacitor in a semiconductor device: A method for forming a capacitor of a semiconductor device ensures charging capacity and improves leakage current characteristic. In the capacitor forming method, a semiconductor substrate formed with a storage node contact is prepared first. Next, a storage electrode is formed such that the storage electrode is connected to the... Agent: Ladas & Parry LLP

20070034849 - Multi-layer chalcogenide devices: A multi-layer chalcogenide electronic device. The device includes an active region in electrical communication with two terminals, where the active region includes two or more layers. In one embodiment, the pore region includes two or more chalcogenide materials which differ in chemical composition. In another embodiment, the pore region includes... Agent: Energy Conversion Devices, Inc.

20070034848 - Reproducible resistance variable insulating memory devices and methods for forming same: The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the thickness of the insulating material at the tip of the bottom electrode is thinnest, creating the largest electric field at the tip of the bottom... Agent: Dickstein Shapiro LLP

20070034851 - Chalcogenide devices and materials having reduced germanium or telluruim content: A chalcogenide material and chalcogenide memory device exhibiting fast operation (short set pulse times) over an extended range of reset state resistances. Electrical devices containing the instant chalcogenide materials permit rapid transformations from the reset state to the set state for reset and set states having a high resistance ratio.... Agent: Energy Conversion Devices, Inc.

20070034850 - Chalcogenide devices incorporating chalcogenide materials having reduced germanium or telluruim content: A chalcogenide material and chalcogenide memory device having less stringent requirements for formation, improved thermal stability and/or faster operation. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. Electrical devices containing the... Agent: Energy Conversion Devices, Inc.

20070034856 - Light emitting element, light emitting device and electronic device: It is an object of the present invention to provide a light emitting element with improved luminous efficiency, a reduced drive voltage, and improved degree of deterioration with respect to driving time. According to a light emitting element including a first electrode; a second electrode; and a light emitting laminated... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070034852 - Mid-infrared resonant cavity light emitting diodes: A Resonant Cavity Light Emitting Diode (RCLED) device having a first active region having one or more quantum wells disposed within, a first chamber and a second chamber coupled to the first active region and a first reflector and a second reflector coupled to the first and second chambers respectively... Agent: Baker & Hostetler LLP

20070034855 - Nitride semiconductor light emitting device: The invention relates to a high-output nitride light emitting device. The light emitting device includes a first conductivity type nitride semiconductor layer, an active layer and a second conductivity type nitride semiconductor layer deposited in their order on a substrate. The light emitting device also includes first and second insulation... Agent: Mcdermott Will & Emery LLP

20070034857 - Nitride-based white light emitting device and manufacturing method thereof: A light emitting device includes an n-type cladding layer. a p-type cladding layer. an active layer interposed between the n-type cladding layer and the p-type cladding layer and an ohmic contact layer contacting the p-type cladding layer or the n-type cladding layer. The ohmic contact layer includes a first film... Agent: Cantor Colburn, LLP

20070034854 - Organometallic complex, and light emitting element and electronic appliance using the same: It is an object of the present invention to provide a substance which can emit red phosphorescence which is closer to the chromaticity coordinates of red according to the NTSC standard. The present invention provides an organometallic complex represented by the general formula (1), wherein each of R1 to R3... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070034853 - Structures for reducing operating voltage in a semiconductor device: A light-emitting device comprises an active region configured to generate light in response to injected charge, and an n-type material layer and a p-type material layer, wherein at least one of the n-type material layer and the p-type material layer is doped with at least two dopants, at least one... Agent: Avago Technologies, Ltd.

20070034858 - Light-emitting diodes with quantum dots: An apparatus includes a light-emitting diode. The light-emitting diode has a semiconductor matrix of one or more group III-nitride alloys and quantum dots dispersed inside the matrix. The quantum dots include a group III-nitride alloy different from the one or more group III-nitride alloys of the matrix.... Agent: Lucent Technologies Inc. Docket Administrator - Room 3j-219

20070034859 - Electroluminescent device: An optical device comprising an anode, a cathode comprising barium, strontium or calcium, and a layer of organic semiconducting material between the anode and the cathode wherein a layer of hole transporting and electron blocking material is located between the anode and the layer of organic semiconducting material.... Agent: Marshall, Gerstein & Borun LLP

20070034862 - Electronic device comprising an organic semiconductor, an organic semiconductor, and an intermediate buffer layer made of a polymer that is cationically polymerizable and contains no photoacid: The present invention describes a novel design principle for organic electronic elements by inserting at least one additional crosslinkable layer. The properties of the electronic devices are thereby improved. Structured construction of these devices is furthermore facilitated.... Agent: Connolly Bove Lodge & Hutz, LLP

20070034860 - Field effect organic transistor: A field effect organic transistor includes a source electrode, a drain electrode, a gate electrode, a gate insulating layer and an organic semiconductive layer; in the field effect organic transistor, the organic semiconductive layer includes a first organic semiconductive layer forming a channel region and a second organic semiconductive layer... Agent: Fitzpatrick Cella Harper & Scinto

20070034861 - Field effect type organic transistor and process for production thereof: A field effect type organic transistor is provided which comprises a source electrode, a drain electrode, and a gate electrode, a gate insulating layer, and an organic semiconductor layer, wherein the gate insulating layer contains an optical anisotropic material having an anisotropic structure formed by light irradiation, and the organic... Agent: Fitzpatrick Cella Harper & Scinto

20070034866 - Laser induced thermal imaging (liti) mask and an organic electroluminescent device fabrication method using the mask: A Laser Induced Thermal Imaging (LITI) mask and an organic electroluminescent device fabrication method using the mask provides a LITI mask in which corner regions are reinforced to improve adhesive force between a receptor substrate and a transfer layer on corners of a pixel portion of the receptor substrate, and... Agent: Robert E. Bushnell

20070034865 - Memory device and a semiconductor device: The present invention provides a memory device and a semiconductor device which have high reliability for writing at low cost. Furthermore, the present invention provides a memory device and a semiconductor device having a non-volatile memory element in which data can be additionally written and which can prevent forgery due... Agent: Eric Robinson

20070034863 - Metal complexes: The present invention describes new types of metal complexes. Such compounds can be used as functional materials in a series of different types of applications which can be classified within the electronics industry in the widest sense. The inventive compounds are described by the formulae (1) and (4).... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070034864 - Organic light-emitting device with improved layer conductivity distribution: An OLED comprises an anode, a hole source, an emissive region, an electron source and a cathode, wherein the materials for the electron source and the hole source are chosen such that the electrical conductivity of these charge carrier sources is greater than the electrical conductivity of the emissive region.... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070034867 - Organic thin film transistor and flat panel display device using the same: An organic thin film transistor and a flat panel display device using the same are disclosed. The organic thin film transistor includes an inorganic layer doped with an impurity in a region of the outer surfaces of source and drain electrodes, or the source and drain electrodes is formed by... Agent: Christie, Parker & Hale, LLP

20070034868 - Semiconductor device and test system thereof: A semiconductor device that includes a clock buffer, which generates an internal clock signal in response to a clock signal and a complementary clock signal if the semiconductor device is operating in a first mode and generates the internal clock signal in response to the clock signal and a reference... Agent: Harness, Dickey & Pierce, P.L.C

20070034869 - Solid-state imaging device and method for producing the same: In the solid-state imaging device of the present invention having a photoelectric conversion section and a charge transfer section equipped with a charge transfer electrode for transferring an electric charge generated in the photoelectric conversion section, the charge transfer electrode has an alternate arrangement of a first layer electrode comprising... Agent: Birch Stewart Kolasch & Birch

20070034870 - Semiconductor device and method of fabricating the same: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070034875 - Light-emitting device: The reliability of a light-emitting device constituted by a combination of a TFT and a light-emitting element is to be improved. A light-emitting element is formed between a first substrate and a second substrate. The light-emitting device is formed over a first insulating layer made of an organic compound and... Agent: Nixon Peabody, LLP

20070034872 - Process for manufacturing a thin-film transistor (tft) device and tft device manufactured by the process: A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions... Agent: Graybeal, Jackson, Haley LLP

20070034874 - Semiconductor device and method for manufacturing the same: A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed. The method for manufacturing the semiconductor device comprises the steps of: forming a semiconductor layer 3 having a source and a... Agent: Eric Robinson

20070034873 - Semiconductor device and semiconductor display device: A semiconductor device includes a control circuit for carrying out gamma correction of a supplied signal, and a memory for storing data used in the gamma correction. The control circuit and the memory are constituted by TFTs, and are integrally formed on the same insulating substrate. A semiconductor display device... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070034871 - Thin film transistor and method of manufacturing the same: An island-like semiconductor layer is formed on a main surface of an insulating substrate. A side wall of the island-like semiconductor layer is made substantially perpendicular to the insulating substrate. An insulating film is formed along the side wall of the semiconductor layer. The insulating film is formed to include... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070034876 - Semiconductor device: A systemized active matrix display in which a pixel matrix circuit, a driver circuit and a logic circuit are mounted on the same substrate, is formed. A TFT of the present invention has such characteristics as to be able to operate in a wide driving frequency range of 0.05 to... Agent: Fish & Richardson P.C.

20070034877 - Semiconductor device and semiconductor device producing system: An insulating film having depressions and projections are formed on a substrate. A semiconductor film is formed on the insulating film. Thus, for crystallization by using laser light, a part where stress concentrates is selectively formed in the semiconductor film. More specifically, stripe or rectangular depressions and projections are provided... Agent: Eric Robinson

20070034878 - Semiconductor device and method for manufacturing the same: A memory element is formed by providing an organic compound between a pair of upper and lower electrodes. However, when the electrode is formed over a layer containing an organic compound, a temperature is limited because the layer containing the organic compound can be influenced depending on a temperature for... Agent: Eric Robinson

20070034879 - Liquid crystal display: A liquid crystal display (“LCD”) includes a data interconnection line including a data line, a source electrode as a branch of the data line, and a drain electrode formed spaced apart from the source electrode, a semiconductor layer formed under the data interconnection line and connected to the source electrode... Agent: Cantor Colburn, LLP

20070034881 - Light emitting device: When a light emitting element is actuated to allow the light emission, the generation of Joule heat occurs, leading to the decomposition or crystallization of an organic compound to cause the degradation of the light emitting device. Therefore, a light emitting element of the present invention is provided for effecting... Agent: Fish & Richardson P.C.

20070034880 - Method for the production of a plurality of opto-electronic semiconductor chips and opto-electronic semiconductor chip: A method for the production of a plurality of optoelectronic semiconductor chips and The invention relates to a method for the production of a plurality of optoelectronic semiconductor chips each having a plurality of structural elements with respectively at least one semiconductor layer. The method involves providing a chip composite... Agent: Cohen, Pontani, Lieberman & Pavane

20070034882 - Semiconductor light-emitting device: An LED chip of the present invention includes a columnar GaP substrate in which a tapered portion whose outer shape is narrowed toward an upper bottom surface side is formed in an outer wall surface thereof, an upper-surface electrode provided in an upper bottom surface of the GaP substrate, a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070034883 - Light emitting device: A light emitting device includes a transparent substrate having first and second surfaces, a semiconductor layer provided on the first surface, a first light emission layer provided on the semiconductor layer and emitting first ultraviolet light including a wavelength corresponding to an energy larger than a forbidden bandwidth of a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070034884 - Pixel cells in a honeycomb arrangement: The present invention, in the various exemplary embodiments, provides a RGB color filter array. The red, green and blue pixel cells are arranged in a honeycomb pattern. The honeycomb layout provides the space to vary the size of pixel cells of an individual color so that, for example, the photosensor... Agent: Dickstein Shapiro LLP

20070034888 - Electromagnetic radiation emitting semiconductor chip and procedure for its production: A semiconductor chip which emits electromagnetic radiation is presented. The chip includes an epitaxially produced semiconductor layer stack based on nitride semiconductor material, which includes an n-conducting semiconductor layer, a p-conducting semiconductor layer, and an electromagnetic radiation generating region, which is arranged between these two semiconductor layers. The chip further... Agent: Cohen, Pontani, Lieberman & Pavane

20070034885 - Green-emitting led: Phosphor from the class of the oxynitridosilicates, having a cation M which is doped with divalent europium and having the empirical formula M(1-c)Si2O2N2:DC, where M=Sr or M=Sr(1-x-y)BaYCax with x+y<0.5 is used, the oxynitridosilicate completely or predominantly comprising the high-temperature-stable modification HT.... Agent: Cohen, Pontani, Lieberman & Pavane

20070034887 - Phosphor-converted led devices having improved light distribution uniformity: A New Phosphor-converted LED Device (“NPCLD”) is disclosed. The NPCLD may include a lens over a phosphor body, in which the lens and the phosphor body each have a substantially convex upper surface. The NPCLD may alternatively include first and second lenses, the first lens having a substantially flat interface... Agent: Avago Technologies, Ltd.

20070034886 - Plcc package with integrated lens and method for making the package: A plastic leaded chip carrier (PLCC) package includes an encapsulant having a domed portion, which is formed as an integral single piece structure. The encapsulant may be formed using an injection molding process. Another injection molding process may be used to form a structural body of the PLCC package.... Agent: Avago Technologies, Ltd.

20070034889 - Diode housing: A housing accommodating a semiconductor chip is set out. The housing and chip may be used for sending and/or receiving radiation. Popular applications of the housing may be in light emitting diodes. The housing includes a conductor strip that is punched into two electrically isolated portions. The housing further includes... Agent: Fish & Richardson PC

20070034890 - Multiple die led and lens optical system: A light emitting device includes a number of light emitting diode dies (LEDs) mounted on a shared submount and covered with a single lens element that includes a corresponding number of lens elements. The LEDs are separated from each other by a distance that is sufficient for lens element to... Agent: Patent Law Group LLP

20070034891 - Nitride-based light emitting device and manufacturing method thereof: A light emitting device according to an exemplary embodiment of the present invention includes: an n-type cladding layer; a p-type cladding layer; an active layer interposed between the n-type cladding layer and the p-type cladding layer; and an ohmic contact layer contacting the p-type cladding layer or the n-type cladding... Agent: Cantor Colburn, LLP

20070034892 - Single-crystal nitride-based semiconductor substrate and method of manufacturing high-quality nitride-based light emitting device by using the same: A nitride-based light emitting device is manufactured by using a single-crystal nitride-based semiconductor substrate. A seed material layer is deposited on a first substrate where organic residues including a natural oxide layer are removed from an upper surface of the first substrate. A multifunctional substrate is grown from the seed... Agent: Cantor Colburn, LLP

20070034893 - Solid-state image pickup device and manufacturing method of the same: In a solid-state image pickup device according to the present invention, groove-like recesses are formed on a semiconductor substrate, and first wiring for vertical transfer electrode use are formed in the groove-like recesses, in order to reduce the distance between the semiconductor substrate and the microlens. According to the solid-state... Agent: Edwards & Angell, LLP

20070034894 - Semiconductor device including field effect transistor for use as a high-speed switching device and a power device: A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070034895 - Folded-gate mos transistor: An insulated-gate transistor includes a semiconductor layer of a first conductivity type, an insulated gate comprising a trench gate extending into the semiconductor layer, a source and a drain regions of a second conductivity type formed in the semiconductor layer at respective sides of the trench gate, wherein each one... Agent: Graybeal Jackson Haley LLP

20070034897 - Esd protecting circuit and manufacturing method thereof: An ESP protecting circuit and a manufacturing method thereof are provided. The ESP protecting circuit includes a device isolation layer, first and second high-concentration impurity regions, a third high-concentration impurity region of a complementary type, first and second conductive wells, and a fourth conductive impurity region. The ESD protecting circuit... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070034896 - Silicon-controlled rectifier for electrostatic discharge protection circuits and structure thereof: A Silicon-Controlled Rectifier (SCR) for Electrostatic Discharge (ESD) protection includes an isolation device. The isolation device isolates a main ground voltage line, connected to a first cathode, from a peripheral ground voltage line, connected to a second cathode. As result, even when noise occurs in the peripheral ground voltage line... Agent: Marger Johnson & Mccollom, P.C.

20070034898 - Heterojunction photodiode: The present invention provides a heterojunction photodiode which includes a pn or Schottky-barrier junction formed in a first material region having a bandgap energy Eg1. When reverse-biased, the junction creates a depletion region which expands towards a second material region having a bandgap energy Eg2 which is less than Eg1.... Agent: Koppel, Patrick & Heybl

20070034899 - Silicon-on-insulator photodiode optical monitoring system for color temperature control in solid state light systems: A silicon-on-insulator (SOI) photodiode optical monitoring method and system for color temperature control in solid state light systems. The method includes the steps of providing a plurality of SOI photodiodes, wherein each SOI photodiode includes a silicon substrate, a buried oxide layer formed on the silicon substrate, and a silicon... Agent: Philips Intellectual Property & Standards

20070034900 - Bipolar junction transistor and method of fabricating the same: A bipolar junction transistor is provided. A p-type well region surrounds an n-type emitter and connects with the bottom of the emitter to serve as a base. A p-type base pick-up region connects with the base and surrounds the emitter. An n-type deep well, connected to the bottom of the... Agent: Jianq Chyun Intellectual Property Office

20070034901 - Trench junction barrier controlled schottky: A Schottky diode includes at least a trenched opened in a semiconductor substrate doped with a dopant of a first conductivity type wherein the trench is filled with a Schottky junction barrier metal. The Schottky diode further includes one or more dopant region of a second conductivity type surrounding sidewalls... Agent: Bo-in Lin

20070034902 - Semiconductor device and method for manufacturing the same: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070034903 - Efficient transistor structure: An integrated circuit comprises a first drain region having a generally rectangular shape. First, second, third and fourth source regions have a generally rectangular shape and that are arranged adjacent to sides of the first drain region. A gate region is arranged between the first, second, third and fourth source... Agent: Harness, Dickey & Pierce P.L.C

20070034904 - Efficient transistor structure: An integrated circuit comprises first and second drain regions have a generally rectangular shape. First, second and third source regions have a generally rectangular shape, wherein the first source region is arranged between first sides of the first and second drain regions and the second and third source regions are... Agent: Harness, Dickey & Pierce P.L.C

20070034905 - Phase-change memory device and its methods of formation: Phase-change memory device and methods for forming the same. The phase-change memory device comprises a first electrode and at least one phase-change material layer formed over the first electrode. The at least one phase-change material layer further comprising at least one implanted region that has higher thermal characteristics than an... Agent: Dickstein Shapiro LLP

20070034906 - Mos devices with reduced recess on substrate surface: A MOS device having reduced recesses under a gate spacer and a method for forming the same are provided. The MOS device includes a gate structure overlying the substrate, a sidewall spacer on a sidewall of the gate structure, a recessed region having a recess depth of substantially less than... Agent: Slater & Matsil, L.L.P.

20070034907 - Image sensor with improved dynamic range and method of formation: Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor structure comprises at least one semiconductor channel region, at least one gate for controlling the channel region, and first and second leads respectively coupled to a... Agent: Dickstein Shapiro LLP

20070034908 - Phase change random access memory device: A phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines, each of which being connected to a plurality of phase-change memory cells; and a plurality of column select transistors selectively connecting the global bit... Agent: Volentine Francos, & Whitt PLLC

20070034909 - Nanometer-scale semiconductor devices and method of making: A semiconductor device including a substrate having a dopant of a first polarity, a first semiconducting structure including a dopant of a second polarity disposed over the substrate, and having substantially planar top and side surfaces. The semiconductor device includes a first junction, formed between the first semiconducting structure and... Agent: Hewlett Packard Company

20070034910 - Fabrication method of spiral inductor on porous glass substrate: The present invention discloses a fabrication method and structure of spiral RF inductor on porous glass substrate. Thick porous silicon layer is natively formed on a silicon wafer by anodic etching the silicon material to a high degree of porosity. The porous silicon is than thermally oxidized at high temperature... Agent: Perkins Coie LLP

20070034912 - Low voltage cmos structure with dynamic threshold voltage: A method for dynamically varying a threshold voltage of a complimentary metal oxide semiconductor (CMOS) includes providing a substrate pickup formed a semiconductor material type which is complimentary to the semiconductor material type of a well thereof, so as to define a diode. The diode is at least partially turned... Agent: Stout, Uxa, Buyan & Mullins LLP

20070034911 - Metal-oxide-semiconductor transistor and method of manufacturing the same: The trench MOS transistor according to the present invention includes a drain region in a form of a trench filled with a semiconductor material. The trench has a bottom surface and side surfaces and extends vertically downward from the top surface of the covering layer into the buried layer, the... Agent: North America Intellectual Property Corporation

20070034913 - Semiconductor device and method of fabricating same: There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel... Agent: Eric Robinson

20070034914 - Isolation trench geometry for image sensors: A pixel cell including a substrate having a top surface. A photo-conversion device is at a surface of the substrate and a trench is in the substrate adjacent the photo-conversion device. The trench has sidewalls and a bottom. At least one sidewall is angled less than approximately 85 degrees from... Agent: Dickstein Shapiro LLP

20070034915 - Transparent double-injection field-effect transistor: A double-injection field-effect transistor has an anode, a cathode, a substantially transparent channel, a substantially transparent gate insulator, and at least one substantially transparent gate electrode. The transistor may also have a substantially transparent anode and/or cathode. The transistor may also be formed on a substantially transparent substrate. Electrode contacts... Agent: Hewlett Packard Company

20070034916 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are provided. A CMOS image sensor includes: a plurality of photodiodes a predetermined distance apart on a semiconductor substrate; an insulation layer on an entire surface of the semiconductor substrate; a passivation layer on the insulation layer; a plurality... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070034917 - Dual capacitor structure for imagers: CMOS and CCD imaging devices comprising different in-pixel capacitors and peripheral capacitors and methods of formation are disclosed. The capacitors used in periphery circuits have different requirements from the capacitors used in the pixel itself. Dual stack capacitors comprising two dielectric layers may be provided to achieve low leakage and... Agent: Dickstein Shapiro LLP

20070034918 - Ferroelectric film, semiconductor device, ferroelectric film manufacturing method, and ferroelectric film manufacturing apparatus: An object of the present invention is, while decreasing a relative dielectric constant of a ferroelectric film of Sr2(Ta1-xNbx)O7 (0≦x≦1), to increase an coercive electric field thereof. The present invention is a ferroelectric film manufacturing method, which includes a film forming step of, in a processing chamber at least an... Agent: Crowell & Moring LLP Intellectual Property Group

20070034919 - Mram with super-paramagnetic sensing layer: An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external... Agent: Stephen B. Ackerman

20070034920 - Semiconductor memory cell and corresponding method of producing same: A semiconductor memory cell and production method provides a storage capacitor connected to a selection transistor. The storage capacitor is formed as a contact hole capacitor in at least one contact hole for a source or drain region. Such a semiconductor memory cell can be produced cost-effectively and allows a... Agent: Brinks Hofer Gilson & Lione

20070034921 - Access transistor for memory device: An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.... Agent: Dickstein Shapiro LLP

20070034926 - Asymmetric field effect transistor: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping... Agent: Law Office Of Monica H Choi

20070034923 - Devices with different electrical gate dielectric thicknesses but with substantially similar physical configurations: An integrated circuit is disclosed having one or more devices having substantially similar physical gate electric thicknesses but different electrical gate electric thicknesses for accommodating various operation needs. One or more devices are manufactured with a same mask set using multiple doping processes to generate substantially similar physical gate dielectric... Agent: Duane Morris LLPIPDepartment (tsmc)

20070034925 - Fin-field effect transistors (fin-fets) having protection layers: Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is provided on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is provided in the trench such that a surface of the first insulation layer is recessed beneath a surface of the... Agent: Myers Bigel Sibley & Sajovec

20070034922 - Integrated surround gate multifunctional memory device: Vertical surround gate memory cells are formed around pillars on a substrate. Each memory cell is comprised of a gate stack formed around each pillar and a gate formed around each gate stack. The substrate can have multiple integrated memory types by varying the effective oxide thickness of the tunnel... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070034924 - Semiconductor device and method of manufacturing the same: The semiconductor device 1 includes an insulating interlayer 10, interconnects 12a to 12c, an insulating interlayer 20, and a capacitor element 30. On the insulating interlayer 10 and the interconnects 12a to 12d, the insulating interlayer 20 is provided via a diffusion barrier 40. On the insulating interlayer 20, the... Agent: Young & Thompson

20070034927 - Trench storage capacitor: A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a “buried” collar insulating layer and masked with the aid of a protective layer fabricated... Agent: Edell, Shapiro & Finnan, LLC

20070034928 - Capacitor structure for two-transistor dram memory cell and method of forming same: A capacitor structure for a semiconductor assembly and a method for forming same are described. The capacitor structure comprises a pair of electrically separated capacitor electrodes and a capacitor electrode being common to only the pair of electrically separated capacitor electrodes.... Agent: Micron Technology, Inc.

20070034930 - Discrete trap non-volatile multi-functional memory device: A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device,... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070034929 - Flash memory device and method of manufacturing the same: A flash memory device and method of manufacturing the same includes a string structure having source select lines, a number of word lines and drain select lines, a first insulating film is filled between the word lines, between the word lines and the source select lines and between the word... Agent: Marshall, Gerstein & Borun LLP

20070034933 - Flash memory device utilizing nanocrystals embedded in polymer: A flash memory device with a nanoscale floating gate and a method of manufacturing thereof are disclosed. At least one embodiment of the present invention provides a much simpler and easier method of manufacturing nanocrystals (or nanocrystallines) for the flash memory device than the conventional method. Since the nanocrystals are... Agent: Knobbe Martens Olson & Bear LLP

20070034935 - Nonvolatile semiconductor memory device and a method of the same: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070034932 - Nor flash memory devices and methods of fabricating the same: A flash memory device includes active regions formed in a semiconductor substrate. The active regions include a cell array region, a high voltage transistor region and a low voltage transistor region. Gate structures are formed across the active regions, source and drain regions are formed at both sides of the... Agent: Harness, Dickey & Pierce, P.L.C

20070034934 - Semiconductor memory device with a stacked gate including a floating gate and a control gate and method of manufacturing the same: A semiconductor memory device includes first and second MOS transistors. The first MOS transistor is formed on a region enclosed by a first element isolating region and includes a first gate insulating film and a first gate electrode. The second MOS transistor is formed on a region enclosed by a... Agent: Frommer Lawrence & Haug

20070034931 - Systems and methods for memory structure comprising a pprom and an embedded flash memory: A memory structure that combines embedded flash memory and PPROM. The PPROM can be used as a memory structure. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. The PPROM cells are stacked on top of the flash memory cells... Agent: Baker & Mckenzie LLP Patent Department

20070034937 - Semiconductor device and a method of manufacturing the same: A method of manufacturing a semiconductor device comprises forming a side wall spacer on side walls of an auxiliary gate in such a way that a CVD method using dichlorosilane as a staring material is carried out for deposition of a so-called high temperature oxide film (HTO film) at a... Agent: Miles & Stockbridge PC

20070034936 - Two-transistor memory cell and method for manufacturing: The present invention provides a method of manufacturing on a substrate (50) a 2-transistor memory cell comprising a storage transistor (1) having a memory gate stack (1) and a selecting transistor, there being a tunnel dielectric layer (51) between the substrate (50) and the memory gate stack. (1). The method... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070034939 - Image sensors with enhanced charge transmission characteristics: An image sensor includes photoelectric conversion elements formed adjacent to each other on a substrate. Two transmission elements transmit charge accumulated in two adjacent photoelectric conversion elements to a first floating diffusion region, and another two transmission elements transmit charge accumulated in the other two photoelectric conversion elements to a... Agent: Harness, Dickey & Pierce, P.L.C

20070034938 - Non-volatile memory devices and methods of forming non-volatile memory devices: A non-volatile memory device including a barrier spacer that serves to protect a control gate, including a metal layer, from damage that may result from exposure to a cleaning solution and/or oxygen. With the barrier spacer layer, a cleaning process using a high-power cleaning solution may be used to effectively... Agent: Lee & Morse, P.C.

20070034940 - Mos semiconductor device: A semiconductor device comprises a gate electrode provided on a gate insulating film, a side wall insulating film provided on a side wall of the gate electrode through a protection insulating film, a barrier SiN film provided to cover the gate electrode and the side wall insulating film, an inter-level... Agent: Foley And Lardner LLP Suite 500

20070034941 - Deep n diffusion for trench igbt: An increased conductivity deep diffusion of the same conductivity type as that of the drift region is provided between adjacent trenches of a trench type IGBT and below the trenches to reduce the on resistance components of the drift region resistance and spreading resistance to current flow when the device... Agent: Ostrolenk Faber Gerb & Soffen

20070034942 - Power ldmos transistor: A LDMOS transistor comprises a trench formed through the epitaxial layer at least to the top surface of the substrate, the trench having a bottom surface and a sidewall contacting the source region and the portion of the channel region extending under the source region. A first insulating layer is... Agent: Duane Morris, LLPIPDepartment

20070034943 - Insulated gate semiconductor device and manufacturing method thereof: Two metal electrode layers are provided. A first electrode layer is patterned with a minute separation distance according to an element region as in the case of the conventional case. Meanwhile, it suffices that a second electrode layer be in contact with the first electrode layer. Thus, no problems arise... Agent: Morrison & Foerster LLP

20070034944 - Power ldmos transistor: A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device includes a doped substrate having an epitaxial layer thereover having source and drain implant regions and body and lightly doped drain regions formed therein. The channel region and lightly doped drain regions are doped to a depth to abut the top surface of... Agent: Duane Morris, LLPIPDepartment

20070034945 - Pmos transistor strain optimization with raised junction regions: Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship... Agent: Intel/blakely

20070034946 - Semiconductor device: The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control... Agent: Miles & Stockbridge PC

20070034947 - Semiconductor device having deep trench charge compensation regions and method: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.L.C.

20070034948 - Silicidation process for an nmos transistor and corresponding integrated circuit: An integrated circuit provided with an NMOS transistor includes a metal silicide on source, drain and gate regions and also on at least one portion of the source and drain extension zones The metal silicide portion located on the source and drain extension zones is thinner than the metal silicide... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070034949 - Semiconductor device having multiple source/drain extension implant portions and a method of manufacture therefor: The present invention provides a semiconductor device, a method for manufacturing therefore, and an integrated circuit including the same. The semiconductor device, in one advantageous embodiment, includes a gate structure (230) located over a substrate (210), and a source/drain region (250) located within the substrate (210) and proximate the gate... Agent: Texas Instruments Incorporated

20070034952 - Method of manufacturing semiconductor device having impurity region under isolation region: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming... Agent: Mcdermott Will & Emery LLP

20070034951 - Schotiky barrier tunnel transistor and method of manufacturing the same: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The... Agent: Ladas & Parry LLP

20070034953 - Semiconductor device and method of fabricating same: A semiconductor device includes: a semiconductor substrate; a first transistor including a first gate electrode including a first metallic silicide layer, the first gate electrode being formed on the semiconductor substrate through a first gate insulating film, a first gate sidewall insulating film formed on a side face of the... Agent: Foley And Lardner LLP Suite 500

20070034950 - Semiconductor wafer and method of fabricating the same: Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second... Agent: Marger Johnson & Mccollom, P.C.

20070034954 - Thin film conductor and method of fabrication: A thin film conductor having improved adhesion and superior conductivity, a method for fabricating the same, a thin film transistor (TFT) plate including the thin film conductor, and a method for fabricating the TFT plate are provided. The thin film conductor includes an adhesive layer containing an oxidation-reactive metal or... Agent: Macpherson Kwok Chen & Heid LLP

20070034955 - Nonvolatile semiconductor integrated circuit devices and fabrication methods thereof: In a method for manufacturing a semiconductor device, an oxide layer, a first polysilicon layer, and a second polysilicon layer are sequentially provided on a substrate. A first hard mask pattern is provided on the second polysilicon layer. The oxide layer, the first polysilicon layer, and the second polysilicon layer... Agent: Mills & Onello LLP

20070034958 - Electro-static discharge protecting device and method for fabricating the same: Provided are an ESD protecting device and a method for fabricating the same. The ESD protecting device includes a semiconductor substrate having a first conductivity type, the semiconductor substrate having a field region and an active region; first and second device isolation layers formed in the field region; a first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070034957 - Electrostatic foot for non-permanent attachment: An apparatus in one example has: an electrostatic device having an engagement portion; and an attractive electrostatic force selectively applicable by the electrostatic device to the engagement portion for at least one of holding the electrostatic device or providing locomotion to the electrostatic device.... Agent: Carmen B. Patti & Associates, LLC

20070034956 - Embedded silicon-controlled rectifier (scr) for hvpmos esd protection: A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain region doped with a p-type impurity in a high voltage p-well (HVPW)... Agent: Slater & Matsil, L.L.P.

20070034959 - Integrated circuit arrangements with esd-resistant capacitor and corresponding method of production: A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite... Agent: Brinks Hofer Gilson & Lione

20070034960 - Esd protection structure using contact-via chains as ballast resistors: According to an exemplary embodiment, an ESD protection structure situated in a semiconductor die includes a FET including a gate and first and second active regions, where the gate includes at least one gate finger, and where the at least one gate finger is situated between the first and second... Agent: Farjami & Farjami LLP

20070034961 - Semiconductor device, display device, and electronic device: It is an object of the invention to provide a semiconductor device having a level shifter, a differential amplifier circuit, and the like, where power consumption is reduced by reducing an unnecessary through current and distortion of an output waveform can be suppressed. A gate terminal of a first transistor... Agent: Eric Robinson

20070034962 - Transistor and method of manufacturing the same: In a transistor and a method of manufacturing the transistor, the transistor includes a dummy structure enclosing source/drain structures and channel structures. Thus, a gate electrode of the transistor may be efficiently formed over the channel structures. In addition, the source/drain structure may not grow exceedingly in an epitaxial growth... Agent: Mills & Onello LLP

20070034965 - Cmos image sensor having drive transistor with increased gate surface area and method of manufacturing the same: A CMOS image sensor cell includes a semiconductor active region of first conductivity type having a surface thereon and a P-N junction photodiode in the active region. A drive transistor is also provided in the semiconductor active region. The drive transistor has a gate electrode that is configured to receive... Agent: Myers Bigel Sibley & Sajovec

20070034966 - Dual gate cmos semiconductor devices and methods of fabricating such devices: Disclosed are dual gate CMOS devices and methods for fabricating such devices. The dual gate structures are produced by forming a first gate electrode having first conductive stack on transistors of a first channel type and forming a second gate electrode having a second conductive stack on transistors of a... Agent: Harness, Dickey & Pierce, P.L.C

20070034964 - Dual gate structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method: In one embodiment, a semiconductor device includes at least two stacked gate structures formed on a substrate. The two stacked gate structures each include a semiconductor layer and a metal layer over the semiconductor layer. The two stacked gate structures on the substrate are characterized by differential intermediate layers, one... Agent: Marger Johnson & Mccollom, P.C.

20070034967 - Metal gate mosfet by full semiconductor metal alloy conversion: A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to... Agent: International Business Machines Corporation Dept. 18g

20070034963 - Semiconductor device with close stress liner film and method of manufacturing the same: Aspects of the present disclosure are generally directed to FETs with stress liners that are closer than typical stressed FETs, as well as methods for manufacturing the same. FETE channel sidewall spacers may be removed, or substantially reduced in width, prior to forming the stress liners. This may be performed... Agent: Banner & Witcoff

20070034968 - Semiconductor integrated circuit device and a method of manufacturing the same: In order to improve the soft error resistance of a memory cell of an SRAM without increasing its chip size in deep through-holes formed by perforating a silicon oxide film, there is a silicon nitride film and a silicon oxide film, a capacitor element having a TIN film serving as... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070034969 - Semiconductor device having a gate electrode material feature located adjacent a gate width side of its gate electrode and a method of manufacture therefor: The present invention provides a semiconductor device, a method of manufacture therefore and an integrated circuit including the same. The semiconductor device (300), without limitation, may include a gate electrode (320) having a gate length (l) and a gate width (w) located over a substrate (310) and a gate electrode... Agent: Texas Instruments Incorporated

20070034970 - Semiconductor device and method of fabricating the same: The semiconductor device comprises a semiconductor substrate having a first active region, wherein the first active region includes a recessed region, a first gate formed on a channel between impurity regions formed on the first active region, and a second gate having a recessed upper surface, wherein a profile of... Agent: F. Chau & Associates, LLC

20070034971 - Chevron cmos trigate structure: Disclosed herein is a structure with two different type tri-gate MOSFETs formed on the same substrate. Each MOSFET comprises a fin with optimal mobility for the particular type of MOSFET. Due to the processes used to form fins with different crystalline orientations on the same substrate, one of the MOSFETs... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070034972 - Tri-gate devices and methods of fabrication: The present invention is a semiconductor device comprising a carbon nanotube body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the carbon nanotube body and on the laterally opposite sidewalls of the carbon nanotube body.... Agent: Intel/blakely

20070034973 - Methods and apparatus for operating a transistor using a reverse body bias: Some embodiments of the present invention provide methods and apparatus for operating a transistor including at least one fully depleted channel region in and/or on a substrate. The methods include applying a reverse body bias to the substrate when turning on the transistor. The substrate may be a bulk wafer... Agent: Myers Bigel Sibley & Sajovec

20070034974 - Semiconductor device and manufacturing method thereof: A semiconductor device comprises a semiconductor region including silicon, and an insulating film including silicon, oxygen, nitrogen, and helium, the dielectric film provided on the semiconductor region, and the dielectric film having a concentration distribution with respect to a film thickness direction, the concentration distribution having a maximal value of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070034976 - Micromechanical capacitive transducer and method for manufacturing the same: A micromechanical capacitive converter and a method for manufacturing a micromechanical converter comprise a movable membrane and an electrically conductive face element in a carrier layer. The electrically conductive face element is arranged opposite the membrane above a cavity. The electrically conductive face element and the carrier layer are perforated... Agent: Maginot, Moore & Beck Chase Tower

20070034975 - Nanotube semiconductor structures with varying electrical properties: There is disclosed a nanotube sensor which essentially employs a straight or twisted nanotube deposited on a supporting surface, such as silicon, silicon dioxide and some other semiconductor or metal material. The nanotube is basically a graphite device which is now subjected to stress causing the electrical characteristics of the... Agent: Plevy & Howard & Darcy P.C.

20070034977 - Reflector and projection type display apparatus: It is an object to prevent deterioration of reflectance of a reflection layer composed of silver or a silver alloy, resulting from heat-caused migration of silver. The reflector for projection type display apparatuses which display image light beams emitted and reflected by a light source, modulated for light intensity by... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070034978 - Photonic crystal emitter, detector and sensor: An infrared emitter, which utilizes a photonic bandgap (PBG) structure to produce electromagnetic emissions with a narrow band of wavelengths, includes a semiconductor material layer, a dielectric material layer overlaying the semiconductor material layer, and a metallic material layer having an inner side overlaying the dielectric material layer. The semiconductor... Agent: Mcdermott Will & Emery LLP Attn: Intellectual Property Deptartment

20070034979 - Microelectronic imaging units and methods of manufacturing microelectronic imaging units: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to... Agent: Dickstein Shapiro LLP

20070034982 - Cmos image sensor and method for fabricating the same: A complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same are disclosed. The image sensor includes a sub-layer having a photodiode and a plurality of transistors formed thereon, a pad insulating layer formed on the sub-layer, a micro-lens formed on the pad insulating layer, the micro-lens... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070034983 - Cmos imager with selectively silicided gates: The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.... Agent: Dickstein Shapiro LLP

20070034980 - Photodiode and phototransistor: A phototransistor includes a first-conduction-type lower region, a second-conduction-type upper region disposed on the first region, a second-conduction-type electrode contact region of a high concentration disposed at a surface inside of the upper region and is connected to an electrode so as to transmit a signal, a first-conduction-type first shield... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20070034981 - Solid-state imaging device and method for producing the same: In the solid-state imaging device of the present invention having a photoelectric conversion section and a charge transfer section equipped with a charge transfer electrode for transferring an electric charge generated in the photoelectric conversion section, the charge transfer electrode has an alternate arrangement of a first layer electrode comprising... Agent: Birch Stewart Kolasch & Birch

20070034984 - Chip-scale schottky device: A chip-scale schottky package which has at least one cathode electrode and at least one anode electrode disposed on only one major surface of a die, and solder bumps connected to the electrode for surface mounting of the package on a circuit board.... Agent: Ostrolenk Faber Gerb & Soffen

20070034985 - Semiconductor device and method of manufacturing the same: A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070034986 - Semiconductor device: Disclosed is a semiconductor device including a base region having a first conductive type, a drain region and a source region having a second conductive type, a gate insulation film and a gate electrode formed on a channel formation region and on a part of the drain region and the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070034989 - Capacitive element, method of manufacture of the same, and semiconductor device: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070034988 - Metal-insulator-metal (mim) capacitors formed beneath first level metallization and methods of forming same: A metal-insulator-metal (MIM) capacitor for an integrated circuit may be provided on the interlayer insulating layer and covered by a inter-metal dielectric (IMD) layer. This IMD layer has at least a first opening therein that exposes an upper surface of a first electrode of the MIM capacitor. This first opening... Agent: Myers Bigel Sibley & Sajovec

20070034987 - Photocathode structure and operation: A novel photocathode employing a rectifying junction is described that permits color imaging extending applications for photocathodes in various instruments and night vision devices.... Agent: Stanley Z Cole

20070034990 - Method for manufacturing a resistor: A method of manufacturing a resistor is provided. At first, a semiconductor layer including at least a high resistance region and a low resistance region is formed on a substrate. Following that, a first ion implantation process is performed to the entire surface of the semiconductor layer, and a second... Agent: North America Intellectual Property Corporation

20070034991 - Semiconductor device: To reduce the ratio of the area of a diode region relative to the chip area. A semiconductor device comprises an insulated gate transistor formed on a substrate 1, a plurality of diodes D1, D2, and D3 formed on the substrate 1 and connected in serial between the gate of... Agent: Young & Thompson

20070034992 - Insulating film-forming composition, insulating film and production method thereof: An insulating film-forming composition comprising: at least one of a compound represented by formula (1) as defined in the specification, a hydrolysate and a condensate thereof; and at least one solvent, wherein the at least one solvent contains an organic solvent(s) having a boiling point of 85 to 250° C.... Agent: Sughrue Mion, PLLC

20070034995 - Optical semiconductor device and method of manufacturing the same: An optical semiconductor device of which the moisture resistance and the like are improved and the manufacturing method thereof are provided. An optical semiconductor device of the embodiment is configured to include an optical semiconductor element on a surface of which a circuit portion including a light-receiving or light-emitting element... Agent: Fish & Richardson P.C.

20070034994 - Package frame and semiconductor package using the same: Provided are a lead frame and a semiconductor package which allows reliable attachment of a small-sized semiconductor chip requiring a large number of leads to a board while providing high heat dissipation capability. The semiconductor package includes leads, each having a top plate extending inward from the outside edge of... Agent: Hiscock & Barclay, LLP

20070034993 - Semiconductor assembly and packaging for high current and low inductance: A device comprising a semiconductor chip (110) having a side edge (111) and a plurality of metal bond pads (120, 121) near the edge; the pads are aligned to form rows (130, 131) parallel to the edge. The device further includes a leadframe (100) having leads (140 . . .... Agent: Texas Instruments Incorporated

20070034996 - System and method for forming one or more integrated circuit packages using a flexible leadframe structure: In certain embodiments, a leadframe structure for forming one or more integrated circuit packages includes a number of adjacent substantially parallel lead bars adapted to receive a die associated with an integrated circuit at one or more of the lead bars such that the one or more lead bars extend... Agent: Texas Instruments Incorporated

20070034997 - Semiconductor device with conductor tracks between semiconductor chip and circuit carrier and method for producing the same: The invention relates to a semiconductor device with conductor tracks between a semiconductor chip and a circuit carrier, and to a method for producing the same. The conductor tracks extend from contact areas on the top side of the semiconductor chip to contact pads on the circuit carrier. The conductor... Agent: Edell, Shapiro & Finnan, LLC

20070034998 - Method for fabricating wafer level semiconductor package with build-up layer: A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass... Agent: Edwards & Angell, LLP

20070034999 - Chip module and chip card: A chip module and to a chip card with a chip module which can be bent in such a way that a cross-sectional area runs along the greatest curvature of the bending line and parallel to one side of the chip module or the chip card. The module comprises contact... Agent: Dickstein Shapiro LLP

20070035000 - Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit board, and electronic device: A semiconductor device includes: a semiconductor substrate having an active face; a first electrode provided on or above the active face; an external connection terminal provided on or above the active face and electrically connected to the first electrode; and a connection terminal provided on or above the active face... Agent: Harness, Dickey & Pierce, P.L.C

20070035001 - Chip scale package for a micro component: A package includes a sensor die with a micro component, such as a MEMS device, coupled to an integrated circuit which may include, for example, CMOS circuitry, and one or more electrically conductive bond pads near the periphery of the sensor die. A semiconductor cap structure is attached to the... Agent: Fish & Richardson P.C.

20070035002 - Semiconductor device and a manufacturing method of the same: Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of... Agent: Miles & Stockbridge PC

20070035004 - Semiconductor module: The present invention realizes strengthening of a ground of a lower-surface ground electrode of an upper semiconductor chip and miniaturization in a semiconductor module on which two semiconductor chips are mounted in a stacked manner. A lower semiconductor chip is fixed to a bottom of a recess formed in an... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070035003 - Three-dimensional stack manufacture for integrated circuit devices and method of manufacture: An integrated circuit package assembly formed by stacking flip-chip mounted substrates interleaved with precisely dimensioned spacers and then bonded by injection molding the stack. The sides of the stack are sawed off to expose vias in the substrates, and multilevel-interconnect substrates are precisely aligned on the sides of the stack.... Agent: Dillon & Yudell LLP

20070035005 - Alternating micro-vias and throughboard vias to create pcb routing channels in bga interconnect grid: A printed circuit board (PCB) assembly having a plurality of circuit layers including outer layers and intervening layers with through-vias and micro-vias used to translate a portion of the signal connections of the grid, thereby creating a set of diagonal routing channels between the vias on internal layers of the... Agent: Law Office Of Jim Zegeer

20070035006 - Stackable single package and stacked multi-chip assembly: A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate contact pads arranged around a periphery portion of the substrate. A chip mounted on the substrate including contact pads that are electrically connected with the conductive wiring... Agent: Slater & Matsil LLP

20070035007 - Differential chip performance within a multi-chip package: A multi-chip package comprises a first die comprising a first integrated circuit and a second die comprising a second integrated circuit. A first plurality of contact pads disposed on the first die are coupled to the first integrated circuit, wherein the first plurality of contact pads comprises a first mode... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070035009 - Printed circuit board, semiconductor package and multi-stack semiconductor package using the same: In an example embodiment, a printed circuit board (PCB) includes a package substrate having a plurality of first solder balls and a first resist layer formed on the first side. The first resist layer may have a plurality of first elliptical openings. Each of the first elliptical openings exposes a... Agent: Harness, Dickey & Pierce, P.L.C

20070035008 - Thin ic package for improving heat dissipation from chip backside: A thin IC package to enhance heat dissipation from the back surface of a chip, comprises a substrate, the chip, and an encapsulant where the substrate has an upper surface, a lower surface, and an opening to accommodate the chip. The chip is disposed in the opening of the substrate... Agent: Troxell Law Office PLLC

20070035010 - Circuit substrate: A circuit substrate includes a carrier, at least one non-conductive diamond-like carbon layer provided on a top surface of the carrier, at least one conductive film-coating layer provided on a surface of the non-conductive diamond-like carbon layer and in the form of a conductive logical circuitry, an upper non-conductive diamond-like... Agent: Pro-techtor International Services

20070035011 - Integrated circuit apparatus with heat speader: An integrated circuit apparatus with heat removal has an electrical interconnection network. The electrical interconnection network has a plurality of electrically and thermally conductive vias in electrical communication with terminals of at least one semiconductor device. An electrically insulating heat spreader is chemically bonded to each of the vias at... Agent: Tyson J. Wilde Novatek International, Inc.

20070035012 - Integrated solder and heat spreader fabrication: A system may include an integrated heat spreader that includes a portion of solder material and a thermal conductor, wherein a voidless interface exists between the solder material and a first side of the thermal conductor.... Agent: Buckley, Maschoff, Talwalkar LLC

20070035013 - Module with built-in circuit elements: In a module including circuit elements, a plurality of wires, which are generally two-dimensionally formed, are multi-layered via electrically insulating material, which comprises a mixture including at least filler and electrically insulating resin. One or more circuit elements are electrically connected to the wires, and at least a part of... Agent: Mcdermott Will & Emery LLP

20070035014 - Method and circuit for reducing series inductance of a decoupling capacitor in a ball grid array (bga): A method reduces a value of an inductance in series with a decoupling capacitor for a ball grid array. The ball grid array includes a plurality of conductive balls coupled to conductive interconnects exposed on a surface of a circuit board. The surface includes a periphery and an interior and... Agent: Hewlett Packard Company

20070035016 - Semiconductor device: A semiconductor device includes a chip having a base semiconductor layer, an insulation layer provided on the base semiconductor layer, and an upper semiconductor layer provided on the insulation layer; a mounting substrate on which the chip is mounted at the base semiconductor layer; and a connecting portion that electrically... Agent: Arent Fox PLLC

20070035015 - Stack structure with semiconductor chip embedded in carrier: A stack structure with semiconductor chips embedded in carriers comprises two carriers stacking together as a whole, at least two semiconductor chips having active surfaces with electrode pads and inactive surfaces corresponding thereto placed in the cavities of the carriers, at least one dielectric layer formed on the active surface... Agent: Mr. Joseph A. Sawyer, Jr. Sawyer Law Group LLP

20070035017 - Semiconductor device: A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070035018 - Mount for a programmable electronic processing device: A processing device embodied in an integrated circuit may be divided into first and second functional units. A mount for the integrated circuit may be assigned to the first functional unit, which may define the external electrical connections of the processing device. Processing may take place in a second functional... Agent: O'shea, Getz & Kosakowski, P.C.

20070035019 - Semiconductor component and method of manufacture: A semiconductor component having a positionally adaptable locking feature and a method for manufacturing the semiconductor component using a wire bond tool. A conductive support substrate having a flag portion, a lead portion and tie-bars is provided. A semiconductor chip is coupled to the flag portion of the conductive support... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070035021 - Printed circuit board and electronic apparatus including printed circuit board: According to one embodiment, a printed circuit board includes a printed wiring board, a semiconductor package, an adhesive and a stepped portion. The printed wiring board has a plurality of pads. The semiconductor package has a plurality of connection terminals corresponding to the pads and is mounted on the printed... Agent: Knobbe Martens Olson & Bear LLP

20070035020 - Semiconductor apparatus and semiconductor module: A semiconductor apparatus includes a semiconductor substrate, a through-electrode, a solder bump, and a circuit element. The semiconductor substrate has an electronic device formed on its front face. The through-electrode extends through the semiconductor substrate. The solder bump is disposed on the front side of the semiconductor substrate. The circuit... Agent: Fish & Richardson P.C.

20070035022 - Semiconductor device and method of manufacturing the same: A semiconductor device, including: a semiconductor layer; an electrode pad formed above the semiconductor layer; an insulating layer formed over the electrode pad and having an opening which exposes at least part of the electrode pad; and a bump formed at least in the opening. The bump includes: a first... Agent: Harness, Dickey & Pierce, P.L.C

20070035023 - Semiconductor device having improved mechanical and thermal reliability: A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic... Agent: Texas Instruments Incorporated

20070035024 - Semiconductor device having an improved wiring or electrode structure: An ohmic electrode is formed by stacking a lower Ti layer, a diffusion preventing layer, an upper Ti layer, and a metallic (Au) layer on a p-type GaAs layer. The diffusion preventing layer includes tantalum (Ta) or niobium (Nb). Thus, interdiffusion of Ga and As in the p-type GaAs layer... Agent: Leydig Voit & Mayer, Ltd

20070035025 - Damascene processing using dielectric barrier films: Damascene processing is implemented with dielectric barrier films for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films to avoid misalignment problems. Embodiments further include dual damascene processing using Cu metallization.... Agent: Mcdermott Will & Emery LLP

20070035027 - Method for forming conductors in semiconductor devices: A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a... Agent: Michael G. Fletcher Fletcher Yoder

20070035028 - Semiconductor memory devices and methods of fabricating the same: Integrated circuit memory devices include an integrated circuit substrate and a plurality of lower wiring lines on the substrate and extending in a first direction. An interlayer insulating layer is on the plurality of lower wiring lines. An upper damascene wiring line is in an upper portion of the interlayer... Agent: Robert W. Glatz Myers Bigel Sibley & Sajovec, P.A.

20070035026 - Via in semiconductor device: An opening in a semiconductor device with improved step coverage. The opening comprises a dielectric layer overlying a substrate, having at least one via opening to expose the substrate. The via opening comprises a step region in the upper portion of the via opening and a concave profile region with... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070035029 - Production of a self-aligned cusin barrier: A semiconductor product includes a portion made of copper, a portion made of a dielectric and a self-aligned barrier between the copper portion and the dielectric portion. The self-aligned barrier includes a first copper silicide layer comprising predominantly first copper silicide molecules, and a second copper silicide layer comprising predominantly... Agent: Jenkens & Gilchrist, PC

20070035030 - Techniques for providing decoupling capacitance: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or... Agent: Ryan, Mason & Lewis, LLP

20070035031 - Sub-resolution assist feature to improve symmetry for contact hole lithography: A method of making a mask design having optical proximity correction features is provided. The method can include obtaining a target pattern comprising a plurality of target pattern features corresponding to a plurality of features to be imaged on a substrate. The method can also comprise generating a mask design... Agent: Texas Instruments Incorporated

20070035032 - Semiconductor device having aerial wiring and manufacturing method thereof: A semiconductor device includes a first aerial wiring including a first wiring layer which is formed in an air gap and contains Cu as a main component and a via layer which is electrically connected to the first wiring layer, is formed in an inter-level insulating film containing a preset... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070035033 - Stackable tier structure comprising high density feedthrough: A stackable tier structure comprising one or more integrated circuit die and one or more feedthrough structures is disclosed. The 1/0 pads of the integrated circuit die are electrically rerouted using conductive traces from the first side of the tier structure to a feedthrough structure comprising one ore more conductive... Agent: W. Eric Boyd, Esq. Irvine Sensors Corporation

20070035034 - System and method for improved auto-boating: According to one embodiment of the invention, a method for auto-boating includes supporting a tape substrate having first and second end portions on a boat, sandwiching the first and second end portions between respective ones of a pair of end sleeves and the boat, coupling a boat clip to the... Agent: Texas Instruments Incorporated

20070035035 - Bonded structure and bonding method: An aluminum wire is bonded to a silicon electrode by a wedge tool pressing the aluminum wire against the silicon electrode. In this way, a firmly bonded structure is obtained by sequentially stacking aluminum, aluminum oxide, silicon oxide, and silicon.... Agent: Mcdermott Will & Emery LLP

20070035036 - Semiconductor device, laminated semiconductor device, and wiring substrate: The semiconductor device according to the present invention includes a semiconductor chip and a wiring substrate on which a wiring pattern is formed. The wiring pattern includes wire bond terminals being electrically connected, via wires, with pads provided on the semiconductor chip. The wire bond terminals are disposed in a... Agent: Nixon & Vanderhye, PC

20070035038 - Novel bonding pad structure to minimize imd cracking: A method is disclosed of forming a bonding pad that is immune to IMD cracking. A partially processes semiconductor wafer is provided having all metal levels completed. A blanket dielectric layer is formed over the uppermost metal level. Patterning and etching said dielectric layer horizontal and vertical arrays of trenches... Agent: Duane Morris, LLPIPDepartment

20070035037 - Semiconductor chip and multi-chip package: There is provided a semiconductor chip and a multi-chip package. Each semiconductor chip includes a plurality of pads formed on a first surface thereof and electrically connected to an integrated circuit, and interconnection patterns formed as stripes on a second surface of the semiconductor chip. The interconnection patterns are formed... Agent: F. Chau & Associates, LLC

20070035039 - Overlay marker for use in fabricating a semiconductor device and related method of measuring overlay accuracy: An overlay marker adapted for use in fabricating a semiconductor device and a method of measuring overlay accuracy using the overlay marker are disclosed. The semiconductor device comprises sequentially disposed first, second, and third material layers, and the overlay marker comprises a primary marker and a secondary marker. The primary... Agent: Volentine Francos, & Whitt PLLC

20070035040 - Alignment error measuring mark and method for manufacturing semiconductor device using the same: A substrate reference mark 110 is produced by forming a concavity by an erosion caused from a chemical mechanical polishing a tungsten on a surface of a interlayer film 132 after holes for substrate reference mark 111 is formed on the interlayer film 132 at a predetermined density and the... Agent: Rabin & Berdo, PC

20070035041 - Methods of forming and using memory cell structures: A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator. The metallic material... Agent: Dickstein Shapiro LLP

20070029538 - Method for fabricating an integrated device comprising a structure with a solid electrolyte: Method for fabricating an integrated device, comprising the step of providing a substrate, which includes an electrode element, and a step of providing a solid electrolyte element coupled to the electrode element. The solid electrolyte element is provided in a crystalline state and in conjunction with electrode element such to... Agent: Morrison & Foerster LLP

20070029537 - Phase change memory cell and method of formation: A phase change memory element and methods for forming the same are provided. The memory element includes a first electrode and a chalcogenide comprising phase change material layer over the first electrode. A metal-chalcogenide layer is over the phase change material layer. The metal chalcogenide layer is tin-telluride. A second... Agent: Dickstein Shapiro LLP

20070029539 - Light-emitting element array and display apparatus: There is provided a light-emitting element array having a plurality of light-emitting elements of different emission colors each comprising a light extraction electrode, a reflecting electrode, and an organic layer disposed between the electrodes, said organic layer comprising a light-emitting layer and a carrier-transporting layer disposed between the light-emitting layer... Agent: Fitzpatrick Cella Harper & Scinto

20070029540 - Semiconductor device: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070029541 - High efficiency light emitting device: A highly efficient III-nitride/II-Oxide light emitting device that has a n++-tunneling layer, which comprises at least one material selected from a group consisting of n++-GaN, n++-InGaN, n++-AlGaN, n++-AlGaInN, n++-ZnO, n++-ZnCdO, n++-ZnMgO, n++-ZnMgCdO, that is deposited on top of the p-layer in a LED structure. After that, a top n-layer is... Agent: Gregory B. Gulliver The Eclipse Group

20070029542 - Semiconductor optical device: A semiconductor optical device comprises a first conductive type III-V compound semiconductor layer, a second conductive type III-V compound semiconductor layer, and an active region. The first conductive type III-V compound semiconductor layer is provided on a substrate. The second conductive type III-V compound semiconductor layer is provided on the... Agent: Smith, Gambrell & Russell

20070029544 - Interconnected high speed electron tunneling devices: An integrated circuit chip includes a formation of integrated layers configured to define at least one integrated electronic component. The integrated layers further define an integrated electron tunneling device, which includes first and second non-insulating layers spaced apart from one another such that a given voltage can be provided thereacross.... Agent: Pritzkau Patent Group

20070029543 - Semiconductor device: To enhance the super-junction effect of a semiconductor device having the super-junction structure and prevent lowering in the breakdown voltage, a semiconductor device described herein has a first-conductivity-type substrate having an element forming region having a gate electrode and a source electrode formed therein, and a periphery region formed around... Agent: Young & Thompson

20070029548 - El display device and a method of manufacturing the same: To provide a high throughput film deposition means for film depositing an organic EL material made of polymer accurately and without any positional shift. A pixel portion is divided into a plurality of pixel rows by a bank, and a head portion of a thin film deposition apparatus is scanned... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070029545 - Pixel having an organic light emitting diode and method of fabricating the pixel: A pixel having an organic light emitting diode (OLED) and method for fabricating the pixel is provided. A planariza-tion dielectric layer is provided between a thin-film transistor (TFT) based backplane and OLED layers. A through via between the TFT backplane and the OLED layers forms a sidewall angle of less... Agent: Pearne & Gordon LLP

20070029547 - Process for forming organic layers, organic electronic devices,and transistors: Organic electronic devices are fabricated by a process includes forming an organic layer including: placing a first liquid composition over a first portion of a surface of a substrate without a well structure connected to or adjacent the first portion of the surface of the substrate, i) the first portion... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070029546 - Resistive memory cell, method for forming the same and resistive memory array using the same: A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell... Agent: Marger Johnson & Mccollom, P.C.

20070029549 - Providing current control over wafer borne semiconductor devices using overlayer patterns: Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer (1240) having a substrate (1240), at least one active layer (1240) and at least one surface layer (1240), Current control can be achieved through the formation of patterns (1240) surrounding contacts (1215), said patterns (1240) including insulating... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20070029550 - Liquid crystal display apparatus: A liquid crystal display apparatus comprises a liquid crystal display panel including a first substrate containing a color filter including a plurality of coloring layers, a second substrate arranged opposite to the first substrate and including a display surface on an opposite side to the first substrate and a liquid... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070029552 - Liquid crystal display panel and fabricating method thereof: A liquid crystal display panel and a fabricating method thereof for reducing the number of data lines and the capacitance of a parasitic capacitor between pixel electrodes are disclosed. A first switching part has at least two thin film transistors for applying a first pixel signal that is supplied to... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070029551 - Thin film transistor substrate using a horizontal electric field: A thin film transistor substrate structure for using a horizontal electric field includes a substrate; a gate line and a first common line formed on the substrate parallel to each other from a first conductive layer; a gate insulating film formed on the substrate, the gate line, and the first... Agent: Morgan Lewis & Bockius LLP

20070029553 - Methods of fabricating strained semiconductor-on-insulator field-effect transistors and related devices: A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor layers to extend onto the insulating layer between the second semiconductor layers. The... Agent: Myers Bigel Sibley & Sajovec

20070029554 - Light-emitting device and manufacturing method thereof: To prevent a point defect and a line defect in forming a light-emitting device, thereby improving the yield. A light-emitting element and a driver circuit of the light-emitting element, which are provided over different substrates, are electrically connected. That is, a light-emitting element and a driver circuit of the light-emitting... Agent: Fish & Richardson P.C.

20070029555 - Edge-emitting led light source: Edge-emitting LED light source, and method for fabricating an edge-emitting LED light source. The edge-emitting LED light source has a plurality of edge-emitting LEDs arranged in close proximity to one another to define an array of edge-emitting LEDs. Light beams separately emitted by each of the plurality of edge-emitting LEDs... Agent: Avago Technologies, Ltd.

20070029556 - Solution processed crosslinkable hole injection and hole transport polymers for oleds: A fully solution-processed polymer electroluminescent device has a hole injection layer fabricated using a crosslinkable hole injection/transport material doped with conductivity dopants.... Agent: Fish & Richardson P.C.

20070029557 - Light-emitting diode, one of the electrodes of which is a multilayer made of amorphous carbon: Diode comprising a substrate and an organic electroluminescent layer interposed between a lower electrode and an upper electrode, at least one of which electrodes is formed from a multilayer which is itself formed by the stack of adjacent sublayers made of amorphous carbon, having different refractive indices n1, n2. The... Agent: Thomson Licensing Inc.

20070029592 - Oriented bismuth ferrite films grown on silicon and devices formed thereby: A functional perovskite cell formed on a silicon substrate layer and including a functional layer of bismuth ferrite (BiFeO3 or BFO) sandwiched between two electrode layers. An intermediate template layer, for example, of strontium titanate allows the bismuth ferrite layer to be crystallographically aligned with the silicon substrate layer. Other... Agent: Law Offices Of Charles Guenzer

20070029595 - Semiconductor device and manufacturing method therefor: A bottom electrode (52) made of Ir, an initial layer (53), a core layer (54) and a termination layer (55) of a PZT film, and a top electrode (56) made of IrO2, are formed on an underlining film (51). The initial layer (53) is formed in a low oxygen partial... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070029596 - Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same: A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070029597 - High-voltage semiconductor device: Provided is a high-voltage semiconductor device which is constructed such that the quantity of P and N charges are balanced in the entire drift region thereby preventing the degradation of the device breakdown characteristics. The high-voltage semiconductor device comprises an active region including N pillars of N conductivity type and... Agent: Townsend And Townsend And Crew, LLP

20070029598 - Semiconductor device manufacturing method and semiconductor device: A manufacturing method of a semiconductor device having a highly reliable capacitor, and the semiconductor device are provided. The semiconductor device manufacturing method according to the present invention includes: a first step of forming a first electrode of a capacitor on a semiconductor substrate; a second step of forming a... Agent: Mcdermott Will & Emery LLP

20070029599 - Semiconductor device: The semiconductor device, in which a flaking of a layer or an element is prevented, is provided. A bonding pad section 13 of a semiconductor device 1 includes a polysilicon film 131, a barrier metal film 133 provided on the polysilicon film 131 and a metallic electrode 134 provided on... Agent: Young & Thompson

20070029603 - Method of fabricating cell of nonvolatile memory device with floating gate: This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device... Agent: Marger Johnson & Mccollom, P.C.

20070029600 - Nanowire based non-volatile floating-gate memory: A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform size and single-crystal orientation.... Agent: Scully Scott Murphy & Presser, PC

20070029602 - Non-volatile memory device and fabricating method thereof: A non-volatile memory device and fabricating method thereof are provided. In the deposition to form a tunneling dielectric layer, a composite charge trapping layer and a block dielectric layer, an ingredient of a depositing material or the depositing material is adjusted to form a grading energy level structure, such that... Agent: Rabin & Berdo, PC

20070029601 - Sonos memory cell having high-k dielectric: A semiconductor memory device may include an intergate dielectric layer of a high-K dielectric material interposed between a floating gate and a control gate. With this intergate high-K dielectric in place, the memory device may be erased using Fowler-Nordheim tunneling.... Agent: Harrity Snyder, L.L.P.

20070029604 - Using thin undoped teos with bpteos ild or bpteos ild alone to improve charge loss and contact resistance in multi-bit memory devices: The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit... Agent: Eschweiler & Associates, LLC National City Bank Building

20070029606 - Phase change material, phase change random access memory including the same, and methods of manufacturing and operating the same: A phase change material, a PRAM including the same, and methods of manufacturing and operating the same are provided. Insulating impurities may be uniformly distributed over an entire or partial region of the phase change material. The PRAM may include a phase change layer including the phase change material. The... Agent: Harness, Dickey & Pierce, P.L.C

20070029605 - Semiconductor device and a method of manufacturing the same: A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070029607 - Dense arrays and charge storage devices: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.... Agent: Foley And Lardner LLP Suite 500

20070029608 - Offset spacers for cmos transistors: An offset spacer for CMOS transistors and a method of manufacture is provided. A gate electrode is formed on a substrate, and an offset mask layer is formed over the surface of the gate electrode and the substrate. The offset mask may be formed of an oxide layer and acts... Agent: Slater & Matsil, L.L.P.

20070029609 - Array substrate having enhanced aperture ratio, method of manufacturing the same and display device having the same: An array substrate includes a substrate, a thin film transistor, a passivation layer, a pixel electrode and a storage capacitor. The thin film transistor includes a gate electrode formed on the substrate, a gate insulation layer formed on the substrate having the gate electrode, a semiconductor layer formed on the... Agent: F. Chau & Associates, LLC

20070029610 - Non-volatile memory and fabricating method thereof: A non-volatile memory and fabricating method thereof are provided. First, a plurality of raised bit lines is formed on the substrate. The raised bit lines are paralleled one another, and extended in the same direction. Then, a charge trap layer is formed on the substrate. Afterwards, a plurality of word... Agent: Jianq Chyun Intellectual Property Office

20070029613 - Electro-optical device, electronic apparatus, and method of manufacturing electro-optical device: An electro-optical device includes: an electro-optical device substrate; step portions having a concave shape that are formed on a predetermined insulating film of the electro-optical device substrate; side wall portions each of which is formed on a side surface of the concave step portion between the surface of the insulating... Agent: Oliff & Berridge, PLC

20070029611 - Integrated circuit having a top side wafer contact and a method of manufacture therefor: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the... Agent: Texas Instruments Incorporated

20070029612 - Scalable high performance carbon nanotube field effect transistor: A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. The structure employs an asymmetric gate which is closer to the source and farther from the drain, which helps to minimize “off current” drain leakage when the drain is biased and the gate is otherwise... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20070029614 - Semiconductor device with thin-film transistors and method of fabricating the same: A semiconductor device with a TFT includes a substrate, an island-shaped semiconductor film serving as an active layer of the TFT on or over the substrate, a pair of source/drain regions formed in the semiconductor film, and a channel region formed between the pair of source/drain regions in the semiconductor... Agent: Mcginn Intellectual Property Law Group, PLLC

20070029615 - Active matrix substrate and repairing method thereof: An active matrix substrate including a substrate, a plurality of pixel units, a plurality of driving lines, an electron static discharge (ESD) protection circuit and a floating line is provided. The substrate has an active region and a peripheral region connected with the active region. The pixel units are arranged... Agent: Jianq Chyun Intellectual Property Office

20070029616 - Semiconductor integrated circuit device and method of fabricating the same: A semiconductor integrated circuit device and a method of fabricating the same are provided. An embodiment of the semiconductor integrated circuit device includes a substrate having a cell region and a peripheral circuit region. A recess channel transistor may be formed in the cell region and include a source/drain region,... Agent: Marger Johnson & Mccollom, P.C.

20070029617 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: a semiconductor layer provided with a P-channel field-effect transistor and an N-channel field-effect transistor that have a common gate electrode, a field plate provided to a back surface of the semiconductor layer with a first insulating layer therebetween and commonly for a channel of the P-channel... Agent: Edwards & Angell, LLP

20070029618 - Dual-gate device and method: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor... Agent: Macpherson Kwok Chen & Heid LLP

20070029619 - Semiconductor devices having a recessed active edge and methods of fabricating the same: A semiconductor device having a recessed active edge is provided. The semiconductor devices include an isolation layer disposed in a substrate to define an active region. A gate electrode is disposed to cross over the active region. A source region and a drain region are disposed in the active region... Agent: Marger Johnson & Mccollom, P.C.

20070029620 - Low-cost high-performance planar back-gate cmos: A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method... Agent: Scully, Scott, Murphy & Pressner

20070029621 - Semiconductor integrated circuit device: Cell placement areas in which a plurality of standard cells are placed in bands are provided on a semiconductor substrate of a semiconductor integrated circuit device. The cell placement areas have N- and P-wells formed in the cell placement areas, and a deep N-well formed in the substrate underneath the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070029622 - Flash memory device and method of fabricating the same: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral region. A cell array is defined within the cell region, the cell array having first, second, third, and fourth sides. A first decoder is defined within the peripheral region and provided adjacent to the first side... Agent: Townsend And Townsend And Crew, LLP

20070029623 - Dual-gate field effect transistor: A dual-gate field effect transistor includes a substrate 1, a source 7-1, a drain 7-2, a vertical channel 5 provided between the source and the drain as rising from the substrate, a pair of gate insulation films 6-1 and 6-2 sandwiching the channel from a direction orthogonal to a carrier-running... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070029624 - Fin-type field effect transistor: Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070029625 - Non-volatile memory semiconductor device having an oxide-nitride-oxide (ono) top dielectric layer: A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between the source and drain... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070029627 - Reducing the dielectric constant of a portion of a gate dielectric: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.... Agent: Trop Pruner & Hu, PC

20070029626 - Semiconductor device, and method of fabricating the same: A silicon oxynitride film is manufactured using SiH4, N2O and H2 by plasma CVD, and it is applied to the gate insulating film (1004 in FIG. 1A) of a TFT. The characteristics of the silicon oxynitride film are controlled chiefly by changing the flow rates of N2O and H2. A... Agent: Eric Robinson

20070029628 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a gate structure formed on a substrate. The gate structure includes an uppermost first metal silicide layer pattern having a first thickness. Spacers are formed on sidewalls of the gate structure. One or more impurity regions are formed in the substrate adjacent to at least one... Agent: Harness, Dickey & Pierce, P.L.C

20070029629 - Integrated sensor and circuitry and process therefor: A micromachined sensor and a process for fabrication and vertical integration of a sensor and circuitry at wafer-level. The process entails processing a first wafer to incompletely define a sensing structure in a first surface thereof, processing a second wafer to define circuitry on a surface thereof, bonding the first... Agent: Hartman & Hartman, P.C.

20070029630 - Integrated circuits with contemporaneously formed array electrodes and logic interconnects: The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting... Agent: Knobbe Martens Olson & Bear LLP

20070029631 - Package structure and wafer level package method: A wafer level package process includes: providing a device substrate, in which one surface of the device substrate includes a plurality of devices; providing a cap substrate and forming a plurality of cavities on one surface of the cap substrate, in which the location of each cavity is corresponding to... Agent: North America Intellectual Property Corporation

20070029632 - Radiation sensor, waver, sensor module, and method for the production a radiation sensor: A radiation sensor (10) comprises a support (1), a cavity (2) which may be a recess or a through hole formed in one surface of the support (1), a sensor element (4, 4a, 4b) formed above the cavity (2), preferably on a membrane (3) covering the cavity (2), and electric... Agent: Wood, Herron & Evans, LLP

20070029633 - Shottky diode and method for fabricating the same: A Schottky diode includes a first nitride semiconductor layer formed on a substrate and a second nitride semiconductor layer selectively formed on the first nitride semiconductor layer and having a different conductivity type from that of the first nitride semiconductor layer. A Schottky electrode is selectively formed on the first... Agent: Mcdermott Will & Emery LLP

20070029634 - High speed diode: The invention relates to a high-speed diode comprising a semiconductor body (1), in which a heavily n-doped zone (8), a weakly n-doped zone (7) and a weakly p-doped zone (6) are arranged successively in a vertical direction (v), between which a pn load junction (4) is formed. A number of... Agent: Baker Botts, L.L.P.

20070029637 - Image sensor for reduced dark current: A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of the image sensor. In one embodiment, dark current is reduced by providing a deep n-type region having an n-type peripheral sidewall formed in a p-type substrate... Agent: Dickstein Shapiro LLP

20070029636 - Semiconductor device and manufacturing method thereof: The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact... Agent: Rossi, Kimms & Mcdowell LLP.

20070029635 - Semiconductor processing methods, semiconductor constructions, and electronic systems: The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present to a concentration of from about 2% to about 40%, by volume. An... Agent: Wells St. John P.s.

20070029638 - Semiconductor device and methods of protecting a semiconductor device: A semiconductor device and methods for protecting a semiconductor device. In an example, the semiconductor device may include a semiconductor substrate including at least one electrostatic discharge (ESD) protection device, at least one metal interconnection line connected to the at least one ESD protection device through a conductive plug and... Agent: Harness, Dickey & Pierce, P.L.C

20070029639 - Edge intensive antifuse and method for making the same: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070029640 - Iii- v group compound semiconductor device: A field effect transistor (FET) with high withstand voltage and high performance is realized by designing a buffer layer structure appropriately to reduce a leakage current to 1×10−9 A or less when a low voltage is applied. An epitaxial wafer for a field effect transistor comprising a buffer layer 2,... Agent: Mcginn Intellectual Property Law Group, PLLC

20070029641 - Semiconductor device: A seal ring is continuously formed along a boundary between a semiconductor element region and a scribe grid region, auxiliary parts are intermittently arranged along the seal ring, and the seal ring is constituted by a metal layer.... Agent: Steptoe & Johnson LLP

20070029642 - Heating and cooling of substrate support: A substrate support assembly and method for controlling the temperature of a substrate within a process chamber are provided. A substrate support assembly includes an thermally conductive body comprising a stainless steel material, a substrate support surface on the surface of the thermally conductive body and adapted to support a... Agent: Patterson & Sheridan, LLP

20070029643 - Methods for nanoscale structures from optical lithography and subsequent lateral growth: Methods, and structures formed thereby, are disclosed for forming laterally grown structures with nanoscale dimensions from nanoscale arrays which can be patterned from nanoscale lithography. The structures and methods disclosed herein have applications with electronic, photonic, molecular electronic, spintronic, microfluidic or nano-mechanical (NEMS) technologies. The spacing between laterally grown structures... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070029644 - Electro-optical device and electronic apparatus: An electro-optical device includes first switching elements which are correspondingly provided at intersections of a plurality of scanning lines and a plurality of data lines in a display region, at least three metal layers which are provided in the display region, a wiring line portion which is provided in an... Agent: Advantedge Law Group, LLC

20070029645 - High permeability layered films to reduce noise in high speed interconnects: An electronic system includes apparatus having a transmission line circuit with an associated high permeability material. The high permeability material may include a layered structure of a nickel iron compound.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. Attn: Edward J. Brooks, Iii

20070029646 - Inter-chip esd protection structure for high speed and high frequency devices: The present invention relates to inter-chip electrostatic discharge (ESD) protection structures for high speed, and high frequency devices that contain one or more direct, inter-chip signal transmission paths. Specifically, the present invention relates to a structure that contains: (1) a first chip including a first circuit, (2) a second chip... Agent: Scully, Scott, Murphy & Pressner

20070029648 - Enhanced multi-die package: System and method for a thermal and space efficient integrated circuit package. A preferred embodiment comprises a first lead frame with a first surface to which a first die is attached and a second surface external to a multi-die package, a second lead frame with a first surface to which... Agent: Texas Instruments Incorporated

20070029649 - Plastic lead frame with snap-together circuitry: A plastic lead frame with snap-together electrical connectors, electrical component system, and method using plastic-injection, plating, and known photolithography techniques is disclosed. The plastic lead frame and electrical component system operates with an integrated circuit, which functions as a sensor, such as a Hall-Effect sensor. The snap-together connectors allow interference... Agent: Kris T. Fredrick Honeywell International Inc.

20070029647 - Radio frequency over-molded leadframe package: An over-molded leadframe (e.g., a Quad Flat No-lead (QFN)) package capable of operating at frequencies in the range of about five gigahertz (GHz) to about 300 GHz and a method of making the QFN package are disclosed. The QFN package includes a capacitance lead configured to substantially reduce and/or offset... Agent: Snell & Wilmer

20070029651 - Semiconductor device: A rectify element as a semiconductor device has a disk section, a first solder part, a buffer plate, a second solder part, a semiconductor chip, and a lead, and a sealing member with which the semiconductor chip is sealed. A cylindrical concave part is formed at one end surface of... Agent: Oliff & Berridge, PLC

20070029650 - Semiconductor package and package stacking structure and method using the same: A semiconductor package presents Z-shaped outer leads. The outer leads have a first portion located near an upper surface of a package body, a second portion, and a third portion located near a lower surface of a package body. A second similar semiconductor package may be stacked on the first... Agent: Marger Johnson & Mccollom, P.C.

20070029652 - Semiconductor device and method of manufacturing the same: A semiconductor device including: a semiconductor substrate having an electrode; a resin protrusion formed on a surface of the semiconductor substrate on which the electrode is formed, the resin protrusion extending along a straight line and having a sloping region of which a height decreases along the straight line as... Agent: Oliff & Berridge, PLC

20070029653 - Application of autonomic self healing composites to integrated circuit packaging: A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.... Agent: Blakely Sokoloff Taylor & Zafman

20070029654 - Electronic parts packaging structure and method of manufacturing the same: In an electronic parts packaging structure of the present invention, an electronic parts is mounted or formed on a silicon circuit substrate having a structure in which wiring layers on both sides thereof are connected to each other through a through electrode, and a protruded bonding portion which is ring-shaped... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070029655 - Jig structure for manufacturin a stacked memory card: A jig structure for manufacturing a stacked memory card, wherein the stacked memory card has a substrate forming with a package area and at least a electrical element, the jig structure is formed with a penetrated slot corresponding to the mounted area of the substrate and at least a protection... Agent: Pro-techtor International Services

20070029656 - Semiconductor device: Electronic parts 12, 13 and a terminal 14 are provided on a substrate 11, an upper surface 18A of a terminal main body portion 18 is set higher than surfaces 12A, 13A of the electronic parts 12, 13, a sealing resin is provided to expose the upper surface 18A of... Agent: Rankin, Hill, Porter & Clark LLP

20070029658 - Electrical connection pattern in an electronic panel: A connector layout for arranging a plurality of parallel electrical connectors between two electronic devices. In one device, each connector has a strip connected to a bump pad. The bump pad is superimposed on and electrically connected to a bump pad on the other device. Each strip has a certain... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070029657 - Semiconductor pressure sensor: A semiconductor pressure sensor can reduce the damage of bonding wires to increase their life time even under an environment in which the temperature and pressure change rapidly and radically. The semiconductor pressure sensor includes a package (1) made of a resin and having a concave portion (1a), a lead... Agent: Sughrue Mion, PLLC

20070029659 - Mems rf switch module including a vertical via: An apparatus and method to provide a micro-electromechanical systems (MEMS) radio frequency (RF) switch module with a vertical via. The MEMS RF switch module includes a MEMS die coupled to a cap section. The vertical via passes through the cap section to electrically couple an RF switch array of the... Agent: Blakely Sokoloff Taylor & Zafman

20070029660 - Stack package implementing conductive support: A stack package may have a plurality of unit packages. Each unit package may include a first substrate, a semiconductor chip, and a second substrate. Conductive supports may stack the second substrate on the first substrate. Conductive bumps may be provided on the bottom surface of the first substrate. An... Agent: Harness, Dickey & Pierce, P.L.C

20070029661 - Power plane design and jumper wire bond for voltage drop minimization: According to one embodiment of the invention, a power system for a die comprises a plurality of supply voltage lines, a plurality of ground lines, a plurality of metallized rails, and a via. Each of the plurality of supply voltage lines are in communication with at least one supply voltage... Agent: Texas Instruments Incorporated

20070029662 - Semiconductor device having termination circuit line: A semiconductor device may have a plurality of dielectric layers and at least one termination circuit line between the dielectric layers. The termination circuit lines may be formed over the active surface of a semiconductor substrate.... Agent: Harness, Dickey & Pierce, P.L.C

20070029663 - Multilayered circuit substrate and semiconductor package structure using the same: A multilayered circuit substrate and a semiconductor package using the multilayered circuit substrate are provided to increase the number of bonding pads arranged on the circuit substrate without reducing the pitch of the bonding pads, and to further increase the routing feasibility of high speed signals by the use of... Agent: Marger Johnson & Mccollom, P.C.

20070029664 - Integrated circuit package and method of assembling the same: Flexible, adhesive materials are used to secure integrated circuit package components together. The die is secured to the heat sink, the ringframe to the heat sink and the leadframe to the ringframe, using epoxy materials that flex over the operational temperature range of the circuit package. The flexibility of the... Agent: Koppel, Patrick & Heybl

20070029665 - Method for the mitigation of hot spots in integrated circuits chip: The invention relates to a method and apparatus for controlling the temperature of integrated circuit chips. Specifically, the invention relates to method and apparatus for controlling the temperature gradient across integrated circuit chips.... Agent: Delphi Technologies, Inc.

20070029666 - Chip-sized flip-chip semiconductor package and method for making the same: A semiconductor package (10; 14) comprises a semiconductor die (2; 2′) with a plurality of contact areas (4) on its active surface and an electrically conductive bump (7) on each contact area (4). The die (2; 2′) and electrically conductive bumps (7) are encapsulated in a plastic housing (11) so... Agent: Baker Botts, L.L.P.

20070029668 - Package module having a stacking platform: The package module comprising a first substrate, a first package, a second package and a molding compound. The first substrate has a first surface. The first package comprises a first chip and a liquid encapsulating compound. The first chip is disposed on the first substrate and electrically connected to the... Agent: Birch Stewart Kolasch & Birch

20070029667 - Semiconductor device: A wiring substrate 11 having a power feeding layer 24 and a ground conductive layer 27 is provided, and also an inverted F-type antenna 20 is provided on a sealing resin 17, which covers a semiconductor chip 12 and a chip parts 13 connected to the wiring substrate 11, and... Agent: Rankin, Hill, Porter & Clark LLP

20070029669 - Integrated circuit with low-stress under-bump metallurgy: An integrated circuit (IC) includes a semiconductor material, electronic circuitry formed on the semiconductor material, a contact layer formed on the electronic circuitry, a final passivation layer formed on the contact layer and an under-bump metallurgy (UBM) formed on at least a portion of the final passivation layer. The contact... Agent: Delphi Technologies, Inc.

20070029671 - Semiconductor device: A semiconductor device includes a semiconductor substrate having an electrode and a conductive pad; a resin projection formed on the semiconductor substrate; and a wiring electrically connected to the electrode, the wiring having a first portion formed on the electrode, a second portion formed on the conductive pad and a... Agent: Oliff & Berridge, PLC

20070029672 - Semiconductor device: A semiconductor device including: a semiconductor substrate on which a plurality of electrodes are formed; a plurality of resin protrusions formed on the semiconductor substrate, arranged along a straight line, and extending in a direction which intersects the straight line; and a plurality of electrical connection sections formed on the... Agent: Harness, Dickey & Pierce, P.L.C

20070029673 - Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument: A semiconductor device includes a semiconductor substrate in which an integrated circuit is formed and which includes interconnects and electrodes, the interconnects electrically connected with the semiconductor substrate, and the electrodes being formed on the interconnects; a resin layer formed on the semiconductor substrate; redistribution interconnects electrically connected with the... Agent: Oliff & Berridge, PLC

20070029670 - Semiconductor device and radiation detector employing it: A wiring substrate 20, comprising a glass substrate, formed by integrally bundling a plurality of glass fibers and provided with through holes 20c, and conductive members 21, disposed at through holes 20c, is used. Input portions 21a of conductive members 21, formed on an input surface 20a of this wiring... Agent: Drinker Biddle & Reath (dc)

20070029674 - Board-on-chip package and stack package using the same: Provided is a board-on-chip package and stack package using the same to reduce the likelihood that bonding wires in an encapsulant may be damaged due to mechanical stresses applied during a package stacking process. A semiconductor package may have a spacer provided along the opposing sides of an encapsulant. The... Agent: Marger Johnson & Mccollom, P.C.

20070029675 - Integral charge storage basement and wideband embedded decoupling structure for integrated circuit: A capacitive structure and technique for allowing near-instantaneous charge transport and reliable, wide-band RF ground paths in integrated circuit devices such as integrated circuit dies, integrated circuit packages, printed circuit boards, and electronic circuit substrates is presented. Methods for introducing resistive loss, dielectric loss, magnetic loss, and/or radiation loss in... Agent: The Law Office Of Jessica Costa, PC

20070029676 - Semiconductor device and method for manufacturing the same: A resistor element formed of a peel-preventive film, a recording layer made of chalcogenide, and an upper electrode film is formed on a semiconductor substrate, first and second insulation films are formed so as to cover the resistor element, a via hole for exposing the upper electrode film is formed... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070029677 - Interconnection structure: An interconnection structure includes a lower interconnection layer formed on a substrate and composed of a copper layer, an interlayer insulating layer formed on the lower interconnection layer and having a via reaching the lower interconnection layer, an upper interconnection layer electrically connected to the lower interconnection layer through the... Agent: Mcdermott Will & Emery LLP

20070029678 - Lead-free solder: According to one embodiment of the invention, there is provided a lead-free solder including an alloy rolled into a shape of sheet. The alloy includes: tin; from 10 wt % to less than 25 wt % of silver; and from 3 wt % to 5 wt % of copper. The... Agent: Young & Thompson

20070029679 - Electrical component having a reduced substrate area: An electrical component having reduced substrate area is suggested, in which a substrate (S) having component structures (BS), on one surface of which solder metal platings (LA), which are electrically connected to the component structures, are positioned, is electrically and mechanically connected in a flip chip arrangement to a carrier... Agent: Fish & Richardson PC

20070029680 - Chip packaging structure without leadframe: A chip packaging structure without leadframe includes a bare chip having one surface provided with a plurality of contacts, and an adhesive and a fixing layer sequentially attached to the surface of the bare chip with the contacts, and a plurality of lead wires sandwiched between the adhesive and the... Agent: Rosenberg, Klein & Lee

20070029681 - Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component mounted to a substrate. The substrate carries a plurality of bond pads at a location substantially coplanar with a terminal surface of... Agent: Perkins Coie LLP Patent-sea

20070029682 - Epoxy resin composition and semiconductor device: An epoxy resin composition is provided comprising (A) an epoxy resin, (B) a phenolic resin curing agent, (C) an inorganic filler, (D) a cure accelerator, (E) an adhesion promoter, and (F) a metal oxide. The metal oxide (F) is a combination of a magnesium/aluminum ion exchanger, a hydrotalcite ion exchanger,... Agent: Birch Stewart Kolasch & Birch

20070029683 - Method for fabricating semiconductor package with heat sink: A semiconductor package with a heat sink and a method for fabricating the same are proposed. The heat sink is provided with a rigid and thermally resistant detach member on a top surface thereof, and is attached via its bottom surface to a chip mounted on a chip carrier. The... Agent: Edwards & Angell, LLP

20070029684 - Wafer dividing method: A method of dividing a wafer having a plurality of areas, which are sectioned by the streets formed on the front surface in a lattice pattern and a plurality of devices, which are formed in the sectioned areas, along streets, the method comprising a first cutting step for holding the... Agent: Smith, Gambrell & Russell

20070023743 - Phase-change tan resistor based triple-state/multi-state read only memory: The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN... Agent: Scully, Scott, Murphy & Pressner

20070023744 - Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.... Agent: Dickstein Shapiro LLP

20070023745 - Strained channel transistor and method of fabricating the same: A strained channel transistor according to the present invention includes a semiconductor substrate, a semiconductor layer having a lattice constant larger than the lattice constant of the semiconductor substrate on the semiconductor substrate, a strained channel layer on the semiconductor layer, and one or more epitaxial layers on sides of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070023748 - 6,13-bis(thienyl)pentacene compounds: 6,13-bis(thienyl)pentacene compounds are described that can be used as a semiconductor material. Semiconductor devices that contain the 6,13-bis(thienyl)pentacene compounds and methods of making such semiconductor devices are also described.... Agent: 3m Innovative Properties Company

20070023746 - Encapsulation layer for electronic devices: An encapsulation, barrier, or protective layer for electronic devices is disclosed comprising a lac-based material, its synthetic form and variant, or a combination thereof, which protects electronic devices from adverse environmental effects.... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070023749 - Organic thin film transistor: The present invention relates to an organic thin film transistor which includes an organic layer comprising an organic compound facilitating the ohmic contact between a semi-conducting layer and electrodes and serving as the semi-conducting layer. The organic thin film transistor according to the present invention has excellent electric contact between... Agent: Mckenna Long & Aldridge LLP

20070023747 - Positive charging photoreceptor: An imaging member includes a substrate, a charge transport layer, a charge generator layer, and a charge transporting or photoconductive overcoating layer.... Agent: Oliff & Berridge, PLC.

20070023750 - Semiconductor device: A semiconductor device can include a channel including a zinc-indium oxide film.... Agent: Hewlett-packard Company Intellectual Property Administration

20070023753 - Fabricating method for a liquid crystal display of horizontal electric field applying type: A liquid crystal display having an applied horizontal electric field comprising: a gate line; a common line substantially parallel to the gate line; a data line arranged to cross the gate line and the common line to define a pixel area; a thin film transistor formed at each crossing of... Agent: Mckenna Long & Aldridge LLP

20070023754 - High aperture lcd with insulating color filters overlapping bus lines on active substrate: A high aperture active matrix liquid crystal display (AMLCD) includes pixel electrodes in respective pixels which overlap adjacent address lines. The color filters are formed on the active substrate in a manner such that the filters also overlap the address lines and function as an insulating layer between the pixel... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070023751 - Thin film device, thin film device module, and method of forming thin film device module: A thin film device includes a thin film element disposed on a surface of a substrate for high voltage formed of a material having an electric resistivity in the range of 108Ω·cm to 1010Ω·cm, with an adhesive layer in between. The substrate for high voltage is a sintered body containing... Agent: Oliff & Berridge, PLC

20070023752 - Transistor array panel, liquid crystal display panel, and method of manufacturing liquid crystal display panel: A transistor array panel includes switching elements provided in intersecting portions between gate and data lines, and display electrodes connected to the switching elements. A conductive film pattern is provided to be electrically insulated from the gate and data lines, and display electrodes, and to be overlapped on the display... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070023755 - Programming optical device: A semiconductor light emitting device and a method to form the same are disclosed. The device has at least one porous or low density dielectric region formed in or on top of a bottom electrode, at least one top electrode on the porous or low density dielectric region, and one... Agent: Howard Chen Preston Gates & Ellis LLP

20070023756 - Virtual body-contacted trigate: A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070023758 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of... Agent: Eric Robinson

20070023757 - Thin-film transistor, method for manufacturing thin-film transistor, and display using thin-film transistor: The present invention provides a thin-film transistor having a higher mobility for electrons or holes, a method for manufacturing the thin-film transistor, and a display using the thin-film transistor. Thus, the present invention provides a thin-film transistor having a source region, a channel region, and a drain region in a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070023759 - Thin film transistor, circuit apparatus and liquid crystal display: A thin film transistor includes a one conductive type semiconductor layer (11); a source region (12) and a drain region (13) which are separately provided in the semiconductor layer; and a gate electrode (14) provided above or below the semiconductor layer with an insulating film interposed therebetween, wherein the width... Agent: Stoel Rives LLP

20070023760 - Thin film transistor substrate: A thin film transistor substrate including a thin film transistor having a drain electrode with an electrode portion, which overlaps with a semiconductor layer, and an extended portion, which extends from the electrode portion and has a portion overlapping with a storage electrode or storage electrode line. A passivation layer... Agent: H.c. Park & Associates, PLC

20070023761 - Silicon carbon germanium (sicge) substrate for a group iii nitride-based device: A substrate for an electronic device formed in a group III nitride material system comprises a layer of silicon carbon and a layer of silicon carbon germanium over the layer of silicon carbon, the layer of silicon carbon and the layer of silicon carbon germanium forming a substrate for a... Agent: Avago Technologies, Ltd.

20070023763 - Semiconductor light-emitting device and method for fabricating the same: A semiconductor light-emitting device includes a light-emitting layer and a light extraction layer formed on the light-emitting layer and made of a resin material containing particles. The maximum size of each of the particles contained in the light extraction layer is smaller than the wavelength of emitted light penetrating through... Agent: Mcdermott Will & Emery LLP

20070023762 - White light emitting led-powered lamp: The invention relates to a white light emitting LED lamp. The LED lamp comprises an LED emitting blue light and luminescent layer for converting a part of the blue light into light having a longer wavelength. According to the invention either a dye is provided for absorbing a part of... Agent: Jlb Consulting, Inc. C/o Intellevate

20070023764 - Cmos image sensor and method of fabricating the same: A CMOS image sensor and a method of fabricating the same are provided. In the CMOS image sensor, a device isolation layer is formed in a substrate to define an active region, and a photodiode is formed in the active region. A floating diffusion region is formed at a position... Agent: Morgan Lewis & Bockius LLP

20070023765 - Acicular ito for led array: In an array of LEDs coupled between a transparent substrate and an electrode, a light emitting surface of each LED is in electrical contact with a region of acicular ITO. By contacting the light emitting surface of the die, the acicular ITO also provides light scattering. The contact regions are... Agent: Paul F. Wille Cantor Colburn LLP

20070023766 - Feed through structure for optical semiconductor package: Includes a stem with a hole, a dielectric sealed into the hole of the stem and including a pair of pin insertion holes, and a pair of high frequency signal pins that penetrate and fit into the pair of pin insertion holes of the dielectric, and constituting differential lines connected... Agent: Buchanan, Ingersoll & Rooney PC

20070023767 - Semiconductor apparatus having conductive layers and semiconductor thin films: A semiconductor apparatus includes a substrate; m electrically conductive layers formed on the substrate, m being an integer of 2 or more, potentials of the m electrically conductive layers being capable of being independently controlled; and semiconductor thin films having at least one semiconductor device respectively. The semiconductor thin films... Agent: Rabin & Berdo, PC

20070023768 - Semiconductor light emitting element: A semiconductor light emitting element has a first conductive-type cladding layer, an undoped active layer, a second conductive-type cladding layer, and a second conductive-type current spreading layer that are formed on a first conductive-type semiconductor substrate. The second conductive-type cladding layer has a first dopant suppressing layer formed at a... Agent: Mcginn Intellectual Property Law Group, PLLC

20070023769 - Led lighting source and led lighting apparatus: An LED lighting source preventing heat deterioration and improving luminous efficiency includes a mounting substrate having a wiring pattern on a first main surface thereof and a plurality of LED bare chips, each composed of a first semiconductor layer and a second semiconductor layer having respectively different conductivity, an active... Agent: Snell & Wilmer L.L.P.

20070023770 - Optical semiconductor device and method for manufacturing the same: An optical semiconductor device includes a first light receiving region and a second light receiving region provided on a substrate and the first and second light receiving regions include light receiving elements, respectively. A first anti-reflection film is formed in the first light receiving region of the substrate and a... Agent: Mcdermott Will & Emery LLP

20070023771 - Led and fabrication method thereof: A light emitting diode is provided. The diode includes: a substrate; a first nitride gallium layer disposed above the substrate; a first electrode provided at one portion of and above the first nitride gallium layer; an active layer provided above the first nitride gallium layer, for emitting light; a second... Agent: Birch Stewart Kolasch & Birch

20070023772 - Semiconductor light-emitting device and method of manufacturing same: A semiconductor light-emitting device has a first conductivity type semiconductor layer (3, 4), a luminous layer (5) formed on the first conductivity type semiconductor layer, a second conductivity type semiconductor layer (8) formed on the luminous layer, and a transmissive substrate (9) which is formed on the second conductivity type... Agent: Morrison & Foerster LLP

20070023773 - Semiconductor light-emitting device: A first cladding layer of a first conductivity type formed above a crystal substrate, an active layer formed above the first cladding layer, a diffusion prevention layer formed on the active layer and preventing an impurity from diffusing into the active layer, an overflow prevention layer of a second conductivity... Agent: Banner & Witcoff, Ltd., Attorneys For Reserve Attorneys For Client No. 000449, 001701

20070023774 - Optoelectronic chip: An optoelectronic chip having a semiconductor body (14), which contains a radiation-emitting region (2), and a partial region (3) in which the surface (13) of the semiconductor body (14) is curved convexly toward a carrier (10). The lateral extent (2r) of the radiation-emitting region (2) is less than the lateral... Agent: Cohen, Pontani, Lieberman & Pavene LLP

20070023776 - Light emitting diode package: A light emitting diode package is provided. The light emitting diode package comprises a submount substrate which includes a mounting region having side walls inclined upwardly, first and second cavities formed around the mounting region, and first and second grooves extending between the mounting region and the first and second... Agent: Mcdermott Will & Emery LLP

20070023775 - Nitride-based compound semiconductor light emitting device and method of fabricating the same: A nitride-based semiconductor light emitting device with improved characteristics of ohmic contact to an n-electrode and a method of fabricating the same are provided. The nitride-based semiconductor light emitting device includes an n-electrode, a p-electrode, an n-type compound semiconductor layer, and an active layer and a p-type compound semiconductor layer... Agent: Buchanan, Ingersoll & Rooney PC

20070023777 - Semiconductor element: It is an object of the present invention to provide a highly reliable and high-quality semiconductor element by effectively preventing the migration of silver to a nitride semiconductor when an electrode main entirely or mostly of silver having high reflection efficiency is formed in contact with a nitride semiconductor layer.... Agent: Birch Stewart Kolasch & Birch

20070023778 - Integrated circuit with multi-length power transistor segments: A monolithic integrated circuit fabricated on a semiconductor die includes a control circuit and a first output transistor having segments substantially equal to a first length. A second output transistor has segments substantially equal to a second length. The first and second output transistors occupy an L-shaped area of the... Agent: Burgess & Bereznak LLP

20070023779 - Semiconductor device: A semiconductor device includes a field effect transistor and a pn junction diode formed on a substrate. The field effect transistor has a source electrode, a drain electrode and a gate electrode formed on an element forming layer including a plurality of nitride semiconductor layers. The diode includes a p-type... Agent: Mcdermott Will & Emery LLP

20070023780 - Semiconductor device and method of manufacturing the same: A gate insulating film is formed using a plasma on a three-dimensional silicon substrate surface having a plurality of crystal orientations. The plasma gate insulating film experiences no increase in interface state in any crystal orientations as compared with tat in Si (100) crystal orientation and has a uniform thickness... Agent: Foley And Lardner LLP Suite 500

20070023781 - Semiconductor rectifier: A semiconductor rectifier has a semiconductor layer formed on a substrate, an electric field reduced layer of conductive type contrary to that of the semiconductor layer, which is formed on the semiconductor layer positioned on a bottom portion of a trench formed on a portion of the semiconductor layer, a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070023782 - Semiconductor device: A semiconductor device includes a surface layer on the side of a first principal surface of a p-semiconductor substrate, a high side n-isolation-diffused region and a low side n-isolation-diffused region formed apart from each other by a distance that is shorter than the diffusion length of electrons in the p-semiconductor... Agent: Rossi, Kimms & Mcdowell LLP.

20070023783 - Semiconductor device: A semiconductor device includes an emitter layer: a base layer; and a collector layer, wherein the collector layer and the emitter layer each include a heavily doped thin sublayer having a high impurity concentration, and each of the heavily doped thin sublayers has an impurity concentration higher than those of... Agent: Sonnenschein Nath & Rosenthal LLP

20070023784 - Method for fabricating a memory cell arrangement with a folded bit line arrangement and corresponding memory cell arrangement with a folded bit line arrangement: A memory cell arrangement, which has a size of 8F2 per memory cell, wherein F is a unit of length, comprises a plurality of active regions along a first direction in a semiconductor substrate, a plurality of parallel buried word lines along a second direction in the semiconductor substrate, a... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070023785 - Method for driving solid-state imaging apparatus and solid-state imaging apparatus: A driving method is applied to a solid-state imaging apparatus having photoelectric conversion portions, transfer portion for reading out signal charges, and an excess charge draining portion for draining charges exceeding a saturation charge amount that is set by a reference voltage. One of driving modes is selected from a... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070023786 - Cmos imager with wide dynamic range pixel: In one aspect of the present invention, a light sensor is provided in the active pixel sensor cell for sensing incident radiation. The voltage corresponding to the photon-generated or other radiation-generated charge in the active pixel sensor cell is stored on a storage node via a sample-and-hold capacitor. Additional elements,... Agent: Macpherson Kwok Chen & Heid LLP

20070023787 - Drive unit for charge coupled devices and driving method for charge coupled devices: A drive unit for a charge coupled device, which includes a plurality of transfer electrodes arranged to intersect a transfer direction of information charge, and stores and transfers information electric charge using potential wells formed in a semiconductor substrate by voltages applied to the transfer electrodes. As at least one... Agent: Cantor Colburn, LLP

20070023788 - Solid-state image pickup device, method of driving solid-state image pickup device and imaging apparatus: There is provided a solid-state image pickup device including: a pixel array portion which includes a plurality of unit pixels each having a photoelectric conversion element and an output transistor for outputting a signal according to charge obtained by photoelectric conversion of the photoelectric conversion element; a comparing portion which... Agent: Sonnenschein Nath & Rosenthal LLP Sears Tower

20070023789 - multiport single transistor bit cell: A multiport memory cell (200, 300, 600) includes a first word line (WL1) coupled to a gate electrode of a first transistor (201, 301, 601). A second word line (WL2) is coupled to a gate electrode of a second transistor (202, 302, 602). Importantly, the memory cell (200, 300, 600)... Agent: Freescale Semiconductor, Inc.

20070023790 - Manufacturing method of semiconductor device: The invention provides a technique to manufacture a highly reliable semiconductor device and a display device at high yield. As an exposure mask, an exposure mask provided with a diffraction grating pattern or an auxiliary pattern formed of a semi-transmissive film with a light intensity reducing function is used. With... Agent: Fish & Richardson P.C.

20070023791 - Method of fabricating gate of fin type transistor: A method of fabricating a gate of a fin type transistor includes forming hard masks to define active regions of a substrate. A shallow trench isolation method is performed to form a first device separation layer, and then an etch-back process is performed such that the active regions protrude. Sidewall... Agent: Marger Johnson & Mccollom, P.C.

20070023795 - Semiconductor device and method of fabricating the same: A semiconductor device includes a metal oxide semiconductor (MOS) transistor including two source/drain regions located at a surface layer side of the semiconductor substrate, a stress-inducing film formed so as to cover the source/drain region of the MOS transistor, the stress-inducing film applying stress to a channel region formed between... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070023794 - Stacked semiconductor device and related method: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the... Agent: Volentine Francos, & Whitt PLLC

20070023792 - Transistor and transistor manufacturing method: In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D′ of the gate electrode 114 is set larger than a uniform... Agent: Nixon & Vanderhye, PC

20070023793 - Trench-gate semiconductor device and manufacturing method of trench-gate semiconductor device: Disclosed is a trench-gate semiconductor device including: a trench gate structure; a source layer having a first conductivity type, facing a gate electrode via a gate insulating film, and having a top plane; a base layer having a second conductivity type, being adjacent to the source layer, and facing the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070023796 - Pinning layer for pixel sensor cell and method thereof: A novel pixel sensor cell structure and method of manufacture. The pixel sensor cell includes a collection well region of a first conductivity type and a pinning layer formed in a substrate. The pinning layer includes a first impurity region of a second conductivity type and a second impurity region... Agent: Ibm Microelectronics Intellectual Property Law

20070023797 - Complementary metal oxide semiconductor image sensor layout structure: A complementary metal oxide semiconductor (CMOS) image sensor layout structure is described. The CMOS image sensor layout structure includes a substrate, a plurality of light sensing devices, a plurality of transistors and a plurality of color-filtering film layers. The substrate has a pixel array region comprising a plurality of pixels.... Agent: Jianq Chyun Intellectual Property Office

20070023798 - Dual conversion gain gate and capacitor combination: A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion gain element having a control gate switches in the capacitance of the capacitor to change the conversion gain of the... Agent: Dickstein Shapiro LLP

20070023802 - Cmos image sensor and method of fabricating the same: In a CMOS image sensor and method of fabricating the same, the CMOS image sensor is comprised of a pixel array generating image signals and a peripheral circuit processing the image signals. In the method, a substrate is provided having a pixel region and a peripheral circuit region. A photo-receiving... Agent: Mills & Onello LLP

20070023803 - Cmos image sensor and method of fabricating the same: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes a photodiode region and a transistor region that have a first concentration and are formed on an active region of a first conductive type semiconductor substrate. Additionally, the CMOS image sensor includes... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070023804 - Double pinned photodiode for cmos aps and method of formation: A pinned photodiode, which is a double pinned photodiode having increased electron capacitance, and a method for forming the same are disclosed. The invention provides a pinned photodiode structure comprising a substrate base over which is a first layer of semiconductor material. There is a base layer of a first... Agent: Dickstein Shapiro LLP

20070023800 - Semiconductor imaging device and fabrication process thereof: A semiconductor imaging device includes a photodetection region formed of a diffusion region of a first conductivity type formed in an active region of a silicon substrate at a first side of a gate electrode such that a top part thereof is separated from a surface of the silicon substrate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070023801 - Stacked pixel for high resolution cmos image sensor: Provided is a solid-state CMOS image sensor, specifically a CMOS image sensor pixel that has stacked photo-sites, high sensitivity, and low dark current. In an image sensor including an array of pixels, each pixel includes: a standard photo-sensing and charge storage region formed in a first region under a surface... Agent: Morgan Lewis & Bockius LLP

20070023799 - Structure and method for building a light tunnel for use with imaging devices: A pixel cell and imager device, and method of forming the same, where the pixel cell has a plurality of metallization and via layers formed over a photosensitive region. The metallization and via layers form a step-like light tunnel structure that augments the photosensitive region's ability to capture light impinging... Agent: Dickstein Shapiro LLP

20070023807 - Magnetic memory: In a magnetic memory 1, a magneto-resistivity effect element 4 is disposed adjacently to a wire 5 for producing a writing magnetic field and further a ferromagnetic body 20 is disposed so as to cover at least part of the wire 5 and consequently orient the state X of magnetization... Agent: Mathews, Shepherd, Mckay, & Bruneau, P.A.

20070023806 - Method and structure for forming slot via bitline for mram devices: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via... Agent: Cantor Colburn LLP-ibm Yorktown

20070023805 - Reverse construction memory cell: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a... Agent: Knobbe Martens Olson & Bear LLP

20070023810 - Capacitor, semiconductor device having the same, and method of manufacturing the semiconductor device: A semiconductor device with a stack type capacitor having a lower electrode formed of an aluminum-doped metal, and a manufacturing method thereof are provided. The semiconductor device includes: a semiconductor substrate having a gate structure and an active region; an interlayer dielectric film formed on the active region; a lower... Agent: Buchanan, Ingersoll & Rooney PC

20070023809 - Memory cell comprising one mos transistor with an isolated body having an improved read sensitivity: A memory cell with one MOS transistor formed in a floating body region isolated on its lower surface by a junction. A region of the same conductivity type as the floating body region but more heavily doped than said region is arranged under the drain region of the MOS transistor.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070023808 - Semiconductor memory, the fabrication thereof and a method for operating the semiconductor memory: A semiconductor memory having a multitude of memory cells (21-1), the semiconductor memory having a substrate (1), at least one wordline (5-1), a first (15-1) and a second line (15-2; 16-1), wherein each of the multitude of memory cells (21-1) comprises a first doping region (6) disposed in the substrate... Agent: Slater & Matsil LLP

20070023811 - Vertical p-n junction device and method of forming same: A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction device results in a raised... Agent: Hoffman, Warnick & D'alessandro LLC

20070023812 - Highly integrated and reliable dram and its manufacture: A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070023813 - Semiconductor device having upper electrode and method of fabricating the same: An embodiment of the semiconductor device includes a semiconductor substrate having at least one cell region and a peripheral circuit region. An interlayer insulating layer is disposed on the semiconductor substrate. Storage node electrodes are disposed on the interlayer insulating layer of the cell region. An upper electrode is disposed... Agent: Marger Johnson & Mccollom, P.C.

20070023815 - Non-volatile memory device and associated method of manufacture: A non-volatile memory device comprises a floating gate formed across an active region of a semiconductor substrate, and a control gate electrode formed over the floating gate. An insulation pattern is formed between the floating gate and the active region such that the insulation pattern makes contact with a bottom... Agent: Volentine Francos, & Whitt PLLC

20070023814 - Nonvolatile memory semiconductor device and method for manufacturing same: A nonvolatile memory semiconductor device and a method for manufacturing thereof are provided to avoid deterioration of the tunnel insulating film to increase frequency of writing data on the nonvolatile memory semiconductor device and erasing thereof. Concentration of atomic nitrogen in a tunnel insulating film 151 of a nonvolatile memory... Agent: Sughrue Mion, PLLC

20070023816 - Eeprom flash memory device with jagged edge floating gate: An EEPROM flash memory device having a floating gate electrode enabling a reduced erase voltage and method for forming the same, the floating gate electrode including an outer edge portion comprising multiple charge transfer pointed tips.... Agent: Tung & Associates Suite 120

20070023818 - Flash memory and method for manufacturing thereof: The invention is directed to a flash memory comprising a first source/drain region, a second source/drain region, a first floating gate, a second floating gate, a lightly doped region and a control gate. The first source/drain region and the second source/drain region are located in the substrate and apart from... Agent: J C Patents, Inc.

20070023820 - Non-volatile memory device and methods of forming and operating the same: In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection... Agent: Mills & Onello LLP

20070023819 - Semiconductor device: A semiconductor device includes: a silicon substrate, having a main surface, in which trenches are formed; element isolation oxide films filling in trenches; a tunnel oxide film, formed on main surface located between element isolation oxide film and element isolation oxide film, having birds beak portions in birds beak forms... Agent: Mcdermott Will & Emery LLP

20070023821 - Semiconductor device and method of manufacturing the same: In a semiconductor device and a method of manufacturing the semiconductor device, preliminary isolation regions having protruded upper portions are formed on a substrate to define an active region. After an insulation layer is formed on the active region, a first conductive layer is formed on the insulation layer. The... Agent: Mills & Onello LLP

20070023817 - Structure and manufacturing method of multi-gate dielectric thicknesses for planar double gate device having multi-threshold voltages: Double gate transistors (12, 13) having different bottom gate dielectric thicknesses are formed on a first wafer (101) by forming a first gate dielectric layer (107); removing part of the first gate dielectric layer (107) from a first area (60); forming a second gate dielectric layer (108) to obtain a... Agent: Hamilton & Terrile, LLP

20070023822 - Programmable non-volatile memory (pnvm) device: A programmable non-volatile memory (PNVM) device and method of forming the same compatible with CMOS logic device processes to improve a process flow, the PNVM device including a semiconductor substrate active area; a gate dielectric on the active area; a floating gate electrode on the gate dielectric; an inter-gate dielectric... Agent: Tung & Associates

20070023823 - Nonvolatile semiconductor memory device and related method: A nonvolatile memory device and a method for fabricating the nonvolatile memory device are disclosed. The method comprises forming a device isolation pattern comprising a first opening and a second opening wider than the first opening, wherein the first opening is formed in the second opening; and forming a gate... Agent: Volentine Francos, & Whitt PLLC

20070023824 - Semiconductor memory device and manufacturing method for semiconductor memory device: The object is simplification of a manufacturing process for nonvolatile memory by reducing additional processes for forming a charge storage structure, and downsizing of nonvolatile memory. The solution is a manufacturing method for semiconductor memory device including a process for forming sequentially a first oxide film 102, a first nitride... Agent: Rabin & Berdo, PC

20070023825 - Semiconductor device: A semiconductor device having: a semiconductor layer; an interlayer dielectric formed on the semiconductor layer; a buffer layer formed on the interlayer dielectric; and an electrode pad formed on the interlayer dielectric, the buffer layer being formed to be covered by an edge portion of at least part of the... Agent: Harness, Dickey & Pierce, P.L.C

20070023826 - Vertical-type metal insulator semiconductor field effect transistor device, and production method for manufacturing such transistor device: In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070023828 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a semiconductor substrate having a gate trench formed therein. A gate electrode is formed on a gate insulator in the gate trench. The gate electrode has ends close to the bottom of the gate trench, which are separated in a direction perpendicular to both sides of... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070023827 - Semiconductor structure with improved on resistance and breakdown voltage performance: In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spaced apart filled trenches bounding... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070023829 - Split electrode gate trench power device: A power semiconductor device which includes gate liners extending along gate insulation liners and an insulation block spacing the two gate liners.... Agent: Ostrolenk Faber Gerb & Soffen

20070023830 - Semiconductor component with a low on-state resistance: A semiconductor component having a semiconductor body is disclosed. In one embodiment, the semiconductor component includes a drift zone of a first conductivity type, a drift control zone composed of a semiconductor material which is arranged adjacent to the drift zone at least in places, a dielectric which is arranged... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070023831 - Field effect transistor and application device thereof: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4.... Agent: Hogan & Hartson L.L.P.

20070023832 - Semiconductor device and method of fabricating the same: In view of micronizing semiconductor device and of suppressing current leakage in a shared contact allowing contact between a gate electrode and an impurity-diffused region, a semiconductor device 100 includes a first gate electrode 108, a fourth source/drain region 114b, and a shared contact electrically connecting the both, wherein in... Agent: Young & Thompson

20070023835 - Asymmetry thin-film transistor: An asymmetry thin-film transistor includes a substrate, a semiconductor layer positioned on the substrate, and a gate positioned on the substrate. The semiconductor layer has a channel region, a single lightly doped region and a first heavily doped region positioned at a side of the channel region, and a second... Agent: North America Intellectual Property Corporation

20070023833 - Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same: An integrated circuit device (for example, logic or discrete memory device) including a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region... Agent: Neil A. Steinberg

20070023834 - Method of measuring a surface voltage of an insulating layer: In a method of measuring a surface voltage of an insulating layer, the number of times that surface voltages are measured in a depletion region increases so that precise data about the depletion region may be obtained. The number of times that the surface voltages are measured in an accumulation... Agent: Marger Johnson & Mccollom, P.C.

20070023836 - Semiconductor device: The present invention provides an MOSFET having a semiconductor substrate, an insulating layer provided on the semiconductor substrate, and an SOI layer provided on the insulating layer. A source region and a drain region are provided in the SOI layer. A non-doped region is provided at a position interposed between... Agent: Rabin & Berdo, PC

20070023837 - Thin film transistor substrate and method of making the same: The present invention relates to a thin film transistor substrate comprising: an insulating substrate; a source electrode and a drain electrode which are formed on the insulating substrate and separated from each other and have a channel area therebetween; a wall exposing at least portions of the source electrode and... Agent: Macpherson Kwok Chen & Heid LLP

20070023838 - Fabricating logic and memory elements using multiple gate layers: Various embodiments are directed to different methods and systems relating to design and implementation of memory cells such as, for example, static random access memory (SRAM) cells. In one embodiment, a memory cell may include a first layer of conductive material and a second layer of conductive material. The first... Agent: Beyer Weaver & Thomas, LLP

20070023839 - Finfet gate formed of carbon nanotubes: A fin field effect transistor (FinFET) gate comprises a semiconductor wafer; a gate dielectric layer over the semiconductor wafer; a conductive material on the gate dielectric layer; an activated carbon nanotube on a surface of the conductive material; and a plated metal layer on the activated carbon nanotube. Preferably, the... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070023840 - Dose rate event protection clamping circuit: A novel system for protecting one or more circuits during a dose rate event is presented. A clamping circuit is utilized that outputs a voltage signal that may be used to control prevent circuits from receiving input signals during a dose rate event. The clamping circuit comprises a photocurrent generating... Agent: Honeywell International Inc.

20070023841 - Transistor and method for forming the same: Disclosed are a transistor and a method for forming the same. The present transistor comprises: a groove formed in a semiconductor substrate; a couple of first sidewall spacers formed in inner sidewalls of the groove, protruding over the substrate; a gate electrode formed between the first sidewall spacers; a gate... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070023843 - Semiconductor device and a method of manufacturing the same: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070023842 - Semiconductor devices having different gate dielectric layers and methods of manufacturing the same: A first transistor includes a first channel region of a first conductivity type located at a first surface region of a semiconductor substrate, a first gate dielectric which includes a first HfO2 layer located over the first channel region, and a first gate located over the first gate dielectric. The... Agent: Volentine Francos, & Whitt PLLC

20070023844 - Semiconductor device: Provided is a method capable of forming a polycrystalline silicon resistor with preferable ratio accuracy so as to design a resistor circuit with high accuracy. In the method, a length of a low concentration impurity region constituting the polycrystalline silicon resistor in a longitudinal direction is varied in accordance with... Agent: Brinks Hofer Gilson & Lione

20070023845 - Semiconductor device and method for fabricating the same: A semiconductor device including an n-channel MISFET including source/drain regions 38 formed in a semiconductor substrate 10 with a channel region between them, and a gate electrode 44 of a metal silicide formed over the channel region with a gate insulating film 12 interposed therebetween; and an insulating film 46... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070023846 - Transistor: In a first aspect, there is provided a field effect transistor comprising a gate having a modified shape having sharply defined geometric patterns or indents of a dimension that creates de Broglie wave interference. According to a second aspect of the present invention, there is provided a spin transistor comprising... Agent: Borealis Technical Limited

20070023847 - Semiconductor device and method of manufacturing the same: A semiconductor device and method of manufacturing the semiconductor device are provided. The semiconductor device may include a semiconductor substrate, a gate insulation layer and a gate electrode, a first spacer, a second spacer, an epitaxial pattern, and/or source/drain regions. The gate insulation layer and the gate electrode may be... Agent: Harness, Dickey & Pierce, P.L.C

20070023848 - Protruding spacers for self-aligned contacts: A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the... Agent: Mendelsohn & Associates, P.C.

20070023849 - Method for forming a fully germano-silicided gate mosfet and devices obtained thereof: A MOSFET comprising a fully germano-silicided gate electrode having a high work function is disclosed. This gate electrode is formed by a self-aligned reaction process between a silicidation metal and a semiconductor material comprising silicon and germanium. Preferably, the fully germano-silicided gate is formed by a reaction between nickel and... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070023850 - Bonding surfaces together via plasma treatment on both surfaces with wet treatment on only one surface: A first surface is bonded to a second surface. The first surface and the second surface are plasma treated. Only the first surface is wet treated. The first surface and the second surface are joined together to bond the first surface to the second surface.... Agent: Hewlett Packard Company

20070023851 - Mems pixel sensor: A MEMS pixel sensor is provided with a thin-film mechanical device having a mechanical body, with a mechanical state responsive to a proximate environment. A thin-film electronic device converts the mechanical state into electrical signals. A pixel interface supplies power to the electronic device and transceives electrical signals. The sensor... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070023852 - Solid-state image sensing device producing method and solid-state image sensing device: A method of producing a solid-state image sensing device comprising a photoelectric conversion layer, the method comprising: laminating a first epitaxial layer on a semiconductor substrate; forming a part of the photoelectric conversion layer in the first epitaxial layer; forming a second epitaxial layer by epitaxial growth on the first... Agent: Birch Stewart Kolasch & Birch

20070023853 - Megavoltage imaging with a photoconductor based sensor: A photodetector for detecting megavoltage (MV) radiation comprises a semiconductor conversion layer having a first surface and a second surface disposed opposite the first surface, a first electrode coupled to the first surface, a second electrode coupled to the second surface, and a low density substrate including a detector array... Agent: Varian/blakely

20070023854 - Cmos image sensors including pickup regions and methods of fabricating the same: A CMOS image sensor includes a field isolation film defining first, second, and third active fields in a substrate having a first conductivity type, a photodiode region in the first active field, the photodiode region having a second conductivity type opposite the first conductivity type, and a floating diffusion region... Agent: Myers Bigel Sibley & Sajovec

20070023855 - Semiconductor structure with improved on resistance and breakdown voltage performance: In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spaced apart filled trenches having... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070023856 - Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.... Agent: Wells St. John P.s.

20070023858 - Device isolation structure of a semiconductor device and method of forming the same: Disclosed are an isolation structure and a method for forming the same. The present isolation structure includes a substrate having a first semiconductor layer having a first lattice parameter, a second semiconductor layer having a second lattice parameter larger than the first lattice parameter, and a strained semiconductor layer; a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070023857 - Fabricating sub-lithographic contacts: A small critical dimension element, such as a heater for an ovonic unified memory, may be formed within a pore by using successive sidewall spacers. The use of at least two successive spacers enables the limitations imposed by lithography and the limitations imposed by bread loafing to be overcome to... Agent: Trop Pruner & Hu, PC

20070023859 - Contact fuse which does not touch a metal layer: The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms... Agent: Texas Instruments Incorporated

20070023861 - Fuse structure window: The present invention provides a fuse structure. The fuse structure comprises a substrate, a plurality of conductive layers, a plurality of dielectric layers and a plurality of conductive plugs. The novel fuse structure includes a plurality of fuse units, and a new layout of the fuse units to increase the... Agent: Robert Popa C/o Ladas & Parry

20070023860 - Semiconductor device having a fuse barrier pattern and fabrication method thereof: In a semiconductor device having a plurality of fuses and a method of fabricating the same, the semiconductor device comprises an inter-layer dielectric layer on a semiconductor substrate; a plurality of fuses on the inter-layer dielectric layer, an inter-metallic dielectric layer on the plurality of fuses and the inter-layer dielectric... Agent: Mills & Onello LLP

20070023862 - Semiconductor device and oscillator: A semiconductor device includes a semiconductor substrate including an active element or an integrated circuit and a plurality of connection electrodes to be electrically connected to the integrated circuit; a first resin layer formed on a surface of the semiconductor substrate on which the connection electrodes are formed in such... Agent: Oliff & Berridge, PLC

20070023863 - Thin film resistor and method of making the same: One embodiment of an integrated circuit includes a substrate and a SiWNi thin film resistor formed on the substrate.... Agent: Joe Pugh, Triquint Semiconductor

20070023865 - Integrated transistor, particularly for voltages and method for the production thereof: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from... Agent: Brinks Hofer Gilson & Lione

20070023864 - Methods of fabricating bipolar transistor for improved isolation, passivation and critical dimension control: A first (e.g. replaceable or disposable) dielectric spacer formed on a sidewall of a dummy emitter mandrel is removed after a raised extrinsic base layer and covering dielectric layer are formed. Thereafter, a second dielectric spacer is formed within the opening that results. As a result, the second dielectric spacer,... Agent: International Business Machines Corporation Dept. 18g

20070023866 - Vertical silicon controlled rectifier electro-static discharge protection device in bi-cmos technology: A vertical silicon controlled rectifier (SCR) that directs an electro-static discharge (ESD) current directly to ground from the input/output pad. The vertical SCR is includes a vertical NPN and a vertical PNP that creates a very good SCR exhibiting very low ohmic on-resistance. The vertical SCR provides a low on-resistance... Agent: Hoffman, Warnick & D'alessandro LLC

20070023867 - Film taking-off method: The invention relates to a method of producing a film intended for applications in electronics, optics or optronics starting from an initial wafer, which includes a step of implanting atomic species through one of the faces of the wafer. This method includes forming a step of defined height around the... Agent: Winston & Strawn LLP Patent Department

20070023868 - Method of forming copper metal line and semiconductor device including the same: A semiconductor device includes a substrate having a bottom metal line formed therein; a nitride layer and an oxide layer having a trench and a via hole, the via hole exposing the bottom metal line; a barrier metal layer formed inside the trench and the via hole; a seed layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070023869 - Vapor phase deposition apparatus and vapor phase deposition method: A vapor phase deposition apparatus includes a chamber, a support table disposed in the chamber and adapted to support a substrate in the chamber, a first passage connected to the chamber and adapted to supply gas to the chamber to form a film on the substrate, and a second passage... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070023870 - Low-k interlevel dielectric materials and method of forming low-k interlevel dielectric layers and structures: A composition of matter and a structure fabricated using the composition. The composition comprising: a resin; polymeric nano-particles dispersed in the resin, each of the polymeric nano-particle comprising a multi-arm core polymer and pendent polymers attached to the multi-arm core polymer, the multi-arm core polymer immiscible with the resin and... Agent: Schmeiser, Olsen & Watts

20070023872 - Chip package with asymmetric molding: A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is... Agent: J.c. Patents, Inc. Suite 250

20070023874 - Metallic laminate and method of manufacturing the same: Disclosed herein are a metallic laminate, including (i) a metal layer and (ii) a polyimide resin layer having a coefficient of thermal expansion of 19 ppm/° C. or less and a glass transition temperature of 350° C. or more, laminated on the metal layer, and a method of manufacturing the... Agent: Mckenna Long & Aldridge LLP

20070023873 - Package structure having recession portion on the surface thereof and method of making the same: The present invention relates to a method for making a package structure having recession portion on the surface thereof. The method comprises: (a) providing a lead frame having a plurality of package units, each package unit having a plurality of leads and a die paddle; (b) providing an upper mold... Agent: Volentine Francos, & Whitt PLLC

20070023875 - Semiconductor package and manufacturing method thereof: A semiconductor package includes a lead frame having an element mounting part and a lead part. A first semiconductor element and a second semiconductor element are sequentially stacked on a principal surface at least on one side of the element mounting part. An insulating resin layer serving as a second... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070023871 - Semiconductor package based on lead-on-chip architecture, the fabrication thereof and a leadframe for implementing in a semiconductor package: A leadframe includes a multiplicity of leads. The leads have a board level contact portion, an intermediate portion and a chip level contact portion. The intermediate portion is disposed between the board level contact portion and the chip level contact portion. The board level contact portions extend from one of... Agent: Slater & Matsil LLP

20070023876 - Tab tape carrier: To provide a TAB tape carrier that can provide improved adhesion of a conductive pattern to an insulating base layer, while strengthening a connection between gold terminals of a semiconductor device and connection terminals covered with a tin plating layer, and can prevent the conductive pattern from sinking into the... Agent: Akerman Senterfitt

20070023877 - Chip on flex tape with dimension retention pattern: To provide a chip on flex (COF) tape having an improved precision of cumulative pitches while retaining bending properties. [Means to Solve the Problems] A chip on flex (COF) tape having a wiring pattern comprising a plurality of wirings arranged in parallel formed on the surface of a flexible insulating... Agent: 3m Innovative Properties Company

20070023878 - Ic with on-die power-gating circuit: In some embodiments a semiconductor device is described that includes, on a single die, both a functional circuit and a power-gating circuit. The power-gating circuit may be used to control the power delivered to core circuit elements on the semiconductor device. The power may be provided to and possibly from... Agent: RyderIPLaw C/o Intellevate

20070023882 - Balance filter packaging chip having balun mounted therein and manufacturing method thereof: A balance filter packaging chip having a balun mounted therein and a manufacturing method thereof are provided. The balance filter packaging chip includes a device substrate; a balance filter mounted on the device substrate; a bonding layer stacked on a certain area of the device substrate; a packaging substrate having... Agent: Sughrue Mion, PLLC

20070023880 - Packaged integrated circuit with enhanced thermal dissipation: A semiconductor package (10) uses a plurality of thermal conductors (56-64) that extend upward within an encapsulant (16) from one or more thermal bond pads (22, 24, 26) on a die (14) to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend... Agent: Freescale Semiconductor, Inc. Law Department

20070023883 - Semiconductor stack block comprising semiconductor chips and methods for producing the same: A semiconductor stack block contains either stacked semiconductor chip size semiconductor devices or semiconductor devices with semiconductor chips in a plastic housing composition, the semiconductor chips and the plastic housing composition having a coplanar area. Arranged on the active top side of the semiconductor chips and the plastic housing composition... Agent: Edell, Shapiro & Finnan, LLC

20070023881 - Semiconductor wafer with a wiring structure, a semiconductor component, and methods for their production: A semiconductor wafer is provided with a wiring structure, and semiconductor chip positions arranged in rows and columns. The semiconductor wafer has at least one coating (6) as a self-supporting dimensionally stable substrate layer (4), and/or as a wiring structure composed of conductive, high-temperature-resistant material. The coating material (6) of... Agent: Baker Botts, L.L.P.

20070023879 - Single unit heat sink, voltage regulator, and package solution for an integrated circuit: A method, apparatus, and system with a subassembly for simple integration of high power integrated electronics, the subassembly including an integrated circuit package, an integrated circuit package cooling device and a printed circuit board with coupled power delivery components.... Agent: Blakely Sokoloff Taylor & Zafman

20070023885 - Ic card and method of manufacturing the same: The productivity of an IC card is to be improved. In a memory card of the type in which a memory body having a wiring substrate and a semiconductor chip mounted on a main surface of the wiring substrate is held so as to be sandwiched in between a first... Agent: Miles & Stockbridge PC

20070023884 - Package: The invention relates to a package, e.g. a blister package, comprising two spaced apart first and second walls formed and joined to each other to define a cavity between them, said walls having peripheral edges and being sealed together at a peripheral joint essentially along the edges wherein a portion... Agent: Greer, Burns & Crain

20070023886 - Method for producing a chip arrangement, a chip arrangement and a multichip device: The present invention relates to a method and apparatus for producing a chip arrangement. In one embodiment, the method includes providing a first chip having an electrically operable structure, of providing at least one through-via through the first chip, and of arranging at least one bond wire through the through-via... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070023887 - Multi-chip semiconductor package featuring wiring chip incorporated therein, and method for manufacturing such multi-chip semiconductor package: In a multi-chip semiconductor package, a rectangular wiring die has a wiring pattern layer, and respective four sides of the wiring die is dimensionally identical to those of a first rectangular semiconductor die. The wiring die is mounted on the first semiconductor die so that the respective sides of the... Agent: Young & Thompson

20070023889 - Copper substrate with feedthroughs and interconnection circuits: A method for fabricating a copper-based circuit module is described. The module is built on a copper sheet and has isolated feedthroughs fabricated using a glass frit. High density interconnection circuits are built on the copper sheet, including wells for accepting bumped devices such as integrated circuit chips. The modules... Agent: Edward N. Bachand Dorsey & Whitney LLP

20070023888 - Semiconductor device and manufacturing method thereof: A semiconductor chip 11 comprising an element formation layer 36 which is formed on a first main surface 35A of a semiconductor substrate 35 and has a semiconductor element, through electrodes 15, 16 which are electrically connected to the semiconductor element and extend through the semiconductor chip 11, and a... Agent: Rankin, Hill, Porter & Clark LLP

20070023890 - Microelectronic device: One embodiment of a microelectronic component system includes a base adapted for supporting a microelectronic component, a membrane sealed to the base, and a glass lid built-up on the membrane and hermetically sealing the membrane.... Agent: Hewlett Packard Company

20070023891 - Substrate based ic-package: A semiconductor component comprises a substrate that includes wiring on a first surface. A chip is mounted on a second surface of the substrate by a die attach, the second surface opposite the first surface. A bond channel in the center of the substrate allows for electrical connection of contact... Agent: Slater & Matsil LLP

20070023892 - Method and apparatus for electrical isolation of semiconductor device: A package includes a thermal solution to thermal couple to a semiconductor device to remove heat generated by the semiconductor device, and a device to electrically isolate at least a portion of the thermal solution from the semiconductor device. The package also includes a biasing device to apply a voltage... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070023893 - Led package structure and manufacturing method, and led array module: An LED package includes a substrate having an electrically conductive portion and an electrically non-conductive portion composed of an oxide of the conductive portion; an LED mounted on the conductive portion and electrically connected to the conductive portion; a first electrode disposed on the non-conductive portion and electrically connected to... Agent: Sughrue Mion, PLLC

20070023894 - Integrated circuit cooling system and method: A system and method for cooling an integrated circuit is provided. One aspect of this disclosure relates to a cooling system that utilizes sound waves to cool a semiconductor structure. The system includes a container to hold at least one semiconductor chip having surfaces to be in contact with a... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070023895 - Semiconductor device having capacitors for reducing power source noise: A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconductor chip being electrically connected to the BGA substrate by... Agent: Mcdermott Will & Emery LLP

20070023896 - Semiconductor device for radio frequencies of more than 10 ghz and method for producing the device: A semiconductor device for radio frequencies of more than 10 GHz having a semiconductor chip is disclosed. In one embodiment, the semiconductor chip, on its active top side, having a radio-frequency region and a low-frequency region and/or a region which is supplied with DC voltage. In one embodiment, the low-frequency... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070023897 - Semiconductor device, power amplifier device and pc card: The present invention is directed to improve high frequency characteristics by reducing inductance of a source. In an HEMT assembled in a power amplifier device, each of a drain electrode, a source electrode, and a gate electrode is constructed by a base portion and a plurality of fingers projected in... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070023900 - Bonding pad fabrication method, method for fabricating a bonding pad and an electronic device, and electronic device: A method for fabricating a bonding pad 45 includes disposing a droplet L including a liquid containing a conductive material on a substrate P by a droplet ejection method and solidifying the disposed droplet L to forms the pad. The bonding pad 45 formed has a cylindrical shape and includes... Agent: Harness, Dickey & Pierce, P.L.C

20070023898 - Integrated circuit chip and integrated device: Embodiments provide for integrated circuit chip and device having such an integrated circuit, in which different types of pads are arranged in separate rows. In one embodiment the pads are intelligently arranged to reduce the loop inductance of corresponding signal and power supply bond wires.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070023899 - Wiring substrate, electro-optic device, electric apparatus, method of manufacturing wiring substrate, method of manufacturing electro-optic device, and method of manufacturing electric apparatus: A wiring substrate includes a substrate, a first film, and a second film formed between the substrate and the first film, and an empty space is formed between at least a part of the second film and the substrate.... Agent: Oliff & Berridge, PLC

20070023901 - Microelectronic bond pad: One embodiment of an integrated circuit includes a substrate, an electrical device positioned above the substrate, and a bond bad positioned above and aligned along a vertical axis with the electrical device such that the electrical device is positioned between the substrate and the bond pad.... Agent: Joe Pugh, Triquint Semiconductor, Inc.

20070023904 - Electro-optic interconnection apparatus and method: A construction for attaching an optical fiber to an electro-optic chip is described. The construction includes support for the optical fiber, optionally provided by an aperture in a supporting copper sheet. High density interconnection circuits are fabricated on the copper sheet. Pillar-in-well connections are used between the electro-optic chip and... Agent: Edward N. Bachand Dorsey & Whitney LLP

20070023905 - Semiconducting device with folded interposer: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070023903 - Semiconductor device, electronic module, and method of manufacturing electronic module: A semiconductor device including: a semiconductor chip having an electrode; a plurality of resin protrusions formed on a surface of the semiconductor chip on which the electrode is formed, heights of the resin protrusions increasing as a distance from a center of the surface of the semiconductor chip increases; and... Agent: Oliff & Berridge, PLC

20070023906 - Semiconductor device-composing substrate and semiconductor device: A semiconductor device-composing substrate 10 has a support base 12, an interconnect layer 14 including interconnects 13, and an insulating resin layer 16. The semiconductor device-composing substrate 10 also has a mounting region D1 on which a semiconductor chip 30 is to be mounted. The insulating resin layer 16 is... Agent: Mcginn Intellectual Property Law Group, PLLC

20070023902 - Semiconductor package with ferrite shielding structure: A semiconductor device comprises at the wafer level one or more ferrite structures adapted to dampen high frequency noise potentially apparent at signal lines and termination points within the semiconductor device. Related methods of forming said ferrite structures are also disclosed.... Agent: Volentine Francos, & Whitt PLLC

20070023910 - Dual bga alloy structure for improved board-level reliability performance: A method of improving the performance of a ball grid array package under temperature cycling and drop tests is disclosed. The method comprises forming a ball grid array with two types of solder balls. The first type of ball has a composition that improves performance under temperature cycling and the... Agent: Texas Instruments Incorporated

20070023908 - Method of fabricating self-assembled electrical interconnections: A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite... Agent: Patent Documentation Center

20070023907 - Self-assembled interconnection particles: A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite... Agent: Patent Documentation Center

20070023909 - System including self-assembled interconnections: A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite... Agent: Patent Documentation Center

20070023911 - Electronic device and method for manufacturing the electronic device: A method for manufacturing an electronic device in which a bonding pad composed of a foundation layer and a surface layer is formed on an Si layer or an Si-base insulation layer, comprises: forming, on the Si layer or Si-base insulation layer and by a droplet discharging method, the foundation... Agent: Harness, Dickey & Pierce, P.L.C

20070023912 - Integrating metal with ultra low-k-dielectrics: In forming a layer of a semiconductor wafer, a dielectric layer is deposited on the semiconductor wafer. The dielectric layer includes material having a low dielectric constant. Recessed and non-recessed areas are formed in the dielectric layer. A metal layer is deposited on the dielectric layer to fill the recessed... Agent: Morrison & Foerster LLP

20070023914 - Electromigration resistant metallurgy device and method: Devices and methods are described including a conducting pathway with improved electromigration properties. The conducting pathway can be used in integrated circuits and semiconductor chips for devices such as semiconductor memory, or information handling systems. Conducting pathways are provided that eliminate electromigration problems without reducing conductivity in the conductive pathway.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070023913 - Enhanced via structure for organic module performance: A circuit board comprises a resin-filled plated (RFP) through-hole; a dielectric layer over the RFP through-hole; a substantially circular RFP cap in the dielectric layer and connected to an upper opening of the RFP through-hole; a via stack in the dielectric layer; and a plurality of via lands extending radially... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070023915 - On-chip test circuit for assessing chip integrity: A semiconductor chip includes an active inner circuit; a die seal ring surrounding the active inner circuit; a first circuit structure fabricated at a first corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the first circuit structure has a first... Agent: North America Intellectual Property Corporation

20070023916 - Semiconductor structure with multiple bottom anti-reflective coating layer and method of forming photoresist pattern and pattern of semiconductor device using the same structure: The semiconductor structure includes an etch target layer to be pattemed, a multiple bottom anti-reflective coating (BARC) layer, and a photoresist (PR) pattern. The multiple BARC layer includes a first mask layer formed on the etch target layer and containing carbon, and a second mask layer formed on the first... Agent: Volentine Francos, & Whitt PLLC

20070023917 - Semiconductor device having multilayer wiring lines and manufacturing method thereof: A plurality of wiring layers made from a conductive material are formed in the same level layer on a substrate. A plurality of cavity layers are formed in the same level layer as the plurality of wiring layers. The plurality of cavity layers have a cavity ratio which is not... Agent: Foley And Lardner LLP Suite 500

20070023919 - Bonding pad on ic substrate and method for making the same: A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer.... Agent: North America Intellectual Property Corporation

20070023918 - Technique for forming a copper-based contact layer without a terminal metal: By directly forming an underbump metallization layer on a copper-based contact region, the formation of any other terminal metals, such as aluminum and corresponding adhesion/barrier layers may be avoided. Consequently, the thermal and electrical behavior of the resulting bump structure may be improved, while process complexity may significantly be reduced.... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070023923 - Flip chip interface including a mixed array of heat bumps and signal bumps: A flip chip interface is described between a semiconductor chip and a substrate having interconnection circuits. Flip chip bumps are provided at the active face of the chip; each bump is preferably a flexible copper pillar fabricated on a pad, and terminating at the substrate in a well filled with... Agent: Edward N. Bachand Dorsey & Whitney LLP

20070023920 - Flip chip package with reduced thermal stress: A flip-chip package includes a packaging substrate; an integrated circuit die affixed to the packaging substrate, wherein the integrated circuit die includes an active integrated circuit surrounded by a peripheral die seal ring therein; and a thermal stress releasing pad disposed in a stress-releasing area that is at a corner... Agent: North America Intellectual Property Corporation

20070023924 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device having a semiconductor chip mounted over a substrate, in which an interconnect is formed, by using an adhesive layer to permit contact conduction between a stud bump of the semiconductor chip and an interconnect of a tape substrate, wherein an adhesive layer formed integral as... Agent: Miles & Stockbridge PC

20070023922 - Semiconductor package: A semiconductor package includes a circuit board having connection pads formed on a front and back surfaces, and a wiring network connected to these connection pads, as a package base. Metal bumps connected to at least part of the connection pads on the front and back surfaces via the wiring... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070023921 - Structures and methods for an application of a flexible bridge: One embodiment of the present invention provides a system that facilitates high-bandwidth communication using a flexible bridge. This system includes a chip with an active face upon which active circuitry and signal pads reside, and a second component with a surface upon which active circuitry and/or signal pads reside. A... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070023925 - Semiconductor element with conductive bumps and fabrication method thereof: A semiconductor device and a fabrication method thereof are provided. A first passivation layer and a second passivation layer are applied on a semiconductor substrate having at least one bond pad, with the bond pad being exposed. A first metallic layer is formed on the second passivation layer and electrically... Agent: Edwards & Angell, LLP

20070023926 - Planar bond pad design and method of making the same: Techniques for an integrated circuit device with planar bond pads are provided. A metal layer region is formed on a substrate. The integrated circuit device also includes a passivation layer that has an opening formed around the metal layer region. The passivation layer and a top surface of the metal... Agent: Townsend And Townsend And Crew, LLP

20070023927 - Semiconductor device: When an interlayer film (22) is formed to have a large thickness and an electrode pad (11) is partly or wholly led out from an active region (16), an I/O region (15) can be reduced in area. Thus, it is possible to reduce an area of a semiconductor device.... Agent: Steptoe & Johnson LLP

20070023928 - Technique for efficiently patterning an underbump metallization layer using a dry etch process: By patterning the underbump metallization layer stack on the basis of a dry etch process, significant advantages may be achieved compared to conventional techniques involving a highly complex wet chemical etch process. In particular embodiments, a titanium tungsten layer or any other appropriate last layer of an underbump metallization layer... Agent: Williams, Morgan & Amerson

20070023929 - Laminate structure: The invention relates to a laminate structure comprising a first active layer having a first electrode potential, a second active layer having a second electrode potential, wherein the second electrode potential being different from the first electrode potential and wherein the first and second active layers are arranged at a... Agent: Greer, Burns & Crain

20070023930 - High speed interface design: The embodiments of the present invention are directed toward the design of routing patterns, including elements such as contacts, traces, and vias, for high speed differential signal pairs in integrated circuit package substrates.... Agent: Lsi Logic Corporation

20070023931 - Carrier tape for electronic components: A carrier tape for electrical components is provided comprising a tape having a length and a plurality of cavities along the length of the tape. Each cavity comprises inner side walls and a bottom surface and is capable of containing an electrical component.... Agent: Edell, Shapiro & Finnan, LLC

20070023932 - Wafer, reticle, and exposure method using the wafer and reticle: A semiconductor wafer is disclosed that includes a substrate; a plurality of device chip areas formed on the substrate; a plurality of scribe lines formed in a lattice-like manner on the substrate, the scribe lines being provided so as to separate the device chip areas from each other; a blank... Agent: Cooper & Dunham, LLP