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Active solid-state devices (e.g., transistors, solid-state diodes) January USPTO class patent listing 01/07

20070018148 - Phase change memory with u-shaped chalcogenide cell: A phase change memory may be made of a chalcogenide material having a U-shape. The U-shaped chalcogenide may transition between amorphous and crystalline phases in an upper part of a vertical portion thereof. As a result, in some embodiments, self-heating may be achieved without the need for a heater, and... Agent: Trop Pruner & Hu, PC

20070018149 - Semiconductor device and method of producing the same: In a semiconductor device, a phase change layer is formed as a side wall and is therefore reduced in volume. Even if the number of times of rewriting is small, the phase change layer is entirely used as a phase change region. Therefore, the phase change region is not increased... Agent: Young & Thompson

20070018150 - Self-emission panel and method of manufacturing same: A self-emission panel and a method of manufacturing a self-emission panel which can prevent emission failures from occurring due to various factors, thereby achieving a self-emission panel that is free from emission failures. The self-emission panel is manufactured by forming a first conductive layer on a substrate directly or via... Agent: Arent Fox PLLC

20070018156 - Dual panel type organic electroluminescent device: An organic electroluminescent device includes first and second substrates facing each other and spaced apart from each other, each of the first and second substrates having a first region and a second region in a periphery of the first region; an array element on an inner surface of the first... Agent: Mckenna Long & Aldridge LLP

20070018154 - Imidazole derivatives and organic electronic device using the same: Disclosed herein are novel imidazole derivatives and organic electronic device using the same. The disclosed organic electronic device show excellent characteristics in terms of efficiency, driving voltage and stability.... Agent: Mckenna Long & Aldridge LLP

20070018155 - New imidazole derivatives, preparation method thereof and organic electronic device using the same: The present invention relates to a new imidazole derivative, a method for preparing the derivative, and an organic electronic device using the derivative. The imidazole derivative according to the invention can perform functions of hole injection, hole transportation, electron injection, electron transportation, and/or light emission in an organic electronic device... Agent: Mckenna Long & Aldridge LLP

20070018152 - Organic electroluminescent device, manufacturing method therefor, and electronic devices therewith: A method for manufacturing an organic EL device in accordance with the invention includes: coating a composition including an organic EL material on a plurality of electrodes to form an organic EL layer on each electrode; defining an effectively optical area in which the plurality of electrodes are formed; and... Agent: Oliff & Berridge, PLC

20070018151 - Short-channel transistors: An electronic switching device comprising a source electrode, a drain electrode, an insulating layer in the region between source and drain electrode, a semiconducting layer in contact with both the source and the drain electrode, and in contact with said insulating layer, wherein the smallest distance between said source and... Agent: Sughrue Mion, PLLC

20070018153 - Thick light emitting polymers to enhance oled efficiency and lifetime: The light emitting polymer layer of an organic light emitting diode (“OLED”) device is formed to be thick having a thickness of more than 80 nanometers and preferably between 80 and 200 nanometers.... Agent: Fish & Richardson P.C.

20070018157 - Methods of forming phase change storage cells for memory devices: Storage cells for a phase change memory device and phase change memory devices are provided that include a first phase change material pattern and a first high-resist phase change material pattern on the first phase change material pattern. The first high-resist phase change material pattern has a higher resistance than... Agent: Myers Bigel Sibley & Sajovec

20070018158 - Apparatus for separating metal coating film and method for separating metal coating film: A metal coating removing apparatus (1) includes a first electrode (13) arranged so as to be opposed to a metal coating (101) as an object to be removed, a second electrode 14 arranged so as to be opposed to the metal coating (101) at a predetermined distance from the first... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070018159 - Array substrate and display device having the same: An array substrate includes a base substrate, a plurality of pixel electrodes, a plurality of first conductive lines, a plurality of second conductive lines and a plurality of semiconductor patterns. The pixel electrodes are disposed on the base substrate. The first conductive lines are disposed between the pixel electrodes. The... Agent: F. Chau & Associates, LLC

20070018160 - Display for displaying product-specific information on display screen: When an ID number is “123”, TFTs (those corresponding to the position of “1”, those corresponding to the position of “2” and those corresponding to the position of “3”) are set to have a lower current drive capability than remaining TFTs. In an ID display mode, driving of TFTs is... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070018165 - Electro-optical device and method for manufacturing the same: An electro-optical device and a method for manufacturing the same are disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer having sandwiched therebetween, said pair of substrates consisting of a first substrate having provided thereon a plurality of gate wires, a... Agent: Eric Robinson

20070018163 - Semiconductor device: A semiconductor device can include a channel including a zinc-indium oxide film.... Agent: Hewlett-packard Company Intellectual Property Administration

20070018164 - Semiconductor device and manufacturing method thereof: A method of realizing an active matrix display device having flexibility is provided. Further, a method for reducing parasitic capacitance between wirings formed on different layers is provided. After fixing a second substrate to a thin film device formed on a first substrate by bonding, the first substrate is removed,... Agent: Fish & Richardson P.C.

20070018162 - Thin film transistor substrate and manufacturing method thereof: Embodiments of the invention provide a thin film transistor substrate, comprising: an insulating substrate; a gate wire formed on the insulating substrate; a first gate insulating layer made of an inorganic material, formed on the gate wire and having a first insulating layer contact hole for exposing at least a... Agent: Macpherson Kwok Chen & Heid LLP

20070018161 - Thin film transistor substrate and method for fabricating the same: A thin film transistor substrate includes an insulating substrate, a gate electrode formed on the insulating substrate, a first gate insulating film formed on the gate electrode and having an opening for exposing at least part of the gate electrode, a second gate insulating film covering the gate electrode exposed... Agent: Cantor Colburn, LLP

20070018166 - Stacked transistors and process: A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsulated in an insulating layer, such as silicon dioxide. One or more openings are formed... Agent: Robert A. Parsons

20070018167 - Semiconductor integrated circuit and method of fabricating same: A semiconductor integrated circuit comprising thin-film transistors in each of which the second wiring is prevented from breaking at steps. A silicon nitride film is formed on gate electrodes and on gate wiring extending from the gate electrodes. Substantially triangular regions are formed out of an insulator over side surfaces... Agent: Eric Robinson

20070018169 - Liquid crystal display device and fabrication method thereof: A liquid crystal display device and its fabrication method may prevent occurrence of light leakage generated from the sides of a data line. A dummy pattern at sides of the data line with glass powder as an insulation film may simplify the repairing process. A method for fabricating a liquid... Agent: Brinks Hofer Gilson & Lione

20070018170 - Organic light emitting display device: An organic light emitting display device including a flexible substrate and a plurality of thin film transistors (TFTs) formed on the substrate. The plurality of TFTs formed on the substrate include a pixel transistor for driving a pixel and a driver circuit transistor for driving a driver circuit, and a... Agent: Christie, Parker & Hale, LLP

20070018168 - Thin film transistor substrate, display device, and method of fabricating the same: A thin film transistor (“TFT”) substrate includes a gate line formed on a base substrate, a data line insulated from the gate line, and a TFT formed at the intersection between the gate line and the data line. A line width of the gate line is greater than a line... Agent: Cantor Colburn, LLP

20070018171 - Semiconductor device and a method for production thereof: A semiconductor device comprises a first layer (1) of a wide band gap semiconductor material doped according to a first conductivity type and a second layer (3) on top thereof designed to form a junction blocking current in the reverse biased state of the device at the interface to said... Agent: Dilworth & Barrese, LLP

20070018172 - Crystals of phenylalanine derivatives and production methods thereof: s

20070018173 - Method of fabricating vertical devices using a metal support film: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal techniques. Trenches that define the boundaries of the individual devices are formed through the semiconductor layers and into the insulating substrate, beneficially by inductive... Agent: Mckenna Long & Aldridge LLP

20070018174 - Light emission from semiconductor integrated circuits: Structures and methods to inject electrons into an insulator from a semiconductor layer that are then collected in a thin layer of a direct semiconductor material which in turn emits light by bandgap recombination.... Agent: John P. O'banion O'banion & Ritchey LLP

20070018175 - Light emitting diodes with improved light collimation: A light emitting diode with improved light collimation comprises a substrate-supported LED die disposed within a transparent dome. A portion of the dome laterally circumscribe the die comprises light reflecting material to reflect emitted light back to the die. A portion of the dome centrally overlying the die is substantially... Agent: Patent Docket Administrator Lowenstein Sandler PC

20070018176 - Image display device and method of manufacturing the same: An image display device includes an envelope having a first substrate and a second substrate located opposite the first substrate across a gap and a plurality of pixels provided in the envelope. A plurality of columnar spacers which support an atmospheric load acting on the first and second substrates are... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070018179 - Vertical conducting power semiconducting devices made by deep reactive ion etching: The Invention Is A Method For Making Power Device On A Semiconductor Wafer, Where The Backside Of The Wafer Has Been Thinned In Selected Regions To A Thickness Of About 25 Um By Reactive Ion Etching.... Agent: Naval Research Laboratory Associate Counsel (patents)

20070018178 - Vertical electrode structure of gallium nitride based light emitting diode: A vertical electrode structure of GaN-based light emitting diode discloses an oxide window layer constructing the GaN-based light emitting diode of vertical electrode structure, which effectively decreases the Fresnel reflection loss and total reflection, and further advances the luminous efficiency. Moreover, the further included metal reflecting layer causes the reflection... Agent: Rosenberg, Klein & Lee

20070018177 - Vertical gan-based led and method of manufacturing the same: Provided are a vertical GaN-based LED and a method of manufacturing the same. The vertical GaN-based LED includes an n-electrode. An AlGaN layer is formed under the n-electrode. An undoped GaN layer is formed under the AlGaN layer to provide a two-dimensional electron gas layer to a junction interface of... Agent: Mcdermott Will & Emery LLP

20070018180 - Vertical electrode structure of gallium nitride based light emitting diode: A vertical electrode structure of GaN-based light emitting diode discloses an oxide window layer constructing the GaN-based light emitting diode of vertical electrode structure, which effectively decreases the Fresnel reflection loss and total reflection, and further advances the luminous efficiency. Moreover, the further included metal reflecting layer causes the reflection... Agent: Rosenberg, Klein & Lee

20070018186 - Light emitting diode device having advanced light extraction efficiency and preparation method thereof: Disclosed is an LED device, a method for manufacturing the same, and a light emitting apparatus having the same. The LED device includes (a) a light emitting diode unit and (b) an adjustment layer laminated on a light emitting surface of the light emitting diode unit, a fine pattern having... Agent: Mckenna Long & Aldridge LLP

20070018185 - Light emitting diode package and light guide pipe and backlight module and liquid crystal display device using the same: A light emitting diode (LED) package includes a base, a body and several LED chips. The body having an end surface is disposed on the base. A peripheral recess is formed in the end surface. The LED chips are disposed on a bottom of the peripheral recess for providing sidelight... Agent: Lowe Hauptman Berner, LLP

20070018184 - Light emitting diodes with high light extraction and high reflectivity: The invention is a light emitting diode that exhibits high reflectivity to externally incident light and high extraction efficiency for internally generated light. The light emitting diode includes a first reflecting electrode that reflects both externally incident light and internally generated light. The first reflecting electrode can be a metal... Agent: William Propp, Esq. Goldeneye, Inc.

20070018182 - Light emitting diodes with improved light extraction and reflectivity: The invention is a light emitting diode that exhibits high reflectivity to externally incident light and high extraction efficiency for internally generated light. The light emitting diode includes a first reflecting electrode that reflects both externally incident light and internally generated light. A multi-layer semiconductor structure is in contact with... Agent: William Propp, Esq. Goldeneye, Inc.

20070018183 - Roughened high refractive index layer/led for high light extraction: A light emitting diode (LED) includes a p-type layer of material, an n-type layer of material and an active layer between the p-type layer and the n-type layer. A roughened layer of transparent material is adjacent one of the p-type layer of material and the n-type layer of material. The... Agent: Koppel, Patrick & Heybl

20070018188 - Thin film transistor sunstrate of a horizontal electric filed type and method of darkening deflective pixel in the same: A method of darkening a defective pixel including a short between a source electrode and a drain electrode in a thin film transistor substrate includes forming a gate line and a data line on a substrate to define a pixel region; forming a thin film transistor at a crossing of... Agent: Mckenna Long & Aldridge LLP

20070018187 - Vertical gan-based led and method of manfacturing the same: A vertical GaN-based LED and a method of manufacturing the same are provided. The vertical GaN-based LED includes an n-electrode, a first n-type GaN layer, a first AlGaN layer, a GaN layer, a second AlGaN layer, a second n-type GaN layer, an active layer, a p-type GaN layer, and a... Agent: Mcdermott Will & Emery LLP

20070018181 - White led headlight: A vehicle headlight (12) that employs a plurality of LED units (38) that emit white light. Each LED unit (38) employs chip-on-board technology where LED semiconductor chips (64) are mounted directly to a submount substrate (56) using solder or stud bumps (60). An elongated lens (28) is molded over the... Agent: Warn Hoffmann Miller & Lalone

20070018190 - Led package and fabricating method thereof: The invention provides an LED package capable of effectively releasing heat emitted from an LED chip out of the package and a fabrication method thereof. For this purpose, at least one groove is formed on an underside surface of the substrate to package the LED chip and the groove is... Agent: Mcdermott Will & Emery LLP

20070018189 - Light emitting diode: A light emitting diode is disclosed. A light emitting diode comprises: a bracing frame; and at least two chips stacked on the bracing frame in a chip-on-chip stacking manner. The light emitting diode for uniform color mixing is completed after each of said at least two chips is electrically connected.... Agent: Troxell Law Office PLLC Suite 1404

20070018191 - Side view led with improved arrangement of protection device: A side view LED includes an insulating substrate, and first and second metal layers each having first and second areas spaced apart from each other at a predetermined gap and disposed on top and underside surfaces of the insulating substrate, respectively. First and second electrical connectors are formed in a... Agent: Mcdermott Will & Emery LLP

20070018192 - Devices incorporating heavily defected semiconductor layers: The structure and growth method are disclosed for a novel heterojunction diode structure. The invention exploits the Fermi level pinning properties of dislocations and defects in compound semiconductors to achieve heterojunctions with nonlinear current-voltage characteristics despite highly defected, polycrystalline, or amorphous semiconductors. The invention enable new diode, photodetector, and transistor... Agent: Dr. Dave S. Garrod, Esq. Goodwin-procter

20070018193 - Initial-on scr device for on-chip esd protection: A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070018194 - Driving circuit: When a PWM command signal reaches a low level, an input transistor turns on, an on-driving transistor turns off, Darlington-connected off-driving transistors connected in series with the on-driving transistor turn on, and an output MOSFET changes from an on-state to an off-state. At this time, a base current of the... Agent: Posz Law Group, PLC

20070018195 - Semiconductor structure and method: A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070018196 - Power semiconductor device with current sense capability: A power semiconductor device includes a power device and a current sense device formed in a common semiconductor region.... Agent: Ostrolenk Faber Gerb & Soffen

20070018197 - Semiconductor device: A semiconductor device is disclosed that includes a first and a second semiconductor package. Each semiconductor package includes a semiconductor element, a plurality of electrode members, and an encapsulating member. The semiconductor elements are interposed between the respective electrode members, and the electrode members are in electrical communication with and... Agent: Posz Law Group, PLC

20070018198 - High electron mobility electronic device structures comprising native substrates and methods for making the same: An electronic device structure comprises a substrate layer of semi-insulating AlxGayInzN, a first layer comprising AlxGayInzN, a second layer comprising Alx′Gay′Inz′N, and at least one conductive terminal disposed in or on any of the foregoing layers, with the first and second layers being adapted to form a two dimensional electron... Agent: Intellectual Property / Technology Law

20070018199 - Nitride-based transistors and fabrication methods with an etch stop layer: A III-Nitride field-effect transistor, specifically a HEMT, comprises a channel layer, a barrier layer on the channel layer, an etch stop layer on the cap layer, a dielectric layer on the etch stop layer, a gate recess that extends to the barrier layer, and a gate contact in the gate... Agent: Myers Bigel Sibley & Sajovec

20070018200 - Single frequency laser: This invention relates to generally to semiconductor devices, for example lasers and more particularly to single frequency lasers and is directed at overcoming problems associated with the manufacture of these devices. In particular, a laser device is provided formed on a substrate having a plurality of layers (1,2,3,4,5), the laser... Agent: Gordon & Rees LLP

20070018201 - Non-volatile memory cells and methods for fabricating non-volatile memory cells: The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory cells. The stacked non-volatile memory cells are formed on a semiconductor wafer, having a... Agent: Slater & Matsil LLP

20070018202 - High performance mosfet comprising stressed phase change material and method of fabricating the same: The present invention relates to semiconductor devices that each comprises at least one field effect transistor (FET) containing an intrinsically stressed phase change material layer. The intrinsically stressed phase change material layer is arranged and constructed for creating stress in the channel region of the FET. Preferably, the intrinsically stressed... Agent: Scully, Scott, Murphy & Pressner, P.C.

20070018203 - Strain inducing multi-layer cap: A strained transistor includes a silicon transistor, an encapsulating layer of silicon insulating material with an outer surface, and a stress inducing multilayer cap deposited on the outer surface of the encapsulating layer with at least two layers including a layer of rare earth oxide and a layer including silicon.... Agent: Robert A. Parsons

20070018204 - High-frequency device including high-frequency switching circuit: A high-frequency device having a switching circuit includes a compound semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency input/output terminal; a control signal input terminal; a power terminal; a ground terminal; an insulating portion disposed on one main surface of the compound semiconductor substrate; and a voltage-applying electrode... Agent: Sonnenschein Nath & Rosenthal LLP

20070018208 - Depletable cathode low charge storage diode: An integrated circuit device comprising a diode and a method of making an integrated circuit device comprising a diode are provided. The diode can comprise an island of a first conductivity type, a first region of a second conductivity type formed in the island, and a cathode diffusion contact region... Agent: Min, Hsieh & Hack LLP

20070018209 - Semiconductor circuit device and simulation method of the same: A first PMIS transistor includes a first active region which is formed on a semiconductor substrate and a first gate electrode which is formed on the first active region and which is connected at one end thereof to a first gate wiring and includes at the other end thereof a... Agent: Mcdermott Will & Emery LLP

20070018207 - Split gate storage device including a horizontal first gate and a vertical second gate in a trench: A split gate storage device includes a first gate electrode in contact with a first gate dielectric and a second gate electrode in contact with a second gate dielectric. A first diffusion region underlies a portion of a trench defined in a semiconductor substrate and a second diffusion region occupies... Agent: Larson Newman Abel Polansky & White, LLP

20070018205 - Structure and method for improved stress and yield in pfets with embedded sige source/drain regions: The present invention provides a technique for forming a CMOS structure including at least one pFET that has a stressed channel which avoids the problems mentioned in the prior art. Specifically, the present invention provides a method for avoiding formation of deep canyons at the interface between the active area... Agent: Scully, Scott, Murphy & Pressner, P.C.

20070018206 - Surround gate access transistors with grown ultra-thin bodies: A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short... Agent: Knobbe Martens Olson & Bear LLP

20070018210 - Switch mode power amplifier using mis-hemt with field plate extension: Disclosed are a switch mode power amplifier and a field effect transistor especially suitable for use in a switch mode power amplifier. The transistor is preferably a compound high electron mobility transistor (HEMT) having a source terminal and a drain terminal with a gate terminal therebetween and positioned on a... Agent: Beyer Weaver & Thomas, LLP

20070018211 - High dielectric constant spacer for imagers: An imager having gates with spacers formed of a high dielectric material. The high dielectric spacer provides larger fringing fields for charge transfer and improves image lag and charge transfer efficiency.... Agent: Dickstein Shapiro LLP

20070018213 - Cmos image sensor and method of fabricating the same: A complementary metal-oxide semiconductor (CMOS) image sensor and a method of fabricating the same arc disclosed. In a complementary metal-oxide semiconductor (CMOS) image sensor including a photodiode receiving irradiated light and generating electric charges, a plurality of conductive circuits each formed in different layers, a plurality of interlayer dielectrics insulating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070018212 - Photodiode array and production method thereof, and radiation detector: A photodiode array 1 is provided with an n-type silicon substrate 3. A plurality of photodiodes 4 are formed in array on the opposites surface side to an incident surface of light L to be detected, in the n-type silicon substrate 3. A depression 6 with a predetermined depth more... Agent: Drinker Biddle & Reath (dc)

20070018214 - Magnesium titanium oxide films: Embodiments of a magnesium titanium oxide structure on a substrate provide a dielectric for use in a variety of electronic devices. Embodiments of methods of fabricating such a dielectric include forming the magnesium titanium oxide structure by atomic layer deposition.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070018216 - Electronic device including discontinuous storage elements: An electronic device can include discontinuous storage elements that lie within a trench. The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate. The electronic device can also include discontinuous storage elements, wherein a... Agent: Larson Newman Abel Polansky & White, LLP

20070018218 - Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement and method for producing the fin field effect transistor memory cell: The invention relates to a bridge field-effect transistor storage cell comprising first and second source/drain areas and a channel area arranged therebetween, which are formed in a semiconductor bridge. The inventive storage cell also comprises a charge-coupled layer that is disposed at least partially on the semiconductor bridge and a... Agent: Slater & Matsil LLP

20070018215 - Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The bottom portions can... Agent: Wells St. John P.s.

20070018217 - Semiconductor device and manufacturing method of the same: According to the present invention, a semiconductor device manufacturing method includes the steps of: forming a capacitor formation groove in a silicon (semiconductor) substrate; and forming a second insulating film by thermally oxidizing at least the upper surface of the silicon substrate and the bottom and the side surfaces of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070018220 - Semiconductor device, gate electrode and method of fabricating the same: Example embodiments of the present invention provide a semiconductor device, a gate electrode and method of manufacturing the same. Other example embodiments of the present invention provide a gate electrode with a refractory metal layer having decreased sheet resistance and increased reliability, a semiconductor device and a method of manufacturing... Agent: Harness, Dickey & Pierce, P.L.C

20070018219 - Unit cell structure, method of manufacturing the same, non-volatile semiconductor device having the unit cell structure and method of manufacturing the non-volatile semiconductor device: A unit cell structure in a non-volatile semiconductor device includes a lower electrode. The variable resistor is formed on the lower electrode and includes a first insulation thin film, a third insulation thin film, and a second insulation thin film located between the first and third insulation thin films. A... Agent: Volentine Francos, & Whitt PLLC

20070018222 - electronic device including discontinuous storage elements: An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench.... Agent: Larson Newman Abel Polansky & White, LLP

20070018221 - Programmable structure including discontinuous storage elements and spacer control gates in a trench: A semiconductor storage cell includes first and second source/drain regions underlying first and second trenches defined in a semiconductor substrate. Sidewalls of the trenches are lined with a charge storage stack that includes a layer of discontinuous storage elements (DSEs), which are preferably silicon nanocrystals. Spacer control gates are located... Agent: Larson Newman Abel Polansky & White, LLP

20070018223 - Dram including a vertical surround gate transistor: DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line... Agent: Knobbe Martens Olson & Bear LLP

20070018224 - Devices and methods for preventing capacitor leakage: Devices and methods for preventing capacitor leakage caused by sharp tip. The formation of sharp tip is avoided by a thicker bottom electrode which fully fills a micro-trench that induces formation of the sharp tip. Alternatively, formation of the sharp tip can be avoided by recessing the contact plug to... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070018225 - Integrated stacked capacitor and method of fabricating same: An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide (poly), a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second... Agent: Texas Instruments Incorporated

20070018226 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory includes: a memory cell transistor including a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode; a low voltage transistor constituted by a low voltage gate insulating film, a floating gate electrode, an inter-gate insulating film having an opening,... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070018227 - Three-gate transistor structure: A transistor structure comprises a semiconductor element extending between a source zone and a drain zone, as well as three portions of gates disposed on different sides of the semiconductor element. Such a structure is especially compact and may be used as two or three transistors having independent respective functions.... Agent: Seed Intellectual Property Law Group PLLC

20070018230 - Eeprom and methods of fabricating the same: An EEPROM includes a tunneling opening having an inclined or a stepped sidewall. A tunnel insulation layer is formed within the tunneling opening. Using a flowed photoresist pattern as an etching mask, the gate insulator is etched to form a tunneling opening having an inclined sidewall. Thus, the tunnel insulation... Agent: Mills & Onello LLP

20070018229 - Electronic device including discontinuous storage elements and a process for forming the same: An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate that includes a trench extending into a semiconductor material. The trench can include a ledge and a bottom, wherein the bottom lies at a depth deeper than... Agent: Larson Newman Abel Polansky & White, LLP

20070018228 - Non-volatile memory with carbon nanotubes: Floating-gate memory cells having carbon nanotubes interposed between the substrate and the tunnel dielectric layer facilitate ballistic injection of charge into the floating gate. The carbon nanotubes may extend across the entire channel region or a portion of the channel region. For some embodiments, the carbon nanotubes may be concentrated... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070018231 - Nonvolatile semiconductor memory device, semiconductor device and manufacturing method of nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070018232 - Nonvolatile storage array with continuous control gate employing hot carrier injection programming: An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous... Agent: Larson Newman Abel Polansky & White, LLP

20070018233 - Semiconductor device and control method therefor: A semiconductor device includes an insulation layer (14) provided on a semiconductor substrate (12), a p-type semiconductor region (16) provided on the insulation layer, an isolation region (18) provided that surrounds the p-type semiconductor region to reach the insulation layer, an n-type source region (20) and an n-type drain region... Agent: Wagner, Murabito & Hao LLP Two N. Market Street

20070018234 - Electronic device including gate lines, bit lines, or a combination thereof: An electronic device can include memory cells that are connected to gate lines, bit lines, or a combination thereof. In one embodiment, at least two sets of memory cells can be oriented substantially along a first direction, (e.g., rows or columns). A first gate line may be electrically connected to... Agent: Larson Newman Abel Polansky & White, LLP

20070018235 - Nonvolatile semiconductor memory device including improved gate electrode: A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070018237 - Non-volatile memory device having fin-type channel region and method of fabricating the same: A non-volatile memory device with improved integration and/or improved performance by reducing an area per bit and controlling a body bias, and a method of fabricating the same. The non-volatile memory device may use surface portions of the outer side surfaces and/or the upper surfaces of at least one pair... Agent: Harness, Dickey & Pierce, P.L.C

20070018236 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor substrate, a monocrystalline channel region of a first conductivity type formed on the surface of the semiconductor substrate, a gate electrode formed on the channel region via a gate insulating film, a pair of source/drain electrodes of a second conductivity type provided on both... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070018238 - Semiconductor device: A semiconductor device includes a semiconductor layer, a pair of a source region and a drain region formed to face each other in a direction on the semiconductor layer and made of a metal or a metal silicide, a first dielectric film formed on at least the semiconductor layer between... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070018239 - Sea-of-fins structure on a semiconductor substrate and method of fabrication: A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070018241 - Early contact, high cell density process: A method of fabricating a power semiconductor device in which contact trenches are formed prior to forming the gate trenches.... Agent: Ostrolenk Faber Gerb & Soffen

20070018240 - Electronic device including discontinuous storage elements: An electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a first set of discontinuous storage elements that overlie a primary surface of the substrate and a second set of discontinuous storage elements that lie within the... Agent: Larson Newman Abel Polansky & White, LLP

20070018242 - Power semiconductor device: Disclosed is a power semiconductor device, including: a gate electrode having a cross section having a length in a vertical direction, and having a shape extending in a direction orthogonal to the cross section; a gate insulating film surrounding the gate electrode; an n-type source layer positioning to face the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070018243 - Semiconductor element and method of manufacturing the same: A semiconductor element is provided, comprising a first semiconductor layer of the first conduction type; and a pillar layer including first semiconductor pillars of the first conduction type and second semiconductor pillars of the second conduction type arranged periodically and alternately on the first semiconductor layer. A semiconductor base layer... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070018244 - Gate electrode structures and methods of manufacture: Gate electrode structures used in field effect transistors and integrated circuits and methods of manufacture are disclosed. Improved work function and threshold modulation are provided by the methods and structures.... Agent: Applied Materials, Inc. Legal Affairs Department

20070018245 - Fringing field induced localized charge trapping memory: The present invention includes a semiconductor layer formed over an insulation layer and a substrate. Doped regions are formed in a portion of the semiconductor layer. A gate dielectric and a gate are respectively formed over the semiconductor layer. The arrangement of the gate sidewall and semiconductor layer surface is... Agent: Kusner & Jaffe Highland Place Suite 310

20070018247 - Method and apparatus for use in improving linearity of mosfet's using an accumulated charge sink: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment,... Agent: Martin J. Jaquez, Esq. Jaquez & Associates

20070018246 - Semiconductor device and semiconductor device manufacturing method: A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer, a second insulating layer formed on the first single-crystal semiconductor layer, a second single-crystal semiconductor layer formed on the second insulating layer and having a film thickness smaller than... Agent: Oliff & Berridge, PLC

20070018248 - Power gating schemes in soi circuits in hybrid soi-epitaxial cmos structures: Disclosed are a multi-threshold CMOS circuit and a method of designing such a circuit. The preferred embodiment combines an MTCMOS scheme and a hybrid SOI-epitaxial CMOS structure. Generally, the logic transistors (both nFET and pFET) are placed in SOI, preferably in a high-performance, high density UTSOI; while the headers or... Agent: Scully Scott Murphy & Presser, PC

20070018249 - Extended drain metal oxide semiconductor transistor and manufacturing method thereof: A MOS transistor having an extended drain structure and including a semiconductor substrate formed in a well of a first conductivity type. A gate insulating layer is formed on the substrate, a gate electrode is formed on the gate insulating layer, and a source region is formed in a first... Agent: Sang Bum Lee

20070018250 - High-voltage diodes formed in advanced power integrated circuit devices: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.... Agent: Hiscock & Barclay, LLP

20070018251 - Semiconductor device and method for fabricating the same: In a MIEET, an impurity which changes a lattice constant is introduced into part of a gate electrode located on an isolation region. A stress which is generated in part of the gate electrode as a starting point and improves the mobility of carries is applied to a channel region... Agent: Mcdermott Will & Emery LLP

20070018253 - Memory cell and manufacturing methods: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate, a first memory device array on the semiconductor substrate, and a logic circuit on the semiconductor substrate. Substantially all gates of at least one type of PMOS and NMOS devices in the... Agent: Slater & Matsil, L.L.P.

20070018252 - Semiconductor device containing high performance p-mosfet and/or n-mosfet and method of fabricating the same: The present invention relates to semiconductor devices that comprise at least one n-channel field effect transistor (n-FET) and/or at least one p-channel field effect transistor (p-FET). The n-FET contains a source region and a drain region with a tensilely stressed metal silicide surface layer, which applies tensile stress to the... Agent: Scully, Scott, Murphy & Pressner, P.C.

20070018255 - Semiconductor device and method for fabricating the same: The method for fabricating a semiconductor device according to the present invention comprises the step of forming a Ni film 66 on source/drain diffused layers 64, the step of performing a first thermal processing to react a lower part of the Ni film 66 and an upper part of the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070018254 - Shared contact structure, semiconductor device and method of fabricating the semiconductor device: A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The... Agent: Harness, Dickey & Pierce, P.L.C

20070018256 - Semiconductor memory device and method for generating rom data pattern: By simplifying the shape of memory cell diffused mask patterns, the patterns are formed stably and the yield of a semiconductor memory device is improved. Adjacent 2-bit memory cell transistors are formed with one diffused mask pattern, the diffused mask patterns are arranged on a memory cell array, and metal... Agent: Stevens, Davis, Miller & Mosher, LLP

20070018257 - Electronic circuit having variable biasing: Techniques are provided for selectively biasing wells in a circuit, such as a Complementary Metal Oxide Semiconductor (CMOS) circuit, that has two types of transistors, one type formed on a substrate and another type formed on the wells. For example, the circuit can be a memory circuit, and the selective... Agent: Ryan, Mason & Lewis, LLP

20070018258 - High-voltage device structure: A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region... Agent: North America Intellectual Property Corporation

20070018259 - Dual gate electrode metal oxide semciconductor transistors: A semiconductor product includes a pair of field effect transistor device structures formed one each within a pair of doped well regions within a semiconductor substrate. The pair of field effect transistor device structures is formed with a pair of metal gate electrodes formed employing different laminated metal constructions. By... Agent: Tung & Associates

20070018260 - Devices having vertically-disposed nanofabric articles and methods of making the same: Electro-mechanical switches and memory cells using vertically-disposed nanofabric articles and methods of making the same are described. An electro-mechanical device, includes a structure having a major horizontal surface and a channel formed therein. A conductive trace is in the channel; and a nanotube article vertically suspended in the channel, in... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070018261 - Low compressive tinx materials and methods of making the same: Disclosed herein is a microelectromechanical device having a structural layer composed of a low stress TiNx layer and a method of making the same.... Agent: Texas Instruments Incorporated

20070018262 - Micromachine and production method thereof: A micromachine for a high-frequency filter which has a high Q value and a higher frequency band is provided. The micromachine includes an electrode provided on a substrate, an inter-layer insulation film composed of a first insulation film and a second insulation film which are provided on the substrate in... Agent: Sonnenschein Nath & Rosenthal LLP

20070018263 - Semiconductor device and manufacturing method of the same: The invention is directed to enhancement of performance of a back surface incident type semiconductor device having a light receiving element and a manufacturing method thereof without increasing a manufacturing cost. A supporting body is attached to a front surface of a semiconductor substrate formed with a light receiving element... Agent: Morrison & Foerster LLP

20070018264 - Optimized image sensor process and structure to improve blooming: An image sensor that has a pixel array using an isolation structure between pixels that reduce electrical cross-talk is disclosed. The pixel array is formed on a substrate that has a thin (less than 5 microns) epitaxial layer. The isolation structure uses a deep p-well to surround a shallow trench... Agent: Perkins Coie LLP

20070018265 - Mask, mask manufacturing method, film forming method, electro-optic device manufacturing method, and electronic apparatus: A mask includes: a base plate having an opening; a chip having an aperture pattern positioned at the opening in the base plate; a plug detachably arranged to the base plate; and a joining member joining the chip and the plug.... Agent: Harness, Dickey & Pierce, P.L.C

20070018266 - Photodetecting device: A method of manufacturing a photodetecting device, by providing a first wafer that includes a photosensitive layer made of a semiconductor material and a second wafer that includes a circuit layer of electronic components, with one of the photosensitive layer or the circuit layer incorporating a field isolation layer; bonding... Agent: Winston & Strawn LLP Patent Department

20070018267 - Anti-blooming storage pixel: Embodiments of the present invention provide pixel cells with increased storage capacity, which are capable of anti-blooming operations. In an exemplary embodiment a pixel cell has an electronic shutter that transfers charge generated by a photo-conversion device to a storage node before further transferring the charge to the pixel cell's... Agent: Dickstein Shapiro LLP

20070018270 - Embedded waveguide detectors: A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the... Agent: (bos) Wilmerhale/applied Materials

20070018268 - Monolithically integrated vertical pin photodiode used in bicmos technology: The invention relates to a monolithically integrated vertical pin photodiode which is produced according to BiCMOS technology and comprises a planar surface facing the light and a rear face and anode connections located across p areas on a top face of the photodiode. An i-zone of the pin photodiode is... Agent: Duane Morris, LLPIPDepartment

20070018269 - Raised silicon photodiode: A pinned photodiode that includes a raised silicon epitaxial layer that serves as a passivating layer. This allows the N−region to be near the surface of the silicon substrate, which enhances linkage to the transfer gate. The photodiode comprises an N−region formed within a P-type region of a semiconductor substrate... Agent: Perkins Coie LLP

20070018271 - Split control pad for multiple signal: A control pad is split into two sections for output one of three signals selected from the group consisted of 00, 01, and 11 on an integrated circuit. Each section is internally connected to different voltage sources, say Vdd which represents logical “1”, or Vss which represents logical “0”, so... Agent: Hung Chang Lin

20070018272 - Reduced leakage power devices by inversion layer surface passivation: A semiconductor device is disclosed that includes a contact and an adjacent film on the surface of an underlying doped semiconductor material. The film has sufficient fixed charge to create an inversion layer adjacent the surface of the doped semiconductor material that under depletion conditions at least balances the number... Agent: Summa, Allan & Additon, P.A.

20070018273 - Reduced electric field dmos using self-aligned trench isolation: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first... Agent: Schneck & Schneck

20070018274 - Semiconductor circuit arrangement and method: One aspect of the present invention relates to a semiconductor circuit arrangement and to a method for producing the latter. One aspect of the invention is that, as a result of a connecting trench structure and an isolation trench structure of a semiconductor circuit being in direct spatial proximity with... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070018276 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device that suppresses emergence of a waste in an isolation trench formation process is to be provided. The method comprises forming an isolation trench having a predetermined depth from a surface of a semiconductor substrate; forming a dielectric layer on the surface of the... Agent: Sughrue Mion, PLLC

20070018275 - Semiconductor device with trench structure: A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define sizes of the semiconductor components and isolate the semiconductor components from the surrounding... Agent: Posz Law Group, PLC

20070018277 - Field effect transistor and semiconductor device: Channel forming sections that are respectively p types and have hexahedral structures are provided in a silicon epitaxial layer of an SOS substrate. Gate oxide films and a gate electrode are provided at both side surfaces of the channel forming sections. Thus, channels can be formed along both side surfaces... Agent: Nixon Peabody, LLP

20070018278 - Semiconductor memory device: The channel regions (T) of the memory cells are directed transversly to the word lines (2), which are arranged parallel at a distance from one another. Local interconnects (6) connect the source/drain regions of the memory cell transistors to bit lines running across the word lines and are connected to... Agent: Slater & Matsil LLP

20070018279 - Protection layer for preventing laser damage on semiconductor devices: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on... Agent: Howard Chen Preston Gates & Ellis LLP

20070018280 - Antifuse structure and system for closing thereof: A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more... Agent: Ratnerprestia

20070018281 - Packaging chip having inductor therein: A packaging chip having inductors therein. The packaging chip includes a substrate for mounting a circuit element therein, at least one port formed on a surface of the substrate, a sealing portion electrically connected on the substrate to the circuit element and the at least one port, respectively, and a... Agent: Sughrue Mion, PLLC

20070018282 - Semiconductor device and fabrication method thereof: A semiconductor device includes a semiconductor substrate having a plurality of conductive layers. The device further includes buried contacts and buried vias, which connect the interconnect layers respectively. At least one of the contacts and vias is dummy.... Agent: Volentine Francos, & Whitt PLLC

20070018283 - Zener diode: A zener diode, including: a semiconductor substrate; a first region of the first conductivity type formed on the surface of the semiconductor substrate; and a second region of the second conductivity type formed on the surface of the semiconductor substrate and included in the first region; and having a pn... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070018284 - Gallium nitride semiconductor substrate and process for producing the same: Dry etching utilizing a halogen plasma is carried out in order to remove the process-transformed layer. The Ga face can be etched off with the halogen plasma. Nevertheless, owing to the dry etching, a problem arises again-surface contamination due to metal particles. To address the problem, wet etching with, as... Agent: Judge & MurakamiIPAssociates

20070018285 - Device containing isolation regions with threading dislocations: An article of manufacture includes a substrate, a relaxed buffer layer disposed on the substrate, and a plurality of isolation regions formed in the relaxed buffer layer. The isolation regions include threading dislocations while the remainder of the relaxed buffer layer is substantially free of threading dislocations. The relaxed buffer... Agent: VistaIPLaw Group LLP

20070018286 - Substrate, lithographic multiple exposure method, machine readable medium: A method for imaging using a lithographic system includes decomposing a desired pattern to be printed on the substrate into at least two constituent sub-patterns that are capable of being optically resolved by the lithographic system, coating a substrate a substrate with a stack of two sacrificial hard masks on... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070018287 - Electronic device and carrier substrate for same: The electronic device (100) comprises an integrated circuit (10) and a carrier substrate (20) with a bottom and top conductive layer, and is provided with voltage supply, ground and signal transmission connections. In order to enable the use of more than one supply voltage, the integrated circuit (10) is subdivided... Agent: Philips Intellectual Property & Standards

20070018290 - Large die package structures and fabrication method therefor: A method for fabricating large die package structures is provided wherein at least portions of the leadtips of at least a plurality of leadfingers of a leadframe are electrically insulated. A die is positioned on the electrically insulated leadtips. The die is electrically connected to at least a plurality of... Agent: The Law Offices Of Mikio Ishimaru

20070018288 - Packaging for high speed integrated circuits: An integrated circuit package comprises an integrated circuit die comprising a first pad, a second pad adjacent to the first pad, a third pad adjacent to the second pad, and a fourth pad adjacent to the third pad. A lead frame comprising a first lead, a second lead adjacent to... Agent: Harness, Dickey & Pierce P.L.C

20070018289 - Packaging for high speed integrated circuits: A lead frame for an integrated circuit die comprises a first lead, a second lead adjacent to the first lead, a third lead adjacent to the second lead, and a fourth lead adjacent to the third lead. A first end of the fourth lead extends beyond at least one of... Agent: Harness, Dickey & Pierce P.L.C

20070018291 - Semiconductor package without chip carrier and fabrication method thereof: A semiconductor package without a chip carrier includes an insulating structure having an opening; an electroplated die pad provided in the opening; a chip attached to the electroplated die pad by a thermally conductive adhesive; a plurality of electrical contacts formed around the electroplated die pad, wherein at least one... Agent: Birch Stewart Kolasch & Birch

20070018295 - Apparatus for stacking semiconductor chips, method for manufacturing semiconductor package using the same and semiconductor package manufactured thereby: The present invention relates to an apparatus for stacking semiconductor chips, a method for manufacturing a semiconductor package using the same and a semiconductor package manufactured thereby. The apparatus for stacking semiconductor chips may comprise two tables for supporting wafers, a picker for picking up semiconductor chips and a picker... Agent: Marger Johnson & Mccollom, P.C.

20070018292 - Packaging for high speed integrated circuits: An integrated circuit package comprises an integrated circuit die comprising a first pad, a second pad adjacent to the first pad, a third pad adjacent to the second pad, and a fourth pad adjacent to the third pad. A lead frame comprises a first lead, a second lead adjacent to... Agent: Harness, Dickey & Pierce P.L.C

20070018293 - Packaging for high speed integrated circuits: An integrated circuit package comprises an integrated circuit die comprising N adjacent pads, where N is an integer greater than three. A lead frame comprises first, second, third and fourth leads that include first ends that are spaced from the integrated circuit die and second ends that are adjacent to... Agent: Harness, Dickey & Pierce P.L.C

20070018294 - Packaging for high speed integrated circuits: An integrated circuit package comprises an integrated circuit die comprising N pads, where N is an integer greater than one. A lead frame comprising N adjacent leads. N connections individually connect the N leads to the N pads, respectively. A first material comprises an insulating layer and a conductive layer.... Agent: Harness, Dickey & Pierce P.L.C

20070018296 - Stacked semiconductor package having adhesive/spacer structure and insulation: Stacked semiconductor assemblies in which a device such as a die, or a package, or a heat spreader is stacked over a first wire-bonded die. An adhesive/spacer structure is situated between the first wire-bonded die and the device stacked over it, and the device has an electrically non-conductive surface facing... Agent: Haynes Beffel & Wolfeld LLP

20070018297 - High-capacity memory card and method of making the same: A memory card assembly with a simplified structure. The memory card assembly has a memory card assembly a printed wiring board substrate and at least one integrated circuit unit mounted and electrically connected to the printed wiring board substrate. A rigid ring is fitted over a periphery of the printed... Agent: Stetina Brunda Garred & Brucker

20070018300 - Apparatus and method for testing a multi-stack integrated circuit package: Provided is an apparatus and method for a testing multi-stack integrated circuit package. The apparatus may include a vacuum pump and a socket. The socket may include a plurality of internal pins, a plurality of external pins, a socket body, and at least one first air inlet. The plurality of... Agent: Harness, Dickey & Pierce, P.L.C

20070018299 - Memory module with stacked semiconductor devices: Embodiments are described in which a stacked arrangement of integrated circuit packages comprises a dummy substrate comprising an embedded discrete or distributed capacitor connected to first and/or second power voltages, or an embedded termination register connected to one or more clock, control, address, and/or data signals(s).... Agent: Volentine Francos, & Whitt PLLC

20070018298 - Optimized multi-apparation assembly: The invention relates to a microelectronic chip assembly ASS comprising at least three microelectronic chip ICH, TCH, BCH stacked together and on which integrated devices are formed. At least one of the chip, called intermediate chip ICH, includes via holes VH running through said chip ICH and filled with conductive... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070018302 - Planar light source device and display device provided with the same: A planar light source includes a first substrate, a second substrate disposed to be spaced apart from the first substrate so as to form a discharge region, a first electrode formed on the first substrate, and a second electrode formed on the second substrate. The planar light source further includes... Agent: F. Chau & Associates, LLC

20070018301 - Semiconductor device and method of manufacturing the same: A semiconductor device including a package (2) having a plurality of wall portions (9a) and a plurality of conductor portions (4), a semiconductor element such as a solid-state image pickup device (1) mounted in an internal space of the base, thin metal wires (5) electrically connecting the semiconductor element and... Agent: Steptoe & Johnson LLP

20070018303 - Stack package made of chip scale packages: A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip... Agent: Marger Johnson & Mccollom, P.C.

20070018304 - Composite metal column for mounting semiconductor device: An integrated circuit chip which has a plurality of pads and non-reflowable contact members to be connected by reflow attachment to external parts. Each of these contact members has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface on each... Agent: Texas Instruments Incorporated

20070018305 - Packaging for high speed integrated circuits: An integrated circuit package comprises an integrated circuit die comprising N adjacent pads, where N is an integer greater than three. A substrate comprises a first pair of traces including first and second traces and a second pair of traces including third and fourth traces. The first, second, third and... Agent: Harness, Dickey & Pierce P.L.C

20070018306 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device, including: providing a semiconductor substrate which has a plurality of electrodes and in which a depression is formed on a side on which the electrodes are formed; forming a resin protrusion on the semiconductor substrate so that part of the resin protrusion is... Agent: Oliff & Berridge, PLC

20070018307 - Integrated circuit chip module: An integrated circuit chip module includes a first integrated circuit chip including a first power source pad for a first power voltage and an adjacent second power source pad for a second power voltage, the first power voltage being higher than the second power voltage, a second integrated circuit chip... Agent: Leydig Voit & Mayer, Ltd

20070018308 - Electronic component and electronic configuration: An electronic component includes a substrate with outer contact areas including copper. Lead-free solder bumps are disposed on the outer contact areas of the electronic component. An electronic configuration includes an electronic component and a printed circuit board. The electronic component is mounted on the printed circuit board by lead-free... Agent: Edell, Shapiro & Finnan, LLC

20070018309 - Image sensor package, optical glass used therein, and processing method of the optical glass: An image sensor package, optical glass used therein, and a processing method of the optical glass are provided. The method includes defining a plurality of cutting paths on a piece of optical glass; grinding the piece of optical glass at the cutting paths to form a rough surface on each... Agent: Edwards & Angell, LLP

20070018310 - Semiconductor device and manufacturing method thereof: In a semiconductor device, a semiconductor element is mounted on a package substrate, and a heat dissipating member is laid above the semiconductor element and the package thereby sealing the semiconductor element. Resin is filled into the space defined by the semiconductor element, the package substrate, and the heat dissipating... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070018311 - Circuit board and light souce device having same: A circuit board comprises a substrate, a plurality of circuit islands, and a plurality of trenches. The circuit islands are formed on the substrate configured for mounting heat-generating devices thereon. The trenches are defined in the substrate configured for increasing a heat dissipation surface area of the substrate. Each of... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070018312 - Wiring substrate and semiconductor package implementing the same: A wiring substrate may have a first surface including a chip mounting pad, and a second surface opposite to the first surface. A heat radiating layer may be provided on the second surface of the wiring substrate. A plurality of heat conducting elements may connect the chip mounting pad to... Agent: Harness, Dickey & Pierce, P.L.C

20070018313 - Electronic parts packaging structure and method of manufacturing the same: In an electronic parts packaging structure of the present invention constructed by stacking a plurality of sheet-like units in a thickness direction, each of the units includes a first insulating layer, wirings formed on one surface of the first insulating layer, a semiconductor chip (electronic parts) connected to the wirings,... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070018314 - Semiconductor chip package and fabrication method thereof: A semiconductor chip package includes a first semiconductor chip, that is an MEMS chip having a movable structure. The movable structure has a movable section. The first semiconductor chip includes a plurality of first electrode pads, and a first sealing section. The first sealing section is a closed loop formed... Agent: Rabin & Berdo, PC

20070018315 - Conductive adhesive composition: A conductive adhesive composition includes a cross-linkable, adhesive component, a fluxing agent, and a conductive metal that has a surface on which is present a metal oxide. The adhesive component includes an epoxy resin and the fluxing agent includes a phenol. The phenol is reactive with the metal oxide on... Agent: Howard & Howard Attorneys, P.C.

20070018316 - Electrode, method for producing same and semiconductor device using same: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101,... Agent: Foley And Lardner LLP Suite 500

20070018317 - Semiconductor device: A semiconductor device, including: a semiconductor layer having an active region; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width smaller than the first width; an interlayer dielectric formed above... Agent: Harness, Dickey & Pierce, P.L.C

20070018319 - Ball grid array package and substrate within: A ball grid array (BGA) package includes a substrate and a chip. A bottom surface of the substrate includes a central area and a marginal area. Several source balls are disposed in the central area. Several ball groups are disposed in the marginal area. Each ball group includes one ground... Agent: Birch Stewart Kolasch & Birch

20070018318 - Means of integrating a microphone in a standard integrated circuit process: A means of integrating a microphone on the same integrated circuit die as other electronics in the system is disclosed. The structure is based on using solder bump technology to form a gap between an electrode on the silicon and another electrode. Charge is stored on the capacitor so when... Agent: Douglas G. Marsh

20070018321 - Multi-component integrated circuit contacts: An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070018320 - Semiconductor chip production method, semiconductor device production method, semiconductor chip, and semiconductor device: A semiconductor chip production method including the steps of: forming a front side recess in a semiconductor substrate; depositing a metal material in the front side recess to form a front side electrode electrically connected to a functional device formed on the front surface; removing a rear surface portion of... Agent: Rabin & Berdo, PC

20070018323 - Reduced inductance in ball grid array packages: Techniques are described for reducing inductance in ball grid array (BGA) packages for integrated circuits (ICs). The BGA package comprises a set of contacts disposed near an outer edge of the BGA package that receives signal lines and isolated power and ground lines. One area of excess parasitic inductance within... Agent: Shumaker & Sieffert, P. A.

20070018322 - Wafer level package and its manufacturing method: A semiconductor package includes a semiconductor die having a plurality of bond pads, a first protective layer formed at the periphery of the bond pads of the semiconductor die, UBM (Under Bump Metals) formed at the bond pads of the semiconductor die, a plurality of solder balls wetted to the... Agent: Serge J. Hodgson Gunnison, Mckay & Hodgson, L.L.P.

20070018324 - Wafer-level-chip-scale package and method of fabrication: A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and... Agent: Volentine Francos, & Whitt PLLC

20070018326 - Semiconductor device: A semiconductor device 1 includes a semiconductor substrate 10, insulating interlayer group 20 (first insulating interlayer group), insulating interlayer group 30 (second insulating interlayer group), and seal ring 40 (guard ring). The insulating interlayer group 20 is formed on the semiconductor substrate 10. The insulating interlayer group 30 is formed... Agent: Young & Thompson

20070018325 - Semiconductor device and method for fabricating the same: The semiconductor device includes an upper electrode line structure and a lower electrode line structure provided over a semiconductor substrate. The semiconductor device also includes a guard contact having a first portion and a second portion. The guard contact is disposed between the upper electrode line structure and the lower... Agent: Townsend And Townsend And Crew, LLP

20070018327 - Semiconductor integrated circuit device and process for manufacturing the same: In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070018329 - Interconnection having dual-level or multi-level capping layer and method of forming the same: An interconnection having a dual-level and multi-level capping layer and a method of forming the same. The interconnection may include an interlayer dielectric layer with a groove formed therein, a metal layer formed within the groove, a metal compound layer on the metal layer, a first barrier layer on the... Agent: Harness, Dickey & Pierce, P.L.C

20070018328 - Piezoelectric stress liner for bulk and soi: A preferred embodiment of the invention provides a semiconductor device. A preferred device comprises an n-channel transistor and a p-channel transistor disposed in a semiconductor body and a piezoelectric layer overlying the n-channel transistor and the p-channel transistor. In a preferred embodiment of the invention, the piezoelectric layer is biased... Agent: Slater & Matsil LLP

20070018330 - Semiconductor device and method of manufacturing the same: A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203... Agent: Reed Smith LLP

20070018331 - Dummy structures extending from seal ring into active circuit area of integrated circuit chip: An integrated circuit chip is provided, which includes an active circuit area, a seal ring structure, and a first dummy structure. The seal ring structure is formed at least partially around the active circuit area. The first dummy structure extends from the seal ring structure into the active circuit area.... Agent: Slater & Matsil, L.L.P.

20070018332 - Semiconductor device and method of manufacturing the same: The method of manufacturing a semiconductor device according to the present invention includes: forming an interconnect trench in an insulating film formed on a semiconductor substrate (S100) ; forming a barrier metal layer on the whole surface of the insulating film (S102); forming a copper layer on the whole surface... Agent: Young & Thompson

20070018333 - Semiconductor packaging device and manufacture thereof: A semiconductor packaging device comprises a carrier having at least a cavity/a slot thereon, at least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is... Agent: Lowe Hauptman Berner, LLP

20070018335 - Polygonal, rounded, and circular flip chip ball grid array board: A flip chip BGA board is disclosed, in which each of the corners of the board is removed to minimize warpage of the board due to heat applied during the manufacturing process. Embodiments of the invention allow the production of thin boards by preventing warpage of the board, and may... Agent: Staas & Halsey LLP

20070018334 - Security method for data protection: A method and device for data security including a printed circuit board and an integrated circuit each having a conductive trace layer shielded by a electrical shield layer. Tampering with either side of the device causes disturbance of a current flowing through a conductive trace layer used as an electrical... Agent: Schneck & Schneck

20070018336 - Stress and force management techniques for a semiconductor die: Stress and force management techniques for a semiconductor die to help compensate for stress within the semiconductor die and to help compensate for forces applied to the semiconductor die to minimize damage thereto.... Agent: Trask Britt

20070018337 - Method and apparatus for attaching microelectronic substrates and support members: A microelectronic package and method for forming such packages. In one embodiment, the package can be formed by providing a support member having a first surface, a second surface facing opposite the first surface, and a projection extending away from the first surface. A quantity of adhesive material can be... Agent: Perkins Coie LLP Patent-sea

20070018338 - Connection element for a semiconductor component and method for producing the same: A connection element is arranged on a connection area of a semiconductor component. The connection element includes at least one bonding wire portion fixed on the connection area. The connection area is covered by an electrically conductive material, the fixed bonding wire portion being surrounded or embedded by the electrically... Agent: Edell, Shapiro & Finnan, LLC

20070018340 - Integrated circuit pad with separate probing and bonding areas: A semiconductor device includes an integrated circuit and a pad coupled to the integrated circuit. The pad has a probing area and a bonding area, and a material of the pad has multiple heights from the probing area to the bonding area. Such heights allow for easy recognition for probing... Agent: Law Office Of Monica H Choi

20070018339 - Relay board and semiconductor device having the relay board: A relay board provided in a semiconductor package where a plurality of semiconductor chips are provided, the relay board relaying a wire for wiring the semiconductor chips or a wire for wiring a lead frame of the semiconductor package and the semiconductor chip, the relay board includes a plurality of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070018341 - Contact etching utilizing partially recessed hard mask: A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon layer is formed... Agent: Quintero Law Office

20070018342 - Devices with nanocrystals and methods of formation: An aspect relates to a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are created on a surface of the substrate. The creation of the nucleation sites includes implanting ions with an energy and a dose selected to provide a controllable distribution of... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070012905 - Novel phase change random access memory: A phase change memory device with a reduced phase change volume and lower drive current and a method for forming the same are provided. The method includes forming a bottom insulating layer comprising a bottom electrode contact, forming a bottom electrode film on the bottom electrode contact, forming an anti-reflective... Agent: Slater & Matsil, L.L.P.

20070012906 - Phase-change semiconductor device and methods of manufacturing the same: In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall... Agent: Harness, Dickey & Pierce, P.L.C

20070012907 - Doped semiconductor nanocrystal layers and preparation thereof: The present invention relates to a doped semiconductor nanocrystal layer comprising (a) a group IV oxide layer which is free of ion implantation damage, (b) from 30 to 50 atomic percent of a semiconductor nanocrystal distributed in the group IV oxide layer, and (c) from 0.5 to 15 atomic percent... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070012908 - Iii/v-semiconductor: The invention relates to a monolithic integrated semiconductor structure comprising a carrier layer on the basis of doped Si or doped GaP and a III/V semiconductor disposed thereupon and having the composition GaxInyNaAsbPcSbd, wherein x=70-100 mole-%, y=0-30 mole-%, a=0.5-15 mole-%, b=67.5-99.5 mole-%, c=0-32.0 mole-% and d=0-15 mole-%, wherein the total... Agent: Mayer & Williams PC

20070012910 - Semiconductor device including a channel with a non-semiconductor layer monolayer: A semiconductor device may include a semiconductor substrate, and at least one metal oxide semiconductor field-effect transistor (MOSFET) thereon. The MOSFET may include spaced-apart source and drain regions, a channel between the source and drain regions, and a gate overlying the channel defining an interface therewith. The gate may include... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070012909 - Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions: A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070012911 - Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance: A semiconductor device may include a substrate and spaced apart source and drain regions defining a channel region therebetween in the substrate. The substrate may have a plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with... Agent: Christopher F. Regan, Esquire Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.

20070012912 - Semiconductor device including a strained superlattice and overlying stress layer and related methods: A semiconductor device may include a strained superlattice layer including a plurality of stacked groups of layers, and a stress layer above the strained superlattice layer. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070012913 - Semiconductor device and production method thereof: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070012914 - Field effect transistor, method of producing the same, and method of producing laminated member: There is provided a field effect transistor having an organic semiconductor layer, including: an organic semiconductor layer containing at least porphyrin; and a layer composed of at least a polysiloxane compound, the layer being laminated on the organic semiconductor layer so as to be in intimate contact with the organic... Agent: Fitzpatrick Cella Harper & Scinto

20070012916 - Flat panel display and method for fabricating the same: A method for fabricating a flat panel display, comprising preparing an insulating substrate; forming separated source and drain electrodes on the insulating substrate to define a channel region; forming a first passivation layer on the source and drain electrodes; forming a metal layer having an opening corresponding to the channel... Agent: Macpherson Kwok Chen & Heid LLP

20070012915 - Organic light emitting display device: where R may be one selected from the group consisting of ethylene, an ethylene derivative, stilbene, a stilbene derivative. Also, R1 to R6 may be different from or equal to each other, and each is selected from the group consisting of a hydrogen atom, a halogen atom, a substituted or... Agent: Knobbe Martens Olson & Bear LLP

20070012917 - Pixel with transfer gate with no isolation edge: A pixel and imager device, and method of forming the same, where the pixel has a transfer transistor gate associated with a photoconversion device and is isolated in a substrate by shallow trench isolation. The transfer transistor gate does not overlap the shallow trench isolation region.... Agent: Dickstein Shapiro LLP

20070012920 - Flat panel display and method for fabricating the same: The invention provides a flat panel display having an insulating substrate; a data line formed on the insulating substrate; an interlayer insulating film formed on the data line having a first contact opening exposing the data line; a connecting member formed in a part of the first contact opening; an... Agent: Macpherson Kwok Chen & Heid LLP

20070012918 - Liquid crystal display device and optical film assembly for the liquid crystal display device: A liquid crystal display device is provided. The liquid crystal display device includes a liquid crystal display panel and an optical film assembly. The liquid crystal display panel includes two substrates and a liquid crystal layer disposed between the substrates, and has a plurality of multi-domains defined in a unit... Agent: F. Chau & Associates, LLC

20070012921 - Semiconductor device including semiconductor circuit made from semiconductor element and manufacturing method thereof: In the present invention, a semiconductor film is formed through a sputtering method, and then, the semiconductor film is crystallized. After the crystallization, a patterning step is carried out to form an active layer with a desired shape. The present invention is also characterized by forming a semiconductor film through... Agent: Eric Robinson

20070012919 - Thin film transistor substrate and method for fabricating the same: Provided are a thin film transistor (TFT) substrate and a method for manufacturing the same. The method comprises forming on a substrate a conductive layer, an impurity-doped silicon layer, and an intermediate layer, wherein the intermediate layer comprises intrinsic silicon; patterning the intermediate layer, the impurity-doped silicon layer, and the... Agent: Macpherson Kwok Chen & Heid LLP

20070012923 - Electronic circuit: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layer is less than 1500 Å, e.g., between 100 and 750 Å. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second... Agent: Nixon Peabody, LLP

20070012922 - Field effect transistor and display using same: The present invention provides a field effect transistor that includes a semiconductor layer (15) containing an organic substance, and a first electrode (16), a second electrode (12), and a third electrode (14) that are not in contact with each other at least electrically. The first electrode (16) is arranged above... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070012924 - Semiconductor device and method for manufacturing same: A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is... Agent: Sughrue Mion, PLLC

20070012926 - Display device with reduced number of wires and manufacturing method thereof: A display device with a decreased number of electrical lines and a method of making such display device are presented. The display device includes: a plurality of thin film transistors electrically connected to data wiring, wherein the data wiring includes a data line and a data electrode; a partition wall... Agent: Macpherson Kwok Chen & Heid LLP

20070012925 - Liquid crystal display panel with different substrate materials and method of making the liquid crystal display panel: An LCD panel with mixed substrate materials and a method of making the LCD panel are presented. The LCD panel is made of a first substrate, a second substrate disposed substantially parallel to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate.... Agent: Kieun "jenny" Sung Dla Piper Rudnick Gray Cary US LLP

20070012928 - Light emitting diode comprising semiconductor nanocrystal complexes and powdered phosphors: A white light light emitting diode (LED) formed by depositing an LED chip that emits light at a first wavelength and forming a semiconductor nanocrystal complex. The semiconductor nanocrystal complex absorbs at least a portion of the light emitted by the LED chip and emits light at a second wavelength.... Agent: Kenyon & Kenyon LLP

20070012929 - Nitride-based semiconductor light-emitting device and method of fabricating the same: A nitride-based semiconductor light-emitting device capable of stabilizing transverse light confinement is obtained. This nitride-based semiconductor light-emitting device comprises an emission layer, a cladding layer, formed on the emission layer, including a first nitride-based semiconductor layer and having a current path portion and a current blocking layer, formed to cover... Agent: Mcdermott Will & Emery LLP

20070012927 - Radiation-emitting optoelectronic semiconductor chip with a diffusion barrier: In a radiation-emitting optoelectronic semiconductor chip comprising an active layer (3) at least one p-doped layer (9) and a layer sequence (8) comprising a plurality of undoped layers (4, 5, 6, 7), which is arranged between the active layer (3) and the p-doped layer (9) and contains at least a... Agent: Thomas Langer

20070012930 - High brightness light-emitting device and manufacturing process of the light-emitting device: A light-emitting device comprises a multi-layer structure including one or more active layer configured to irradiate light in response to the application of an electric signal, a transparent passivation layer laid over an outmost surface of the multi-layer stack, a reflector layer laid over the passivation layer, and a plurality... Agent: David I. Roche And Daniel A. Tallitsch Baker & Mckenzie LLP

20070012931 - White semiconductor light emitting device: A white light semiconductor light emitting device includes a semiconductor LED and first and second phosphors provided on a light emitting region of the LED to emit light within a first wavelength range, which is different from that of light emitted from the LED, by absorbing a portion of the... Agent: Conley Rose, P.C.

20070012933 - Light emitting diode and method of fabricating the same: A light emitting diode (LED) and a method are provided for fabricating the a LED with an improved structure for better light emitting efficiency and better light output performance. The LED includes an n-GaN layer formed on a substrate to have a plurality of protrusions, thereby having an uneven surface,... Agent: Buchanan, Ingersoll & Rooney PC

20070012932 - Nitride semiconductor; light-emitting device, light-emitting diode, laser device and lamp using the semiconductor; and production methods thereof: An object of the present invention is to provide a nitride semiconductor product which causes no time-dependent deterioration in reverse withstand voltage and maintains a satisfactory initial reverse withstand voltage. The inventive nitride semiconductor product comprises an n-type layer, a light-emitting layer, and a p-type layer which are formed of... Agent: Sughrue Mion, PLLC

20070012934 - Method and system of led light extraction using optical elements: A light extraction plate can be used with a light emitting diode (LED) to efficiently extract and provide control over the spatial distribution of extracted light in terms of intensity and angle. The extraction plate can have millions of optical micro-elements and can be manufactured independently of the LED using... Agent: Michael K. Lindsey Gavrilovich, Dodd & Lindsey, LLP

20070012935 - Organic electroluminescent device: l

20070012936 - Silicophosphate-based phosphor and light-emitting device including the same: where 0<x≦0.2, 0≦y≦0.2, 0<a≦0.2, 0<b≦0.5, and 0<c≦0.5. The silicophosphate-based phosphor of Formula 1 is chemically and thermally stable and can be easily prepared. The phosphor exhibits a high luminous property when excited by a UV LED excitation light source having a wavelength of 360-420 nm, and emits light having a... Agent: Cantor Colburn, LLP

20070012939 - Flip chip light emitting diode and method of manufacturing the same: The present invention relates to a flip chip light emitting diode, in which the flow of current concentrated on a portion adjacent to an n-type electrode can be induced into the center of a light emitting section and a current-spreading effect is accordingly enhanced, thereby increasing light emission efficiency of... Agent: Mcdermott Will & Emery LLP

20070012937 - High-brightness light emitting diode having reflective layer: An LED structure is disclosed herein, which comprises, sequentially arranged in the following order, a light generating structure, a non-alloy ohmic contact layer, a metallic layer, and a substrate. As a reflecting mirror, the metallic layer is made of a pure metal or a metal nitride for achieving superior reflectivity.... Agent: Lin & Associates Intellectual Property

20070012941 - Light emitting diode comprising semiconductor nanocrystal complexes: A light emitting diode (LED) formed by depositing an LED chip and coupling a stability layer to the LED chip. Semiconductor nanocrystals are placed in a first matrix material to form a nanocrystal complex layer. The nanocrystal complex layer is deposited on top of the stability layer. A thickness of... Agent: Kenyon & Kenyon LLP

20070012938 - Light-emitting-diode packaging structure having thermal-electric element: A light-emitting-diode packaging structure having thermoelectric device, which is applied to the LED unit packaged using the flip chip technology. This is realized by directly building the thermoelectric elements into the solder bump layer of the light-emitting-diode packaging structure to replace a part of the solder bumps, as such raising... Agent: Harness, Dickey & Pierce, P.L.C

20070012940 - Wavelength-convertible light emitting diode package: The invention relates to a wavelength-convertible LED package including a package substrate having a lead frame, and an LED mounted on the package substrate and electrically connected to the lead frame. The wavelength-convertible LED package also includes a low refractive index region surrounding the LED, having a first refractive index,... Agent: Mcdermott Will & Emery LLP

20070012942 - Light emitting diode package with coaxial leads: The leads of a light emitting diode are made coaxial. The inner lead protrudes lower than the outer lead. The package is inserted into a spongy display panel for power supply. The display panel has three layers: a lower conducting layer for contacting said inner lead and a top conducting... Agent: Hung Chang Lin

20070012943 - Group iii nitride semiconductor substrate and manufacturing method thereof: A method of manufacturing a group III nitride semiconductor substrate includes the growth step of epitaxially growing a first group III nitride semiconductor layer on an underlying substrate, and the process step of forming a first group III nitride semiconductor substrate by cutting and/or surface-polishing the first group III nitride... Agent: Mcdermott Will & Emery LLP

20070012944 - Gan-based light emitting-diode chip and a method for producing same: An LED chip comprising an electrically conductive and radioparent substrate, in which the epitaxial layer sequence is provided on substantially the full area of its p-side with a reflective, bondable p-contact layer. The substrate is provided on its main surface facing away from the epitaxial layer sequence with a contact... Agent: Fish & Richardson PC

20070012945 - Semiconductor device and method for manufacturing semiconductor device: The present invention is to provide a semiconductor device including: a semiconductor layer that has a first-conductivity-type region, a second-conductivity-type region, a first-conductivity-type region, and a second-conductivity-type region that are adjacent to each other in that order; first and second electrodes that are connected to the first-conductivity-type region and the... Agent: Rader Fishman & Grauer PLLC

20070012946 - Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors: A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts... Agent: Merchant & Gould PC

20070012947 - Direct fet device for high frequency application: A source mounted semiconductor device package is described which includes a semiconductor die having first and second opposing major surfaces, first and second major electrodes disposed on respective major surfaces and a control electrode disposed on the second major surface, and a thin metal clip electrically connected to the first... Agent: Kourosh Salehi Ostrolenk, Faber, Gerb & Soffen, LLP

20070012948 - Combined apd / pin ingaas photodetector with microlens structure and method of manufacture: An InGaAs photodetector is provided having an avalanche photodiode (APD), a p-intrinsic-n (PIN) photodiode, and a microlens structure that provides high optical fill factors for both the APD and the PIN photodiodes. The photodetector can be used for both ranging and imaging applications, can be formed as a single pixel,... Agent: Michael R. Friscia Mccarter & English, LLP

20070012949 - Bipolar transistor and power amplifier: A base mesa finger (an emitter ledge layer 15, a base layer 16, and a collector layer 17) is interposed between two collector fingers (collector electrodes 13), and on the base mesa finger, a base finger (a base electrode 12) and two emitter fingers (an emitter layer 14 and an... Agent: Mcdermott Will & Emery LLP

20070012950 - Production of electronic devices: A method of producing a metal element of an electronic device on a substrate, including the steps of: forming a mixture of a material comprising metal atoms with a liquid, depositing the material from the liquid mixture onto a substrate, and then irradiating at least part of the deposited material... Agent: Sughrue Mion, PLLC

20070012951 - Semiconductor device: An improved electrostatic discharge (ESD) protection structure that is suitable for use in a large-scale CMOS circuit fabrication technology is disclosed. When surge energy enters the first conductor during an ESD event, the surge current is conducted through the first contacts of the first MOS transistors, the second contacts of... Agent: GlobalIPCounselors, LLP

20070012952 - Segmented magnetic shielding elements: A second shield layer, under the master shielding layer, is added to a segmented MRAM array. This additional shielding is patterned so as to provide one shield per bit slice. The placement of longitudinal biasing tabs at the ends of these segmented shields ensures that each segmented shield is a... Agent: Stephen B. Ackerman

20070012953 - Solid-state image sensing device driving method and solid-state image sensing apparatus: A method of driving a solid-state image sensing device comprises plural photoelectric conversion devices arranged in rows and columns perpendicular to the rows, VCCDs through which charges generated by the photoelectric conversion devices are transferred in the column direction, and an HCCD through which the charges transferred from the VCCDs... Agent: Birch Stewart Kolasch & Birch

20070012954 - Solid state image pickup device and endoscope: A solid state image pickup device includes: a semiconductor substrate; a well formed in a surface layer of the semiconductor substrate; a light reception region formed in the well and including a plurality of charge accumulation regions formed in a matrix shape and a plurality of vertical CCDs formed along... Agent: Sughrue Mion, PLLC

20070012955 - Organic and inorganic hybrid photoelectric conversion device: A photoelectric conversion device comprising: an inorganic photoelectric conversion film; and an organic photoelectric conversion film, wherein an insulating film between the inorganic photoelectric conversion film and the organic photoelectric conversion film has a thickness of from 1 to 6 μm, wherein the organic photoelectric conversion film has a multilayer... Agent: Sughrue Mion, PLLC

20070012956 - Phase change memory cell having nanowire electrode: A memory cell includes a first electrode comprising a nanowire, a second electrode, and phase-change material between the first electrode and the second electrode.... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070012957 - Electrode and method for making electrode: Disclosed is a gas permeable electrode comprising an electrocatalyst which is permeable to a reactant or reaction product, the electrocatalyst comprising particulate boron-doped diamond. There is also disclosed a method of making an electrocatalyst which is permeable to a reactant or reaction product, the method comprising the step of forming... Agent: Nixon & Vanderhye, PC

20070012958 - Distributed high voltage jfet: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions... Agent: Texas Instruments Incorporated

20070012959 - Memory device: The present invention is to provide a memory device including: a plurality of memory cells that each include a memory element having a memory layer and first and second electrodes that sandwich the memory layer, the plurality of memory cells being divided into memory blocks of m columns by n... Agent: Sonnenschein Nath & Rosenthal LLP

20070012960 - Direct channel stress: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming a strained channel region in semiconductor devices. Embodiments include forming a stressor layer over an amorphous portion of the semiconductor device at an intermediate stage of fabrication. The device is masked and strain in a portion... Agent: Slater & Matsil LLP

20070012961 - N-type carbon nanotube field effect transistor and method of fabricating the same: Provided are an n-type carbon nanotube field effect transistor (CNT FET) and a method of fabricating the n-type CNT FET. The n-type CNT FET may include a substrate; electrodes formed on the substrate and separated from each other; a CNT forrmed on the substrate and electrically connected to the electrodes;... Agent: Buchanan, Ingersoll & Rooney PC

20070012963 - Cmos image sensor and manufacturing method thereof: Disclosed are a CMOS image sensor and a manufacturing method thereof. The method includes the steps of: forming an isolation layer on a semiconductor substrate, defining an active region that includes a photo diode region and a transistor region; forming a gate in the transistor region, the gate including a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070012962 - Method for making image sensor with reduced etching damage: A method of forming a pixel of an image sensor with reduced etching damage is disclosed. The method first includes forming a light sensitive element in a substrate. Then, a transfer gate is formed atop the substrate and adjacent to the light sensitive element. A protective layer, such as an... Agent: Perkins Coie LLP

20070012966 - Image sensors and methods of fabricating same: Image sensor devices are provided having reduced dark current generation characteristics. These image sensor devices include a semiconductor substrate and a photo-detector therein (e.g., P-N photodiode). The photo-detector includes a charge-generating region therein that is configured to convert photons received by the photo-detector into charge carriers. A first transistor, which... Agent: Myers Bigel Sibley & Sajovec

20070012964 - Method and apparatus providing capacitor on an electrode of an imager photosensor: An imaging device having a pixel array in which one plate of a storage capacitor is coupled to a storage node while another plate is formed by an electrode of a photo-conversion region.... Agent: Dickstein Shapiro LLP

20070012965 - Photodetection system and module: One photodetection system includes a wide bandgap photodetector array which is physically and electrically integrated on a flexible interconnect layer including electrical connections, which is packaged in a manner for being electrically integrated with processing electronics such that the packaging and the processing electronics are configured for obtaining and processing... Agent: General Electric Company Global Research

20070012968 - Solid-state imaging device and camera: A solid-state imaging device is formed on a silicon substrate for providing a MOS type solid-state imaging device which has a device isolation structure and causes a small amount of leak current. The solid-state imaging device includes, for each pixel, an imaging region which includes a photodiode having a charge... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070012967 - Thin film transistor array panel and fabrication: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film... Agent: Macpherson Kwok Chen & Heid LLP

20070012969 - Transparent metal shielded isolation for image sensors: An isolation region formed in a substrate and lined with a transparent metal layer. The isolation region provides isolation between adjacent active areas of an integrated circuit structure, for example the inventive region may provide isolation between pixels of a pixel array. Utilizing a transparent material maintains high quantum efficiency... Agent: Dickstein Shapiro LLP

20070012971 - Cmos image sensor and manufacturing method thereof: Provided is a CMOS image sensor and a manufacturing method thereof. The CMOS image sensor includes a gate electrode, a photodiode, a transistor region, and a light blocking material. The gate electrode is formed on a semiconductor substrate with an intervening gate insulating layer. The photodiode region is formed on... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070012970 - Image sensor with soi substrate: An imager pixel utilizing a silicon-on-insulator substrate, a photodiode in said substrate below the buried oxide, and a dual contact to said photodiode and methods of forming said imager pixel. The photodiode has an increased fill factor due to its increased size relative to the pixel.... Agent: Dickstein Shapiro LLP

20070012975 - Coated conductors: Articles are provided including a base substrate having a layer of an IBAD oriented material thereon, and, a layer of barium-containing material selected from the group consisting of barium zirconate, barium hafnate, barium titanate, barium strontium titanate, barium dysprosium zirconate, barium neodymium zirconate and barium samarium zirconate, or a cubic... Agent: Los Alamos National Security, LLC

20070012978 - Junction-isolated depletion mode ferroelectric memory devices and systems: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells for memory devices and electronic systems. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb.... Agent: Leffert Jay & Polglaze, P.A.

20070012972 - Magnetic memory device: A magnetic memory device includes a magnetoresistive element and a first wiring layer. The magnetoresistive element includes a fixed layer, a recording layer, and a non-magnetic layer interposed therebetween. The first wiring layer extends in a first direction and generates a magnetic field for recording data in the magnetoresistive element.... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070012974 - Method for manufacturing material layer, method for manufacturing ferroelectric capacitor using the same, ferroelectric capacitor manufactured by the same method, semiconductor memory device having ferroelectric capacitor and manufacturing method thereof: Provided is a method for manufacturing a material layer capable of increasing the deposition rate of a noble metal layer on a ferroelectric layer, a method for manufacturing a ferroelectric capacitor using the same, a ferroelectric capacitor manufactured by the same method, and a semiconductor memory device having the ferroelectric... Agent: Harness, Dickey & Pierce, P.L.C

20070012976 - Semiconductor device and manufacturing method of the same: A seal ring (102) is formed in a manner to surround each ferroelectric capacitor (101). Additionally, a seal ring (103) is formed in a manner to surround a plurality of ferroelectric capacitors (101). Further, a seal ring (104) is formed in a manner to surround all of the ferroelectric capacitors... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070012977 - Semiconductor device and method for forming the same: A semiconductor device includes a MOS transistor having a capacitor-forming surface; and a ferroelectric capacitor formed on the capacitor-forming surface of the MOS transistor and including upper and lower electrode layers of Pt and a dielectric layer sandwiched between the upper and lower electrode layers. The ferroelectric capacitor has a... Agent: Ladas & Parry LLP

20070012973 - Semiconductor device having mim capacitor and manufacturing method thereof: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a... Agent: Foley And Lardner LLP Suite 500

20070012980 - Large-area nanoenabled macroelectronic substrates and uses therefor: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor... Agent: Nanosys Inc.

20070012979 - Nand flash memory device and method of fabricating the same: A NAND type flash memory device includes a semiconductor substrate, word lines, first and second selection lines, tunnel insulation layers, and selection gate insulation layers. The semiconductor substrate includes a memory transistor region and a selection transistor region. The word lines are arranged in the memory transistor region of the... Agent: F. Chau & Associates, LLC

20070012981 - Semiconductor memory device including multi-layer gate structure: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent... Agent: Frommer Lawrence & Haug

20070012982 - Multipurpose metal fill: The present invention adds a plurality of substrate barriers for reducing substrate noise. The barriers, consisting of a plurality of equally sized n-well regions formed within the p-substrate, are formed between the analog and digital portions and on at least one side of sensitive analog circuits. A MOSFET transistor configured... Agent: Garlick Harrison & Markison

20070012984 - Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same: A semiconductor device and its method of fabrication are provided. The semiconductor device includes a substrate, a patterning stop region, an insulating overlayer, a container region within the insulating overlayer, a charge storage lamina or conductive layer over an interior surface of the container region; a contact region defined by... Agent: Dinsmore & Shohl LLP

20070012983 - Terminations for semiconductor devices with floating vertical series capacitive structures: This invention relates to achieving high breakdown voltage and low on-resistance in semiconductor devices that have top, intermediate and bottom regions with a controllable current path traversing any of these regions. The device has an insulating trench that is coextensive with the top and intermediate regions and girds these regions... Agent: Lumen Intellectual Property Services, Inc.

20070012985 - Nanowire capacitor and methods of making same: A nanowire capacitor and methods of making the same are disclosed. The nanowire capacitor includes a substrate and a semiconductor nanowire that is supported by the substrate. An insulator is formed on a portion of the surface of the nanowire. Additionally, an outer coaxial conductor is formed on a portion... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20070012986 - Phase-change memory device including nanowires and method of manufacturing the same: a phase-change random access memory (PRAM) device including a plurality of nanowires and a method of manufacturing the same include: a lower structure including a plurality of contact plugs; the nanowires extending into the contact plugs from surfaces defining a respective terminal end of the contact plugs; and a phase-change... Agent: Cantor Colburn, LLP

20070012987 - Memory cell with selective deposition of refractory metals: Methods are provided for selective formation of oxidation-resistant caps for conductive plugs in semiconductor device fabrication. One embodiment of the present invention forms a sacrificial layer over a recessed polysilicon plug. The sacrificial layer is readily planarized using chemical mechanical planarization to isolate the cap within a recessed via. Then,... Agent: Knobbe Martens Olson & Bear LLP

20070012988 - High density nand non-volatile memory device: Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non-volatile memory cells with band engineered gate-stacks that are placed above or below the channel region in front-side or back-side charge trapping gate-stack configurations in NAND memory array architectures. The band-gap engineered gate-stacks with asymmetric or... Agent: Leffert Jay & Polglaze, P.A.

20070012989 - Nonvolatile semiconductor memory and fabrication method for the same: A nonvolatile semiconductor memory includes a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically separate the first and the second active area; a plurality of word lines configured to extend in the row direction and be... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070012990 - Nonvolatile semiconductor memory with transistor whose gate electrode has bird's beak: A nonvolatile semiconductor memory according to an example of the present invention is provided with a memory cell having a floating gate electrode and a control gate electrode, and a select gate transistor having a select gate electrode and connected in series to the memory cell. A cell unit is... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070012991 - Semiconductor memory device including multi-layer gate structure: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first-stepped portion is formed by etching the substrate adjacent to... Agent: Frommer Lawrence & Haug

20070012992 - Method for manufacturing and operating a non-volatile memory: A method for manufacturing and operating a nonvolatile memory in which a floating gate is formed on a silicon substrate to reduce the difference in heights between a memory region and a logic region so that a process margin is assured. The method includes forming first trenches having a designated... Agent: Marshall, Gerstein & Borun LLP

20070012993 - Non-volatile memory device, non-volatile memory cell thereof and method of fabricating the same: The present invention disclosed a non-volatile memory device and fabricating method thereof. The structure of non-volatile memory device at least comprises a substrate, several dielectric strips, several bit lines, a dielectrically stacking multi-layer, and several word lines. The substrate has several recesses. The dielectric strips are formed on the substrate,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070012994 - Semicondutor device and manufacturing method thereof: A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate structure,... Agent: Jianq Chyun Intellectual Property Office

20070012995 - Three-dimensional high voltage transistor and method for manufacturing the same: A method for manufacturing a three-dimensional high voltage transistor is disclosed. According to the method, lengths and widths of channels are increased while the reducing transistor forming area on plane, and semiconductor devices are completely separated from each other while restraining parasitic capacitance, latch-up phenomena, and formation of field transistors.... Agent: Marshall, Gerstein & Borun LLP

20070012996 - Vertical channel semiconductor devices and methods of manufacturing the same: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart... Agent: Robert W. Glatz Myers Bigel Sibley & Sajovee, P.A.

20070012998 - Semiconductor device: A semiconductor device has a semiconductor substrate, and a parallel p-n layer provided between the main surface and the back surface of the semiconductor substrate, and first-conductivity-type drift region and second-conductivity-type partition regions alternately arranged therein, wherein in the parallel p-n layer, the second-conductivity-type partition regions are periodically formed conforming... Agent: Young & Thompson

20070012997 - Transistor for semiconductor device and method of forming the same: Disclosed herein is a transistor for a semiconductor device and a method of forming the same. According to the present invention, a recess channel region is formed on a cell region to increase a channel length and a fin-type channel region is simultaneously formed on a peripheral circuit region to... Agent: Heller Ehrman White & Mcauliffe LLP

20070012999 - Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance: A method for making a semiconductor device which may include providing a substrate having a plurality of spaced apart superlattices therein, and forming source and drain regions in the substrate defining a channel region therebetween and with the plurality of spaced apart superlattices in the channel and/or drain regions. Each... Agent: Christopher F. Regan, Esquire Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.

20070013000 - Semiconductor device and manufacturing method of the same, and non-isolated dc/dc converter: In a low withstand voltage vertical trench MOSFET having an SJ structure, an N type epitaxial layer which is a current path and a trench structure which extends from a semiconductor surface into the N type epitaxial layer are provided, and a floating P type region is formed in a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070013001 - Epitaxial imprinting: The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar... Agent: Scully Scott Murphy & Presser, PC

20070013002 - Field effect transistor with a heterostructure and associated production method: A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x... Agent: Brinks Hofer Gilson & Lione

20070013003 - N-ary mask-programmable memory: The present invention discloses an N-ary mask-programmable memory (N-MPM). N-MPM cells can have N cell-states, with N>2. N-MPM cells could be geometry-defined, junction-defined, or both. Based on an nF-opening process (n≧1), partial-contacts with feature size<1F can be implemented with an nF-opening mask with feature size≧1F. N can be a non-integral... Agent: Dr.guobiao Zhang

20070013005 - Semiconductor device and method for manufacturing the same: A semiconductor device, comprises: a transistor having structured to include a gate electrode formed on a semiconductor layer on a semiconductor substrate via a gate insulating film, and a source layer and a drain layer formed on the semiconductor layer sandwiching the gate electrode; a hollow portion existing between the... Agent: Edwards & Angell, LLP

20070013004 - Tarp loading structure and method for using same: A building structure for covering a large object with a cover comprising: multiple frames, each frame being part of a building structure); at least one motor suspended from at least one of said plurality of frames and connected to one or more spools; and an arm lifting structure suspended from... Agent: The Bilicki Law Firm, PC

20070013006 - Apparatus and method of manufacture for integrated circuit and cmos device including epitaxially grown dielectric on silicon carbide: An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric... Agent: Lsi Logic Corporation

20070013007 - Semiconductor device and method of fabricating the same: A semiconductor device, comprising: a substrate; a floating body region formed in the substrate, a gate electrode formed above a first surface region of the floating body region via a gate insulating film, the gate electrode being connected to a word line; and source and drain regions, respectively, formed on... Agent: Foley And Lardner LLP Suite 500

20070013008 - Power ldmos transistor: An LDMOS device comprises a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. Source and drain regions of the first conductivity type are formed in the epitaxial layer along with a channel region of a second conductivity type formed therebetween. A... Agent: Duane Morris, LLPIPDepartment

20070013009 - Semiconductor device including i/o oxide and nitrided core oxide on substrate, and method of manufacture: A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070013010 - High performance mos device with graded silicide: A semiconductor device suffering fewer current crowding effects and a method of forming the same are provided. The semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying a portion of the substrate, a diffusion region in the substrate... Agent: Slater & Matsil, L.L.P.

20070013011 - Semiconductor device having guard ring and manufacturing method thereof: An interlayer insulation film is etched to form contact holes in an integrated circuit part. At this time, a trench is not formed in a guard ring part. Subsequently, ion implantation is carried out in source/drain regions in a peripheral circuit part for contact compensation, and high-temperature annealing is carried... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070013012 - Etch-stop layer structure: A semiconductor structure that includes a first gate structure, second gate structure and a nitrogen-containing etch-stop layer. The first gate structure whose sidewalls are bounded by at least one first spacer is formed on a semiconductor substrate. The second gate structure whose sidewalls are bounded by at least one second... Agent: Howard Chen Preston Gates & Ellis LLP

20070013013 - Semiconductor chemical sensor: A chemical sensor is provided that includes a semiconductor layer, an organic chemical layer disposed on a surface of the semiconductor layer, and a heating element configured to heat the semiconductor layer.... Agent: Caterpillar/finnegan, Henderson, L.L.P.

20070013014 - High temperature resistant solid state pressure sensor: A harsh environment transducer including a substrate having a first surface and a second surface, wherein the second surface is in communication with the environment. The transducer includes a device layer sensor means located on the substrate for measuring a parameter associated with the environment. The sensor means including a... Agent: Thompson Hine L.L.P.

20070013015 - Magnetoresistive effect element and magnetic memory: A magnetoresistive effect element includes a nonmagnetic layer having mutually facing first and second surfaces. A reference layer is provided on the first surface and has a fixed magnetization direction. A magnetization variable layer is provided on the second surface, has variable magnetization direction, and has a planer shape including... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070013016 - Method and structure for generating offset fields for use in mram devices: A method for generating an offset field for a magnetic random access memory (MRAM) device includes forming a first pinned layer integrally with a wordline, and forming a second pinned layer integrally with a bitline. An MRAM cell is disposed between the wordline and the bitline, the MRAM cell including... Agent: Cantor Colburn LLP - IBM Fishkill

20070013017 - Electro-optical circuitry having integrated connector and methods for the production thereof: A packaged electro-optic integrated circuit and a multi-fiber connector including an integrated circuit substrate, at least one optical signal providing element, at least one optical signal sensor, sensing at least one optical signal from the at least one optical signal providing element and at least one discrete reflecting optical element,... Agent: Darby & Darby P.C.

20070013018 - Imaging device and method of manufacture: An imaging chip is packaged in transparent injection molded material. The chip may have photosensitive elements arranged in a two-dimensional array on semiconductor material. Each element corresponds to a pixel of an image. The package may be formed of epoxy resin. In one aspect of the invention, the transparent plastic... Agent: Dickstein Shapiro LLP

20070013019 - Method of eliminating curl for devices on thin flexible substrates, and devices made thereby: A thin film semiconductor device such as a photovoltaic device is fabricated on a lightweight substrate material which is affixed to a layer of material which is in turn supported by a carrier. Following the fabrication of the device, the carrier is removed such as by an etching process, leaving... Agent: Gifford, Krass, Groh, Sprinkle & Citkowski, P.c

20070013020 - Reflector for a double-pass photodetector: An apparatus comprises: a substrate; a photodetector formed on an area of a surface of the substrate; an electrical contact formed on a portion of the photodetector; and a reflector formed over a portion of the photodetector distinct from the portion of the photodetector having the electrical contact formed thereon.... Agent: Christie, Parker & Hale, LLP

20070013022 - Semiconductor device and method for producing the same: A semiconductor device is configured that a high-withstand voltage semiconductor device (101) and logic circuits (201 and 301) are integrated on a single chip and that a high-withstand voltage high-potential island (402) including the high-potential-side logic circuit (301) is separated using multiple partition walls enclosing therearound. The semiconductor device is... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070013021 - Semiconductor device with a conduction enhancement layer: A semiconductor device includes a drift layer of a first conductivity type having a doping concentration and a conduction layer also of the first conductivity type on the drift layer that has a doping concentration greater than the doping concentration of the drift layer. The device also includes a pair... Agent: Koppel, Patrick & Heybl

20070013023 - Isolation structure configurations for modifying stresses in semiconductor devices: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as,... Agent: Blakely Sokoloff Taylor & Zafman

20070013024 - High-voltage transistor having shielding gate: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070013025 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes an insulation layer disposed in a fuse region of a substrate, a fuse including a conductive pattern disposed on the insulation layer and a metal pattern disposed in physical contact with the conductive pattern, the conductive pattern composed of a material that thermally explodes when... Agent: Marger Johnson & Mccollom, P.C.

20070013027 - Semiconductor device and method of manufacturing the same: In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are... Agent: James Hao, Esq. Wagner, Murabito & Hao, LLP

20070013028 - Semiconductor device and method of manufacturing the same: A semiconductor device 1 includes an interconnect 12, a conductive layer 14 (first conductive layer), an insulating layer 20 (first insulating layer), another conductive layer 30 (second conductive layer), another insulating layer 40 (second insulating layer), a via plug 52 (first via plug), and another via plug 54 (second via... Agent: Young & Thompson

20070013029 - Semiconductor device and mim capacitor: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070013026 - Varactor structure and method for fabricating the same: A varactor structure with high quality factor and good linearity, and a method for fabricating the same are disclosed. According to the method, an additional ion implantation is performed between a first electrode ion implantation and a second electrode ion implantation to form a high doped region. In other words,... Agent: North America Intellectual Property Corporation

20070013030 - Memory cell comprising one mos transistor with an isolated body having a reinforced memory effect: A memory cell with one transistor on a floating body region isolated by its lower surface by a junction. According to the present invention, the junction is non-planar and, for example, includes a protrusion directed towards the transistor surface.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070013031 - Vertical pnp transistor and method of making same: The present invention relates to a device structure located in a semiconductor substrate and containing high performance vertical NPN and PNP transistors. Specifically, the vertical PNP transistor has an emitter region, and the vertical NPN transistor has an intrinsic base region. The emitter region of the vertical PNP transistor and... Agent: Scully, Scott, Murphy & Pressner

20070013032 - Bipolar power transistor and related integrated device with clamp means of the collector voltage: A bipolar power transistor does not include integration of a Zener diode electrically connected between the base and collector for limiting the collector voltage. The power transistor is formed in a substrate, and includes an equalization diffusion and an auxiliary diffusion forming a P-N junction along a perimeter of the... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070013033 - Semiconductor apparatus and method of manufacturing the same: A semiconductor apparatus comprises a plurality of transistor devices including a control terminal being inputted with a control signal and a first and a second terminals that a current flows therein according to the control signal, and a plurality of substrate conductive portions each formed in a region different from... Agent: Mcginn Intellectual Property Law Group, PLLC

20070013034 - Semiconductor device and method for manufacturing the same: A semiconductor device consistent with the present invention includes a semiconductor substrate having a semiconductor chip region and a scribe region; a first insulating layer formed in the semiconductor chip region of the semiconductor substrate; a metal contact plug formed in the first insulating layer; a metal sidewall formed on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070013035 - Oxide interface with improved oxygen bonding: A deposition oxide interface with improved oxygen bonding and a method for bonding oxygen in an oxide layer are provided. The method includes depositing an M oxide layer where M is a first element selected from a group including elements chemically defined as a solid and having an oxidation state... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070013036 - Mems package using flexible substrates, and method thereof: A MEMS package and a method for its forming are described. The MEMS package has at least one MEMS device located on a flexible substrate. A metal structure surrounds the at least one MEMS device wherein a bottom surface of the metal structure is attached to the flexible substrate and... Agent: Stephen B. Ackerman

20070013037 - Monolithic integrated circuit with integrated interference suppression device: The invention discloses a monolithic integrated circuit with at least one signal connection carrying a signal and with an interference suppression device integrated in the circuit to reduce radiated interference. The interference suppression device has at least one stripline having a section whose beginning is coupled to the signal connection... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070013038 - Semiconductor package having pre-plated leads and method of manufacturing the same: A quad flat non-lead (QFN) package at least comprises a die, a lead frame and a molding compound. The lead frame comprises a plurality of L-shaped leads for electrically connecting the die. Two pre-plated conductive layers, formed on a bottom portion and a top portion of each L-shaped lead, are... Agent: Bacon & Thomas, PLLC

20070013039 - Package substrate and semiconductor package using the same: A package substrate may have an improved surface structure for controlling the flow of an adhesive. The package substrate may have an upper surface and a lower surface covered with a passivation layer. A window may be provided in, for example, the center of the package substrate. Sinks may be... Agent: Marger Johnson & Mccollom, P.C.

20070013040 - Packaging of a microchip device: The present invention is directed to an interposer for packaging a microchip device, which includes a plurality of electrical contacts on an outer side of the interposer, for electrically contacting the packaged microchip device and to be electrically connected with the microchip device. There is an aperture extending from the... Agent: Greenblum & Bernstein, P.L.C

20070013043 - Chip package without core and stacked chip package structure thereof: A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically... Agent: J.c. Patents, Inc.

20070013042 - Electronic module assembly with heat spreader: An electronic module assembly including a first substrate; a first semiconductor die mounted to a top surface of the first substrate; a second substrate located above the first semiconductor die and electrically and mechanically connected to the top surface of the first substrate; a second semiconductor die mounted to a... Agent: Harrington & Smith, LLP

20070013041 - Flexible wiring board and flex-rigid wiring board: The invention provides a flexible wiring board for repeated folding sections which exhibits excellent folding endurance, and a flex-rigid wiring board comprising the flexible wiring board as a section thereof. The flexible wiring board for repeated folding sections of the invention comprises a wiring patterned base film layer (11), a... Agent: Sughrue Mion, PLLC

20070013044 - Packaged integrated circuits and methods of producing thereof: A packaged integrated circuit and method for producing thereof, including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical... Agent: Tessera Lerner David Et Al.

20070013045 - Printed circuit board for thermal dissipation and electronic device using the same: A printed circuit board (PCB) for a package substrate of a multi-package module (MPM). The PCB comprises a substrate and a heat sink thereon. The heat sink comprises a first portion under the package substrate of the MPM. The heat sink further comprises a second portion adjacent to the first... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070013046 - Semiconductor substrate, method for producing it, and method for producing a circuit module: A semiconductor substrate and a method for producing it is disclosed. In one embodiment, a contact region and a corresponding contact material of the semiconductor substrate are formed, in regions or completely, with a protection against oxidation.... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070013047 - Enhanced pga interconnection: A pin grid array package, comprising a substrate, a chip mounted abutting said substrate, and a plurality of pins electrically connected to said substrate, each pin comprising a substantially flat disc at an end of the pin opposite the substrate, said disc oriented perpendicular to said pin. The substrate contains... Agent: Sam Tung Texas Instruments Incorporation

20070013048 - Electronic parts packaging structure and method of manufacturing the same: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070013049 - Interlayer insulating layer for printed wiring board, printed wiring board and method for manufacturing same: A printed wiring board is provided which includes an interlayer dielectric layer formed on a substrate from a curable resin having flaky particles dispersed therein. The printed wiring board is excellent in cooling/heating cycle resistance and packaging reliability while maintaining a satisfactory heat resistance, electrical insulation, heat liberation, connection reliability... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070013050 - Structure of an over-current protection device and method for manufacturing the same: This invention is novel structure of an over-current protection device and manufacturing method thereof. The over-current protection device is formed with a main body with a lead frame and a ceramic fiber lead wound by a metal wire exteriorly, by coating the exterior of the whole lead with a thermally-insulating... Agent: Ladas & Parry

20070013052 - Mems packaging method for enhanced emi immunity using flexible substrates: A MEMS package and methods for its embodiment are described. The MEMS package has at least one MEMS device mounted on a flexible and foldable substrate. A metal cap structure surrounds the at least one MEMS device wherein an edge surface of the metal cap structure is attached to the... Agent: George O. Saile

20070013051 - Multichip circuit module and method for the production thereof: A multichip circuit module includes a main board, at least one carrier substrate mounted on and in electrical contact with the main board, and at least one semiconductor chip arranged on the carrier substrate and in electrical contact therewith. The carrier substrate has at least one cavity on an assembly... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20070013053 - Semiconductor device and method for manufacturing a semiconductor device: A semiconductor device mountable to a substrate includes: a semiconductor die; an electrically conductive attachment region having a first attachment surface and a second attachment surface, the first attachment surface arranged for electrical communication with the semiconductor die; an interface material having a first interface surface and a second interface... Agent: Mayer & Williams PC

20070013054 - Thermally conductive materials, solder preform constructions, assemblies and semiconductor packages: A thermally conductive material that includes an alloy which includes indium, zinc, magnesium or a combination thereof is described herein. Also, a semiconductor package comprising a thermal interface material which includes solder and particles dispersed throughout the solder, the particles being of thermal conductivity greater than or equal to about... Agent: Sandra Poteat Thompson Buchalter Nemer, A Professional Law Corporation

20070013055 - Chip cooling: A thermionic or thermotunneling gap diode device consisting of two silicon electrodes maintained at a desired distance from one another by means of spacers. These spacers are formed by oxidizing one electrode, protecting certain oxidized areas and removing the remainder of the oxidized layer. The protected oxidized areas remain as... Agent: Borealis Techical Limited

20070013057 - Multicolor led assembly with improved color mixing: In accordance with the invention, a multicolor LED assembly with improved color mixing comprises an assembly of closely-packed LED dice of different colors packaged for high temperature operation and arranged to minimize same-color adjacency to promote color mixing. The assembly of dice is encapsulated in a dispersive medium such as... Agent: Patent Docket Administrator Lowenstein Sandler PC

20070013058 - Packaging chip having interconnection electrodes directly connected to plural wafers and fabrication method therefor: A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers... Agent: Sughrue Mion, PLLC

20070013056 - Tape wiring substrate and chip-on-film package using the same: A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film.... Agent: Harness, Dickey & Pierce, P.L.C

20070013059 - Semiconductor power module with sic power diodes and method for its production: A semiconductor power module has at least one power semiconductor chip (2) which can be controlled by the field effect and has a plurality of fail-safe, small-area SiC power diodes (D1 to D8). The function of a large-area SiC power diode chip which is susceptible to failure is distributed over... Agent: Baker Botts, L.L.P.

20070013060 - Stacked semiconductor package having adhesive/spacer structure and insulation: Stacked semiconductor assemblies in which a device such as a die, or a package, or a heat spreader is stacked over a first wire-bonded die. An adhesive/spacer structure is situated between the first wire-bonded die and the device stacked over it, and the device has an electrically non-conductive surface facing... Agent: Haynes Beffel & Wolfeld LLP

20070013061 - System, method and apparatus for improved electrical-to-optical transmitters disposed within printed circuit boards: The present invention provides a system, method and apparatus for improved electrical-to-optical transmitters (100) disposed within printed circuit boards (104). The heat sink (110, 200) is a thermal conductive material disposed within a cavity (102) of the printed circuit board (104) and is thermally coupled to a bottom surface (112)... Agent: Chalker Flores, LLP

20070013063 - Self alignment features for an electronic assembly: Some embodiments of the present invention relate to an electronic assembly that includes a substrate and a die. The electronic assembly further includes an alignment bump on one of the die and the substrate and a group of mating bumps on the other of the die and the substrate. The... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070013062 - Semiconductor device: A semiconductor device includes: a semiconductor substrate having a first face in which a hole is formed; an insulating section made of an insulating material, the insulating material accommodated in the hole; and a wire having a turning pattern and arranged on the insulating section.... Agent: Harness, Dickey & Pierce, P.L.C

20070013064 - Semiconductor device and electronic apparatus: External connection terminals 27 which are electrically connected to semiconductor chips 11-1, 11-2, 12-1, 12-2 and also protrude beyond the semiconductor chips 11-1, 11-2, 12-1, 12-2 are disposed on a substrate 13 of the side to which the plural semiconductor chips 11-1, 11-2, 12-1, 12-2 are connected.... Agent: Rankin, Hill, Porter & Clark LLP

20070013067 - Electronic component mounting method and apparatus: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is... Agent: Wenderoth, Lind & Ponack L.L.P.

20070013065 - Semiconductor device: A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first... Agent: Harness, Dickey & Pierce, P.L.C

20070013066 - Semiconductor package and fabrication method thereof: A semiconductor package and a fabrication method thereof are provided. The fabrication method includes the steps of preparing a chip having a plurality of conductive bumps formed on an active surface thereof; preparing a tape having a first surface and an opposed second surface, wherein the tape has a plurality... Agent: Birch Stewart Kolasch & Birch

20070013068 - Integrated circuit package and method with an electrical component embedded in a substrate via: An integrated circuit package and method exploit the volume enclosed by the package substrate vias. In one embodiment, an integrated circuit package includes a first substrate having electrically conductive layers formed on substantially parallel surfaces of the first substrate, a second substrate having electrically conductive layers formed on substantially parallel... Agent: Lsi Logic Corporation

20070013074 - Integrated circuit device and electronic instrument: An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects for supplying a first power supply voltage to a plurality of memory cells are provided in a metal interconnect layer in which a plurality of bitlines are formed; wherein a second power supply interconnect... Agent: Oliff & Berridge, PLC

20070013072 - Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof: A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level... Agent: Schmeiser, Olsen & Watts

20070013073 - Method and structure for reduction of soft error rates in integrated circuits: A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the... Agent: Schmeiser, Olsen & Watts

20070013075 - Modular containment structure: A modular containment system which has a plurality of stackable building elements, including two or more peripheral sidewall members, a roof and a base. Means are provided for coupling each of the building elements to an adjoining building element. The building elements are stacked such that the two or more... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20070013071 - Probing pads in kerf area for wafer testing: A structure and a method for forming the same. The structure includes (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a bond pad electrically connected to a transistor of the integrated circuit; (c) a protection ring... Agent: Schmeiser, Olsen & Watts

20070013076 - Semiconductor device and method of manufacturing thereof: A first conductive layer and a second conductive layer are formed on an upper surface of a semiconductor substrate. The second conductive layer formed at a higher location than the first conductive layer. An insulating film is formed over the semiconductor substrate to cover the first conductive layer and the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070013070 - Semiconductor devices and methods of manufacture thereof: Novel etch stop layers for semiconductor devices and methods of forming thereof are disclosed. In one embodiment, an etch stop layer comprises tensile or compressive stress. In another embodiments, etch stop layers are formed having a first thickness in a first region of a workpiece and at least one second... Agent: Slater & Matsil, L.L.P.

20070013069 - Wiring structure and method for manufacturing the same: A multilayer wiring structure for connecting a semiconductor device is disclosed which is obtained by forming metal wirings on a substrate in which the semiconductor device is formed. The wiring structure free from such conventional problems that insulation between wirings next to each other is damaged or insulation resistance between... Agent: Sughrue Mion, PLLC

20070013078 - Wire structure, method for fabricating wire, thin film transistor substrate, and method for fabricating thin film transistor substrate: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate, and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper nitride and a copper conductive layer formed on the barrier layer... Agent: Macpherson Kwok Chen & Heid LLP

20070013077 - Wire structure, method of forming wire, thin film transistor substrate, and method of manufacturing thin film transistor substrate: Provided are a wire structure, a method of forming a wire, a thin film transistor (TFT) substrate, and a method of manufacturing the TFT substrate. The wire structure includes a barrier layer disposed on a lower structure, a copper conductive layer comprising copper or copper alloy disposed on the barrier... Agent: F. Chau & Associates, LLC

20070013079 - Die pad arrangement and bumpless chip package applying the same: A bumpless chip package including at least a chip and an interconnection structure is provided. Wherein, the chip has a die pad arrangement disposed on an active surface of the chip. The die pad arrangement includes a plurality of point-shaped pads and at least a non-point-shaped pad. The area of... Agent: J.c. Patents, Inc.

20070013081 - Electronic module with stacked ic chip structure: The invention relates to an electronic module with a plurality of IC chips staked densely. The electronic module includes a substrate with an electrode formed thereon and at least one spacer disposed on the substrate. The electronic module also includes an IC chip disposed on the spacer and electrically connected... Agent: Lowe Hauptman Berner, LLP

20070013082 - Semiconductor device and method for manufacturing semiconductor device: A disclosed semiconductor device comprises a substrate, an element on the substrate and a sealing structure for sealing the element. The sealing structure has a structure such that a partition wall made of a metallic material formed on the substrate by a plating method so as to surround the element... Agent: Ladas & Parry LLP

20070013080 - Voltage regulators and systems containing same: A voltage regulator on a first chip is embedded in a core. The voltage regulator on a chip and the core are part of an integral package. The package can include a microelectronic device on a second chip. The voltage regulator is disposed on a bumpless, build-up layer structure. The... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070013084 - Bumped die and wire bonded board-on-chip package: An apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a first surface and a second surface with at least one opening therethrough. The die includes an active surface and a back surface, wherein the die is attached face... Agent: Trask Britt, P.C.

20070013083 - Semiconductor device and a manufacturing method of the same: Improvement in the mountability of a semiconductor device is aimed at. By preparing a package substrate which has a plurality of lands of NSMD structure, and the taking-out wiring and dummy wiring which were connected to each of the lands, and have been arranged mutually in the location of 180°... Agent: Miles & Stockbridge PC

20070007505 - Chalcogenide pvd components: A chalcogenide PVD component includes a bonded mixture of particles of a first solid and a second solid. The first solid contains a first compound. The particle mixture may exhibit a minimum solid phase change temperature greater than a solid phase change phase temperature of an element in the first... Agent: Wells St. John P.s.

20070007506 - Layered resistance variable memory device and method of fabrication: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to one embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between two glass layers, wherein at least... Agent: Dickstein Shapiro LLP

20070007507 - Single photon source: Microcavity comprising two reflectors, at least one semiconductor layer separating said reflectors and a semiconductor quantum well wherein at least one of said reflectors and of said at least one semiconductor layer comprises a structure which is adjusted to localize a polariton in said microcavity.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070007508 - Semiconductor device including a strained superlattice layer above a stress layer: A semiconductor device may include a stress layer and a strained superlattice layer above the stress layer and including a plurality of stacked groups of layers. More particularly, each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070007509 - Strained semiconductor structures: A method for in situ formation of low defect, strained silicon and a device formed according to the method are disclosed. In one embodiment, a silicon germanium layer is formed on a substrate, and a portion of the silicon germanium layer is removed to expose a surface that is smoothed... Agent: Intel/blakely

20070007512 - Bio-inorganic conjugates: A method for producing a bio-inorganic conjugate is provided comprising supplying a plurality of inorganic particles that are axially anisotropic; and positioning biomolecules intermediate the particles to form a chain-like structure. Also provided is an organized microscopic structure capable of vectorial electron transport within the structure, comprising a plurality of... Agent: Cherskov & Flaynik

20070007517 - Cavity ball grid array apparatus having improved inductance characteristics: A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically conductive adhesive layer. Bond... Agent: Trask Britt, P.C.

20070007516 - Composite material and light emitting element, light emitting device, and electronic device using the composite material: The present invention provides a composite material in which an organic compound and an inorganic compound are composited, which is superior in conductivity, a composite material which is superior in a property of injecting carriers to an organic compound, and a composite material having low resistance with metal. Further, the... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070007515 - Flat panel display and method of fabricating the same: A flat panel display apparatus includes a gate insulating layer having openings which define pixels. The flat panel display apparatus includes: a substrate; a source electrode and a drain electrode formed on the substrate; a semiconductor layer contacting the source electrode and the drain electrode; a gate formed on the... Agent: Robert E. Bushnell

20070007514 - Method for contacting semiconductor components with a test contact: A method for contacting an external contact area with a test contact is provided. The external contact area has a galvanically applied coating of a metal or a metal alloy. Before the contact is established between the external contact area and the test contact, the external contact area is wetted... Agent: Edell, Shapiro & Finnan, LLC

20070007511 - Nanoparticle thin film, method for dispersing nanoparticles and method for producing nanoparticle thin film using the same: A nanoparticle thin film, a method for dispersing nanoparticles and a method for producing nanoparticle thin film using the same. The method for dispersing nanoparticles may include modifying the surface of nanoparticles with a charged material, drying the surface-modified nanoparticles under vacuum and/or dispersing the dried nanoparticles in a solvent.... Agent: Harness, Dickey & Pierce, P.L.C

20070007513 - Organic electrically bistable material and its use for producing a memory switch: n

20070007510 - Stackable memory device and organic transistor structure: In the present electronic structure, a first electronic device includes a first pair of electrodes and an active layer between the first pair of electrodes. An organic transistor is made up of organic material, a source, a drain, and a gate, one of the first pair of electrodes being connected... Agent: Paul J. Winters

20070007518 - Encapsulation of nano-dimensional structures by oxidation: This invention relates to a method of encapsulating nano-dimensional structures, comprising: depositing at least one material upon a substrate such that the material includes at least one portion; and creating an oxidized layer located substantially adjacent to the deposited material such that the at least one portion of the deposited... Agent: Hewlett Packard Company

20070007520 - Display substrate, method of manufacturing the same and display apparatus having the same: A display substrate includes a plastic substrate, a gate wiring, a gate insulation layer, an active layer, a data wiring and a drain wiring. The gate wiring includes a gate line and a gate electrode portion that is electrically connected to the gate line. The active layer is formed on... Agent: Macpherson Kwok Chen & Heid LLP

20070007519 - Failure prediction for parallel mosfets: Power conversion circuits often consist of several MOSFETs operating in parallel. Due to thermal cycling and mechanical operations, MOSFETs or the respective electric connections of the MOSFETs may fail. According to the present invention, there is provided a diagnosis circuit for a plurality of parallel MOSFETs, which predicts or determines... Agent: Philips Intellectual Property & Standards

20070007521 - Semiconductor device and test method of semiconductor device: There is provided a semiconductor device comprising, a function unit portion including a circuit element, rank data presenting results of a rank-classification test on the circuit element, the rank-classification test being performed on the basis of a plurality of test criteria on wafer state, a non-volatile memory portion in which... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070007522 - Thin film transistor and method of forming the same: A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a source/drain is provided. The gate is disposed over a substrate, wherein the gate comprises at least one molybdenum-niobium alloy nitride layer. The gate insulating layer is formed over the substrate to cover the gate.... Agent: Jianq Chyun Intellectual Property Office

20070007523 - Active matrix substrate: An active matrix substrate includes a substrate, pixel units, driving lines, and an electrostatic discharge protection circuit. The substrate has an active region and a peripheral region. The pixel units are arranged to form a matrix inside the active region. The driving lines are inside the active region and the... Agent: Jianq Chyun Intellectual Property Office

20070007526 - Display panel and display device: The proceeding of peeling of a conductive layer in the vicinity of terminals is prevented. A display panel includes a conductive layer extending to the outside of terminals, and the conductive layer has slits extending in directions from one end face to the other end face alternately at two end... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070007527 - Light emitting device, driving method for the same and electronic apparatus: It is a problem to provide a light-emitting device capable of obtaining a constant brightness without being affected by deterioration in an organic light-emitting layer or temperature change, and of making desired color display. The lowering in OLED brightness due to deterioration is reduced by causing the OLED to emit... Agent: Fish & Richardson P.C.

20070007525 - Liquid crystal display with wide viewing angle: A liquid crystal display (LCD) capable of preventing texture, light leakage, and/or formation of an instantaneous afterimage while improving an aperture ratio is presented. The LCD includes a first insulating substrate, a gate line formed on the first insulating substrate, a data line insulated from the gate line and extending... Agent: Macpherson Kwok Chen & Heid LLP

20070007528 - Thin film transistor in which fluctuations in current flowing therethrough are suppressed, and image display apparatus: A thin film transistor according to the present invention includes a gate electrode, a semiconductor layer having a channel forming region arranged on the gate electrode and an impurity region arranged on a part of the channel forming region, source and drain electrodes electrically connected to the impurity region, and... Agent: Birch Stewart Kolasch & Birch

20070007524 - Thin film transistor plate and method of fabricating the same: A thin film transistor (TFT) plate having improved processing efficiency without degradation in performance and a method of fabricating the TFT plate are provided. The TFT plate includes gate insulating layer patterns made of dual layers. Upper portions of both sidewalls of an upper gate insulating layer pattern are substantially... Agent: Macpherson Kwok Chen & Heid LLP

20070007529 - Semiconductor device and method for forming the same: A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of... Agent: Nixon Peabody, LLP

20070007531 - Semiconductor device and manufacturing method thereof: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, a first gate insulating layer, a second gate insulating layer, a first gate electrode, and a second gate electrode. The semiconductor substrate is divided into a first region and a second region. The... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070007530 - Thin-film transistors with metal source and drain and methods of fabrication: A thin-film transistor includes a source and a drain that have each been replaced with a metal by a heat-treatment at a temperature within the range of 250° C. and 500° C.... Agent: Cooper & Dunham, LLP

20070007532 - Stacked semiconductor device and related method: A stacked semiconductor device and a method for manufacturing the stacked semiconductor device are disclosed. The stacked semiconductor device comprises a seed layer doped with first impurities, a multilayer insulation pattern disposed on the seed layer comprising at least two insulation interlayer patterns stacked vertically on the seed layer and... Agent: Volentine Francos, & Whitt PLLC

20070007534 - Optical mask, method of manufacturing thin film transistor array substrate, and thin film transistor array substrate manufactured by the method: Provided are an optical mask, a method of manufacturing a thin film transistor array substrate using the optical mask, and a thin film transistor array substrate manufactured by the method. The method includes forming a data metal layer on a substrate, forming an insulating layer on the data metal layer,... Agent: Cantor Colburn, LLP

20070007533 - Pixel array strcuture: A pixel array structure is provided. The pixel array structure comprises a plurality of pixel units and a plurality of dielectric walls. Each dielectric wall is disposed between two neighboring pixel units, wherein each pixel unit comprises at least one organic light emitting diode and a complementary metal-oxide-semiconductor (CMOS). The... Agent: Jianq Chyun Intellectual Property Office

20070007535 - Pixle circuit system for a light emitting display: A pixel circuit for driving a plurality of pixel units within a display includes: a plurality of scanning lines formed within the display for transmitting scanning signals to the pixel units; a plurality of data lines formed within the display and transversely crossing the scanning lines for transmitting data signals... Agent: Birch Stewart Kolasch & Birch

20070007536 - Thin film magnetic memory device capable of conducting stable data read and write operations: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic... Agent: Mcdermott Will & Emery LLP

20070007537 - Semiconductor device: A semiconductor device comprises: a first semiconductor layer of silicon carbide of a first conductivity type; a second semiconductor layer of silicon carbide of a second conductivity type selectively provided on the first semiconductor layer; a main electrode layer of silicon carbide of the first conductivity type selectively provided on... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070007538 - Light-emitting device, method for producing same, and display: Disclosed herein is a light-emitting device comprising a transparent or semi-transparent first substrate, a second substrate provided opposite to the first substrate, a transparent or semi-transparent first electrode provided on the first substrate, a second electrode provided on the second substrate so as to be opposite to the first electrode,... Agent: Panasonic Patent Center C/o Mcdermott Will & Emery LLP

20070007539 - Light emitting diode module, backlight assembly and display device provided with the same: The present invention relates to a light emitting diode module, as well as a backlight assembly and a display device including the same. The light emitting diode module according to an exemplary embodiment of the present invention includes a printed circuit board having a plurality of junction holes, a plurality... Agent: Cantor Colburn, LLP

20070007540 - Light-emitting device: A light-emitting device (200) has a submount (100) and a plate for heat transfer (300) having a metallic plate (30). The submount (100) has a mount base (10), at least one light-emitting diode chip (5) mounted thereon and electrically conducting lines (12-17) formed on the mount base (10) to be... Agent: Greenblum & Bernstein, P.L.C

20070007541 - White light emitting device: The invention relates to a nitride light emitting device including first and second conductivity type nitride layers and a plurality of active regions emitting light of different wavelength. The active regions are sequentially formed between the first and the second conductivity type nitride layers. The active regions include at least... Agent: Volpe And Koenig, P.C.

20070007543 - Semiconductor light emitting device and manufacturing method therefor: A semiconductor light emitting device in the present invention is formed by laminating an epitaxial layer 30 including an AlGaInP active layer and a second wafer 23 which transmits light derived from the active layer. The crystal axes of the epitaxial layer 30 and the second wafer 23 are generally... Agent: Nixon & Vanderhye, PC

20070007542 - White-light emitting device: High-output white light emitting devices that, being unsusceptible to deterioration despite large drive power, are usable in lighting applications. The light-emitting devices are formed by combining a phosphor component (4) with an LED (2, 3). The phosphorescent component (4) is selected from materials in which the relation between thermal conductivity... Agent: Judge & MurakamiIPAssociates

20070007544 - Semiconductor devices having self aligned semiconductor mesas and contact layers: Methods of forming a semiconductor device can include forming a semiconductor structure on a substrate, the semiconductor structure having mesa sidewalls and a mesa surface opposite the substrate. A contact layer can be formed on the mesa surface wherein the contact layer has sidewalls and a contact surface opposite the... Agent: Myers Bigel Sibley & Sajovec

20070007545 - Devices with adjustable dual-polarity trigger- and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal cmos/bicmos integrated circuits: Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A... Agent: Min, Hsieh & Hack LLP

20070007546 - Semiconductor gas sensor and method for manufacturing the same: The gate insulating film is a film stack including at least an SiO2 film and an SRN (Si-rich nitride) film. The SRN film functions as a etching stopper film when the gate insulating film is exposed by etching of an inter-layer insulating film. Pressure resistance of the gate insulating film... Agent: Stanley P. Fisher Reed Smith LLP

20070007547 - Iii-nitride enhancement mode devices: A III-nitride power semiconductor device that includes a gate barrier under the gate thereof, and a method for fabricating the device.... Agent: Ostrolenk Faber Gerb & Soffen

20070007549 - Master slice type semiconductor integrated circuit device: A plurality of terminals is formed in a basic cell. One terminal has first to fifth patterns. The first and second patterns are arranged to be spaced from each other. The third and fourth patterns are arranged to be spaced from each other, and are arranged so as to be... Agent: Banner & Witcoff, Ltd., Attorneys For Reserve Attorneys For Client No. 000449, 001701

20070007548 - Method of forming nitride films with high compressive stress for improved pfet device performance: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited... Agent: International Business Machines Corporation Dept. 18g

20070007550 - Semiconductor device and manufacturing method thereof: A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate and the second gate line of a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070007551 - Semiconductor integrated circuit: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070007552 - Self-aligned dual stressed layers: Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a latter deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited... Agent: Hoffman, Warnick & D'alessandro LLC

20070007553 - Memory device: An object of the present invention is to provide, in an FeRAM memory device fixed to a cell plate, a memory device in which RES_N (source line) of a reset transistor for resetting a storage node has a low resistance. A memory cell (101) includes a ferroelectric capacitance, a first... Agent: Steptoe & Johnson LLP

20070007554 - Display device: The present invention relates to a display device, such as an organic electroluminescent device, for preventing corrosion of a signal line. A display device according to the present invention, comprising a substrate; a first electrode layer disposed over the substrate; a second electrode layer disposed to cover the first electrode... Agent: Fleshner & Kim, LLP

20070007555 - Ccd charge-splitter adjustment by static charge gradient: A charge splitter for separating an incoming charge packet into two outgoing packets while the charge is in a static state, i.e., not while it is flowing down a channel or over a barrier. A splitting gate may have a biasing charge impressed upon it, such as via the application... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070007556 - Backside-illuminated photodetector: The present invention provides a back illuminated photodetector having a sufficiently small package as well as being capable of suppressing the scattering of to-be-detected light. A back illuminated photodiode 1 comprises an N-type semiconductor substrate 10, a P+-type doped semiconductor region 11, a recessed portion 12, and a coating layer... Agent: Drinker Biddle & Reath (dc)

20070007557 - Gate driver circuit and display device having the same: A gate driver circuit includes a driving section and a wiring section. The wiring section receives a plurality of signals from an external device. The driving section includes a plurality of stages providing a plurality of gate lines with a gate signal. The wiring section includes first and second signal... Agent: Cantor Colburn, LLP

20070007559 - Image sensors including active pixel sensor arrays: In one aspect, an image sensor is provided which includes an array of unit active pixels. Each of the unit active pixels comprises a first active area including a plurality of photoelectric conversion regions, and a second active area separated from the first active area. The first active areas are... Agent: Volentine Francos, & Whitt PLLC

20070007558 - Light emitting diode package and method for making same: A light emitting diode (LED) package for high temperature operation which includes a printed wire board and a heat sink. The LED package may include a formed heat sink layer, which may be thermally coupled to an external heat sink. The printed wire board may include apertures that correspond to... Agent: Patent Docket Administrator Lowenstein Sandler PC

20070007560 - Metal-substituted transistor gates: One aspect of this disclosure relates to an integrated circuit structure. An integrated circuit structure embodiment includes a substrate, a gate dielectric over the substrate, a carbon structure having a predetermined thickness in contact with and over the gate dielectric, and a layer of desired gate material for a transistor... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070007561 - Discharge circuit for a word-erasable flash memory device: A non-volatile memory device is proposed. The memory device includes a plurality of blocks of memory cells, each block having a common biasing node for all the memory cells of the block, biasing means for providing a biasing voltage, and selection means for selectively applying the biasing voltage to the... Agent: Graybeal Jackson Haley LLP Suite 350

20070007562 - Image sensor and method for fabricating the same: An image sensor includes a first conductivity type substrate with a trench formed in a predetermined portion thereof, a second conductivity type impurity region formed in the first conductivity type substrate below the trench and being a part of a photodiode, a second conductivity type first epitaxial layer filling the... Agent: Morgan Lewis & Bockius LLP

20070007563 - Silicon-based resonant cavity photodiode for image sensors: An imager with pixels having a resonant-cavity photodiode. The resonant cavity photodiode increases absorption of light having long wavelengths. A trench is formed for the photodiode and reflective film is grown on the bottom of the trench. The reflective film reflects light that is not initially absorbed back to the... Agent: Dickstein Shapiro LLP

20070007568 - Field-effect transistor: The field-effect transistor includes: a ferromagnetic layer, having a film thickness of 50 nm or less, which is made of a Ba—Mn oxide showing ferromagnetism at 0° C. or higher; a dielectric layer made of a dielectric material or a ferroelectric material, and the ferromagnetic layer and the dielectric layer... Agent: Harness, Dickey & Pierce, P.L.C

20070007565 - Integration of capacitive elements in the form of perovskite ceramic: The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070007564 - Semiconductor device and method for fabricating the same: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including... Agent: Panasonic Patent Center C/o Mcdermott Will & Emery LLP

20070007566 - Semiconductor device having silicide film and method of manufacturing the same: A semiconductor device having a semiconductor substrate, a SRAM area formed in the semiconductor substrate, the SRAM area having first transistors, the first transistor having a metallic compound film formed on each of a source and a drain regions of the first transistor, and a logic circuit area formed in... Agent: SprinkleIPLaw Group

20070007569 - Semiconductor memory device comprising magneto resistive element and its manufacturing method: A semiconductor memory device including a memory cell having a first ferromagnetic film, a tunnel barrier film formed on the first ferromagnetic film, and a second ferromagnetic film formed on the tunnel barrier film, the tunnel barrier film having a larger film thickness in its in-surface edge portion than in... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070007567 - Semiconductor substrate and production process thereof: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070007570 - Semiconductor device: A semiconductor device has an N type diffusion layer between an insulating layer formed on the surface of a trench and an N type semiconductor region. An N type impurity is diffused in the N type diffusion layer so as to have a concentration gradient in a direction that connects... Agent: Howard & Howard Attorneys, P.C.

20070007572 - Capacitor fabrication methods and capacitor constructions: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at... Agent: Wells St. John P.s.

20070007571 - Semiconductor device with a buried gate and method of forming the same: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under... Agent: Slater & Matsil LLP

20070007573 - Controlled equivalent series resistance capacitor: Some embodiments of the present invention include capacitors with controlled equivalent series resistance.... Agent: Blakely Sokoloff Taylor & Zafman

20070007576 - Multi-bit storageable non-volatile memory device: A non-volatile memory device includes a channel region defined between a source region and a drain region, a charge storage film disposed on the channel region to store a charge, and a tunnel insulating film interposed between the channel region and the charge storage film to tunnel the charge, the... Agent: F. Chau & Associates, LLC

20070007575 - Nonvolatile memory cell with multiple floating gates formed after the select gate: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation... Agent: Macpherson Kwok Chen & Heid LLP

20070007574 - Semiconductor memory device and driving method of the same: A semiconductor memory device includes a semiconductor substrate including a semiconductor layer on a first insulation film; a memory cell including a source and a drain formed in the semiconductor layer, and a floating body region provided between the source and the drain, the memory cell storing data according to... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070007577 - Integrated circuit embodying a non-volatile memory cell: An integrated circuit is provided including at least one memory cell. Such memory cell, in turn, includes a transistor and a capacitor. The transistor includes a source, a drain, and a gate. Further, the capacitor includes a well and a gate. The gate of the transistor remains in communication with... Agent: Zilka-kotab, PC

20070007579 - Memory cell comprising a thin film three-terminal switching device having a metal source and /or drain region: A nonvolatile memory cell comprising a switchable resistor memory element and a thin-film three-terminal switching device, preferably a MOSFET, in series. The switchable resistor memory element has the property of having at least two stable resistance states, for example a high-resistance state and a low-resistance state. It is switched between... Agent: Matrix Semiconductor, Inc.

20070007581 - Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same: A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070007580 - Non-volatile memory devices having floating gates that define a void and methods of forming such devices: Non-volatile memory devices include a floating gate having a lower portion and a pair of walls extending upward from opposite edges of the lower portion to define a void. An overlap area between adjacent floating gates is decreased by a side area of the void defined by the lower portion... Agent: Myers Bigel Sibley & Sajovec

20070007578 - Sub zero spacer for shallow mdd junction to improve bvdss in nvm bitcell: A semiconductor process and apparatus includes forming a floating gate stack structure (1) and a low voltage transistor gate stack structure (2) over a substrate (11) by including a shallow extension implant region (51, 52) that is aligned with the floating gate (13). By using a spacer etch process after... Agent: Hamilton & Terrile, LLP

20070007582 - Semiconductor device including a floating gate electrode having stacked structure: A semiconductor device includes a semiconductor layer having a plurality of element regions in its surface area, which are delimited by at least one element isolation trench, a plurality of floating gate electrodes provided on the element regions with a first gate insulation film interposed therebetween and each including a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070007583 - Gate structure and related non-volatile memory device and method: A gate structure adapted for use in a SONOS device unit cell is disclosed. The gate structure comprises a charge trap insulator and a single electrode. The charge trap insulator comprises a multilayer structure comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.... Agent: Volentine Francos, & Whitt PLLC

20070007584 - Nitride semiconductor light emitting diode and method of manufacturing the same: The present invention relates to a GaN-based semiconductor light emitting diode and a method of manufacturing the same. The GaN-based semiconductor light emitting diode includes: a substrate; a n-type nitride semiconductor layer formed on the substrate; an active layer formed on a predetermined portion of the n-type nitride semiconductor layer;... Agent: Mcdermott Will & Emery LLP

20070007585 - Memory device with improved data retention: The present memory device includes first and second electrodes, a passive layer between the first and second electrodes and an active layer between the first and second electrodes, the active layer being of a material containing randomly oriented pores which are interconnected to form passages through the active layer.... Agent: Paul J. Winters

20070007587 - Diode: A diode has a semiconductor body (1), which has a front side (11) and a rear side (12) opposite the front side (11) in a vertical direction (z) of the semiconductor (1), and in which a heavily n-doped zone (5), a weakly n-doped zone (4), a weakly p-doped zone (3)... Agent: Baker Botts, L.L.P.

20070007588 - Insulated gate semiconductor device, protection circuit and their manufacturing method: A first electrode layer, which comes into contact with a source region, and a second electrode layer, which comes into contact with a body (back gate) region, are provided. The first and second electrode layers are insulated from each other and are extended in a direction different from an extending... Agent: Morrison & Foerster LLP

20070007586 - Method of forming a charge-trapping memory device: In a charge-trapping device having an array of memory cells, which are controlled by word lines buried in trenches within a substrate, further trenches are formed parallel to said word lines within said substrate. These subdivide diffusion regions adjacent to the word lines into each a first diffusion region adjacent... Agent: Slater & Matsil LLP

20070007589 - Semiconductor device: A first main electrode is provided on one surface thereof. On the other surface thereof, a second semiconductor layer of the first conduction type and a third semiconductor layer of the second conduction type are arranged alternately along the surface. A fourth semiconductor layer of the second conduction type and... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070007590 - Field effect transistor and manufacturing method thereof: A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070007591 - Electric device comprising an ldmos transistor: The LDMOS transistor (99) of the invention is provided with a stepped shield structure (50) and/or with a first (25) and a second (26) drain extension region having a higher dopant concentration than the second drain extension region, and being covered by the shield.... Agent: Philips Intellectual Property & Standards

20070007592 - Semiconductor component with a channel stop zone: A semiconductor component has a semiconductor body (100) having a basic doping and a first and second side, an inner region (103) arranged between the first and second sides, and an edge region (104) adjacent to the inner region in a lateral direction, at least one active component zone (12)... Agent: Baker Botts, L.L.P.

20070007593 - Metal-oxide-semiconductor device with enhanced source electrode: An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain... Agent: Duane Morris, LLPIPDepartment

20070007596 - Method to manufacture silicon quantum islands and single-electron devices: The present invention provides a method of manufacturing a single-electron transistor device (100). The method includes forming a thinned region (110) in a silicon substrate (105), the thinned region (110) offset by a non-selected region (115). The method also includes forming at least one quantum island (145) from the thinned... Agent: Texas Instruments Incorporated

20070007594 - Semiconductor device and method of manufacturing the same: According to the present invention, there is provided a semiconductor device manufacturing method comprising: depositing a semiconductor layer and mask material in order over a semiconductor substrate on an insulating film; patterning the semiconductor layer and mask material to form a semiconductor layer in a predetermined region; removing a surface... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070007595 - Semiconductor device with effective heat-radiation: The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070007597 - Esd structure having different thickness gate oxides: An electrostatic discharge (ESD) structure having increased voltage withstand at an output terminal of an integrated circuit device has a thin gate oxide layer metal oxide semiconductor (MOS) device coupled in series with a thicker gate oxide layer MOS device. The thin gate oxide layer MOS device may be controlled... Agent: Baker Botts, LLP

20070007598 - System and method for esd protection: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20070007599 - Semiconductor device: A semiconductor device including: a semiconductor layer including an active region and an isolation region provided around the active region; an element formed in the active region; an interlayer dielectric formed above the semiconductor layer; and an electrode pad formed above the interlayer dielectric and having a rectangular planar shape... Agent: Harness, Dickey & Pierce, P.L.C

20070007600 - Mos transistor and method of manufacturing the same: Example embodiments of the present invention relate to a metal oxide semiconductor (MOS) transistor and a method of manufacturing the MOS transistor. A MOS transistor may include a substrate, a semiconductor pattern, a gate insulation layer and/or source-drain regions. The substrate may include an active region and/or a field region.... Agent: Harness, Dickey & Pierce, P.L.C

20070007601 - Vertical mosfet sram cell: A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch... Agent: Graham S. Jones, Ii Attorney At Law

20070007602 - Semiconductor device which has mos structure and method of manufacturing the same: The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070007603 - Semiconductor device: A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region.... Agent: Mcdermott Will & Emery LLP

20070007604 - Method for forming a dielectric layer and related devices: A dielectric layer may be formed by depositing the dielectric layer to an intermediate thickness and applying a nitridation process to the dielectric layer of intermediate thickness. The dielectric layer may then be deposited to the final, desired thickness.... Agent: Blakely Sokoloff Taylor & Zafman

20070007606 - Method for manufacturing mos transistor: Disclosed is a method for fabricating a MOS transistor. The present method includes forming a buffer layer pattern including nitrogen on the semiconductor substrate; forming a gate insulating layer and a gate electrode on the exposed substrate surface; forming a LDD region in the substrate under the buffer pattern; forming... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070007605 - Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate: The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric... Agent: Dorsey & Whitney LLP Intellectual Property Department

20070007607 - Semiconductor sensor and manufacturing mehtod therefor: A semiconductor sensor is disclosed that includes a semiconductor substrate, a sensing portion provided on the semiconductor substrate, and a pad in electrical communication with the sensing portion and provided on the semiconductor substrate. The semiconductor sensor also includes a bonding wire in electrical communication with the pad. Furthermore, the... Agent: Posz Law Group, PLC

20070007609 - Magnetoresistive effect element and magnetic memory: It is made possible to provide a highly reliable magnetoresistive effect element and a magnetic memory that operate with low power consumption and current writing and without element destruction. The magnetoresistive effect element includes a first magnetization pinned layer comprising at least one magnetic layer and in which a magnetization... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070007608 - Tilted array geometry for improved mram switching: An array of conductive lines for MRAM circuits wherein at least one set of mutually parallel conductive traces is tilted with respect to being perpendicular with a corresponding set of mutually parallel conductive traces wherein individual conductive traces within the sets intersect adjacent individual MRAM cells and wherein the tilting... Agent: Knobbe Martens Olson & Bear LLP

20070007610 - Magneto-resistive effect element and magnetic memory: It is possible to perform a writing operation with low power consumption and a low current, and enhance reliability without causing element breakdown. There are provided a first magnetization-pinned layer including at least one magnetic film in which a magnetization direction is pinned; a second magnetization-pinned layer including at least... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070007611 - Image sensor and related fabrication method: An image sensor comprising a transfer gate electrode having a uniform impurity doping distribution is provided. The image sensor further comprises a semiconductor substrate comprising a pixel area, wherein the pixel area comprises an active region and the transfer gate electrode is disposed on the active region. A method of... Agent: Volentine Francos, & Whitt PLLC

20070007612 - Method of providing an optoelectronic element with a non-protruding lens: An optoelectronic component has a lens that is formed in the surface of an encapsulant surrounding a semiconductor diode element. With respect to emitters, the lens reduces internal reflection and reduces dispersion to increase overall efficiency. With respect to detectors, the lens focuses photons on the active area of the... Agent: Knobbe Martens Olson & Bear LLP

20070007613 - Phase change memory with adjustable resistance ratio and fabricating method thereof: A phase change memory with adjustable resistance ratio is disclosed, which includes a phase change layer and an interfacial layer formed to be in contact with each other, and at least two electrodes in contact with the phase change layer and the interfacial layer respectively. The contact sections between the... Agent: Harness, Dickey & Pierce, P.L.C

20070007614 - Schottky diode with improved surge capability: An SiC Schottky diode die or a Si Schottky diode die is mounted with its epitaxial anode surface connected to the best heat sink surface in the device package. This produces a substantial increase in the surge current capability of the device.... Agent: Ostrolenk Faber Gerb & Soffen

20070007615 - Devices containing multiple undercut profiles: Devices including multiple undercut profiles in a single material are disclosed. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch that produces a polymer film in... Agent: Trask Britt

20070007616 - Semiconductor structure: A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited on the bottom surface of the substrate,... Agent: Baker Botts, L.L.P.

20070007617 - Semiconductor device and method for fabricating the same: An isolation insulating film is formed so that an active region of a first access transistor and a substrate contact region can be integrated with each other in a plan view. A dummy gate electrode is formed on the semiconductor substrate between the active region of the first access transistor... Agent: Mcdermott Will & Emery LLP

20070007618 - Semiconductor device: There is disclosed a semiconductor device comprising a plurality of inter-level dielectric films which are stacked and provided in plural layers above a substrate, at least one first conductor which is provided in at least one inter-level dielectric film of the stacked inter-level dielectric films, and a plurality of second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070007619 - Semiconductor device and method for manufacturing the same: After formation of a gate insulating film for a high voltage transistor on the entire surface, when removing the gate insulating film existing within a low voltage region, etching is not finished upon expose of an active region, but overetching is performed until the surface of an element isolation insulating... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070007620 - Fuse box of semiconductor device: A fuse box of a semiconductor device is provided. More specifically, provided is a device of forming a uniformly residual oxide film by rearranging fuse boxes in consideration of an etching ratio depending on plasma density of the semiconductor device to prevent a fuse attack. During a repair etching process... Agent: Heller Ehrman White & Mcauliffe LLP

20070007621 - Fuse breakdown method adapted to semiconductor device: A plurality of pulses each having relatively low energy are consecutively applied to a subject fuse to cause breakdown, wherein the total energy of pulses is set in light of a prescribed breakdown threshold, which is calculated in advance. The subject fuse has a pair of terminals and an interconnection... Agent: Dickstein Shapiro LLP

20070007622 - Method of manufacturing a passive integrated matching network for power amplifiers: An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070007623 - Method to fabricate horizontal air columns underneath metal inductor: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath... Agent: Saile Ackerman LLC

20070007624 - Method for fabricating a capacitor: The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises: a trench inside a substrate, the trench having a lower region and an upper region, wherein the trench's diameters in the lower region is larger than... Agent: Slater & Matsil LLP

20070007625 - Method for forming a bipolar transistor device with self-aligned raised extrinsic base: Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-are lithographic patterning. An opening is aligned above the dielectric pad and... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070007626 - High-power-gain, bipolar transistor amplifier: Improved radio frequency gain in a silicon-based bipolar transistor may be provided by adoption of a common-base configuration, preferably together with excess doping of the base to provide extremely low base resistances boosting performance over similar common-emitter designs.... Agent: Boyle Fredrickson Newholm Stein & Gratz, S.c.

20070007627 - Method of forming openings in an organic resin material: A thin film of organic resin material (17), such as novolac, is used as an etch mask and openings (32) are formed in the mask in a predetermined pattern to allow processing in selected areas defined by the openings. The openings (32) are formed by applying a pattern of droplets... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20070007628 - Electron-beam treated cdo films: A method of forming an integrated circuit including forming a dielectric film is described. The forming of the dielectric film includes: providing a substrate, providing a carbon doped oxide film on the substrate, and treating the carbon doped oxide film with an electron beam. The carbon doped oxide film can... Agent: Fish & Richardson, PC

20070007629 - Integrated circuit power supply network: An integrated circuit including an assembly of functional blocks and an interconnection network formed of at least N levels of conductive tracks separated by conductive via levels, the interconnection network including a power supply network comprising a first assembly of substantially parallel rails placed at the N-th track level, and... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070007630 - Switching element for a pixel electrode and methods for fabricating the same: The invention discloses a switching element for a pixel electrode of display device and methods for fabricating the same. A gate is formed on a substrate. A high-k dielectric layer is formed on the gate. The high-k dielectric layer comprises HfO2, HfNO, HfSiO, HfSiNO, or HfAlO. A semiconductor layer is... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070007631 - Advanced leadframe: A leadframe includes at least one lead extending from an integrated circuit and terminating at a connector pin. The lead includes multiple predefined bases to connect to one or more components external to the integrated circuit.... Agent: Kacvinsky LLC

20070007633 - Lead frame, resin-encapsulated semiconductor device, and method of producing the same: A resin-encapsulated semiconductor device includes: a semiconductor chip on a surface of which a group of electrodes is disposed; a plurality of inner leads arranged along a periphery of the semiconductor chip; connecting members for connecting the electrodes of the semiconductor chip with the respective inner leads, an encapsulating resin... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070007632 - Optical package with double formed leadframe: Packages for an optical integrated circuit die and a method for making such packages are disclosed. The package includes a die, a die pad, a plurality of lead fingers, and an encapsulating dielectric material. The downward second pad surface of the die pad bearing an integrated circuit is encapsulated by... Agent: Rosenberg, Klein & Lee

20070007634 - Method for manufacturing semiconductor chip package: A semiconductor chip package may have through holes extending from a chip contact surface of a film type die attaching material to a second surface of a die pad. A resin encapsulant may extend into the through holes to directly contact portions of a semiconductor chip that are superposed over... Agent: Harness, Dickey & Pierce, P.L.C

20070007635 - Self aligned metal gates on high-k dielectrics: A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070007636 - Parallel chip embedded printed circuit board and manufacturing method thereof: A parallel chip embedded printed circuit board and manufacturing method thereof are disclosed. With a method of manufacturing a parallel chip embedded printed circuit board, comprising: (a) forming a parallel chip by connecting in parallel a plurality of unit chips having electrodes or electrically connected members formed on the upper... Agent: Staas & Halsey LLP

20070007638 - Memory array module mounting structure: A memory array module mounting structure is disclosed to include a main board, which has circuit contacts arranged thereon, a plurality of connectors installed in the main board and electrically connected to the circuit contacts of the main board, and a plurality of memory chips respectively detachably inserted into the... Agent: Optimum Care International Tech. Inc.

20070007637 - Multi-layered substrate assembly with vialess electrical interconnect scheme: A multi-layered substrate (42) is disclosed. The substrate (42) includes at least a receptor layer (46) and a bonding layer (64). One or more holes (54) extend completely through the receptor layer (46). A shaped block (10) may be disposed in a given hole (54). When the substrate (42) is... Agent: Marsh, Fischmann & Breyfogle LLP

20070007639 - Semiconductor device, manufacturing method for semiconductor device, and electronic equipment: A semiconductor device includes: a plurality of stacked semiconductor chips including a first semiconductor chip having a side surface, and a second semiconductor chip stacked on the first semiconductor chip; and a sealing resin placed between the plurality of semiconductor chips, at least one edge of the first semiconductor chip... Agent: Harness, Dickey & Pierce, P.L.C

20070007640 - Surface mount package: Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and... Agent: Townsend And Townsend And Crew, LLP

20070007641 - Chip-embedded interposer structure and fabrication method thereof, wafer level stack structure and resultant package structure: A method for fabricating a chip-embedded interposer may comprise forming at least one cavity on a silicon substrate, forming a plurality of through vias penetrating the silicon substrate, providing an integrated circuit chip having a plurality of I/O pads, and forming rerouting conductors connected to the I/O pads and the... Agent: Marger Johnson & Mccollom, P.C.

20070007642 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a functional circuit block, a power supply for supplying power to the functional circuit block, a power supply interruption circuit disposed between the functional circuit block and the power supply and including a plurality of switching elements, and a power supply interruption control circuit... Agent: Mcdermott Will & Emery LLP

20070007643 - Semiconductor multi-chip package: The invention provides a semiconductor multi-chip package including a substrate, a first semiconductor chip mounted on the substrate and a second semiconductor chip disposed directly above the first semiconductor chip. The package further includes a spacer disposed between the substrate and the second semiconductor chip to maintain a vertical interval... Agent: Lowe Hauptman Berner, LLP

20070007644 - Ball grid array package enhanced with a thermal and electrical connector: Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. A substrate has a surface, wherein the surface has an opening therein. A stiffener has a surface coupled to the surface of the substrate. An area of the surface of the stiffener can be greater than, equal to,... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20070007645 - Stack package and semiconductor module implementing the same: The stack package may have a structure in which unit packages may be inserted into slots of a receiving substrate. The unit package may have a plurality of connecting pads. The receiving substrate may have substrate pads, which may be electrically connected to the connecting pads of the unit packages... Agent: Harness, Dickey & Pierce, P.L.C

20070007646 - Substrate treatment apparatus, substrate holding device, and semiconductor device manufacturing method: A substrate processing apparatus houses plural wafers (substrates) held on a boat (substrate holder) in a processing chamber, supplying processing gas to the heated processing chamber, thereby performing film-forming processing for the wafers. The boat includes: at least three support columns 15 provided substantially vertically; plural wafer support portions 16... Agent: Oliff & Berridge, PLC

20070007647 - High frequency package device: In a high frequency package device includes a bottom plate, a side wall, a lid, a dielectric plate, an input line, an output line and a projection. The side wall is provided on the bottom plate, and configured to surround a space above the bottom plate. The lid is configured... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070007648 - Semiconductor device protective structure and method for fabricating the same: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The... Agent: Kusner & Jaffe Highland Place Suite 310

20070007649 - Low cte substrates for use with low-k flip-chip package devices: Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one... Agent: Baker & Mckenzie On Behalf Of Tsmc

20070007650 - Driver device and display device: Disclosed is a device which comprises a substrate, a plurality of signal output terminal electrodes provided on the substrate, a plurality of signal input terminal electrodes provided on the substrate, and a display driver IC having input terminals thereof connected to the signal input terminal electrodes and output terminals thereof... Agent: Young & Thompson

20070007651 - Semiconductor device: A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate and including a plurality of first portions and a second portion disposed between two of the first portions adjacent to each other; and an interconnect electrically connected to the electrode and extending... Agent: Harness, Dickey & Pierce, P.L.C

20070007652 - Stack type package: A stack type semiconductor package uses rigid, C-shaped guide substrates that hold semiconductor packages stacked in place and which also provide signal pathways between the stacked semiconductors and contact surfaces of the package. The C-shaped guide eliminate short circuits caused by prior art lead wires.... Agent: Ladas & Parry LLP

20070007653 - Interconnects with improved reliability: An interconnect architecture with improved reliability. An interconnect with rounded top corners is inlaid in a dielectric layer. A filler borders the interconnect along the corners of the interconnect.... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070007654 - Metal line of semiconductor device and method for forming thereof: There is provided a metal line of a semiconductor device and a method for forming the metal line. In the method, a first metal line can be formed above a semiconductor substrate. An etch barrier layer can be formed on the first metal line. An interlayer insulating layer can be... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070007658 - Method of manufacturing interconnecting structure with vias: First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the... Agent: Leydig Voit & Mayer, Ltd

20070007657 - Methods for forming conductive vias in a substrate and electronic devices and systems including an at least partially reversed oxidation injury at an interface between a conductive via and a conductive interconnect structure: Methods for forming conductive vias in a substrate include oxidizing at least a portion of a metallic structure that is exposed through an opening in a substrate to form an oxidation injury in the metallic structure. The oxidation injury is at least partially reversed, and conductive material is provided within... Agent: Trask Britt

20070007655 - Semiconductor device: A semiconductor device that includes a pad over a multilevel interconnect formed by stacking an interconnect layer and an interlayer insulating film, the semiconductor device including a protective member that is formed in a continuous manner under outer circumference of the pad and has moisture resistance, the protective member surrounding... Agent: Robert J. Depke Lewis T. Steadman

20070007656 - Semiconductor device and methods thereof: An insulation interlayer having first contact holes exposing first contact pads is formed on a semiconductor structure having the first and second contact pads. Conductive patterns connected to the first contact pads through the first contact holes are formed on the insulation interlayer. Insulation layer patterns are formed on the... Agent: Harness, Dickey & Pierce, P.L.C

20070007659 - Seedless wirebond pad plating: An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a platable metal layer.... Agent: Law Office Of Charles W. Peterson, Jr. Fishkill Fishkill

20070007660 - Mask etch processing apparatus: Method and apparatus for supporting and transferring a substrate in a semiconductor wafer processing system are provided. In one aspect, an apparatus is provided for supporting a substrate comprising a cover ring comprising a base having a bore disposed therethough, the base having an upper surface and one or more... Agent: Patterson & Sheridan, LLP

20070007661 - Hybrid conductive coating method for electrical bridging connection of rfid die chip to composite antenna: A radio frequency identification device (RFID) includes a non-conductive first substrate, an integrated circuit device mounted to the carrier substrate and having at least one conductive terminal and a patterned conductive coating applied to the non-conductive substrate and in contact with the at least one conductive terminal. The patterned conductive... Agent: Dilworth & Barrese, LLP

20070007662 - Semiconductor device: A semiconductor device including: a semiconductor layer including an element formation region and an isolation region provided around the element formation region; an element formed in the element formation region; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric; a passivation layer formed... Agent: Harness, Dickey & Pierce, P.L.C

20070007663 - Semiconductor package having dual interconnection form and manufacturing method thereof: An embodiment includes a dual interconnection form in which power/ground pads and signal pads of a semiconductor chip are electrically connected to a package substrate in different connection manners. First connection members that electrically connect the power/ground pads with the substrate have relatively large cross-sectional dimensions in comparison to its... Agent: Marger Johnson & Mccollom, P.C.

20070007664 - Semiconductor package with molded back side and method of fabricating the same: Provided are a semiconductor package having a semiconductor chip, a rear surface of which is molded, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip including a wafer and a metal pad formed on a front surface of the wafer; a solder ball formed... Agent: Marger Johnson & Mccollom, P.C.

20070007665 - Structure and method for producing multiple size interconnections: An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically... Agent: Schmeiser, Olsen & Watts

20070007667 - Electronic package having a sealing structure on predetermined area, and the method thereof: An electronic package for a photo-sensing device is provided. The package is formed to include a substrate of a material substantially transparent to light within a predetermined range of wavelengths. The package further formed to include at least one photo-sensing die having a photo-sensing area defined on a front side... Agent: Rosenberg, Klein & Lee

20070007668 - Microelectronic assembly with underchip optical window, and method for forming same: A microelectronic assembly includes an integrated circuit die spaced apart from a substrate and connected by bump interconnections, and an polymeric encapsulant molded about the die. The encapsulant extends into the gap about the interconnections, but is confined to the perimeter so as to define an underchip optical window adjacent... Agent: Delphi Technologies, Inc.

20070007666 - Substrate for manufacturing semiconductor device, semiconductor device manufacturing method: A substrate for manufacturing semiconductor device includes a wafer; a plurality of semiconductor elements formed on the wafer; a bump arranged in each peripheral section of the semiconductor elements; an alignment mark arranged in the each peripheral section of the semiconductor elements; and an adhesive layer formed on the semiconductor... Agent: Harness, Dickey & Pierce, P.L.C

20070007669 - Wire-bonding method and semiconductor package using the same: A wire-bonding method and a semiconductor package using the same are provided. The semiconductor package includes a carrier; a chip mounted on the carrier; a plurality of first wires and second wires alternatively arranged in a stagger manner, with a wire loop of each second wire being downwardly bent to... Agent: Edwards & Angell, LLP

20070007670 - Reworkable bond pad structure: A bond pad structure includes a plurality of normal bond pads, a conductive structure and a plurality of backup bond pads. The conductive structure has a plurality of blocks, and at least one of the backup bond pads is disposed on individual blocks. The blocks are isolated from each other... Agent: Rosenberg, Klein & Lee

20070007671 - Semiconductor device and method of manufacturing the same: A semiconductor device including a semiconductor substrate having a plurality of electrodes, a resin protrusion formed on the semiconductor substrate, and an interconnect electrically connected to the electrodes and formed to extend over the resin protrusion. A depression is formed in a top surface of the resin protrusion. The interconnect... Agent: Harness, Dickey & Pierce, P.L.C

20070007672 - Package film, package of electrode member, and stand for package: The present invention provides an electrode material package, by which the electrode materials are protected from damages due to external impacts, etc. during the transportation or storage. Further, with the electrode material package of the present invention, the electrode material can be kept under a low humidity atmosphere, and the... Agent: Birch Stewart Kolasch & Birch