Active solid-state devices (e.g., transistors, solid-state diodes) inventions 12/06

20060289847 - Reducing the time to program a phase change memory to the set state: A phase change memory may be formed with a chalcogenide layer that contains titanium. The titanium reduces the crystallization time. Set state resistance may also be decreased, thereby reducing the access time of the semiconductor memory, in some embodiments.... Agent: Trop Pruner & Hu, PC

20060289849 - Composition for forming porous film, porous film and method for forming the same, interlevel insulator film, and semiconductor device: The invention includes a semiconductor device. Specifically provided is a semiconductor device comprising a porous film therein, the porous film being formable by a composition comprising a surfactant, an aprotic polar solvent and a solution comprising a polymer formed by hydrolysis and condensation of one or more silane compounds represented... Agent: Alston & Bird LLP

20060289850 - Phase change memory and phase change recording medium: A phase change memory comprises: a substrate; an insulation film formed on a main surface of the substrate; a first electrode deposited on the insulation film; a phase change recording film deposited on the first electrode; and a second electrode deposited on the phase change recording film. The phase change... Agent: Antonelli, Terry, Stout & Kraus, LLP

20060289848 - Reducing oxidation of phase change memory electrodes: A phase change memory may be formed in a way which reduces oxygen infiltration through a chalcogenide layer overlying a lower electrode. Such infiltration may cause oxidation of the lower electrode which adversely affects performance. In one such embodiment, an etch through an overlying upper electrode layer may be stopped... Agent: Trop Pruner & Hu, PC

20060289851 - Resistance variable memory device and method of fabrication: Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least one chalcogenide glass layer. The invention also relates to methods of forming such a... Agent: Dickstein Shapiro LLP

20060289852 - Bipolar transistor with collector having an epitaxial si:c region: A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region... Agent: Scully, Scott, Murphy & Pressner

20060289853 - Apparatus for manufacturing a quantum-dot element: An apparatus for manufacturing a quantum-dot element is disclosed. The apparatus includes a reaction chamber for evaporating or sputtering at least one electrode layer or at least one buffer layer on the substrate. The substrate-supporting base is located inside the reaction chamber for fixing the substrate. The atomizer has a... Agent: Bacon & Thomas, PLLC

20060289854 - Optical semiconductor device with multiple quantum well structure: An optical semiconductor device with a multiple quantum well structure, in which well layers and barrier layers comprising various types of semiconductor layers are alternately layered, in which device well layers (6a) of a first composition based on a nitride semiconductor material with a first electron energy and barrier layers... Agent: Fish & Richardson PC

20060289855 - Quantum dot based optoelectronic device and method of making same: A method of forming an optically active region on a silicon substrate includes the steps of epitaxially growing a silicon buffer layer on the silicon substrate and epitaxially growing a SiGe cladding layer having a plurality of arrays of quantum dots disposed therein, the quantum dots being formed from a... Agent: VistaIPLaw Group LLP

20060289856 - Semiconductor device and production method thereof: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060289859 - Method for forming a stacked structure of an insulating layer and an organic semiconductor layer, organic field effect transistor and method for making same: A method for making an organic field effect transistor of a bottom gate/bottom contact type or a bottom gate/top contact type is provided. The method comprises (a) forming a gate electrode 12 on a support and forming a gate insulating layer 13 on the support 10 and the gate electrode... Agent: Bell, Boyd & Lloyd, LLC

20060289857 - Organic light emitting display capable of showing images on double sides thereof: An organic light emitting display (OLED) has a substrate, on two opposite sides of which a fist electrode, an organic layer and a second electrode are stacked in sequence respectively. To prevent the light of the organic layers at the opposite sides of the substrate from interference, the substrate or... Agent: Bacon & Thomas, PLLC

20060289858 - Organic thin film transistor(s) and method(s) for fabricating the same: Example embodiments of the present invention for fabricating an organic thin film transistor including a substrate, a gate electrode, a gate insulating layer, metal oxide source/drain electrodes and an organic semiconductor layer wherein the metal oxide source/drain electrodes are surface-treated with a self-assembled monolayer (SAM) forming compound containing a sulfonic... Agent: Harness, Dickey & Pierce, P.L.C

20060289860 - Semiconductor layer: The semiconductor layer includes a β-Ga2O3 substrate 1 made of a β-Ga2O3 single crystal, a GaN layer 2 formed by subjecting a surface of the β-Ga2O3 substrate 1 to nitriding processing, and a GaN growth layer 3 formed on the GaN layer 2 through epitaxial growth by utilizing an MOCVD... Agent: Mcginn Intellectual Property Law Group, PLLC

20060289863 - Semiconductor device evaluation apparatus and semiconductor device evaluation method: An apparatus for evaluating a field-effect transistor includes a pulse generator, a current/voltage converter, a switch and a first constant-voltage source. The pulse generator can be electrically connected to a gate electrode of a field-effect transistor. The current/voltage converter includes an input terminal. The input terminal can be electrically connected... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060289861 - Systems and arrangements to interconnect components of a semiconductor device: Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density are disclosed. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20060289862 - Systems and methods for thermal sensing: Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional... Agent: Law Offices Of Mark L. Berrier

20060289864 - High impedance antifuse: A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the... Agent: Ibm Microelectronics Intellectual Property Law

20060289866 - Electro-optic display and manufacturing method thereof: A pixel electrode is disposed to cover the inner surfaces of a pixel-drain contact hole passing through a third insulating film and a second insulating film to reach a drain electrode. At the bottom of the pixel-drain contact hole, the pixel electrode is electrically connected with the drain electrode through... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289868 - Flat panel display and method for driving the same: A flat panel display for preventing a thin film transistor from deteriorating due to voltage, static electricity, and external force, accidentally applied to a substrate, and a method for driving the same. The flat panel display includes a conductive substrate, at least one insulating layer formed on the conductive substrate,... Agent: Christie, Parker & Hale, LLP

20060289867 - Liquid crystal display device capable of reducing leakage current, and fabrication method thereof: The present invention discloses a liquid crystal display device which can improve quality of image by reducing a leakage current by a backlight, and a fabrication method thereof. The liquid crystal display device includes: first and second substrates; a plurality of gate lines aligned on the first substrate in a... Agent: Mckenna Long & Aldridge LLP

20060289865 - Method of manufacturing a semiconductor device: TFT structures optimal for driving conditions of a pixel portion and driving circuits are obtained using a small number of photo masks. First through third semiconductor films are formed on a first insulating film. First shape first, second, and third electrodes are formed on the first through third semiconductor films.... Agent: Eric Robinson

20060289869 - Semi-transparent tft array substrate, and semi-transparent liquid crystal display: A contrast reduction preventive electrode is formed in a reflective region, and in the same layer as a transparent pixel electrode. A connection for connecting the contrast reduction preventive electrode and the transparent pixel electrode is formed, in such a position that the connection does not overlap an auxiliary capacitive... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289871 - Thin film transistor substrate and method of manufacturing the same: A thin film transistor (TFT) substrate having an improved wire structure without an under-cut phenomenon that may occur during formation of a gate wire having a double-layered structure and a method of manufacturing the same are provided, where the method includes forming a first metal layer made of at least... Agent: F. Chau & Associates, LLC

20060289870 - Thin film transistor substrate and production method thereof: A method for producing a thin film transistor substrate includes the steps of: (i) depositing an amorphous semiconductor film on a transparent insulating substrate; (ii) patterning the amorphous semiconductor film so as to form insular amorphous semiconductor films, the step (ii) including a process (I) for forming, in respective stripe... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20060289872 - Wiring substrate, electronic device, electro-optical device, and electronic apparatus: The invention achieves stable performance, such as low parasitic capacitance generated at conductive components. Components having a low dielectric constant of 4 or less are disposed on a base member. Functional films partitioned by the low-dielectric-constant components are also provided.... Agent: Oliff & Berridge, PLC

20060289873 - Semiconductor devices and methods of making same: A composite structure having a silicon carbide epitaxial layer is provided. The epitaxial layer includes at least four regions arranged vertically and defining respective interfaces, where each of the regions is characterized by a respective impurity concentration, where the impurity concentrations vary across each of the interfaces, and where each... Agent: Patrick S. Yoder Fletcher Yoder

20060289874 - Silicon carbide devices with hybrid well regions: MOS channel devices and methods of fabricating such devices having a hybrid channel are provided. Exemplary devices include vertical power MOSFETs that include a hybrid well region of silicon carbide and methods of fabricating such devices are provided. The hybrid well region may include an implanted p-type silicon carbide well... Agent: Myers Bigel Sibley & Sajovec

20060289875 - Light emitting diode and method making the same: A light emitting diode and the method of the same are provided. The light emitting diode includes a substrate, a thermal spreading layer, a connecting layer and an epitaxial structure. The substrate is selected from a transparent substrate or a non-transparent substrate, which corresponds to different materials of the connecting... Agent: Snell & Wilmer

20060289876 - Methods of combining silicon and iii-nitride material on a single wafer: A semiconductor device that includes one semiconductor device formed in one semiconductor material and a second semiconductor device formed in another semiconductor material on a common substrate, and a method of fabricating the semiconductor device.... Agent: Ostrolenk Faber Gerb & Soffen

20060289877 - Semiconductor device: The barrier φb between the Fermi level Ef of Se and the valence band of the wide band gap p-type semiconductor becomes the lowest by including the Se layer in the p-type ohmic electrode, and an ohmic contact is achieved that has a resistance far lower than that obtained when... Agent: Steptoe & Johnson LLP

20060289879 - Dual-face display apparatus, systems, and methods: Apparatus and systems, as well as methods and articles, may operate to display image information from one side of a light-emitting material layer disposed between a pair of non-opaque electrodes. The image information may be displayed through a transparent substrate, perhaps adjacent a conductive silicon layer, adjacent one of the... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060289880 - Illuminating device and display device including the same: Provided is a display device including: a light guide member for mixing light from a blue LED element coated with a translucent resin mixed with phosphor particles which converts blue light into green light with light from a red LED element to make white light exit from a light exit... Agent: Bruce L. Adams, Esq.

20060289878 - White-emitting led having a defined color temperature: LED with a low color temperature up to 3500 K, comprising a blue-emitting LED with two phosphors in front of it, a first phosphor from the class of the oxynitridosilicates, having a cation M, which is doped with divalent Europium, and has the empirical formula M(1-c)Si2O2N2:Dc, with M=Sr, or M=Sr(1-x-y)BayCax... Agent: Cohen, Pontani, Lieberman & Pavane

20060289881 - Semiconductor light emitting device: A semiconductor light emitting device including a substrate, a semiconductor light emitting stack, a first electrode, a first transparent oxide conductive layer and a second electrode is provided. The semiconductor light emitting stack is disposed on the substrate and has a first surface region and a second surface region. The... Agent: Jianq Chyun Intellectual Property Office

20060289882 - Organic electroluminescent element and organic electroluminescent display device: An organic electroluminescent element comprising a cathode, an anode, an intermediate unit arranged between a cathode and an anode, a first light emitting unit arranged between a cathode and an intermediate unit, and a second light emitting unit arranged between an anode and an intermediate unit, wherein an electron extracting... Agent: Mcdermott Will & Emery LLP

20060289883 - Light emitting device having protrusion and recess structure and method of manufacturing same: The semiconductor light emitting device having a protrusion and recess structure includes: a lower clad layer disposed on a substrate; an active layer formed on one portion of a top surface of the lower clad layer; an upper clad layer formed on the active layer; a first electrode formed on... Agent: Buchanan, Ingersoll & Rooney PC

20060289885 - Light-emitting diode: A light-emitting diode (LED) is described. The light-emitting diode has a light-emitting diode chip and a package structure covering the light-emitting diode chip. A surface of the package structure has a pattern structure, in which the pattern structure includes a plurality of stria structures for controlling a light shape output... Agent: Sughrue Mion, PLLC

20060289884 - Luminescent sheet covering for leds: A lighting apparatus comprising at least one light emitting diode is disposed on an interconnect board to emit ultraviolet or blue radiation. A polymeric layer including a luminophor is disposed about the lighting apparatus to convert at least a portion of the radiation emitted from the LED into visible light.... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20060289886 - Semiconductor light emitting device: A semiconductor light emitting device comprises: a semiconductor multilayer structure including a light emitting layer, a first semiconductor layer and a second semiconductor layer; a first electrode that forms ohmic contact with the first semiconductor layer in the semiconductor multilayer structure; a second electrode that forms ohmic contact with the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289889 - Display device and manufacturing method thereof: It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel, and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid... Agent: Eric Robinson

20060289888 - Packaging of smd light emitting diodes: An SMD LED package with superior thermal dissipation capability is provided. The SMD LED package comprises a supporting block with circuit patterns and at least one LED attached to the supporting block. Wherein, circuit patterns of holes/vias, insulating layers, and conducting traces/pads are formed on and in the supporting block.... Agent: Lin & Associates Intellectual Property

20060289887 - Surface mount light emitting diode (led) assembly with improved power dissipation: A high performance LED (402) and associated semiconductor package (400) advantageously utilizes an integrated heat sink (408) for purposes of power dissipation. At a next level of assembly, (500, 600) the semiconductor package (400) is electromechanically coupled to a printed circuit board (300). The printed circuit board (300) has a... Agent: Miller Johnson Snell Cummiskey, PLC

20060289890 - Light emitting device: A light emitting device includes: a first LED that emits a first primary light in a first primary wavelength range when activated; a second LED that emits a second primary light in a second primary wavelength range when activated, the second primary wavelength range differing from the first primary wavelength... Agent: Ladas & Parry Suite 2100

20060289891 - Electronic and/or optoelectronic devices grown on free-standing gan substrates with gan spacer structures: A GaN-based electronic and/or optoelectronic device formed on a free-standing GaN substrate, wherein a thick GaN spacer layer is provided between the device and the substrate, thereby separating the active region of the electronic and/or optoelectronic device from high impurity content at the substrate-epitaxial interface and reducing the detrimental impact... Agent: Intellectual Property / Technology Law

20060289892 - Method for preparing light emitting diode device having heat dissipation rate enhancement: A method for fabricating an LED having section grown on a sapphire substrate, a boded structure, and a unit chip separated from the bonded structure. The method includes (a) bonding the section grown on a first surface of the sapphire substrate to a first surface of a first substrate with... Agent: Mckenna Long & Aldridge LLP

20060289893 - Display device and driving apparatus having reduced pixel electrode discharge time upon power cut-off: A driving apparatus of a display device including a plurality of switching elements and a plurality of pixel electrodes connected to the switching elements is provided, in which the apparatus includes a gate-off voltage generator for generating a gate-off voltage and a gate driver for outputting the gate-off voltage from... Agent: Att: Patent Group Kieun "jenny" Sung

20060289894 - Semiconductor device: A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1−xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1−N; and a source electrode, a drain electrode and a gate... Agent: Mcdermott Will & Emery LLP

20060289895 - Semiconductor device: A semiconductor device includes a channel region, an oxide film, a gate electrode and source/drain regions. The channel region includes Ge. The oxide film is formed on the channel region. The oxide film includes Si and a metallic element M selected from the group consisting of Zr, Hf, La, Ce,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060289896 - Semiconductor device and method for fabricating the same: A semiconductor device has an interconnect layer for providing an electric connection between a base electrode and a base terminal provided on the region of a semi-insulating substrate on which a transistor is not formed. A resistor layer composed of a material different from respective materials composing the base electrode... Agent: Mcdermott Will & Emery LLP

20060289897 - Semiconductor device: A semiconductor device includes a first power supply which is disposed in a first direction, a first pad array which is disposed in the first direction, adjacent to the first power supply line, a second power supply line extending in the first direction, a first buffer circuit which is disposed... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289898 - Semiconductor device and fuse blowout method: A fuse includes a fuse portion laid in such a manner that the direction of each turn of the fuse portion is parallel to the direction in which pads are arranged. The distance between the pads and the fuse portion is defined as the distance between the side of a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289899 - Semiconductor devices having fuses and methods of forming the same: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be... Agent: Harness, Dickey & Pierce, P.L.C

20060289900 - Methods for forming a transistor and creating channel stress: Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stress in PMOS and NMOS transistors.... Agent: Scott S. Servilla Applied Materials, Inc.

20060289901 - Integrated nitride and silicon carbide-based devices and methods of fabricating integrated nitride-based devices: A monolithic electronic device includes a first nitride epitaxial structure including a plurality of nitride epitaxial layers. The plurality of nitride epitaxial layers include at least one common nitride epitaxial layer. A second nitride epitaxial structure is on the common nitride epitaxial layer of the first nitride epitaxial structure. A... Agent: Myers Bigel Sibley & Sajovec

20060289902 - Method for forming raised structures by controlled selective epitaxial growth of facet using spacer: Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of monocrystalline silicon on the surface of a semiconductive substrate, and forming a thin film... Agent: Whyte Hirschboeck Dudek S.c.

20060289903 - Method of forming metal/high-k gate stacks with high mobility: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate... Agent: Scully Scott Murphy & Presser, PC

20060289908 - Field effect device with a channel with a switchable conductivity: A field effect device includes a source electrode, a drain electrode, a channel formed between the source electrode and the drain electrode, and a gate electrode formed directly on the channel and arranged in a gap between the source electrode and the drain electrode. The channel includes a switching material... Agent: Ryan, Mason & Lewis, LLP

20060289907 - Metal oxide semiconductor (mos) transistors having buffer regions below source and drain regions and methods of fabricating the same: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region.... Agent: Myers Bigel Sibley & Sajovec

20060289909 - Self-aligned low-k gate cap: A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric... Agent: Scully Scott Murphy & Presser, PC

20060289905 - Semiconductor device: A semiconductor device comprising at least one FET formed on the semiconductor substrate, wherein the FET comprises a source region, a drain region, a channel region formed between the source and drain regions and including a plurality of projected epitaxial silicon regions arranged in a width direction of the channel... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289904 - Semiconductor device and method of manufacturing the same: In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289906 - Semiconductor device including a capacitance: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289911 - Cmos image sensor: Disclosed is a CMOS image sensor, comprising a photodiode formed in a substrate, a floating diffusion region formed in the substrate in a manner such that it is distanced from the photodiode surrounds the photodiode and a transfer gate formed in a manner such that it is distanced from the... Agent: Foley And Lardner LLP Suite 500

20060289912 - Cmos image sensor and manufacturing method thereof: Provided are a CMOS image sensor and a manufacturing method thereof. The CMOS image sensor incorporates an interlayer insulating layer, a color filter layer, a first planarizing layer, and at least one microlens. The interlayer insulating layer is formed on a semiconductor substrate having at least one photodiode. The color... Agent: Jeff Lloyd Saliwanchik, Lloyd & Saliwanchik

20060289910 - Image sensor and method for fabricating the same: A complementary metal oxide semiconductor (CMOS) image sensor capable of improving photosensitivity and a signal to noise ratio and a method for fabricating the same are provided. An image sensor for embodying the colors of red, green and blue includes: a plurality of photodiodes formed on a substrate and collecting... Agent: Blakely Sokoloff Taylor & Zafman

20060289913 - Pattern definition of mram device using chemical mechanical polishing: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a first dielectric... Agent: Dickstein Shapiro LLP

20060289918 - Low resistance peripheral local interconnect contacts with selective wet strip of titanium: Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.... Agent: Whyte Hirschboeck Dudek S.c.

20060289916 - Power trench mosfets having sige/si channel structure: Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the... Agent: Townsend And Townsend And Crew, LLP

20060289914 - Semiconductor constructions, memory cells, dram arrays, electronic systems; methods of forming semiconductor constructions; and methods of forming dram arrays: The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double the plate pitch. The invention includes a method of forming a semiconductor construction. A plurality of conductive layers is formed over the substrate, the plurality of layers... Agent: Wells St. John P.s.

20060289915 - Semiconductor device: A semiconductor device comprises a semiconductor portion including first semiconductor layers of a first conduction type and second semiconductor layers of a second conduction type alternately arranged on the surface of a semiconductor substrate to form a striped shape. A main region is formed to arrange a main cell in... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289917 - Semiconductor device, rf-ic and manufacturing method of the same: Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode,... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20060289919 - Two-sided surround access transistor for a 4.5f2 dram cell: An isolation transistor having a grounded gate is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device... Agent: Knobbe Martens Olson & Bear LLP

20060289920 - Composite gate structure in an integrated circuit: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal... Agent: Slater & Matsil, L.L.P.

20060289921 - Method of manufacturing a capacitor for semiconductor device: A capacitor for use in a semiconductor device, a method of fabricating the capacitor, and an electronic device adopting the capacitor, wherein the capacitor includes upper and lower electrodes, each formed of a platinum group metal; a thin dielectric layer disposed between the upper and lower electrodes; and a buffer... Agent: Lee & Morse, P.C.

20060289922 - Non-volatile semiconductor memory device: To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with... Agent: Mcginn Intellectual Property Law Group, PLLC

20060289924 - Low power electrically alterable nonvolatile memory cells and arrays: Nonvolatile memory cells having a conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, and mass-filtering function to charge-carriers flows. The conductor-insulator system provides Image-Force barrier lowering effect to collect charge-carriers. The charge-injection system includes the conductor-filter system and... Agent: Chih-hsin Wang

20060289925 - Non-volatile memory, manufacturing method and operating method thereof: A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate... Agent: Jianq Chyun Intellectual Property Office

20060289923 - Oxide epitaxial isolation: Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxial structure in the recess. A... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060289926 - Semiconductor device and method of manufacturing the same: A semiconductor device including a semiconductor substrate having trenches oriented in a predetermined direction; a gate insulating film overlaying the semiconductor substrate interposed between the trenches; and floating gate electrodes formed on the gate insulating film aligned in a predetermined direction and in a direction intersecting thereto, an element isolation... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289927 - Non-volatile memory with hole trapping barrier: A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises two layers of dielectric having different band... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060289928 - Insulated gate type semiconductor device and manufacturing method thereof: The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P− body region 41, and N−... Agent: Kenyon & Kenyon LLP

20060289931 - Recessed gate structures including blocking members, methods of forming the same, semiconductor devices having the recessed gate structures and methods of forming the semiconductor devices: A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void... Agent: Myers Bigel Sibley & Sajovec

20060289930 - Semiconductor device and method of fabricating the same: Aiming at providing a semiconductor device capable of reducing the ON-resistance when voltage smaller than a predetermined value is applied to the base region and the drift region, and capable of increasing the ON-resistance so as to prevent thermal fracture when the voltage is not smaller than the predetermined value,... Agent: Mcginn Intellectual Property Law Group, PLLC

20060289929 - Structure and method for forming laterally extending dielectric layer in a trench-gate fet: A field effect transistor (FET) is formed as follows. A trench is formed in a silicon region. An oxidation barrier layer is formed over a surface of the silicon region adjacent the trench and along the trench sidewalls and bottom. A protective layer is formed over the oxidation barrier layer... Agent: Townsend And Townsend And Crew, LLP

20060289932 - Semiconductor memory device having power decoupling capacitor: Provided is a semiconductor memory device using a layout scheme where a bottom conductive layer in a peripheral circuit region, which is simultaneously formed with a self-align contact, is connected to one electrode of a power decoupling capacitor. Predetermined capacitors selected among a plurality of capacitors are connected to each... Agent: Marger Johnson & Mccollom, P.C.

20060289933 - Field effect transistor and method for producing a field effect transistor: A field effect transistor is provided having a source region, a drain region formed in a first well region, and a channel region. The first well region is doped with doping atoms of a first conductivity type. At least a part of the channel region which extends into the first... Agent: Brinks Hofer Gilson & Lione Infineon

20060289934 - Semiconductor device, liquid crystal display panel, electronic device, and method of manufacturing semiconductor device: In a plurality of transistors in which the thresholds that are required in the circuit design are equal, a transistor having an initial threshold at a lower limit within an acceptable range of the required threshold is arranged at a circuit position where an absolute value of a threshold voltage... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser

20060289935 - Layout structure for esd protection circuits: A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20060289936 - Esd protection device structure: An electrostatic discharge (ESD) protective device structure. The ESD protection device includes: at least a first conductive type metal-oxide semiconductor (MOS), in which the drain and source of the first conductive type MOS are electrically connected to a first power terminal and a second power terminal separately; at least a... Agent: North America Intellectual Property Corporation

20060289937 - System for esd protection with extra headroom in relatively low supply voltage integrated circuits: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20060289938 - Non-volatile memory devices and related methods: A semiconductor device may include a semiconductor substrate having an active region on a surface thereof. First, second, and third gate lines may cross the active region of the semiconductor substrate, and the first, second, and third gate lines may be arranged in parallel across the active region, and the... Agent: Myers Bigel Sibley & Sajovec

20060289939 - Array substrate and display device having the same: An LCD display device in which the gate lines are controlled by a gate circuit part that outputs gate signals to the gate lines. A first signal wiring is formed adjacent to the gate circuit part and transmits a starting signal, which initiates an operation of the gate circuit part,... Agent: Macpherson Kwok Chen & Heid LLP

20060289940 - Fin fet cmos device, method of manufacturing the same, and memory including fin fet cmos device: A fin FET CMOS device, a method of manufacturing the same, and a memory including the fin FET CMOS device are provided. The CMOS device may include a substrate, an n-type transistor disposed on the substrate, an interlayer insulating layer disposed on the n-type transistor, and a p-type transistor disposed... Agent: Harness, Dickey & Pierce, P.L.C

20060289941 - Transistor component: A source connection of a field effect transistor is formed using a contact region, which adjoins a source region, is highly oppositely doped and forms a butting contact with the source region. A well or substrate connecting region which is electrically conductively connected to a supply potential lead is arranged... Agent: Dickstein Shapiro LLP

20060289942 - Memory cell, semiconductor memory device, and method of manufacturing the same: A memory cell in a semiconductor memory device comprises a variable resistor element configured so that a variable resistor body is sandwiched between a first electrode and a second electrode, and a transistor element capable of controlling a flow of current in the variable resistor element, wherein the transistor element... Agent: Nixon & Vanderhye, PC

20060289943 - Memory: A memory allowing reduction of a memory cell size is obtained. This memory comprises a first conductive type first impurity region formed on the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a word line, a plurality... Agent: Mcdermott Will & Emery LLP

20060289944 - Nonvolatile memory devices having a fin shaped active region and methods of fabricating the same: A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are... Agent: Myers Bigel Sibley & Sajovec

20060289945 - Semiconductor memory device: Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting... Agent: Mcdermott Will & Emery LLP

20060289946 - Method and apparatus for maintaining topographical uniformity of a semiconductor memory array: A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack... Agent: Freescale Semiconductor, Inc. Law Department

20060289947 - Semiconductor device and its manufacturing method: This semiconductor device includes a first device and a second device provided on a semiconductor substrate and having different breakdown voltages. More specifically, the semiconductor device includes a semiconductor substrate, a first region defined on the semiconductor substrate and having a first device formation region isolated by a device isolation... Agent: Rabin & Berdo, PC

20060289948 - Method to control flatband/threshold voltage in high-k metal gated stacks and structures thereof: The present invention provides a metal stack (or gate stack) structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a gate conductor and a dielectric material having a dielectric constant of greater than about 4.0, especially a Hf-based dielectric. This present invention stabilizes the flatband... Agent: Scully Scott Murphy & Presser, PC

20060289949 - Method of composite gate formation: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing... Agent: Whyte Hirschboeck Dudek S.c.

20060289950 - Method of composite gate formation: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing... Agent: Whyte Hirschboeck Dudek S.c.

20060289951 - Method of composite gate formation: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing... Agent: Whyte Hirschboeck Dudek S.c.

20060289952 - Method of composite gate formation: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing... Agent: Whyte Hirschboeck Dudek S.c.

20060289953 - Semiconductor device and manufacturing method of the same: A semiconductor device includes a first semiconductor layer of a first conductivity type, a first gate insulating film, a first gate electrode and first source/drain regions. The first gate insulating film is formed on the first semiconductor layer. The first gate electrode is formed on the first gate insulating film.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060289954 - Method for processing a mems/cmos cantilever based memory storage device: A method is disclosed. The method includes fabricating microelectromechanical (MEMS) structures of a Seek and Scan Probe (SSP) memory device on a first wafer, and fabricating CMOS and memory medium components of the SSP memory device on a second wafer.... Agent: Blakely Sokoloff Taylor & Zafman

20060289955 - Semiconductor composite device and method of manufacturing the same: The present invention provides a semiconductor composite device including a semiconductor device formed on or in a substrate, an insulating film formed on the substrate so as to cover the semiconductor device, a micro electro mechanical portion formed on the insulating film, and a wiring layer connected to the semiconductor... Agent: Sonnenschein Nath & Rosenthal LLP

20060289956 - Process for creating tilted microlens: A microlens structure that includes a wedge formed to support and tilt the microlens is disclosed. The wedge results from heating a layer of patterned flowable material. The degree and direction of incline given to the wedge can be controlled in part by the type of patterning that is performed.... Agent: Dickstein Shapiro LLP

20060289957 - Germanium/silicon avalanche photodetector with separate absorption and multiplication regions: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of... Agent: Blakely Sokoloff Taylor & Zafman

20060289958 - Color filter and image pickup apparatus including the same: Provided is a color filter, including a plurality of filter units arranged at predetermined intervals, in which each of filter units includes a red transmission filter for red light transmission, a first green transmission filter for first green light transmission, a second green transmission filter for second green light transmission... Agent: Morgan & Finnegan, L.L.P.

20060289959 - Yield improvement in silicon-germanium epitaxial growth: A method for determining a SiGe deposition condition so as to improve yield of a semiconductor structure. Fabrication of the semiconductor structure starts with a single-crystal silicon (Si) layer. Then, first and second shallow trench isolation (STI) regions are formed in the single-crystal Si layer. The STI regions sandwich and... Agent: Schmeiser, Olsen & Watts

20060289960 - Structure improvement of depletion region in p-i-n photodiode: The present invention with a structure of depletion region improves the product of output power and bandwidth of a photodetector and prevents the drifting velocity of electron from slowing down under a bias, which can be applied to a photodetector of communicative wavelength over optical fiber.... Agent: Troxell Law Office PLLC

20060289961 - Semiconductor device: A semiconductor device including: a semiconductor layer; a transistor formed in the semiconductor layer and including a gate insulating layer and a gate electrode, the transistor being a high voltage transistor in which an insulating layer having a thickness greater than the thickness of the gate insulating layer is formed... Agent: Harness, Dickey & Pierce, P.L.C

20060289962 - An isolation region for use in a semiconductor device: An isolation region for use in a semiconductor device is formed in a p-type silicon substrate. An n-type silicon layer is disposed on the p-type silicon substrate, wherein the n-type silicon layer is separated by an oxidized porous silicon layer. At least a portion of the oxidized porous silicon layer... Agent: VistaIPLaw Group LLP

20060289963 - Compound semiconductor device: A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending from the direct current terminal... Agent: Morrison & Foerster LLP

20060289964 - Spacecraft regulation unit with decentralized bus capacitance: A Spacecraft Regulation Unit SRU or Power Conditioning Unit PCU with decentralized capacitance comprising several power conversion modules each coupled, via interconnection means, to a high-level power bus for supplying power to equipment of a satellite. Each power conversion module has a bus capacitor (Cmod) coupled via the interconnection means... Agent: Sughrue Mion, PLLC

20060289965 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer;... Agent: Michael A. Cantor

20060289966 - Silicon wafer with non-soluble protective coating: A silicon wafer with an array of integrated circuit (IC) dies formed on the wafer is provided with a protective coat applied to a surface of the wafer to protect the IC dies from debris created during a laser scribing process. The IC dies can include die bumps that can... Agent: Marger Johnson & Mccollom, P.C.

20060289968 - Conductive interconnect structures and formation methods using supercritical fluids: Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via having a width and a length generally transverse to the width, and with a length being approximately 100 microns... Agent: Perkins Coie LLP Patent-sea

20060289967 - Through-wafer vias and surface metallization for coupling thereto: An apparatus and method of fabricating a through-wafer via. A first mask is formed over a first side of a first semiconductor die to define a first via area. A deep recess is etched through the first semiconductor die in the first via area and a blanket metal layer is... Agent: Blakely Sokoloff Taylor & Zafman

20060289969 - Laser assisted material deposition: Electronic devices and systems are provided with material structured from irradiation of a gas precursor with electromagnetic energy at a frequency tuned to an absorption frequency of the gas precursor. The frequency of the electromagnetic energy may be selected to impart specific amounts of energy to a gas precursor at... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060289970 - Magnetic shielding of mram chips: An apparatus comprising a magnetically shielded MRAM chip and a method of manufacturing the same. The apparatus includes an MRAM module and a protective cover. The MRAM module includes a circuit board and a memory chip attached to the circuit board, the memory chip containing magnetoresistive random access memory (MRAM)... Agent: Slater & Matsil LLP

20060289973 - Lead frame for semiconductor package: A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the... Agent: Stetina Brunda Garred & Brucker

20060289972 - Semiconductor device: A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060289971 - Semiconductor device having firmly secured heat spreader: A semiconductor device comprising a leadframe (903), which has first (903a) and second (903b) surfaces, a planar pad (910) of a certain size, and a plurality of non-coplanar members (913) adjoining the pad. The device further has a heat spreader (920) with first (920a) and second (920b) surfaces, a planar... Agent: Texas Instruments Incorporated

20060289974 - Reliable integrated circuit and package: A packaged integrated circuit which includes a die 700 having a surface and corners separated by edges. The die surface includes depressions 600, 720 so that mold compound 114 covering the die surface fills the depressions. The filling of the depressions in the die surface enhances the adhesion of the... Agent: Texas Instruments Incorporated

20060289975 - Alignment using fiducial features: The present invention relates to positioning components of an assembly using fiducial features. A first fiducial feature on a first piece of the assembly can be located. A first component can be positioned on the first piece of the assembly based on the location of the first fiducial feature. A... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20060289977 - Lead-free semiconductor package: A package substrate includes die solder pads and pin solder fillets. The pin solder fillets might comprise between approximately 90 wt % to approximately 99 wt % tin and approximately 10 wt % to 1 wt % antimony. The die solder pads might comprise between approximately 4 wt % to... Agent: Farjami & Farjami LLP

20060289978 - Memory element conducting structure: Disclosed is a memory element conducting structure, which includes a substrate with contacts, hollow sockets provided at the top side of the substrate corresponding to the contacts of the substrate, conducting media respectively mounted in the hollow sockets and supported on the contacts, and a plurality of positioning means respectively... Agent: Optimum Care International Tech. Inc.

20060289976 - Pre-patterned thin film capacitor and method for embedding same in a package substrate: An embedded passive structure, its method of formation, and its intergration onto a substrate during fabrication are disclosed, In one embodiment the embedded passive structure is a thin film capacitor (TFC) formed using a thin film laminate that has been mounted onto a substrate. The TFC's capacitor dielectric and/or lower... Agent: Blakely Sokoloff Taylor & Zafman

20060289979 - Bridge modules for smart labels: The invention relates to module bridges for smart labels for positioning chip modules (5) on carries (12) and for the bridging connection of connection elements of the chip modules (5) to connection elements (11a, 11b) of antenna elements (11) arranged on or in the carriers (12), a plurality of module... Agent: Black Lowe & Graham, PLLC

20060289980 - Stacked memory card and method for manufacturing the same: A structure of stacked memory card, the structure includes a substrate, a lower chip, wires, adhered element, upper chip, and compound resin. The substrate has an upper surface formed with a plurality of first electrodes, and a lower surface. The B-stage glue is coated on the upper surface of the... Agent: Pro-techtor International

20060289981 - Packaging logic and memory integrated circuits: Logic and memory may be packaged together in a single integrated circuit package that, in some embodiments, has high input/output pin count and low stack height. In some embodiments, the logic may be stacked on top of the memory which may be stacked on a flex substrate. Such a substrate... Agent: Trop Pruner & Hu, PC

20060289982 - Semiconductor device and method for producing same: A semiconductor device is provided and includes: an interlayer insulating layer and a wiring layer provided above a surface of a semiconductor substrate having an element region. At least a portion of the interlayer insulating layer containing impurities in contact with the wiring layer has been removed at the edge... Agent: Birch Stewart Kolasch & Birch

20060289983 - System, method and device for reducing electromagnetic emissions and susceptibility from electrical and electronic devices: A system, device, and method are provided to analyze and provide recommendations regarding electrical noise in circuitry. A rule and algorithm-based recommendation generator may be used to analyze electrical noise at the schematic design stage. The engineer is provided with detailed recommendations of changes to the schematic diagram of the... Agent: Bourque & Associates Intellectual Property Attorneys, P.A.

20060289984 - Lead contact structure for emr elements: EMR elements and methods of fabricating the EMR elements are disclosed. The EMR structure includes one or more layers that form an active region, such as a two-dimensional electron gas (2DEG). The EMR structure has a first side surface, having a plurality of lead protrusions that extend outwardly from the... Agent: Duft Bornsen & Fishman, LLP

20060289985 - Glass lid, and package provided with such a lid, for the encapsulation of electronic components: The encapsulation lid comprises at least two glass layers of different compositions, a first layer called the bottom layer, which is continuous, and at least a second layer, which is discontinuous and designed so as to define cavities or anfractuosities in this lid. Preferably, the glass layers other than the... Agent: Thomson Licensing Inc.

20060289986 - In-package connection between integrated circuit dies via flex tape: An integrated circuit (IC) package includes a package substrate and a cap attached to the package substrate. The package substrate and the cap define a space therebetween. The IC package also includes a section of flex tape housed in the space defined by the cap and the package substrate.... Agent: Buckley, Maschoff, Talwalkar LLC

20060289987 - Microelectronic die cooling device including bonding posts and method of forming same: A microelectronic assembly and a method of forming same. The microelectronic assembly comprises: a microelectronic package including a substrate and a die, the die being electrically conductively bonded to the substrate at a front side thereof and further having a backside; a cover plate defining an inlet opening and an... Agent: Blakely Sokoloff Taylor & Zafman

20060289988 - Integrated circuit with heat conducting structures for localized thermal control: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first... Agent: Ryan, Mason & Lewis, LLP

20060289989 - Intrinsic thermal enhancement for fbga package: A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the device, and methods of fabricating the device and package are provided. In one embodiment, the semiconductor device comprises a thick thermally conductive plane (e.g., copper plane)... Agent: Whyte Hirschboeck Dudek S.c.

20060289990 - Apparatus and method for high density multi-chip structures: Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. Another advantage of this design includes shorter distances for interconnection pathways, which... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060289991 - Semiconductor device and manufacturing method of the same: The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode formed on a semiconductor substrate with insulation films interposed therebetween, a plating layer formed on the pad electrode, a conductive terminal formed on the plating layer and electrically connected with the pad... Agent: Morrison & Foerster LLP

20060289992 - Stacked semiconductor component, fabrication method and fabrication system: A semiconductor component includes a carrier and multiple semiconductor substrates stacked and interconnected on the carrier. The carrier includes conductive members bonded to corresponding conductive openings on the semiconductor substrates. The component can also include terminal contacts on the carrier in electrical communication with the conductive members, and an outer... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20060289993 - Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow: A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor.... Agent: Whyte Hirschboeck Dudek S.c.

20060289995 - Interconnection device including one or more embedded vias and method of producing the same: Briefly, some demonstrative embodiments of the present invention include an interconnection device, e.g., a Systems In Package (SIP) device, or Systems In Chip (SIC) device, including one or more embedded vias. Some demonstrative embodiments of the invention include a process to produce the interconnection device. Other embodiments are described and... Agent: Pearl Cohen Zedek Latzer, LLP

20060289994 - Multi-level interconnections for an integrated circuit chip: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts... Agent: Ibm Microelectronics Intellectual Property Law

20060289996 - Semiconductor device: A semiconductor device includes a first wiring line group made of a metal, wiring lines of the first wiring line group being arranged in parallel with each other, a second wiring line group which is made of a semiconductor and crosses the first wiring line group, wiring lines of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060289997 - Semiconductor device: The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289998 - Semiconductor device and a method of manufacturing the same: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in... Agent: Miles & Stockbridge PC

20060289999 - Selective copper alloy interconnections in semiconductor devices and methods of forming the same: A selective copper alloy interconnection in a semiconductor device is provided. The interconnection includes a substrate, a dielectric formed on the substrate, and a first interconnection formed in the dielectric. The first interconnection has a first pure copper pattern. In addition, a second interconnection having a larger width than the... Agent: Myers Bigel Sibley & Sajovec

20060290000 - Composite metal layer formed using metal nanocrystalline particles in an electroplating bath: A method for forming a composite metal layer on a substrate comprises providing nanocrystalline particles of a first metal, adding the nanocrystalline particles to a plating bath that contains ions of a second metal to form a colloid-like suspension, immersing the substrate in the plating bath, and causing a co-deposition... Agent: Blakely Sokoloff Taylor & Zafman

20060290001 - Interconnect vias and associated methods of formation: Interconnect vias and associated methods of formation are disclosed. One such method includes forming an operable microelectronic feature in a substrate, with the substrate having a first surface and a second surface facing away from the first surface. The method can further include forming a via in the substrate at... Agent: Perkins Coie LLP Patent-sea

20060290002 - Method of forming through-silicon vias with stress buffer collars and resulting devices: A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.... Agent: Intel Corporation

20060290003 - Substrate structure and manufacturing method of the same: A Ti film is pattern-formed on a desired portion on a silicon substrate, and a Co film is formed on the substrate so as to cover the Ti film. CNTs are formed only on a portion, under which the Ti film is formed, of the surface of the Co film... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20060290005 - Multi-chip device and method for producing a multi-chip device: The present invention relates to a multi-chip device comprising a substrate having a first surface on which a number of first contact elements is provided, a plurality of integrated circuit chips arranged in a chip stack which is arranged on a second surface of the substrate opposing the first surface,... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies

20060290004 - Semiconductor device: In the case where a first semiconductor chip 100 and a second semiconductor chip 200 are stacked, both the semiconductor chips 100 and 200 are connected using micro bumps, in which a circuit block in the first semiconductor chip and a circuit block in the second semiconductor chip are connected... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060290007 - Flip chip die assembly using thin flexible substrates: Apparatus and methods for flattening thin substrate surfaces by stretching thin flexible substrates to which ICs can be bonded. Various embodiments beneficially maintain the substrate flatness during the assembly process through singulation. According to one embodiment, the use of a window frame type component carrier allows processing of thin laminates... Agent: Faegre & Benson LLP Patent Docketing

20060290006 - Semiconductor package: A semiconductor package includes a combination die embedded in a base. The combination die includes a plurality of functional blocks, where the functional blocks are insulated from one another on the combination die. Each functional block has plural die connectors. The base includes insulating layers conductive layers and vias. Each... Agent: Harrington & Smith, LLP

20060290008 - Smt passive device noflow underfill methodology and structure: An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. The SMD, having a pair of electrical contacts, is pressed into... Agent: John A. Jordan, Esq.

20060290009 - Semiconductor device and method for manufacturing the same: A semiconductor device (1) of the present invention includes a semiconductor element (103) including electrode parts (104), and a wiring substrate (108) including an insulation layer (101), electrode-part-connection electrodes (102) provided in the insulation layer (101), and external electrodes (107) that is provided in the insulation layer (101) and that... Agent: Hamre, Schumann, Mueller & Larson P.C.

20060290010 - Method of embedding semiconductor chip in support plate and embedded structure thereof: A method of embedding a semiconductor chip in a support plate and an embedded structure thereof are proposed. A first dielectric layer having a reinforced filling material is provided, and a semiconductor chip is mounted on the first dielectric layer. A support plate having an opening and a second dielectric... Agent: Clark & Brody

20060290011 - Molded stiffener for thin substrates: A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is molded to the substrate to provide rigidity and support to the substrate. The stiffener material can comprise a polymeric material molded to the substrate... Agent: Whyte Hirschboeck Dudek S.c.

20060290012 - Multiple mask process with etch mask stack: A method for forming etch features in an etch layer over a substrate is provided. An etch mask stack is formed over the etch layer. A first mask is formed over the etch mask stack. A sidewall layer is formed over the first mask, which reduces the widths of the... Agent: Beyer Weaver & Thomas, LLP

20060290013 - Method for chemical vapor deposition in high aspect ratio spaces: A method of depositing conformal film into high aspect ratio spaces includes the step of forming a gradient of precursor gas inside the space(s) prior to deposition. The gradient may be formed, for example, by reducing the pressure within the deposition chamber or by partial evacuation of the deposition chamber.... Agent: VistaIPLaw Group LLP

20060284155 - Switching device: A switching device in which an organic bistable material layer containing an organic bistable compound having two types of stable resistance against an applied voltage is provided between at least two electrodes. In the switching device, a first electrode layer, an electric charge injection suppressing layer, an organic bistable material... Agent: Rossi, Kimms & Mcdowell LLP.

20060284156 - Phase change memory cell defined by imprint lithography: A memory cell includes a first electrode, a second electrode, and a phase-change material between the first electrode and the second electrode. A minimum cross-sectional area of a current path between the first electrode and the second electrode is defined by an imprint lithography process.... Agent: Dicke, Billig & Czaja, P.l.l.c.

20060284158 - Self-aligned, embedded phase change ram and manufacturing method: An integrated circuit with an embedded memory comprises a substrate and a plurality of conductor layers arranged for interconnecting components of the integrated circuit. An intermediate layer in the plurality of conductor layers includes a first electrode having a top surface, a second electrode having a top surface, an insulating... Agent: Macronix C/o Haynes Beffell & Wolfeld LLP

20060284157 - Thin film plate phase change ram circuit and manufacturing method: A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first... Agent: Macronix C/o Haynes Beffell & Wolfeld LLP

20060284159 - Phase change memory device and method for manufacturing the same: A phase change memory device reduces the current necessary to cause a phase change of a phase change layer. The phase change memory device includes a first oxide layer formed on a semiconductor substrate; a lower electrode formed inside the first oxide layer; a second oxide layer formed on the... Agent: Ladas & Parry LLP

20060284160 - Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof: A contact structure for a PCM device is formed by an elongated formation having a longitudinal extension parallel to the upper surface of the body and an end face extending in a vertical plane. The end face is in contact with a bottom portion of an active region of chalcogenic... Agent: Seed Intellectual Property Law Group PLLC

20060284161 - Light source module and vehicle lamp: A light source module is provided with a semiconductor light emitting element disposed in a hollow airtight region within a cover fixed to a circuit board, and electrodes which are disposed outside of the airtight region and supplies a current to the semiconductor light emitting element. The circuit board is... Agent: Sughrue Mion, PLLC

20060284162 - Programmable optical component for spatially controlling the intensity of beam of radiation: A programmable optical component (10) for spatially controlling the intensity of a beam of radiation (b), which component comprises a programmable layer which is divided in programmable elements (4,6,8), characterized in that each programmable element comprises bendable nano-elements (8) which are switchable between a non-bend state (8) and a bend... Agent: Philips Intellectual Property & Standards

20060284163 - Single elog growth transverse p-n junction nitride semiconductor laser: A vertical quantum well nitride laser-can be fabricated by ELOG (epitaxial lateral overgrowth), with the vertical quantum wells created by deposition over the vertical a-face of the laterally growing edges and forming the transverse junction in a single ELOG-MOCVD (metal organic chemical vapor deposition) growth step. Vertical quantum wells may... Agent: Avago Technologies, Ltd.

20060284164 - Strained germanium field effect transistor and method of making the same: A strained germanium field effect transistor (FET) and method of making the same, comprise forming a germanium layer on a substrate, then forming a Si protective layer on the germanium layer, next forming a gate insulation layer on the Si protective layer, and fmally positioning a gate on the gate... Agent: Harness, Dickey & Pierce, P.L.C

20060284165 - Silicon-based backward diodes for zero-biased square law detection and detector arrays of same: A Si-based diode (10, 10′, 100) is formed by epitaxially depositing a Si-based diode structure on a silicon substrate. The Si-based diode structure includes a Si-based pn junction (16, 16′, 18, 18′, 30, 32, 160, 161) having a backward diode current-voltage characteristic in which the forward tunneling current is substantially... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20060284168 - Light emitting device: The present invention relates to a light emitting device, particularly to an organic electroluminescent device, that a part of data lines includes a first conduction layer and an insulation layer formed on a substrate in sequence. The light emitting device includes a substrate, a plurality of anode electrode layers disposed... Agent: Fleshner & Kim, LLP

20060284169 - Method of patterning nano conductive film: A donor substrate for forming a nano conductive film includes a base substrate and a transferring layer that is disposed on the base substrate. The transferring layer includes nano conductive particles and an organic semiconductor. A method of patterning a nano conductive film is provided, wherein a donor substrate in... Agent: Robert E. Bushnell

20060284167 - Multilayered substrate obtained via wafer bonding for power applications: A multi-layer semiconductor device utilizes the good thermal and electrical properties of a polycrystalline substrate with the electrical properties of single crystal film transferred via wafer bonding. The device structure includes a polycrystalline, e.g., silicon carbide substrate, which was polished. A planarization layer of silicon is formed on the surface,... Agent: Birch Stewart Kolasch & Birch

20060284166 - Polymer transistor: A transistor including a semiconductive layer; and a gate dielectric layer comprising an insulating polymer, characterised in that the insulating polymer is crosslinked and comprises one or more units having a low cohesive-energy-density and one or more crosslinking groups and the insulating polymer includes substantially no residual —OH leaving groups.... Agent: Sughrue Mion, PLLC

20060284170 - Transparent light-emitting component: The invention concerns a transparent light-emitting component, in particular an organic light-emitting diode (OLED), with a layer arrangement in which a light-emitting organic layer is arranged between an upper and a lower electrode, the layer arrangement being transparent in a switched-off state and emitting light which is produced in