Active solid-state devices (e.g., transistors, solid-state diodes) inventions 12/06

20060289847 - Reducing the time to program a phase change memory to the set state: A phase change memory may be formed with a chalcogenide layer that contains titanium. The titanium reduces the crystallization time. Set state resistance may also be decreased, thereby reducing the access time of the semiconductor memory, in some embodiments.... Agent: Trop Pruner & Hu, PC

20060289849 - Composition for forming porous film, porous film and method for forming the same, interlevel insulator film, and semiconductor device: The invention includes a semiconductor device. Specifically provided is a semiconductor device comprising a porous film therein, the porous film being formable by a composition comprising a surfactant, an aprotic polar solvent and a solution comprising a polymer formed by hydrolysis and condensation of one or more silane compounds represented... Agent: Alston & Bird LLP

20060289850 - Phase change memory and phase change recording medium: A phase change memory comprises: a substrate; an insulation film formed on a main surface of the substrate; a first electrode deposited on the insulation film; a phase change recording film deposited on the first electrode; and a second electrode deposited on the phase change recording film. The phase change... Agent: Antonelli, Terry, Stout & Kraus, LLP

20060289848 - Reducing oxidation of phase change memory electrodes: A phase change memory may be formed in a way which reduces oxygen infiltration through a chalcogenide layer overlying a lower electrode. Such infiltration may cause oxidation of the lower electrode which adversely affects performance. In one such embodiment, an etch through an overlying upper electrode layer may be stopped... Agent: Trop Pruner & Hu, PC

20060289851 - Resistance variable memory device and method of fabrication: Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least one chalcogenide glass layer. The invention also relates to methods of forming such a... Agent: Dickstein Shapiro LLP

20060289852 - Bipolar transistor with collector having an epitaxial si:c region: A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region... Agent: Scully, Scott, Murphy & Pressner

20060289853 - Apparatus for manufacturing a quantum-dot element: An apparatus for manufacturing a quantum-dot element is disclosed. The apparatus includes a reaction chamber for evaporating or sputtering at least one electrode layer or at least one buffer layer on the substrate. The substrate-supporting base is located inside the reaction chamber for fixing the substrate. The atomizer has a... Agent: Bacon & Thomas, PLLC

20060289854 - Optical semiconductor device with multiple quantum well structure: An optical semiconductor device with a multiple quantum well structure, in which well layers and barrier layers comprising various types of semiconductor layers are alternately layered, in which device well layers (6a) of a first composition based on a nitride semiconductor material with a first electron energy and barrier layers... Agent: Fish & Richardson PC

20060289855 - Quantum dot based optoelectronic device and method of making same: A method of forming an optically active region on a silicon substrate includes the steps of epitaxially growing a silicon buffer layer on the silicon substrate and epitaxially growing a SiGe cladding layer having a plurality of arrays of quantum dots disposed therein, the quantum dots being formed from a... Agent: VistaIPLaw Group LLP

20060289856 - Semiconductor device and production method thereof: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060289859 - Method for forming a stacked structure of an insulating layer and an organic semiconductor layer, organic field effect transistor and method for making same: A method for making an organic field effect transistor of a bottom gate/bottom contact type or a bottom gate/top contact type is provided. The method comprises (a) forming a gate electrode 12 on a support and forming a gate insulating layer 13 on the support 10 and the gate electrode... Agent: Bell, Boyd & Lloyd, LLC

20060289857 - Organic light emitting display capable of showing images on double sides thereof: An organic light emitting display (OLED) has a substrate, on two opposite sides of which a fist electrode, an organic layer and a second electrode are stacked in sequence respectively. To prevent the light of the organic layers at the opposite sides of the substrate from interference, the substrate or... Agent: Bacon & Thomas, PLLC

20060289858 - Organic thin film transistor(s) and method(s) for fabricating the same: Example embodiments of the present invention for fabricating an organic thin film transistor including a substrate, a gate electrode, a gate insulating layer, metal oxide source/drain electrodes and an organic semiconductor layer wherein the metal oxide source/drain electrodes are surface-treated with a self-assembled monolayer (SAM) forming compound containing a sulfonic... Agent: Harness, Dickey & Pierce, P.L.C

20060289860 - Semiconductor layer: The semiconductor layer includes a β-Ga2O3 substrate 1 made of a β-Ga2O3 single crystal, a GaN layer 2 formed by subjecting a surface of the β-Ga2O3 substrate 1 to nitriding processing, and a GaN growth layer 3 formed on the GaN layer 2 through epitaxial growth by utilizing an MOCVD... Agent: Mcginn Intellectual Property Law Group, PLLC

20060289863 - Semiconductor device evaluation apparatus and semiconductor device evaluation method: An apparatus for evaluating a field-effect transistor includes a pulse generator, a current/voltage converter, a switch and a first constant-voltage source. The pulse generator can be electrically connected to a gate electrode of a field-effect transistor. The current/voltage converter includes an input terminal. The input terminal can be electrically connected... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060289861 - Systems and arrangements to interconnect components of a semiconductor device: Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density are disclosed. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20060289862 - Systems and methods for thermal sensing: Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional... Agent: Law Offices Of Mark L. Berrier

20060289864 - High impedance antifuse: A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the... Agent: Ibm Microelectronics Intellectual Property Law

20060289866 - Electro-optic display and manufacturing method thereof: A pixel electrode is disposed to cover the inner surfaces of a pixel-drain contact hole passing through a third insulating film and a second insulating film to reach a drain electrode. At the bottom of the pixel-drain contact hole, the pixel electrode is electrically connected with the drain electrode through... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289868 - Flat panel display and method for driving the same: A flat panel display for preventing a thin film transistor from deteriorating due to voltage, static electricity, and external force, accidentally applied to a substrate, and a method for driving the same. The flat panel display includes a conductive substrate, at least one insulating layer formed on the conductive substrate,... Agent: Christie, Parker & Hale, LLP

20060289867 - Liquid crystal display device capable of reducing leakage current, and fabrication method thereof: The present invention discloses a liquid crystal display device which can improve quality of image by reducing a leakage current by a backlight, and a fabrication method thereof. The liquid crystal display device includes: first and second substrates; a plurality of gate lines aligned on the first substrate in a... Agent: Mckenna Long & Aldridge LLP

20060289865 - Method of manufacturing a semiconductor device: TFT structures optimal for driving conditions of a pixel portion and driving circuits are obtained using a small number of photo masks. First through third semiconductor films are formed on a first insulating film. First shape first, second, and third electrodes are formed on the first through third semiconductor films.... Agent: Eric Robinson

20060289869 - Semi-transparent tft array substrate, and semi-transparent liquid crystal display: A contrast reduction preventive electrode is formed in a reflective region, and in the same layer as a transparent pixel electrode. A connection for connecting the contrast reduction preventive electrode and the transparent pixel electrode is formed, in such a position that the connection does not overlap an auxiliary capacitive... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289871 - Thin film transistor substrate and method of manufacturing the same: A thin film transistor (TFT) substrate having an improved wire structure without an under-cut phenomenon that may occur during formation of a gate wire having a double-layered structure and a method of manufacturing the same are provided, where the method includes forming a first metal layer made of at least... Agent: F. Chau & Associates, LLC

20060289870 - Thin film transistor substrate and production method thereof: A method for producing a thin film transistor substrate includes the steps of: (i) depositing an amorphous semiconductor film on a transparent insulating substrate; (ii) patterning the amorphous semiconductor film so as to form insular amorphous semiconductor films, the step (ii) including a process (I) for forming, in respective stripe... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20060289872 - Wiring substrate, electronic device, electro-optical device, and electronic apparatus: The invention achieves stable performance, such as low parasitic capacitance generated at conductive components. Components having a low dielectric constant of 4 or less are disposed on a base member. Functional films partitioned by the low-dielectric-constant components are also provided.... Agent: Oliff & Berridge, PLC

20060289873 - Semiconductor devices and methods of making same: A composite structure having a silicon carbide epitaxial layer is provided. The epitaxial layer includes at least four regions arranged vertically and defining respective interfaces, where each of the regions is characterized by a respective impurity concentration, where the impurity concentrations vary across each of the interfaces, and where each... Agent: Patrick S. Yoder Fletcher Yoder

20060289874 - Silicon carbide devices with hybrid well regions: MOS channel devices and methods of fabricating such devices having a hybrid channel are provided. Exemplary devices include vertical power MOSFETs that include a hybrid well region of silicon carbide and methods of fabricating such devices are provided. The hybrid well region may include an implanted p-type silicon carbide well... Agent: Myers Bigel Sibley & Sajovec

20060289875 - Light emitting diode and method making the same: A light emitting diode and the method of the same are provided. The light emitting diode includes a substrate, a thermal spreading layer, a connecting layer and an epitaxial structure. The substrate is selected from a transparent substrate or a non-transparent substrate, which corresponds to different materials of the connecting... Agent: Snell & Wilmer

20060289876 - Methods of combining silicon and iii-nitride material on a single wafer: A semiconductor device that includes one semiconductor device formed in one semiconductor material and a second semiconductor device formed in another semiconductor material on a common substrate, and a method of fabricating the semiconductor device.... Agent: Ostrolenk Faber Gerb & Soffen

20060289877 - Semiconductor device: The barrier φb between the Fermi level Ef of Se and the valence band of the wide band gap p-type semiconductor becomes the lowest by including the Se layer in the p-type ohmic electrode, and an ohmic contact is achieved that has a resistance far lower than that obtained when... Agent: Steptoe & Johnson LLP

20060289879 - Dual-face display apparatus, systems, and methods: Apparatus and systems, as well as methods and articles, may operate to display image information from one side of a light-emitting material layer disposed between a pair of non-opaque electrodes. The image information may be displayed through a transparent substrate, perhaps adjacent a conductive silicon layer, adjacent one of the... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060289880 - Illuminating device and display device including the same: Provided is a display device including: a light guide member for mixing light from a blue LED element coated with a translucent resin mixed with phosphor particles which converts blue light into green light with light from a red LED element to make white light exit from a light exit... Agent: Bruce L. Adams, Esq.

20060289878 - White-emitting led having a defined color temperature: LED with a low color temperature up to 3500 K, comprising a blue-emitting LED with two phosphors in front of it, a first phosphor from the class of the oxynitridosilicates, having a cation M, which is doped with divalent Europium, and has the empirical formula M(1-c)Si2O2N2:Dc, with M=Sr, or M=Sr(1-x-y)BayCax... Agent: Cohen, Pontani, Lieberman & Pavane

20060289881 - Semiconductor light emitting device: A semiconductor light emitting device including a substrate, a semiconductor light emitting stack, a first electrode, a first transparent oxide conductive layer and a second electrode is provided. The semiconductor light emitting stack is disposed on the substrate and has a first surface region and a second surface region. The... Agent: Jianq Chyun Intellectual Property Office

20060289882 - Organic electroluminescent element and organic electroluminescent display device: An organic electroluminescent element comprising a cathode, an anode, an intermediate unit arranged between a cathode and an anode, a first light emitting unit arranged between a cathode and an intermediate unit, and a second light emitting unit arranged between an anode and an intermediate unit, wherein an electron extracting... Agent: Mcdermott Will & Emery LLP

20060289883 - Light emitting device having protrusion and recess structure and method of manufacturing same: The semiconductor light emitting device having a protrusion and recess structure includes: a lower clad layer disposed on a substrate; an active layer formed on one portion of a top surface of the lower clad layer; an upper clad layer formed on the active layer; a first electrode formed on... Agent: Buchanan, Ingersoll & Rooney PC

20060289885 - Light-emitting diode: A light-emitting diode (LED) is described. The light-emitting diode has a light-emitting diode chip and a package structure covering the light-emitting diode chip. A surface of the package structure has a pattern structure, in which the pattern structure includes a plurality of stria structures for controlling a light shape output... Agent: Sughrue Mion, PLLC

20060289884 - Luminescent sheet covering for leds: A lighting apparatus comprising at least one light emitting diode is disposed on an interconnect board to emit ultraviolet or blue radiation. A polymeric layer including a luminophor is disposed about the lighting apparatus to convert at least a portion of the radiation emitted from the LED into visible light.... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20060289886 - Semiconductor light emitting device: A semiconductor light emitting device comprises: a semiconductor multilayer structure including a light emitting layer, a first semiconductor layer and a second semiconductor layer; a first electrode that forms ohmic contact with the first semiconductor layer in the semiconductor multilayer structure; a second electrode that forms ohmic contact with the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289889 - Display device and manufacturing method thereof: It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel, and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid... Agent: Eric Robinson

20060289888 - Packaging of smd light emitting diodes: An SMD LED package with superior thermal dissipation capability is provided. The SMD LED package comprises a supporting block with circuit patterns and at least one LED attached to the supporting block. Wherein, circuit patterns of holes/vias, insulating layers, and conducting traces/pads are formed on and in the supporting block.... Agent: Lin & Associates Intellectual Property

20060289887 - Surface mount light emitting diode (led) assembly with improved power dissipation: A high performance LED (402) and associated semiconductor package (400) advantageously utilizes an integrated heat sink (408) for purposes of power dissipation. At a next level of assembly, (500, 600) the semiconductor package (400) is electromechanically coupled to a printed circuit board (300). The printed circuit board (300) has a... Agent: Miller Johnson Snell Cummiskey, PLC

20060289890 - Light emitting device: A light emitting device includes: a first LED that emits a first primary light in a first primary wavelength range when activated; a second LED that emits a second primary light in a second primary wavelength range when activated, the second primary wavelength range differing from the first primary wavelength... Agent: Ladas & Parry Suite 2100

20060289891 - Electronic and/or optoelectronic devices grown on free-standing gan substrates with gan spacer structures: A GaN-based electronic and/or optoelectronic device formed on a free-standing GaN substrate, wherein a thick GaN spacer layer is provided between the device and the substrate, thereby separating the active region of the electronic and/or optoelectronic device from high impurity content at the substrate-epitaxial interface and reducing the detrimental impact... Agent: Intellectual Property / Technology Law

20060289892 - Method for preparing light emitting diode device having heat dissipation rate enhancement: A method for fabricating an LED having section grown on a sapphire substrate, a boded structure, and a unit chip separated from the bonded structure. The method includes (a) bonding the section grown on a first surface of the sapphire substrate to a first surface of a first substrate with... Agent: Mckenna Long & Aldridge LLP

20060289893 - Display device and driving apparatus having reduced pixel electrode discharge time upon power cut-off: A driving apparatus of a display device including a plurality of switching elements and a plurality of pixel electrodes connected to the switching elements is provided, in which the apparatus includes a gate-off voltage generator for generating a gate-off voltage and a gate driver for outputting the gate-off voltage from... Agent: Att: Patent Group Kieun "jenny" Sung

20060289894 - Semiconductor device: A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1−xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1−N; and a source electrode, a drain electrode and a gate... Agent: Mcdermott Will & Emery LLP

20060289895 - Semiconductor device: A semiconductor device includes a channel region, an oxide film, a gate electrode and source/drain regions. The channel region includes Ge. The oxide film is formed on the channel region. The oxide film includes Si and a metallic element M selected from the group consisting of Zr, Hf, La, Ce,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060289896 - Semiconductor device and method for fabricating the same: A semiconductor device has an interconnect layer for providing an electric connection between a base electrode and a base terminal provided on the region of a semi-insulating substrate on which a transistor is not formed. A resistor layer composed of a material different from respective materials composing the base electrode... Agent: Mcdermott Will & Emery LLP

20060289897 - Semiconductor device: A semiconductor device includes a first power supply which is disposed in a first direction, a first pad array which is disposed in the first direction, adjacent to the first power supply line, a second power supply line extending in the first direction, a first buffer circuit which is disposed... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289898 - Semiconductor device and fuse blowout method: A fuse includes a fuse portion laid in such a manner that the direction of each turn of the fuse portion is parallel to the direction in which pads are arranged. The distance between the pads and the fuse portion is defined as the distance between the side of a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289899 - Semiconductor devices having fuses and methods of forming the same: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be... Agent: Harness, Dickey & Pierce, P.L.C

20060289900 - Methods for forming a transistor and creating channel stress: Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stress in PMOS and NMOS transistors.... Agent: Scott S. Servilla Applied Materials, Inc.

20060289901 - Integrated nitride and silicon carbide-based devices and methods of fabricating integrated nitride-based devices: A monolithic electronic device includes a first nitride epitaxial structure including a plurality of nitride epitaxial layers. The plurality of nitride epitaxial layers include at least one common nitride epitaxial layer. A second nitride epitaxial structure is on the common nitride epitaxial layer of the first nitride epitaxial structure. A... Agent: Myers Bigel Sibley & Sajovec

20060289902 - Method for forming raised structures by controlled selective epitaxial growth of facet using spacer: Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of monocrystalline silicon on the surface of a semiconductive substrate, and forming a thin film... Agent: Whyte Hirschboeck Dudek S.c.

20060289903 - Method of forming metal/high-k gate stacks with high mobility: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate... Agent: Scully Scott Murphy & Presser, PC

20060289908 - Field effect device with a channel with a switchable conductivity: A field effect device includes a source electrode, a drain electrode, a channel formed between the source electrode and the drain electrode, and a gate electrode formed directly on the channel and arranged in a gap between the source electrode and the drain electrode. The channel includes a switching material... Agent: Ryan, Mason & Lewis, LLP

20060289907 - Metal oxide semiconductor (mos) transistors having buffer regions below source and drain regions and methods of fabricating the same: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region.... Agent: Myers Bigel Sibley & Sajovec

20060289909 - Self-aligned low-k gate cap: A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric... Agent: Scully Scott Murphy & Presser, PC

20060289905 - Semiconductor device: A semiconductor device comprising at least one FET formed on the semiconductor substrate, wherein the FET comprises a source region, a drain region, a channel region formed between the source and drain regions and including a plurality of projected epitaxial silicon regions arranged in a width direction of the channel... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289904 - Semiconductor device and method of manufacturing the same: In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289906 - Semiconductor device including a capacitance: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289911 - Cmos image sensor: Disclosed is a CMOS image sensor, comprising a photodiode formed in a substrate, a floating diffusion region formed in the substrate in a manner such that it is distanced from the photodiode surrounds the photodiode and a transfer gate formed in a manner such that it is distanced from the... Agent: Foley And Lardner LLP Suite 500

20060289912 - Cmos image sensor and manufacturing method thereof: Provided are a CMOS image sensor and a manufacturing method thereof. The CMOS image sensor incorporates an interlayer insulating layer, a color filter layer, a first planarizing layer, and at least one microlens. The interlayer insulating layer is formed on a semiconductor substrate having at least one photodiode. The color... Agent: Jeff Lloyd Saliwanchik, Lloyd & Saliwanchik

20060289910 - Image sensor and method for fabricating the same: A complementary metal oxide semiconductor (CMOS) image sensor capable of improving photosensitivity and a signal to noise ratio and a method for fabricating the same are provided. An image sensor for embodying the colors of red, green and blue includes: a plurality of photodiodes formed on a substrate and collecting... Agent: Blakely Sokoloff Taylor & Zafman

20060289913 - Pattern definition of mram device using chemical mechanical polishing: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a first dielectric... Agent: Dickstein Shapiro LLP

20060289918 - Low resistance peripheral local interconnect contacts with selective wet strip of titanium: Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.... Agent: Whyte Hirschboeck Dudek S.c.

20060289916 - Power trench mosfets having sige/si channel structure: Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the... Agent: Townsend And Townsend And Crew, LLP

20060289914 - Semiconductor constructions, memory cells, dram arrays, electronic systems; methods of forming semiconductor constructions; and methods of forming dram arrays: The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double the plate pitch. The invention includes a method of forming a semiconductor construction. A plurality of conductive layers is formed over the substrate, the plurality of layers... Agent: Wells St. John P.s.

20060289915 - Semiconductor device: A semiconductor device comprises a semiconductor portion including first semiconductor layers of a first conduction type and second semiconductor layers of a second conduction type alternately arranged on the surface of a semiconductor substrate to form a striped shape. A main region is formed to arrange a main cell in... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289917 - Semiconductor device, rf-ic and manufacturing method of the same: Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode,... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20060289919 - Two-sided surround access transistor for a 4.5f2 dram cell: An isolation transistor having a grounded gate is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device... Agent: Knobbe Martens Olson & Bear LLP

20060289920 - Composite gate structure in an integrated circuit: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal... Agent: Slater & Matsil, L.L.P.

20060289921 - Method of manufacturing a capacitor for semiconductor device: A capacitor for use in a semiconductor device, a method of fabricating the capacitor, and an electronic device adopting the capacitor, wherein the capacitor includes upper and lower electrodes, each formed of a platinum group metal; a thin dielectric layer disposed between the upper and lower electrodes; and a buffer... Agent: Lee & Morse, P.C.

20060289922 - Non-volatile semiconductor memory device: To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with... Agent: Mcginn Intellectual Property Law Group, PLLC

20060289924 - Low power electrically alterable nonvolatile memory cells and arrays: Nonvolatile memory cells having a conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, and mass-filtering function to charge-carriers flows. The conductor-insulator system provides Image-Force barrier lowering effect to collect charge-carriers. The charge-injection system includes the conductor-filter system and... Agent: Chih-hsin Wang

20060289925 - Non-volatile memory, manufacturing method and operating method thereof: A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate... Agent: Jianq Chyun Intellectual Property Office

20060289923 - Oxide epitaxial isolation: Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxial structure in the recess. A... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060289926 - Semiconductor device and method of manufacturing the same: A semiconductor device including a semiconductor substrate having trenches oriented in a predetermined direction; a gate insulating film overlaying the semiconductor substrate interposed between the trenches; and floating gate electrodes formed on the gate insulating film aligned in a predetermined direction and in a direction intersecting thereto, an element isolation... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289927 - Non-volatile memory with hole trapping barrier: A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises two layers of dielectric having different band... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060289928 - Insulated gate type semiconductor device and manufacturing method thereof: The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P− body region 41, and N−... Agent: Kenyon & Kenyon LLP

20060289931 - Recessed gate structures including blocking members, methods of forming the same, semiconductor devices having the recessed gate structures and methods of forming the semiconductor devices: A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void... Agent: Myers Bigel Sibley & Sajovec

20060289930 - Semiconductor device and method of fabricating the same: Aiming at providing a semiconductor device capable of reducing the ON-resistance when voltage smaller than a predetermined value is applied to the base region and the drift region, and capable of increasing the ON-resistance so as to prevent thermal fracture when the voltage is not smaller than the predetermined value,... Agent: Mcginn Intellectual Property Law Group, PLLC

20060289929 - Structure and method for forming laterally extending dielectric layer in a trench-gate fet: A field effect transistor (FET) is formed as follows. A trench is formed in a silicon region. An oxidation barrier layer is formed over a surface of the silicon region adjacent the trench and along the trench sidewalls and bottom. A protective layer is formed over the oxidation barrier layer... Agent: Townsend And Townsend And Crew, LLP

20060289932 - Semiconductor memory device having power decoupling capacitor: Provided is a semiconductor memory device using a layout scheme where a bottom conductive layer in a peripheral circuit region, which is simultaneously formed with a self-align contact, is connected to one electrode of a power decoupling capacitor. Predetermined capacitors selected among a plurality of capacitors are connected to each... Agent: Marger Johnson & Mccollom, P.C.

20060289933 - Field effect transistor and method for producing a field effect transistor: A field effect transistor is provided having a source region, a drain region formed in a first well region, and a channel region. The first well region is doped with doping atoms of a first conductivity type. At least a part of the channel region which extends into the first... Agent: Brinks Hofer Gilson & Lione Infineon

20060289934 - Semiconductor device, liquid crystal display panel, electronic device, and method of manufacturing semiconductor device: In a plurality of transistors in which the thresholds that are required in the circuit design are equal, a transistor having an initial threshold at a lower limit within an acceptable range of the required threshold is arranged at a circuit position where an absolute value of a threshold voltage... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser

20060289935 - Layout structure for esd protection circuits: A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20060289936 - Esd protection device structure: An electrostatic discharge (ESD) protective device structure. The ESD protection device includes: at least a first conductive type metal-oxide semiconductor (MOS), in which the drain and source of the first conductive type MOS are electrically connected to a first power terminal and a second power terminal separately; at least a... Agent: North America Intellectual Property Corporation

20060289937 - System for esd protection with extra headroom in relatively low supply voltage integrated circuits: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20060289938 - Non-volatile memory devices and related methods: A semiconductor device may include a semiconductor substrate having an active region on a surface thereof. First, second, and third gate lines may cross the active region of the semiconductor substrate, and the first, second, and third gate lines may be arranged in parallel across the active region, and the... Agent: Myers Bigel Sibley & Sajovec

20060289939 - Array substrate and display device having the same: An LCD display device in which the gate lines are controlled by a gate circuit part that outputs gate signals to the gate lines. A first signal wiring is formed adjacent to the gate circuit part and transmits a starting signal, which initiates an operation of the gate circuit part,... Agent: Macpherson Kwok Chen & Heid LLP

20060289940 - Fin fet cmos device, method of manufacturing the same, and memory including fin fet cmos device: A fin FET CMOS device, a method of manufacturing the same, and a memory including the fin FET CMOS device are provided. The CMOS device may include a substrate, an n-type transistor disposed on the substrate, an interlayer insulating layer disposed on the n-type transistor, and a p-type transistor disposed... Agent: Harness, Dickey & Pierce, P.L.C

20060289941 - Transistor component: A source connection of a field effect transistor is formed using a contact region, which adjoins a source region, is highly oppositely doped and forms a butting contact with the source region. A well or substrate connecting region which is electrically conductively connected to a supply potential lead is arranged... Agent: Dickstein Shapiro LLP

20060289942 - Memory cell, semiconductor memory device, and method of manufacturing the same: A memory cell in a semiconductor memory device comprises a variable resistor element configured so that a variable resistor body is sandwiched between a first electrode and a second electrode, and a transistor element capable of controlling a flow of current in the variable resistor element, wherein the transistor element... Agent: Nixon & Vanderhye, PC

20060289943 - Memory: A memory allowing reduction of a memory cell size is obtained. This memory comprises a first conductive type first impurity region formed on the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a word line, a plurality... Agent: Mcdermott Will & Emery LLP

20060289944 - Nonvolatile memory devices having a fin shaped active region and methods of fabricating the same: A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are... Agent: Myers Bigel Sibley & Sajovec

20060289945 - Semiconductor memory device: Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting... Agent: Mcdermott Will & Emery LLP

20060289946 - Method and apparatus for maintaining topographical uniformity of a semiconductor memory array: A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack... Agent: Freescale Semiconductor, Inc. Law Department

20060289947 - Semiconductor device and its manufacturing method: This semiconductor device includes a first device and a second device provided on a semiconductor substrate and having different breakdown voltages. More specifically, the semiconductor device includes a semiconductor substrate, a first region defined on the semiconductor substrate and having a first device formation region isolated by a device isolation... Agent: Rabin & Berdo, PC

20060289948 - Method to control flatband/threshold voltage in high-k metal gated stacks and structures thereof: The present invention provides a metal stack (or gate stack) structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a gate conductor and a dielectric material having a dielectric constant of greater than about 4.0, especially a Hf-based dielectric. This present invention stabilizes the flatband... Agent: Scully Scott Murphy & Presser, PC

20060289949 - Method of composite gate formation: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing... Agent: Whyte Hirschboeck Dudek S.c.

20060289950 - Method of composite gate formation: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing... Agent: Whyte Hirschboeck Dudek S.c.

20060289951 - Method of composite gate formation: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing... Agent: Whyte Hirschboeck Dudek S.c.

20060289952 - Method of composite gate formation: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing... Agent: Whyte Hirschboeck Dudek S.c.

20060289953 - Semiconductor device and manufacturing method of the same: A semiconductor device includes a first semiconductor layer of a first conductivity type, a first gate insulating film, a first gate electrode and first source/drain regions. The first gate insulating film is formed on the first semiconductor layer. The first gate electrode is formed on the first gate insulating film.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060289954 - Method for processing a mems/cmos cantilever based memory storage device: A method is disclosed. The method includes fabricating microelectromechanical (MEMS) structures of a Seek and Scan Probe (SSP) memory device on a first wafer, and fabricating CMOS and memory medium components of the SSP memory device on a second wafer.... Agent: Blakely Sokoloff Taylor & Zafman

20060289955 - Semiconductor composite device and method of manufacturing the same: The present invention provides a semiconductor composite device including a semiconductor device formed on or in a substrate, an insulating film formed on the substrate so as to cover the semiconductor device, a micro electro mechanical portion formed on the insulating film, and a wiring layer connected to the semiconductor... Agent: Sonnenschein Nath & Rosenthal LLP

20060289956 - Process for creating tilted microlens: A microlens structure that includes a wedge formed to support and tilt the microlens is disclosed. The wedge results from heating a layer of patterned flowable material. The degree and direction of incline given to the wedge can be controlled in part by the type of patterning that is performed.... Agent: Dickstein Shapiro LLP

20060289957 - Germanium/silicon avalanche photodetector with separate absorption and multiplication regions: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of... Agent: Blakely Sokoloff Taylor & Zafman

20060289958 - Color filter and image pickup apparatus including the same: Provided is a color filter, including a plurality of filter units arranged at predetermined intervals, in which each of filter units includes a red transmission filter for red light transmission, a first green transmission filter for first green light transmission, a second green transmission filter for second green light transmission... Agent: Morgan & Finnegan, L.L.P.

20060289959 - Yield improvement in silicon-germanium epitaxial growth: A method for determining a SiGe deposition condition so as to improve yield of a semiconductor structure. Fabrication of the semiconductor structure starts with a single-crystal silicon (Si) layer. Then, first and second shallow trench isolation (STI) regions are formed in the single-crystal Si layer. The STI regions sandwich and... Agent: Schmeiser, Olsen & Watts

20060289960 - Structure improvement of depletion region in p-i-n photodiode: The present invention with a structure of depletion region improves the product of output power and bandwidth of a photodetector and prevents the drifting velocity of electron from slowing down under a bias, which can be applied to a photodetector of communicative wavelength over optical fiber.... Agent: Troxell Law Office PLLC

20060289961 - Semiconductor device: A semiconductor device including: a semiconductor layer; a transistor formed in the semiconductor layer and including a gate insulating layer and a gate electrode, the transistor being a high voltage transistor in which an insulating layer having a thickness greater than the thickness of the gate insulating layer is formed... Agent: Harness, Dickey & Pierce, P.L.C

20060289962 - An isolation region for use in a semiconductor device: An isolation region for use in a semiconductor device is formed in a p-type silicon substrate. An n-type silicon layer is disposed on the p-type silicon substrate, wherein the n-type silicon layer is separated by an oxidized porous silicon layer. At least a portion of the oxidized porous silicon layer... Agent: VistaIPLaw Group LLP

20060289963 - Compound semiconductor device: A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending from the direct current terminal... Agent: Morrison & Foerster LLP

20060289964 - Spacecraft regulation unit with decentralized bus capacitance: A Spacecraft Regulation Unit SRU or Power Conditioning Unit PCU with decentralized capacitance comprising several power conversion modules each coupled, via interconnection means, to a high-level power bus for supplying power to equipment of a satellite. Each power conversion module has a bus capacitor (Cmod) coupled via the interconnection means... Agent: Sughrue Mion, PLLC

20060289965 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer;... Agent: Michael A. Cantor

20060289966 - Silicon wafer with non-soluble protective coating: A silicon wafer with an array of integrated circuit (IC) dies formed on the wafer is provided with a protective coat applied to a surface of the wafer to protect the IC dies from debris created during a laser scribing process. The IC dies can include die bumps that can... Agent: Marger Johnson & Mccollom, P.C.

20060289968 - Conductive interconnect structures and formation methods using supercritical fluids: Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via having a width and a length generally transverse to the width, and with a length being approximately 100 microns... Agent: Perkins Coie LLP Patent-sea

20060289967 - Through-wafer vias and surface metallization for coupling thereto: An apparatus and method of fabricating a through-wafer via. A first mask is formed over a first side of a first semiconductor die to define a first via area. A deep recess is etched through the first semiconductor die in the first via area and a blanket metal layer is... Agent: Blakely Sokoloff Taylor & Zafman

20060289969 - Laser assisted material deposition: Electronic devices and systems are provided with material structured from irradiation of a gas precursor with electromagnetic energy at a frequency tuned to an absorption frequency of the gas precursor. The frequency of the electromagnetic energy may be selected to impart specific amounts of energy to a gas precursor at... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060289970 - Magnetic shielding of mram chips: An apparatus comprising a magnetically shielded MRAM chip and a method of manufacturing the same. The apparatus includes an MRAM module and a protective cover. The MRAM module includes a circuit board and a memory chip attached to the circuit board, the memory chip containing magnetoresistive random access memory (MRAM)... Agent: Slater & Matsil LLP

20060289973 - Lead frame for semiconductor package: A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the... Agent: Stetina Brunda Garred & Brucker

20060289972 - Semiconductor device: A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060289971 - Semiconductor device having firmly secured heat spreader: A semiconductor device comprising a leadframe (903), which has first (903a) and second (903b) surfaces, a planar pad (910) of a certain size, and a plurality of non-coplanar members (913) adjoining the pad. The device further has a heat spreader (920) with first (920a) and second (920b) surfaces, a planar... Agent: Texas Instruments Incorporated

20060289974 - Reliable integrated circuit and package: A packaged integrated circuit which includes a die 700 having a surface and corners separated by edges. The die surface includes depressions 600, 720 so that mold compound 114 covering the die surface fills the depressions. The filling of the depressions in the die surface enhances the adhesion of the... Agent: Texas Instruments Incorporated

20060289975 - Alignment using fiducial features: The present invention relates to positioning components of an assembly using fiducial features. A first fiducial feature on a first piece of the assembly can be located. A first component can be positioned on the first piece of the assembly based on the location of the first fiducial feature. A... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20060289977 - Lead-free semiconductor package: A package substrate includes die solder pads and pin solder fillets. The pin solder fillets might comprise between approximately 90 wt % to approximately 99 wt % tin and approximately 10 wt % to 1 wt % antimony. The die solder pads might comprise between approximately 4 wt % to... Agent: Farjami & Farjami LLP

20060289978 - Memory element conducting structure: Disclosed is a memory element conducting structure, which includes a substrate with contacts, hollow sockets provided at the top side of the substrate corresponding to the contacts of the substrate, conducting media respectively mounted in the hollow sockets and supported on the contacts, and a plurality of positioning means respectively... Agent: Optimum Care International Tech. Inc.

20060289976 - Pre-patterned thin film capacitor and method for embedding same in a package substrate: An embedded passive structure, its method of formation, and its intergration onto a substrate during fabrication are disclosed, In one embodiment the embedded passive structure is a thin film capacitor (TFC) formed using a thin film laminate that has been mounted onto a substrate. The TFC's capacitor dielectric and/or lower... Agent: Blakely Sokoloff Taylor & Zafman

20060289979 - Bridge modules for smart labels: The invention relates to module bridges for smart labels for positioning chip modules (5) on carries (12) and for the bridging connection of connection elements of the chip modules (5) to connection elements (11a, 11b) of antenna elements (11) arranged on or in the carriers (12), a plurality of module... Agent: Black Lowe & Graham, PLLC

20060289980 - Stacked memory card and method for manufacturing the same: A structure of stacked memory card, the structure includes a substrate, a lower chip, wires, adhered element, upper chip, and compound resin. The substrate has an upper surface formed with a plurality of first electrodes, and a lower surface. The B-stage glue is coated on the upper surface of the... Agent: Pro-techtor International

20060289981 - Packaging logic and memory integrated circuits: Logic and memory may be packaged together in a single integrated circuit package that, in some embodiments, has high input/output pin count and low stack height. In some embodiments, the logic may be stacked on top of the memory which may be stacked on a flex substrate. Such a substrate... Agent: Trop Pruner & Hu, PC

20060289982 - Semiconductor device and method for producing same: A semiconductor device is provided and includes: an interlayer insulating layer and a wiring layer provided above a surface of a semiconductor substrate having an element region. At least a portion of the interlayer insulating layer containing impurities in contact with the wiring layer has been removed at the edge... Agent: Birch Stewart Kolasch & Birch

20060289983 - System, method and device for reducing electromagnetic emissions and susceptibility from electrical and electronic devices: A system, device, and method are provided to analyze and provide recommendations regarding electrical noise in circuitry. A rule and algorithm-based recommendation generator may be used to analyze electrical noise at the schematic design stage. The engineer is provided with detailed recommendations of changes to the schematic diagram of the... Agent: Bourque & Associates Intellectual Property Attorneys, P.A.

20060289984 - Lead contact structure for emr elements: EMR elements and methods of fabricating the EMR elements are disclosed. The EMR structure includes one or more layers that form an active region, such as a two-dimensional electron gas (2DEG). The EMR structure has a first side surface, having a plurality of lead protrusions that extend outwardly from the... Agent: Duft Bornsen & Fishman, LLP

20060289985 - Glass lid, and package provided with such a lid, for the encapsulation of electronic components: The encapsulation lid comprises at least two glass layers of different compositions, a first layer called the bottom layer, which is continuous, and at least a second layer, which is discontinuous and designed so as to define cavities or anfractuosities in this lid. Preferably, the glass layers other than the... Agent: Thomson Licensing Inc.

20060289986 - In-package connection between integrated circuit dies via flex tape: An integrated circuit (IC) package includes a package substrate and a cap attached to the package substrate. The package substrate and the cap define a space therebetween. The IC package also includes a section of flex tape housed in the space defined by the cap and the package substrate.... Agent: Buckley, Maschoff, Talwalkar LLC

20060289987 - Microelectronic die cooling device including bonding posts and method of forming same: A microelectronic assembly and a method of forming same. The microelectronic assembly comprises: a microelectronic package including a substrate and a die, the die being electrically conductively bonded to the substrate at a front side thereof and further having a backside; a cover plate defining an inlet opening and an... Agent: Blakely Sokoloff Taylor & Zafman

20060289988 - Integrated circuit with heat conducting structures for localized thermal control: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first... Agent: Ryan, Mason & Lewis, LLP

20060289989 - Intrinsic thermal enhancement for fbga package: A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the device, and methods of fabricating the device and package are provided. In one embodiment, the semiconductor device comprises a thick thermally conductive plane (e.g., copper plane)... Agent: Whyte Hirschboeck Dudek S.c.

20060289990 - Apparatus and method for high density multi-chip structures: Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. Another advantage of this design includes shorter distances for interconnection pathways, which... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060289991 - Semiconductor device and manufacturing method of the same: The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode formed on a semiconductor substrate with insulation films interposed therebetween, a plating layer formed on the pad electrode, a conductive terminal formed on the plating layer and electrically connected with the pad... Agent: Morrison & Foerster LLP

20060289992 - Stacked semiconductor component, fabrication method and fabrication system: A semiconductor component includes a carrier and multiple semiconductor substrates stacked and interconnected on the carrier. The carrier includes conductive members bonded to corresponding conductive openings on the semiconductor substrates. The component can also include terminal contacts on the carrier in electrical communication with the conductive members, and an outer... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20060289993 - Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow: A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor.... Agent: Whyte Hirschboeck Dudek S.c.

20060289995 - Interconnection device including one or more embedded vias and method of producing the same: Briefly, some demonstrative embodiments of the present invention include an interconnection device, e.g., a Systems In Package (SIP) device, or Systems In Chip (SIC) device, including one or more embedded vias. Some demonstrative embodiments of the invention include a process to produce the interconnection device. Other embodiments are described and... Agent: Pearl Cohen Zedek Latzer, LLP

20060289994 - Multi-level interconnections for an integrated circuit chip: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts... Agent: Ibm Microelectronics Intellectual Property Law

20060289996 - Semiconductor device: A semiconductor device includes a first wiring line group made of a metal, wiring lines of the first wiring line group being arranged in parallel with each other, a second wiring line group which is made of a semiconductor and crosses the first wiring line group, wiring lines of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060289997 - Semiconductor device: The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060289998 - Semiconductor device and a method of manufacturing the same: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in... Agent: Miles & Stockbridge PC

20060289999 - Selective copper alloy interconnections in semiconductor devices and methods of forming the same: A selective copper alloy interconnection in a semiconductor device is provided. The interconnection includes a substrate, a dielectric formed on the substrate, and a first interconnection formed in the dielectric. The first interconnection has a first pure copper pattern. In addition, a second interconnection having a larger width than the... Agent: Myers Bigel Sibley & Sajovec

20060290000 - Composite metal layer formed using metal nanocrystalline particles in an electroplating bath: A method for forming a composite metal layer on a substrate comprises providing nanocrystalline particles of a first metal, adding the nanocrystalline particles to a plating bath that contains ions of a second metal to form a colloid-like suspension, immersing the substrate in the plating bath, and causing a co-deposition... Agent: Blakely Sokoloff Taylor & Zafman

20060290001 - Interconnect vias and associated methods of formation: Interconnect vias and associated methods of formation are disclosed. One such method includes forming an operable microelectronic feature in a substrate, with the substrate having a first surface and a second surface facing away from the first surface. The method can further include forming a via in the substrate at... Agent: Perkins Coie LLP Patent-sea

20060290002 - Method of forming through-silicon vias with stress buffer collars and resulting devices: A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.... Agent: Intel Corporation

20060290003 - Substrate structure and manufacturing method of the same: A Ti film is pattern-formed on a desired portion on a silicon substrate, and a Co film is formed on the substrate so as to cover the Ti film. CNTs are formed only on a portion, under which the Ti film is formed, of the surface of the Co film... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20060290005 - Multi-chip device and method for producing a multi-chip device: The present invention relates to a multi-chip device comprising a substrate having a first surface on which a number of first contact elements is provided, a plurality of integrated circuit chips arranged in a chip stack which is arranged on a second surface of the substrate opposing the first surface,... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies

20060290004 - Semiconductor device: In the case where a first semiconductor chip 100 and a second semiconductor chip 200 are stacked, both the semiconductor chips 100 and 200 are connected using micro bumps, in which a circuit block in the first semiconductor chip and a circuit block in the second semiconductor chip are connected... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060290007 - Flip chip die assembly using thin flexible substrates: Apparatus and methods for flattening thin substrate surfaces by stretching thin flexible substrates to which ICs can be bonded. Various embodiments beneficially maintain the substrate flatness during the assembly process through singulation. According to one embodiment, the use of a window frame type component carrier allows processing of thin laminates... Agent: Faegre & Benson LLP Patent Docketing

20060290006 - Semiconductor package: A semiconductor package includes a combination die embedded in a base. The combination die includes a plurality of functional blocks, where the functional blocks are insulated from one another on the combination die. Each functional block has plural die connectors. The base includes insulating layers conductive layers and vias. Each... Agent: Harrington & Smith, LLP

20060290008 - Smt passive device noflow underfill methodology and structure: An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. The SMD, having a pair of electrical contacts, is pressed into... Agent: John A. Jordan, Esq.

20060290009 - Semiconductor device and method for manufacturing the same: A semiconductor device (1) of the present invention includes a semiconductor element (103) including electrode parts (104), and a wiring substrate (108) including an insulation layer (101), electrode-part-connection electrodes (102) provided in the insulation layer (101), and external electrodes (107) that is provided in the insulation layer (101) and that... Agent: Hamre, Schumann, Mueller & Larson P.C.

20060290010 - Method of embedding semiconductor chip in support plate and embedded structure thereof: A method of embedding a semiconductor chip in a support plate and an embedded structure thereof are proposed. A first dielectric layer having a reinforced filling material is provided, and a semiconductor chip is mounted on the first dielectric layer. A support plate having an opening and a second dielectric... Agent: Clark & Brody

20060290011 - Molded stiffener for thin substrates: A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is molded to the substrate to provide rigidity and support to the substrate. The stiffener material can comprise a polymeric material molded to the substrate... Agent: Whyte Hirschboeck Dudek S.c.

20060290012 - Multiple mask process with etch mask stack: A method for forming etch features in an etch layer over a substrate is provided. An etch mask stack is formed over the etch layer. A first mask is formed over the etch mask stack. A sidewall layer is formed over the first mask, which reduces the widths of the... Agent: Beyer Weaver & Thomas, LLP

20060290013 - Method for chemical vapor deposition in high aspect ratio spaces: A method of depositing conformal film into high aspect ratio spaces includes the step of forming a gradient of precursor gas inside the space(s) prior to deposition. The gradient may be formed, for example, by reducing the pressure within the deposition chamber or by partial evacuation of the deposition chamber.... Agent: VistaIPLaw Group LLP

20060284155 - Switching device: A switching device in which an organic bistable material layer containing an organic bistable compound having two types of stable resistance against an applied voltage is provided between at least two electrodes. In the switching device, a first electrode layer, an electric charge injection suppressing layer, an organic bistable material... Agent: Rossi, Kimms & Mcdowell LLP.

20060284156 - Phase change memory cell defined by imprint lithography: A memory cell includes a first electrode, a second electrode, and a phase-change material between the first electrode and the second electrode. A minimum cross-sectional area of a current path between the first electrode and the second electrode is defined by an imprint lithography process.... Agent: Dicke, Billig & Czaja, P.l.l.c.

20060284158 - Self-aligned, embedded phase change ram and manufacturing method: An integrated circuit with an embedded memory comprises a substrate and a plurality of conductor layers arranged for interconnecting components of the integrated circuit. An intermediate layer in the plurality of conductor layers includes a first electrode having a top surface, a second electrode having a top surface, an insulating... Agent: Macronix C/o Haynes Beffell & Wolfeld LLP

20060284157 - Thin film plate phase change ram circuit and manufacturing method: A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first... Agent: Macronix C/o Haynes Beffell & Wolfeld LLP

20060284159 - Phase change memory device and method for manufacturing the same: A phase change memory device reduces the current necessary to cause a phase change of a phase change layer. The phase change memory device includes a first oxide layer formed on a semiconductor substrate; a lower electrode formed inside the first oxide layer; a second oxide layer formed on the... Agent: Ladas & Parry LLP

20060284160 - Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof: A contact structure for a PCM device is formed by an elongated formation having a longitudinal extension parallel to the upper surface of the body and an end face extending in a vertical plane. The end face is in contact with a bottom portion of an active region of chalcogenic... Agent: Seed Intellectual Property Law Group PLLC

20060284161 - Light source module and vehicle lamp: A light source module is provided with a semiconductor light emitting element disposed in a hollow airtight region within a cover fixed to a circuit board, and electrodes which are disposed outside of the airtight region and supplies a current to the semiconductor light emitting element. The circuit board is... Agent: Sughrue Mion, PLLC

20060284162 - Programmable optical component for spatially controlling the intensity of beam of radiation: A programmable optical component (10) for spatially controlling the intensity of a beam of radiation (b), which component comprises a programmable layer which is divided in programmable elements (4,6,8), characterized in that each programmable element comprises bendable nano-elements (8) which are switchable between a non-bend state (8) and a bend... Agent: Philips Intellectual Property & Standards

20060284163 - Single elog growth transverse p-n junction nitride semiconductor laser: A vertical quantum well nitride laser-can be fabricated by ELOG (epitaxial lateral overgrowth), with the vertical quantum wells created by deposition over the vertical a-face of the laterally growing edges and forming the transverse junction in a single ELOG-MOCVD (metal organic chemical vapor deposition) growth step. Vertical quantum wells may... Agent: Avago Technologies, Ltd.

20060284164 - Strained germanium field effect transistor and method of making the same: A strained germanium field effect transistor (FET) and method of making the same, comprise forming a germanium layer on a substrate, then forming a Si protective layer on the germanium layer, next forming a gate insulation layer on the Si protective layer, and fmally positioning a gate on the gate... Agent: Harness, Dickey & Pierce, P.L.C

20060284165 - Silicon-based backward diodes for zero-biased square law detection and detector arrays of same: A Si-based diode (10, 10′, 100) is formed by epitaxially depositing a Si-based diode structure on a silicon substrate. The Si-based diode structure includes a Si-based pn junction (16, 16′, 18, 18′, 30, 32, 160, 161) having a backward diode current-voltage characteristic in which the forward tunneling current is substantially... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20060284168 - Light emitting device: The present invention relates to a light emitting device, particularly to an organic electroluminescent device, that a part of data lines includes a first conduction layer and an insulation layer formed on a substrate in sequence. The light emitting device includes a substrate, a plurality of anode electrode layers disposed... Agent: Fleshner & Kim, LLP

20060284169 - Method of patterning nano conductive film: A donor substrate for forming a nano conductive film includes a base substrate and a transferring layer that is disposed on the base substrate. The transferring layer includes nano conductive particles and an organic semiconductor. A method of patterning a nano conductive film is provided, wherein a donor substrate in... Agent: Robert E. Bushnell

20060284167 - Multilayered substrate obtained via wafer bonding for power applications: A multi-layer semiconductor device utilizes the good thermal and electrical properties of a polycrystalline substrate with the electrical properties of single crystal film transferred via wafer bonding. The device structure includes a polycrystalline, e.g., silicon carbide substrate, which was polished. A planarization layer of silicon is formed on the surface,... Agent: Birch Stewart Kolasch & Birch

20060284166 - Polymer transistor: A transistor including a semiconductive layer; and a gate dielectric layer comprising an insulating polymer, characterised in that the insulating polymer is crosslinked and comprises one or more units having a low cohesive-energy-density and one or more crosslinking groups and the insulating polymer includes substantially no residual —OH leaving groups.... Agent: Sughrue Mion, PLLC

20060284170 - Transparent light-emitting component: The invention concerns a transparent light-emitting component, in particular an organic light-emitting diode (OLED), with a layer arrangement in which a light-emitting organic layer is arranged between an upper and a lower electrode, the layer arrangement being transparent in a switched-off state and emitting light which is produced in the... Agent: Sutherland Asbill & Brennan LLP

20060284171 - Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby: A thin film transistor comprises a zinc-oxide-containing semiconductor material. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating a thin film transistor device, wherein the substrate temperature is no more than 300° C.... Agent: Paul A. Leipold Patent Legal Staff

20060284172 - Thin film transistor having oxide semiconductor layer and manufacturing method thereof: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and... Agent: Frishauf, Holtz, Goodman & Chick, PC

20060284174 - Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer: An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and... Agent: Francis J. Thornton

20060284173 - Method to test shallow trench isolation fill capability: A shallow trench isolation (STI) test pattern comprising a plurality of test structures. Each of the test structures comprise at least two lines comprising a predefined line length, line width, and gap between the lines. At least one of the line length, line width and gap are different between each... Agent: Texas Instruments Incorporated

20060284175 - Thin-film semiconductor substrate, method of manufacturing thin-film semiconductor substrate, method of crystallization, apparatus for crystallization, thin-film semiconductor device, and method of manufacturing thin-film semiconductor device: A thin-film semiconductor substrate includes an insulative substrate, an amorphous semiconductor thin film that is formed on the insulative substrate, and a plurality of alignment marks that are located on the semiconductor thin film and are indicative of reference positions for crystallization.... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060284178 - Active-matrix addressing substrate and method of fabricating the same: An active-matrix addressing substrate improves the degradation of initial alignment of liquid-crystal molecules caused by the steps or level differences due to the pixel electrodes and/or the common electrode. The pixel electrodes are formed on or over the first insulating layer and the common electrode is formed on the second... Agent: Mcginn Intellectual Property Law Group, PLLC

20060284177 - Image sensor with compact pixel layout: Solid-state image sensors, specifically the image sensor pixels, which have three or four transistors, high sensitivity, low noise, and low dark current, are provided. The pixels have separate active regions for active components, row-shared photodiodes and may also contain a capacitor to adjust the sensitivity, signal-to-noise ratio and dynamic range.... Agent: Fernandez & Associates, LLP

20060284180 - Semiconductor device, el display device, liquid crystal display device, and calculating device: There is provided a semiconductor device able to increase the mobility of carriers and reduce the current in the OFF state. The semiconductor device includes a gate electrode, an insulating layer on the gate electrode, a first electrode on the insulating layer, a second electrode on the insulating layer at... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060284179 - Silicon thin film transistor and method of manufacturing the same: A silicon thin film transistor (“TFT”) and method of manufacturing the same are provided where the silicon TFT includes buffer layers deposited on both surfaces of a substrate, respectively, and a silicon channel is deposited on one of the buffer layers. A gate insulator is deposited on the silicon channel,... Agent: Cantor Colburn, LLP

20060284176 - Switching device for a pixel electrode and methods for fabricating the same: The invention discloses a switching device for a pixel electrode of display device and methods for fabricating the same. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A buffer layer is formed between the gate and the substrate, and/or formed between the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20060284181 - Fabricating method for thin film transistor substrate and thin film transistor substrate using the same: A thin film transistor substrate and its fabrication method are discussed. According to an embodiment, the fabricating method of a thin film transistor substrate includes forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode, the gate insulating film having a groove in an... Agent: Birch Stewart Kolasch & Birch

20060284182 - Liquid crystal display: A liquid crystal display device includes first thin film transistor with a first polysilicon active layer in which a first channel area has first grain boundaries, wherein the first thin film transistor has a first channel direction different from a first grain boundary direction of the first grain boundaries, and... Agent: Jenkens & Gilchrist, P.C.

20060284184 - Display device: The irregularities of characteristics of a pair of transistors, which are prepared by a pseudo single crystallizing technique, are reduced. To achieve this, semiconductor layers are formed on a substrate and have pseudo single crystal regions therein, and a plurality of thin film transistors are arranged inside the pseudo single... Agent: Antonelli, Terry, Stout & Kraus, LLP

20060284183 - Semiconductor device and manufacturing method thereof: It has been difficult to manufacture a semiconductor device equipped with a microstructure having a space, an electric circuit for controlling the microstructure, and the like over one substrate. In a semiconductor device, a microstructure and an electric circuit for controlling the microstructure can be provided over one substrate by... Agent: Fish & Richardson P.C.

20060284187 - Grown photonic crystals in semiconductor light emitting devices: A photonic crystal is grown within a semiconductor structure, such as a III-nitride structure, which includes a light emitting region disposed between an n-type region and a p-type region. The photonic crystal may be multiple regions of semiconductor material separated by a material having a different refractive index than the... Agent: Patent Law Group LLP

20060284185 - Light emitting device and phosphor for the same: Provided is a light emitting device including a light emititng chip, and a phosphor through which a light emitting from the light emitting chip at least partially passes such that the light is converted into lights having at least two different wavelengths and emitted. The light emtting device emits white... Agent: Birch Stewart Kolasch & Birch

20060284191 - Light emitting diode: A light emitting diode includes a light emitting structure, a heterojunction, a first electrode, and a second electrode. The light emitting structure has a top surface where the first electrode and the second electrode are positioned thereon. The heterojunction is in the light emitting structure and includes a first semiconductor... Agent: Ingrassia Fisher & Lorenz, P.C.

20060284190 - Light emitting diodes with reflective electrode and side electrode: A light emitting diode includes a first doped semiconductor layer, an active region and a second doped semiconductor layer. The first reflective electrode of the light emitting diode is connected to the edge surfaces of the first doped semiconductor layer. The second reflective electrode includes an optically transparent layer and... Agent: William Propp. Esq. / Goldeneye, Inc.

20060284188 - Light-emitting diode and method for manufacturing the same: A light-emitting diode (LED) and a method for manufacturing the same are described. The light-emitting diode has a first substrate. An illuminant epitaxial structure is deposited on a surface of the first substrate, in which the illuminant epitaxial structure has a first surface and a second surface opposite each other,... Agent: Sughrue Mion, PLLC

20060284189 - Light-emitting element, light-emitting device, and electronic device: The present invention provides a light-emitting element, a light-emitting device and an electronic device in which an optical path length through which generated light goes can be changed easily. The present invention provides a light-emitting element including a light-emitting layer between a first electrode and a second electrode, and a... Agent: Eric Robinson

20060284186 - Semiconductor light emiting device and method of producing the same: To provide a semiconductor light emitting device capable of improving an aspect ratio of a laser beam to make it close to a circular shape and a method of producing the same, a first conductive type first cladding layer 11, an active layer 12, and a second conductive type second... Agent: Sonnenschein Nath & Rosenthal LLP

20060284192 - Radiation-emitting semi-conductor component: In a radiation-emitting semiconductor component with a layer structure comprising an n-doped confinement layer, a p-doped confinement layer, and an active, photon-emitting layer disposed between the n-doped confinement layer and the p-doped confinement layer, it is provided according to the invention that the n-doped confinement layer is doped with a... Agent: Fish & Richardson PC

20060284193 - Organic electroluminescent device: The present invention relates to a light emitting device, particularly to an organic electroluminescent device, that can prevent corrosion of data lines and scan lines and improve the adhesive strength of a sealant. The organic electroluminescent device includes a substrate, a plurality of anode electrode layers disposed in a first... Agent: Fleshner & Kim, LLP

20060284194 - Imaging member: An imaging member includes an electrically conductive layer; a positive charge blocking layer, an imaging layer, and an undercoat layer. The undercoat layer is intermediate the imaging layer and the electrically conductive layer. The undercoat layer includes a film forming polymer and a particulate material dispersed therein. The particulate material... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20060284202 - Electronic component and method of producing same: There are provided an electronic component production method and an electronic component by which the number of scribing processes can be reduced and the productivity can be made higher while surely preventing short circuiting during the production. An electronic component including a short ring residue portion and a method of... Agent: Fitzpatrick Cella Harper & Scinto

20060284205 - Flip-chip light-emitting device with micro-reflector: A Flip-chip light-emitting device with integral micro-reflector. The flip-chip light-emitting device emits reflected light provided by a light-emitting layer. The micro-reflector reflects light that might otherwise be lost to internal refraction and absorption, so as to increase light-emitting efficiency.... Agent: North America Intellectual Property Corporation

20060284204 - Light emitting device and electronic device: The invention provides a light emitting device which uses a color conversion layer, with high light emission efficiency and a low driving voltage. The light emitting device includes a light emitting element having a pair of electrodes and a layer containing an organic compound sandwiched between the pair of electrodes,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20060284198 - Light emitting diode with larger illumination area: The present invention relates to a light emitting diode with larger illumination area that includes a LED chip and a shielding layer. The shielding layer is disposed over an incident plane of the LED chip and its length is longer, equal to or shorter than the length of the incident... Agent: Rosenberg, Klein & Lee

20060284201 - Light-emitting diode incorporating gradient index element: The light-emitting device includes a light source and a gradient index (GRIN) element. The GRIN element has a cylindrical refractive index profile in which the refractive index varies radially and is substantially constant axially. The GRIN element includes a first end surface opposite a second end surface and is characterized... Agent: Avago Technologies, Ltd. C/o Klaas, Law, O'meara & Malkin, P.C.

20060284199 - Light-emitting module: The light-emitting module according to the present invention comprises a heat dissipation element, a substrate for example a metal core printed circuit board (MCPCB), or FR4 board which is coupled to one or more light-emitting elements and provides a means for operative connection of the light-emitting elements to a source... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20060284197 - Optical element: An optical element includes: a first semiconductor element; a second semiconductor element, wherein the first semiconductor element includes a semiconductor layer, a first electrode and a second electrode of a first conductivity type for driving the first semiconductor element, formed at mutually separated positions and above the semiconductor layer, and... Agent: Oliff & Berridge, PLC

20060284200 - Optical radiation emitting device and method of manufacturing same: A device for emitting optical radiation is integrated on a substrate of semiconductor material. The device includes an active layer having a main area for generating radiation, and first and second electro-conductive layers having an electric signal that generates an electric field to which an exciting current is associated. In... Agent: Hogan & Hartson LLP

20060284206 - Packaging technique for the fabrication of polarized light emitting diodes: A polarized light emitting diode (LED) includes a marker indicating a polarization direction. A package for the LED also includes a marker indicating the polarization direction. The markers on the LED and package are used for mutual alignment, wherein the LED is attached in a favorable orientation with respect to... Agent: Gates & Cooper LLP Howard Hughes Center

20060284196 - Red garnet phosphors for use in leds: Phosphor compositions having the formula LlMmAaGgPpQqNnZz:Ce3+, where L is at least one of Li, Na, K, Rb, and/or Cs; M is at least one of Be, Mg, Ca, Sr, Ba, Mn, Sn, Pb, and/or Zn; A is at least one of Bi, Sb, In, Sc, Y, and/or any of the... Agent: Scott A. Mccollister, Esq. Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20060284195 - Semiconductor light emitting device, light emitting module, lighting apparatus, display element and manufacturing method of semiconductor light emitting device: An LED array chip (2), which is one type of a semiconductor light emitting device, includes an array of LEDs (6), a base substrate (4) supporting the array of the LEDs (6), and a phosphor film (48). The array of LEDs (6) is formed by dividing a multilayer epitaxial structure... Agent: Snell & Wilmer L.L.P.

20060284203 - Side-emitting led package and manufacturing method of the same: The invention relates to a side-emitting LED package and a manufacturing method of the same. The invention provides a side-emitting LED package for emitting light from a light source sideward including a substrate with an electrode formed thereon. The package also includes a light source disposed on the substrate, a... Agent: Mcdermott Will & Emery LLP

20060284207 - Light emitting diode package with metal reflective layer and method of manufacturing the same: The invention relates to an LED package having a metal reflective layer for focusing and emitting light through a side of the package, and a manufacturing method of the same. The LED package includes a substrate with an electrode formed thereon, a light emitting diode chip disposed on the substrate,... Agent: Mcdermott Will & Emery LLP

20060284209 - Light emitting device package: A light emitting device package is provided. The light emitting device package comprises a base substrate on which a wiring pattern is formed; a light emitting device mounted on the base substrate to emit light when supplied with driving power through the wiring pattern; a molded lens stably seated on... Agent: Buchanan, Ingersoll & Rooney PC

20060284208 - Light emitting diode device using electrically conductive interconnection section: A light emitting diode devic that includes (a) a light emitting diode section, (b) an electrically conductive pad section being disposed outside the light emitting diode section and being electrically connected to an external power source, and (c) at least one electrically conductive interconnection section for connecting the electrically conductive... Agent: Mckenna Long & Aldridge LLP

20060284210 - Capacitorless dram on bulk silicon: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A... Agent: Knobbe Martens Olson & Bear LLP

20060284211 - Power semiconductor module: The power semiconductor module includes a module package housing power semiconductor devices therein and a magnetic core set around the module package, such that magnetic core surrounds the power semiconductor devices such as IGBTs. Alternatively, the magnetic core is built in the module package such that the outer circumference faces... Agent: Rossi, Kimms & Mcdowell LLP.

20060284212 - Hetero-junction bipolar transistor and manufacturing method thereof: A high-performance hetero-junction bipolar transistor with good processibility and which does not increase ON resistance (Ron), and a manufacturing method thereof are provided. The hetero-junction bipolar transistor includes a sub-collector layer made of n-type GaAs, a second collector layer made of n-type GaAs having a lower impurity concentration than the... Agent: Greenblum & Bernstein, P.L.C

20060284213 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1-xAsySb1-y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060284214 - Thin film fuse phase change cell with thermal isolation layer and manufacturing method: A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode... Agent: Macronix C/o Haynes Beffell & Wolfeld LLP

20060284215 - Solid-state imaging device and method of manufacturing said solid-state imaging device: It is an object to provide solid-state imaging device, which can easily be manufactured and has a high reliability, and a method of manufacturing the solid-state imaging device. In the present invention, a manufacturing method comprises the steps of forming a plurality of IT-CCDs on a surface of a semiconductor... Agent: Birch Stewart Kolasch & Birch

20060284216 - Method for producing optical film and apparatus for producing the same: Disclosed herein is a method for producing an optical film, comprising carrying out a given process by allowing a film having a joint to continuously pass through the given process while meandering the film to increase the length of a film transport path, wherein when the joint of the film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060284217 - Silicon carbide semiconductor device: A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth... Agent: Posz Law Group, PLC

20060284218 - Nanoelectonic devices based on nanowire networks: Semiconductor devices where networks of molecular nanowires (or nanofibers) are used as the semiconductor material. Field effect transistors are disclosed where networks of molecular nanowires are used to provide the electrical connection between the source and drain electrodes. The molecular nanowires have diameters of less than 500 nm and aspect... Agent: Venable LLP

20060284221 - Semiconductor device and electronic device: A channel forming region of a thin-film transistor is covered with an electrode and wiring line that extends from a source line. As a result, the channel forming region is prevented from being illuminated with light coming from above the thin-film transistor, whereby the characteristics of the thin-film transistor can... Agent: Eric Robinson

20060284220 - Semiconductor device and manufacturing method of the semiconductor device: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint... Agent: Oliff & Berridge, PLC

20060284219 - Semiconductor integrated circuit device method of fabricating the same: A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a semiconductor substrate, a transistor having a gate interconnection that extends in one direction on the semiconductor substrate and source/drain regions aligned in the gate interconnection and formed in the semiconductor substrate, and a diffusion-preventing metallic pattern... Agent: F. Chau & Associates, LLC

20060284223 - Cmos image sensor and manufacturing method thereof: Disclosed are a CMOS image sensor and manufacturing method thereof. The method includes the steps of forming a lower insulating layer and an upper insulating layer on an entire surface of a semiconductor substrate in successive order, the substrate having an isolation layer defining an active region comprising a photodiode... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20060284222 - Wide dynamic range sensor having a pinned diode with multiple pinned voltages: A pixel cell has controlled photosensor anti-blooming leakage by having dual pinned voltage regions, one of which is used to set the anti-blooming characteristics of the photosensor. Additional exemplary embodiments also employ an anti-blooming transistor in conjunction with the dual pinned photosensor. Other exemplary embodiments provide a pixel with two... Agent: Dickstein Shapiro LLP

20060284224 - Ferroelectric memory device and method of manufacturing the same: A ferroelectric memory device, which includes a vertical ferroelectric capacitor having an electrode distance smaller than a minimum feature size of lithography technology being used and suitable for the miniaturization, and a method of manufacturing the same are disclosed. According to one aspect of the present invention, it is provided... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060284227 - Capacitor device having low dependency of capacitance value change upon voltage: Capacitors are formed on an insulating film covering the surface of a semiconductor substrate. Each capacitor is constituted of a lower electrode layer of doped silicon, a dielectric film of silicon oxide formed on the lower electrode and an upper electrode layer of polycide formed on the dielectric film. Capacitors... Agent: Dickstein Shapiro LLP

20060284225 - Memory cell array and method of forming the same: A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second... Agent: Edell, Shapiro & Finnan, LLC

20060284226 - Semiconductor devices including a topmost metal layer with at least one opening and their methods of fabrication: In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on... Agent: Marger Johnson & Mccollom, P.C.

20060284228 - Semiconductor device and method for fabricating the same: A method for fabricating a three dimensional type capacitor is provided. The method includes forming a first insulation layer including first contact layers over a substrate, forming a second insulation layer over the first insulation layer, forming second contact layers by using a material having an etch selectivity different from... Agent: Blakely Sokoloff Taylor & Zafman

20060284229 - Semiconductor device with a bit line contact plug and method of fabricating the same: In one embodiment, a semiconductor device includes a plurality of gate electrodes formed on a semiconductor substrate including a cell region, a core region, and a peripheral circuit region, along with source/drain regions. A first landing pad contacts the source/drain of the cell region. A second landing pad contacts the... Agent: Marger Johnson & Mccollom, P.C.

20060284231 - Dielectric memory and method for manufacturing the same: A method for manufacturing a dielectric memory including the steps of: forming a second insulating film which covers wires formed above first contact plugs connected to impurity diffusion layers; forming a third insulating film on the second insulating film; forming a first hydrogen barrier film on the third insulating film;... Agent: Panasonic Patent Center C/o Mcdermott Will & Emery LLP

20060284232 - Semiconductor device having a capacitor and a fabrication method thereof: In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate having a memory cell array region and a peripheral region, a plurality of capacitors in the memory cell array region each having a storage electrode, a dielectric layer on... Agent: Mills & Onello LLP

20060284230 - Vertical organic field effect transistor: A vertical organic field effect transistor that includes an active cell and a capacitor that share a common source electrode. The active cell includes a semiconductor layer that is sandwiched between a drain electrode and the common source electrode. The capacitor includes a dielectric layer that is sandwiched between a... Agent: Venable LLP

20060284233 - Acceptor doped barium titanate based thin film capacitors on metal foils and methods of making thereof: The present invention is directed to a dielectric thin film composition comprising: (1) one or more barium/titanium-containing additives selected from (a) barium titanate, (b) any composition that can form barium titanate during firing, and (c) mixtures thereof; dissolved in (2) organic medium; and wherein said thin film composition is doped... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20060284236 - Back-side trapped non-volatile memory device: Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth

20060284235 - Low power flash memory devices: A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and injected over a barrier to a floating gate of... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060284237 - Phase change memory cells having a cell diode and a bottom electrode self-aligned with each other and methods of fabricating the same: Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower region of the contact hole and a bottom electrode in... Agent: Robert W. Glatz Myers Bigel Sibley & Sajovec, P.A.

20060284234 - Structure of a non-volatile memory device and operation method: A nonvolatile memory device, including composite gate structures formed on a substrate in series along a bit line (BL) direction. Each of the composite gate structures has a first storage gate, a second storage gate, and a selection gate between the two storage gates. Each of the composite gate structures... Agent: J C Patents, Inc.

20060284239 - Flash cell using a piezoelectric effect: Described is a flash cell using a piezoelectric effect. The flash cell includes a silicon substrate; a floating gate formed on a predetermined area of the silicon substrate; a control gate formed on the floating gate and the silicon substrate; a piezoelectric layer formed on the control gate; and an... Agent: Marshall, Gerstein & Borun LLP

20060284238 - Non-volatile two-transistor programmable logic cell and array layout: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within... Agent: Sierra Patent Group, Ltd.

20060284240 - Structure of a non-volatile memory device and operation method: A nonvolatile memory device includes composite gate structures formed on a substrate in series along a bit line direction. The composite gate structure has a first storage gate structure, a second storage gate structure, and a selection gate between the two storage gate structures. Each of the composite gate structures... Agent: J.c. Patents

20060284241 - Nanocrystal non-volatile memory device and method of fabricating the same: Non-volatile memory cells (e.g., EEPROM cells) utilize floating gate electrodes that are each defined by a plurality of spaced-apart semiconductor nanocrystals. Each of the memory cells includes a semiconductor substrate having a tunnel dielectric layer thereon. A plurality of semiconductor nanocrystals are provided on the tunnel dielectric layer. These plurality... Agent: Myers Bigel Sibley & Sajovec

20060284242 - Non-volatile memory device having floating gate and methods forming the same: A non-volatile memory device includes a device isolation layer disposed on a semiconductor substrate to define an active region, a floating gate disposed on the active region including a flat portion and a wall portion extending upwardly from an edge of the flat portion, a tunnel insulator interposed between the... Agent: F. Chau & Associates, LLC

20060284243 - Electrically erasable programmable read only memory (eeprom) cell and method for making the same: An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to the first N+ doped junction... Agent: Martine Penilla & Gencarella, LLP

20060284244 - Erasable non-volatile memory device using hole trapping in high-k dielectrics: A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises at least one layer of high-K.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060284246 - Memory utilizing oxide nanolaminates: Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060284245 - Sonos memory device having curved surface and method for fabricating the same: A new SONOS memory device is provided, in which a conventional planar surface of multi-dielectric layers (ONO layers) is instead formed with a curved surface such as a cylindrical shape, and included is a method for fabricating the same. A radius of curvature of the upper surface of a blocking... Agent: Marger Johnson & Mccollom, P.C.

20060284247 - Novel method for integrating silicon cmos and algan/gan wideband amplifiers on engineered substrates: High-speed silicon CMOS circuits and high-power AlGaN/GaN amplifiers are integrated on the same wafer. A thin layer of high resistivity silicon is bonded on a substrate. Following the bonding, an AlGaN/GaN structure is grown over the bonded silicon layer. A silicon nitride or a silicon oxide layer is then deposited... Agent: Birch Stewart Kolasch & Birch

20060284248 - Semiconductor device and method of fabricating the same: First semiconductor pillar layers of a first conduction type and second semiconductor pillar layers of a second conduction type are arranged on a first semiconductor layer of the first conduction type laterally, periodically and alternately at a first period to forma first pillar layer. Third semiconductor pillar layers of the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060284249 - Impurity co-implantation to improve transistor performance: A pMOS transistor having reduced diffusion from source/drain regions and a method of forming the same are provided. The pMOS transistor includes a source/drain region doped with a p-type impurity and a diffusion-retarding material in a semiconductor substrate. The pMOS transistor further includes a gate dielectric over a channel region... Agent: Slater & Matsil, L.L.P.

20060284251 - Coplanar silicon-on-insulator (soi) regions of different crystal orientations and methods of making the same: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI... Agent: Ibm Corporation Intellectual Property Law Dept. 917

20060284250 - Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates: A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions... Agent: James R. Nock IBM Corporation, Dept. 917

20060284253 - Organic thin film transistor and method of manufacturing the same: An organic thin film transistor (OTFT) includes a substrate, a gate electrode formed on the transparent substrate, a gate insulation film formed on the gate electrode, a source electrode and a drain electrode formed spaced apart from each other on the gate insulation film, a device insulation film formed over... Agent: Morgan Lewis & Bockius LLP

20060284252 - Process for holding strain in an island etched in a strained thin layer and structure obtained by implementation of this process: The invention relates to structures useful for the manufacture of electronic components, which comprise a substrate, a strain holding layer, and a layer of a strained semiconducting material. These structures are particularly useful where islands are later formed in the strained semiconducting material because the strain holding layer limits relaxation... Agent: Winston & Strawn LLP

20060284254 - Pixel structures and methods for fabricating the same: Pixel structures and methods for fabricating the same are provided. The pixel structure comprises a thin film transistor formed on a substrate. The thin film transistor comprises a gate electrode and an active layer. The active layer comprises a source region and a drain region doped with a first dopant.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20060284255 - Complementary field-effect transistors having enhanced performance with a single capping layer: Performance of a complementary metal-oxide-semiconductor (CMOS) device having n-channel MOS transistors and p-channel MOS transistors is enhanced by providing a single capping layer overlying the MOS transistors with the single capping layer inducing stress in the transistor channel regions to enhance carrier mobility. The n-channel transistor is preferably fabricated in... Agent: Beyer Weaver & Thomas, LLP

20060284257 - Display substrate and apparatus and method for testing display panel having the same: A display substrate includes a gate pad part, a source pad part, a first static dissipative part, and a first test part. A gate pad part is formed on one terminal of each of a plurality of gate lines and transfers signals to the gate lines. A source pad part... Agent: Cantor Colburn, LLP

20060284256 - Layout structure for esd protection circuits: The present invention provides a layout structure for an electrostatic discharge (ESD) protection circuit. The layout structure includes a first MOS device area, a second MOS device area, and a doped region. The first MOS device area has at least one source/drain region of a first polarity type. The second... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20060284258 - Divided drain implant for improved cmos esd performance: A divided drain implant structure for transistors used for electrostatic discharge protection is disclosed. At least two transistors are formed close to each other on a substrate with their gates and sources coupled together and with the drains placed next to each other and separated as a divided drain implant... Agent: Howard Chen Preston Gates & Ellis LLP

20060284259 - Semiconductor device and method of manufacturing the same: In a semiconductor device having asymmetric bit lines and a method of manufacturing the same, a plurality of active regions are electrically isolated from one another by an isolation layer. Each active region extends in a first direction and has a central portion between end portions. The device includes a... Agent: Harness, Dickey & Pierce, P.L.C

20060284260 - Vertical diode formation in soi application: A method for making a semiconductor device is provided. The method comprises (a) providing a semiconductor stack comprising a semiconductor substrate (203), a first semiconductor layer (205), and a first dielectric layer (207) disposed between the substrate and the first semiconductor layer; (b) forming a first trench in the first... Agent: Fortkort & Houston P.C.

20060284261 - Semiconductor devices having varying electrode widths to provide non-uniform gate pitches and related methods: Semiconductor devices including a plurality of unit cells connected in parallel are provided. Each of the unit cells have a first electrode, a second electrode and a gate finger. One of the first electrodes at a center of the semiconductor device has a first width and one of the first... Agent: Myers Bigel Sibley & Sajovec

20060284262 - Semiconductor wafer having different impurity concentrations in respective regions: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate... Agent: Volentine Francos, P.l.l.c.

20060284263 - Semiconductor device and fabrication method thereof: A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over the silicon-containing conductive layer. The protection layer is disposed over the refractory metal salicide... Agent: Jianq Chyun Intellectual Property Office

20060284264 - Semiconductor device and manufacturing method thereof: A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconductor device having gate electrodes of a polymetal gate structure and... Agent: Mcdermott Will & Emery LLP

20060284265 - High voltage n-channel ldmos devices built in a deep submicron cmos process: A novel Laterally Diffused NMOS device is described. With proper design the drain terminal of this device can be raised to a much higher voltage that the maximum allowed gate voltage of the CMOS technology into which the device is built. The device can be built in a conventional deep... Agent: Berkeley Law & Technology Group

20060284266 - High voltage n-channel ldmos devices built in a deep submicron cmos process: A novel Laterally Diffused NMOS device is described. With proper design the drain terminal of this device can be raised to a much higher voltage that the maximum allowed gate voltage of the CMOS technology into which the device is built. The device can be built in a conventional deep... Agent: Berkeley Law & Technology Group

20060284267 - Flash memory and fabrication method thereof: A flash memory comprises a substrate, control gates, doped regions, an isolation layer, isolation structures, floating gates, tunneling dielectric layers and inter-gate dielectric layers. The control gates are arranged over the substrate with a first direction, and the doped regions are arranged within the substrate with a second direction. The... Agent: J C Patents, Inc.

20060284268 - Semiconductor integrated circuit device: A control gate includes a first conductive film formed in contact with an inter-gate insulating film and a second conductive film electrically connected to the first conductive film. An inter-level insulating film which insulates first and second stacked gate structures from each other. The inter-level insulating film includes a first... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060284269 - Method for forming raised structures by controlled selective epitaxial growth of facet using spacer: Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of monocrystalline silicon on the surface of a semiconductive substrate, and forming a thin film... Agent: Whyte Hirschboeck Dudek S.c.

20060284270 - Semiconductor device and method for manufacturing the same: The present invention discloses improved semiconductor device and method for manufacturing wherein one side of a source and drain region and a portion of a channel region are disposed on a buried oxide layer formed on a semiconductor substrate and the side of the source and drain region and another... Agent: Heller Ehrman White & Mcauliffe LLP

20060284271 - Metal gate device with reduced oxidation of a high-k gate dielectric: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such... Agent: Intel Corporation C/o Intellevate, LLC

20060284272 - Gate structure and method for preparing the same: The present gate structure comprises a gate oxide layer positioned on a substrate, a conductive stack positioned on the gate oxide layer, a passivation layer positioned on the sidewall of the conductive stack, and a cap layer positioned on the conductive stack. The conductive stack includes a polysilicon layer, a... Agent: Oliff & Berridge, PLC

20060284273 - Cmos image sensor and method for fabrication thereof: There are provided a CMOS image sensor and a method for fabrication thereof. The CMOS image sensor having a reset transistor, a select transistor, a drive transistor and a photodiode, includes an active region in shape of a line, a gate electrode of the drive transistor, which is intersected with... Agent: Morgan Lewis & Bockius LLP

20060284274 - Cmos image device with local impurity region and method of manufacturing the same: According to a CMOS image device and a method of manufacturing same, dark current is decreased by a local impurity region. The image device includes a semiconductor substrate, and a transfer gate formed on a predetermined portion of the semiconductor substrate and electrically insulated from the semiconductor substrate. A photodiode... Agent: Myers Bigel Sibley & Sajovec

20060284275 - Optical sensor element and sensor array: The invention relates to an optical sensor element (10) which comprises, in a semiconductor substrate (1), a light-sensitive region (18) in which charge carriers can be released by irradiation, and two doped regions (15, 16) for receiving the charge carriers released in the light-sensitive region (18). The invention is characterized... Agent: Akerman Senterfitt

20060284276 - High voltage semiconductor devices with jfet regions containing dielectrically isolated junctions: A high-voltage field-effect device contains an extended drain or “drift” region having a plurality of JFET regions separated by portions of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and at least two sides of... Agent: Silicon Valley Patent Group LLP

20060284277 - Semiconductor device including bit line formed using damascene technique and method of fabricating the same: A semiconductor device includes an insulating layer having a T-shaped groove formed by a wide opening overlapping a narrow opening, a bit line conductive layer that at least partially fills the narrow opening, and a bit line capping layer that fills the groove so that its top surface is as... Agent: F. Chau & Associates, LLC

20060284278 - Area diode formation in soi application: A semiconductor device (201) is provided which comprises (a) a substrate (203) having a first dielectric layer (205) disposed thereon, (b) a second dielectric layer (207) disposed over a first region of the first dielectric layer, and (c) an implant region (209), disposed on the substrate, which extends through the... Agent: Fortkort Grether & Kelton LLP

20060284279 - Thin film fuse phase change ram and manufacturing method: A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode... Agent: Macronix C/o Haynes Beffell & Wolfeld LLP

20060284280 - Electrodes, inner layers, capacitors, electronic devices and methods of making thereof: A method of embedding thick-film fired-on-foil capacitors includes entirely covering the dielectric with an encapsulating electrode to avoid cracking in the dielectric due to shrinkage and temperature coefficient of expansion differences between the electrode and dielectric.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20060284281 - Three dimensional, 2r memory having a 4f2 cell size rram and method of making the same: A method of fabricating a multi-level 3D memory array includes: preparing a wafer and peripheral circuits thereon; layers of metal, memory resistor material, and metal are deposited, patterned and etched. The steps of the method of the invention are repeated for N levels of a memory array.... Agent: Robert D. Varitz

20060284282 - Heterjunction bipolar transistor with tunnelling mis emitter junction: A manufacturing method and structure for a MIS Heterojunction Bipolar Transistor (HBT) is provided including a GaAs substrate which has a collector region; a base layer coupled to the collector region; the ultra-thin insulating layer including a rare earth oxide coupled to the base layer; and an emitter structure including... Agent: Banner & Witcoff

20060284283 - Semiconductor device and manufacturing method thereof: A -Zener diode includes a first conductivity type semiconductor region and a second conductivity type semiconductor region which form pn junction, an insulating film for covering the junction part of the semiconductor regions, a first electrode electrically connected with the first conductivity type semiconductor region, and a second electrode electrically... Agent: Mcdermott Will & Emery LLP

20060284284 - Epitaxial semiconductor layer and method: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060284285 - Manufacturing method for a semiconductor device, semiconductor device, circuit substrate and electronic device: A manufacturing method for a semiconductor device, includes: preparing a semiconductor wafer having an active surface and a rear surface; forming a plurality of semiconductor regions, each of which having semiconductor elements formed on the active surface of the semiconductor wafer; forming cutting regions on the outer periphery of the... Agent: Harness, Dickey & Pierce, P.L.C

20060284286 - Flashless molding of integrated circuit devices: A method for encapsulating an IC package is performed, in one example embodiment, by providing a lead frame member including the IC chip mounted on a portion of the lead frame member, wherein the lead frame member further includes a plurality of apertures disposed substantially around the mounted IC chip.... Agent: Texas Instruments Incorporated

20060284287 - Two-pole smt miniature housing for semiconductor components and method for the manufacture thereof: In a two-pole SMT miniature housing in leadframe technique for semiconductor components, a semiconductor chip is mounted on one leadframe part and is contacted to a further leadframe part. The further leadframe part is conducted out of the housing in which the chip is encapsulated as a solder terminal. No... Agent: Fish & Richardson PC

20060284288 - Wafer and single chip having circuit rearranged structure and method for fabricating the same: A wafer and single chip having a circuit rearranged structure and method for fabricating the same are proposed. A wafer having a plurality of chips is provided. Each of the chip has an active surface having a plurality of electrode pads. A dielectric layer is formed on the active surface.... Agent: Mr. Joseph A. Sawyer, Jr. Sawyer Law Group LLP

20060284289 - Electronic component comprising a cooling surface: The invention relates to an electronic component comprising at least two connection elements (2, 7, 8), each provided with at least one contact surface (13.1, 13.2, 13.3, 9, 10) which is used to fix the electronic component (1) to a surface of a printed circuit board. An at least partially... Agent: Lewis, Rice & Fingersh, Lc Attn: BoxIPDept.

20060284290 - Chip-package structure and fabrication process thereof: The present invention discloses a chip-package structure and a fabrication process thereof, wherein a mount board is used as a support part, which is removed after completing the chip-package process, in order to promote the planarity, firmness and reliability of the entire package structure, to reduce the height of the... Agent: Rosenberg, Klein & Lee

20060284291 - Lead frame structure with aperture or groove for flip chip in a leaded molded package: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes... Agent: Townsend And Townsend And Crew, LLP

20060284295 - Method and system for hermetically sealing packages for optics: A system for hermetically sealing devices. The system includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of... Agent: Townsend And Townsend And Crew, LLP

20060284294 - Optical device package: An optical device package includes a substrate having an upper surface, a distal end, a proximal end, and distal and proximal longitudinally extending notches co-linearly aligned with each other. A structure is mounted to the substrate and has at least one recessed portion. The structure can be a lid or... Agent: Jonathan D. Baskin Rohm And Haas Electronic Materials LLC

20060284292 - Package structure of chip and the package method thereof: For a package structure of chip and the formation thereof, adhesive, conductive and metal layers are positioned on a substrate. The portions of the conductive and metal layers are removed to form multitudes of trenches therethrough, so that the metal layer is divided into chip supporters and conductive nodes isolated... Agent: Rosenberg, Klein & Lee

20060284296 - Semiconductor device: A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal... Agent: Stanley P. Fisher Reed Smith Hazel & Thomas LLP

20060284293 - Semiconductor integrated circuit and device and method for testing the circuit: An accelerated test for transistors included in inverter circuits of a semiconductor integrated circuit is to be improved in efficiency. Output terminals 30A, 30B of inverter circuits 11, 12, each including a CMOS circuit, may be short-circuited. A test circuit 20 supplies signals of mutually exclusive logical values to the... Agent: Young & Thompson

20060284298 - Chip stack package having same length bonding leads: A chip stack package has semiconductor chips connected to the substrate by the same signal pathway lengths to prevent malfunction of the semiconductor chips. In the chip stack package, first and second semiconductor chips disposed opposite to each other. The first and second semiconductor chips having bonding bumps are bonded... Agent: Ladas & Parry LLP

20060284297 - Memory card stack circuit wiring structure: A memory card stack circuit wiring structure includes a control chip and a flash memory installed on a substrate in a stack. The layout of circuit wiring is such that the control chip can be connected with the substrate in an L- or U-shape method, in order to simplify the... Agent: Troxell Law Office PLLC

20060284299 - Module having stacked chip scale semiconductor packages: Stacked CSP (chip scale package) modules include a molded first (“top”) chip scale package having a molding side and a substrate side, and a second (“bottom”) package affixed to the substrate side of the top chip scale package, the second package being electrically connected to the first package by wire... Agent: Haynes Beffel & Wolfeld LLP

20060284300 - Module with built-in component and method for manufacturing module: A module with a built-in component is produced by disposing a cavity on a mounting surface side of a ceramic multilayer substrate, storing a circuit component therein and, thereafter, performing resin molding. A second resin portion is disposed on the mounting surface side of the ceramic multilayer substrate so as... Agent: Murata Manufacturing Company, Ltd. C/o Keating & Bennett, LLP

20060284301 - Csp semiconductor chip and bga assembly with enhanced physical protection, protective members and assemblies used with same, and methods of enhancing physical protection of chips and assemblies: Chip scale package semiconductor devices include a semiconductor chip and a protective member attached to an active surface of the semiconductor chip. At least one electrically conductive pad of the semiconductor chip is exposed through the protective member. The protective member includes a cantilevered portion that extends laterally beyond a... Agent: Trask Britt, P.C.

20060284302 - Semiconductor integrated circuit including a power supply, semiconductor system including a semiconductor integrated circuit, and method of forming a semiconductor integrated circuit: Provided are a semiconductor integrated circuit including a power supply, a semiconductor system including the semiconductor integrated circuit, and a method of forming the semiconductor integrated circuit. The semiconductor integrated circuit includes: a semiconductor substrate on a surface of which a plurality of electrical circuits and a plurality of power... Agent: Harness, Dickey & Pierce, P.L.C

20060284303 - Light-emitting device and light source apparatus using the same: In a light-emitting device, a mount member mounting a semiconductor light-emitting element is mounted on a circuit board. A multilayer board is used for the mount member. A first conductive pattern formed on the surface layer of the multilayer board and a semiconductor light-emitting element are electrically connected. On the... Agent: Osha Liang L.L.P.

20060284304 - Wirebond electronic package with enhanced chip pad design, method of making same, and information handling system utilizing same: A wirebond electronic package which includes a semiconductor chip bonded to the upper surface of an organic laminate substrate, including to a thermal material located on the substrate and comprised of a plurality of thermally conductive concentric lines. These lines form paths of heat escape for the chip during operation... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20060284305 - Packaging base for semiconductor elements: A packaging base for semiconductor elements is made of metal powder selected from the group consisting of cupper (Cu), iron (Fe), wolfram (W), molybdenum (Mo), aluminum (Al), indium (In), and gallium (Ga) or from an alloy of combinations thereof. A heat sink is integrally formed by metallurgical injection molding process.... Agent: Rosenberg, Klein & Lee

20060284307 - Component with sensitive component structures and method for the production thereof: An electrical component has electrically conducting structures placed on an electrically isolating or semiconductive substrate and component structures sensitive to a voltage or an electrical arcing and galvanically separated from one another. To prevent an arcing between the galvanically separated component structures, the component structures are short-circuited with a shunt... Agent: Gregory L. Mayback, P.A.

20060284306 - Multi-chip type semiconductor device: A first semiconductor chip (1) of a high withstand voltage and a second semiconductor chip (2) of a low withstand voltage are connected to each other in a package (3). The first semiconductor chip (1) has a voltage conversion circuit (4), a plurality of first inter-chip connection portions (10) for... Agent: Steptoe & Johnson LLP

20060284308 - Power converter and semiconductor device mounting structure: An electric power converter has a main circuit section including a semiconductor module and a cooling device; a control circuit substrate section electrically connected to a signal terminal of the semiconductor module, and having a control circuit; and a power wiring section connected to a main electrode terminal of the... Agent: Oliff & Berridge, PLC

20060284309 - Integrated circuit package and integrated circuit module: An integrated circuit package may include a board that may support an integrated circuit chip. A post pin may be provided on a surface of the board. The post pin may be electrically connected to the integrated circuit chip. A land pin may be provided on the other surface of... Agent: Harness, Dickey & Pierce, P.L.C

20060284312 - Flip chip packaging using recessed interposer terminals: A method and apparatus for packaging a semiconductor die with an interposer substrate. The semiconductor device assembly includes a conductively bumped semiconductor die and an interposer substrate having multiple recesses formed therein. The semiconductor die is mounted to the interposer substrate with the conductive bumps disposed in the multiple recesses... Agent: Trask Britt

20060284311 - Method of manufacturing self-aligned contact openings and semiconductor device: A method of manufacturing self-aligned contact openings is provided. A substrate having a plurality of device structures is provided and the top of the device structures is higher than the surface of the substrate. A first dielectric layer and a conductive layer are sequentially formed on the surfaces of the... Agent: Jianq Chyun Intellectual Property Office

20060284310 - Offset via on pad: A printed circuit board with an electrically conductive bonding pad disposed on an outer surface of the printed circuit board. The bonding pad has a bonding pad perimeter at immediately bounding edges of the bonding pad. An electrically conductive via directly electrically contacts the bonding pad, and is disposed within... Agent: Lsi Logic Corporation

20060284313 - Low stress chip attachment with shape memory materials: Some embodiments of the present invention include low stress chip attachment with shape memory materials.... Agent: Blakely Sokoloff Taylor & Zafman

20060284314 - Multi-package module and electronic device using the same: A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20060284315 - Semiconductor device and circuit board: A semiconductor device 1 includes a silicon substrate 5, a semiconductor chip 2 placed on a surface S1 of the silicon substrate 5, a protruding electrode 6 (first protruding electrode) provided on a surface S2 of the semiconductor chip 2 opposite to the silicon substrate 5, and another protruding electrode... Agent: Young & Thompson

20060284316 - Chip size package: A chip size package comprises a substrate to one surface of which a chip is mounted, a solder ball land formed on the other surface of the substrate and having a projecting center part, a solder mask formed on the other surface of the substrate and having an opening for... Agent: Ladas & Parry LLP

20060284317 - Semiconductor device and a fabrication process thereof: A method of fabricating a semiconductor device comprises the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060284318 - Semiconductor device and method for fabricating the same: According to a method for fabricating a semiconductor device, a first semiconductor layer made of a first nitride semiconductor is formed over a substrate. Thereafter, a mask film covering part of the upper surface of the first semiconductor layer is selectively formed on the first semiconductor layer. A multilayer film,... Agent: Panasonic Patent Center C/o Mcdermott Will & Emery LLP

20060284319 - Chip-on-board assemblies: An apparatus and method for preventing damage to tape attachment semiconductor assemblies due to encapsulation filler particles causing damage to a semiconductor die active surface and/or to a corresponding semiconductor substrate surface by providing an adhesive tape which extends across areas of contact between the semiconductor die active surface and... Agent: Trask Britt, P.C.

20060284320 - Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board: An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device (10) having a semiconductor chip (12) with electrodes (16), a... Agent: Oliff & Berridge, PLC

20060284321 - Led structure for flip-chip package and method thereof: LED structure can be packaged by using flip-chip package. An LED structure is covered by a conduction enhancing layer. A bumping area definition layer is then formed on the conduction enhancing layer to expose bumping area portions with p-pad and n-pad underneath, and a bumping pad is then formed over... Agent: Bacon & Thomas, PLLC

20060284322 - Electronic board, method of manufacturing the same, and electronic device: An electronic board includes: a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor that has a first electrode that is disposed... Agent: Harness, Dickey & Pierce, P.L.C

20060284323 - Electronic board, method of manufacturing the same, and electronic device: An electronic board includes a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; a rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor. The capacitor has a first electrode that... Agent: Harness, Dickey & Pierce, P.L.C

20060284324 - Power-up and power-down circuit for system-on-a-chip integrated circuit: A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second... Agent: Sierra Patent Group, Ltd.

20060278863 - Phase change ram device and method for fabricating the same: Disclosed are a phase change RAM device and a method for fabricating a phase change RAM device, which can efficiently lower intensity of current required for changing a phase of a phase change layer. The method includes the steps of providing a semiconductor substrate formed with an insulating interlayer including... Agent: Ladas & Parry LLP

20060278864 - Light-emitting device: A light-emitting device is equipped with a GaN substrate; an n-type AlxGa1-xN layer on a first main surface side of the GaN substrate; a p-type AlxGa1-xN layer positioned further away from the GaN substrate than the n-type AlxGa1-xN layer; and a multi-quantum well (MQW) positioned between the n-type AlxGa1-xN layer... Agent: Darby & Darby P.C.

20060278865 - Non-polar (al,b,in,ga)n quantum well and heterostructure materials and devices: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11{overscore (2)}0) a-plane GaN layers are grown on an r-plane (1{overscore (1)}02) sapphire substrate using MOCVD. These non-polar (11{overscore (2)}0) a-plane GaN layers comprise templates for producing non-polar (Al, B, In, Ga)N quantum well and heterostructure... Agent: Attention Of George H. Gates Gates & Cooper LLP

20060278866 - Nanotube optoelectronic memory devices: Nanotube transistors are coated with optically responsive agents to form optoelectronic detectors. In response to illumination, an electronic property of the inventive detector changes from one value to another. It retains the new value when the illumination is removed, so that the detector remembers having been illuminated. The detector can... Agent: Alexander Star

20060278868 - Functional molecular element, method for producing functional molecular element, and functional molecular device: A functional molecular element with a reduced contact resistance between the constituting molecule and the electrode, a method for production thereof, and a functional molecular device are provided herein. The method consists of the following steps. A closely adhering molecular monolayer is formed on the surface of the electrodes from... Agent: Bell, Boyd & Lloyd, LLC

20060278867 - Living synthesis of conducting polymers including regioregular polymers, polythiophenes, and block copolymers: Regioregular poly(3-alkylthiophenes) and other polythiophenes can be prepared by living polymerization which have good solubility, processability and environmental stability. The polymerization method can afford regioregular poly(3-alkylthiophenes) in high yields. Kinetic study of polymerization revealed the living character of this process. The molecular weight of poly(3-alkylthiophenes) is a function of the... Agent: Foley And Lardner LLP Suite 500

20060278869 - Photoelectric conversion layer, photoelectric conversion device and imaging device, and method for applying electric field thereto: g

20060278870 - Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method: A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric layer defines at least one area where the thin... Agent: Slater & Matsil, L.L.P.

20060278871 - Detecting and improving bond pad connectivity with pad check: A method for analyzing an integrated circuit (or constituent parts thereof), a computer program implementing the method, and a computer configured to execute the program is disclosed. Analyzing the integrated circuit may include retrieving a design for the integrated circuit from a layout database, identifying the bond pads and gates... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies

20060278873 - Liquid crystal display apparatus: A thin film transistor is provided in a vicinity of a crossing region of scanning and the data lines on a first substrate. A pixel electrode is connected with the thin film transistor. A transparent electroconductive layer which is applied with a common potential is provided between the pixel electrodes... Agent: Frishauf, Holtz, Goodman & Chick, PC

20060278874 - Liquid crystal display device: The liquid crystal display device of this invention includes a plurality of picture element regions each defined by a first electrode provided on a face of a first substrate facing a liquid crystal layer and a second electrode provided on a second substrate so as to oppose the first electrode... Agent: Nixon & Vanderhye, PC

20060278872 - Switching device for a pixel electrode and methods for fabricating the same: The invention discloses a switching element of a pixel electrode for a display device and methods for fabricating the same. A gate is formed on a substrate. A first copper silicide layer is formed on the gate. An insulating layer is formed on the first copper silicide layer. A semiconductor... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20060278876 - Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain... Agent: Eric Robinson

20060278875 - Semiconductor device and manufacturing method thereof: The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film... Agent: Fish & Richardson P.C.

20060278878 - Semiconductor device equipped with semiconductor circuits composed of semiconductor elements and processes for production thereof: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400-700° C.) is possible because the wiring is made of Ta film or... Agent: Eric Robinson

20060278877 - Thin film transistor array panel and method of manufacturing the same: A thin film transistor (“TFT”) array panel is provided. The TFT array panel includes an insulation substrate, a gate line formed on the insulation substrate and including a gate electrode, a data line insulated from and intersecting the gate line, and including a source electrode, a drain electrode opposite to... Agent: Cantor Colburn, LLP

20060278879 - Nanochannel device and method of manufacturing same: The invention provides a device comprising a substrate, a first material disposed on the substrate to form a first material layer, a second material disposed on the substrate to form a second material layer, and a nanochannel bounded by the substrate, the first material layer, and the second material layer.... Agent: Steven Weseman Associate General Counsel, I.p.

20060278880 - Light emitting semiconductor device: A novel NPBL and ANPL light emitting semiconductor device and a method for fabricating the same are provided. In the present invention, plural nano-particles are applied in the active layer of the light emitting semiconductor device, so that the leakage current thereof is reduced. In addition, the provided light emitting... Agent: Silicon Valley Patent Group LLP

20060278883 - Light-emitting devices having an antireflective layer that has a graded index of refraction and methods of forming the same: A light-emitting device includes a substrate that is at least partially transparent to optical radiation and has a first index of refraction. A diode region is disposed on a first surface of the substrate and is configured to emit light responsive to a voltage applied thereto. An encapsulation layer is... Agent: Myers Bigel Sibley & Sajovec

20060278882 - Power lamp package: Adhesive-free assembly of the substrate and reflector components of a semiconductor die package is achieved by injection molding the reflector onto a surface of the substrate or by molding the reflector separate from the substrate and securing it in place on the substrate through deformation of a portion of the... Agent: Koppel, Patrick & Heybl

20060278881 - Reflection type light-emitting diode device: A reflection type light-emitting diode device of a kind capable of emitting rays of light to the outside after having been reflected by a reflecting surface includes a recessed casing (22) having a cavity defining the reflecting surface (15) and also having a pair of bearing grooves (17a and 17b)... Agent: Sughrue Mion, PLLC

20060278885 - Led wafer-level chip scale packaging: A structure of light emitting diode (LED) wafer-level chip scale packaging (WL-CSP) is disclosed. The process of making the same is also provided in this invention. The LED CSP utilizes the through hole metal filling to enhance heat conduction between the LED die and its carrier substrate. The CSP structure... Agent: Lowe Hauptman Berner, LLP

20060278886 - Light emitting diode, method of manufacturing light emitting diode, light emitting diode backlight, light emitting diode illuminating device, light emitting diode display, and electronic apparatus: A light emitting diode is provided. The light emitting diode includes a semiconductor layer that forms a light emitting diode structure and has a major face and an end face inclined at an angle θ1 to the major face, and a reflector that is provided outside the end face with... Agent: Bell, Boyd & Lloyd, LLC

20060278884 - Substrate-free flip chip light emitting diode and manufacturing method thereof: A substrate-free LED device is provided. The LED device comprises a substrate, an epitaxial layer disposed on the substrate, a first electrode disposed on a portion of the epitaxial layer, a second electrode disposed on another portion of the epitaxial layer, and a protection layer, disposed over the epitaxial layer.... Agent: J C Patents, Inc.

20060278887 - White light-emitting diode and manufacturing method therefor: The present invention relates to a white light-emitting diode which emits white light by combining a blue light emitted from a light-emitting diode chip for emitting the blue light, with a light that is emitted through being excited by the blue light emitted from the light-emitting diode chip; and a... Agent: Staas & Halsey LLP

20060278888 - Vertically-structured nitride semiconductor light emitting diode: The present invention relates to a vertically-structured nitride semiconductor light emitting diode. The vertically-structured nitride semiconductor light emitting diode includes an n-type electrode; an n-type nitride semiconductor layer that is formed on the lower surface of the n-type electrode and on which surface texturing with a diffraction grating structure is... Agent: Mcdermott Will & Emery LLP

20060278889 - Power rectifier and manufacturing method thereof: A power rectifier and its manufacturing method are proposed in the present invention. A cylinder-shaped PN junction is formed during the manufacturing process of the power rectifier. Via the effect of the curved surface of the cylinder-shaped PN junction, a breakdown path under a reverse bias is provided so as... Agent: Birch Stewart Kolasch & Birch

20060278890 - Organic solar cell comprising an intermediate layer with asymmetrical transport properties: The invention relates to an organic solar cell comprising a photoactive layer consisting of two molecular components, namely an electron donator and an electrode acceptor, and comprising two electrodes provided on both sides of the photoactive layer, whereby an intermediate layer having an asymmetric conductivity is placed between at least... Agent: Fish & Richardson PC

20060278891 - Highly uniform group iii nitride epitaxial layers on 100 millimeter diameter silicon carbide substrates: A semiconductor structure is disclosed that includes a silicon carbide wafer having a diameter of at least 100 mm with a Group III nitride heterostructure on the wafer that exhibits high uniformity in a number of characteristics. These include: a standard deviation in sheet resistivity across the wafer less than... Agent: Summa, Allan & Additon, P.A.

20060278892 - Gallium nitride based high-electron mobility devices: A heterojunction device includes a first layer of p-type aluminum gallium nitride; a second layer of undoped gallium nitride on the first layer; a third layer of aluminum gallium nitride on the second layer; and an electron gas between the second and third layers. A heterojunction between the first and... Agent: Volentine Francos, & Whitt PLLC

20060278893 - A hybrid bypolar-mos trench gate semiconductor device: An improved MOS device is disclosed that utilizes a voltage configuration shorting the body and the gate, and independently biasing the source. As a result, the device functions as a trench MOS device with an NPN bipolar transistor in parallel therewith, permitting a smaller size device to perform the DC-DC... Agent: Philips Intellectual Property & Standards

20060278894 - Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same: The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same. In one illustrative embodiment, an integrated circuit is provided that comprises a plurality of voltage supply structures formed above a substrate, the plurality of... Agent: Williams, Morgan & Amerson

20060278895 - Reprogrammable fuse structure and method: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed... Agent: Paul D. Greeley, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20060278896 - Solid-state image sensing device: A solid-state image sensing device has a pixel that includes a photodiode that generates an electrical charge according to an amount of incoming light, a floating diffusion portion, a charge transfer transistor that transfers the electrical charge to the floating diffusion portion from the photoelectric conversion portion, a reading circuit... Agent: Fitzpatrick Cella Harper & Scinto

20060278897 - Multispectral energy/power meter for laser sources: A device for measuring optical power simultaneously for two or more spectral regions. Two or more photodetectors, such as photodiodes, measure the pulse energy and/or power emitted by a laser having output in two or more spectral regions. The laser radiation is transmitted through a diffuser or beamsplitter, then filtered... Agent: Greenberg Traurig, LLP

20060278898 - Backside-illuminated photodetector and method for manufacturing same: The present invention provides a back illuminated photodetector having a sufficiently small package as well as being capable of suppressing the scattering of to-be-detected light and method for manufacturing the same. A back illuminated photodiode 1 comprises an N-type semiconductor substrate 10, a P+-type impurity semiconductor region 11, a recessed... Agent: Drinker Biddle & Reath (dc)

20060278899 - Phase change ram device and method for manufacturing the same: A phase change RAM device includes a semiconductor substrate having a phase change cell area and a voltage application area; a first oxide layer, a nitride layer and a second oxide layer sequentially formed on the semiconductor substrate; a first plug formed in the first oxide layer, the nitride layer... Agent: Ladas & Parry LLP

20060278900 - Phase change memory device having an adhesion layer and manufacturing process thereof: A memory includes a phase change memory element having a memory layer of a calcogenide material and a glue layer of an alloy of the form TiaXbNc where X is selected in the group comprising silicon, aluminum, carbon, or boron, and c may be 0. The nitrogen and silicon are... Agent: Seed Intellectual Property Law Group PLLC

20060278901 - In-chip structures and methods for removing heat from integrated circuits: An in-chip system and method for removing heat from integrated circuits is disclosed. One embodiment is a substrate with a front side and a back side. The front side of the substrate is capable of having formed thereon a plurality of transistors. A plurality of structures within the substrate contain... Agent: Morgan, Lewis & Bockius, LLP.

20060278902 - Nano structure electrode design: A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are... Agent: Lsi Logic Corporation

20060278903 - Semiconductor device with electrostrictive layer in semiconductor layer and method of manufacturing the same: A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first... Agent: Foley And Lardner LLP Suite 500

20060278904 - Image pickup device: An image pickup device includes a plurality of photoelectric transducers; and a diffusion-reflection layer provided in front of the plurality of photoelectric transducers, wherein a part of light incident on the diffusion-reflection layer is reflected and dispersed therefrom, and the remainder of the incident light is transmitted through the diffusion-reflection... Agent: Greenblum & Bernstein, P.L.C

20060278905 - Cmos pixel with dual gate pmos: A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P+ type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N− well will... Agent: Saile Ackeman LLC

20060278906 - Image sensor: An image sensor includes a substrate, transparent layers covering the substrate and delimiting an exposition surface exposed to light, separate photosensitive areas at the substrate level and, for each photosensitive area, a first optical means capable of deviating towards the photosensitive area light reaching a central region of a portion... Agent: Graybeal, Jackson, Haley LLP

20060278907 - Semiconductor element, semiconductor sensor and semiconductor memory element: A semiconductor element, a semiconductor sensor, and a semiconductor memory element are provided, in which an MFMIS structure having a lower electrode and an integrated circuit can be integrated. An epitaxially grown γ-Al2O3 single crystal film (2) is disposed on a semiconductor single crystal substrate (1), and an epitaxial single... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060278908 - Write line design in mram: A magnetic random access memory device (MRAM) and the method for forming the same are disclosed. The MRAM has a magnetic tunnel junction (MTJ) device, a first write line, and a second write line orthogonal to the first write line, wherein at least one of the first and second write... Agent: Duane Morris, LLPIPDepartment

20060278909 - Mis transistor and cmos transistor: A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of... Agent: Morgan & Finnegan, L.L.P.

20060278911 - Relaxed-pitch method of aligning active area to digit line: According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at least two drains defining a first axis. The memory device further comprises at least two substantially parallel word lines, at least a portion of... Agent: Knobbe Martens Olson & Bear LLP

20060278912 - Selective polysilicon stud growth: A memory cell having a bit line contact and a method of manufacturing the memory cell is provided The memory cell may be a 6F2 or smaller memory cell. The bit line contact may have a contact hole bounded by insulating side walls, the contact hole may have a selective,... Agent: Dinsmore & Shohl LLP

20060278910 - Vertical transistor, memory cell, device, system and method of forming same: A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate. A first source/drain region is formed in the substrate and a body region and a second source/drain region are formed within the pillar. A first... Agent: Trask Britt, P.C.

20060278913 - Non-volatile memory cells without diffusion junctions: A plurality of memory cell stacks are formed over a substrate. The substrate does not have diffusion regions between each memory cell stack to link the memory cells. The cells are formed close enough such that the memory cells are linked serially by the electric fields generated by each floating... Agent: Leffert Jay & Polglaze, P.A.

20060278914 - Semiconductor device: A semiconductor device including a nonvolatile memory element, the nonvolatile memory element, including: a first region, a second region formed adjacent to the first region, and a third region formed adjacent to the second region; the nonvolatile memory element further including a semiconductor layer, a separating insulation layer which is... Agent: Harness, Dickey & Pierce, P.L.C

20060278915 - Finfet split gate eeprom structure and method of its fabrication: A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel... Agent: Slater & Matsil, L.L.P.

20060278917 - Floating gate structures: Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060278916 - Non-volatile semiconductor memory device having a two-layer gate electrode transistor and method of manufacturing the device: A non-volatile semiconductor memory device has a gate insulating film formed on a semiconductor substrate between isolation regions, a first gate electrode formed on the gate insulating film, an intergate insulating film formed on the first gate electrode, and a second gate electrode formed on the intergate insulating film. The... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060278918 - Semiconductor device and method for fabricating the same: A semiconductor device includes a bit line formed in a semiconductor substrate, a first interconnection line provided above the bit line and connected to the bit line, and a second interconnection line provided above the first interconnection line and connected to the first interconnection line and a transistor in a... Agent: Ingrassia Fisher & Lorenz, P.C.

20060278919 - Semiconductor device and method for semiconductor device: A semiconductor device includes a semiconductor substrate, a memory cell region provided on the semiconductor substrate, a word line provided on the memory cell region, a first gate insulating film provided in the memory cell region beneath the word line, a first floating gate electrode provided on the first gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060278920 - Metal oxide semiconductor field-effect transistor (mosfet) and method of fabricating the same: A Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) is provided. The MOSFET includes a semiconductor substrate, a device isolating region disposed on a predetermined portion of the semiconductor substrate to define an active region, a source region and a drain region spaced apart from each other about a channel region within... Agent: F. Chau & Associates, LLC

20060278921 - Vertical mosfet transistor, in particular operating as a selector in nonvolatile memory devices: A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first... Agent: Seed Intellectual Property Law Group PLLC

20060278922 - Trench transistor with increased avalanche strength: In order to obtain an increased avalanche strength, a trench transistor is proposed in which the breakdown location is defined in a trench bottom region below body contact zones. This is done by means of a modulation of the dopant concentration in a drift zone and an insulation layer thickness... Agent: Dicke, Billig & Czaja, P.l.l.c.

20060278923 - Integrated circuit and method for manufacturing an integrated circuit: An integrated circuit is disclosed that includes a component region with at least one NDMOS transistor and at least one PDMOS transistor and a substrate, which is isolated from the component region by a dielectric, whereby the component region, dielectric, and substrate form a first substrate capacitance standardized to a... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20060278924 - High-voltage mos device: A high-voltage MOS device includes a substrate; a drift ion well formed in the substrate; a first isolation region formed in the drift ion well; a gate electrode formed on the substrate and covering a portion of the first isolation region; a drain doping region disposed adjacent to the first... Agent: North America Intellectual Property Corporation

20060278925 - Power semiconductor device: A power semiconductor device has a first base layer of first conductive type, a contact layer of first conductive type formed on a surface of the first base layer, a second base layer of first conductive layer which is formed on the surface of the first base layer at a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060278927 - Body biasing structure of soi: A body biasing structure of devices connected in series on an SOI substrate is provided. According to some embodiments, the shallow junction of common source/drain regions enables all devices to bias by only one body contact on an SOI substrate like a conventional bulk MOSFET, and the floating body effect... Agent: Marger Johnson & Mccollom, P.C.

20060278926 - Capacitorless dram on bulk silicon: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A... Agent: Knobbe Martens Olson & Bear LLP

20060278928 - Semiconductor layout structure for esd protection circuits: A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning... Agent: Howard Chen Preston Gates & Ellis LLP

20060278929 - Active matrix substrate: An active matrix substrate is provided, including a substrate, a plurality of pixel units, a static releasing conductive line and an ESD protection circuit, wherein the substrate has an active area and a peripheral area adjacent to each other. The pixel units are arranged in the active area in an... Agent: Jianq Chyun Intellectual Property Office

20060278930 - Esd protection circuit using a transistor chain: An electrostatic discharge (ESD) protection circuit for dissipating an ESD current from a first pad to a second pad during an ESD event. The ESD protection circuit includes a first bipolar transistor having an emitter coupled to the first pad. A second bipolar transistor having a base and a collector... Agent: Howard Chen Preston Gates & Ellis LLP

20060278931 - Electrostatic protection device for semiconductor circuit: The electrostatic protection device includes a semiconductor substrate having a well formed therein. At least two sets of transistor fingers, for example the NMOS type, are spaced apart from each other. Each set of the MOS fingers includes multiple gates arranged in parallel to each other in one direction, and... Agent: Ladas & Parry LLP

20060278932 - Secure electrically programmable fuse: The present invention provides electrically-programmable fuse structures having radiation inhibitive properties for preventing non-destructive security breaches by radiation imaging techniques such as X-ray imaging, without adversely effecting fuse programmability, and methods of designing the same.... Agent: International Business Machines Corporation Dept. 18g

20060278933 - Semiconductor device and manufacturing method thereof: A semiconductor device which is suitable for miniaturization, capable of improving variations in characteristics of a transistor and enhancing the current driving capability comprises a semiconductor substrate, an isolation protruding from the semiconductor substrate and having a width above the semiconductor substrate narrower than a width in the semiconductor substrate,... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060278934 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device including, on a substrate, a first conduction type MOS transistor having a gate electrode provided in a first trench formed in an insulation film on the substrate, and a second conduction type MOS transistor having a gate electrode provided in a second trench formed in the insulation... Agent: Sonnenschein Nath & Rosenthal LLP

20060278935 - Recessed transistors and methods of forming the same: According to some embodiments of the invention, there is provided recessed transistors without semiconductor substrate fences formed on the sidewalls of a device isolation layer and methods of forming the same. The recessed transistors and methods provide a way of removing the fences of the semiconductor substrate from the sidewalls... Agent: Marger Johnson & Mccollom, P.C.

20060278936 - Semiconductor device and fabrication method therefor: There are provided a semiconductor device and a fabrication method therefor including an ONO film (18) formed on a semiconductor substrate (10), a word line (24) formed on the ONO film (18), a bit line (20) formed in the semiconductor substrate (10), and a conductive layer (32) that is in... Agent: Ingrassia Fisher & Lorenz, P.C.

20060278937 - Semiconductor device and manufacturing method of the same: As shown in FIG. 2B, a gate electrode is formed on a gate insulating film on a semiconductor substrate. A high dielectric film with a dielectric constant higher than that of a silicon oxide film is used for the gate insulating film, and a platinum-rich silicide film is used for... Agent: Reed Smith LLP

20060278938 - Low-power multiple-channel fully depleted quantum well cmosfets: A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The... Agent: Mcdermott Will & Emery LLP

20060278939 - Pmos depletable drain extension made from nmos dual depletable drain extensions: In accordance with an embodiment of the invention, there is an integrated circuit device having a complementary integrated circuit structure comprising a first MOS device. The first MOS device comprises a source doped to a first conductivity type, a drain extension doped to the first conductivity type separated from the... Agent: Min, Hsieh & Hack LLP

20060278940 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor substrate; an insulation film provided on the semiconductor substrate; and an electrode provided on the insulation film, and containing boron and a semiconductor material, wherein at least one element of the group V and carbon is introduced into an interface between the insulation film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060278941 - Semiconductor device with a high-k gate dielectric and a metal gate electrode: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.... Agent: Intel Corporation

20060278942 - Antistiction mems substrate and method of manufacture: A composite wafer for fabricating MEMS devices is provided with a plurality of antistiction bumps, buried under a device layer of the composite wafer. The antistiction bumps are prepared lithographically, by patterning an antistiction material prior to the assembly of the composite wafer.... Agent: Jaquelin K. Spong

20060278943 - Accelerated particle and high energy radiation sensor: An accelerated electron detector comprises an array of monolithic sensors in a CMOS structure, each sensor comprising a substrate (10), an epi layer (11), a p+ well (12) and n+ wells (13) which are separated from the p+ well (12) by the epi layer (11). Integrated in the p+ well... Agent: Birch Stewart Kolasch & Birch 8110 Gatehouse Road

20060278944 - Organic photosensitive cells having a reciprocal-carrier exciton blocking layer: A photosensitive cell includes an anode and a cathode; a donor-type organic material and an acceptor-type organic material forming a donor-acceptor junction connected between the anode and the cathode; and an exciton blocking layer connected between the acceptor-type organic material of the donor-acceptor junction and the cathode, the blocking layer... Agent: Kenyon & Kenyon LLP

20060278945 - Electro-optical device, method of manufacturing the same, and image forming apparatus: An electro-optical device in which a plurality of light-emitting elements including a first electrode layer, a second electrode layer, and a light-emitting functional layer emitting light in accordance with a voltage between the first electrode layer and the second electrode layer are arranged, the device including: a main substrate; the... Agent: Oliff & Berridge, PLC

20060278946 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the... Agent: Rankin, Hill, Porter & Clark LLP

20060278947 - Image pickup apparatus, radiation image pickup apparatus and radiation image pickup system: The invention provides an image pickup apparatus which is provided with plural light receiving areas arranged two-dimensionally, and a vertical scanning circuit composed of plural unit circuit stages arranged in the vertical direction and a horizontal scanning circuit composed of plural unit circuit stages arranged in the horizontal direction, for... Agent: Fitzpatrick Cella Harper & Scinto

20060278948 - Solid-state image sensor and manufacturing method thereof: An object of the present invention is to provide a small solid-state image sensor which realizes significant improvement in sensitivity. The solid-state image sensor of the present invention includes a semiconductor substrate in which photoelectric conversion units are formed, a light-blocking film which is formed above the semiconductor substrate and... Agent: Greenblum & Bernstein, P.L.C

20060278949 - Semiconductor integrated circuit device and method for fabricating the same: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer... Agent: Mills & Onello LLP

20060278950 - Semiconductor device having first and second insulation separation regions: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface; a first insulation separation region disposed on the first surface of the semiconductor substrate; a second insulation separation region surrounded with the first insulation separation region and electrically isolated from the first insulation separation region;... Agent: Posz Law Group, PLC

20060278951 - Metal oxide semiconductor (mos) field effect transistor having trench isolation region and method of fabricating the same: A leakage current occurring on a boundary of a trench isolation region and an active region can be prevented in a Metal Oxide Semiconductor (MOS) Field Effect transistor, and a fabricating method thereof is provided. The transistor includes the trench isolation region disposed in a predetermined portion of a semiconductor... Agent: F. Chau & Associates, LLC

20060278952 - Semiconductor device and fabrication process thereof: There is provided a semiconductor device having a device isolation region of STI structure formed on a silicon substrate so as to define a device region, wherein the device isolation region comprises a device isolation trench formed in the silicon substrate, and a device isolation insulation film filling the device... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060278953 - Semiconductor memory device: A semiconductor device comprises a lower substrate, an interlayer insulation film formed on the lower substrate, a first wiring pattern having a first wiring layer formed on the lower substrate, a first fuse formed on the interlayer insulation film, and a first contact plug electrically connected between the first wiring... Agent: GlobalIPCounselors, LLP

20060278954 - Semiconductor device having interlayer insulating film covered with hydrogen diffusion barrier film and its manufacture method: An interlayer insulating film made of insulating material is formed on a semiconductor substrate. A hydrogen diffusion barrier film is formed on the interlayer insulating film, the hydrogen diffusion barrier film being made of material having a higher hydrogen diffusion barrier function than a hydrogen diffusion barrier function of material... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060278955 - Optoelectronic system and method for its manufacture: An optoelectronic system includes a printed circuit board having a ground pad and a bond pad as well as an optoelectronic element. The optoelectronic element is electrically connected to the bond pad via a bonding wire and is additionally fastened to the ground pad by a soldering connection. The ground... Agent: Kenyon & Kenyon LLP

20060278957 - Fabrication of semiconductor integrated circuit chips: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other, wherein each of the plurality of active circuit die areas has substantially four corners. An... Agent: North America Intellectual Property Corporation

20060278958 - Semiconductor arrangement and method for producing a semiconductor arrangement: A semiconductor arrangement having at least one semiconductor chip, which has, on one surface, an integrated circuit and at least one contact element which is electrically conductively connected to the latter, and having an edge protector, which at least partially covers an edge region on the surface of the semiconductor,... Agent: Dickstein Shapiro LLP

20060278956 - Semiconductor wafer with non-rectangular shaped dice: A semiconductor wafer having a plurality of dice formed on the wafer. The plurality of dice having non-rectangular shapes with at least one notched corner. A plurality of saw streets are defined between the plurality of dice. At an intersection of two of the plurality of saw streets, a distance... Agent: Morrison & Foerster LLP

20060278959 - Method for reducing leakage current in a semiconductor device: A method for reducing leakage current in a semiconductor structure is disclosed. One or more dielectric layers are formed on a semiconductor substrate, on which at least one device is constructed. A hydrogen-containing layer is formed over the dielectric layers. A silicon nitride passivation layer covers the dielectric layers and... Agent: Howard Chen Preston Gates & Ellis LLP

20060278960 - Y branch circuit and method for manufacturing the same: A Y branch circuit according to the present invention includes; a under clad; a circuit core, formed on the under clad and having a main core and two branch cores, connected to the main core, and an over clad that embeds the circuit core. The main core and the two... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20060278961 - Leadless semiconductor package: A leadless semiconductor package includes a lead frame, an adhesive, a chip, a plurality of first electrically conductive wires and a plurality of second electrically conductive wires. In this case, the lead frame has a chip paddle, a plurality of leads surrounding the chip paddle. The chip paddle has a... Agent: Bacon & Thomas, PLLC

20060278962 - Microelectronic loop packages: A microelectronic package including a dielectric element having a fold, a first run and a second run. The dielectric element also includes a first region on the first run, and a second region on the second run. The first and second runs define a cavity which has a first microelectronic... Agent: Tessera Lerner David Et Al.

20060278963 - Multi-layer substrate having conductive pattern and resin film and method for manufacturing the same: A multi-layer substrate connecting to an external electric device includes: a plurality of resin films; and a plurality of conductive patterns. The resin films are stacked together with the conductive patterns. The conductive pattern includes an inner conductive pattern and a surface conductive pattern. The inner conductive pattern is disposed... Agent: Posz Law Group, PLC

20060278965 - Hermetically sealed package and methods of making the same: Hermetically sealed packages having organic electronic devices are presented. A number of sealing mechanisms are provided to hermetically seal the package to protect the organic electronic device from environmental elements. A metal alloy sealant layer is employed proximate to the organic electronic device. Alternatively, a metal alloy sealant layer in... Agent: Patrick S. Yoder Fletcher Yoder

20060278964 - Plastic integrated circuit package, leadframe and method for use in making the package: A semiconductor package comprises a plurality of metal contacts, each contact having a first surface, a second surface opposite the first surface, and a locking mechanism to lock the contacts with an encapsulant material of the package. A plurality of extended metallic interconnections are provided, each having a first surface... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20060278966 - Contact-based encapsulation: An electrical connection between two chips includes an IC pad on a first chip, an IC pad on a second chip, a first barrier metal over the IC pad of the first chip, a second barrier metal over the IC pad of the second chip, a malleable electrically conductive metal,... Agent: Morgan & Finnegan, L.L.P.

20060278968 - Laminated semiconductor package: A laminated semiconductor package includes: a first package having: an insulating layer; a first semiconductor chip embedded in the insulating layer; a wiring connected to the first semiconductor chip; a first connecting section which is formed on a first face side of the insulating layer and connected to the wiring;... Agent: Rankin, Hill, Porter & Clark LLP

20060278967 - Method for manufacturing an electronic module and an electronic module: This publication discloses an electronic module and a method for manufacturing an electronic module, in which a component (6) is glued (5) to the surface of a conductive layer, from which conductive layer conductive patterns (14) are later formed. After gluing the component (6), an insulating-material layer (1), which surrounds... Agent: Birch Stewart Kolasch & Birch

20060278969 - Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods: Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One such device can include a first support member, a second support member, and a microelectronic die positioned between the first support member and the second support member such that the second support... Agent: Perkins Coie LLP Patent-sea

20060278970 - Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device: A semiconductor device includes: a base substrate; a semiconductor chip formed on the base substrate in such a manner that an adhesive layer is interposed between the semiconductor chip and the base substrate; a resin layer covering at least a portion of the semiconductor chip; and an external connection terminal... Agent: Nixon & Vanderhye, PC

20060278971 - Method and apparatus for applying external coating to grid array packages for increased reliability and performance: A method and apparatus are disclosed for selective removal of a conformal coating from the solder balls of grid array packages such that the benefits of the coating are realized. An ancillary benefit of the invention is improved process-ability of the grid array package by improving the mechanical containment of... Agent: Honeywell International Inc.

20060278972 - Panel and semiconductor component having a composite board with semiconductor chips and plastic package molding compound and method for the production thereof: A panel and a semiconductor component including a composite board with semiconductor chips and plastic package molding compound and a method for the production thereof is disclosed. In one embodiment, the panel includes a composite board with semiconductor chips arranged in rows and columns in a corresponding plastic package molding... Agent: Dicke, Billig & Czaja, P.l.l.c.

20060278973 - Semiconductor device with improved design freedom of external terminal: A semiconductor device comprises: a base; a semiconductor chip provided on the base which includes a first main surface 20a on which a plurality of electrode pads is provided, a surface protecting film provided on the first main surface, a second main surface which opposes the first main surface, and... Agent: Rabin & Berdo, PC

20060278974 - Method for forming wafer-level heat spreader structure and package structure thereof: A method for forming wafer-level heat sink in a chip of the packaging structure is provided. Before the sawing process, a plurality of via holes are formed and covered with a heat conductive layer such as a metal layer for forming a heat spreader structure in the backside of a... Agent: Birch Stewart Kolasch & Birch

20060278975 - Ball grid array package with thermally-enhanced heat spreader: A ball grid array (BGA) package having a thermally enhanced dummy chip is provided. In one embodiment, the package comprises a substrate. A chip is attached to the substrate. A heat spreader is disposed over the chip, and a dummy chip is disposed between the heat spreader and the chip.... Agent: Birch, Stewart, Kolasch & Birch, LLP

20060278976 - Semiconductor device, method and manufacturing same, identification label and information carrier: The semiconductor device (100) comprises an integrated circuit (20) and a first and a second contact face (31,33). These are connected with vertical interconnects (32,34) to the integrated circuit (20). This integrated circuit (20) is present in a semiconductor layer of a substrate. This substrate is absent in a non-active... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20060278977 - Carrier to hold semiconductor device using opposed rollers: A carrier for a semiconductor device includes a body having an opening formed therein to receive the semiconductor device and a pair of rollers to hold the semiconductor device between the rollers in the opening.... Agent: Buckley, Maschoff, Talwalkar LLC

20060278978 - Semiconductor component with a media channel and method for manufacturing same: A semiconductor component includes a media channel and at least the following components: a semiconductor chip on a wiring substrate, electric connecting elements disposed between the semiconductor chip and the wiring substrate, and a plastic housing mass that embeds these components. The media channel is impressed into the plastic housing... Agent: Edell, Shapiro & Finnan, LLC

20060278979 - Die stacking recessed pad wafer design: A die-to-die alignment structure is disclosed that facilitates the alignment and/or positional retention of die during a 3-D stacked assembly process.... Agent: Blakely Sokoloff Taylor & Zafman

20060278981 - Electronic chip contact structure: A chip contact functionally having an IC pad, a barrier layer over the IC pad, and a malleable material over the barrier layer. An alternative chip contact functionally having an IC pad, a barrier layer over the IC pad, and a rigid material over the barrier layer.... Agent: Morgan & Finnegan, L.L.P.

20060278980 - Patterned contact: A chip having at least one electrical contact having a first end proximate to the chip and a second end removed from the chip, the second end including a pattern configured to facilitate penetration of the at least one contact into a malleable contact on another chip, the pattern comprising... Agent: Morgan & Finnegan, L.L.P.

20060278982 - Metal bump with an insulation for the side walls and method of fabricating a chip with such a metal bump: A chip with at least two metal bumps (6a, 6b) which has insulation layers for opposing side walls which are deposited in a plasma activated gas. Predetermined portions of the insulation layer (7) are removed by reactive ion etching. The metal bumps can be formed of a noble metal and... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20060278984 - Semiconductor device: The present invention provides a semiconductor device exhibiting an improved reliability. A semiconductor device comprises a semiconductor chip having an electrode on a surface thereof and a mounting substrate, and the electrode (aluminum electrode) of the semiconductor chip is coupled to the mounting substrate through a bump (solder bump 104).... Agent: Young & Thompson

20060278983 - Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus: A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically... Agent: Harness, Dickey & Pierce, P.L.C

20060278985 - Multilevel semiconductor devices and methods of manufacturing the same: A multilevel semiconductor device and method of making the same includes a first active semiconductor structure, a first insulating layer on the first active semiconductor structure, a second active semiconductor structure on the first insulating layer and over the first active semiconductor structure, a second insulating layer on the second... Agent: Lee & Morse, P.C.

20060278986 - Chip capacitive coupling: A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom... Agent: Morgan & Finnegan, L.L.P.

20060278987 - Integrated circuit having a programmable conductive path on each conductive layer and related method of modifying a version number assigned to the integrated circuit: An integrated circuit has an identification circuit for providing a read-only logic value for identifying the integrated circuit. The identification circuit includes a plurality of programmable stages for determining the read-only logic value. Each of the programmable stages includes a logic cell and a conductive path. The logic cell has... Agent: North America Intellectual Property Corporation

20060278988 - Profiled contact: A semiconductor chip, having IC pads, the semiconductor chip having a device, electrically connected to at least one electrical contact through the IC pad, the electrical contact having a height and a cross sectional profile, through the height, configured to facilitate penetration of at least a portion of the electrical... Agent: Morgan & Finnegan, L.L.P.

20060278989 - Triaxial through-chip connection: A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing an inner and outer perimeter side wall of the annulus trench with a metal, etching a via trench within the periphery of the annulus... Agent: Morgan & Finnegan, L.L.P.

20060278990 - Etch stop in a damascene interconnect structure: An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials act as insulating layers through which trenches and vias are subsequently formed by employing a timed etching. Since the low dielectric constant materials are selected so that... Agent: Dickstein Shapiro LLP

20060278996 - Active packaging: A method involves stacking a first chip, comprising high-speed circuitry formed using a first fabrication process, together with a wafer comprising multiple iterations of low-speed circuitry formed using a second fabrication process, hybridizing the first chip to the wafer so as to form electrical connections between the first chip and... Agent: Morgan & Finnegan, L.L.P.

20060278993 - Chip connector: A method of electrically joining a first contact on a first wafer with a second contact on a second wafer, the first contact, a rigid material, and the second contact, a material that is malleable relative to the rigid material, such that when brought together the rigid material will penetrate... Agent: Morgan & Finnegan, L.L.P.

20060278995 - Chip spanning connection: A system has a first chip having first semiconductor devices and first electrical connections, a second chip having second semiconductor devices and second electrical connections, and a third chip having third semiconductor devices and third electrical connections, the third chip being stacked on top of and physically spanning at least... Agent: Morgan & Finnegan, L.L.P.

20060278994 - Inverse chip connector: A system for connecting a first chip to a second chip having a post on the first chip having a first metallic material, a recessed wall within the second chip and defining a well within the second chip, a conductive diffusion layer material on a surface of the recessed wall... Agent: Morgan & Finnegan, L.L.P.

20060278992 - Post & penetration interconnection: A method of physically and electrically joining two chips to each other involves aligning an electrically conductive contact of a first chip with a corresponding electrically conductive contact on a second chip, the electrically conductive contact of the first chip being a rigid material and the electrically conductive contact of... Agent: Morgan & Finnegan, L.L.P.

20060278991 - Stack circuit member and method: A stack circuit member may include a first circuit member and a second circuit member. The first and the second circuit members may be electrically and mechanically connected together using a thermocompression bonding method. A photosensitive polymer layer may be interposed between the first circuit member and the second circuit... Agent: Harness, Dickey & Pierce, P.L.C

20060278998 - Integrated electronic chip and interconnect device and process for making the same: A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting... Agent: International Business Machines Corporation Dept. 18g

20060278997 - Soldered assemblies and methods of making the same: A microelectronic element is mounted to a substrate using solder elements disposed at least partially within vias of the substrate. The vias have tapering walls. During reflow of the solder, the microelectronic element may move toward the substrate. Such movement may be impelled, for example, by interfacial tension between the... Agent: Tessera Lerner David Et Al.

20060278999 - Substrate for pre-soldering material and fabrication method thereof: A substrate for a pre-soldering material and a fabrication method of the substrate are proposed. The substrate having at least one surface formed with a plurality of conductive pads is provided. An insulating layer is formed over the surface of the substrate in such a way that a top surface... Agent: Fulbright And Jaworski LLP

20060279000 - Pre-solder structure on semiconductor package substrate and method for fabricating the same: A pre-solder structure on a semiconductor package substrate and a method for fabricating the same are proposed. A plurality of conductive pads are formed on the substrate, and a protective layer having a plurality of openings for exposing the conductive pads is formed over the substrate. A conductive seed layer... Agent: Clark & Brody

20060279001 - Semiconductor device and manufacturing method therefor: The semiconductor device according to an aspect of the invention includes: an internal circuit area having an internal circuit; an I/O circuit area positioned outside the internal circuit area; and an electrode pad placed across an outer edge of the I/O circuit area. In the electrode pad, an area outside... Agent: Sughrue Mion, PLLC

20060279002 - Protected chip stack: A protected chip stack having a first chip and a second chip on the first chip. A functional layer in at least the first chip or the second chip. On the first chip and on the second chip there is in each case a connecting element, the connecting element on... Agent: Darby & Darby P.C.

20060279004 - Mold, pattern forming method, and pattern forming apparatus: A pattern forming method for forming a pattern includes: preparing a mold 104 provided with a first surface including a pattern area 1000, a second surface located opposite from the first surface, and an alignment mark 2070 provided at a position at which the alignment mark 2070 is away from... Agent: Fitzpatrick Cella Harper & Scinto

20060279003 - Semiconductor device having an alignment mark formed by the same material with a metal post: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060279005 - Techniques for forming passive devices during semiconductor back-end processing: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive... Agent: Lsi Logic Corporation

20060273297 - Phase change memory cell having ring contacts: A memory cell includes a first ring contact, a second ring contact, and phase-change material contacting the first ring contact and the second ring contact.... Agent: Dicke, Billig & Czaja, P.l.l.c.

20060273298 - Rewriteable memory cell comprising a transistor and resistance-switching material in series: A nonvolatile memory cell is provided, the cell comprising a transistor in series with resistance-switching material, which can be switched between at least two stable resistance states, for example a high-resistance state and a low-resistance state. In preferred embodiments the transistor is a TFT, having a channel region not formed... Agent: Matrix Semiconductor, Inc.

20060273300 - Iii-v group gan-based compound semiconductor device: A III-V Group GaN-based compound semiconductor device with an improved structure having low current comsumption, high optical output, and a long lifetime is provided. The III-V Group GaN-based compound semiconductor device includes an active layer and a first clad layer and a second clad layer, wherein at least one of... Agent: Buchanan, Ingersoll & Rooney PC

20060273299 - Method for making a semiconductor device including a dopant blocking superlattice: A method for making a semiconductor device may include forming at least one metal oxide field-effect transistor (MOSFET) by forming a body, forming a dopant blocking superlattice adjacent the body, and forming a channel layer adjacent the dopant blocking superlattice and opposite the body. The dopant blocking superlattice may include... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20060273301 - High speed electron tunneling devices: A detector includes a voltage source for providing a bias voltage and first and second non-insulating layers, which are spaced apart such that the bias voltage can be applied therebetween and form an antenna for receiving electromagnetic radiation and directing it to a specific location within the detector. The detector... Agent: Pritzkau Patent Group

20060273302 - Barrier layer for an organic electronic device: A novel barrier layer which protects electronic devices from adverse environmental effects such as exposure to light, oxygen and/or moisture is described. The barrier layer comprises a polymer, an antioxidant, and an inorganic particulate material.... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20060273306 - Compounds and methods for nanoscale patterning and structure formation: Organosulfur compounds suitable as protected thiol-containing reactive organic layer precursors, for example 3,5-dimethoxy-α,α-dimethylbenzyloxycarbonyl-3-mercaptopropyltriethoxysilane, are useful in methods of nanometer scale (nanoscale) patterning and fabrication of nanoscale structures on patterned surfaces. The compounds and methods enable the patternwise placement of nanoparticles, with nanometer resolution to form, for example, electrically conductive nanostructures.... Agent: Beyer Weaver & Thomas, LLP

20060273307 - Electronic device including a first workpiece, a second workpiece, and a conductive member substantially directly bonded to the first and second workpieces: An electronic device can include a first workpiece, a second workpiece, and a conductive member. The first workpiece can include an electronic component that includes an electrode and an organic layer. The first workpiece can also include a substrate structure lying adjacent to the electronic component. The second workpiece can... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20060273308 - Electronic device including conductive members between a first workpiece and second workpiece: An electronic device can include a first workpiece including at least 4,000 electronic components that each include a corresponding electrode and a second workpiece including at least one conductor. The electronic device can also include at least 4,000 conductive members that are substantially directly bonded to the corresponding electrodes and... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20060273312 - Electronic element: The object is to fabricate a novel organic semiconductor element which can effectively utilize the main-chain conduction of a conjugated high molecular compound having semiconductor-like properties. Provided is an electronic element which contains, as components, a pair of electrodes which is formed on a substrate, a mesoporous film in which... Agent: Fitzpatrick Cella Harper & Scinto

20060273310 - Light-emitting component with an arrangement of electrodes: The invention concerns a light-emitting component with an arrangement of electrodes for applying an electrical voltage to multiple organic areas, which form a light-emitting area, are distributed across a component surface and which each emit light when the electrical voltage is applied, in which the multiple organic areas are arranged... Agent: Sutherland Asbill & Brennan LLP

20060273304 - Oled device having curved viewing surface: A method of manufacturing an OLED device with a curved light-emitting surface comprising: a) forming a flexible substrate and providing the flexible substrate in a flat configuration; b) forming one or more OLEDs having a first electrode, one or more layers of organic material, at least one of which is... Agent: Paul A. Leipold Patent Legal Staff

20060273311 - Organic semiconductor material, organic semiconductor thin film and organic semiconductor device: where each of R1 to R10 may be independently the same substituents or different substituents but all of R1, R4, R5, R6, R9 and R10 may never be hydrogen atoms at the same time, and where each of R1 to R10 is at least one kind of substituent selected from... Agent: Bell, Boyd & Lloyd, LLC

20060273303 - Organic thin film transistors with multilayer electrodes: An thin-film transistor (TFT) with multilayer source and drain electrodes is provided. Each source and drain electrode comprises a first layer of a first conductive material and a second layer of a conductive polymer which has a work function identical or similar to that of the semiconductor layer. The second... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20060273305 - Printing conductive patterns using lep: A method of printing an electrode component is disclosed. The method can include steps of electrostatically printing a polymer onto a substrate, where at least a portion of the printing occurs while the polymer is in a first conductive state, and altering the polymer to a second conductive state that... Agent: Hewlett Packard Company

20060273309 - Workpiece including electronic components and conductive members: A workpiece can include conductive members that include a material that melts at a temperature no higher than 240° C. In one embodiment, conductive members that are attached to electronic components that each include an electrode and an organic layer that emits radiation, responds to radiation, or a combination thereof,... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20060273313 - Ic packaging technique: An IC packaging technique uses a recyclable and environmental benign plastic material (such as a thermal plastic material) to perform packaging to an IC chip, in order to solve shortcomings of an inability of being recycled of a thermosetting material, an inability of reprocessing and repairing the IC, and a... Agent: Troxell Law Office PLLC Suite 1404

20060273316 - Array substrate having enhanced aperture ratio, method of manufacturing the same and display apparatus having the same: An array substrate includes a transparent substrate, a thin film transistor (TFT), a pixel electrode and a storage capacitor. The TFT includes a gate electrode formed on the transparent substrate, a first gate insulation layer formed on the gate electrode, a second gate insulation layer formed on the first gate... Agent: Macpherson Kwok Chen & Heid LLP

20060273314 - Display device with improved pixel light emission and manufacturing method of the same: A display device with pixels capable of uniform light emission and a method of making the display device are presented. A display device has a plurality of TFTs, a protection layer formed on the TFTs, and a plurality of pixel electrodes formed on the protection layer and electrically connected to... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20060273315 - Liquid crystal display device and fabrication method thereof: An LCD device, and a fabrication method thereof, having a high aperture ratio and a high optical transmittance that enhances a fabrication yield and reduces the number of masks required in a fabrication process are disclosed. The LCD device includes a first substrate and a second substrate; a gate line... Agent: Mckenna Long & Aldridge LLP

20060273317 - Semiconductor device and method of fabricating the same: An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a... Agent: Fish & Richardson P.C.

20060273318 - Displaying device with photocurrent-reducing structure and method of manufacturing the same: A displaying device includes a substrate, a gate electrode formed on the substrate, a gate insulating layer, a gate a-Si region covering the gate electrode, a source metal region, a drain metal region, a data-line (DL) metal region, a passivation layer and a conductive layer. The gate a-Si region is... Agent: Bacon & Thomas, PLLC

20060273319 - Integrated circuit device and manufacturing method thereof: It is an object of the present invention to improve a factor which influences productivity such as variation caused by a characteristic defect of a circuit by thinning or production yield when an integrated circuit device in which a substrate is thinned is manufactured. A stopper layer is formed over... Agent: Eric Robinson

20060273320 - Method of manufacturing semiconductor device: According to an aspect of the invention, there is provided a method of manufacturing a semiconductor device including simultaneously supplying a source gas of an oxide insulating film and H2 to a semiconductor substrate when the oxide insulating film is formed on the semiconductor substrate by a CVD method.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060273321 - Cmos image sensor and method for fabricating the same: A method for fabricating a CMOS image sensor includes: forming a gate electrode on a pixel region of the semiconductor substrate and, at the same time, forming a polysilicon pattern on a middle resistor region; forming a first lightly doped n-type diffusion region on the photodiode region; forming a second... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060273322 - Silicon layer with high resistance and fabricating method thereof: A silicon layer with high resistance is provided. The silicon layer with high resistance is positioned on a substrate. Also, the silicon layer with high resistance includes a plurality of silicon material layers, and an interface layer between every two of the silicon material layers, wherein, the silicon material layers... Agent: Jianq Chyun Intellectual Property Office

20060273323 - Semiconductor device having sic substrate and method for manufacturing the same: A semiconductor device includes: a SiC substrate; a silicide layer disposed on the SiC substrate; and a carbide layer disposed on the silicide layer. The silicide layer includes a first metal, and the carbide layer includes a second metal. The first metal is Ni or Ni alloy, and the second... Agent: Posz Law Group, PLC

20060273327 - Light emitting diode: A light emitting diode is provided. The light emitting diode includes: a n-type semiconductor layer; a p-type semiconductor layer facing the n-type semiconductor layer; an active layer formed between the n-type semiconductor layer and the p-type semiconductor layer; and a nanopattern metal layer that is formed in a predetermined pattern... Agent: Buchanan, Ingersoll & Rooney PC

20060273328 - Light emitting nanowires for macroelectronics: Systems and methods to fabricate macroelectronic light emitting devices using densely oriented nanowires are disclosed. In one embodiment, core nanowires are synthesized and an insulating shell is fabricated around the nanowires. The nanowire core-shell structures are then deposited on a substrate to create a densely oriented nanowire thin film. Once... Agent: Nanosys Inc.

20060273324 - Light-emitting diode and process for producing the same: The back surface of a semiconductor crystal substrate 102 which has a thickness of about 150 μm and is made of undoped GaN bulk crystal consists of a polished plane 102a which is flattened through dry-etching and a grinded plane 102b which is formed in a taper shape and is... Agent: Mcginn Intellectual Property Law Group, PLLC

20060273329 - Semiconductor device: The semiconductor device according to the present invention includes a semiconductor layer containing plural band gap change thin films in which a band gap is continuously monotonously changed in a laminating direction. Therefore, the present invention provides a semiconductor device having high reliability and low electric resistance.... Agent: Hogan & Hartson L.L.P.

20060273330 - Semiconductor device using partial soi substrate and manufacturing method thereof: A semiconductor device manufacturing method includes selectively removing portions of a buried oxide layer and first semiconductor layer in an SOI substrate having the first semiconductor layer formed above a semiconductor substrate with the buried oxide layer disposed therebetween and exposing part of the semiconductor substrate, removing an exposed region... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060273326 - Semiconductor light emitting device, its manufacturing method, semiconductor device and its manufacturing method: A semiconductor light emitting device made of nitride III-V compound semiconductors includes an active layer made of a first nitride III-V compound semiconductor containing In and Ga, such as InGaN; an intermediate layer made of a second nitride III-V compound semiconductor containing In and Ga and different from the first... Agent: Sonnenschein Nath & Rosenthal LLP

20060273325 - Ultraviolet detector: An UV detector, comprising: a sapphire substrate; a high temperature AlN buffer layer grown on the sapphire substrate; an intermediate temperature GaN buffer layer grown on the high temperature AlN buffer layer; a GaN epitaxial layer deposited on the intermediate temperature GaN buffer layer; a Schottky junction formed on top... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20060273331 - Two-terminal led device with tunable color: A two-terminal light-emitting diode (“LED”) device has a first terminal and a second terminal, and a first color LED and a second color LED. An intensity control device is coupled to the first color LED and a control circuit controls the intensity control device so as to produce a selected... Agent: Avago Technologies, Ltd.

20060273332 - Nitride semiconductor light emitting device: The present invention relates to a nitride semiconductor light emitting device. The nitride semiconductor light emitting device includes a substrate; an n-type nitride semiconductor layer that is formed on the substrate; an active layer that is formed on the n-type nitride semiconductor layer; a p-type nitride semiconductor layer that is... Agent: Mcdermott Will & Emery LLP

20060273333 - Light emitting diode and method of fabricating thereof: A light emitting diode (LED) is made of a substrate and an epitaxial structure. A surface of the epitaxial structure has many mass transferred patterns. The mass transferred patterns are formed by a mass transfer method to deform an original rough surface of the epitaxial structure. The surface topography of... Agent: Jianq Chyun Intellectual Property Office

20060273334 - Light emitting device, method for making the same, and nitride semiconductor substrate: A light-emitting device according to the present invention includes: a GaN substrate 1; a n-type AlxGa1-xN layer 3 on a first main surface side of the GaN substrate 1; a p-type AlxGa1-xN layer 5 positioned further away from the GaN substrate 1 compared to the n-type AlxGa1-xN layer 3; a... Agent: Darby & Darby P.C.

20060273336 - Light emitting diode and manufacturing method thereof: A technique of ensuring compatibility between the method of improving the light extraction efficiency by roughening the surface of a LED structure, and the method of avoiding the adverse effect of a low-cost electrode pad ((1) forming a current distribution layer by a transparent conductive film made of metal or... Agent: Antonelli, Terry, Stout & Kraus, LLP

20060273335 - Semiconductor light emitting device: A semiconductor light emitting device includes a semiconductor light emitting portion having a first contact layer of a first conductivity, a second contact layer of a second conductivity and an active layer sandwiched between the first and second contact layers. The device further includes a transparent electrode which substantially entirely... Agent: Rabin & Berdo, PC

20060273337 - Side-emitting led package and method of manufacturing the same: The invention relates to a side-emitting LED package and a manufacturing method thereof. The side-emitting LED package includes a substrate with an electrode formed thereon, and a light source disposed on the substrate and electrically connected to the electrode. The side-emitting LED package also includes a molded part having an... Agent: Mcdermott Will & Emery LLP

20060273339 - contacting scheme for large and small area semiconductor light emitting flip chip devices: A light emitting device includes a layer of first conductivity type, a layer of second conductivity type, and a light emitting layer disposed between the layer of first conductivity type and the layer of second conductivity type. A via is formed in the layer of second conductivity type, down to... Agent: Patent Law Group LLP

20060273338 - High power led package and fabrication method thereof: An LED diode package includes a heat connecting part for mounting a light emitting part on an upper surface thereof, frames electrically connected to the light emitting part while holding the heat connecting part and a molded part fixing the heat connecting part and the frames together. The light emitting... Agent: Mcdermott Will & Emery LLP

20060273340 - Led package and method using the same: An LED package including an LED chip (LA, A, B), a sealed transparent envelope (D) containing the LED chip inside, transparent liquid (E) filled in the envelope, electrodes (C) is disclosed. The LED chip comprises a plurality of conductive nodes. The transparent liquid is provided with a high resistance, the... Agent: Knobbe Martens Olson & Bear LLP

20060273343 - A1xinyga1-x-yn mixture crystal substrate, method of growing same and method of producing same: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1−x−yN (0≦x≦1, 0≦y≦1, 0<x+y≦1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and... Agent: Mcdermott Will & Emery LLP

20060273342 - Gan-series of light emitting diode with high light extraction efficiency: A GaN-series of light emitting diode with high light extraction efficiency includes a substrate, a n-type semiconductor, a light emitting layer and a p-type semiconductor layer. More particular, the p-type semiconductor layer includes a p-type cladding layer, a p-type transition layer and a p-type ohmic contact layer, wherein the p-type... Agent: Rosenberg, Klein & Lee

20060273341 - Vertically-structured gan-based light emitting diode and method of manufacturing the same: The present invention relates to a method of manufacturing a vertically-structured GaN-based light emitting diode. The method of manufacturing a vertically-structured GaN-based light emitting diode includes forming a GaN layer on a substrate; patterning the compound layer in a predetermined shape; forming an n-type GaN layer on the patterned compound... Agent: Mcdermott Will & Emery LLP

20060273344 - Semiconductor devices having transistors with different gate structures and methods of fabricating the same: A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which... Agent: Myers Bigel Sibley & Sajovec

20060273345 - Method of manufacturing liquid crystal display, liquid crystal display, and aging system: Provided are a method of manufacturing a liquid crystal display including an amorphous silicon thin film transistor, a liquid crystal display, and an aging system adapted to the method of manufacturing the liquid crystal display. The method includes providing a liquid crystal display including a liquid crystal panel having a... Agent: F. Chau & Associates, LLC

20060273346 - Edge structure with voltage breakdown in the linear region: One aspect of the invention relates to an edge structure for a semiconductor component having two electrodes arranged opposite one another on opposite sides of a semiconductor body having a doped zone of the first charge carrier type. The semiconductor body has at least one doped zone of the second... Agent: Dicke, Billig & Czaja, P.l.l.c.

20060273347 - Field-effect transistor and method for fabricating the same: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are... Agent: Mcdermott Will & Emery LLP

20060273348 - Transistor and display and method of driving the same: A field-effect transistor including an electrically conductive substrate; a first insulating film coating the electrically conductive substrate; a gate electrode disposed on the electrically conductive substrate with the first insulating film interposed therebetween; a source electrode; a drain electrode opposing the source electrode with the channel therebetween; a second insulating... Agent: Fitzpatrick Cella Harper & Scinto

20060273349 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes: an epitaxial layer of a first conductivity type, formed in a semiconductor substrate of the first conductivity type; a blue photodiode region of a second conductivity type, formed in the epitaxial layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060273350 - Semiconductor integrated circuit: Data circuit power supply wiring for supplying power supply voltage to a data circuit and clock circuit power supply wiring for supplying power supply voltage to a clock circuit are connected by a via and power supply wiring formed in a wiring layer that is different from (for example, that... Agent: Mcdermott Will & Emery LLP

20060273351 - Vertical type semiconductor device and method for manufacturing the same: A vertical type semiconductor device includes: a silicon substrate having a first surface and a second surface; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate. Current is capable of flowing between the first... Agent: Posz Law Group, PLC

20060273352 - Cmos imager pixel designs: A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a... Agent: Dickstein Shapiro LLP

20060273353 - Cmos active pixel sensor shared amplifier pixel with reduced sense node capacitance: An image sensor includes a unit cell having a plurality of pixels; the unit cell comprising an amplifier input transistor that is shared by the plurality of pixels; a plurality of floating diffusions that are joined by a floating diffusion interconnect layer and are connected to the amplifier input transistor;... Agent: Pamela R. Crocker Patent Legal Staff

20060273355 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and manufacturing method thereof are disclosed. The present CMOS image sensor comprises: a first conductivity type semiconductor substrate having an isolation region and an active region, the active region including a blue (or cyan) photo diode region and a transistor region; an isolation layer in the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20060273354 - Pixel of image sensor and method for fabricating the same: A pixel of an image sensor includes a polysilicon layer, and an active region which needs to be electrically coupled with the polysilicon layer, wherein the polysilicon layer extends over a portion of the active region, such that the polysilicon layer and the active region are partially overlapped, and the... Agent: Morgan Lewis & Bockius LLP

20060273356 - Single-electron transistor, field-effect transistor, sensor, method for producing sensor, and sensing method: A single-electron transistor comprising at least a substrate, a source electrode and a drain electrode formed on top of the substrate opposing to each other, and a channel arranged between the source electrode is disclosed wherein the channel is composed of ultra fine fibers. By having such a constitution, a... Agent: Crowell & Moring LLP Intellectual Property Group

20060273357 - Semiconductor device and manufacturing method thereof: The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20060273358 - Semiconductor device: In a laser pickup photodetector of an optical disk playback device, the sensitivity to blue light is improved. On a main surface of a semiconductor substrate, a high resistivity epitaxial layer that becomes an i layer of a PIN photodiode (PIN-PD) is formed. On a surface of the epitaxial layer,... Agent: Oliff & Berridge, PLC

20060273360 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and manufacturing method thereof are disclosed. The present CMOS image sensor comprises: a semiconductor substrate including an active region having a photo diode region and a transistor region; a gate on the active region, comprising a gate insulating layer and a gate electrode thereon; a first... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20060273359 - Solid state imaging device, camera, and method for fabricating solid state imaging device: In a solid state imaging device which includes a photodiode in the upper part of a silicon substrate and a MOSFET active region separated from the photodiode by a device isolation region, the width of the device isolation region is smaller in its lower part than in its upper part.... Agent: Mcdermott Will & Emery LLP

20060273363 - Method for fabricating cmos image sensor: A method for fabricating a CMOS image sensor is provided. The method includes: forming a gate electrode with a gate insulating layer interposed on a transistor region of a semiconductor substrate having an active region defined by a photo diode and a transistor region; forming a first impurity region of... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060273362 - Photoelectric conversion layer, photoelectric conversion device and imaging device, and method for applying electric field thereto: wherein R11 to R14 each independently represents a hydrogen atom or a substituent; X11 and X12 each independently represents a substituted or unsubstituted carbon atom, a substituted or unsubstituted nitrogen atom, an oxygen atom, or a sulfur atom; and Y11 to Y14 each independently represents a substituted or unsubstituted carbon... Agent: Sughrue Mion, PLLC

20060273361 - Solid state imaging device and solid state imaging element: Each of three light receiving sections has a P-type well having a P+-type layer and an N-type layer formed therein. The P+-type layer is diffused from substrate surface to depth d1. A PN junction forming portion of the N-type layer is diffused from depth d1 to depth d2 which is... Agent: Crowell & Moring LLP Intellectual Property Group

20060273364 - Identical/symmetrical metal shielding: An image sensor includes a unit cell having a plurality of pixels; the unit cell having a plurality of photodetectors having two or more subsets in which each subset has a physical shape which is different than the other subset; and light-shielding layers that create an aperture associated with each... Agent: Pamela R. Crocker Patent Legal Staff

20060273366 - Methods of manufacturing ferroelectric capacitors and semiconductor devices: In a method of manufacturing a ferroelectric capacitor, a lower electrode layer is formed on a substrate. The lower electrode layer includes at least one lower electrode film. A ferroelectric layer is formed on the lower electrode layer, and then an upper electrode layer is formed on the ferroelectric layer.... Agent: Myers Bigel Sibley & Sajovec

20060273365 - Semiconductor device and its manufacture method, and measurement fixture for the semiconductor device: A semiconductor device comprises a substrate, a ferroelectric capacitor which includes a ferroelectric film on the substrate, and a stress application layer which applies tensile or compressive stress to the ferroelectric film of the ferroelectric capacitor by applying stress to the substrate.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060273367 - Semiconductor device and manufacturing method therefor: A ferroelectric capacitor having a bottom electrode (9a), a ferroelectric film (10a) and a top electrode (11a) is formed above a semiconductor substrate (1). The ferroelectric film (10a) is constituted of CSPZT with 0.1-5 mol % of La and 0.1-5 mol % of Nb.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060273368 - Semiconductor device having capacitor with upper electrode of conductive oxide and its manufacture method: A ferroelectric capacitor is formed above a substrate and made of a lamination of a lower electrode, a capacitor ferroelectric film and an upper electrode stacked in this order. The upper electrode is made of conductive oxide and has such an oxygen concentration distribution as an oxygen concentration in a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060273369 - Capacitor for semiconductor device and method of forming the same: A capacitor for a semiconductor device includes a lower electrode, a dielectric layer formed on a lower electrode, and an upper electrode formed on the dielectric layer. The lower electrode includes a first layer having a cylindrical shape and a mesh second layer formed on inner sidewalls and the bottom... Agent: Volentine Francos, & Whitt PLLC

20060273370 - Nrom flash memory with vertical transistors and surrounding gates: An NROM flash memory array is comprised of a plurality of surrounding gate NROM flash memory cells. The transistors are pillar-type devices with either silicon pillars or silicon bodies on oxide pillars. The array comprises a substrate with a plurality of the pillars organized in rows and columns. An upper... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20060273371 - Evaluation semiconductor device: An evaluation semiconductor device is used for evaluating a yield of a DRAM portion of an integrated circuit device. The evaluation semiconductor device includes an evaluation gate interconnect provided in a layer corresponding to a gate interconnect layer of the DRAM portion; and an evaluation source contact corresponding to a... Agent: Mcdermott Will & Emery LLP

20060273372 - Lateral lubistor structure and method: An ESD LUBISTOR structure based on FINFET technology employs a vertical fin (a thin vertical member containing the source, drain and body of the device) in alternatives with and without a gate. The gate may be connected to the external electrode being protected to make a self-activating device or may... Agent: International Business Machines Corporation Dept. 18g

20060273373 - Semiconductor device: A semiconductor device, includes: a non-volatile memory element, wherein the non-volatile memory element includes: a first region; a second region formed adjacent to the first region; and a third region formed adjacent to the second region; and the non-volatile memory element includes: a semiconductor layer; an isolation insulating layer provided... Agent: Harness, Dickey & Pierce, P.L.C

20060273374 - Semiconductor device and manufacturing method thereof: A technology capable of improving a charge retention characteristic of a nonvolatile memory is provided. In a memory cell in which an interlayer insulating film formed of an ONO film obtained by laminating a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film is formed... Agent: Miles & Stockbridge PC

20060273375 - Transistor with nanocrystalline silicon gate structure: A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of nanocrystalline silicon particles. Each nanocrystalline silicon particle has... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060273376 - Method of manufacturing devices comprising conductive nano-dots, and devices comprising same: A method is disclosed that may include forming a first layer of insulating material above a semiconducting substrate, forming an aluminum oxide layer above the first layer of insulating material, forming a plurality of spaced-apart dots of material on the aluminum oxide layer, forming a second layer of insulating material... Agent: Williams, Morgan & Amerson

20060273377 - Nonvolatile memory device and method of manufacturing the same: Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the... Agent: Buchanan, Ingersoll & Rooney PC

20060273378 - Bidirectional split gate nand flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20060273383 - High density hybrid mosfet device: A hybrid semiconductor power device that includes a plurality of closed power transistor cells each surrounded by a first and second trenched gates constituting substantially a closed cell and a plurality of stripe cells comprising two substantially parallel trenched gates constituting substantially an elongated stripe cell wherein the closed cells... Agent: Bo-in Lin

20060273382 - High density trench mosfet with low gate resistance and reduced source contact space: A trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes gate contact trenches and source contact trenches opened through oxide insulation layers into the gate polysilicon and the body-source silicon regions. The gate contact trenches and the source contact trenches are filled with gate contact plug and source... Agent: Bo-in Lin

20060273387 - Insulated gate-type semiconductor device and manufacturing method thereof: This invention has a purpose to provide an insulated gate-type semiconductor device and its manufacturing method in which a decrease in gate insulation dielectric strength voltage and a reduction in manufacturing costs are both achieved. First, (a) a CZ bulk substrate is prepared. Next, (b) P− diffused layer and N+... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060273379 - Mosfet using gate work function engineering for switching applications: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold voltage and shifts the C-Vds characteristics. The reduced Cgd... Agent: Bo-in Lin

20060273388 - Semiconductor device and method for manufacturing the same: A semiconductor device is provide with a semiconductor substrate, a groove formed in the semiconductor substrate, a gate insulting film formed on the inner wall of the groove, a gate electrode formed in the groove, and a source/drain region and an LDD region arranged in the direction that is substantially... Agent: Mcdermott Will & Emery LLP

20060273380 - Source contact and metal scheme for high density trench mosfet: A trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a source-body contact trench opened with sidewalls substantially... Agent: Bo-in Lin

20060273384 - Structure for avalanche improvement of ultra high density trench mosfet: A trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a source-body contact trench opened with sidewalls substantially... Agent: Bo-in Lin

20060273381 - Transistor and method for fabricating the same: Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a... Agent: Ladas & Parry LLP

20060273386 - Trench-gate field effect transistors and methods of forming the same: A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate... Agent: Townsend And Townsend And Crew, LLP

20060273385 - Trenched mosfet device with contact trenches filled with tungsten plugs: A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells in an active cell area and extending as trench-gate fingers to intersect with a trenched gate under the gate metal runner at a termination area. At least one... Agent: Bo-in Lin

20060273390 - Gate contact and runners for high density trench mosfet: A trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a buried trench-poly gate runner electrically contacting to... Agent: Bo-in Lin

20060273389 - Vertical fet with nanowire channels and a silicided bottom contact: A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.... Agent: Scully Scott Murphy & Presser, PC

20060273391 - Cmos devices for low power integrated circuits: A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device and thermally oxidizing the MOS device to form a gate dielectric substantially thicker at a gate dielectric edge than that at a gate dielectric center. Embodiments further comprise performing a source/drain ion... Agent: Slater & Matsil, L.L.P.

20060273392 - Semiconductor device and method of manufacturing the same: Disclosed is a method for manufacturing a semiconductor device comprising implanting ions of an impurity element into a semiconductor region, implanting, into the semiconductor region, ions of a predetermined element which is a group IV element or an element having the same conductivity type as the impurity element and larger... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060273394 - Semiconductor device and method of manufacturing same: A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060273393 - Structure and method of making field effect transistor having multiple conduction states: A field effect transistor (“FET”) is provided has a semiconductor region including a channel region, a source region and a drain region and a gate conductor overlying the channel region. Such FET has a first threshold voltage having a first magnitude and a second threshold voltage having a second magnitude... Agent: International Business Machines Corporation Dept. 18g

20060273396 - Semiconductor device and manufacturing method thereof: The present invention aims to provide a semiconductor device that can improve an element isolation breakdown voltage, which includes a semiconductor resistor using an InGaP layer as a semiconductor layer exposed on a surface. The present invention includes: an FET having a channel layer and a schottky layer which is... Agent: Greenblum & Bernstein, P.L.C

20060273395 - Semiconductor device comprising an integrated circuit: A semiconductor device with a plurality of passive components (7,7a,8,8a) comprising a bottom substrate (1), a buried oxide layer (2) on a portion of the top surface of the bottom substrate (1), an dielectric intermediate insulating layer (3) on a portion of the buried oxide layer (2), a dielectric top... Agent: Harness, Dickey & Pierce, P.L.C

20060273399 - Esd protection structure and method utilizing substrate triggering for a high-voltage tolerant pad: In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the... Agent: Rabin & Berdo, PC

20060273397 - Protect diodes for hybrid-orientation substrate structures: A semiconductor structure and method for forming the same. The structure includes a hybrid orientation block having first and second silicon regions having different lattice orientations. The first silicon region is directly on the block, while the second silicon region is physically isolated from the block by a dielectric region.... Agent: Schmeiser, Olsen & Watts

20060273398 - Semiconductor device and manufacturing method of semiconductor device: To present a semiconductor device mounting ESD protective device appropriately applicable to transistors mutually different in dielectric strength, and its manufacturing method. The semiconductor device comprises a first ESD protective circuit 1A including a first transistor 3 and a first ballast resistance 4, and a second ESD protective circuit 1B... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060273400 - High voltage analog switch ics and ultrasound imaging systems using same: A MOSFET including a JFET resistor resultant between a drain region and a channel region caused by depletion of current carriers. Since most of the drain-source voltage is imposed on the JFET resistor, the voltage imposed on a channel region is reduced to prevent concentration of an electric field therein.... Agent: Crowell & Moring LLP Intellectual Property Group

20060273401 - Manufacturing method of cmos type semiconductor device, and cmos type semiconductor device: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors,... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060273402 - Semiconductor device and method of manufacture: A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200, 300, 400) that includes a semiconductor substrate (110, 210, 310, 410) having a first conductivity type and buried semiconductor region (115, 215, 315, 415) having a second conductivity type located above the semiconductor substrate.... Agent: Ingrassia, Fisher & Lorenz, P.C.

20060273403 - Semiconductor device having a diode for a rectifier circuit: A semiconductor device has a rectifier circuit and integrated circuit on a semiconductor substrate of a first conduction type, and has a first well region in the substrate, a second well region in first well region, and a diode region formed in second well region and constituting a diode with... Agent: Arent Fox PLLC

20060273405 - Semiconductor device and method for patterning: In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20060273404 - Tft charge storage memory cell having high-mobility corrugated channel: A rewriteable nonvolatile memory cell having two bits per cell is described. The memory cell preferably operates by storing charge in a dielectric charge storage layer or in electrically isolated conductive nanocrystals by a channel hot electron injection method. In preferred embodiments the channel region has a corrugated shape, providing... Agent: Matrix Semiconductor, Inc.

20060273406 - Semiconductor integrated circuit device having deposited layer for gate insulation: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second... Agent: Antonelli, Terry, Stout & Kraus, LLP

20060273407 - Semiconductor device and wiring method for semiconductor device: A semiconductor device includes: a first circuit in which a diffusion area A1, a first gate G1, a diffusion area A2, a second gate G2 and a diffusion area A3 constitute two transistors; and a second circuit in which a diffusion area B1, the first gate G1, a diffusion area... Agent: Staas & Halsey LLP

20060273408 - Semiconductor device: A semiconductor device includes a substrate, and a gate electrode on the substrate via a gate insulating film. The gate insulating film includes a base interface layer on the substrate, metal silicate film on the base interface layer and containing a metal, oxygen, and silicon, and a nitrogen-containing metal silicate... Agent: Leydig Voit & Mayer, Ltd

20060273409 - High performance cmos with metal-gate and schottky source/drain: A semiconductor device having a metal/metal silicide gate and a Schottky source/drain and a method of forming the same are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a metal or metal silicide gate electrode having a work function of less than about 4.3 eV or... Agent: Slater & Matsil, L.L.P.

20060273410 - Thermally stable fully silicided hf silicide metal gate electrode: A method is described for forming an n-MOSFET with a fully silicided Hf suicide gate electrode that has a work function essentially the same as n+ polysilicon. An in-situ phosphorous doped polysilicon film is deposited on a gate dielectric layer on a CMOS substrate and annealed at 900° C. After... Agent: Saile Ackerman LLC

20060273411 - In-situ nitridation of high-k dielectrics: A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack may include... Agent: Freescale Semiconductor, Inc. Law Department

20060273412 - Method of manufacturing semiconductor device: A gate insulating film and a gate electrode are formed on a silicon substrate. The gate insulating film contains at least hafnium, oxygen, fluorine, and nitrogen. The fluorine concentration is high in the vicinity of an interface with the silicon substrate and progressively decreases with decreasing distance from the gate... Agent: Leydig Voit & Mayer, Ltd

20060273413 - Semiconductor device and method of manufacturing the same: There are provided: a semiconductor substrate including first and second device regions isolated by device isolation regions; a first gate insulating film of a high-k material formed in the first device region; a first gate electrode formed on the first gate insulating film; first source and drain regions formed at... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060273414 - Refractory metal-based electrodes for work function setting in semiconductor devices: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The... Agent: Texas Instruments Incorporated

20060273415 - Transistor for memory device and method for manufacturing the same: Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a groove formed in the active region.... Agent: Ladas & Parry LLP

20060273416 - Capacitive resonators: A micro-electro-mechanical system (MEMS) capacitive resonator and methods for manufacturing the same are invented and disclosed. In one embodiment, an apparatus comprises a micro-electro-mechanical system (MEMS) capacitive resonator, the resonator comprising support means, a semiconductor resonating member coupled to the support means, and electrodes comprised of a different material than... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20060273417 - Authentication system having a flexible imaging pressure sensor: A sensor for a textured surface (e.g., a fingerprint) is provided. The sensor includes a flexible substrate and a flexible membrane supported above the substrate by one or more spacers. The sensor also includes multiple pressure sensor elements responsive to a separation between parts of the membrane and corresponding parts... Agent: Lumen Intellectual Property Services, Inc.

20060273418 - 3-d inductor and transformer devices in mram embedded integrated circuits: An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and at least one inductance element formed on the same substrate using the same fabrication process technology. The inductance element, which may be an inductor or a transformer, is formed at the same metal layer (or layers) as... Agent: Ingrassia, Fisher & Lorenz, P.C.

20060273419 - Magnetic field sensing device: The invention is directed to a magnetic field sensing device (FSD) capable of visually indicating exposure to a magnetic field with a strength that exceeds a threshold value. The magnetic FSD comprises a magnetic layer magnetized to define a pattern. The threshold value is approximately equal to a coercivity of... Agent: Eric Levinson Imation Legal Affairs

20060273420 - Semiconductor sensor component including a sensor chip and methods for the manufacturing thereof: A semiconductor sensor component including a sensor chip and methods for the manufacturing thereof is disclosed. In one embodiment, the semiconductor sensor component includes a package which itself includes a transparent plastic material. The sensor chip has an active top side and a back side, wherein a sensor area is... Agent: Dicke, Billig & Czaja, P.l.l.c.

20060273421 - Semiconductor photodetector and method for manufacturing the same: In order to improve reliability by preventing an edge breakdown in a semiconductor photodetector having a mesa structure such as a mesa APD, the semiconductor photodetector comprises a mesa structure formed on a first semiconductor layer of the first conduction type formed on a semiconductor substrate, the mesa structure including... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20060273422 - Switching element for characteristic inspection, and characteristic inspection method: A thin film transistor for characteristic inspection has a source, a gate and a drain connected to electrode terminals, namely to a source terminal, a gate terminal and a drain terminal, respectively. The electrode terminals are connected to a potential uniformalizing terminal via potential uniformalizing wiring in order to uniform... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060273423 - Chip resistor and method for manufacturing same: A chip resistor (A1) includes a resistor element (1) including an electrode forming surface (10b), two electrodes (3) provided at the electrode-forming surface (10b), and an insulating layer (2A) provided at the electrode-forming surface (10b). The electrode-forming surface (10b) includes an inter-electrode region positioned between the two electrodes (3) and... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20060273424 - Semiconductor device: The semiconductor device has a fuse and a fuse opening created above the fuse. The fuse is divided into a plurality of lines at a crossing portion where the fuse crosses with an edge of the fuse opening. The plurality of divided lines of the fuse 101 are in parallel... Agent: Sughrue Mion, PLLC

20060273425 - High density capacitor structure: A capacitor structure for an integrated circuit having at least first, second and third layers, with each layer having first and second conductors, includes multiple sidewall capacitors formed between sidewalls of the first conductor and the second conductor in each layer. Several inter-layer capacitors are formed between the first and... Agent: Freescale Semiconductor, Inc. Law Department

20060273426 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device with a capacitor comprises a lower electrode, a dielectric and an upper electrode on the dielectric layer. The dielectric layer comprising one or more polycrystalline tantalum oxide layers and one or more separation layers, wherein the polycrystalline tantalum oxide layers and the separation layers are alternately stacked,... Agent: Mcdermott Will & Emery LLP

20060273427 - Vertical metal-insulator-metal (mim) capacitors: An MIM capacitor structure having a metal structure formed thereover is provided. A dielectric layer is disposed over the metal structure and a top layer is disposed over the dielectric layer. A capacitance trench is formed through the top layer and into the dielectric layer. Respective bottom electrodes are formed... Agent: Mark J. Marcelli Duane Morris LLP

20060273428 - Semiconductor device and method of manufacture: A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100) including a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a plurality of first semiconductor regions... Agent: Ingrassia, Fisher & Lorenz, P.C.

20060273429 - Switching element, programmable logic integrated circuit and memory element: A switching element with a switching voltage set higher than conventional, which includes an ion conduction layer including tantalum oxide, a first electrode provided in contact with the ion conduction layer, and a second electrode provided in contact with the ion conduction layer and capable of supplying the ion conduction... Agent: Mcginn Intellectual Property Law Group, PLLC

20060273430 - Method of wafer-level packaging using low-aspect ratio through-wafer holes: A wafer-level packaged IC is made by attaching a cap wafer to the front of an IC base wafer before cutting the IC base wafer, i.e. before singulating the plurality of dies on the IC base wafer. The cap wafer is mechanically attached and electrically connected to the IC base... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20060273431 - Interconnects having sealing structures to enable selective metal capping layers: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the... Agent: Blakely Sokoloff Taylor & Zafman

20060273432 - Lead frame with attached components: According to an embodiment of the invention, a package comprises a lead frame, a first passive component, a first wire bond connection, and a mold compound. The lead frame has a first pair of resilient arms. The first passive component is disposed between the first pair of resilient arms. The... Agent: Texas Instruments Incorporated

20060273433 - Semiconductor device: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that... Agent: Hamre, Schumann, Mueller & Larson P.C.

20060273434 - Semiconductor device and the manufacturing method for the same: A semiconductor device has a semiconductor substrate having first and second surface, a first resin film formed on the first surface of the semiconductor substrate and a second resin film formed on the second surface of the semiconductor substrate. A projection electrode or an interconnection is formed on the first... Agent: Merchant & Gould PC

20060273435 - Chip package: A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.... Agent: North America Intellectual Property Corporation

20060273436 - Arrangement, apparatus, and associated method, for providing stored data in secured form for purposes of identification and informational storage: Card member apparatus, and an associated method, for storing and permitting selectable use of informational data associated with a subject. Identifying indicia stored at a first storage element, and the informational data is stored at a second storage element, together disposed upon a substrate, or otherwise supported to permit carriage... Agent: Scheef & Stone, L.L.P.

20060273437 - Optoelectronic semiconductor assembly with an optically transparent cover, and a method for producing optoelectronic semiconductor assembly with an optically transparent cover: An optoelectronic semiconductor assembly includes at least the following components: a semiconductor chip with an optical sensor region on its active topside, a wiring substrate on which the semiconductor chip is arranged, electrical connecting elements extending between the semiconductor chip and the wiring substrate, and an optically transparent cover an... Agent: Edell, Shapiro & Finnan, LLC

20060273438 - Stacked chip security: The present invention is directed to an integrated circuit module device. The device includes a first semiconductor chip having a first circuit layer and at least one first interconnection element disposed on a first chip surface. The at least one first interconnection element is electrically coupled to the first circuit... Agent: Bond Schoeneck & King, PLLC

20060273440 - Stacking apparatus and method for stacking integrated circuit elements: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position... Agent: Morgan Lewis & Bockius LLP

20060273439 - Three-dimensional multichip stack electronic package structure: The present invention relates to a three-dimensional multichip stack electronic package structure and method for making the same, including a main substrate having at least a pin-hole set and at least a flexible substrate having at least a pin terminal. At least an electronic device including an active component and... Agent: Bacon & Thomas, PLLC

20060273441 - Assembly structure and method for chip scale package: Disclosed is an assembly structure of chip scale package, which can effectively avoid various yield and quality problems resulted from the poor control of epoxy during the process of chip scale package. A buffer zone whose planar size is smaller than that of the chip is disposed on the substrate,... Agent: Lin & Associates Intellectual Property

20060273443 - Package for an electronic component and method for its production: A package for an electronic component includes a synthetic package compound. This synthetic package compound includes an upper outer contact on its upper side and a lower outer contact on its lower side, where the upper outer contact is electrically connected to the lower outer contact via a conduction path.... Agent: Edell, Shapiro & Finnan, LLC

20060273442 - Semiconductor device for accommodating large chips, fabrication method thereof, and carrier used in the semiconductor device: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to... Agent: The Law Offices Of Mikio Ishimaru

20060273444 - Packaging chip and packaging method thereof: A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit... Agent: Sughrue Mion, PLLC

20060273445 - Three-dimensional structure composed of silicon fine wires, method for producing the same, and device including the same: A three-dimensional structure composed of highly-reliable silicon ultrafine wires, a method for producing the three-dimensional structure, and a device including the same are provided. The three-dimensional structure composed of silicon fine wires includes wires (2) on the order of nanometers to micrometers formed by wet etching utilizing the crystallinity of... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060273446 - Circuit board device and method of interconnecting wiring boards: A circuit board device comprises a first wiring board (79) having plural first electrode terminals (73, 75, 77) for connection row-arranged on a surface layer, a second wiring board (87) having plural second electrode terminals (81, 83, 85) for connection row-arranged on a surface layer, and an anisotropic conductive member... Agent: Dickstein Shapiro Morin & Oshinsky LLP

20060273447 - Electronic package structures and methods: Electronics packages are provided with structure that provides a significantly-reduced package footprint and also facilitates substantial reduction of package fabrication time and cost. The footprint reduction is realized with a frame that defines an aperture wall which surrounds first sets of components on the first side of a printed circuit... Agent: Koppel, Patrick & Heybl

20060273448 - Semiconductor structures having electrophoretically insulated vias: Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed... Agent: Trask Britt

20060273449 - Hermetically sealed package for optical, electronic, opto-electronic and other devices: Techniques are disclosed for hermetically sealing one or more devices within a package. According to one aspect, a lid is attached to a substrate on which one or more devices are provided such that the devices are encapsulated within an area defined by the substrate and the lid. A substance,... Agent: Fish & Richardson P.C.

20060273453 - Heat sink and display panel including heat sink: A heat sink that absorbs heat generated from at least one semiconductor device and dissipates the heat absorbed includes: a first surface adapted to match and contact at least one semiconductor device; a second surface having a fin structure adapted to dissipate heat from the heat sink into the air,... Agent: Robert E. Bushnell

20060273451 - Semiconductor ic and its manufacturing method, and module with embedded semiconductor ic and its manufacturing method: A semiconductor IC includes a semiconductor IC main body having a predetermined circuit formed on a main surface, a metal layer selectively provided on substantially the whole back surface of the semiconductor IC main body excluding the periphery. According to the present invention, the metal layer provided on the semiconductor... Agent: Young Law Firm, P.C. Alan W. Young

20060273452 - Semiconductor package and fabrication method thereof: A semiconductor package and a fabrication method thereof are provided. During a molding process, a substrate mounted with a chip is placed in a mold having a molding cavity, wherein the molding cavity is sized larger than the predetermined size of the semiconductor package, and a portion of the mold... Agent: Edwards & Angell, LLP

20060273450 - Solid-diffusion, die-to-heat spreader bonding methods, articles achieved thereby, and apparatus used therefor: A die and heat spreader are bonded with an intermetallic thermal interface material (TIM). The bonding process is carried out in a tool that can control conditions such that fluxing is not required. An article including an intermetallic TIM between a die and a heat spreader is provided in a... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060273454 - Locking mechanism for die assembly: Some embodiments of the present invention include locking mechanisms for die assembly.... Agent: Blakely Sokoloff Taylor & Zafman

20060273455 - Electronic packaging including die with through silicon via: An apparatus, method, and system for electronic device packaging having stacked dice are disclosed herein. A first die has a through silicon via formed therethrough. A second die is landed on the through silicon via of the first die. A mount having a lead is coupled to the through silicon... Agent: Schwabe, Williamson & Wyatt

20060273457 - Data line layout in semiconductor memory device and method of forming the same: In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n<m, and M=m+1, and... Agent: Volentine Francos, & Whitt PLLC

20060273456 - Multiple spacer steps for pitch multiplication: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one... Agent: Knobbe Martens Olson & Bear LLP

20060273459 - Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry: Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a... Agent: Wells St. John P.s.

20060273458 - Substrate structure of semiconductor package: A substrate structure of a semiconductor package is proposed. The structure includes a substrate with at least one opening; a grounding ring formed on the substrate and around the opening; and a plurality of plating through holes (PTH) formed in the substrate and corresponding to the grounding ring. The grounding... Agent: Mr. Joseph A. Sawyer, Jr. Sawyer Law Group LLP

20060273460 - Method and structure for determining thermal cycle reliability: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure... Agent: Keusey, Tutunjian & Bitetto, P.C.

20060273461 - Electronic device and method of manufacturing the same: An electronic device includes a substrate 23 on which foot patterns 24A, 24B and a solder resist 25 are provided such that the foot patterns 24A, 24B are exposed from opening portions 27A, 27B in the solder resist 25, packaging parts 20A, 20B mounted on the substrate 23 by solder... Agent: Rankin, Hill, Porter & Clark LLP

20060273463 - Semiconductor device and mounting structure thereof: A semiconductor device includes a semiconductor substrate having an integrated circuit, a first insulating film formed on the semiconductor substrate, at least one power source internal wiring line formed on the first insulating film, and a second insulating film formed on the first insulating film and on the internal wiring... Agent: Frishauf, Holtz, Goodman & Chick, PC

20060273462 - System and method based on field-effect transistors for addressing nanometer-scale devices: A system and method for selecting nanometer-scaled devices. The method includes a plurality of semiconductor wires. Two adjacent semiconductor wires of the plurality of semiconductor wires are associated with a separation smaller than or equal to 100 nm. Additionally, the system includes a plurality of address lines. Each of the... Agent: Townsend And Townsend And Crew, LLP

20060273465 - Semiconductor device and manufacturing method therefor: In a manufacturing method for a semiconductor storage device, an interlayer insulating film, a first hard mask made of an insulative material for coating the interlayer insulating film and a second hard mask are formed on a substrate. The second hard mask is opened, and with use of the second... Agent: Harness, Dickey & Pierce, P.L.C

20060273464 - Semiconductor device and method of manufacturing a semiconductor device: A semiconductor device comprises: an insulation layer located on or above a semiconductor element; a conductive pad formed on the insulation film; and a first opening pattern formed on the conductive pad.... Agent: Harness, Dickey & Pierce, P.L.C

20060273466 - Adhesion of tungsten nitride films to a silicon surface: A process is described that forms a low resistivity connection between a tungsten layer and a silicon surface with high adherence of the tungsten to the silicon. The silicon surface is plasma-cleaned to remove native oxide. A very thin layer (one or more monolayers) of Si-NH2 is formed on the... Agent: Patent Law Group LLP

20060273467 - Flip chip package and method of conducting heat therefrom: A flip chip package and method for conducting heat from one or more flip chips within the package. The package includes a substrate having a first surface to which the flip chips are attached with solder connections, a second surface with solder balls electrically connected to the solder connections on... Agent: Delphi Technologies, Inc.

20060273468 - Configuration for multi-layer ball grid array: Disclosed herein is a method and circuit arrangement for a multi-layer ball grid array configuration. In one embodiment, there is presented a board comprising a first surface, a second surface, and a plurality of vias. The second surface is connected to the first surface. The plurality of vias are positioned... Agent: Mcandrews Held & Malloy, Ltd

20060273469 - Carrier sheet with adhesive film and method for producing semiconductor devices using the carrier sheet with adhesive film: A carrier sheet with an adhesive film includes a heat-resistant base film with an upper side and an underside, and a thermoactive adhesive layer arranged on the underside of the base film and oriented toward the carrier sheet. The upper side of the base film includes an adhesive layer with... Agent: Edell, Shapiro & Finnan, LLC