Active solid-state devices (e.g., transistors, solid-state diodes) inventions 10/06

20060237705 - Method and related apparatus for calibrating signal driving parameters between chips: A calibrating method for adjusting related parameters when a first chip and a second chip switch signals is disclosed. The calibrating method includes: utilizing the first chip to output a test signal through using a first driving force in order to represent a test value; utilizing the second chip to...

20060237706 - Non-volatile semiconductor memory and method for controlling a non-volatile semiconductor memory: A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain-region having the first conductivity type and in contact...

20060237707 - Memory array for increased bit density and method of forming the same: A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the...

20060237708 - Semiconductor carbon nanotubes fabricated by hydrogen functionalization and method for fabricating the same: Semiconductor carbon nanotubes functionalized by hydrogen and a method for fabricating the same, wherein the functional hydrogenated semiconductor carbon nanotubes have chemical bonds between carbon and hydrogen atoms. The semiconductor carbon nanotube fabricating method includes heating carbon nanotubes in a vacuum, dissociating hydrogen molecules in hydrogen gas into hydrogen atoms,...

20060237709 - Gan-based compound semiconductor device: A gallium nitride (GaN)-based compound semiconductor device having a structure improving a surface characteristic of a thin film growing on a substrate is provided. The GaN-based compound semiconductor device includes an AlxInyGa1-x-yN substrate (0≦x≦1, 0≦y≦1, and 0≦x+y≦1) whose surface inclines toward a predetermined direction at an off-angle of greater than...

20060237710 - Semiconductor optical device: Since the semiconductor devices including a stacked structure of group-III-V alloy semiconductor layers different in the kind of group-V constituent atom form the so-called band line-up of type II, band discontinuity in the heterostructure has impeded smooth transport of carriers and deteriorated device characteristics. According to the present invention, an...

20060237711 - Field-effect transistor: A nitride-based group III-V compound semiconductor device includes a buffer layer, a first nitride semiconductor layer and a second nitride semiconductor layer successively stacked on a substrate, the first and the second nitride layers having their respective lattice constants a1 and a2 in the relation a1>a2, an ohmic source electrode...

20060237713 - Color organic electroluminescent display and method for fabricating the same: A method of fabricating a color organic electroluminescent display involves forming cathode electrodes on a substrate, and forming a first organic semiconductor layer having an electron-injection transporting property on the cathode electrodes. Solutions containing organic light-emitting material that can dissolve portions of the first organic semiconductor layer are patterned on...

20060237716 - Material and cell structure for storage applications: The present invention relates to compositions for storage applications, relates to a memory cell which comprises the abovementioned composition and two electrodes and furthermore relates to a process for the production of microelectronic components and the use of the composition according to the invention in the production of these microelectronic...

20060237712 - N,n'-di(arylalkyl)-substituted naphthalene-based tetracarboxylic diimide compounds as n-type semiconductor materials for thin film transistors: A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide naphthalene-based compound having, attached to each of the imide nitrogen atoms, a substituted or unsubstituted arylalkyl moiety. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said...

20060237714 - Organic metal compounds in which compounds for host and compounds for dopant are connected, organic electroluminesence display devices using the compounds and method for preparation of the devices: The present embodiments relate to organic metal compounds in which compounds for host and compounds for dopant are connected, organic electroluminescence display devices using the compounds and a method for preparation of the devices. More precisely, the present embodiments relate to organic metal compounds in which compounds for host and...

20060237715 - Organic metal compounds in which compounds for host and compounds for dopant are connected, organic electroluminesence display devices using the compounds and method for preparation of the devices: The present embodiments relate to organic metal compounds in which compounds for host and compounds for dopant are connected, organic electroluminescence display devices using the compounds and a method for preparation of the devices. More precisely, the present embodiments relate to organic metal compounds in which the compounds for host...

20060237717 - Organic polymers, electronic devices, and methods: wherein: each R1 is independently H, an aryl group, Cl, Br, I, or an organic group that includes a crosslinkable group; each R2 is independently H, an aryl group or R4; each R3 is independently H or methyl; each R5 is independently an alkyl group, a halogen, or R4; each...

20060237718 - Valatime copper (ii) complexes and reducing agents for deposition of copper films by atomic layer deposition: The present invention relates to novel 1,3-diimine copper complexes and the use of 1,3-diimine copper complexes for the deposition of copper on substrates or in or on porous solids in an Atomic Layer Deposition process....

20060237719 - Electronic components: A method of manufacturing an electronic component comprising at least one n- or p-doped portion, comprising the steps of: co-depositing inorganic semi-conducting nanoparticles and dopant on a substrate, the nanoparticles being a group four element such as silicon or germanium; fusing the nanoparticles by heating to form a continuous layer;...

20060237720 - Active matrix substrate and liquid crystal display device, production methods thereof and electronic device: A layer stack including an operating semiconductor layer and a low resistance semiconductor layer is patterned by using a first mask pattern so as to have an insular shape and then a circumferential sidewall of the layer stack whose top surface is covered by the first mask pattern is oxidized...

20060237723 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a stopper film formed so as to cover an element formation region and an element isolation region, an interlayer insulating film formed on the stopper film, a contact hole formed in the element formation region so as to extend through the interlayer insulating film and the...

20060237722 - Solid state imaging device: A solid state imaging device includes: a plurality of photoelectric conversion elements which are arranged in a two-dimensional matrix on a semiconductor chip; vertical transfer registers including a vertical transfer channel and vertical transfer electrodes, respectively, for transferring signal charge read out of the photoelectric conversion elements in the vertical...

20060237721 - Solid-state image pickup device, driving method for solid-state image pickup device, and image pickup apparatus: A solid-state image pickup device includes a pixel array area in which pixels each including a photoelectric conversion element are two-dimensionally arranged; first control means for performing control such that signals of pixels in a desired region of the pixel array area are sequentially read row by row; and second...

20060237725 - Semiconductor devices having thin film transistors and methods of fabricating the same: Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes...

20060237724 - Thin film transistor and method of forming the same: A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a soruce/drain is provided. The gate is disposed over a substrate, wherein the gate comprises at least one layer of aluminum-yttrium alloy nitride. The gate insulating layer is formed over the substrate to cover the...

20060237727 - Display device and semiconductor device: A display device of high definition, multiple colors and low power consumption includes a display panel having a pixel section in which pixels are arrayed in the form of a matrix at the cross points of a plurality of data lines and a plurality of scanning lines, a scanning circuit...

20060237726 - Semiconductor device: Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1...

20060237728 - Silicon carbide power devices with self-aligned source and well regions: Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices are provided by successively etching a mask layer to provide windows for formation of a source region of a first conductivity type, a buried silicon carbide region of a second conductivity type opposite to the first conductivity type...

20060237729 - Light emission from semiconductor integrated circuits: Structures and methods to inject electrons into an insulator from a semiconductor layer that are then collected in a thin layer of a direct semiconductor material which in turn emits light by bandgap recombination....

20060237730 - Peltier cooler with integrated electronic device(s): A Peltier effect cooling device is formed in combination with an electronic device to form a unique thermal and electrical relationship. An electronic device to be cooled is placed in a serial electrical relationship between at least two thermoelectric couples while simultaneously being in thermal contact with a cold side...

20060237731 - Semiconductor element, organic transistor, light-emitting device, and electronic device: It is an object of the present invention to provide an organic transistor having a low drive voltage. It is also another object of the present invention to provide an organic transistor, in which light emission can be obtained, which can be manufactured simply and easily. According to an organic...

20060237732 - Light-emitting device, method for making the same, and nitride semiconductor substrate: A light-emitting device is presented which includes a GaN substrate 1; an n-type nitride semiconductor substrate layer (n-type AlxGa1-xN layer 3) disposed on a first main surface side of the GaN substrate 1; a p-type nitride semiconductor substrate layer (p-type AlxGa1-xN layer 5) disposed further away from the GaN substrate...

20060237733 - Light emitting device: A light emitting device includes an active layer, having a multiple quantum well structure, sandwiched between an n-type semiconductor layer and a p-type semiconductor layer. The active layer includes first and second well layers made of a nitride compound semiconductor containing In, where the second well layer emits light having...

20060237735 - High-efficiency light extraction structures and methods for solid-state lighting: A soft solder flowing into the recesses of a semiconductor thin film LED provides: (a) increased bonding strength and better mechanical durability, (b) improved heat dissipation, (c) enhanced light extraction when the LED film is bonded to a new carrier. Annealing localized islands of absorbing metal creates an ohmic contact....

20060237738 - Led lamps: A high power LED lamp has a GaN chip placed over an AlGaInP chip. A reflector is placed between the two chips. Each of the chips has trenches diverting light for output. The chip pair can be arranged to produce white light having a spectral distribution in the red to...

20060237737 - Light emitting diode and backlight module having light emitting diode: The present invention relates to a light emitting diode comprising a blue die and a fluorescent material layer. The blue die is used for generating blue light when being activated. The fluorescent material layer is used for generating yellow light when being activated. The light emitting diode further comprises a...

20060237739 - Light-emitting device and illuminator: A light-emitting device, having high light extraction efficiency, capable of obtaining diffused light is obtained. This light-emitting device comprises a light-emitting diode, a portion, formed on a plane substantially parallel to a light-emitting surface of the light-emitting diode, having a dielectric constant periodically modulated with respect to the in-plane direction...

20060237736 - Light-emitting diode and method for improving emitting directivity of light-emitting chip: A light-emitting diode (20) includes: a first electrode (202) with a supporting portion (201); a second electrode (203) opposite to the first electrode; a light-emitting chip (204) on the supporting portion, the light-emitting chip is electrically connected to the first electrode and the second electrode; and a cover (205) has...

20060237734 - Thin-layer light-emitting diode chip and method for the production thereof: A thin-layer LED chip (5) is claimed, comprising an epitaxial layer sequence (6) that is disposed on a carrier element (2) and contains an electromagnetic-radiation-generating active region (8), and a reflective layer (3) that is disposed on a principal surface of the epitaxial layer sequence (6) facing toward the carrier...

20060237741 - Light-emitting diode and method for production thereof: An LED (10) includes a compound semiconductor layer (13) that contains a light-emitting part and an alkali glass substrate (150) that contains at least 1 mass % of one element selected from sodium, calcium, barium and potassium and is transparent to light-emitting wavelength of the part. The substrate is fixed...

20060237740 - Mbe growth of an algan layer or algan multilayer structure: A method of growing an AlGaN semiconductor layer structure by Molecular Beam Epitaxy comprises supplying ammonia, gallium and aluminium to a growth chamber thereby to grow a first (Al,Ga)N layer by MBE over a substrate disposed in the growth chamber. The first (Al,Ga)N layer has a non-zero aluminium mole fraction....

20060237742 - Power control center with solid state device for controlling power transmission: An automotive power control center that includes a housing, a first conductor coupled to the housing, a second conductor, a control circuit, which is coupled to the housing, and a semiconductor. The second conductor is coupled to the housing and insulated from the first conductor. The solid-state device includes a...

20060237743 - Heterojunction bipolar transistor and method for fabricating the same: On a high-concentration n-type first sub-collector layer, a high-concentration n-type second sub-collector layer made of a material having a small bandgap, an i-type or low-concentration n-type collector layer, a high-concentration p-type base layer, an n-type emitter layer made of a material having a large bandgap, a high-concentration n-type emitter cap...

20060237744 - Formation of highly dislocation free compound semiconductor on a lattice mismatched substrate: A highly dislocation free compound semiconductor, e.g. AlxInyGa1-x-yN (0≦x, y≦1), is formed on a lattice mismatched substrate, e.g. Si, by first depositing a polycrystalline buffer layer on the substrate. A defective layer is then created at or near the interface of the substrate and the polycrystalline buffer layer, e.g. through...

20060237745 - Super lattice modification of overlying transistor: The invention provides a device having a substrate, a buffer region positioned upon the substrate, wherein the buffer region has an upper buffer region and a lower buffer region, a heterojunction region positioned upon the buffer region, and a superlattice positioned between the lower buffer region and the upper buffer...

20060237746 - Gesoi transistor with low junction current and low junction capacitance and method for making the same: A semiconductor device (101) is provided herein which comprises a substrate (103) comprising germanium. The substrate has source (107) and drain (109) regions defined therein. A barrier layer (111) comprising a first material that has a higher bandgap (Eg) than germanium is disposed at the boundary of at least one...

20060237747 - Heterojunction bipolar transistor and amplifier including the same: An N-type collector layer is partially formed on an N+-type collector contact layer. The N-type collector layer includes a second N-type collector layer that is partially formed on the N+-type collector contact layer and relatively hard to deplete, and a first N-type collector layer that is formed on the whole...

20060237748 - Semiconductor device and method of manufacturing the same: A semiconductor device according to an embodiment of the invention includes: at least a first power supply system and a second power supply system; an input/output circuit capable of controlling an current for an input or output signal; a control signal input circuit that is provided to the first power...

20060237749 - Nanoscopic wire-based devices and arrays: Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used...

20060237750 - Field effect transistor structures: An embodiment of the present invention provides a structure comprising a field effect transistor (FET) comprising: at least one source rail with at least one source finger; at least one drain rail with at least one drain finger; and at least one serpentine gate having a plurality of gate fingers,...

20060237751 - Image pickup device, image pickup unit and image pickup apparatus: An image pickup device wherein the range in the amount of incident light (dynamic range) for obtaining an appropriate image can be expanded, and shutter and aperture functions are provided. A light shielding element for light shielding a photoelectric conversion section and an actuator for driving the light shielding element...

20060237752 - Schottky barrier mosfet device and circuit: A Schottky barrier integrated circuit is disclosed, the circuit having at least one PMOS device or at least one NMOS device, at least one of the PMOS device or NMOS device having metal source-drain contacts forming Schottky barrier or Schottky-like contacts to the semiconductor substrate. The device provides a lower...

20060237753 - Semiconductor device and method for manufacturing the same: A field effect transistor according to the present invention includes a channel layer formed above a semi-insulating substrate, a Schottky layer formed above the channel layer, a gate electrode formed on the Schottky layer, Ohmic contact layers that are located above the Schottky layer with the gate electrode interposed therebetween...

20060237754 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate having a plurality of trenches, a plurality of element isolation regions formed by burying an element isolation insulating film in the trenches, a gate insulating film formed in an element formation region defined between the element isolation regions on the semiconductor substrate, and...

20060237755 - Method for automated testing of the modulation transfer function in image sensors: A method for automatically measuring the modulation transfer function of an imager is disclosed. A opaque mask is placed over selected columns and rows of the imager during fabrication. In the course of an automated process, photons are uniformly shone over the image sensor. The amount of the input signal...

20060237756 - Phase change memory devices and their methods of fabrication: In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region...

20060237758 - Semiconductor device: A semiconductor device includes a plurality of first active areas arranged in a first area including a first sub area, a second sub area located adjacent to the first sub area in a first direction, and a third sub area adjacent to the first sub area in a second direction...

20060237757 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films...

20060237759 - Semiconductor device manufacturing method and semiconductor device: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in...

20060237760 - Thin-film capacitative element and electronic circuit and electronic equipment including the same: A thin film capacitive element according to the present invention includes between a first electrode layer and a second electrode layer a dielectric layer formed of a dielectric material containing a bismuth layer structured compound having a composition represented by the stoichiometric compositional formula: (Bi2O2)2+ (Am−1BmO3m+1)2−, where a symbol m...

20060237763 - Electronic systems: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over...

20060237761 - Non-volatile memory, fabrication method thereof and operation method thereof: A method of fabrication a non-volatile memory is provided. A stacked structure is formed on a substrate, the stacked structure including a gate dielectric layer and a control gate. Then, a first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed on the top and...

20060237762 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device has a stabilizing member that encloses an upper portion of a storage electrode to improve structural stability. A dielectric layer and a plate electrode are successively formed on the storage electrode including a stabilizing member. Since the stabilizing member includes a protruding portion to support the storage...

20060237764 - Lanthanide doped tiox dielectric films: A dielectric film containing lanthanide doped TiOx and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. The lanthanide doped TiOx dielectric layer is arranged as a layered structure of one or more monolayers of the...

20060237765 - Eeprom and method of manufacturing the same: An EEPROM includes a substrate, a first semiconductor layer and a second semiconductor layer formed on the substrate. The first semiconductor layer is isolated from the second semiconductor layer by a trench. A first source and a first drain are located at two opposing sides of the first semiconductor layer....

20060237768 - Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers: Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel...

20060237766 - Semiconductor device using solid phase epitaxy and method for fabricating the same: A semiconductor device includes an epitaxial layer using a solid phase epitaxy (SPE) process; a first metal layer on the epitaxial layer; a nitride-based barrier metal layer on the first metal layer; a second metal layer on the barrier metal layer; and a metal silicide layer formed between the epitaxial...

20060237767 - Semiconductor device with double barrier film: A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has...

20060237774 - Backgated finfet having different oxide thicknesses: A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced...

20060237771 - Flash memory device having a graded composition, high dielectric constant gate insulator: A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator is comprised of amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to...

20060237769 - Floating gate isolation and method of making the same: The present invention relates to a method for forming a set of floating gates which are isolated from each other by means of slits, as well as semiconductor devices using the floating gate. The present invention provides a method for manufacturing an array of semiconductor devices on a substrate (10),...

20060237776 - High density stepped, non-planar flash memory: A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column. The second plurality of memory cells are coupled to the first plurality of memory cells through a...

20060237775 - Memory device with high dielectric constant gate dielectrics and metal floating gates: A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are greater than silicon dioxide. Each memory cell has a...

20060237772 - Method of manufacturing flash memory device: An embodiment of the present invention relates to a method of manufacturing a flash memory device. The method includes sequentially forming a tunnel oxide film, an oxide film, and a first conductive layer on a semiconductor substrate, infiltrating a first etchant between grains of the first conductive layer to form...

20060237773 - Semiconductor device with reconfigurable logic: A semiconductor device includes multiple transistors (70, 75, 80, 85), each of the transistors (70, 75, 80, 85) including a gate electrode (18) formed above a semiconductor substrate (30), source/drain regions (10, 12, 14, 16) formed on both sides of the gate electrode (18), and a charge storage layer (38)...

20060237770 - Semiconductor flash device: A flash memory device includes a floating gate made of a multi-layered structure. The floating gate includes a hetero-pn junction which serves as a quantum well to store charge in the floating gate, thus increasing the efficiency of the device, allowing the device to be operable using lower voltages and...

20060237777 - Multi-bit non-volatile memory device having a dual-gate and method of manufacturing the same, and method of multi-bit cell operation: The present invention relates to a multi-bit non-volatile memory device having a dual gate employing local charge trap and method of manufacturing the same, and an operating method for a multi-bit cell operation....

20060237778 - Non-volatile semiconductor memory cell and method of manufacturing the same: A non-volatile memory cell. The non-volatile memory cell comprises a substrate with a first conductive type, a gate structure, at least two source/drain regions with a second conductive type and a buried channel region with the second conductive type. The gate structure is located on the substrate, and the source/drain...

20060237779 - Semiconductor device and fabrication method therefor: A semiconductor device includes an ONO film (17) formed on a semiconductor substrate (15), a first gate (14), the first gate (14) formed on the ONO film (17), a source (10) and a drain (12) provided at both sides of the first gate (14) to face each other, and a...

20060237782 - Power semiconductor device with l-shaped source region: A power semiconductor device includes a substrate, a well region, a body region, a trench gate, a gate oxide layer, an L-shaped source region, an inter-layer dielectric layer and a metal layer. The body region is formed on the well region. The trench gate is formed at bilateral sides of...

20060237783 - Semiconductor device having a recess channel and method for fabricating the same: Provided is a semiconductor device having recess channel, comprising a semiconductor substrate having first and second trenches disposed to cross each other on both sides of an active region among adjoining regions between an active region and element-isolation films; a gate insulation film disposed on the semiconductor substrate of the...

20060237780 - Semiconductor device having screening electrode and method: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a screening electrode spaced apart from a channel region....

20060237781 - Structure and method for forming trench gate fets with reduced gate to drain charge: a field effect transistor includes a trench extending into a semiconductor region. The trench has a gate dielectric lining the trench sidewalls and a gate electrode therein. A channel region in the semiconductor region extends along a sidewall of the trench. The gate dielectric has a non-uniform thickness such that...

20060237784 - Method and apparatus with varying gate oxide thickness: An integrated circuit having an enhanced on-off swing for pass gate transistors is provided. The integrated circuit includes a core region that includes core transistors and pass gate transistors. The core transistors have a gate oxide associated with a first thickness, the pass transistors having a gate oxide associated with...

20060237785 - Strained complementary metal oxide semiconductor (cmos) on rotated wafers and methods thereof: The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that...

20060237786 - Power semiconductor device: A power semiconductor device according to the present invention comprises: a first conductive type base layer; a second conductive type base layer selectively formed on the first conductive type base layer; an insulation layer formed in the region on the first conductive type base layer on which the second conductive...

20060237787 - Semiconductor device and a method of manufacturing the same: In a technique to improve the high-frequency power gain of an LDMOS, the distance from the surface of a passivation film covering electrode pads to the rear surface of a silicon substrate is set into 200 μm or less, or a trench of 2 μm or more in thickness, in...

20060237788 - Semiconductor device and its fabrication method: A semiconductor device has a semiconductor substrate, a first MOSFET which has a first gate insulating film made of a high dielectric material formed above the semiconductor substrate and a first gate electrode formed above the first gate insulating film, an insulating film which is formed directly on sidewalls of...

20060237790 - Structure and method for manufacturing planar soi substrate with multiple orientations: The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single...

20060237789 - Thin film transistor (tft) and flat panel display including the tft: A Thin Film Transistor (TFT) that can reduce leakage current and can prevent crosstalk between adjacent TFTs includes: a substrate; a gate electrode disposed on the substrate; a source electrode and a drain electrode separated from each other and insulated from the gate electrode; and a semiconductor layer which is...

20060237791 - Ultra thin body fully-depleted soi mosfets: A method of creating ultra thin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen...

20060237792 - Electrostatic discharge protection device: An electrostatic discharge (ESD) protection device includes a first-type substrate, a second-type well formed in the substrate and a first-type well formed in the substrate. The second-type well includes a second-type+ region formed between first and second first-type+ regions. The first-type well is formed in the substrate adjacent a first...

20060237793 - Igbt with injection regions between mosfet cells: A cellular MOSgated device of planar or trench topology has base injection regions formed between pairs of cells to inject minority carriers to modulate the resistivity of the drift region....

20060237794 - Method for providing a programmable electrostatic discharge (esd) protection device: A method for providing a programmable electrostatic discharge (ESD) protection device is provided. The method includes providing a source diffusion in a substrate, providing a deeper body diffusion in the substrate, providing a gate at a space between the source diffusion and the body diffusion, and providing a variable structure...

20060237795 - Semiconductor device and a method of manufacturing the same: A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of...

20060237797 - Triple well structure and method for manufacturing the same: The present invention discloses a triple well structure, which includes a substrate of a first conductive type, a deep buried well of a second conductive type, a well of a first conductive type, a well ring of a second conductive type, and a well ring of a first conductive type....

20060237796 - Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled cmos devices: The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes...

20060237798 - Semiconductor chip with fuse unit: A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside of the logic circuit unit and the memory macro unit, and the least one fuse unit group storing...

20060237799 - Carbon nanotube memory cells having flat bottom electrode contact surface: The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a...

20060237800 - Semiconductor contact device: The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and self-aligned vias in a first layer disposed over the array to form contacts to each of the source and drain junction in the array. Further, self-aligned...

20060237801 - Compensating for induced strain in the channels of metal gate transistors: Strained channel field effect transistors may have a threshold voltage shift. This threshold voltage shift may be compensated for by adjusting channel doping. But this also adversely affects mobility. The threshold voltage shift may be compensated, without adversely affecting mobility, by tailoring the workfunction of a metal gate electrode used...

20060237802 - Method for improving sog process: A method for forming a memory device includes providing a substrate, providing a plurality of features on the substrate, and forming a silicon-rich dielectric layer over the features. An inter-layer dielectric (ILD) or inter-metal dielectric (IMD) layer may be formed by a spin-on-glass (SOG) process on the silicon-rich dielectric layer,...

20060237803 - Ultra-thin hf-doped-silicon oxynitride film for high performance cmos applications and method of manufacture: A semiconductor structure and method of forming the same, comprising forming a uniform buffer layer of diffusion-controlling stable material on top of a base gate dielectric layer, and then forming a uniform layer which contains a source of transitional metal atoms, and then annealing the structure to diffuse the transitional...

20060237804 - Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films: The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors....

20060237805 - Sensor platform using a horizontally oriented nanotube element: Sensor platforms and methods of making them are described, and include platforms having horizontally oriented sensor elements comprising nanotubes or other nanostructures, such as nanowires. Under certain embodiments, a sensor element has an affinity for an analyte. Under certain embodiments, such a sensor element comprises one or more pristine nanotubes,...

20060237806 - Micromachined microphone and multisensor and method for producing same: A micromachined microphone is formed from a silicon or silicon-on-insulator (SOI) wafer. A fixed sensing electrode for the microphone is formed from a top silicon layer of the wafer. Various polysilicon microphone structures are formed above a front side of the top silicon layer by depositing at least one oxide...

20060237807 - Electro-optic transducer die including a temperature sensing pn junction diode: An electro-optic transducer die that includes both an optically emissive PN junction diode and a temperature sensing PN junction diode. Since the temperature sensing PN junction diode is in the very same die as the optically emissive PN junction diode, there is very little thermal resistance between the optically emissive...

20060237808 - Spin injection magnetic domain wall displacement device and element thereof: A spin injection magnetic domain wall displacement device has a plurality of spin injection magnetic domain wall displacement elements. Each element includes a magnetic domain wall displacement layer having a magnetic domain wall, and a first, second, and third magnetic layer groups each having a ferromagnetic layer. The first, second,...

20060237809 - Methods of making optoelectronic devices: The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator being silicon-enriched silicon oxide and silicon-enriched silicon nitride), and includes solar cells containing one or more layers of semiconductor-enriched insulator. The invention also includes methods of forming optoelectronic devices and solar cells....

20060237810 - Bonding interface for micro-device packaging: In one embodiment, a method for making a cover for a micro-device package includes forming a layer of silicon on a transparent substrate and selectively removing parts of the silicon layer to form a bonding ring and an alignment target....

20060237811 - Non-destructive, in-line characterization of semiconductor materials: A method for non-destructively determining parameters of a doped semiconductor material involves applying an excitation to a surface of the semiconductor material to photogenerate minority carriers in a region of the semiconductor material, presenting an electric field across the region of the semiconductor material, measuring photoluminescence produced by recombination of...

20060237812 - Electronic emitters with dopant gradient: Electron emitters and a method of fabricating emitters are disclosed, having a concentration gradient of impurities, such that the highest concentration of impurities is at the apex of the emitters and decreases toward the base of the emitters. The method comprises the steps of doping, patterning, etching, and oxidizing the...

20060237813 - Junction barrier schottky with low forward drop and improved reverse block voltage: This invention discloses a junction barrier Schottky device supported on a substrate that has a first conductivity type. The Schottky device includes a first diffusion region of a fist conductivity type for functioning as a forward barrier height reduction region. The Schottky device further includes a second diffusion region of...

20060237814 - Semiconductor device having surface mountable external contact areas and method for producing the same: A semiconductor device having surface-mountable external contact areas and a method for producing the same is disclosed. The surface-mountable external contacts are arranged as flat external contacts on the underside of the semiconductor device. In one embodiment, the semiconductor chip of the semiconductor device has a source contact area and...

20060237815 - High voltage integrated circuit device including high-voltage resistant diode: Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage...

20060237817 - Methods of forming asymmetric recesses and gate structures that fill such recesses and related methods of forming semiconductor devices that include such recesses and gate structures: In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufacturing the semiconductor device, a semiconductor substrate is etched to form...

20060237816 - Semiconductor device and manufacturing method for the same: In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film,...

20060237818 - Fuse structure of semiconductor device and method for fabricating same: Provided a double-wired fuse structure of a semiconductor device and a method for fabricating the same which is not affected electrically by fuse crack. The fuse structure of a semiconductor device comprises a fuse layer formed over a semiconductor substrate wherein a predetermined portion of the fuse layer is cut,...

20060237820 - Biasing device for low parasitic capacitance in integrated circuit applications: The present invention is directed to an apparatus and method for reducing a parasitic capacitance in an integrated circuit. The apparatus includes a substrate and a biasing device. The substrate has a circuit disposed thereon, wherein a first capacitance exists between the substrate and an element of the circuit. The...

20060237819 - Semiconductor device: A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has...

20060237821 - Interconnects including members integral with bit lines, as well as metal nitride and metal silicide, and methods for fabricating interconnects and semiconductor device structures including the interconnects: An interconnect includes a member that is integral and lacks a discernable boundary with a bit line, as well as metal nitride and metal silicide between the member and an active-device region of a semiconductor substrate. The interconnect may extend adjacent to and be insulated from a stacked capacitor structure...

20060237822 - Semiconductor substrate: A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over a back side of the wafer while in a rough state from backgrinding without prior, conventional polishing or plasma etching of the back side. The thin...

20060237823 - Shielding arrangement to protect a circuit from stray magnetic fields: A shielding arrangement for protecting a circuit containing magnetically sensitive materials from external stray magnetic fields. A shield of a material having a relatively high permeability is formed over the magnetically sensitive materials using thin film deposition techniques. Alternatively, a planar shield is affixed directly to a surface of semiconductor...

20060237825 - Device packages having a iii-nitride based power semiconductor device: A semiconductor device package includes a die pad, a substrate disposed on the die pad, and a III-nitride based semiconductor device disposed on the substrate. The device package may also include a second semiconductor device disposed on the die pad or the substrate, which device may be electrically connected to...

20060237824 - Lead frame for semiconductor package and method of manufacturing the same: A lead frame for a semiconductor package and a manufacturing method thereof are provided. In the lead frame, a Ni plating layer made of Ni or a Ni alloy is plated on a base metallic layer. A Ni—Pd plating layer made of a Ni—Pd based alloy and having a Ni...

20060237826 - Leadframe designs for plastic overmold packages: The specification describes a plastic overmolded package for high power devices that has a very low lead count, typically fewer than eight, and in a preferred embodiment, only two. The leads occupy essentially the same linear space as the multiple leads in a conventional package and thus have a wide-blade...

20060237827 - Thermal enhanced low profile package structure and method for fabricating the same: A thermal enhanced low profile package structure and a method for fabricating the same are provided. The package structure typically includes a metallization layer with an electronic component thereon which is between two provided dielectric layers. The metallization layer as well as the electronic component is embedded and packaged while...

20060237829 - Method and system for a semiconductor package with an air vent: Systems and methods for a structure for semiconductor packages where the effects that features on the package substrate have on the impedance of signal traces within the semiconductor package is substantially reduced. These systems and methods may allow a feature, or multiple features, to be placed anywhere on the semiconductor...

20060237830 - Semiconductor device and electronic device: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a...

20060237831 - Semiconductor device and electronic device: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a...

20060237832 - Standoffs for centralizing internals in packaging process: A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the semiconductor device comprises a pair of semiconductor dies mounted on opposing sides of a flexible tape substrate, the outer surfaces of the dies having one or more standoffs...

20060237828 - System and method for enhancing wafer chip scale packages: System and method for enhancing the performance of wafer chip scale packages (WCSP). A preferred embodiment comprises a parent electrical device 305 and a daughter electrical device 310 coupled to a bottom surface of the parent electrical device, wherein the bottom surface is also used to attach the parent electrical...

20060237833 - System having semiconductor component with multiple stacked dice: A system includes a semiconductor component having a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary die to the base die, and a set of interconnect contacts configured as an...

20060237835 - Electronic circuit device: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by...

20060237834 - Method for forming an electric device comprising power switches around a logic circuit and related apparatus: A method for forming an electric device having power switches around a logic circuit including: forming a logic circuit on a substrate; forming a plurality of power switches around the logic circuit; and coupling first ends of the power switches to a voltage end, and coupling second ends of the...

20060237836 - Microelectronic assemblies having compliant layers: A compliant semiconductor chip package assembly includes a a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also...

20060237837 - Field effect transistor and method of manufacturing the same: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the...

20060237839 - Apparatus for conducting heat in a flip-chip assembly: An apparatus for thermally conducting heat from a semiconductor device, namely, a flip-chip assembly. In one embodiment, a heat sink, such as a diamond layer having openings therein, is provided over a surface of a semiconductor device. Conductive pads are formed in the openings to be partially contacting the diamond...

20060237838 - Thermal interconnect systems methods of production and uses thereof: Layered interface materials described herein include at least one pulse-plated thermally conductive material, such as an interconnect material, and at least one heat spreader component coupled to the at least one pulse-plated thermally conductive material. A plated layered interface material having a migration component is also described herein and includes...

20060237840 - Semiconductor package: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can....

20060237841 - Semiconductor device and method for producing the same: A semiconductor device includes a tape carrier substrate having a flexible insulating film base, a plurality of conductor wirings provided on the film base, and wiring bumps respectively formed so as to cover an upper surface and both side surfaces of the conductor wirings, and a semiconductor chip mounted on...

20060237842 - Semiconductor device including an under electrode and a bump electrode: Making the relative size of the surface area of a bump electrode at a portion in contact with an under electrode larger than the surface area of a base of a hole increases the contact surface area between the lower surface of the bump electrode and a polyimide layer. As...

20060237843 - Bga-type multilayer circuit wiring board: Provided is a BGA-type multilayer circuit wiring board which is mounted on a printed wiring board directly via a solder ball with the electrode pad for solder ball connection formed thereon and in which the electric connection reliability of the filled via connected to the electrode pad for solder ball...

20060237844 - Semiconductor integrated circuit package having electrically disconnected solder balls for mounting: Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to temporarily hold the die in position with...

20060237845 - Semiconductor integrated circuit package having electrically disconnected solder balls for mounting: Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to temporarily hold the die in position with...

20060237846 - Doped nitride film, doped oxide film and other doped films and deposition rate improvement for rtcvd processes: When forming a silicon nitride film from a nitrogen precursor, using a silicon precursor combination rather than a single silane precursor advantageously increases the deposition rate. For example, adding silane during formation of a silicon nitride film made using BTBAS and ammonia improves (increases) the deposition rate while still yielding...

20060237847 - Integrated circuit interconnect: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the...

20060237848 - Semiconductor device having a leading wiring layer: A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first...

20060237849 - Electronic device, method of manufacture of the same, and sputtering target: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least...

20060237851 - Semiconductor device and related method of manufacture: Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a...

20060237852 - Semiconductor device in which lsi chip is arranged on package substrate in flipped condition and substrate wiring designing method: In the LSI design stage, areas indicating the circuits that handle a minute signal are formed as wiring excluding area patterns. The coordinates of the wiring excluding area patterns in a state that the LSI chip is flipped are calculated, and the substrate design tool is caused to recognize such...

20060237850 - Semiconductor die edge reconditioning: An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut...

20060237853 - Cobalt tungsten phosphate used to fill voids arising in a copper metallization process: A semiconductor device includes a substrate, at least one layer of functional devices formed on the substrate, a first dielectric layer formed over the functional device layer and a first trench/via located in the first dielectric layer. A copper conductor fills the first trench/via. An electromigration inhibiting barrier layer is...

20060237854 - Carrying structure of electronic components: A carrying structure of electronic components is proposed. The carrying structure includes at least one supporting board with at least one cavity disposed thereon, at least one adhesive layer formed on the supporting board, and at least one electronic component having an active face and a non-active face located in...

20060237855 - Substrate for producing a soldering connection to a second substrate: A substrate for producing a soldering connection to a second substrate is disclosed. Soldering pads are distributed on the substrate surface. Solder balls can be applied to these pads. A soldering pad has a top side area and side areas connected to a conductor track. A soldering mask with openings...

20060237856 - Microelectronic contact structure and method of making same: Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined on a sacrificial substrate. The openings may be within the surface of the substrate, or in one or more layers deposited on the surface of the sacrificial substrate. Each spring contact element has...

20060237857 - Hybrid carbon nanotube fet(cnfet)-fet static ram (sram) and method of making same: Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain...

20060231822 - Flash memory devices and methods of fabricating the same: A flash memory device includes a common source region that is disposed in an active region at a side of a ground-selection gate line, being apart from the ground-selection gate line. A pair of source spacers crosses over both top edges of the common source region. A source line fills...

20060231823 - Structure for amorphous carbon based non-volatile memory: A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a second layer of amorphous carbon. The device also includes at least one first conductive layer common to the at least one first and the...

20060231824 - Resistance variable memory with temperature tolerant materials: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device....

20060231825 - Use of quasi-one-dimensional transition metal ternary compounds and quasi-one-dimensional transition metal chacogenide compounds as electron emitters: The present invention pertains to the use of quasi-one-dimensional transition metal ternary compounds MxHyHaz (where M is a transition metal Mo, W, Ta, Nb; H is sulfur (S), selenium (Se), tellurium (Te); Ha is iodine (I)) and of doped quasi-one-dimensional transition metal ternary compounds MxHyHaz, (where M=Ta, Ti, Nb; H...

20060231826 - Step-embedded sige structure for pfet mobility enhancement: A device, and method for manufacturing the same, including a PFET having an embedded SiGe layer where a shallow portion of the SiGe layer is closer to the PFET channel and a deep portion of the SiGe layer is further from the PFET channel. Thus, the SiGe layer has a...

20060231830 - Display device and a method of manufacturing the same: In a display device having a plurality of organic electroluminescence devices arranged on a substrate, each of the devices including a lower electrode, an organic layer at least containing a light emitting layer, and an upper electrode in this order, the light emitting layer of at least some of the...

20060231827 - Functional organic thin film, organic thin-film transistor, pi-electron conjugated molecule-containing silicon compound, and methods of forming them: An organic thin film having both a chemical structure of an organic material that is a factor determining a characteristic of the thin film and a high-order structure of the thin film, for example, the crystallinity of molecules, namely, the orientation. A functional organic thin film composed of molecules the...

20060231831 - Light emitting display device and method of manufacturing the same: The present invention relates to a light emitting display device, such as an organic electroluminescent device, and a method for manufacturing the same. Particularly, the present invention relates to reducing electrical resistance between the scan lines and the cathode electrode layers so that scan line signals do not degrade significantly...

20060231828 - Light-emitting diode: The invention pertains to a light-emitting diode (LED) comprising layers of an anode, an acidic hole conducting-injecting material, a light-emitting polymer, and a cathode, characterized in that the hole conducting-injecting material comprises a poly(3,4-ethylenedioxythiophene poly(styrenesulfonate) (PEDOT), which is obtainable by at least partially neutralizing the PEDOT with an anion that...

20060231832 - Liquid crystalline organic compound, organic semiconductor structure, organic semiconductor device, and process for producing liquid crystalline organic compound: wherein, R1 and R2 are each independently a saturated or unsaturated hydrocarbon of a straight chain, a branched chain or a cyclic structure having 1 to 22 carbon atoms; R1 and R2 may be each independently bonded directly to Z1 without interposing Y1 or Y2 therebetween; and Y1 and Y2...

20060231829 - Tft gate dielectric with crosslinked polymer: A thin film transistor composed of a gate dielectric which includes a radiation-induced crosslinked polymer composed of polymerized one or more monomers, wherein the one or more monomers include an optionally substituted vinyl arylalcohol....

20060231834 - Bonding strength testing device: A bonding strength test device suits to perform a bonding strength test for at least one solder ball that fixed on a substrate. The bonding strength test device includes a fixed base and an impact apparatus. The impact apparatus has a first end and a second end corresponding to the...

20060231833 - High-frequency, high-signal-density, surface-mount technology footprint definitions: Methods for designing SMT connector footprints are disclosed. A circuit board may have disposed thereon an arrangement of SMT pads and corresponding vias. The arrangement of vias may differ from the arrangement of SMT pads. The arrangement of SMT pads may differ from the arrangement of contacts in a connector...

20060231835 - Semiconductor device including rom interface pad: A semiconductor device comprises a multilayer formed on a semiconductor substrate, the multilayer including a first circuit pattern, a second circuit pattern for testing the semiconductor device, the second circuit formed on a predetermined region of the multilayer, an inter-metal insulating layer formed on the second circuit pattern, a plurality...

20060231836 - Surge voltage protection diode and method of forming the same: To prevent the destruction of a semiconductor element due to negative resistance, and to reduce the dynamic resistance of a static electricity prevention diode, the ratio of the maximum electric field intensity during an avalanche and the average electric field in a strong electric field region, as well as the...

20060231840 - Active matrix substrate, method of making the substrate, and display device: An active matrix substrate includes base substrate, gate lines, data lines, thin-film transistors and pixel electrodes. The gate lines are formed on the base substrate. The data lines are formed over the gate lines. Each of the data lines crosses all of the gate lines with an insulating film interposed...

20060231838 - Liquid crystal display: A liquid crystal display includes an array of pixels. Each pixel is divided into a first sub-pixel and a second sub-pixel, and different data voltages are separately applied to (or evolved at) the two sub-pixels, thereby enhancing the lateral side visibility. Each sub-pixel includes a sub-pixel electrode (connected to the...

20060231839 - Method of treating inorganic oxide film, electronic device substrate, method of manufacturing electronic device substrate, liquid crystal panel, and electronic apparatus: A method of treating an inorganic oxide film includes: dipping an inorganic oxide film having a plurality of pores therein which is formed by an oblique deposition method into a treatment liquid containing alcohol; reducing pressure of a space where the treatment liquid is provided to infiltrate the treatment liquid...

20060231837 - Thin-film assembly and method for producing said assembly: A thin-film assembly (1) including a substrate (2) and at least one electronic thin-film component (8) applied on the substrate by thin-film technology, wherein a base electrode (4) is provided on the substrate, on which base electrode thin-film layers (21) forming part of the thin-film component are arranged together with...

20060231841 - Silicon carbide semiconductor device: A silicon carbide semiconductor device includes a semiconductor element disposed in a semiconductor substrate having a first conductive type silicon carbide layer and a silicon substrate. The device includes: a trench on the silicon carbide layer to reach the silicon substrate; and a conductive layer in the trench between the...

20060231842 - Display device: To improve an image quality of an organic EL display by utilizing characteristics of a dual emission type organic light emitting element. A display device includes a first substrate over which a plurality of organic light emitting elements are provided and a second substrate over which an organic light emitting...

20060231844 - Organic optoelectronic device: An organic optoelectronic device includes a substrate having an upper surface and a lower surface, at least one organic diode situated on the upper surface of the substrate, the organic diode including, an anode including a material of high work function situated over the upper surface of the substrate, an...

20060231843 - Phosphorescent light-emitting component comprising organic layers: The invention relates to a light emitting component with organic layers and emission of triplet exciton states (phosphorescent light) with increased efficiency, having a layer sequence with a hole injecting contact (anode), one or more hole injecting and transporting layers, a system of layers in the light emission zone, one...

20060231846 - Thin film transistor array panel for liquid crystal display: A black matrix having an opening at pixels of a matrix array in a display area, a common wire including common pads and common signal lines, and gate pads in a peripheral area, and an alignment key in outer area to align interlayer thin films are formed on an insulating...

20060231845 - White-light emitting semiconductor device: A white-light emitting semiconductor device includes a first light-emitting die, a second light-emitting die, a photostimulable luminescent substance, and a holding assembly. The first light-emitting die emits a first radiation having a first wavelength range. The second light-emitting die emits a second radiation having a second wavelength range, and a...

20060231847 - Multiple-wavelength light emitting diode and its light emitting chip structure: The present invention discloses a multiple-wavelength light emitting diode that includes a fluorescent layer with a predetermined wavelength disposed at the bottom of the light emitting diode, such that a light emitting chip can be fixed onto a carrier and connected in parallel with the circuit of the light emitting...

20060231848 - Light emitting diode package for enhancing light extraction: A light emitting diode package for enhancing light extraction includes a plurality of LED dies. A holder having a die pad on which the LED dies are seated and a plurality of pins is electrically connected to the plurality of LED dies respectively. A transparent molding covers the plurality of...

20060231849 - White light emitting diode component having two phosphors and related phosphor and formation method: A white light emitting diode component capable of emitting white light includes an LED chip capable of emitting luminescent light, a first phosphor for absorbing first luminescent light of the luminescent light and emitting first emission, and a second phosphor for absorbing second luminescent light of the luminescent light and...

20060231850 - Semiconductor laser diode having ridge portion and method of manufacturing the same: Provided is a semiconductor laser diode having a ridge portion and a method of manufacturing the semiconductor laser diode. The semiconductor laser diode includes: a first clad layer, an active layer formed on the first clad layer, a second clad layer formed on the active layer and having a stripe...

20060231851 - Red phosphor for led based lighting: Disclosed are phosphor compositions having the formula (RE1-yCey)Mg2-xLixSi3-xPxO12, where RE is at least one of Sc, Lu, Gd, Y, and Tb, 0.0001<x<0.1 and 0.001<y<0.1. When combined with at least one additional phosphor and subjected to radiation from a blue or UV LED, these phosphors can provide white light sources with...

20060231854 - Flip chip type nitride semiconductor light emitting device: The present invention relates to a flip chip type nitride semiconductor light emitting device having p-type and n-type nitride semiconductor layers, and an active layer in between. The invention also has an ohmic contact layer formed on the p-type nitride semiconductor layer, a light-transmitting conductive oxide layer formed on the...

20060231856 - Led device and optical detector therewith for bill validator: An LED device is provided which comprises a plastic encapsulant 7 formed with an integrated cylindrical lens 8 disposed opposite to an LED chip 5 to provide light from LED chip 5 with the wider directivity angular range in the vertical Y irradiative direction than that in the horizontal X...

20060231855 - Semiconductor device: A semiconductor device includes a semiconductor element, a light-blocking region enclosing the semiconductor element, a plurality of contacts disposed in a staggered arrangement in a first region of the light-blocking region, and a linear contact formed to extend along at least a first direction in a second region of the...

20060231853 - Semiconductor light-emitting device and its manufacturing method: In a light-emitting device and its manufacturing method, mounting by batch process with surface-mount technology, high light extraction efficiency, and low manufacturing cost are realized. The light-emitting device 1 comprises semiconductor layers (2, 3) of p-type and n-type nitride semiconductor, semiconductor-surface-electrodes (21, 31) to apply currents into each of the...

20060231852 - Semiconductor light-emitting device, method for manufacturing same and light-emitting apparatus using same: A nitride semiconductor light-emitting device includes a layered portion emitting light on a substrate. The layered portion includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The periphery of the layered portion is inclined, and the surface of the n-type semiconductor layer is exposed at the...

20060231857 - Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) device: A method for making a semiconductor device may include forming at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto. The NDR device may include a superlattice including a plurality of stacked groups of layers, with each group of layers of the...

20060231858 - Display device and manufacturing method of the display device: It is an object of the present invention to provide a technique to manufacture a highly reliable display device at a low cost with high yield. A display device according to the present invention includes a semiconductor layer including an impurity region of one conductivity type; a gate insulating layer,...

20060231859 - Heterojunction bipolar transistor: An n-type InP sub collector layer 2 heavily doped with silicon (Si), an InP collector layer 3, a p-type GaAs(0.51)Sb(0.49) base layer 4 heavily doped with carbon (C), an n-type In(1-y)Al(y)P emitter layer 7 doped with Si, an n-type InP cap layer 8 heavily doped with Si, and an n-type...

20060231861 - Field effect transistor and method of manufacturing the same: An FET includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound...

20060231860 - Polarization-doped field effect transistors (polfets) and materials and methods for making the same: Novel GaN/AlGaN metal-semiconductor field-effect transistor (MESFET) structures grown without any impurity doping in the channel. A high-mobility polarization-induced bulk channel charge is created by grading the channel region linearly from GaN to Al0.3Ga0.7N over a distance, e.g., 1000 Å. A polarization-doped field effect transistor (PolFET) was fabricated and tested under...

20060231862 - Ballistic semiconductor device: A ballistic semiconductor device of the present invention comprises a n-type emitter layer (102), a base layer (305) made of n-type InGaN, a n-type collector layer (307), an emitter barrier layer (103) interposed between the emitter layer (102) and the base layer (305) and having a band gap larger than...

20060231863 - Manufacturing process of a chip package structure: A manufacturing process of a chip package structure is provided. The manufacturing method uses fine pitch circuit processes, such as a TFT-LCD process or an IC process, to increase layout density and shorten electrical transmission pathways so that a higher electrical performance level is attained. First, a multi-layered interconnection structure...

20060231864 - Sealed nitride layer for integrated circuits: The present invention relates to an integrated circuit. The integrated circuit includes a substrate, at least one device region formed in the substrate, a patterned layer of oxide, a first and second layer of nitride and at least one metal contact region. The patterned layer of oxide is formed over...

20060231865 - Electromechanical three-trace junction devices: Three-trace electromechanical devices and methods of using same are described. The device of the present invention includes first and second electrically conductive elements with a nanotube ribbon (or other electromechanical elements) disposed therebetween. The nanotube ribbon is capable of maintaining its position after removing an electrical stimulus applied to at...

20060231866 - Method and circuit arrangement for setting an initial value on a charge-storage element: A method is provided for setting an initial value on a charge-storage element. A circuit includes at least one charge-storage element with at least one signal node coupled to at least one reset circuit that is associated with the charge-storage element. A diode can be included between the charge-storage element...

20060231867 - Semiconductor device and manufacturing method thereof: A semiconductor device has a semiconductor base, an anode electrode, and a cathode electrode. The semiconductor base includes a P type semiconductor substrate, an insulating film, an N− type semiconductor region formed on the insulating film, an N+ type semiconductor region, and a P+ type semiconductor region facing the N+...

20060231868 - Semiconductor device for high voltage ic: A semiconductor device includes: a plurality of transistors connected in series between a ground potential and a predetermined potential; an input terminal provided by a gate terminal of the first step transistor; a plurality of resistors connected in series between the ground potential and the predetermined potential; and an output...

20060231869 - Non-volatile memory device capable of preventing damage by plasma charge: A non-volatile memory device for preventing damage by plasma charges includes a gate electrode formed on a predetermined region of a semiconductor substrate, a source/drain region which is overlapped with the gate electrode and formed in a first well region of the semiconductor substrate, a first metal line coupled to...

20060231870 - Cmos image sensor and method of fabricating the same: A CMOS image sensor and a method of fabricating the same are provided. The image sensor includes a blocking layer protecting a photodiode at a diode region. The blocking layer is formed to cover a top of the diode region and extended to an active region so as to cover...

20060231871 - Semiconductor device: A gate electrode serving as a Schottky electrode includes a TaNx layer and an Au layer. The TaNx layer serves as a barrier metal for preventing atoms from diffusing from the Au layer into a substrate. TaNx does not contain Si, and therefore has a higher humidity resistance than WSiN...

20060231874 - Field effect transistor and method for fabricating it: A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention...

20060231872 - Field effect transistor using insulator-semiconductor transition material layer as channel material and method of manufacturing the same: Provided is a field effect transistor including an insulator-semiconductor transition material layer. The insulator-semiconductor transition material layer selectively provides a first state where charged holes are not introduced to a surface of the insulator-semiconductor transition material layer when a gate field is not applied and a second state where a...

20060231873 - Planar dual-gate field effect transistors (fets): A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region on the back gate dielectric region comprising...

20060231875 - Dual conversion gain pixel using schottky and ohmic contacts to the floating diffusion region and methods of fabrication and operation: The exemplary embodiments provide an imager with dual conversion gain charge storage and thus, improved dynamic range. A dual conversion gain element (e.g., Schottky diode) is coupled between a floating diffusion region and a respective capacitor. The dual conversion gain element switches in the capacitance of the capacitor, in response...

20060231876 - Semiconductor device and mask pattern: A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3...

20060231877 - Semiconductor device: A semiconductor device comprises a semiconductor substrate having a surface of a plane orientation {100}, and a plurality of memory cells formed on the semiconductor substrate. The memory cells each include a capacitor formed in a trench extending from the surface into the semiconductor substrate, and a transistor. The transistor...

20060231879 - Merged mos-bipolar capacitor memory cell: A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-polar transistor having an emitter region, a base region and...

20060231878 - Semiconductor device and method for manufacturing same: The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor 116 formed on the semiconductor substrate 102, including a structure composed of a lower electrode 118, a capacitive film 120 and an upper electrode 122, which are stacked in this sequence; an extracting unit 124 of the upper electrode...

20060231880 - Semiconductor device and method of fabricating the same: According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate, and a capacitor formed above the semiconductor substrate by sandwiching a dielectric film between a lower electrode and upper electrode, wherein the upper electrode has a stacked structure including a first MOx type...

20060231881 - Multiple dielectric finfet structure and method: Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics...

20060231882 - Low voltage flexible organic/transparent transistor for selective gas sensing, photodetecting and cmos device applications: A thin film transistor (TFT) includes a source electrode, a drain electrode, and a gate electrode. A gate insulator is coupled to the source electrode, drain electrode, and gate electrode. The gate insulator includes room temperature deposited high-K materials so as to allow said thin film transistor to operate at...

20060231884 - Nonvolatile semiconductor device and method of manufacturing nonvolatile semiconductor device: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate,...

20060231886 - Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers: Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel...

20060231883 - Semiconductor device: A semiconductor memory device, firstly, has both the thickness of a tunnel film and that of a top film provided thereon and configured to be in the FN tunneling region (4 nm or more). The data retention characteristics can be improved by configuring both the thickness of a tunnel film...

20060231885 - Semiconductor device and method of fabricating the same: The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation...

20060231887 - Memory device having serially connected resistance nodes: A memory device may include a plurality of resistance nodes. The resistance nodes may be connected serially in a NAND or AND structure, by a plurality of metal plugs. The metal plugs may have a lower resistance. A control device corresponding to each resistance node may control the resistance devices....

20060231888 - Programmable and erasable digital switch device and fabrication method and operating method thereof: A programmable and erasable digital switch device is provided. An N-type memory transistor and a P-type memory transistor are formed over a substrate. The N-type memory transistor includes a first N-type doped region, a second N-type doped region, a first charge storage layer and a first control gate. The P-type...

20060231889 - Two-terminal solid-state memory device and two-terminal flexible memory device based on nanocrystals or nanoparticles: A two-terminal memory device based on semiconductor (such as Si or Ge) or metal (such as Al or Au) nanocrystals and/or nanoparticles is described wherein each device has a substrate, a dielectric layer (such as SiO2 or organic dielectric materials) nanocrystals and/or nanoparticles distributed throughout the dielectric layer, and a...

20060231890 - Technique for improving negative potential immunity of an integrated circuit: An integrated circuit (IC) with negative potential protection includes at least one double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The IC also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket and a...

20060231892 - Enhanced silicon-on-insulator (soi) transistors and methods of making enhanced soi transistors: Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions...

20060231893 - Hybrid crystal orientation cmos structure for adaptive well biasing and for power and performance enhancement: The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device...

20060231891 - Soi sram products with reduced floating body effect and the method thereof: A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer. The memory device includes a memory array in a memory region of the SOI structure, a plurality of first substrate...

20060231894 - Transistor: A transistor comprises: an insulating layer; a semiconductor layer provided on a major surface of the insulating layer; a gate insulating layer provided on the base region; and a gate electrode provided on the gate insulating layer. The semiconductor layer has a source portion having a plurality of source regions...

20060231896 - Esd protection device with thick poly film and method for forming the same: An ESD protection device with thicker polysilicon film, an electronic apparatus having the same, and a method for manufacturing the same are provided. The ESD protection device can be a diode or a MOS transistor with a thicker polysilicon film employed in an ESD protection circuit to protect an electronic...

20060231895 - Guardwall structures for esd protection: A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well,...

20060231897 - Guardwall structures for esd protection: A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well....

20060231898 - Cmos image sensor and method of manufacturing the same: Provided are a CMOS image sensor and a method of manufacturing the same. The CMOS image sensor includes a semiconductor substrate having photodiodes and transistors. An interlayer insulating layer is formed on the resultant structure having the photodiodes and transistors, and light blocking patterns are formed on the interlayer insulating...

20060231899 - Hybrid bulk-soi 6t-sram cell for improved cell stability and performance: The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first...

20060231900 - Semiconductor device having fine contacts and method of fabricating the same: A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer disposed on the substrate, annular spacers situated in the interlayer insulating layer,...

20060231901 - Semiconductor device: A semiconductor device comprising an n-channel region and a p-channel region formed on a common substrate, both channel regions having a source and a drain, the device further comprising a gate electrode common to both channel regions and spaced from the substrate by an area of non-polarising dielectric material arranged...

20060231902 - Locos trench isolation structures: Isolation structures having trenches formed on both sides of a LOCOS structure are disclosed. A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede, such that a portion of the...

20060231903 - Semiconductor devices having dual capping layer patterns and methods of manufacturing the same: Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked thereon. At least one gate pattern...

20060231904 - Monolithically-integrated buck converter: An integrated buck converter is formed on a substrate of a first polarity type and having a first and second substrate surface. An epitaxial layer is formed over the first substrate surface and has a first epitaxial layer surface. A drift region lightly-doped with dopants of a second polarity type...

20060231905 - Electronic device comprising a field effect transistor for high-frequency aplications: An electronic device comprising a field-effect transistor having an inter digitated structure suitable for high-frequency power applications, and having multiple threshold voltages that are provided in different regions of each a segment of the interdigitated structure. This leads to a dramatic improvement in linearity over a large power range in...

20060231907 - Semiconductor device with finfet and method of fabricating the same: A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in...

20060231906 - Structure for measuring gate misalignment and measuring method thereof: Provided are an improved structure for measuring gate misalignment and a measuring method thereof. The structure includes an active region and a device isolation region, a first gate group including a plurality of gates extending in one direction at one side of the active region, widths of the gates being...

20060231908 - Multilayer gate dielectric: An electronic device composed of: a multilayer dielectric including: (i) a first layer composed of a first material selected from the group consisting of an optionally substituted silsesquioxane, an optionally substituted silsesquioxane-metal oxide hybrid composition, an optionally substituted siloxane-metal oxide hybrid composition, and a mixture thereof, and (ii) a second...

20060231909 - Method of manufacturing an non-volatile memory device: A method of manufacturing an non-volatile memory device is provided herein. A substrate is provided and then a trench is formed in the substrate. Thereafter, a bottom oxide layer, a charge-trapping layer and a top oxide layer are sequentially formed over the substrate and the surface of the trench. A...

20060231910 - Method for forming silicide and semiconductor device formed thereby: A method for forming silicide and a semiconductor device formed thereby. A Si-containing polycrystalline region is converted to an amorphous region, and annealed to form a regrown polycrystalline region having an increased grain size. A silicide layer is formed by reacting a metal and the regrown polycrystalline region having the...

20060231911 - Method of manufacturing and image device: An imaging device comprises a select line, a first signal line crossing the select line, and a first pixel provided at a portion corresponding to a crossing portion of the select line and the first signal line, the first pixel comprising a first buffer layer formed on a substrate, a...

20060231912 - Printed wiring board and information processing apparatus: According to one embodiment, a printed wiring board includes, a main body including an obverse side with an obverse wiring layer, and a reverse side with a reverse wiring layer first pads provided on the obverse side in a first region defined thereon, and to be connected to terminals arranged...

20060231913 - Method for determining wavelengths of light incident on a stacked photodetector structure: Described are a device and a method for determining a wavelength of light incident on a device having an upper photodiode vertically disposed on a lower photodiode. Currents generated by the upper and lower photodiodes in response to the incident light are measured. The wavelength of the light is determined...

20060231914 - Silicon-based visible and near-infrared optoelectric devices: In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the...

20060231915 - Process for high voltage superjunction termination: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is...

20060231917 - Semiconductor device: This semiconductor device comprises a pillar layer including a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type formed alternately on a first semiconductor layer. At the same depth position in the device region and the end region, a...

20060231916 - Semiconductor device and manufacturing method thereof: In this invention, the semiconductor device is provided with a gate electrode formed on a gate insulating film in a region sectioned by an element isolation formed on a semiconductor layer of the first conduction type, and a source region and a drain region of the second conduction type. At...

20060231918 - Field effect transistor and method for the production thereof: A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention...

20060231920 - Mim capacitor structure and method of fabrication: A method of forming a metal-insulator-metal (MIM) capacitor wherein a plate of a MIM capacitor is formed in the entire thickness of a metallization layer of a semiconductor device. At least one thin conductive material layer is disposed within the material of the metallization layer to reduce the surface roughness...

20060231919 - Passive microwave device and method for producing the same: The present invention provides an electrical circuit component, specifically a passive microwave device, and a method for producing the same. In one embodiment, the present invention provides an electrical circuit component, comprising: at least one patterned resistive area on a first surface of a diamond substrate, a first patterned conductive...

20060231921 - Micro fuse: A micro fuse for use in a semiconductor device. The micro fuse comprises an insulating substrate and an elongate metal fuse member, the fuse member being supported at either end on the substrate and including at least one fuse region suspended out of contact with the substrate and shaped such...

20060231922 - Gate dielectric antifuse circuit to protect a high-voltage transistor: According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to...

20060231923 - Inductor for semiconductor integrated circuit and method of fabricating the same: Disclosed are an inductor for a semiconductor integrated circuit, which provides a wider cross-sectional area, significantly reduces the resistance to improve the Q value and has a highly uniform film thickness, and a method of fabricating the inductor. A spiral inductor is formed on a topmost interconnection layer of a...

20060231924 - Bipolar transistor structure with self-aligned raised extrinsic base and methods: The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer...

20060231925 - Poly-silicon-germanium gate stack and method for forming the same: A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion...

20060231926 - Semiconductor wafer, semiconductor chip and dicing method of a semiconductor wafer: The metal wirings of the uppermost layer are exposed so as to be contactable to the probe and arranged so as to be spatially separated from one another via spaces that are approximately parallel to the longitudinal direction of the dicing area, and the position and size of the space...

20060231927 - Semiconductor chip mounting body and manufacturing method thereof: A semiconductor chip (20) including a protruding electrode (bump) (23) in an external extraction electrode is mounted on a wiring board (10), and a semiconductor chip (30) is mounted on the semiconductor chip (20). Electrical connections between a wiring layer (12) of the wiring board (10) and the protruding electrode...

20060231928 - Semiconductor device and chip-stack semiconductor device: A semiconductor device has multiple power-supply through electrodes, grounding through electrodes, and signal-routing through electrodes made through a semiconductor chip. The power-supply through electrodes, the grounding through electrodes, and the signal-routing through electrodes differ mutually in cross-sectional area. Hence, a semiconductor device and a chip-stack semiconductor device are provided which...

20060231929 - Semiconductor device having freestanding semiconductor layer: A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the...

20060231930 - Heat resistant photomask for high temperature fabrication processes: A temperature resistant photomask is disclosed which is made from photoresist containing Si, which is exposed to oxygen during Reactive Ion Etching. The temperature resistant photomask may include a secondary mask layer, which may also acts as a release layer, and which may include spin-on polymide. The photoresist containing Si...

20060231932 - Electrical package structure including chip with polymer thereon: An electrical package structure incorporating a chip with polymer thereon is described, including at least a package, a polymer and a molding compound. The package includes a carrier, at least one chip and multiple wires, wherein the chip is disposed on the carrier and the wires electrically connect the chip...

20060231931 - Lead frame for semiconductor package: A lead frame for a semiconductor package having not only high molding resin adhesiveness and a low delamination problem under a severe moisture absorbing atmosphere but also high interface adhesiveness and solder wettability of an Au wire, and a method of manufacturing the lead frame are provided. The lead frame...

20060231933 - Robust leaded molded packages and methods for forming the same: A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die...

20060231934 - Semiconductor device: Decrease in parasitic resistance caused by paste for adhering a semiconductor device to a lead frame or by a semiconductor substrate is disclosed. In a semiconductor device having a semiconductor substrate with an electrode formed on a rear surface thereof, an uneven structure is formed on the rear surface of...

20060231935 - Bga type semiconductor package featuring additional flat electrode teminals, and method for manufacturing the same: In a semiconductor package including a wiring board having a top surface, a bottom surface and a side face. The bottom surface is divided into a central area, and a peripheral area surrounding the central area. A semiconductor chip is mounted on the top surface of the wiring board so...

20060231936 - Semiconductor device having resin-sealed area on circuit board thereof: A semiconductor device having a molded sealing resin for sealing a semiconductor chip on a circuit board thereof reduces resin burrs resulting from the leakage of the sealing resin, and also restrains the occurrence of disconnection caused by a wiring layer being crushed. In the semiconductor device, the sealing resin...

20060231940 - High density direct connect loc assembly: An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces...

20060231939 - Multilevel semiconductor module and method for fabricating the same: A semiconductor module is formed by alternately stacking resin boards and sheet members. Each of the resin boards includes first buried conductors. A semiconductor chip is mounted on the upper face of each of the resin boards. Each of the sheet members having an opening for accommodating the semiconductor chip...

20060231938 - Structure for stacking an integrated circuit on another integrated circuit: Two or more semiconductor packages are stacked with an intervening element that is positioned between within an area surrounded by conductive bumps of a bottom surface of the overlying package. Different shapes of the intervening element are used depending upon how many sides of the bottom surface have conductive bumps....

20060231937 - Thin multiple semiconductor die package: A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (100) including a lead frame (10) having a plurality of leads (11)...

20060231941 - Pillar grid array package: A pillar grid array package (PGA) includes a substrate, a chip disposed on top of the substrate, and a plurality of stud bumps disposed on bottom of the substrate. The stud bumps are formed in an array and each has a flattened top to electrically connect to a printed circuit...

20060231942 - Semiconductor device: A semiconductor device includes a semiconductor substrate, an electrode pad, a wiring, a conductive post, an insulator, a sealing resin, and an external electrode. The electrode pad is formed on the main surface of the semiconductor substrate. The wiring is formed above the semiconductor substrate, the wiring electrically connecting with...

20060231943 - Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. When the substrate and dice are encased during the molding process, the rigid wave...

20060231944 - Thermally enhanced semiconductor package and fabrication method thereof: A thermally enhanced semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted and electrically connected to a chip carrier. A receiving plate having an opening is provided on the chip carrier and the semiconductor chip is received in the opening. A heat sink formed with...

20060231945 - Heat dissipation for heat generating element of semiconductor device and related method: A structure and method are disclosed for heat dissipation relative to a heat generating element in a semiconductor device. The structure includes a plurality of heat transmitting lines partially vertically coincidental with the heat generating element, and at least one interconnecting path from each heat transmitting line to a substrate...

20060231946 - Nanotube surface coatings for improved wettability: A thermal interface includes an array of generally aligned carbon nanotubes joined to a surface with a metal layer. The array of carbon nanotubes includes a coating on the ends of the carbon nanotubes for improved wetting of the metal layer to the ends of the carbon nanotubes so that...

20060231947 - Systems and methods for reducing simultaneous switching noise in an integrated circuit: Systems and methods for reducing switching noise in an integrated circuit. In one embodiment, decoupling capacitors are connected to the integrated circuit from the underside of the substrate on which the integrated circuit die is manufactured. The decoupling capacitors are positioned with a higher concentration in the “hot spot” areas...

20060231951 - Electronic devices including offset conductive bumps: Bumping a substrate having a metal layer thereon may include forming a barrier layer on the substrate including the metal layer and forming a conductive bump on the barrier layer. Moreover, the barrier layer may be between the conductive bump and the substrate, and the conductive bump may be laterally...

20060231948 - Integrated circuit system for bonding: An integrated circuit system provides a precursor for an integrated wire bond and flip chip structure. The precursor has a plurality of contact pads thereon. A layer of titanium is deposited on the precursor. A layer of nickel-vanadium is deposited on the layer of titanium. A layer of copper is...

20060231949 - Semiconductor module and method of forming a semiconductor module: In one embodiment, a semiconductor module includes at least one semiconductor chip package, a board having functional pads and dummy pads, and at least one solder joint electrically connecting the semiconductor chip package and one of the functional pads of the board. Furthermore, at least one supporting solder bump is...

20060231950 - Semiconductor package accomplishing fan-out structure through wire bonding: Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while...

20060231952 - Bga semiconductor chip package and mounting structure thereof: In example embodiments of the present invention, a structure of a BGA semiconductor chip package includes a substrate having first and second surfaces, a semiconductor chip having a plurality of bonding pads, and mounted on the first surface of the substrate, and plurality of in/out (I/O) solder balls and dummy...

20060231953 - Structure for mounting semiconductor part in which bump and land portion are hardly detached from each other and method of manufacturing mounting substrate used therein: There is provided a structure for mounting a semiconductor part having improved productivity, in which a bump is detached from a land portion and a method of manufacturing a mounting substrate used therein. The structure for mounting the semiconductor part includes a mounting substrate 1 having an insulating substrate 2...

20060231954 - Electric contact materials comprising organic heterojunction and device: This invention relates to electric contact materials comprising organic heterojunction for improving the contact of organic semiconductor and metal electrode. The electric contact materials comprising organic heterojunction are composed of electron-type organic semiconductors, hole-type organic semiconductors and heterojunctions made thereof. The invention further relates to the organic diode, organic FET...

20060231955 - Conductive line end extension: Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a first conductive feature of an interconnect structure is extended by a first distance, and an end of a second conductive feature of the interconnect structure...

20060231956 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a first insulating film having a plurality of wiring trenches formed at predetermined intervals in an upper part, the first insulating film having an upper surface, a second insulating film formed on the upper surface of the first insulating film so as to be located between...

20060231957 - Transistor, display device including the same, and manufacturing method thereof: A transistor includes a wire formed on a substrate, the wire comprising a semiconductor core, a first cover enclosing a portion of the semiconductor core, and a second cover enclosing the first cover, a first electrode formed on the second cover of the wire, an insulating layer formed on the...

20060231958 - Fan out type wafer level package structure and method of the same: To pick and place standard dice on a new base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type wafer level...

20060231959 - Bonding pad for a packaged integrated circuit: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. Vias in the package substrate provide electrical connection between the top and bottom sides. The vias have a via...

20060231960 - Non-cavity semiconductor packages: Non-cavity semiconductor packages. One embodiment of the packages includes a non-cavity substrate, a first die, an encapsulant, and a second die. The non-cavity substrate comprises a first surface and an opposite second surface. The first surface comprises an external terminal thereon. The first die is attached and wire-bonded to the...

20060231961 - Semiconductor device and radiation detector employing it: A wiring substrate 20, comprising a glass substrate, which is provided with through holes 20c, each having a tapered part 20d that becomes large in opening area at the side of an input surface 20a, and conductive members 21, formed on the inner walls of through holes 20c, is used....

20060226410 - Heating phase change material: A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another along a substantial portion of their lateral extent. An opening may be provided in the intervening dielectric to allow the phase change layers to...

20060226411 - Multi-bit memory device having resistive material layers as storage node and methods of manufacturing and operating the same: Provided are a multi-bit memory device having resistive material layers as a storage node, and methods of manufacturing and operating the same. The memory device includes a substrate, a transistor formed on the substrate, and a storage node coupled to the transistor, wherein the storage node includes: a lower electrode...

20060226409 - Structure for confining the switching current in phase memory (pcm) cells: Disclosed are a phase change memory cell and a method of forming the memory cell. The memory cell comprises a main body of phase change material connected directly to a bottom contact and via a narrow channel of phase change material to a top contact. The channel is tapered from...

20060226413 - Composite substrates of conductive and insulating or semi-insulating group iii-nitrides for group iii-nitride devices: Group III-Nitride semiconductor device structures and methods of fabricating Group III-Nitride structures are provided that include an electrically conductive Group III-Nitride substrate, such as a GaN substrate, and a semi-insulating or insulating Group III-Nitride epitaxial layer, such as a GaN epitaxial layer, on the electrically conductive Group III-Nitride substrate. The...

20060226414 - Group iii-v nitride-based semiconductor substrate and method of making same: A method of making a group III-V nitride-based semiconductor substrate has the steps of: providing a first crystal substrate; placing the first crystal substrate on a susceptor; holding down the first crystal substrate on the susceptor; and growing a first group III-V nitride-based semiconductor crystal on the first crystal substrate....

20060226415 - Semiconductor integrated circuit device and vehicle-mounted radar system using the same: A semiconductor integrated circuit device includes a HFET formed on part of a substrate made of sapphire and including a Group III-V nitride semiconductor layer, a dielectric film formed on the substrate to cover the top and side surfaces and upper corners of the Group III-V nitride semiconductor layer, a...

20060226412 - Thick semi-insulating or insulating epitaxial gallium nitride layers and devices incorporating same: Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures...

20060226416 - Nitride semiconductor device: The invention relates to a nitride semiconductor device having electron-emitting. In the device, an n-type nitride semiconductor layer is formed over a substrate, and an active layer is formed over the n-type nitride semiconductor layer. Also, a p-type nitride semiconductor layer is formed on the active layer. The active layer...

20060226417 - Photodetector: A photodetector is described. The photodetector is comprised of a substrate, a first n-type III-V compound semiconductor layer located on the substrate, an n++-type III-V compound semiconductor layer located on a first portion of the first n-type III-V compound semiconductor layer with a second portion of the first n-type III-V...

20060226418 - Method and system for binary signaling via quantum non-locality: A method of, and system for, binary signalling via quantum non-locality. The method and system are particularly suitable for rapid communication including superluminal signalling. The method and system use an ensemble of quantum-systems in which the quantum-systems are in pairs, with one quantum-system of each pair being in quantum entanglement...

20060226421 - Amine compound and uses thereof: The objectives of this invention are to extend the range of choosing materials to use in the preparation of photopolymerizable compositions by providing a novel organic compound which absorbs a visible light; or to provide an organic material which is useful as host compound in organic electroluminescent devices, as well...

20060226422 - Electroluminescent device: Disclosed is an organic electroluminescent display, comprising a first active electrode region and a first dummy electrode region, the first dummy electrode region electrically isolated from the first active electrode region. Further disclosed is an organic electroluminescent display, comprising a first active electrode region, a first dummy electrode region, and...

20060226419 - Encapsulation for an organic electronics component and production method therefor: The invention relates to an encapsulation for an organic electronics component, particularly an OLED, which can be produced by simple coating methods or printing methods and which still has a high degree of tightness with regard to environmental influences that are detrimental to the organic electronics component. This is made...

20060226420 - Organic thin-film transistor and process for fabricating the same, active matrix type display employing it and radio identification tag: An organic thin film transistor of the present invention includes a substrate (11) and a semiconductor layer (14) made of an organic semiconductor and formed on the substrate (11). The semiconductor layer (14) is composed of crystals of the organic semiconductor, and a crystal phase of the crystals is the...

20060226423 - Electro-optical device, manufacturing method thereof, and electronic apparatus: An electro-optical device having a pixel-switching thin film transistor disposed below the data lines on a substrate and a storage capacitor with a stacked structure of a high-potential electrode, a dielectric layer, and pixel-potential electrode that is disposed in an area including a region opposed to a channel region of...

20060226427 - Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus: An electro-optical device including a substrate, data lines and scanning lines, thin film transistors being disposed below the data lines and above the substrate. Storage capacitors are disposed over the data lines in a region opposite to the channel region of the thin film transistors in plan view. Each storage...

20060226426 - Liquid crystal display device: An LCD device according to the present invention includes having first and second substrates facing each other, whereby crossing gate and data lines are formed on the first substrate to define a pixel region. A thin film transistor is provided that includes a gate electrode protruding from the gate line,...

20060226424 - Thin film transistor and method of fabricating the same: A thin film transistor includes: a silicon nanowire on a substrate, the silicon nanowire having a central portion and both side portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode spaced apart from the source electrode on the both...

20060226425 - Thin film transistor and method of fabricating the same: A thin film transistor includes a multi-coaxial silicon nanowire unit including a plurality of coaxial silicon nanowires on a substrate, the multi-coaxial silicon nanowire unit including a central portion and end portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain...

20060226428 - Vertical gate device for an image sensor and method of forming the same: A CMOS pixel cell having a charge transfer transistor adjacent the photo-conversion device. The transistor has a channel region surrounded by a gate and an upper source/drain region over the channel region....

20060226429 - Method and apparatus for directional organic light emitting diodes: The directionality of organic light emitting diodes is improved by the introduction of a patterned metal electrode as either the anode or the cathode....

20060226430 - Electro-optical device and manufacturing method thereof: An electro-optical device having high operation performance and reliability, and a manufacturing method thereof A TFT structure which is strong agains hot carrier injection is realized by disposing a Lov region 207 in an n-channel TFT 203 which forms a driver circuit. Further, Loff regions 217 to 220 and offset...

20060226431 - Light-emitting device and method of manufacturing the same: Provided is a light-emitting device and a method of manufacturing the same. The light-emitting device includes a substrate having at least one protruded portion with a curved surface in which a consistent defect density and uniform stress distribution can be obtained even when the growth of the semiconductor crystal layer...

20060226432 - Semiconductor integrated device: To improve reliability in controlling an output of a semiconductor laser. There are provided a prism adhered to the semiconductor substrate, and having a light reflection surface formed with a light reflection film for reflecting a laser beam emitted from the semiconductor laser and a light transmission surface for transmitting...

20060226433 - Strobe light control circuit and igbt device: As external connection terminals for an emitter electrode (12) of an IGBT chip, a first emitter terminal (151) for electrically connecting a light emitter in a strobe light control circuit to the emitter electrode (12) and a second emitter terminal (152) for connecting a drive circuit for driving an IGBT...

20060226434 - Nitride-based semiconductor light emitting device and manufacturing method thereof: A present nitride-based semiconductor light emitting device includes: a pattern surface formed on a conductive substrate; a multilayered metal layer formed on the pattern surface; and a multilayered semiconductor layer formed on the multilayered metal layer, and characterized in that main surfaces of the multilayered metal layer and the multilayered...

20060226435 - Compact light emitting device package with enhanced heat dissipation and method for making the package: A light emitting device package and method for making the package utilizes a first leadframe having a first surface and a second leadframe having a second surface that are relatively positioned such that the second surface is at a higher level than the first surface. The light emitting device package...

20060226436 - Lens assembly for sideward light emission: A lens assembly for sideward light emission includes a lens and a lens cap. The lens has a cup portion, an open end portion, and first and second refracting portions. The cup portion surrounds a light source. The open end portion defines an opening. The first refracting portion interconnects the...

20060226437 - Light-emitting diode: A light-emitting diode includes a substrate having a main surface, a light-emitting diode device arranged on the main surface, a translucent sealing resin portion sealing the light-emitting diode device so that the light-emitting diode device is implemented as an independent convex portion projecting from the main surface, and a reflector...

20060226438 - Solid-state imaging device: A solid-state imaging device including an n-type semiconductor substrate including a photoelectric conversion portion, and a signal detection portion for detecting a signal charge is used. The photoelectric conversion portion is provided with a photodiode, and a p-well that overlaps the photoelectric conversion portion and the signal detection portion when...

20060226439 - Bi-directional transistor and method therefor: In one embodiment, a transistor is formed to conduct current in both directions through the transistor....

20060226440 - Use of deep-level transitions in semiconductor devices: The invention relates to the design, fabrication, and use of semiconductor devices that employ deep-level transitions (i.e., deep-level-to-conduction-band, deep-level-to-valence-band, or deep-level-to-deep-level) to achieve useful results. A principal aspect of the invention involves devices in which electrical transport occurs through a band of deep-level states and just the conduction band (or...

20060226441 - Thin film transistor including organic semiconductor layer and substrate including the same: Provided is a thin film transistor including a gate electrode on a substrate; a gate insulating layer on the gate electrode; source and drain electrodes including first source and drain layers on the gate insulating layer, respectively, and spaced apart from each other, wherein at lease one of the first...

20060226442 - Gan-based high electron mobility transistor and method for making the same: A high electron mobility transistor including: a GaN material system based heterostructure; a passivating nitride layer over the heterostructure and defining a plurality of openings; and a plurality of electrical contacts for the heterostructure and formed through the openings....

20060226443 - High-performance fet devices and methods: An epitaxially layered structure with gate voltage bias supply circuit element for improvement in performance for semiconductor field effect transistor (FET) devices utilizes a structure comprised of a substrate, a first layer semiconductor film of either an n-type or a p-type grown epitaxially on the substrate, with the possibility of...

20060226446 - Bipolar transistor and method for fabricating the same: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base...

20060226445 - Silicon optoelectronic device, manufacturing method thereof, and image input and/or output apparatus using the same: A method of manufacturing a silicon optoelectronic device, a silicon optoelectronic device manufactured by the method, and an image input and/or output apparatus having the silicon optoelectronic device are provided. The method includes: preparing an n-type or p-type silicon-based substrate; forming a polysilicon in one or more regions of the...

20060226444 - Transistor device and method: A method for making a heterojunction bipolar transistor includes the following steps: forming a heterojunction bipolar transistor by depositing, on a substrate, subcollector, collector, base, and emitter regions of semiconductor material; the step of depositing the subcollector region including depositing a material composition transition from a relatively larger bandgap material...

20060226447 - Semiconductor integrated circuit and wafer having diffusion regions differing in thickness and method for manufacturing the same: A semiconductor integrated circuit includes a rectangular low speed circuit area including a low speed circuit comprising a low speed transistor having a first source extension region and a first drain extension region, and a rectangular high speed circuit area adjacent to the low speed circuit area and including a...

20060226448 - Method of fabricating semiconductor device and semiconductor device fabricated thereby: A method includes preparing a semiconductor substrate having a cell region, a core NMOS region, and a core PMOS region; defining a cell active region, an NMOS active region, and a PMOS active region in the cell region, the core NMOS region, and the core PMOS region, respectively, by forming...

20060226449 - Semiconductor integrated circuit device with reduced leakage current: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low...

20060226450 - Connecting member used for semiconductor device including plurality of arranged semiconductor modules and semiconductor device provided with the same: A connector includes a fitting hole into which a signal line is fitted, a tapered portion formed to lead a tip portion of the signal line to the fitting hole, and a bonded portion for bonding the connector to a control substrate. The tapered portion has a tapered shape on...

20060226451 - Power semiconductor device and method therefor: A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a...

20060226452 - Solid-state image pickup device and the manufacture method thereof: A solid-state image pickup device includes: a photoelectric conversion section formed on one face of a silicon substrate, a seal member for sealing the photoelectric conversion section, and an electrode for sending and receiving an electric signal, wherein the seal member comprises an image pickup lens section for causing the...

20060226455 - Integrated circuit devices having buried insulation layers and methods of forming the same: An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least...

20060226453 - Methods of forming stress enhanced pmos structures: Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a gate structure disposed on a substrate comprising at least one recess, wherein a channel region is in a <110> direction, and then forming a compressive layer in the at least one recess....

20060226454 - Semiconductor device: A semiconductor device 1 according to the present invention includes a semiconductor substrate 5, a first transistor 10 which is formed on the semiconductor substrate 5 and includes a first gate electrode portion 16 constituted by a first gate insulating film 24 and a first gate electrode 26 having a...

20060226456 - Pixel sensor cell having reduced pinning layer barrier potential and method thereof: A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced....

20060226457 - Ferroelectric memory device and method of manufacture of same: A ferroelectric memory device has a lower insulating film (first insulating film) formed on a semiconductor substrate. A ferroelectric capacitor structure is formed on the lower insulating film. The ferroelectric capacitor structure is created by layering in order a lower electrode, ferroelectric layer and upper electrode. The ferroelectric memory device...

20060226458 - Magnetic memory having synthetic antiferromagnetic pinned layer: A magnetic memory element includes a sense structure, a tunnel barrier adjacent the sense structure, and a synthetic antiferromagnet (SAF) adjacent the tunnel barrier on a side opposite the sense structure. The SAF includes an antiferromagnetic structure adjacent a ferromagnetic seed layer. The ferromagnetic seed layer provides a texture so...

20060226460 - High density integrated read-only memory (rom) with reduced access time: An integrated circuit memory of the read-only memory type includes at least one memory cell. Each memory cell includes a storage transistor realized in a semiconductor substrate and presenting a source connected to a reference potential, a gate connected to an electrically conductive word line, and a drain connected to...

20060226459 - Layout structure in semiconductor memory device and layout method therefor: A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word...

20060226461 - Semiconductor device and semiconductor device manufacturing method: A semiconductor technique is provided which can achieve both of lowered resistance in a logic formation region and reduced leakage current of the capacitor of a memory device. Source/drain regions (4) are formed in the upper surface of a semiconductor substrate (1) in a memory formation region and cobalt silicide...

20060226462 - Semiconductor device having a compensation capacitor in a mesh structure: The compensation capacitor includes: a charge accumulating element having a diffusion layer, a dielectric layer, and a gate electrode layer, wherein the gate electrode layer, the dielectric layer, and the diffusion layer are stacked in this order, and at least partially overlap with each other when viewed from a direction...

20060226463 - Merged mos-bipolar capacitor memory cell: A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-polar transistor having an emitter region, a base region and...

20060226465 - Concentric or nested container capacitor structure for integrated circuits: Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the...

20060226464 - High voltage gain topology for analog circuits in short channel technologies: A stacked MOS configuration for use in short channel length analog circuit technologies is provided. The stacked MOS configuration comprises a plurality of short-channel MOS transistors coupled in series and sharing a common gate terminal. In an embodiment, a first peripheral transistor provides a drain terminal for the stacked MOS...

20060226471 - Flash memory cells with reduced distances between cell elements: An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching process could include CF4...

20060226466 - Non-volatile semiconductor memory element and corresponding production and operation method: The invention relates to a nonvolatile semiconductor storage element and an associated production and control method, comprising a semiconductor substrate (1) in which a source region (S), a drain region (D) and an intermediate channel region are formed. On a first part section (I) of the channel region, a control...

20060226467 - P-channel charge trapping memory device with sub-gate: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first inversion region, a second inversion region, and a channel region between the first inversion region and the second inversion region. The semiconductor device further includes a control gate over the channel region and at least one sub-gate...

20060226470 - Semiconductor device having metal gate patterns and related method of manufacture: A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises a first gate insulation layer...

20060226469 - Semiconductor device with integrated flash memory and peripheral circuit and its manufacture method: A non-volatile semiconductor memory device includes: a non-volatile memory area including gate electrodes, each including stack of a floating gate, an inter-electrode insulating film and a control gate, and having first insulating side walls formed on side walls of the gate electrode; a peripheral circuit area including single-layer gate electrodes...

20060226468 - Split gate multi-bit memory cell: A multi-bit memory cell (200) with a control gate (220) for controlling a middle portion of a channel region (208) provides improved operation including faster programming at smaller voltages and currents. The memory cell (200) includes a source (204) and a drain (206) diffused into a substrate (202) forming a...

20060226472 - Cell region layout of semiconductor device and method of forming contact pad using the same: A cell region layout of a semiconductor device formed by adding active regions in the outermost portion of a cell region, and a method of forming a contact pad using the same are provided. The layout and the method include a first active region formed at the outermost portion of...

20060226473 - Gate electrode stack and use of a gate electrode stack: A gate electrode stack is disposed on a substrate in a semiconductor device. A gate conductor includes at least one layer of polysilicon and at least one layer of poly-Si1−x,Gex material. The invention is also concerned with a process. This structure can be etched effectively since an end point detection...

20060226474 - Structure and method of fabricating high-density, trench-based non-volatile random access sonos memory cells for soc applications: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to...

20060226475 - Vertical field effect transistor: A MOSFET has a base layer and a source layer in a cell surrounded by a trench gate formed in a semiconductor substrate. A trench contact is formed through the source layer and the base layer. The gate is polygonal such as square. The trench contact is thin and linear...

20060226476 - Sige nickel barrier structure employed in a cmos device to prevent excess diffusion of nickel used in the silicide material: A CMOS device such as an NFET or a PFET and a method of forming a CMOS device are provided. The method begins by forming at least one patterned gate region atop a first semiconductor layer that includes silicon. Dielectric spacers are formed about exposed portions of the patterned gate...

20060226478 - Semiconductor device having a lateral channel and contacts on opposing surfaces thereof: A semiconductor device having a lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a lateral...

20060226479 - Semiconductor device having field stabilization film and method: In one embodiment, a high voltage semiconductor device is formed with a first dielectric layer and a charge stabilization layer comprising a flowable glass formed over the first dielectric layer....

20060226477 - Substrate driven field-effect transistor: A substrate driven field effect transistor (FET) and a method of forming the same. In one embodiment, the substrate driven FET includes a substrate having a source contact covering a substantial portion of a bottom surface thereof and a lateral channel above the substrate. The substrate driven FET also includes...

20060226480 - Method for fabricating oxygen-implanted silicon on insulation type semiconductor and semiconductor formed therefrom: The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation (“SOI”) type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be...

20060226483 - Method of fabricating strained channel devices: A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon...

20060226482 - Methods of fabricating silicon nitride regions in silicon carbide and resulting structures: A method is disclosed for fabricating a silicon nitride regions in silicon carbide. The method includes the steps of implanting a sufficient dose and energy of nitrogen ions into a silicon carbide substrate maintained at a temperature above about 350° C. to produce an as-implanted layer of a silicon nitride...

20060226485 - Semiconductor device: A semiconductor element is configured to prevent deterioration thereof due to an electrical charge occurring at a top surface/bottom surface of a support substrate during a plasma process in manufacturing a semiconductor device using an SOI substrate. The semiconductor device includes a MOS transistor formed on an SOI layer of...

20060226486 - Semiconductor device: The present invention provides a semiconductor device which has a substrate formed as a rigid body, stress relaxation layers formed by filling in concave portions defined in a first main surface of the substrate, and a device forming layer which covers part of the first main surface and is formed...

20060226481 - Simplified vertical array device dram/edram integration: method and structure: The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active...

20060226484 - Thin film transistor: A thin film transistor (TFT) is disclosed, and the thin film transistor comprises: a substrate, a gate electrode, a first adhesion layer, a gate insulting layer, a semiconductor layer, and a source electrode and a drain electrode. The gate electrode is formed on the substrate, and the gate electrode is...

20060226487 - Resistor with reduced leakage: A resistor 100 is formed in a semiconductor layer 106, e.g., a silicon layer on an SOI substrate. A body region 108 is formed in a portion of the semiconductor layer 106 and is doped to a first conductivity type (e.g., n-type or p-type). A first contact region 110, which...

20060226488 - Lateral bipolar transistor with additional esd implant: A semiconductor device (10) includes a semiconductor body (12) of a first conductivity type (e.g., p-type). A first doped region (14) of a second conductivity type (e.g., n-type) is disposed at an upper surface of the semiconductor body (12). A second doped region (16) of the second conductivity type is...

20060226490 - Interlayer dielectric under stress for an integrated circuit: An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD...

20060226489 - System and methods for retention-enhanced programmable shared gate logic circuit: Retention-enhanced, programmable, shared floating gate logic circuits are employed as NVM cells. In one embodiment, the NVM cell is formed by a dual transistor logic gate circuit with a shared floating gate. The logic circuit is an inverter. The shared floating gate is doped partially or completely with p-type impurities...

20060226493 - High performance pfet header in hybrid orientation technology for leakage reduction in digital cmos vlsi designs: Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various gate- and body-biased schemes in HOT technology to significantly reduce the performance...

20060226491 - Inverted multilayer semiconductor device assembly: An apparatus and method for an inverted multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device may be different than the active region of at least another device. Where the multilayer SOI device has...

20060226492 - Semiconductor device featuring an arched structure strained semiconductor layer: A semiconductor device includes a mechanically strained channel, wherein the channel comprises of a single crystalline structure of a strained semiconductor layer having a non-linear geometry, the non-linear geometry including a portion of an arch shape. The semiconductor device further includes a dielectric layer, wherein a first portion of the...

20060226494 - Tungsten plug drain extension: A power metal-oxide-semiconductor field effect transistor (MOSFET) cell includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A voltage sustaining layer is formed on the semiconductor substrate. A highly doped active zone of a second conductivity type is formed in the voltage sustaining layer opposite the...

20060226495 - Structure and method of three dimensional hybrid orientation technology: A method and device for increasing pFET performance without degradation of nFET performance. The method includes forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direction. In use, the device includes a nFET...

20060226496 - Concentric or nested container capacitor structure for integrated circuits: Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the...

20060226497 - Vertical nanotransistor, method for producing the same and memory assembly: A vertical nano-transistor having a source contact, a drain contact, a gate region and a semiconductor cylindrical channel region between the source contact and the drain contact, the cylindrical channel region being embedded in a flexible insulating substrate and in the upper section of the channel region, in such a...

20060226498 - Power semiconductor device and method therefor: A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a...

20060226499 - Semiconductor device incorporating protective diode with stable esd protection capabilities: A semiconductor device provided with stable ESD protection capabilities, incorporating a transistor and a protective diode to form a power control IC. The semiconductor device includes a semiconductor substrate of a first conductivity type; a well region of a second conductivity type, formed in the semiconductor substrate; the transistor formed...

20060226500 - Gate dielectric layer and method of forming the same: A method of forming a gate dielectric is described. A plasma treatment process is performed to form a dielectric structure on a substrate, wherein the dielectric structure having a graded dielectric constant value that decreases gradually in a direction toward the substrate....

20060226501 - Collapsing zipper varactor with inter-digit actuation electrodes for tunable filters: According to one embodiment a microelectromechanical (MEMS) switch is disclosed. The MEMS switch includes a substrate, a plurality of actuation electrodes mounted on the substrate, a plurality of bottom electrodes mounted on the substrate, a capacitor having subcomponents mounted on the two or more bottom electrodes and a top bendable...

20060226502 - Microelectromechanical systems (mems) device including a superlattice: A microelectromechanical system (MEMS) device may include a substrate and at least one movable member supported by the substrate. The at least one movable member may include a superlattice including a plurality of stacked groups of layers with each group of layers of the superlattice comprising a plurality of stacked...

20060226503 - Isolation trench geometry for image sensors: A pixel cell including a substrate having a top surface. A photo-conversion device is at a surface of the substrate and a trench is in the substrate adjacent the photo-conversion device. The trench has sidewalls and a bottom. At least one sidewall is angled less than approximately 85 degrees from...

20060226504 - High-breakdown-voltage semiconductor device: A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent ones of the trenches and having an impurity concentration higher than that of the semiconductor...

20060226505 - Nonvolatile memory devices and methods of fabricating the same: Nonvolatile memory devices and methods of fabricating the same are provided. A semiconductor substrate is provided having a cell field region and a high-voltage field region. Device isolation films are provided on the substrate. The device isolation films define active regions of the substrate. A cell gate-insulation film and a...

20060226506 - Trench isolation structure and method of formation: In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a bottom portion and first and second trench sidewalls. At least...

20060226507 - Fuse structure having a tortuous metal fuse line: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area....

20060226508 - Semiconductor device having patterns for protecting fuses and method of fabricating the semiconductor device: A semiconductor device having patterns for protecting fuses is provided. The semiconductor device comprises a plurality of fuses formed on a semiconductor substrate, and a pattern covering a region of the semiconductor device where the fuses are not to be cut. The patterns formed on the semiconductor device protect the...

20060226509 - Antifuse element and electrically redundant antifuse array for controlled rupture location: An antifuse element (102) having end corners (120, 122) of a gate electrode (104) positioned directly above an active area (106) or bottom electrode. The minimum programming voltage between the gate electrode (104) and the active area (106) creates a current path through an insulating layer (110) positioned therebetween. The...

20060226510 - Integrated circuit transformer devices for on-chip millimeter-wave applications: Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit transformer devices have universal and scalable architectures that can be used as templates or building blocks for constructing various types of on-chip devices for millimeter-wave applications....

20060226511 - Miniature inductor suitable for integrated circuits: A miniature inductor suitable for integrated circuits comprises a semiconductor substrate having a coplanar strip line and a plurality of metal-insulator-metal (MIM) capacitors, wherein the plurality of MIM capacitors are connected between the transmission lines of the coplanar strip line in parallel, and the coplanar strip line connected with the...

20060226512 - Integrated circuit comprising a substrate and a resistor: An integrated circuit includes a substrate and a resistor. The resistor is formed from at least two access wells of a first conductivity type and a deep buried layer electrically connecting the wells. The deep buried layer is at least partly covered by a region of opposite conductivity....

20060226513 - Elimination of low frequency oscillations in semiconductor circuitry: Low frequency oscillations in a circuit are eliminated. A sub-collector region is formed over a semi-insulator region. Bipolar transistor circuitry is formed over the sub-collector region. The bipolar transistor circuitry includes a collector. Voltage at the semi-insulator region is controlled so that voltage at the semi-insulator region is approximately equal...

20060226514 - Semiconductor epitaxial wafer: Multiple epitaxial layers are grown on the front side of a p silicon substrate and no layers are grown on the other side. Among the multiple epitaxial layers the one in contact with the silicon substrate is a first p+ epitaxial layer. Since the epitaxial layer is in contact with...

20060226515 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions to be adjacent to said gate electrode; and an Al wiring through an interlayer insulating film covering said gate electrode, wherein impurity ions are implanted into a surface of said semiconductor substrate...

20060226516 - Silicon-doped carbon dielectrics: A silicone-doped carbon interlayer dielectric (ILD) and its method of formation are disclosed. The ILD's dielectric constant and/or its mechanical strength can be tailored by varying the ratio of carbon-to-silicon in the silicon-doped carbon matrix....

20060226517 - Gas barrier film, substrate film, and organis electroluminescence device: A gas barrier film comprising a gas barrier laminate on a substrate film, wherein the gas barrier laminate comprises at least one three-layer unit consisting of a silicon nitride layer, a silicon oxynitride layer adjacent to the silicon nitride layer, and a silicon nitride layer adjacent to the silicon oxynitride...

20060226519 - Method and system for increasing tensile stress in a thin film using collimated electromagnetic radiation: A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed...

20060226518 - Method and system for increasing tensile stress in a thin film using multi-frequency electromagnetic radiation: A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed...

20060226520 - Method of manufacturing stack-type semiconductor device and method of manufacturing stack-type electronic component: A first semiconductor element is bonded on a substrate. A complex film formed of integrated dicing film and adhesive film is affixed on a rear surface of a semiconductor wafer which is to be second semiconductor elements, the dicing film having a thickness within a range of not less than...

20060226521 - Semiconductor package having integrated metal parts for thermal enhancement: A semiconductor device comprising a metallic leadframe (103) with a first surface (103a) and a second surface (103b). The leadframe includes a chip pad (104) and a plurality of segments (107); the chip pad is held by a plurality of straps (105), wherein each strap has a groove (106). A...

20060226522 - Full fault tolerant architecture for organic electronic devices: An organic device package that provides full fault tolerance against both electrical shorts and electrical opens is presented. An organic device package comprising a plurality of groups of organic electronic elements electrically coupled in series, where at least one of the plurality of groups of organic electronic elements comprises a...

20060226524 - Micro-device packaging: In one embodiment, a package for a micro-device includes a substrate, a transparent material covering the substrate, and a bond ring bonding the transparent material to the substrate. The bond ring comprises a silicon oxide layer on one of the substrate or the transparent material bonded to a silicon layer...

20060226523 - Organic electronic devices having external barrier layer: An organic device package includes a flexible substrate having a topside and a bottom side. Further, the organic device package includes an organic electronic device having a first side and a second side disposed on the topside of the flexible substrate. In addition, the organic device package includes a first...

20060226525 - Area mount type semiconductor device, and die bonding resin composition and encapsulating resin composition used for the same: An area mount type semiconductor device having high reliability when a semiconductor element is mounted on a surface with the use of a lead-free solder, and a die bonding resin composition and encapsulating resin composition used for the area mount type semiconductor device attainable by an area mount type semiconductor...

20060226526 - Microcontroller internal data capture and display: Capture and monitoring of critical data from a microcontroller is performed without halting or changing normal program execution therein. Data is captured according to stored program addresses that may run in the background during operation of the microcontroller. When an address match occurs data may thereby be captured. The captured...

20060226528 - Multipackage module having stacked packages with asymmetrically arranged die and molding: Semiconductor chip packages have die asymmetrically arranged on the respective substrates. Two such packages having complementary arrangements can be stacked, one inverted with respect to the other, such that the two die are situated side-by-side in the space between the two substrates. Also, multipackage modules include stacked packages, each having...

20060226527 - Semiconductor device and method of manufacturing semiconductor device: The present invention provides a semiconductor device that is inexpensive and can suppress signal transmission delay, and a manufacturing method thereof. The semiconductor device includes: a plurality of semiconductor chips; a semiconductor substrate that has, on the same surface thereof, a chip-to-chip interconnection for electrically connecting the plurality of semiconductor...

20060226529 - Semiconductor device, method for manufacturing the semiconductor device and semiconductor substrate: The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted...

20060226530 - Advanced standard cell power connection: A method for establishing standard cell power connections is disclosed. The method generally includes the steps of (A) calculating a power consumption of a plurality of logic cells receiving power directly from a power rail, (B) removing at least one excess via from a plurality of vias directly connecting the...

20060226531 - Power semiconductor module: A semiconductor power module has a support (1), whereon are formed conductor strips (5, 6, 7, 8) by applying a structure on an electrically conductive layer (3) applied on one side (2) of the support. A semiconductor power module can be manufactured easily and economically enabling several mounting technologies by...

20060226532 - Semiconductor device: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface...

20060226535 - Reinforced bond pad for a semiconductor device: Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe region 212 from...

20060226534 - Structure and assembly method of integrated circuit package: A packaging structure and an assembly method are disclosed. A packaging structure includes a substrate, a die, conductive wires, and conductively filled material. The substrate includes a conductive structure, and the conductive wires are insulator-coated. The die is mounted on the substrate, and the conductive wires are connected between the...

20060226533 - Via connection structure with a compensative area on the reference plane: The invention discloses a via connection structure with compensative area on a reference plane. The substrate has several conductive layers isolated by the insulation layers. When two conductive lines formed on different conductive layers where a reference plane is sandwiched in, these two conductive lines are not electrical connected because...

20060226536 - Semiconductor multipackage module including tape substrate land grid array package stacked over ball grid array package: A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces...

20060226537 - Multilayer circuit board and method of manufacturing the same: A multilayer circuit board is provided that includes at least two insulating layers each sandwiched by circuit layers, thus having at least one internal circuit layer sandwiched by the at least two insulating layers. Via holes are formed in one or more of the insulating layers at the same pitch...

20060226538 - Interposer and semiconductor device employing same, and method for manufacturing semiconductor device: Bending generated in a side of a device mounting surface of an organic resin substrate after an assembly process for a semiconductor device is inhibited, thereby providing an improved production yield. A semiconductor device 100 is formed by solder-joining a semiconductor chip 105 onto a device mounting surface 111 of...

20060226540 - Chip package: A chip package including a heat spreader, a circuit substrate, locating structures, a chip, wires, and an encapsulating compound is provided. The heat spreader has a bonding surface, and the circuit substrate is disposed on the bonding surface of the heat spreader. The circuit substrate has an opening, which exposes...

20060226541 - Electroosmotic pumps using porous frits for cooling integrated circuit stacks: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be...

20060226539 - Integrated circuit coolant microchannel assembly with targeted channel configuration: A microchannel structure has microchannels formed therein. The microchannels are to transport a coolant and to be proximate to an integrated circuit to transfer heat from the integrated circuit to the coolant. At least one of the microchannels has a length extent and has a first section at a first...

20060226543 - Ball grid array package stack: Disclosed herein is a ball grid array (BGA) package stack that is not limited by ball arrangement because it utilizes a foldable circuit substrate, which permits interconnection between upper and lower individual BGA packages. The foldable circuit substrate has three portions. By bending the middle second portion, the foldable circuit...

20060226542 - Semiconductor device and fabrication method thereof: A semiconductor device and a fabrication method thereof are proposed. A first dielectric layer is formed on a semiconductor substrate having at least one bond pad, wherein the first dielectric layer has a first opening for exposing the bond pad and a second opening at a predetermined position for redistribution....

20060226544 - Semiconductor package substrate having contact pad protective layer formed thereon and method for fabricating the same: A semiconductor package substrate and a method for fabricating the same are proposed. An insulating layer has a plurality of blind vias to expose inner traces underneath the insulating layer. A conductive film is formed on the insulating layer and over the bind vias. A first resist is formed on...

20060226545 - Semiconductor device: A semiconductor device includes: a semiconductor substrate having a semiconductor element; an electrode pad electrically connected to the semiconductor element; an insulating layer formed on the substrate, the insulating layer having an opening extended to the electrode pad; a wiring portion electrically connected to the electrode pad via the opening,...

20060226546 - Alloy material for semiconductors, semiconductor chip using the alloy material and production method of the same: According to the present invention, there is provided an alloy material for semiconductors containing of Au as a main component and Ag in the range of not less than 3 wt % to not more than 40 wt %....

20060226547 - Semiconductor chip capable of implementing wire bonding over active circuits: A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically...

20060226548 - Very low dielectric constant plasma-enhanced cvd films: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liable groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced...

20060226549 - Semiconductor device and fabricating method thereof: A semiconductor device and a fabrication method thereof. The semiconductor device has a substrate with a first conductive area, a dielectric layer formed of a low dielectric constant material disposed on the substrate, and a dielectric anti-reflective coating (DARC) layer disposed on the dielectric layer. A contact hole is disposed...

20060226550 - Molybdenum-based electrode with carbon nanotube growth: A carbon nanotube is formed on at least one Molybdenum-based electrode. In one embodiment, a carbon-nanotube device includes a pair of Molybdenum-based electrodes over respective terraces. Using a catalyst on the Molybdenum-based material of at least one electrode, a carbon nanotube is grown over a gap that separates the terraces...

20060226551 - Integrated circuit device and method of producing the same: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a...

20060226553 - Selective isotropic etch for titanium-based materials: A process for etching a sacrificial layer of a structure. The structure is exposed to a plasma derived from nitrogen trifluoride for etching the sacrificial layer. The process is selective in that it etches titanium-nitride and titanium but does not affect adjacent silicon dioxide or aluminum layers. Applications of the...

20060226555 - Semiconductor device and manufacturing method thereof: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties...

20060226554 - Semiconductor device with contact structure and manufacturing method thereof: A plurality of gate lines are formed on a substrate. After depositing a gate insulating layer, a semiconductor layer and a doped amorphous silicon layer are sequentially formed thereon. A lower insulating layer made of silicon nitride and an upper insulating layer made of a photosensitive organic material are deposited...

20060226552 - Semiconductor structure formed using a sacrificial structure: A method of forming a buried conductive structure in a semiconductor device includes the steps of forming a first insulating layer on a semiconductor layer; forming a sacrificial structure on at least a portion of the first insulating layer; forming a second insulating layer on at least a portion of...

20060226556 - Semiconductor device and method of manufacturing the same: The semiconductor device 1 includes interconnect layers 10, 20, an IC chip 30, via plugs 42, 44, a seal resin 50, and solder balls 60. The interconnect layer 10 includes a via plug 42. An end face of the via plug 42 on the side of the interconnect layer 20...

20060226557 - Semiconductor substrate with occurrence of slip suppressed and method of manufacturing the same: A semiconductor substrate includes a denuded zone that is formed on a surface where a semiconductor device is to be formed, and an oxygen precipitate layer that is formed on at least a part of a surface, which is opposite to the surface where the semiconductor device is to be...

20060226558 - Method of manufacturing a semiconductor device and semiconductor device: Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by patterning a resist film after the resist film...

20060226559 - Nitridation of sti liner oxide for modulating inverse width effects in semiconductor devices: A method (1300) of forming a semiconductor device comprising an isolation structure is disclosed, and includes forming a trench region within a semiconductor body (1308). Then, surfaces of the trench region are nitrided (1310) via a nitridation process. An oxidation process is performed that combines with the nitrided surfaces (1312)...

20060219994 - Structure for amorphous carbon based non-volatile memory: A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a second layer of amorphous carbon. The device also includes at least one first conductive layer common to the at least one first and the...

20060219995 - Electron emission device and electron emission display device using the same: An electron emission device includes a substrate; a cathode electrode formed on the substrate; a gate electrode crossing the cathode electrode and insulated from the cathode electrode; and an electron emission region electrically connected to the cathode electrode. The cathode electrode includes a main electrode with an inner opening portion,...

20060219998 - Gallium nitride-based compound semiconductor multilayer structure and production method thereof: The object of the present invention is to provide a gallium nitride-based compound semiconductor multilayer structure useful for manufacturing a gallium nitride-based compound semiconductor light-emitting device which requires a low operating voltage and from which a good emission output can be obtained. The present gallium nitride-based compound semiconductor multilayer structure...

20060219996 - Optical semiconductor device and fabrication method thereof: In order to prevent As/P replacement at the boundary face of a re-grown semiconductor layer and avoid a crystalline defect caused by the replacement, there is provided an optical semiconductor device comprising: a semiconductor substrate; a striped stacking body including a first semiconductor layer, an active layer, and a second...

20060219997 - Semiconductor device and fabrication method of the same: A semiconductor device includes a substrate, a SiC drift layer formed above the substrate, a GaN-based semiconductor layer that is formed on the SiC drift layer and includes a channel layer, a source electrode and a gate electrode formed on the GaN-based semiconductor layer, current blocking regions formed in portions...

20060219999 - Group iii-nitride light emitting device: The present invention provides a group III-nitride light emitting device improved in operating voltage and electrostatic discharge characteristics. The group III-nitride light emitting device comprises a lower n-type clad layer, a current spreading layer, an upper n-type clad layer, an active layer and an p-type clad layer formed in their...

20060220000 - Photon source: A photon source comprising a photon source body, said photon source body comprising at least one quantum dot; carrier injection means for injecting carriers into said at least one quantum dot and change of state means for changing the state of the carriers within the quantum dot after a predetermined...

20060220001 - Semiconductor device: A semiconductor device including quantum dots comprises a barrier layer of a semiconductor crystal having a first lattice constant and a quantum dot layer including a plurality of quantum dots of a semiconductor crystal having a second lattice constant formed on the barrier layer and a side barrier layer of...

20060220002 - Semiconductor laser having optical guide layer doped for decreasing resistance: In a semiconductor laser element: a lower cladding layer of a first conductivity type, a quantum-well active layer, an upper cladding layer of a second conductivity type, a contact layer of the second conductivity type, and a first electrode of the second conductivity type are formed in this order above...

20060220003 - Semiconductor device: A semiconductor device comprising a resistance element with a high resistance and high resistance accuracy and a non-volatile semiconductor storage element is rationally realized by comprising the non-volatile semiconductor storage element comprising a first isolation formed to isolate a first semiconductor area, a first insulator, and a first electrode in...

20060220007 - Acene compounds having a single terminal fused thiophene as semiconductor materials for thin film transistors and methods of making the same: A thin film transistor comprises a layer of organic semiconductor material comprising a comprising, in a thin film transistor, a thin film of organic semiconductor material that comprises an acene compound having a linear configuration of at least three fused benzene rings, which compound has, at one end only of...

20060220005 - Logic gate with a potential-free gate electrode for organic integrated circuits: The invention relates to an organic logic gate comprising at least one charging field effect transistor (charging FET) and at least one switching field effect transistor (switching FET), the charging FET having at least one gate electrode, a source electrode and a drain electrode, the gate electrode of the charging...

20060220004 - Metal complexes: The present invention relates to new types of metal complexes. Such compounds can be used as active components (=functional materials) in a series of different types of applications which can be classed within the electronics industry in the widest sense. The inventive compounds are described by the structure 1 and...

20060220008 - Method of fabricating electroluminescent display: A method for fabrication organic light emitting diode (OLED) displays. A white light OLED element is formed on the first substrate. A micro-cavity layer is formed on a second substrate. A color filter is formed on the micro-cavity layer. The first and the second substrates are assembled, wherein the light...

20060220006 - Molecular-doped transistor and sensor: Molecular-doped devices, including transistors and sensors, for nano-scale applications are provided. The device comprises a substrate, a source and a drain, both supported on the substrate and separated by a distance. The molecular-doped device further comprises a layer or wire of a semiconductor material formed on the substrate between the...

20060220011 - Organic electroluminescent device: The invention discloses an organic electroluminescent device having an anode, a cathode and a plurality of organic compound layers provided between the anode and the cathode and including a light-emitting layer, wherein the light-emitting layer contains two light-emitting materials including a phosphorescent light-emitting material, and a host material; and when...

20060220010 - Organic light emitting diode display: An organic light emitting diode display includes a substrate, an electroluminescence device fabricated on the lower surface of the substrate, a back plate, and a metal pattern formed on the surface of the back plate facing the substrate and contacted with the cathode of the electroluminescence device....

20060220009 - Tft having a fluorocarbon-containing layer: A thin film transistor composed of: (a) a semiconductor layer including a thiophene compound, wherein the thiophene compound comprises one or more substituted thiophene units, one or more unsubstituted thiophene units, and optionally one or more divalent linkages; (b) a gate dielectric; and (c) a layer contacting the gate dielectric...

20060220013 - Techniques for facilitating identification updates in an integrated circuit: An integrated circuit comprises an identification portion having an output representative of one or more bits of digital information identifying the integrated circuit. This identification information may, for example, allow the manufacturer to determine which photolithographic masks were used to manufacture the integrated circuit. The identification portion is formed at...

20060220012 - Test key having a chain circuit and a kelvin structure: A test key formed on a semiconductor substrate has a plurality of electronic components, a plurality of conductors, a plurality of vias for connecting the electronic components and the conductors, a first pad, a second pad, a third pad, and a fourth pad. The first pad, the electronic components, the...

20060220018 - Array substrate for in-plane switching liquid crystal display device and method of fabricating the same: A fabricating method of an array substrate for an in-plane switching liquid crystal display device includes: forming a gate line and a common line on a substrate, the common line spaced apart from the gate line; forming a data line crossing the gate line to define a pixel region; forming...

20060220016 - Light emitting display and method of manufacturing the same: A light emitting display includes a thin film transistor formed on a substrate, a first insulating layer deposited on the thin film transistor, and at least one organic light emitting diode for forming an image displaying part on the first insulating layer. At least one blocking part is adjacent to...

20060220019 - Liquid crystal display: A liquid crystal display including: a panel; a first electric field generating electrode formed on the panel; a second electric field generating electrode opposed to the first electric field generating electrode; a liquid crystal layer disposed between the first electric field generating electrode and the second electric field generating electrode;...

20060220014 - Liquid crystal display device and manufacturing method therefor: To provide a liquid crystal display device in which capacity value of storage capacitance is large and manufacturing cost is low, and a manufacturing method thereof. A plurality of gate lines is provided on a pixel circuit substrate of a liquid crystal display device. Further, a TFT is provided to...

20060220021 - Method of manufacturing a semiconductor device: There is provided a method of manufacturing a semiconductor device having a TFT with sufficient characteristics and little fluctuation by accurately controlling the addition amount of impurity ions to the semiconductor layer using an ion doping device. A semiconductor device having a TFT showing sufficient and stable characteristics may be...

20060220017 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate formed with a trench, an element isolation region formed by burying a first insulating film in the trench, an element forming area divided by the element isolation region on an area of a surface of the semiconductor substrate, a second insulating film formed...

20060220020 - Thin film transistor, flat panel display device, and method of fabricating the same: A thin film transistor, a flat panel display device including the same, and a method of fabricating the same. An uneven structure is formed at a part of a polycrystalline silicon layer pattern corresponding to a channel region to form a channel length at the edge of the channel region...

20060220015 - Thin film transistor, thin film transistor display panel, and manufacturing method thereof: A thin film transistor is provided. The thin film transistor includes a frame formed on a substrate and having a plurality of grooves, line-shaped semiconductors disposed in at least one of the grooves, a first electrode overlapping with the line-shaped semiconductors, and second and third electrodes connected to ends of...

20060220022 - Semiconductor device, electronic apparatus, method of manufacturing semiconductor device, and method of manufacturing electronic apparatus: A semiconductor device includes first and second electrodes disposed apart from each other on a substrate, a gate electrode disposed so as to face the first and second electrodes and to cover at least part of each of the first and second electrodes, a semiconductor layer disposed between the first...

20060220025 - Image sensor and method of manufacturing the same: An image sensor comprises a substrate including a photodiode, and an insulation pattern structure making contact with the photodiode on the substrate. An anti-reflection pattern is formed on the insulation pattern structure and the substrate. The anti-reflection pattern includes a first opening through which the insulation pattern structure is exposed...

20060220024 - Liquid crystal display device and display device: The present invention provides a technique which can make an image quality on a screen of a TFT liquid crystal display device uniform. A liquid crystal display device includes a TFT substrate on which TFT circuits are arranged in an array, a counter substrate which is arranged to face a...

20060220023 - Thin-film device: Embodiments of methods, apparatuses, devices and systems associated with a thin-film device are disclosed....

20060220026 - Semiconductor element: In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the <11-20> direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region,...

20060220027 - Silicon carbide semiconductor device and process for producing the same: A method for fabricating a semiconductor device includes the steps of implanting ions into a silicon carbide thin film (2) formed on a silicon carbide substrate (1), heating the silicon carbide substrate in a reduced pressure atmosphere to form a carbon layer (5) on the surface of the silicon carbide...

20060220028 - Silicon on diamond-like carbon devices: Embodiments of the invention provide substrate with an insulator layer on the substrate. The insulator layer may comprise diamond-like carbon. A device, such a tri-gate transistor may be formed on the diamond-like carbon layer....

20060220031 - A1lngap led having reduced temperature dependence: To increase the lattice constant of AlInGaP LED layers to greater than the lattice constant of GaAs for reduced temperature sensitivity, an engineered growth layer is formed over a substrate, where the growth layer has a lattice constant equal to or approximately equal to that of the desired AlInGaP layers....

20060220033 - Electro-optical device, method of manufacturing the same, and electronic apparatus: An electro-optical device includes: a substrate; data lines and scanning lines extending to cross each other on the substrate; thin film transistors disposed below the data lines on the substrate; storage capacitors each of which is disposed in a region including a region facing a channel region of each of...

20060220035 - Light emitting device and its manufacturing method: The present invention is intended to provide a light emitting device which can be operated at a low voltage, has excellent luminous efficiency, stability, production cost, and the like. A light emitting device which has at least electrode layers 11, 14, a light emitting layer 13, a structure layer 12...

20060220029 - Light-emitting device and method for manufacturing light-emitting device: A light emitting device 1 has formed therein a light emitting layer section 24 based on a double heterostructure in which a p-type cladding layer 34, an active layer 33 and an n-type cladding layer 32, individually composed of a MgaZn1-aO (0≦a≦1) type oxide, are stacked in this order, and...

20060220030 - Lighting device with flipped side-structure of leds: Disclosed is a lighting device with flipped side-structure of LEDs, which allows emitted lights to travel in parallel with the mounting surface. Single or plural LED chips are mounted on a substrate with their side surfaces facing the substrate surface. The lighting device can be further combined with optical protrusions...

20060220032 - Semiconductor light emitting device: A semiconductor light emitting device has: a semiconductor substrate; a semiconductor layer having an n-type cladding layer, an active layer, a p-type cladding layer and a p-type contact layer, wherein the p-type contact layer is made of an As-based material and located at the top of the semiconductor layer and...

20060220034 - Thin film transistor with capping layer and method of manufacturing the same: A thin film transistor and a method of manufacturing the thin film transistor. The thin film transistor may include a substrate, a buffer layer, a polysilicon layer, a gate insulating layer and/or a gate electrode, and a capping layer. The buffer layer may be formed on the substrate. The polysilicon...

20060220036 - Led package using si substrate and fabricating method thereof: There are provided an LED package using a Si substrate and a fabricating method of the LED package. In the LED package, a supporting structure includes a Si substrate and an insulating layer formed on top and bottom surfaces of the Si substrate, and the supporting structure defines at least...

20060220038 - Receiving optical subassembly with an improved high frequency performance: The present invention provides a receiving optical subassembly (ROSA) with a co-axial shape and a stem for mounting semiconductor devices thereon that improves the high frequency performance of the ROSA. The ROSA mounts a photodiode (PD) and a pre-amplifier on a stem and the stem has a hollow the PD...

20060220037 - Semiconductor optical element: A semiconductor optical element having a includes an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, a first InGaAsP (including zero As content) guide layer without added dopant impurities, an InGaAsP (including zero In content) active layer, a second InGaAsP (including zero As content) guide layer without added dopant...

20060220039 - Semiconductor device, method of manufacturing the same, and substrate for manufacturing the same: A semiconductor device includes a substrate, a buffer layer that is formed with an aluminum nitride layer on the substrate and has a film thickness of 5 nm to 40 nm, an operating layer that is formed with a gallium nitride-based semiconductor on the buffer layer, and a control electrode...

20060220040 - Surface illuminator and liquid crystal display having the same: The invention relates to a surface illuminator and a liquid crystal display having the same and provides a surface illuminator capable of achieving high display quality by employing an array of discrete light sources and a liquid crystal display having the same. A reflective surface for reflecting light in a...

20060220042 - Semiconductor device and fabrication method of the same: A semiconductor device includes a mask layer having openings on a substrate, a GaN-based semiconductor layer selectively formed on the substrate with the mask layer that serves as a mask, a gate electrode and either a source electrode or an emitter electrode formed on the GaN-based semiconductor layer, and a...

20060220041 - Solid state device with current spreading segments: Solid state devices, such as solid state light emitting devices, having non-linear current spreading segments are disclosed. Projection subsystems and systems equipped with such solid state light emitting devices are also disclosed....

20060220044 - Gallium nitride based semiconductor device and method of manufacturing same: A gallium nitride based semiconductor device comprises: a first gallium nitride based semiconductor film doped with magnesium; and a second gallium nitride based semiconductor film provided on the first gallium nitride based semiconductor film and doped with magnesium. The first gallium nitride based semiconductor film has substantially flat distributions of...

20060220043 - Nitride semiconductor light emitting device: The present invention relates to a nitride semiconductor light emitting device having a rectangular top view in which n-electrode and p-electrode structure is appropriately formed to improve propagation of currents and enhance luminance. The light emitting device includes an n-type nitride semiconductor layer formed on a substrate, and an n-electrode...

20060220046 - Led: An LED light-mixing package providing white light has at least a red LED chip, at least a blue LED chip, at least a green LED chip, and pluralities of diffuser particles distributed in a sealing member that covers the LED chips, or integrate a lens. The diffuser particles scatter light...

20060220045 - Micromirror array device with compliant adhesive: A microstructure is packaged with a device substrate of the microstructure being attached to a package substrate. For dissipating possible deformation of the microstructure, which may result in device failure or quality degradation of the microstructure, an adhesive material comprising a compliant adhesive component is applied and positioned between the...

20060220049 - Overmolded lens on leadframe and method for overmolding lens on lead frame: A light emitting diode (LED) assembly including an LED, an optically transmissive cover and a base for supporting the LED. The optically transmissive cover encapsulates the LED and includes a stiffener for reinforcing a base portion of the cover. The base includes electrical leads extending therefrom that are electrically connected...

20060220047 - Phosphor and manufacturing method of the same, and light emitting device using the phosphor: To provide a phosphor having a broad emission spectrum in a range of blue color (peak wavelength from 400 nm to 500 nm), having a broad and flat excitation band in the range of near ultraviolet/ultraviolet, and having excellent emission efficiency and emission intensity/luminance. The phosphor is expressed by a...

20060220048 - Semiconductor light emitting device and semiconductor light emitting unit: In various aspects, a semiconductor light emitting device may include a mold resin having a cup shape portion on an upper surface of the mold resin; a first lead provided in the mold resin and extending from the cup shape portion to outside of the mold resin, the first lead...

20060220052 - Led lamp apparatus and manufacturing method thereof: In an LED lamp apparatus comprising an LED, a circuit portion and a case portion, a pair of the leads of the LED are surrounded at their parts by a sealing member and are extended to comprise the circuit portion, then at least one of the leads constituting the circuit...

20060220053 - Semiconductor light emitting device: A semiconductor light emitting device may include a first lead; a second lead; a first semiconductor light emitting element mounted on the first lead, being configured to emit a light having an optical emission spectrum no more than 400 nm from a light extraction surface of the first semiconductor light...

20060220050 - Semiconductor light-emitting device mounting member, light-emitting diode constituting member using same, and light-emitting diode using same: A semiconductor-light-emitting-device-mounting member BL comprises (a) a highly heat-dissipative member 1 having a main surface 10 on which connecting-use electrode layers 41 and 42 are provided to form a device-mounting area 10a and (b) a frame-shaped member 2 placed on the main surface 10 so as to surround the device-mounting...

20060220051 - System and method for surface mountable display: A system and method is disclosed for allowing a solid substrate, such as a printed circuit board (PCB), to act as the support structure for an electronic circuit. In one embodiment, the LEDs which form a part of a scrambler assembly are constructed on a first substrate and the electrical...

20060220055 - Light emitting diode systems: Light emitting diode systems are disclosed. An optical display system that includes a light emitting diode (LED) and a cooling system is disclosed. The cooling system is configured so that, during use, the cooling system regulates a temperature of the light emitting diode....

20060220056 - Light emitting display and method of manufacturing the same: A method of manufacturing a light emitting display including an image display part formed on a substrate and a pad part including at least one terminal electrically connected to the image display part. The method includes forming thin film transistors and at least one electroluminescent device electrically connected to the...

20060220054 - Super light full space emitting diode buled: Certain aspects of the invention may be found in an SLED with an improved luminance dispersion diagram. In one embodiment of the invention, an SLED may include a light-emitting element of solid geometry comprising a p-n junction. The light emitting element of solid geometry may enable distribution of light energy...

20060220057 - Group iii-nitride light emitting device: The invention provides a group III-nitride light emitting device having improved external quantum efficiency and brightness. The light emitting device comprises an n-type clad layer, an active layer and a p-type clad layer formed in their order. Also, a p-electrode is formed on the p-type clad layer, wherein the p-electrode...

20060220058 - Multiple tunnel junction thermotunnel device on the basis of ballistic electrons: The present invention is a tunnel diode, in which the space between the emitter electrode and the collector electrode is occupied by a porous material which has a thickness less then the free mean free path of an electron in the porous material. The present invention also includes heat pumping...

20060220059 - Solar cell: A solar cell including a light-absorption layer of a compound semiconductor with a chalcopyrite crystal structure and having excellent characteristics such as conversion efficiency is provided. The solar cell includes a first electrode layer, a second electrode layer, a p-type semiconductor layer interposed between the first electrode layer and the...

20060220060 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a GaN-based semiconductor layer that is formed on a substrate and an opening region, an electron conduction layer formed on an inner surface of the opening region, an electron supply layer that has a larger band gap than the electron conduction layer and is formed on...

20060220061 - Semiconductor device and method of manufacturing the same: A semiconductor device of the invention includes a first conductive type semiconductor base substrate; and a switching mechanism which is formed on a first main surface of the semiconductor base substrate and switches ON/OFF of a current. In the semiconductor base substrate, a plurality of columnar hetero-semiconductor regions are formed...

20060220062 - Phemt with barrier optimized for low temperature operation: In one embodiment, a semiconductor device (500) includes a buffer layer (504) formed over a substrate (502). An AlxGa1-xAs layer (506) is formed over the buffer layer (504) and has a first doped region (508) formed therein. An InxGa1-xAs channel layer (512) is formed over the AlxGa1-xAs layer (506). An...

20060220063 - Semiconductor device having gan-based semiconductor layer: A semiconductor device includes a GaN-based semiconductor layer formed on a substrate, and an insulating film composed of any one of silicon nitride in which the composition ratio of silicon to nitrogen is 0.85 to 3.0, silicon oxide in which the composition ratio of silicon to oxygen is 0.6 to...

20060220064 - Method for manufacturing a bipolar transistor and bipolar transistor manufactured by the method: A bipolar transistor and a method for manufacturing the bipolar transistor is disclosed. The bipolar transistor is formed by the steps of: doping of a surface region of a substrate with a first doping to form an active emitter region; formation of at least one cavity in the substrate; application...

20060220065 - Semiconductor device and fabrication method therefor: A semiconductor device includes a substrate, a GaN-based semiconductor layer formed on the substrate, a gate electrode embedded in the GaN-based semiconductor layer, a source electrode and a drain electrode formed on both sides of the gate electrode, a first recess portion formed between the gate electrode and the source...

20060220066 - Semiconductor device having a dummy gate: A semiconductor device includes a plurality of MOS transistors, wherein each of the MOS transistors has a drain region, a pair of source regions sandwiching therebetween the drain region, and a pair of normal gates each overlying a space between the drain region and a corresponding one of the source...

20060220067 - Nanoscopic wire-based devices and arrays: Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used...

20060220069 - Isolation structures for preventing photons and carriers from reaching active areas and methods of formation: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching...

20060220068 - Solid-state image pick-up unit and method of manufacturing the same: A solid-state image pick-up unit comprises: a semiconductor substrate comprising an area in which a photoelectric converting portion is formed; and an electric charge transfer portion that transfers an electric charge formed by the photoelectric converting portion, wherein the electric charge transfer portion comprises: an electric charge transfer electrode including...

20060220070 - Imaging system and driving method: An imaging system, capable of reducing blooming in a solid-state imaging device and improving image sensitivity, comprises an imaging section which has at least three transfer electrodes and is continuously arranged with pixels for producing information charges in response to the light from the outside, wherein the information charges are...

20060220071 - Phase-change semiconductor memory device and method of programming the same: In one aspect, a semiconductor memory device includes a plurality of phase-change memory cells which are programmed according to a write current applied to the phase-change memory cells, a voltage boosting circuit which receives a first voltage and outputs a boosted voltage which is greater than the first voltage, and...

20060220072 - Vertical junction field effect transistor having an epitaxial gate: A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is formed within the trench by epitaxial regrowth. The epitaxial...

20060220073 - Solid-state image pickup element and method of producing the same: A solid-state image pickup element comprises: a semiconductor substrate; a photoelectric converting portion formed in the semiconductor substrate; a reflective material portion comprising a hole portion wherein the hole portion is located on a surface, on an area in which the photoelectric converting portion is formed, of the semiconductor substrate,...

20060220074 - Carbon nanotube energy well (cnew) field effect transistor: A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped...

20060220075 - Methods of fabricating self-aligned source of flash memory device: Example methods of fabricating semiconductor devices are disclosed. One example method may include depositing an oxide layer, a first conducting layer for a floating gate, a dielectric layer, and a second conducting layer for a control gate in sequence on a semiconductor substrate including a device isolation layer; forming gates...

20060220076 - Semiconductor device and its manufacturing method: The object of the invention is to provide a semiconductor device that can form photodiodes that do not short circuit, without damage that causes leakage, despite formation of the opening part, and its manufacturing method. The second semiconductor layer (12, 16) of the second conductivity type is formed on the...

20060220077 - Display device with built-in sensor: A drive circuit that can cover a possible dispersion in characteristics among optical sensors is constructed in order to obtain a stable sensor output. The device includes an optical sensor provided in each of pixels arranged in lines in vertical and horizontal directions, a circuit that instructs a timing of...

20060220078 - Photodiode with controlled current leakage: The present invention is directed towards radiation detectors and methods of detecting incident radiation. In particular the present invention is directed towards photodiodes with controlled current leakage detector structures and a method of manufacturing photodiodes with controlled current leakage detector structures. The photodiodes of the present invention are advantageous in...

20060220079 - Semiconductor light receiving device and method of manufacturing the same: A semiconductor light receiving device includes a plurality of photodiode units, each of which is configured to convert a received light into an electric signal; and a separating unit configured to electrically separates the plurality of photodiode units from each other. The impurity concentration of a surface portion of the...

20060220080 - Polymer memory and method of its fabrication: An embodiment mitigates one or more of the limiting factors of fabricating polymer ferroelectric memory devices. For example, an embodiment reduces the degradation of the ferroelectric polymer due to the polymer's reaction with, and migration or diffusion of, adjacent metal electrode material. Further, the ferroelectric polymer is exposed to fewer...

20060220083 - Semiconductor device: A semiconductor device includes a semiconductor substrate, a first electrode that is formed over said semiconductor substrate, a capacitive insulating film that is formed on the first electrode and is made of a metal oxide ferroelectric, a second electrode that is formed on the capacitive insulating film, an insulating film...

20060220081 - Semiconductor device and manufacturing method of the same: After a ferroelectric capacitor is formed, an Al wiring (conductive pad) connected to the ferroelectric capacitor is formed. Then, a silicon oxide film and a silicon nitride film are formed around the Al wiring. Thereafter, as a penetration inhibiting film which inhibits penetration of moisture into the silicon oxide film,...

20060220082 - Semiconductor device and manufacturing method of the same: After a ferroelectric capacitor is formed, a cap film made of Ti or Ir is formed on a top electrode of the ferroelectric capacitor. Thereafter, an alumina film which covers the ferroelectric capacitor is formed as a protective film. Further, a SiO2 film which covers the ferroelectric capacitor with the...

20060220086 - Imos transistor: A vertical IMOS-type transistor including: a stack of a first semiconductor portion doped with dopant elements of a first type, of a second substantially undoped intrinsic semiconductor portion, and of a third semiconductor portion doped with dopant elements of a second type forming a PIN-type diode; and a conductive gate...

20060220084 - Magnetoresistive effect element and method for fabricating the same: The magnetoresistive effect element comprises a first ferromagnetic layer 50, a nonmagnetic layer 52 formed on the first ferromagnetic layer 50, a second ferromagnetic layer 54 formed on the nonmagnetic layer 52, and a sidewall insulating film 64 formed on the side wall of the second ferromagnetic layer 54. The...

20060220087 - Method of forming a contact structure including a vertical barrier structure and two barrier layers: This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more...

20060220085 - Single transistor floating body dram cell having recess channel transistor structure and method of fabricating the same: Single transistor floating body dynamic random access memory (DRAM) cells include a semiconductor substrate and a barrier layer on the semiconductor substrate and a recess channel transistor on the barrier layer. The recess channel transistor includes a source region of a first conductivity type, a drain region of the first...

20060220089 - Memories having a charge storage node at least partially located in a trench in a semiconductor substrate and electrically coupled to a source/drain region formed in the substrate: A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material (120.3) providing at least...

20060220088 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed, which includes a semiconductor substrate including a device region and an isolation region having an isolation trench, a gate electrode formed on the device region through a gate insulating film, a first isolation insulating film formed in the isolation trench, the first isolation insulating film...

20060220091 - Semiconductor device and method for fabricating the same: A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least one common type of atoms for allowing the...

20060220090 - Semiconductor device with a high-k gate dielectric and a metal gate electrode: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed over a channel that is positioned within a substrate, and a metal gate electrode that is formed on the high-k gate dielectric layer. The high-k gate dielectric layer has off-state leakage characteristics that...

20060220092 - Titanium oxide extended gate field effect transistor: A titanium oxide extended gate field effect transistor (EGFET) device and fabricating method thereof. Titanium oxide is formed on an EGFET by sputtering, coating a detection membrane therefor. Current-voltage relationships at different pH values are also measured via a current measuring system. Sensitivity parameter of the titanium oxide EGFET is...

20060220101 - Highly compact non-volatile memory and method therefor with internal serial buses: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant...

20060220093 - Non-volatile memory cell and method of fabrication: Semiconductor device comprising a vertical split gate non-volatile memory cell, for storing at least one bit, on a semiconductor substrate, comprising on the substrate a trench, a first active area, a second active area, a channel region extending along a sidewall of the trench, the trench having a length extending...

20060220095 - Non-volatile memory having three states and method for manufacturing the same: Disclosed is a non-volatile memory having three data states and a method for manufacturing the same. The non-volatile memory includes a silicon substrate having a device separation film; a floating gate formed on the silicon substrate; a tunnel oxide film interposed between the silicon substrate and the floating gate below...

20060220094 - Non-volatile memory transistor with nanotube floating gate: Non-volatile memory transistors have a semiconductor substrate with spaced apart source and drain regions defining a channel, a layer of tunnel oxide over the channel and a conductive layer of carbon nanotubes over the tunnel oxide. In patterning, mesas are formed retaining desired locations of nanotubes as floating gates. The...

20060220098 - Nonvolatile memory devices and methods of making the same: Nonvolatile memory devices and methods of making the same are described. A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of...

20060220099 - Semiconductor device: In a conventional semiconductor device, there has been a problem that, in a region where a wiring layer to which a high electric potential is applied traverses a top surface of an isolation region, the withstand voltage is deteriorated. In a semiconductor device of the present invention, an epitaxial layer...

20060220097 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a silicon substrate 14 having a step formed in the surface which makes the surface in a flash memory cell region 10 lower than the surface in a peripheral circuit region 12; a device isolation region 20a formed in a trench 18 in the flash memory...

20060220100 - Semicondudctor device: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit...

20060220096 - Tunneling-enhanced floating gate semiconductor device: Tunneling-enhanced, floating gate semiconductor devices and methods for forming such devices are described. In one embodiment, a p-n junction device is formed with a floating gate that is partially doped with n- and p-type impurities. Two regions on either side of an n+ doped region in the floating gate and...

20060220102 - Non-volatile memory cell including a capacitor structure and processes for forming the same: A non-volatile memory cell can include a substrate, an active region overlying the substrate, and a capacitor structure overlying the substrate. From a plan view, the capacitor structure surrounds the active region. In one embodiment, the non-volatile memory cell includes a floating gate electrode and a control gate electrode. The...

20060220105 - Self-aligned split-gate nonvolatile memory structure and a method of making the same: Provided are non-volatile split-gate memory cells having self-aligned floating gate and the control gate structures and exemplary processes for manufacturing such memory cells that provide improved dimensional control over the relative lengths and separation of the split-gate elements. Each control gate includes a projecting portion that extends over at least...

20060220104 - Semiconductor device and method for manufacturing the same: A semiconductor device including a bipolar transistor in which the collector resistance. The bipolar transistor includes a first conduction type semiconductor substrate having a main surface. A second conduction type collector region is formed in the semiconductor substrate. A shallow trench isolation structure isolates the main surface of the semiconductor...

20060220103 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate divided into a memory cell region in which a memory cell is formed and a peripheral circuit region in which a peripheral circuit for driving the memory cell is formed, a plurality of conductive layers provided in each region so as to interpose...

20060220106 - Gate structures of a non-volatile memory device and methods of manufacturing the same: In a gate structure of a non-volatile memory device is formed, a tunnel insulating layer and a charge trapping layer are formed on a substrate. A composite dielectric layer is formed on the charge trapping layer and has a laminate structure in which first material layers including aluminum oxide and...

20060220108 - Field-effect transistor in semiconductor device, method of manufacturing the same: A field-effect transistor has: a substrate having a first cavity; a gate electrode buried in the substrate; and diffusion layers formed in the substrate and being in contact with the first cavity. A channel region is formed substantially perpendicular to a surface of the substrate between the diffusion layers....

20060220110 - Integrated circuit with protected implantation profiles and method for the formation thereof: An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer....

20060220107 - Mosfet with a second poly and an inter-poly dielectric layer over gate for synchronous rectification: This invention discloses a new trenched vertical semiconductor power device that includes a capacitor formed between a conductive layer covering over an inter-dielectric layer disposed on top of a trenched gate. In a specific embodiment, the trenched vertical semiconductor power device may be a trenched metal oxide semiconductor field effect...

20060220109 - Selectively doped trench device isolation: A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function...

20060220111 - Semiconductor device having step gates and method of manufacturing the same: A semiconductor device having step gates includes a semiconductor substrate including first regions having relatively low steps at both ends of an active region defined by trench isolation films and a second region having a relatively high step at a central part of the active region, a groove having a...

20060220116 - Method and system for vertical dmos with slots: A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of...

20060220113 - P-channel mos transistor, semiconductor integrated circuit device and fabrication process thereof: A p-channel MOS transistor includes source and drain regions of p-type formed in a silicon substrate at respective lateral sides of a gate electrode wherein each of the source and drain regions of p-type includes any of a metal film region and a metal compound film region as a compressive...

20060220115 - Semiconductor device: In a semiconductor device of the present invention, an N-type epitaxial layer 2 is deposited on a P-type substrate 1. In the epitaxial layer 2, a P-type diffusion layer 5 to be used as a back gate region is formed. An N-type diffusion layer 8 to be used as a...

20060220114 - Semiconductor device and manufacturing method thereof: An ideal step-profile in a channel region is realized easily and reliably, whereby suppression of the short-channel effect and prevention of mobility degradation are achieved together. A silicon substrate is amorphized to a predetermined depth from a semiconductor film, and impurities to become the source/drain are introduced in this state....

20060220112 - Semiconductor device having step gates and method of manufacturing the same: Methods and structure formed for retarding diffusion of a dopant into a channel of a strained Si—SiGe CMOS device are disclosed. The methods form a diffusion retardant region in a substrate including at least one diffusion retardant species such as xenon (Xe), and then form a channel layer over the...

20060220117 - Structure for an ldmos transistor and fabrication method thereof: A structure for an LDMOS transistor has a horseshoe-shaped gate layer formed on an N-type layer of a semiconductor silicon substrate, in which the gate layer comprises a transverse-extending area, a first lengthwise-extending area connected to a left end of the transverse-extending area and a second lengthwise-extending area connected to...

20060220118 - Semiconductor device including a dopant blocking superlattice: A semiconductor device may include at least one metal oxide field-effect transistor (MOSFET). The at least one MOSFET may include a body, a channel layer adjacent the body, and a dopant blocking superlattice between the body and the channel layer. The dopant blocking superlattice may include a plurality of stacked...

20060220119 - Strained-channel semiconductor structure and method for fabricating the same: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region A pair...

20060220123 - Chip scale surface mounted device and process of manufacture: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact...

20060220120 - High voltage ldmos device with counter doping: LDMOS structures and methods for fabricating them includes a counter dopant implant region in a drain well. According to another aspect, an LDMOS device includes a graded junction region in the LDMOS device's channel region. The counter dopant implant region may extend from the drain portion into the graded junction...

20060220122 - Semiconductor device and method of manufacturing the same: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a...

20060220121 - Switching-controlled power mos electronic device: Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks connected to a gate pad and at least...

20060220125 - Semiconductor device: In a semiconductor device of the present invention, a thin gate oxide film is formed on a P-type diffusion layer. On the gate oxide film, a gate electrode is formed. N-type diffusion layers are formed in the P-type diffusion layer, and the N-type diffusion layer is used as a drain...

20060220124 - Semiconductor device and fabrication method of the same: A semiconductor device includes a gate electrode, a source electrode, a drain electrode and an electrode part. The gate electrode is formed above a semiconductor layer. The source electrode and the drain electrode are formed on the semiconductor layer. The gate electrode is located between the source electrode and the...

20060220133 - Doping of semiconductor fin devices: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface....

20060220131 - Fin-type channel transistor and method of manufacturing the same: It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions. There are provided: a first semiconductor layer of a first conductivity type in a substantially a rectangular solid shape formed on...

20060220130 - High breakdown voltage semiconductor device and fabrication method of the same: A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the active layer, a P-type source region formed...

20060220129 - Hybrid fully soi-type multilayer structure: The invention relates to a silicon-on-insulator-type multilayer structure that includes a support layer, at least two working layers having different crystalline orientations, and an insulating layer extending over at least a portion of the support layer. This insulating layer extends over the whole surface of the support layer so as...

20060220127 - Method for producing a tensioned layer on a substrate, and a layer structure: The invention relates to a method for producing a tensioned layer on a substrate involving the following steps: producing a defect area in a layer adjacent to the layer to be tensioned, and; relaxing at least one layer adjacent to the layer to be tensioned. Additional layers can be epitaxially...

20060220126 - Method of manufacturing an electronic arrangement: The device of the invention comprises a thin film transistor of an organic semiconductor material. This semiconductor material is patterned by applying first a protective layer and thereafter a photoresist. As a result hereof, the transistor of the invention (A) shows a very low leakage current and a low threshold...

20060220128 - Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate and method for manucfacturing semiconductor device: A semiconductor substrate comprising a semiconductor base, a dielectric layer formed in at least a part of an area on the semiconductor base, and a single crystal semiconductor layers having mutually different film thicknesses, disposed on the dielectric layer and formed by epitaxial growth....

20060220132 - Semiconductor substrate, semiconductor device, method of manufacturing semiconductor substrate, and method of manufacturing semiconductor device: A method of manufacturing a semiconductor device, includes: forming an insulating layer on a single crystal semiconductor substrate; forming a non-crystalline semiconductor layer on the insulating layer; forming an insulating film on the non-crystalline semiconductor layer; forming an opening section for exposing a part of a surface of the single...

20060220134 - Cmos sram cells employing multiple-gate transistors and methods fabricating the same: Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type) MOS load transistor...

20060220135 - Electrostatic discharge input protection circuit: An ESD protection circuit includes: a first metal oxide semiconductor (MOS) transistor discharging an excessive electrostatic current generated between an input pad and an internal circuit, and having a first terminal connected to a ground voltage supply terminal; and a second MOS transistor discharging an electrostatic current generated between the...

20060220136 - Electro-static discharge protection circuit and semiconductor device having the same: An electro-static discharge protection circuit comprises a thyristor mode ensuring circuit and a thyristor rectifier circuit. The thyristor mode ensuring circuit includes a capacitive element C1 connected between a higher potential line Vdd and a lower potential line Vss, and ensures a constant and sufficient capacity independently of the number...

20060220137 - Electro-static discharge protection circuit and semiconductor device having the same: An electro-static discharge protection circuit and a semiconductor device having the same is disclosed. The electro-static discharge protection circuit has a current control circuit. The current control circuit has a first capacitive element. When the external source voltage is applied to the external source voltage supply line, the booster circuit...

20060220138 - Esd protection circuit with scalable current capacity and voltage capacity: An ESD protection circuit includes semiconductor structures as basic elements whose electrical conductivity changes in a breakdown or avalanche manner in the presence of an applied voltage which exceeds a threshold value. The ESD protection circuit has a matrix of basic elements in which a desired current capacity can be...

20060220139 - Semiconductor device and fabrication process thereof: A semiconductor device includes a semiconductor substrate of a first conductivity type, a well of the first conductivity type formed in the semiconductor substrate, a transistor formed in the well, a diffusion region of a second conductivity type formed in the semiconductor substrate so as to cover a lateral side...

20060220141 - Low contact resistance cmos circuits and methods for their fabrication: A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive...

20060220140 - Method of forming an integrated power device and structure: In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor....

20060220147 - Isolation structure configurations for modifying stresses in semiconductor devices: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as,...

20060220146 - Semiconductor device: A semiconductor device for effectively suppressing noise propagation between circuits. The semiconductor device includes a semiconductor substrate having a main surface. Two circuit regions are defined in the semiconductor substrate. A circuit isolation region is located between the two circuit regions. A dummy diffusion layer is formed in the circuit...

20060220144 - Semiconductor device and its manufacture method: A semiconductor device includes: a semiconductor substrate; and STIs formed in the semiconductor substrate and defining a high voltage transistor area and a low voltage transistor area, the STIs including: a first STI with a first liner including a thermal oxide film and not including a nitride film and surrounding...

20060220143 - Semiconductor device and manufacturing method of the same: Patterning is performed in such a manner that an end portion fabricated of a second gate insulating film partially overlaps an end portion fabricated of a first gate insulating film. Then, a surface recovery treatment is performed in the aforementioned state where the first and second gate insulating films partially...

20060220142 - Semiconductor device and manufacturing method thereof: The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between both active regions, and a...

20060220145 - Semiconductor device with increased channel length and method for fabricating the same: A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide layer, having a first...

20060220148 - Shallow trench isolation formation: A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is...

20060220149 - Dynamically tunable resistor or capacitor using a non-volatile floating gate memory cell: An integrated circuit programmable resistor or programmable capacitor has a floating gate memory cell connected either in series or in parallel to a fixed resistor or a fixed capacitor. The resistance or the capacitance of the floating gate memory cell can be changed by the amount of charge stored on...

20060220150 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: a gate electrode that is provided on a semiconductor layer; a source electrode and a drain electrode that are provided on the semiconductor layer so as to interpose the gate electrode; a source wall that extends from the source electrode to a point between the gate...

20060220151 - Semiconductor device having enhanced performance and method: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation....

20060220153 - Method of fabricating a field effect transistor structure with abrupt source/drain junctions: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending...

20060220152 - Mosfet structure with ultra-low k spacer: Disclosed is a MOSFET structure and method of fabricating the structure that incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. In one embodiment, the multi-layer sidewall spacer is formed with...

20060220155 - Semiconductor device: A semiconductor device has a semiconductor substrate, a gate insulator, a gate electrode, and a pair of lightly doped regions. The gate insulator is formed on the semiconductor substrate. The gate electrode is formed on the gate insulator and has first bottom faces and second bottom faces. The distance of...

20060220156 - Semiconductor device and method for manufacturing same: The present semiconductor device comprises pillar layers formed on a first semiconductor layer, the pillar layers comprising a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type which are alternately formed in a first direction along a surface of...

20060220154 - Semiconductor device comprising a field-effect transitor and method of operating the same: The invention relates to in particular a lateral DMOST with a drain extension (8). In the known transistor a further metal strip (20) is positioned between the gate electrode contact strip and the drain contact (16) which is electrically connected with the source region contact (15). In the device proposed...

20060220157 - Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors: A gate dielectric structure (201) fabrication process includes forming a transitional dielectric film (205) overlying a silicon oxide film (204). A high dielectric constant film (206) is then formed overlying an upper surface of the transitional dielectric film (205). The composition of the transitional dielectric film (205) at the silicon...

20060220158 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: a semiconductor layer; a high dielectric constant gate insulation film disposed above the semiconductor layer, the high dielectric constant gate insulation film containing a plurality of elements; a gate electrode disposed on the high dielectric constant gate insulation film; and an impurity region disposed in the...

20060220159 - Sensor: A sensor having a terminal connection structure in which an elongated sensor element (21) is inserted, from its rear end through relative movement, into a metallic-terminal-member retainer. Metallic terminal members (51) are elastically deformed and pressed against corresponding electrode terminals (25) formed on side surfaces (26) of the sensor element....

20060220160 - Structure of a structure release and a method for manufacturing the same: A structure of a structure release and a manufacturing method are provided. The structure and manufacturing method are adapted for an interference display cell. The structure of the interference display cell includes a first electrode, a second electrode and at least one supporter. The second electrode has at least one...

20060220161 - Spin-injection fet: An spin-injection FET according to an embodiment of the invention includes a first ferromagnetic body whose magnetization direction is fixed, a second ferromagnetic body whose magnetization direction is changed by spin-injection current, a gate electrode which is formed on a channel between the first and second ferromagnetic bodies, a first...

20060220162 - Spin tunnel transistor: Some spin tunnel transistors with a larger current transmittance and a higher MR ratio are described. One of the spin tunnel transistor comprises a collector; an emitter; abase formed between the collector and the emitter, including a first ferromagnetic metal layer variable in its magnetization under an external magnetic field;...

20060220163 - Light sources that use diamond nanowires: Light sources that use diamond nanowires, and methods of forming the same, are described. For example, the light source can include a diamond nanowire that bridges the gap between a first electrode and a second electrode to electrically couple the two electrodes. A power source coupled to the first and...

20060220164 - Thermopile-based gas sensor: A method of manufacturing a sensor is provided. The method includes disposing a sacrificial layer on a substrate, disposing a low-thermal-conductivity layer on the sacrificial layer, and disposing a first set of conductive arms and a second set of conductive arms on the low-thermal-conductivity layer to form a plurality of...

20060220165 - Semiconductor device: There is provided a semiconductor device capable of ensuring a complete enhancement-mode operation and realizing a power transistor excellent in the low-distortion, high-efficiency performance. On a surface of a substrate (1) composed of single crystal GaAs, a second barrier layer (3) composed of AlGaAs, a channel layer (4) composed of...

20060220166 - Semiconductor device: In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion...

20060220169 - Device having conductive material disposed in a cavity formed in an isolation oxide disposed in a trench: Devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an isolation oxide. Cavities are formed in the isolation oxide and filled with a conductive material, such a doped polysilicon. Doped regions may be formed in the substrate directly adjacent...

20060220167 - Ic package with prefabricated film capacitor: A method of fabricating an integrated circuit package, comprising prefabricating a film capacitor including forming a first conductive layer, depositing a dielectric layer on the first conductive layer, and depositing a second conductive layer on the dielectric layer; forming a substrate; and laminating the prefabricated film capacitor to the substrate....

20060220168 - Shielding high voltage integrated circuits: Methods and apparatus are disclosed for protecting the electric field distribution of the high voltage semiconductor devices and of the high voltage junction terminating structures from the influences of overlaying interconnections. The proposed methods and apparatus prevent the breakdown voltage of the devices from decreasing. At the same time, circuit...

20060220170 - High-voltage field effect transistor having isolation structure: A high-voltage MOSFET having isolation structure is provided. An N-type MOSFET includes a first deep N-type well. A first P-type region is formed in the first deep N-type well to enclose a first source region and a first contact region. A first drain region is formed in the first deep...

20060220171 - Trench isolation structures for semiconductor devices and methods of fabricating the same: A device isolation structure of semiconductor device includes a semiconductor substrate having a cell region, a low voltage region and a high voltage region defined therein. A cell trench isolation region is disposed in the cell region. A low voltage trench isolation region is disposed in the low voltage region...

20060220172 - Coating of copper and silver air bridge structures to improve electromigration resistance and other applications: An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air bridge extending through a gaseous medium so as to reduce the capacitance of the interconnect. The air bridge is supported at a first and second end such that...

20060220173 - Wafer level package including a device wafer integrated with a passive component: According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated...

20060220174 - E-fuse and anti-e-fuse device structures and methods: Standard photolithography is used to pattern and fabricate a final polysilicon wafer imaged structure which is smaller than normal allowable photo-lithographic minimum dimensions. Three different methods are provided to produce such sub-minimum dimension structures, a first method uses a photolithographic mask with a sub-minimum space between minimum size pattern features...

20060220176 - High-k thin film grain size control: A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of...

20060220175 - Organic substrates with embedded thin-film capacitors, methods of making same, and systems containing same: A thin-film capacitor assembly includes two plates that are accessed through deep and shallow vias. The thin-film capacitor assembly is able to be coupled with a spacer and an interposer. The thin-film capacitor assembly is also able to be stacked with a plurality of thin-film capacitor assemblies. The thin-film capacitor...

20060220177 - Reduced porosity high-k thin film mixed grains for thin film capacitor applications: A method including forming a layer of a first ceramic material on a substrate; and after forming the layer, forming a second ceramic material on the layer of the first ceramic material, the formed second ceramic material including an average grain size less than a grain size of the first...

20060220178 - Semiconductor device and method of manufacturing the same: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to...

20060220179 - Method for forming an improved isolation junction in high voltage ldmos structures: A method for forming an improved isolation junction in an LDMOS structure to reduce current leakage at high operating Voltages including forming doped regions in a buried layer prior to forming an overlying epitaxial region including doped isolation regions followed by a drive-in process to form a continuous isolation region...

20060220180 - Semiconductor device with extraction electrode: First and second connection electrodes are formed separately to be opposed to each other on an emitter electrode of an IGBT. Other first and second connection electrodes are formed separately to be opposed to each other on an anode electrode of a diode. A first electrode interconnection part extends from...

20060220181 - Controllable varactor within dummy substrate pattern: A dummy region varactor for improving a CMP process and improving electrical isolation from active areas and a method for forming the same, the varactor including a semiconductor substrate having a dummy region said dummy region including a first well region having a first polarity; shallow trench isolation (STI) structures...

20060220182 - Semiconductor device: A through-electrode that penetrates a semiconductor substrate and that is insulatively separated from the semiconductor substrate includes an inner through-electrode, a quadrangular ring-shaped semiconductor, and an outer peripheral through-electrode. The quadrangular ring-shaped semiconductor is formed around the inner through-electrode, and the outer peripheral through-electrode is formed around the quadrangular ring-shaped...

20060220183 - Semiconductor wafer having multiple semiconductor elements and method for dicing the same: A semiconductor wafer includes: a first layer having a first refraction index; a second layer having a second refraction index, which is different from the first refraction index; a plurality of semiconductor elements; and a layer removal region. The semiconductor elements are capable of being separated each other by irradiating...

20060220184 - Antireflective coating for use during the manufacture of a semiconductor device: An antireflective layer formed from boron-doped amorphous carbon may be removed using a process which is less likely to over etch a dielectric layer than conventional technology. This layer may be removed by exposing the layer to an oxygen plasma (i.e. an “ashing” process), preferably concurrently with the ashing and...

20060220185 - Optical information storage medium: An optical information storage medium includes a first substrate, a first recording stack layer and a second substrate. The first recording stack layer is disposed above the first substrate. The second substrate is disposed above the first recording stack layer, and the hardness of the second substrate is higher than...

20060220186 - Semiconductor constructions: In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material...

20060220187 - Heatsink moldlocks: A system of mold locks (28, 30) is formed on a heatsink (2) of a packaged semiconductor to prevent/mitigate delamination . The mold locks (4, 12) anchor a plastic mold compound (34) that forms the protective cover for the packaged semiconductor die. The mold locks (4, 12) are miniaturized to...

20060220190 - Lead frame and semiconductor device: A lead frame is provided. Although there is a die pad (2) located to deviate from a main plane center line of a resin molding area (10), a die pad connecting portion (6) is located to deviate from the main plane center line of the resin molding area in a...

20060220188 - Package structure having mixed circuit and composite substrate: The present invention provides a package structure, which includes a substrate, wherein the circuit has been configured within the substrate; a lead-frame having lead on the first surface of the substrate; at least one first electronic device located on the lead-frame; a second electronic device located on the first surface...

20060220189 - Semiconductor module and method of manufacturing the same: A semiconductor module according to the invention includes: an island formed of a conductive material; a plurality of leads disposed in vicinity of the island; a resin sealing body which is mounted on the island and disposed such that a back surface of a circuit board on which semiconductor elements...

20060220191 - Electronic package with a stepped-pitch leadframe: A leadframe for an electronic package is provided. The lead frame includes a plurality of leads each having an outer lead bond and an inner lead bond. The plurality of leads are interconnected by a tie bar. The plurality of leads have a first pitch at an exit or attach...

20060220192 - Semiconductor substrate, substrate for semiconductor crystal growth, semiconductor device, optical semiconductor device, and manufacturing method thereof: A semiconductor substrate includes: a semiconductor crystal layer grown on one face of a substrate; and a stress relaxation layer, which is formed on the other face opposite to the one face and the side face of the substrate and applies stress to the substrate in the same direction as...

20060220193 - Manufacturing method for magnetic sensor and lead frame therefor: A magnetic sensor is constituted using magnetic sensor chips mounted on stages supported by interconnecting members and a frame having leads in a lead frame. Herein, the stages are inclined upon plastic deformation of the interconnecting members. When the frame is held in a metal mold and the stages are...

20060220194 - Controlling warping in integrated circuit devices: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a...

20060220196 - Semiconductor device and method of manufacturing the same, metal component and method of manufacturing the same: A semiconductor device that includes: a metal component that has at least one face sealed with resin; a semiconductor element that is electrically or thermally connected to the metal component; and a protruding portion that is formed on the one face of the metal component by a push from the...

20060220195 - Structure and method to control underfill: A silicon die having a junction side being attachable to a substrate, a backside surface spaced from the junction side and an underfill control feature to prevent an underfill from settling above said backside surface is disclosed herein....

20060220199 - Low cost hermetically sealed package: Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package frame contacts the top surface of the top substrate and top surface of the package substrate, and hermetically seals the device between the...

20060220197 - Method of forming self-passivating interconnects and resulting devices: A method of forming self-passivating interconnects. At least one of two mating bond structures is formed, at least in part, from an alloy of a first metal and a second metal (or other element). The second metal is capable of migrating through the first metal to free surfaces of the...

20060220198 - Semiconductor integrated circuit (ic) packaging with carbon nanotubes (cnt) to reduce ic/package stress: A packaged integrated circuit (IC) is described having an integrated circuit that is electrically coupled to its package's wiring with Carbon nanotubes (CNTs) placed within an electrically conductive material....

20060220200 - Substrate for ic package: A packaging substrate is formed of an array of packaging units. Each packaging unit includes a chip pad on which a chip is carried, a plurality of pins arranged around the chip pad and spaced from one another and the chip pad by an open space, an insulative member filling...

20060220202 - Ic card and method of manufacturing the same: An IC body is loaded to a case 2 made of thermosetting resin material and sealed with a sealing portion made of thermosetting resin material to be integrated, whereby an IC card is manufactured. The IC body comprises: a wiring substrate formed with an external connection terminal at a back...

20060220203 - Memory card: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the...

20060220204 - Memory card: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the...

20060220201 - Structure of memory card packaging and method of forming the same: A structure and a method for a memory card are provided, including a circuit substrate and an encapsulating case. The substrate is completed with chips and circuit connected, and is stamped on the circumferential borders to form a plurality of ribs or gaps. The case is formed by a burying...

20060220205 - Electronic component mounting package and package assembled substrate: A package of the present invention has a laminate structure formed by laminating a plurality of ceramic layers, and has a mount surface to be a joint surface when mounted on a mother board, defined parallel with the laminating direction. A first ceramic layer has a recess with an L-shaped...

20060220211 - Method for manufacturing semiconductor apparatus, and semiconductor apparatus and electric appliance: According to the package and the method for manufacturing the package of the present invention, a chip can be formed extremely to be thin, and manufactured at lower cost and higher throughput, and the variations of a chip thickness can be reduced without back grind that causes cracks or polishing...

20060220210 - Semiconductor assembly including chip scale package and second substrate and having exposed substrate surfaces on upper and lower sides: Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the molding of the first package with the...

20060220209 - Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides: Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other; that is, the die attach sides of the package substrates face one...

20060220212 - Stacked package for electronic elements: A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic...

20060220207 - Stacked semiconductor package: A metal pattern for heat dissipation is formed on the backside of a second semiconductor substrate, the metal pattern being in contact with a first semiconductor element mounted on a semiconductor device adjacent to the backside. Vias are formed on the peripheries of semiconductor substrates, the vias penetrating in the...

20060220208 - Stacked-type semiconductor device and method of manufacturing the same: A semiconductor device of a stacked type includes a semiconductor chip (1) that is mounted on a substrate (4), a first sealing resin (12) that seals the semiconductor chip (1), a built-in semiconductor device (9) that is placed on the first sealing resin (12), and a second sealing resin (13)...

20060220206 - Vertically integrated system-in-a-package: According to one embodiment of the invention, a method of forming a system-in-a-package includes providing a first substrate, coupling a first die to a top surface of the first substrate, coupling one or more surface mount devices to a top surface of a second substrate, coupling the second substrate to...

20060220213 - Semiconductor device: One of the aspects of the present invention is to provide a power semiconductor device, including a first substrate having a first circuit pattern formed thereon, and a second substrate having a second circuit pattern formed thereon. The first substrate has a first center line extending along a predetermined transverse...

20060220214 - Semiconductor device and manufacturing method thereof: A semiconductor device of the present invention includes: a substrate having a first region and second regions; dicing grooves which separate the first region from the second regions; step parts which are provided on surfaces of the first region and the second regions of the substrate adjacent to the dicing...

20060220216 - Circuit device and manufacturing method thereof: A circuit device includes a ceramic substrate, an Al wiring layer provided on the ceramic substrate, and a semiconductor device and a bus bar which are electrically connected to the wiring layer. On part of the wiring layer, a Ni layer is plated. Thus a coated region in which the...

20060220215 - Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same: Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically...

20060220217 - High precision connector member and manufacturing method thereof: The connection member has a conductor portion (13) and a dummy pattern portion (15) both formed of a metallic conductor and arranged on a base (11). The conductor portion (13) and the dummy pattern portion (15) are formed by etching. The dummy pattern portion (15) has a positioning portion (21)...

20060220218 - Embedded-type power semiconductor package device: An embedded-type power semiconductor package device that can clasp an isolating material over a semiconductor die in the inside thereof that through a two-fold strategy reduces the impact force during the embedding process, which includes a pin, a semiconductor die, and a cup. The cup is formed with a cup...

20060220219 - Substrate for ic package: A packaging substrate is formed of an array of packaging units. Each packaging unit has a chip pad carrying a chip, a plurality of pins arranged around the chip pad and spaced from one another and the chip pad by an open space, an insulative member formed of a plurality...

20060220222 - Chip embedded package structure and fabrication method thereof: A chip embedded package structure and a fabrication method thereof are proposed. An adhesive layer is formed on a bottom surface of a carrier board having at least one cavity to seal one end of the cavity. At least one semiconductor chip is mounted via its non-active surface on the...

20060220220 - Electronic device and method for fabricating the same: The electronic device comprises a first substrate 10; a first electrode 22 formed on one primary surface of the first substrate 10; a first resin layer 32 of a thermosetting resin formed on said one primary surface of the first substrate 10, burying the first electrode 22; a second substrate...

20060220221 - Semiconductor device and a manufacturing method of the same: The present invention enhances the reliability of a semiconductor device. The semiconductor device includes a package substrate having a dry resist film which covers some conductive portions out of a plurality of conductive portions formed on a main surface and a back surface and is formed of a film, a...

20060220223 - Reactive nano-layer material for mems packaging: According to one embodiment an apparatus and method for MEMS packaging including a reactive nano-layer is presented. The apparatus comprises a substrate, an environmentally sensitive device on the substrate, a cap to fit over the device, and a hermetic seal between the cap and the substrate. The hermetic seal comprises...

20060220224 - Thermally enhanced three-dimensional package and method for manufacturing the same: A thermally enhanced three-dimensional (3D) package is disclosed. The package includes a heat sink having an opening and a stiffener ring inside the opening. The stiffener ring has a first surface and a second surface. A first substrate of a first package is disposed inside the opening and secured to...

20060220225 - Semiconductor packages and methods of manufacturing thereof: Described are semiconductor package devices with improved reliability and methods of manufacturing thereof. In one embodiment, a package device is disclosed that includes a chip having an active surface and a coupling surface opposite the active surface, where the chip has one or more integrated circuits and bumps. The device...

20060220226 - Integrated heat spreader with intermetallic layer and method for making: Integrated heat spreader and die coupled with solder in a manner forming an intermetallic compound having a higher liquidus temperature than the liquidus temperature of the solder used to create the intermetallic compound are described herein....

20060220233 - Electronic component mounting package and package assembled substrate: A package of the present invention has a laminate structure of a plurality of ceramic layers, and includes a cavity for housing a light emitting element. A mount surface is defined on a side surface parallel with the depth direction of the cavity. A pair of external electrodes each including...

20060220227 - High density integrated circuit having multiple chips and employing a ball grid array (bga) and method for making same: High density integrated circuits and more particularly to a high density integrated circuit incorporating a multiplicity of functional chips arranged on a substrate comprised of a plurality of dielectric and conductive layers which interface the semiconductor dies with a ball gate array (BGA) arranged on the underside of the substrate...

20060220228 - Methods and apparatus for a flexible circuit interposer: Methods and apparatus for testing a semiconductor device are disclosed. A flexible circuit interposer includes a flexible circuit substrate which allows in-situ probing of an attached device during, for example, circuit debugging, assembly qualification, and the like. A first set of pads is configured in a predetermined pattern on the...

20060220229 - Methods and apparatus for a flexible circuit interposer: A flexible circuit interposer includes a flexible circuit substrate which allows in-situ probing of an attached device during, for example, circuit debugging, assembly qualification, and the like. A first set of pads (and optionally a fourth set of pads) is configured in a predetermined pattern on the bottom surface of...

20060220231 - Semiconductor device and manufacturing method therefor: To provide a semiconductor device that enables high integration degree, and a manufacturing method therefor. A multi-chip module according to an embodiment of the present invention includes: a first semiconductor chip having a first bonding pad; a second semiconductor chip having a second bonding pad thinner than the first bonding...

20060220230 - Semiconductor device and method of manufacturing thereof: In order to implement a high-density high-performance semiconductor system small in size, there is provided a method for implementing three-dimensional connection between a plurality of semiconductor chips differing from each other with the shortest metal interconnect length, using penetration electrodes, thereby enabling a fast operation at a low noise level,...

20060220232 - Semiconductor device module and manufacturing method of semiconductor device module: In a module for an optical device as a semiconductor device module of the present invention, a bonding wire that electrically connects a substrate on which a conductor wiring is formed and an image pickup element as a semiconductor element is covered with a cover, and a holder as a...

20060220235 - Semiconductor device and insulating substrate for the same: A semiconductor device including: an insulating substrate including a ceramic substrate having first and second principal surfaces, a first metallic conductor fixed on the first principal surface, and a second metallic conductor fixed on the second principal surface; a semiconductor element disposed on the first metallic conductor on the first...

20060220234 - Wire bonded wafer level cavity package: A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges...

20060220236 - Semiconductor device with power module housed in casing: An electrically insulating member is provided between a bus bar of an IPM and a nearby casing so as to electrically insulate the casing from the bus bar of the IPM. Above the portion where electrical insulation is necessary, a bracket provided for supporting a component-to-be supported is secured to...

20060220237 - Electronic substrate: A substrate for mounting a device is disclosed. The substrate includes at least one transition for providing an RF connection to a lead of the device, the lead extending from a device input to an otherwise free end. The transition comprises two spaced apart electrically coupled members, the first member...

20060220238 - Multi-functional metal shield case and method for making the same: A multi-functional metal shield case and a method for making the same are provided. The multi-functional metal shield case includes a metal main body and an electrically non-conductive and heat conductive silicon layer. The metal main body includes a base and sidewalls integrally bent along edges of the base, and...

20060220240 - Analytic structure for failure analysis of semiconductor device: An analytic structure includes a plurality of analytic fields formed on a predetermined region of a semiconductor substrate; semiconductor transistors arranged in the analytic fields to compose an array structure, each transistor having a gate electrode and an impurity region; wordlines arranged crosswise on the analytic fields and connecting the...

20060220239 - Lga socket with emi protection: A socket is provided which has an insulative housing surrounding a metal substrate. The substrate has an array of apertures which are located in spatially arranged order to accommodate the precise pattern desired for the device to be connected. Contact assemblies include stamped and formed contacts having an insulative plastic...

20060220241 - Packaged semiconductor device and method of manufacture using shaped die: A semiconductor packaging technique provides for a semiconductor device with improved electrical and thermal performance. According to one embodiment of the invention, die edges are shaped before encapsulation to move the peripheral area of the die, which is more susceptible to stress and cracking, further inside the molding compound. This...

20060220243 - Electronic device package: An electronic device package comprises a substrate, a die, and a material having a Young's modulus of between about 0.1 megapascals and about 20 megapascals (at a solder reflow temperature) for attaching the die to the substrate. In one embodiment, the package utilizes a material having a Young's modulus of...

20060220242 - Method for producing flexible printed wiring board, and flexible printed wiring board: The present invention provides a method for producing a flexible printed wiring board which allows formation of a bump on a wire trace even in a high-density mounting process, and a flexible printed wiring board which realizes high-density mounting with high reliability. In the method for producing a flexible printed...

20060220246 - Bump land structure of circuit substrate for semiconductor package: A bump land structure of a circuit substrate for a semiconductor package may have a combination of an SMD type bump land structure and an NSMD type bump land structure. A lower portion of a solder mask and a lower layer of a bump land may form the SMD type...

20060220244 - Contact pad and bump pad arrangement for high-lead or lead-free bumps: A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with...

20060220245 - Flip chip package and the fabrication thereof: The invention discloses a flip chip package using an interposer to electrically and mechanically connect the chip and the carrier. The interposer comprises: an insulation layer, two adhesive layers and a plurality of conductive elements. The insulation layer is also the mechanical support of interposer and has one adhesive layer...

20060220247 - Semiconductor device and manufacturing method therefor: A semiconductor device includes: a semiconductor substrate; an insulation layer which is disposed on the semiconductor substrate and includes a groove formed on a second surface of the insulation layer, opposite from a first surface of the insulation layer facing the semiconductor substrate; and a conductive part disposed on the...

20060220248 - Low-temperature chemical vapor deposition of low-resistivity ruthenium layers: A low-temperature chemical vapor deposition process for depositing of a low-resistivity ruthenium metal layers that can be used as barrier/seed layers in Cu metallization schemes. The method includes providing a substrate in a process chamber of a deposition system, forming a process gas containing a ruthenium carbonyl precursor vapor and...

20060220249 - Nobel metal barrier and seed layer for semiconductors: A barrier and seed layer for a semiconductor damascene process is described. The seed layer is formed from a noble metal with an intermediate region to prevent oxidation of the barrier between the barrier and noble metal layers to prevent oxidation of the barrier layer....

20060220250 - Crack stop and moisture barrier: A design for a crack stop and moisture barrier for a semiconductor device includes a plurality of discrete conductive features formed at the edge of an integrated circuit proximate a scribe line. The discrete conductive features may comprise a plurality of staggered lines, a plurality of horseshoe-shaped lines, or a...

20060220253 - Porous film, composition and manufacturing method, interlayer dielectric film, and semiconductor device: A porous film-forming composition comprising (A) a curable silicone resin having a Mn of at least 100, (B) a micelle-forming surfactant, and (C) a compound which generates an acid upon pyrolysis remains stable during storage. The composition is coated and heat treated to form a porous film which has flatness,...

20060220251 - Reducing internal film stress in dielectric film: A method of forming a film. The method comprises depositing a porous film. The porous film has active end groups; and preventing cross-linking among said active end groups, wherein the end groups are capped with less reactive or unreactive groups....

20060220252 - Semiconductor device and driving method thereof: The present invention provides a semiconductor device including a memory with a simple structure, an inexpensive semiconductor device, a manufacturing method and a driving method thereof. One feature is that, in a memory which has a layer including an organic compound as a dielectric, by applying a voltage to a...

20060220254 - Semiconductor device which prevents peeling of low-permittivity film by using multilevel interconnection: A semiconductor device includes an alignment mark which is arranged adjacent to each corner of a semiconductor chip, and a plug which contacts the alignment mark. The alignment mark is formed by part of the uppermost interconnection layer in a multilevel interconnection which is formed on the semiconductor chip and...

20060220255 - Terminal layer setting method for semiconductor circuit having a plurality of circuit layers, storage media storing terminal layer setting program, storage media storing a wiring terminal extension processing program and terminal extending component used: A terminal layer setting method according to the present invention is a method for a computer setting up a terminal layer of a semiconductor circuit having a plurality of wiring layers, comprises the steps of obtaining various kinds of information such as placement information relating to a plurality of cells...

20060220256 - Encapsulant cavity integrated circuit package system: An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity....

20060220258 - Method for mounting semiconductor chips on a substrate and corresponding assembly: A method for mounting semiconductor chips on a substrate using flip-chip technology and a corresponding assembly are provided, which method includes the steps of: a) providing a semiconductor chip having a component region including components and an edge region, a mounting region containing a plurality of bonding pads being situated...

20060220257 - Multi-chip package and method for manufacturing the same: A multi-chip package includes a first chip group including at least one semiconductor chip on a substrate. The first chip group may be sealed to form a first package body. Connecting test terminals to ball pads allows package-level testing of the first chip group. A second chip group including at...

20060220259 - Multi-chip structure and method of assembling chips: A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is...

20060220260 - Semiconductor chip package and manufacturing method thereof: An acceleration sensor chip package comprises a frame section, a first semiconductor chip corresponding to an MEMS chip having a plurality of first bumps, a second semiconductor chip having a plurality of second bumps, a substrate on which the first and second semiconductor chips are mounted in parallel with each...

20060220261 - Semiconductor device: A semiconductor device according to the invention of the present application comprises a semiconductor substrate including a first surface and a second surface corresponding to a back surface with respect to the first surface and having first through electrodes which extend through the first surface and the second surface, semiconductor...

20060220262 - Stacked die package: A stacked die package includes a substrate or interposer board that includes a contact area on a top surface and landing pads surrounding the contact area. Solder pads are disposed on an opposite side of the substrate. The solder pads are electrically connected with the landing pads by inner board...

20060220263 - Semiconductor device to be applied to various types of semiconductor package: A plurality of first pads for bonding is arranged in a central portion of a semiconductor device in a longitudinal direction of the device. In an edge portion of the semiconductor device, a plurality of second pads for bonding is arranged in the longitudinal direction of the device. The first...

20060220264 - Mounting structure and mounting method of a semiconductor device, and liquid crystal display device: A mounting structure of a semiconductor device includes an electroconductive film provided on a substrate. An insulating film is formed on the electroconductive film, and provided with an opening portion to expose a part of the electroconductive film, and its internal stress is set to serve as a compression stress....

20060220265 - Alignment mark for semiconductor device, and semiconductor device: An alignment mark for a semiconductor device is provided. The alignment mark defines a plane pattern and includes a conductive layer embedded in a recessed section provided in an insulation layer, and an oxidation barrier layer provided on the conductive layer, wherein an area occupancy ratio of the recessed section...