Active solid-state devices (e.g., transistors, solid-state diodes) inventions 09/06

20060208247 - Method and system for an integrated circuit supporting auto-sense of voltage for drive strength adjustment: Certain embodiments of the invention may be found in a method for integrated circuit supporting auto-sense of voltage for drive strength adjustment. The method may comprise detecting an input voltage received at an auto-sense pad integrated on a mobile multimedia processing (MMP) chip. The input voltage may be a power...

20060208248 - Nonvolatile nanochannel memory device using organic-inorganic complex mesoporous material: A memory device of the current invention includes a memory layer having nanochannels sandwiched between an upper electrode and a lower electrode, in which the memory layer is made of an organic-inorganic complex for use in formation of nanopores, and has metal nanoparticles or metal ions fed into the nanopores....

20060208249 - Programmable conductor memory cell structure and method therefor: In programmable conductor memory cells, metal ions precipitate out of a glass electrolyte element in response to an applied electric field in one direction only, causing a conductive pathway to grow from cathode to anode. The amount of conductive pathway growth, and therefore the programming, depends, in part, on the...

20060208250 - Semiconductor device based on si-ge with high stress liner for enhanced channel carrier mobility: The carrier mobility in transistor channel regions of Si—Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate...

20060208252 - Molecular rectifiers: The present invention relates to molecules exhibiting rectifying properties. In particular, the present invention relates to a molecular rectifying assembly, comprising the general structure METAL1-CON1-BRIDGE-CON2-METAL2 in which CON1 and CON2 are a connecting group or connecting part and independently of each other are molecular groups bound to METAL1,2 in such...

20060208251 - Organic semiconductor device and producing method therefor: The invention provides an organic semiconductor device with a p-type organic semiconductor layer sandwiched between a source electrode and a drain electrode including an n-type organic semiconductor layer formed in an intermediate portion of the p-type organic semiconductor layer and a gate electrode embedded in the n-type organic semiconductor layer,...

20060208253 - Organic thin film transistor, flat display device including the same, and method of manufacturing the organic thin film transistor: An organic thin film transistor, a flat display device including the same, and a method of manufacturing the organic thin film transistor are disclosed. In one embodiment, the organic thin film transistor includes: i) a substrate, ii) a gate electrode disposed on the substrate, iii) a gate insulation film disposed...

20060208255 - Stressed organic semiconductor: A semiconductor device and method of manufacturing the semiconductor device. The semiconductor device includes: a substrate; an organic semiconductor material coupled to the substrate at an interface therebetween; and an actuator provided for use with the substrate and/or the organic semiconductor. The actuator applies a mechanical force to the substrate...

20060208254 - Techniques and systems for analyte detection: Techniques are used to detect and identify analytes. Techniques are used to fabricate and manufacture sensors to detect analytes. An analyte (810) is sensed by sensors (820) that output electrical signals in response to the analyte. The electrical signals may be preprocessed (830) by filtering and amplification. In one embodiment,...

20060208256 - Self-calibration in non-contact surface photovoltage measurement of depletion capacitance and dopant concentration: The surface photovoltage dopant concentration measurement of a semiconductor wafer is calibrated by biasing the semiconductor wafer into an avalanche breakdown condition in a surface depletion region; determining a contact potential difference value corresponding to an avalanche breakdown; determining small signal ac-surface photovoltage value corresponding to an avalanche breakdown; and...

20060208257 - Method for low-temperature, hetero-epitaxial growth of thin film csi on amorphous and multi-crystalline substrates and c-si devices on amorphous, multi-crystalline, and crystalline substrates: A crystalline, highly textured or biaxially textured, foreign (non-silicon) material, which is closely lattice-matched to silicon, is deposited on a glass or other amorphous or multi-crystalline substrate to provide a template for hetero-epitaxial growth of highly ordered crystalline silicon semiconductor layers on such substrates. This process enables crystalline silicon semiconductor...

20060208258 - Semiconductor device, and method of fabricating the same: A multi-layered gate electrode of a crystalline TFT is constructed as a clad structure formed by deposition of a first gate electrode, a second gate electrode and a third gate electrode, to thereby to enhance the thermal resistance of the gate electrode. Additionally, an n-channel TFT is formed by selective...

20060208259 - Cmos image sensors and methods for fabricating the same: CMOS image sensors and methods for fabricating the same are disclosed. A disclosed CMOS image sensor comprises: a semiconductor substrate; a photo diode; a microlens located over the photo diode; and a color filter layer located over the microlens....

20060208260 - Powdered fluorescent material and method for manufacturing the same, light-emitting device, and illumination apparatus: Powdered fluorescent material excited by visible light that emits visible light has particles with particle sizes of 20 μm or less in the content of below 2% by mass. The method for manufacturing a powdered fluorescent material comprises the steps of: sintering raw material powder of the fluorescent material; and...

20060208261 - Semiconductor device and manufacturing method thereof: A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposite to the first conduction type located between...

20060208262 - Light emitting device and illumination apparatus: A light-emitting device and illumination apparatus using the same are provided. The light-emitting device includes a semiconductor light-emitting element that emits blue-violet or blue light and a fluorescent material that absorbs the light emitted by the semiconductor light-emitting element and emits fluorescence of wavelengths different from the light, wherein the...

20060208263 - Light emitting device, method of manufacturing the same, and manufacturing apparatus therefor: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of...

20060208264 - Nitride semiconductor led improved in lighting efficiency and fabrication method thereof: A nitride semiconductor LED improved in lighting efficiency and a fabrication method thereof, in which an n-doped semiconductor layer is formed on a substrate. An active layer is formed on the n-doped semiconductor layer to expose at least a partial area of the n-doped semiconductor layer. A p-doped semiconductor layer...

20060208265 - Light emitting diode and light emitting diode array: A light emitting diode array comprises compound semiconductor layers epitaxially grown on a p-type GaAs conductive layer 11 formed on a semi-insulating GaAs substrate 30. The epitaxial layer is isolated and divided into a plurality of light emitting parts 1 which function as a light emitting diode. A Si-doped n-type...

20060208266 - Method for manufacturing an organic semiconductor device, as well as organic semiconductor device, electronic device, and electronic apparatus: A method for manufacturing an organic semiconductor device having a gate electrode, a source electrode, a drain electrode, an organic semiconductor layer, a gate insulation layer, and a substrate, including: forming, on the substrate, an underlayer that contains an organic polymer material having a liquid crystal core and is oriented...

20060208268 - Light emitting device: A light-emitting device can include a blue LED chip that is covered in a sealing resin composed of a filling resin mixed with a wavelength conversion material, such as a yellow fluorescent material. Light from the blue LED chip is mixed with a light from the yellow fluorescent material to...

20060208269 - Side-emitting led package having scattering area and backlight apparatus incorporating the led lens: The invention provides an LED package and a backlight device incorporating the LED lens. The LED package has a bottom surface and a light exiting surface cylindrically extended around a central axis of the package from the bottom surface. Also, a reflecting surface is positioned on an opposite side of...

20060208267 - Side-emitting solid-state semiconductor light emitting device: A side-emitting solid-state semiconductor light emitting device (light emitting diode) comprises a light emitting diode package and a lens, wherein the lens is mounted on the front surface of the light emitting diode package to receive the light emitted from the light emitting diode and redirect the received light by...

20060208270 - Borate phosphor materials for use in lighting applications: Boron containing phosphor compositions having the formulas (1) M3Ln2(BO3)4 doped with at least one activator selected from the group of Eu2+, Mn2+, Pb2+, Ce3+, Eu3+, Tb3+, and Bi3+ where M is at least one of Mg, Ca, Sr, Ba, or Zn, and Ln is at least one of Sc, Y,...

20060208271 - Light source apparatus and fabrication method thereof: A light source apparatus and a fabrication method thereof can prevent light interference between light emitting devices adjacent to each other by forming a groove in a sub-mount and bonding a light emitting device to the groove, enhance heat radiating effect as well as luminous efficiency by collecting light emitted...

20060208272 - Method for filling recessed micro-structures with metallization in the production of a microelectronic device: A method for filling recessed micro-structures at a surface of a semiconductor wafer with metallization is set forth. In accordance with the method, a metal layer is deposited into the micro-structures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to...

20060208273 - Nitride micro light emitting diode with high brightness and method of manufacturing the same: The present invention relates to a nitride micro light emitting diode (LED) with high brightness and a method of manufacturing the same. The present invention provides a nitride micro LED with high brightness and a method of manufacturing the same, wherein a plurality of micro-sized luminous pillars 10 are formed...

20060208274 - Electrical fuse for silicon-on-insulator devices: An apparatus for providing an electrical fuse is provided. An electrical fuse is patterned from the active layer of a semiconductor-on-insulator (SOI) wafer. One shape of the electrical fuse may be a first and second portion electrically coupled via a third section. The third section is typically thinner than the...

20060208276 - Semiconductor device and method of producing the same, and power conversion apparatus incorporating this semiconductor device: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement...

20060208275 - Transflective liquid crystal display panel and manufacturing method thereof: A transistor array panel comprises a substrate, a transparent electrode disposed on the substrate, a gate line disposed on the substrate, a gate insulating layer disposed on the transparent electrode and the gate line, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode...

20060208277 - Bipolar transistor with a low saturation voltage: A bipolar transistor with a specific area resistance less than about 500 mOhms·mm2 comprises a first semiconductor region of a first conductivity type defining a collector region (2). A second semiconductor region of a second conductivity type defines a base region (3). A third semiconductor region of the first conductivity...

20060208278 - Two-wavelength semiconductor laser device and method of manufacturing the same: A two-wavelength semiconductor laser device includes a first conductive material substrate having thereon first and second regions separated from each other. A first semiconductor laser diode is formed on the first region. A non-active layer is formed on the second region and has the same layers as those of the...

20060208280 - Group iii nitride field effect transistors (fets) capable of withstanding high temperature reverse bias test conditions: Group III Nitride based field effect transistor (FETS) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (VDS) of about 56 volts, a gate to source voltage (Vgs) of from about −8 to about −14 volts and a temperature of about...

20060208279 - Multi-layer structure for use in the fabrication of integrated circuit devices and methods for fabrication of same: A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The structure has, on a substrate, a channel layer, spacer layer on the channel...

20060208281 - Contact in planar nrom technology: A method for fabricating a non-volatile memory array includes placing contacts over bit lines in a self-aligned manner. The placing includes forming self-aligned contact holes bounded by a second insulating material resistant to the removal of a first insulating material previously deposited over the bit lines, and depositing contact material,...

20060208282 - Memory cell arrays: A memory device includes memory cells, bit lines, active areas, and transistors formed in each active area and electrically coupling memory cells to corresponding bit lines. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit...

20060208283 - Semiconductor device: A semiconductor device includes a plurality of first word lines which extend in a first direction, a plurality of second word lines which extend in a direction orthogonal to the first direction, a plurality of selection circuits which are provided at intersections of the first word lines and the second...

20060208284 - Method for manufacturing a microlens substrate and method for manufacturing a liquid crystal panel: Disclosed herein is a method for manufacturing a microlens substrate which is excellent in chemical resistance and light fastness to intense light irradiation, and is capable of forming a microlens substrate of a high accuracy of form. The method includes the steps of: forming a lens-shaped curve at a surface...

20060208285 - Image sensor with embedded photodiode region and fabrication method thereof: An image sensor in which a plurality of pixels having at least a photodiode, a reset transistor, and source follower transistor are formed, wherein each pixel comprises an electrical-charge transfer gate transistor between the photodiode and reset transistor, and a floating diffusion region constituting a node connecting the reset transistor...

20060208286 - Method for manufacturing semiconductor device and semiconductor device: A method of forming a crystal grain for use in a semiconductor manufacturing process, the method including the steps of forming an oxide silicon film on a glass substrate, etching at least one hole at a predetermined location in the oxide silicon film, forming an amorphous silicon film over the...

20060208287 - Lateral programmable polysilicon structure incorporating polysilicon blocking diode: A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of...

20060208288 - Imaging with gate controlled charge storage: A pixel cell comprises a photo-conversion device for generating charge and a gate controlled charge storage region for storing photo-generated charge under control of a control gate. The charge storage region can be a single CCD stage having a buried channel to obtain efficient charge transfer and low charge loss....

20060208289 - Mos image sensor: A semiconductor image sensor includes: a semiconductor substrate having a number of pixels disposed in a matrix shape, the semiconductor substrate comprising a first region including a charge accumulation region of a photodiode and a floating diffusion and a second region including transistors, each having a gate electrode and source/drain...

20060208292 - Image pickup device and camera with expanded dynamic range: The image pickup device of the invention has a path deeper in a semiconductor substrate, than a region wherein a channel is formed, upon turning on a first MOS transistor, under a gate thereof. The path is arranged by forming a P-type layer for forming a potential barrier, within a...

20060208290 - Semiconductor light emitting devices and methods: A method for producing an optical output, including the following steps: providing first and second electrical signals; providing a bipolar light-emitting transistor device that includes collector, base, and emitter regions; providing a collector electrode coupled with the collector region and an emitter electrode coupled with the emitter region, and coupling...

20060208291 - Solid state image pickup device and camera: A solid state image pickup device which can prevent color mixture by using a layout of a capacitor region provided separately from a floating diffusion region and a camera using such a device are provided. A photodiode region is a rectangular region including a photodiode. A capacitor region includes a...

20060208293 - Color filter substrate for liquid crystal display device and method for fabricating the same: A method for fabricating a color filter substrate for a liquid crystal display device having a RGBW pixel structure, wherein a white sub-color filter layer is formed during a process of forming a planarization layer with a step, and a spacer pattern is formed on the white sub-color filter layer...

20060208294 - Method of manufacturing magnetic random access memory including middle oxide layer: In a magnetic random access memory (MRAM) having a transistor and a magnetic tunneling junction (MTJ) layer in a unit cell, the MTJ layer includes a lower magnetic layer, an oxidation preventing layer, a tunneling oxide layer, and an upper magnetic layer, which are sequentially stacked. The tunneling oxide layer...

20060208295 - Ferroelectric memory device: The present invention provides a ferroelectric memory device (101) having plural memory cells each composed of a memory cell transistor and a memory cell capacitor, in which the respective memory cell capacitor (101a) comprises a lower electrode (2) that is independent for each of the memory cell capacitors, a ferroelectric...

20060208296 - Novel structure and method to fabricate high performance mtj devices for mram applications: A high performance MTJ in an MRAM array is disclosed in which the bottom conductor has an amorphous Ta capping layer. A key feature is a surfactant layer comprised of oxygen that is formed on the Ta surface. The resulting smooth and flat Ta capping layer promotes a smooth and...

20060208297 - Polymer memory having a ferroelectric polymer memory material with cell sizes that are asymmetric: A polymer memory and its method of manufacture are provided. One multi-layer construction of the polymer memory has two sets of word lines and a set of bit lines between the word lines. The word lines of each set of word lines have center lines that are spaced by a...

20060208298 - Memory cell of dynamic random access memory and array structure thereof: A DRAM cell including a trench capacitor structure, a transistor and a stacked capacitor structure is provided. A first electrode of the trench capacitor structure is disposed in the substrate at the bottom of a trench. A second electrode of the trench capacitor structure is disposed in the trench. The...

20060208299 - Semiconductor device having stacked decoupling capacitors: A semiconductor device having transistors formed on different layers of a stack structure includes a stacked capacitor cluster, wherein a stacked capacitor of the stacked capacitor cluster includes an insulation layer of a transistor of the semiconductor device, and at least a first conduction layer and a second conduction layer...

20060208300 - Finfet-type semiconductor device and method for fabricating the same: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and...

20060208305 - In-service reconfigurable dram and flash memory device: A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of...

20060208302 - Non-volatile memory device having charge trap layer and method of fabricating the same: A non-volatile memory device having a charge trap layer and a method of fabricating the same are provided. The non-volatile memory device includes a semiconductor substrate having an active region and a field region in contact with the active region. A trench isolation layer is formed within the semiconductor substrate...

20060208303 - Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same: The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer,...

20060208301 - Semiconductor memory device and method of driving a semiconductor memory device: A semiconductor memory device includes a semiconductor layer; a source layer provided in the semiconductor layer; a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer; a gate insulation film provided on the body region; and...

20060208304 - Three-dimensional memory devices: Memory devices are disclosed. One example of a memory device may include two layers of memory arrays each containing at least four memory cells. In particular, the memory device includes two word lines commonly shared by the two layers of the memory arrays, with the word lines coupled with the...

20060208309 - Non-planar flash memory having shielding between floating gates: A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in the same column. The second plurality of memory cells is coupled to the first plurality of memory cells...

20060208306 - Single-poly eeprom: The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+...

20060208307 - Split gate flash memory and manufacturing method thereof: A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling...

20060208308 - Use of selective epitaxial silicon growth in formation of floating gates: Apparatus utilizing epitaxial silicon growth on a base structure of a floating gate of a floating-gate memory cell to increase the available coupling area of the floating gate while reducing the spacing between adjacent memory cells. The epitaxial silicon growth facilitates a reduction in spacing between adjacent cells beyond the...

20060208310 - Method and apparatus for a flash memory device comprising a source local interconnect: A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer...

20060208311 - Quantum circuit and quantum computer: The present invention realizes a quantum circuit and a quantum computer capable of performing multi-bit quantum computation. A quantum bit is represented by the polarization directions of light, a sequence of polarized light pulses representing a quantum bit string is sequentially supplied, and the amount of polarization rotation applied to...

20060208312 - Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and ic card: A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function of storing electric charge and formed on the...

20060208313 - Double gate fet and fabrication process: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material,...

20060208314 - Semiconductor device and manufacturing method for semiconductor device: To provide a semiconductor device capable of reducing a gate capacitance, and preventing breakdown of a gate oxide film if a large amount of current flows. A semiconductor device according to an embodiment of the present invention includes: an epitaxial layer; a channel region formed on the epitaxial layer; a...

20060208315 - Semiconductor element and semiconductor memory device using the same: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures...

20060208316 - High performance tunneling-biased mosfet and a process for its manufacture: A semiconductor structure and a method for its manufacture are provided. In one example, the structure includes a well region doped with a first type dopant (e.g., a P-type or N-type dopant). A gate pedestal formed over the well region has two ends, one of which at least partially overlies...

20060208317 - Layout structure of semiconductor cells: A layout structure of semiconductor cells is described. The layout structure includes multiple semiconductor cells, wherein at least one pair of cells has an overlap member part between them, so that the area of the pair of cells is smaller than the sum of respective areas of the two cells....

20060208318 - Mos field effect semiconductor device and method for fabricating the same: A high-performance CMOS field effect semiconductor device using metal gate electrodes. An n-type gate electrode and a p-type gate electrode are formed by using a same metal and differ in nitrogen concentration. As a result, a high-performance CMOS field effect semiconductor device having the n-type gate electrode and the p-type...

20060208319 - Semiconductor memory device and method of manufacturing the same, a method of manufacturing a vertical misfet and a vertical misfet, and a method of manufacturing a semiconductor device and a semiconductor device: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with...

20060208320 - Mis-type semiconductor device: A MIS-type semiconductor device is configured with a semiconductor substrate, and a p-type MIS transistor, and a n-type MIS transistor which is provided on the semiconductor substrate, the p-type MIS transistor including a gate electrode which is made of Ge and one element which is selected from the group consisting...

20060208321 - Selectable open circuit and anti-fuse element: An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a suicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor...

20060208322 - Method and apparatus for removing adjacent conductive and non-conductive materials of a microelectronic substrate: A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate material (such as borophosphosilicate glass) having an aperture with a conductive material (such as platinum) disposed in the aperture and a fill material (such as...

20060208323 - Dual gate dielectric thickness devices: A semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: one or more FETs of a first polarity and one or more FETs of a second and opposite polarity, at least one of the one or more FETs of the first polarity having a gate...

20060208324 - Linear device: A linear MISFET is resilient, flexible and capable of being fabricated into an integrated circuit in an arbitrary shape. Typically a structure includes a source region and drain region arranged in parallel. However, since a channel length of the MISFET for determining the electric characteristics thereof is determined by a...

20060208325 - Semiconductor device with gate insulating film and manufacturing method thereof: A MISFET includes: a p type substrate having a channel region with an impurity concentration C; an insulating film made of SiO2 and formed on the channel region; and an insulating film made of HfSiON and formed on the gate insulating film. When there is a postulated MISFET including a...

20060208327 - Acceleration sensor and method of manufacturing acceleration sensor: An acceleration sensor includes a semiconductor substrate, a sensing element formed on the semiconductor substrate, a bonding frame made of polysilicon which is formed on the semiconductor substrate and surrounds the sensing element, and a glass cap which is bonded to a top surface of the bonding frame made of...

20060208326 - Method of fabrication of ai/ge bonding in a wafer packaging environment and a product produced therefrom: A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between...

20060208328 - Electrostatic micro switch, production method thereof, and apparatus provided with electrostatic micro switch: An electrostatic micro switch includes a fixed electrode disposed on a fixed substrate; a movable substrate elastically supported by the fixed substrate, the movable substrate including a movable electrode facing the fixed electrode. The movable substrate includes a semiconductor including a plurality of regions having different values of resistivity and...

20060208329 - Semiconductor device including semiconductor memory element and method for producing same: A wafer, in which a plurality of rectangular regions are defined on the face of the wafer by streets arranged in a lattice pattern, and a semiconductor memory element is disposed in each of the rectangular regions, is divided along the streets to separate the rectangular regions individually, thereby forming...

20060208330 - Method and structure to reduce optical crosstalk in a solid state imager: Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away and disposed of as waste during fabrication are left as conserved sections. These conserved sections are used to amend the properties and performance of the imager...

20060208331 - Miniature optical element for wireless bonding in an electronic instrument: A method of manufacturing an optical element including the steps of: forming a through hole in a semiconductor element which has an optical section and an electrode electrically connected to the optical section; and forming a conductive layer extending from a first surface of the semiconductor element on which the...

20060208332 - Schottky diode and method of manufacture: A Schottky diode capable of sustaining a breakdown voltage of greater than about 250 volts and a method for its manufacture. An epitaxial layer disposed on a semiconductor substrate has a thickness of at least about 15 micrometers and an impurity concentration ranging from about 1×1014 atoms per cubic centimeter...

20060208333 - Image sensor: A buried oxide is provided in a substrate of a photodiode so as to be opposed to a cathode and is in contact with a lower end of a depletion layer. The buried oxide is polarized owing to charges forming the depletion layer and thus works as a capacitor. A...

20060208334 - Semiconductor device having super junction structure and method for manufacturing the same: A super junction type semiconductor device includes a first semiconductor layer of a first conductivity type, a super junction structure, and a second semiconductor layer of a second conductivity type. The thickness of the second semiconductor layer varies such that the thickness in the peripheral region is greater than that...

20060208337 - Enhancing strained device performance by use of multi narrow section layout: A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between...

20060208335 - Films deposited at glancing incidence for multilevel metallization: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure that includes a vapor-deposited dielectric material. The dielectric material has a predetermined microstructure formed using a glancing angle deposition (GLAD) process. The microstructure includes columnar...

20060208336 - Semiconductor structure having a strained region and a method of fabricating same: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent...

20060208338 - Nonvolatile memory devices and methods of forming the same: Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on...

20060208339 - Semiconductor device and mim capacitor: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from...

20060208340 - Protection device for handling energy transients: A protection device for handling energy transients includes a plurality of basic unit Zener diodes connected in series to achieve a desired breakdown voltage. Each of the basic unit Zener diodes is formed in a first-type substrate. Each of the basic unit Zener diodes comprises a second-type well formed in...

20060208341 - Bonded substrate and method of making same: Ge/Si and other nonsilicon film heterostructures are formed by hydrogen-induced exfoliation of the Ge film which is wafer bonded to a cheaper substrate, such as Si. A thin, single-crystal layer of Ge is transferred to Si substrate. The bond at the interface of the Ge/Si heterostructures is covalent to ensure...

20060208342 - Silicon-on-nothing metal oxide semiconductor field effect transistor and method of manufacturing the same: The present invention relates to a SON MOSFET and method of manufacturing the same, in which a blister is formed within a silicon substrate, thus improving the disadvantages of a bulk structure and a Silicon-On-Insulator (SOI) structure at the same time. The SON MOSFET according to the present invention comprises...

20060208343 - Micromechanical strained semiconductor by wafer bonding: One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a silicon substrate using a Local Oxidation of Silicon (LOCOS) process, and a silicon membrane is bonded to the substrate....

20060208346 - Flat-shaped battery: A flat-shaped battery according to the present invention includes: an outer can having an opening at its upper end; a gasket disposed at an inner edge of the opening; and a sealing plate that seals the opening together with the gasket. In this flat-shaped battery, the outer can houses a...

20060208344 - Lead frame panel and method of packaging semiconductor devices using the lead frame panel: A lead frame panel (40) includes a body (42) having an array of die support areas (44) for receiving respective semiconductor dies. The die support areas (44) are surrounded by leads (46). Adjacent rows of leads are coupled by half-etched connection bars (48), such that each half-etched portion of the...

20060208345 - Semiconductor chip and semiconductor device including the same: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of...

20060208347 - Semiconductor device package: A semiconductor device package includes a semiconductor device mounted and electrically coupled to the upper surface of a substrate, a package body encapsulating the semiconductor device against a portion of the upper surface of the substrate; and a metal ring formed on the upper surface of the substrate and connected...

20060208348 - Stacked semiconductor package: In a stacked semiconductor package, since electric power is supplied to a second semiconductor package through a first semiconductor package, a power supply path becomes complicated and fluctuation of its inductance becomes large, whereby power bounce occurs to reduce signal quality and also prevent high speed signal communication. Therefore, according...

20060208349 - Semiconductor device and manufacturing method for the same: A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip,...

20060208350 - Support elements for semiconductor devices with peripherally located bond pads: A support structure for a semiconductor device with peripherally disposed contacts includes a support substrate and at least one conductive column protruding from the support substrate. The at least one conductive column is configured to contact an outer connector on a peripheral edge of a semiconductor device that may be...

20060208351 - Semiconductor devices including peripherally located bond pads, intermediates thereof, and assemblies and packages including the semiconductor devices: A semiconductor device package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by forming a conductive via that extends substantially through a substrate blank and laterally across a street...

20060208352 - Strain silicon wafer with a crystal orientation (100) in flip chip bga package: A method and system is disclosed for better packaging semiconductor devices. In one example, a semiconductor device package comprises a package substrate, at least one die with an orientation of <100> placed on the substrate with electrical connections made between the package substrate and the die, and an underfill fillet...

20060208353 - Semiconductor cooling system and process for manufacturing the same: A cooling device for an element such as a microprocessor in a computer, and a process for manufacturing the cooling device. The cooling device provides an effective structure of cooling a microprocessor by providing a metallic filler layer and a metal plate layer spreading out heat generated from the microprocessor,...

20060208354 - Thermal interface structure and process for making the same: A thermal interface structure (10, 20) is provided for a highly conductive thermal interface between an electronic component and a cooling device for dissipating heat generated by the electronic component. The thermal interface structure includes a matrix (12, 22) and a plurality of carbon nanotubes (14, 24) incorporated in the...

20060208355 - routing configuration for high frequency signals in an integrated circuit package: An apparatus for routing a high-speed signal is disclosed, having a signal router and a plurality of projections extending therefrom. The projections are separated from each other by a distance between about 0.25 and 0.125 of λgo, wherein λgo is a guide wavelength at cut-off frequency of the first signal...

20060208356 - Wiring board and method of manufacturing the same: A wiring board includes an insulating layer in which a semiconductor chip is embedded, and a wiring structure connected to the semiconductor chip. A reinforcing member reinforcing the insulating layer is embedded in the insulating layer. This enables reduction in a thickness of the wiring board and a suppression of...

20060208359 - Double density method for wirebond interconnect: A method, comprising bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a second wire to the first bond, and coupling the second wire to the bond post....

20060208357 - Integrated device and electronic system: The present invention relates to an integrated device comprising an electronic circuit chip, a solder contact structure to provide contact to the electronic circuit chip and an elastic contact structure to provide contact to the electronic circuit chip, wherein the solder contact structure and the elastic contact structure are arranged...

20060208358 - Stacked package integrated circuit: The invention relates to an integrated circuit, electronic device, and method for assembling an integrated circuit package with at least one bottom module with a stacked die package comprising at least two dies within one single mold cap. To allow chip area reduction, the invention provides at least one memory...

20060208360 - Top via pattern for bond pad structure: Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line...

20060208361 - Semiconductor chip: A semiconductor chip 100 includes a semiconductor substrate (not shown), and a stacked film 150 formed over the semiconductor substrate, which includes carbon-containing insulating films such as a first interlayer insulating film 106, and carbon-free insulating films such as an underlying layer 102 and a top cover film 124. The...

20060208362 - Carbon nanotubes with controlled diameter, length, and metallic contacts: Some embodiments of the present invention include fabricating carbon nanotube bundles with controlled length, diameter, and metallic contacts....

20060208363 - Three-dimensional package and method of forming same: An electronic device (60) including a first integrated circuit (IC) die (62) electrically connected to a first lead frame (64) and a second IC die (66) electrically connected to a second lead frame (68). The first lead frame (64) is electrically connected to the second lead frame (68) by at...

20060208365 - Flip-chip-on-film package structure: A flip-chip-on-film package structure includes a flexible substrate, a flip chip, and a first heat sink. The flexible substrate has an upper surface and a lower surface. The flip chip is mounted on the upper surface of the flexible substrate and electrically connected to the flexible substrate. The first heat...

20060208364 - Led device with flip chip structure: The present invention provides an LED device with a flip chip structure. The LED device comprises an insulating substrate, an LED flip chip, a molding compound, a first conductive element, and a second conductive element. The LED flip chip is electrically connected to the connection pads on the insulating substrate...

20060208366 - Microelectronic component assemblies with recessed wire bonds and methods of making same: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, a substrate, and at least one bond wire. The substrate has a reduced-thickness base adjacent terminals of the microelectronic component and a...

20060202187 - Photonic device: Embodiments of methods, apparatuses, devices, or systems for forming a photonic device are described....

20060202188 - Nitride semiconductor light-emitting device, method of fabricating it, and semiconductor optical apparatus: A nitride semiconductor laser device has a nitride semiconductor substrate that includes a dislocation-concentrated region 102 and a wide low-dislocation region and that has the top surface thereof slanted at an angle in the range of 0.3° to 0.7° relative to the C plane and a nitride semiconductor layer laid...

20060202189 - Semiconductor device including a memory cell with a negative differential resistance (ndr) device: A semiconductor device may include at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto. The NDR device may include a superlattice including a plurality of stacked groups of layers, with each group of layers of the superlattice including a plurality of...

20060202190 - Aromatic amine derivative and organic electroluminescent element employing the same: The present invention relates to aromatic amine derivatives having a specific structure in which a substituted anthracene structure is bonded to an amine structure substituted with benzene rings having substituent groups; and organic electroluminescence devices comprising a cathode, an anode and one or plural organic thin film layers having at...

20060202193 - Bis-anthracenyl chiroptical compositions: where X is sulfur or selenium; where the R and R1 groups are alkyl or alkyl that together form a ring of carbon atoms; where An is the anion of a strong acid; and where the Z element is a chiral ring-completing system of atoms that changes chirality on tautomerization....

20060202198 - Integrated circuit, and method for the production of an integrated circuit: Embodiments of the invention relate to an integrated circuit comprising an organic semiconductor, particularly an organic field effect transistor (OFET) that is provided with a dielectric layer. The integrated circuit is produced by means of a polymer formulation consisting of a) 100 parts of at least one crosslinkable basic polymer,...

20060202192 - Memory device with improved switching speed and data retention: The present memory device includes first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the passive layer and the second electrode. In undertaking an operation on the memory device, ions moves into within and from within the active layer, and the...

20060202199 - Organic thin film transistor array panel and manufacturing method thereof: An organic thin film transistor array panel according to an embodiment of the present invention includes: a substrate; a data line disposed on the substrate; an insulating layer disposed on the data line and having a contact hole exposing the data line; a first electrode disposed on the insulating layer...

20060202200 - Organic thin film transistor array panel and manufacturing method thereof: An organic thin film transistor array panel includes a substrate, a data line disposed on the substrate, a gate line intersecting the data line and including a gate electrode, a gate insulating layer disposed on the gate line and having a contact hole exposing the data line, a first electrode...

20060202197 - Platinum complex and light-emitting device: In the general formula 1, two of the rings A, B, C, and D each independently represent an aromatic ring or an aromatic heterocyclic ring, while the other two rings each represent a nitrogen-containing heterocyclic ring; RA-D represent the substituents; each the rings A and B, the rings B and...

20060202194 - Red phosphorescene compounds and organic electroluminescence device using the same: Red phosphorescene compounds and organic electro-luminescence device using the same are disclosed. In an organic electroluminescence device including an anode, a hole injecting layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injecting layer, and a cathode serially deposited on one another, the organic...

20060202191 - Semiconductors containing perfluoroether acyl oligothiohpene compounds: Semiconductor devices are described that include a semiconductor layer that comprises a perfluoroether acyl oligothiophene compound, preferably an α,ω-bis-perfluoroether acyl oligothiophene compound. Additionally, methods of making semiconductor devices are described that include depositing a semiconductor layer that contains a perfluoroether acyl oligothiophene compound, preferably an α,ω-bis(2-perfluoroether acyl oligothiophene compound....

20060202195 - Siloxane-polymer dielectric compositions and related organic field-effect transistors: Dielectric compositions comprising siloxane and polymeric components, as can be used in a range of transistor and related device configurations....

20060202196 - Transistor: A thin film field effect transistor is disclosed that includes a gate electrode, a gate insulator film the on gate electrode, and a first organic electronic material film containing a first organic electronic material on the gate insulator film. A source electrode and a drain electrode are spaced apart from...

20060202201 - Wafer-level package having test terminal: A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at...

20060202205 - Organic electroluminescent device and method of fabricating the same: An organic electroluminescent device includes first and second substrates facing and spaced apart from each other, the first and second substrates including a pixel region; a gate line on an inner surface of the first substrate; a data line crossing the gate line; a switching thin film transistor connected with...

20060202202 - Pixel structure, active matrix substrate, method of manufacturing active matrix substrate, electro-optical device, and electronic apparatus: A pixel structure includes pixel electrodes and switching elements which correspond to the pixel electrodes. The pixel electrodes and the switching elements are formed on the same substrate, and each pixel electrode is provided in a layer on the substrate, not on a semiconductor layer of the switching element....

20060202203 - Structure of tft electrode for preventing metal layer diffusion and manufacturing method therefor: The invention provides a TFT electrode structure and its manufacturing method that can prevent metal diffusion occurring in the fabrication of a TFT, and thereby reduce the risk of contamination of the chemical vapor deposition process due to metallic ion diffusion. The transparent pixel electrode is formed after the gate...

20060202204 - Thin film transistor, thin film transistor panel, and method of manufacturing the same: The present invention relates to a TFT, a TFT array panel, and a method of manufacturing the TFT array panel. A method of manufacturing the TFT array panel includes the steps of forming a first electrode and a second electrode that are separated from each other on a substrate, forming...

20060202206 - Semiconductor device and method for manufacturing the same: An object of the present invention is to provide a semiconductor device which has flexibility and resistance to a physical change such as bending and a method for manufacturing the semiconductor device. A semiconductor device of the present invention includes a plurality of transistors provided over a flexible substrate, each...

20060202207 - Image display device: On a cathode substrate 10, a bottom electrode 11, a tunneling insulator 12, and a top electrode 13 are prepared. On a lower layer of the top electrode 13, a top electrode bus line 16 is formed, and the top electrode 13 is reliably connected to the top electrode bus...

20060202208 - Silicon plate, producing method thereof, and solar cell: A polycrystalline silicon plate has grain boundary lines on a surface thereof, and at least one of the grain boundary lines is a quasi-linear grain boundary line (1). The silicon plate is used to produce a solar cell. The silicon plate is formed using a base substrate having an irregular...

20060202209 - Limiting net curvature in a wafer: A method and apparatus for limiting net curvature in a substrate is provided. A layer is formed on one side of a substrate to limit curvature that may be introduced in the substrate by formation of a thermal spreading layer on an opposing side of the substrate. For example, introduction...

20060202210 - Led mounting having increased heat dissipation: There is disclosed a system and method for increasing heat dissipation of LED displays by using the current PCB packaging mounted to a LCD panel support structure thereby eliminating the need for a metal core PCB. In one embodiment, reverse mounted LEDs having heat dissipation pads are used to optimize...

20060202211 - Method for fabricating light-emitting device utilizing substrate transfer by laser decomposition: A light-emitting device includes an element structure including at least two semiconductor layers having mutually different conductivity types. A transparent p-side electrode of ITO is formed on the element structure. A bonding pad is formed on a region of the p-side electrode. An n-side electrode made of Ti/Au is formed...

20060202212 - Semiconductor optical device: A semiconductor optical device comprises a lower cladding layer of a first conductive type, an upper cladding layer of a second conductive type, and an active layer. The lower cladding layer has a first region and a second region. The first region extends in a direction of a predetermined axis,...

20060202213 - Device mounting substrate and image display device: A method of repairing a defective one of devices mounted on substrate is provided. Devices are arrayed on a substrate and electrically connected to wiring lines connected to a drive circuit, to be thus mounted on the substrate. The devices mounted on the substrate are then subjected to an emission...

20060202214 - Organic thin film transistor and flat panel display device including the same: Provided are an organic thin film transistor providing smoother movement of holes between a source electrode or a drain electrode and a p-type organic semiconductor layer, and a flat panel display device including the organic thin film transistor. The organic thin film transistor includes a substrate, a gate electrode disposed...

20060202217 - Nitride semiconductor light emitting device and method of manufacturing the same: A nitride semiconductor light emitting device includes a substrate for growing a gallium nitride-based semiconductor material, an n-type nitride semiconductor layer on the substrate, an active layer on the n-type nitride semiconductor layer such that a predetermined portion of the n-type nitride semiconductor layer is exposed, a p-type nitride semiconductor...

20060202215 - Polarization-reversed iii-nitride light emitting device: A device structure includes a III-nitride wurtzite semiconductor light emitting region disposed between a p-type region and an n-type region. A bonded interface is disposed between two surfaces, one of the surfaces being a surface of the device structure. The bonded interface facilitates an orientation of the wurtzite c-axis in...

20060202216 - Semiconductor light emitting device, semiconductor light emitting apparatus, and method of manufacturing a semiconductor light emitting device: A semiconductor light emitting device comprises: a semiconductor multilayer structure; and an aluminum nitride layer. The semiconductor multilayer structure includes a light emitting layer that emits a light. The aluminum nitride layer is provided on a surface of the semiconductor multilayer structure. The aluminum nitride layer has asperities with an...

20060202218 - Light-emitting diode for decoration: A light emitting diode includes a light emitting body, a lead frame supplying power to the light emitting body and a light transmitting resin covering the light emitting body and part of the lead frame. The top surface of the light transmitting resin is formed as a plane at a...

20060202220 - Display device and method for manufacturing the same: A method for manufacturing a display device and a display device manufactured thereby are provided. The above method has the steps of forming a first resin material on a base substrate so as to surround a region in which light-emitting devices are provided, applying a second resin material in the...

20060202221 - Led: A LED comprises a base body. The base body carries a light generating element. A light guide body is provided in the emitting direction of the light generating element. According to the invention, the light guide body comprises diffractive groups of light guide elements to fix the emission angle of...

20060202222 - Package structure of organic electroluminescent devices: A package structure of organic electroluminescent device comprises at least one isolating wall and at least one squeeze-out channel provided under a package lid. The adhesive coating place and squeeze-out area as laminating are able to be defined in package process due to the isolating wall and squeeze-out channel provided,...

20060202219 - Semiconductor light emitting device and semiconductor light emitting apparatus: A semiconductor light emitting device comprises: a substrate; a semiconductor stacked structure; a first electrode; a second electrode; and a reflective film. The substrate has a top face and a rear face electrode forming portion opposed thereto, and is translucent to light in a first wavelength band. The rear face...

20060202223 - Increased light extraction from a nitride led: In a method for fabricating a flip-chip light emitting diode device, a submount wafer is populated with a plurality of the light emitting diode dies. Each device die is flip-chip bonded to the submount. Subsequent to the flip-chip bonding, a growth substrate is removed. The entire submount is immersed in...

20060202225 - Submount for use in flipchip-structured light emitting device including transistor: Disclosed herein is a submount to mount a light emitting diode in a flipchip-structured light emitting device. The submount including a transistor to mount a nitride semiconductor light emitting diode in a flipchip-structured light emitting device includes: a substrate made of a first conductive semiconductor material; a first region formed...

20060202224 - Substrate structure for light-emitting diode module: A substrate structure for light-emitting diode module includes a highly heat-radiating metal substrate, a plurality of isolating islands formed on a top surface of the metal substrate only at positions and/or paths for forming required conducting circuits, and a plurality of conduction islands separately formed on the isolating islands to...

20060202226 - Single or multi-color high efficiency light emitting diode (led) by growth over a patterned substrate: A single or multi-color light emitting diode (LED) with high extraction efficiency is comprised of a substrate, a buffer layer formed on the substrate, one or more patterned layers deposited on top of the buffer layer, and one or more active layers formed on or between the patterned layers, for...

20060202227 - Vertical type nitride semiconductor light emitting diode: Disclosed herein is a vertical type nitride semiconductor light emitting diode. The nitride semiconductor light emitting diode comprises an n-type nitride semiconductor layer, an active layer formed under the n-type nitride semiconductor layer, a p-type nitride semiconductor layer formed under the active layer, and an n-side electrode which comprises a...

20060202228 - Semiconductor device: A semiconductor device is provided which comprises a heat-radiative support plate 5; and first and second semiconductor elements 1 and 2 mounted and layered on support plate 5 for alternate switching of first and second semiconductor elements 1 and 2. The arrangement of piling and securing first and second semiconductor...

20060202229 - Semiconductor device and method of manufacturing such a device: The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (12) with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2) and a collector region (3), which are provided with, respectively, a first, a second and a third...

20060202230 - Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method: An SOI structure semiconductor integrated circuit is disclosed that reduces the number of power supply wires setting substrate potential of a semiconductor element and reduces power consumption. With an SOI structure semiconductor integrated circuit, a first circuit block 51 does not include a critical path and a second circuit block...

20060202231 - Semiconductor integrated circuit device, and apparatus and program for designing same: Disclosed are a design method and apparatus in which information regarding a cell is input, the cell having taps in a substrate surface, for supplying the potentials of respective ones of wells in which active elements are formed, and source diffusion regions in the substrate surface, conductivity types thereof being...

20060202232 - Memory control unit and memory system: A memory control unit includes fuses that are selectively blown to set a manufacturer's identification code (ID), and a further fuse that is selectively blown to designate the memory control unit as a general-purpose unit or a custom unit. When designated as a custom unit, the memory control unit uses...

20060202233 - Semiconductor device and manufacturing method thereof: A semiconductor device is disclosed. The semiconductor device includes a semiconductor layer having a channel region, a strain generating layer to cause strain in the channel region by applying a stress to the channel region, a gate insulating film formed on the channel region, and a gate electrode formed on...

20060202234 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×1018 cm−3 to 5.0×1019 cm−3, or alternatively, the strain generating layer...

20060202235 - Solid-state imaging apparatus in which a plurality of pixels each including a photoelectric converter and a signal scanning circuit are arranged two-dimensionally: A solid-state imaging apparatus includes a semiconductor substrate, a photoelectric converter which is formed in a surface region of the semiconductor substrate and converts light into signal charges, and reading electrodes which read out the signal charges and supply the signal charges to a signal sensor. At least some of...

20060202236 - Thin film transistor, liquid crystal display device and method for fabricating thereof: A thin film transistor including: an active layer on a substrate, the active layer having at least two unit channels; and source and drain electrodes on the active layer, wherein an interval D between each of the channels is larger than a unit channel width W....

20060202237 - Metal gate semiconductor device and manufacturing method: A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to...

20060202238 - Lateral junction field effect transistor and method of manufacturing the same: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer...

20060202241 - D/a converter circuit, semiconductor device incorporating the d/a converter circuit, and manufacturing method of them: D/A conversion having higher accuracy is provided by improving relative accuracy of the resistance value of resistors which configure a resistor string. A manufacturing method of a D/A converter circuit of the invention comprises the steps of: forming a resistor string 11 which includes a plurality of resistors R0 to...

20060202239 - Methods for providing gate conductors on semiconductors and semiconductors formed thereby: A method of providing a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, binding a seed layer to the activated sites, and plating the dummy gate on the...

20060202240 - Semiconductor device: Provided is a semiconductor device which includes a conductive bonding pad formed on a semiconductor substrate of the first conduction type via an insulating film and a diffusion layer of the second conduction type formed on a surface of the semiconductor substrate under the bonding pad. Characteristics do not deteriorate...

20060202242 - Solid-state imaging device: A MOS solid-state imaging device is provided in which withstand voltage and 1/f noise of a MOS transistor are improved. In the MOS solid-state imaging device whose unit pixel has at least a photoelectric converting portion and a plurality of field effect transistors, the thickness of gate insulating film in...

20060202243 - Metamorphic avalanche photodetector: A metamorphic avalanche photodetector includes a substrate, and an active structure supported on the substrate. The active structure has a metamorphic absorption structure that absorbs light and responsively produces primary charge carriers, and an avalanche multiplication structure that receives the primary charge carriers from the metamorphic absorption structure and responsively...

20060202244 - Magnetic random access memory with stacked memory cells having oppositely-directed hard-axis biasing: A magnetic random access memory (MRAM) has memory stacks arranged in the X-Y plane on the MRAM substrate, with each memory stack having two memory cells stacked along the Z axis and each memory cell having an associated biasing layer. Each biasing layer reduces the switching field of its associated...

20060202245 - Phase-change memory device and manufacturing process thereof: A phase-change memory device, wherein memory cells form a memory array arranged in rows and columns. The memory cells are formed by a MOS selection device and a phase-change region connected to the selection device. The selection device is formed by first and second conductive regions which extend in a...

20060202246 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: an channel layer formed on a semiconductor substrate; a drain electrode and a source electrode both formed on the channel layer apart from each other; a surface passivation film formed on the channel layer so as to cover the channel layer except for the drain electrode...

20060202247 - Sram cell structure and manufacturing method thereof: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over...

20060202248 - Sram cell structure and manufacturing method thereof: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over...

20060202249 - Simplified buried plate structure and process for semiconductor-on-insulator chip: A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a first unitary semiconductor region disposed below...

20060202250 - Storage capacitor, array of storage capacitors and memory cell array: A storage capacitor, suitable for use in a DRAM cell, is at least partially formed above a substrate surface and includes: a storage electrode at least partially formed above the substrate surface, a dielectric layer formed adjacent the storage electrode, and a counter electrode formed adjacent the dielectric layer, the...

20060202253 - Flash memory cell transistor and method for fabricating the same: A flash memory cell transistor and a method for fabricating the same compensates a work function difference of a pMOS and a nMOS with a triple gate insulating film by using electron density trapped in a pMOS gate insulating film. The flash memory cell transistor comprises a p-well region and...

20060202252 - Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height;...

20060202251 - Scalable high performance non-volatile memory cells using multi-mechanism carrier transport: The device comprises a plurality of select gates that are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a vertical...

20060202256 - Flash memory cell arrays having dual control gates per memory cell charge storage element: A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory...

20060202254 - Multi-level flash memory cell capable of fast programming: A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers...

20060202257 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in...

20060202255 - Split gate non-volatile memory devices and methods of forming same: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance....

20060202258 - Technique for fabricating logic elements using multiple gate layers: Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and memory array cell sizes may be reduced by fabricating various transistor gates...

20060202259 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, a source/drain diffusion layer formed in the semiconductor substrate at both sides of the gate electrode, and a channel region formed in the semiconductor substrate...

20060202260 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes: a laminated body which has a floating-gate-forming groove and includes a semiconductor support layer, an impurity diffusion layer, an ion-implantation-damage protection film, and an interlayer insulating film; a floating-gate-insulating film; a floating gate disposed on the floating-gate-insulating film so as to be buried in the...

20060202261 - Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height;...

20060202262 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same are provided. A gate insulating film is formed under a vacuum condition to prevent deterioration of reliability of the device due to degradation of a gate insulating material and to have stable operating characteristics. The semiconductor device includes an element...

20060202264 - Enhancing schottky breakdown voltage (bv) without affecting an integrated mosfet-schottky device layout: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells and a junction barrier Schottky (JBS) area. The semiconductor power device includes the JBS area that further includes a plurality of Schottky diodes each having a PN junction disposed on...

20060202263 - Nonvolatile semiconductor memory device and method of fabricating the same: In an example embodiment, a semiconductor substrate has a plurality of active regions separated by a plurality of trenches. A gate insulation film fills at least a portion of the trenches, and a conductive gate film is formed over the gate insulation film. In an example embodiment, the gate insulation...

20060202265 - Process insensitive esd protection device: Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the...

20060202266 - Field effect transistor with metal source/drain regions: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in...

20060202267 - Methods of optimization of implant conditions to minimize channeling and structures formed thereby: Methods of forming a microelectronic structure are described. Those methods comprise implanting a first concentration of a species into an active area with a first energy, wherein the species pre-damages a portion of the active area, and then implanting a second concentration of the species into the active area with...

20060202268 - Soi semiconductor device and method of manufacturing thereof: An SOI semiconductor device has a substrate, an insulation film, a silicon film, a gate insulation film, a gate electrode, a pair of first diffusion regions, a first region, and a second diffusion region. The insulation film is formed on the substrate. The silicon film is formed on the insulation...

20060202269 - Wireless chip and electronic appliance having the same: The present invention provides a wireless chip having high mechanical strength. Moreover, the present invention also provides a wireless chip which can prevent an electric wave from being blocked. In a wireless chip of the present invention, a layer having a thin film transistor formed over an insulating substrate is...

20060202270 - Fin field effect transistors having capping insulation layers: A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation...

20060202271 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device includes a first power supply interconnect formed of a first single-crystal semiconductor layer and coupled to a first potential, and a second power supply interconnect formed of a second single-crystal semiconductor layer and coupled to a second potential, the second single-crystal semiconductor layer being deposited over the...

20060202273 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device comprises the steps of: preparing a semiconductor substrate, the semiconductor substrate having first and second predetermined regions; forming a first field region surrounding the first predetermined region; forming a second field region surrounding the second predetermined region while a separating region exists between...

20060202272 - Wide bandgap transistors with gate-source field plates: A transistor comprising an active region having a channel layer, with source and drain electrodes formed in contact with the active region and a gate formed between the source and drain electrodes and in contact with the active region. A spacer layer is on at least part of the surface...

20060202274 - Semiconductor integrated circuit and nonvolatile memory element: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The...

20060202275 - Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same: A semiconductor memory device provided with a memory cell region having first gate electrodes and a peripheral circuit region having second gate electrodes includes first gate electrodes arranged a first distance apart from each other on a semiconductor substrate, second gate electrodes arranged a second distance, which is larger than...

20060202276 - Semiconductor device and method of making semiconductor devices: A semiconductor device includes a semiconductor substrate in which an insulating layer is formed in a part of an region, a semiconductor layer is formed by epitaxial growth and located on the insulating layer, a first gate electrode is formed at the sidewall of the semiconductor layer, first source and...

20060202277 - Semiconductor devices with rotated substrates and methods of manufacture thereof: Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by...

20060202278 - Semiconductor integrated circuit and cmos transistor: A p-channel MOS transistor includes first and second SiGe mixed crystal regions formed epitaxially to a silicon substrate at respective outer sides of sidewall insulation films of a gate electrode so as to fill respective trenches formed in source and drain diffusion regions of p-type respectively, wherein the p-channel MOS...

20060202279 - Thin germanium oxynitride gate dielectric for germanium-based devices: A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed...

20060202280 - P-channel mos transistor and fabrication process thereof: A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of p-type are formed in the substrate at...

20060202281 - Semiconductor device: A semiconductor device, including: a semiconductor substrate; a first gate insulation film installed on the semiconductor substrate; a first gate electrode installed on the first insulation film; a silicon oxide film, installed beneath a periphery of the first gate electrode, being thicker than the first gate insulation film; a source...

20060202282 - Semiconductor device and a method of manufacturing the same and designing the same: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary...

20060202283 - Metal silicide adhesion layer for contact structures: A high aspect ratio contact structure using a metal silicide adhesion layer that is interposed between titanium and titanium nitride (TiN) to promote adhesion of TiN to Ti. The metal silicide adhesion layer created from silicon doped CVD Ti can be deposited over the unreacted Ti after the silicidation reaction...

20060202284 - Nonvolatile memory: Source diffusion layers and drain diffusion layers are alternately formed in lateral device forming regions separated by device isolation regions. Control gate electrodes are formed on both sides of each source diffusion layer through gate ONO films interposed therebetween. Gate electrodes are formed over their corresponding side surfaces of the...

20060202285 - Semiconductor device, semiconductor element and method for producing same: A semiconductor device comprises: a semiconductor substrate; a plurality of first diffusion layers having a low impurity density, the first diffusion layers being formed on the surface of the semiconductor substrate; a plurality of second diffusion layers having a high impurity density, the second diffusion layers being formed on the...

20060202286 - Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical misfet and a vertical misfet, and a method of manufacturing a semiconductor device and a semiconductor device: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with...

20060202287 - Semiconductor device and method for fabricating the same: A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer...

20060202288 - Insulator composition, organic semiconductor device, electronic device, and electronic apparatus: An insulator composition includes a polysilsesquioxane derivative with an organic group as a substituent, the insulator composition being used for formation of an insulating section that an organic semiconductor device includes....

20060202289 - Electrochemical device: An electrochemical transistor device is provided, which comprises a flexible substrate; a layer of organic material, which comprises a source portion, a drain portion and a transistor channel portion; a gate electrode arranged on said substrate separated from said layer of organic material; and a layer of solidified electrolyte arranged...

20060202290 - Magnetic tunnel junction structure with amorphous cofesib or nifesib free layer: A magnetic tunnel junction (MTJ) structure for a magnetic random access memory (MRAM) is provided. Specifically, an MTJ structure with an amorphous CoFeSiB or NiFeSiB free layer is provided. The free layer is a CoFeSiB single layer, a NiFeSiB single layer, a CoFeSiB/Ru/CoFeSiB SAF layer, or a NiFeSiB/Ru/NiFeSiB SAF layer....

20060202291 - Magnetoresistive sensor module and method for manufacturing the same: In the method of manufacturing a magnetoresistive sensor module, at first a composite arrangement out of a semiconductor substrate and a metal-insulator arrangement is provided, wherein a semiconductor circuit arrangement is integrated adjacent to a main surface of the semiconductor substrate into the same, wherein the metal-insulator arrangement is arranged...

20060202292 - Magnetoresistive medium including a vicinally treated substrate: A magnetoresistive medium (1) comprises a substrate (2) which has been treated to provide a miscut vicinal surface (3) in the form of terraces (4(a), 4(b)) and steps (5) of atomic and nanometer scale. A further upper film (11) provides upper nanowires (10(a), 10(b)). A thin protective layer (15) covers...

20060202295 - Method and structure for reducing noise in cmos image sensors: A method and device is disclosed for reducing noises in CMOS image sensors. An improved CMOS image sensor includes a light sensing structure surrounded by a support feature section. An active section of the light sensing structure is covered by no more than optically transparent materials. A light blocking portion...

20060202294 - Nanolithography and microlithography devices and method of manufacturing such devices: A lithography device includes one or more conductive strips monolithically embedded within an insulative structure. A method of manufacturing a lithography device includes monolithically forming a conductive strip through an insulative structure. Monolithically forming such a device includes forming the conductive strip on an mixed conductive-insulative layer, and embedding the...

20060202293 - Optical module and optical system: An optical module has a circuit carrier, a housed semiconductor element placed on the circuit carrier, and a lens unit for projecting electromagnetic radiation onto the semiconductor element. The lens unit, which is constructed separate from the cased semiconductor element, preferably comprises a lens assembly formed of, for example, three...

20060202296 - Encapsulated light receiving and processing semiconductor module with enhanced shielding and grounding properties: A semiconductor module includes a resin package, a conductive film formed on the resin package, and a lead partially covered by the resin package. The lead includes an inner portion covered by the resin package, and an outer portion projecting from the resin package. A semiconductor element is mounted to...

20060202297 - Semiconductor photodetector device: A transmitted light absorption/recombination layer, a barrier layer, a wavelength selection/absorption layer, and an InP window layer having a p-type region are supported by an n-type substrate and arranged in that order. Light with a wavelength of 1.3 μm reaches the wavelength selection/absorption layer through the InP window layer. Then,...

20060202298 - Device produced by method for etching a layered substrate: A device made through a fabrication method is disclosed. In one embodiment, the method includes a dry etch plasma process that utilizes CO2 to etch a layer. Furthermore, the dry etch plasma process may utilize CO2 in combination with NH3, H2, Ar, N2, He, or other inert gases during the...

20060202299 - Semiconductor devices integrating high-voltage and low-voltage field effect transistors on the same wafer: A field effect transistor (FET) with novel field-plate structure relates to a Schottky gate FET structure with field plate thereon for high voltage operations. The structure and fabrication processes thereof not only provide a reliable way to produce high-voltage FETs, but also allow the integration of conventional low-voltage FETs on...

20060202300 - Semiconductor structure and method of fabrication: Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask...

20060202301 - Semiconductor device with sti and its manufacture: A semiconductor device includes: a silicon substrate with semiconductor elements; an isolation trench formed in the silicon substrate for isolating active regions in the silicon substrate, the isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from the surface of the silicon substrate;...

20060202302 - Adjustable self-aligned air gap dielectric for low capacitance wiring: An adjustable self aligned low capacitance integrated circuit air gap structure comprises a first interconnect adjacent a second interconnect on an interconnect level, spacers formed along adjacent sides of the first and second interconnects, and an air gap formed between the first and second interconnects. The air gap extends above...

20060202303 - Package configuration and manufacturing method enabling the addition of decoupling capacitors to standard package designs: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The...

20060202304 - Integrated circuit with temperature-controlled component: An integrated circuit has a circuit component and a heating component thermally coupled together in a region thermally isolated from other parts of the integrated circuit. The thermal isolation can be provided by a bridge over a cavity in the substrate or caps over a thin substrate. A control circuit,...

20060202306 - Bipolar junction transistor with high beta: In one embodiment of the invention, a bipolar junction transistor (BJT) includes an emitter comprised of a first doped region doped with a first dopant of a first conductivity type. In addition, a salicide block is disposed over a periphery portion of the first doped region, and a salicide is...

20060202307 - Bipolar transistors having controllable temperature coefficient of current gain: A bipolar transistor which has a base formed of a combination of shallow and deep acceptors species. Specifically, elements such as Indium, Tellurium, and Gallium are deep acceptors in silicon, and are appropriate for such an application, in combination with boron as the shallow acceptor. The use of a deep...

20060202305 - Trench mos structure: A semiconductor device has a trench (42) adjacent to a cell (18). The cell includes source and drain contact regions (26, 28), and a central body (40) of opposite conductivity type. The device is bidirectional and controls current in either direction with a relatively low on-resistance. Preferred embodiments include potential...

20060202308 - Semiconductor device: A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically...

20060202309 - Integrated circuit substrate material: A semiconductor substrate material is disclosed for producing a semiconductor substrate. In an embodiment, the semiconductor substrate material may include a multitude of hollow microspheres. Each one of the multitude of hollow microspheres may have an inner layer and an outer layer. The inner layer may include a first material,...

20060202310 - Film or layer of semiconducting material, and process for producing the film or layer: SOI wafers are manufactured to have very thin device layers of high surface quality. The layer is ≦ 20 nm in thickness, has an HF density of ≦ 0.1/cm2, and a surface roughness of 0.2 nm RMS....

20060202311 - Low k dielectric cvd film formation process with in-situ imbedded nanolayers to improve mechanical properties: A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of...

20060202312 - Radio-frequency module for communication and method of manufacturing the same: A communication radio-frequency module is provided that has a semiconductor device to which an antenna element is connected. This communication radio-frequency module includes: a supporting body that has a waveguide formed therein; a wiring board that is fixed onto a surface of the supporting body; the semiconductor device that is...

20060202313 - High performance chip scale leadframe with t-shape die pad and method of manufacturing package: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second...

20060202315 - Microelectronic devices having conductive complementary structures and methods of manufacturing microelectronic devices have conductive complementary structures: Microelectronic devices, microfeature workpieces, and methods of forming and stacking the microelectronic devices and the microfeature workpieces. In one embodiment, a microfeature workpiece includes a plurality of first microelectronic dies. The individual first dies have an integrated circuit, a plurality of pads electrically coupled to the integrated circuit, and a...

20060202314 - Semiconductor package and method for manufacturing the same: A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a...

20060202316 - Semiconductor component having stiffener, circuit decal and terminal contacts: A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal includes conductors which function as an internal signal transmission system for the component, and a mask layer which functions as a solder mask and an outer...

20060202319 - Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads: An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first semiconductor device is disclosed. Spacers space the active surface of the first semiconductor device substantially a predetermined distance apart from the back side of the second semiconductor device....

20060202318 - Imaging module and method for forming the same: An imaging module is formed by stacking: a first resin board; a second resin board having a first opening; a first electrically-conductive member electrically connecting the first resin board and the second resin board to each other; a printed circuit board having a second opening; a second electrically-conductive member electrically...

20060202317 - Method for mcp packaging for balanced performance: Embodiments of the invention generally provide methods and apparatus for constructing multi chip packages having balance performance as between the various integrated circuits in a stack. In one embodiment, contacts on an outer surface of a first pad are “redistributed” from one area of the outer surface to another area...

20060202320 - Power semiconductor package: A semiconductor package that includes a semiconductor device and a lead frame having a first lead frame portion and a second lead frame portion, each lead frame portion including a plurality of fingers and a lead pad, each finger being electrically connected to a respective electrode of the semiconductor device....

20060202321 - Impedance matching external component connections with uncompensated leads: In one aspect, an electronic assembly includes an interconnection substrate, a component, and a discontinuity compensator. The interconnection substrate includes a signal conductor and a ground conductor. The component includes a device having a signal line and a ground conductor, a package, and a signal lead. The signal lead is...

20060202322 - Interposer, and multilayer printed wiring board: An interposer capable of preventing breaking of a wiring pattern with an IC chip loaded on a package substrate. Stress due to a difference in thermal expansion coefficient between a multilayer printed wiring board having a large thermal expansion and the IC chip having a small thermal expansion can be...

20060202323 - Semiconductor module: One of the aspects of the present invention is to provide a semiconductor module, which includes at least one semiconductor device including a semiconductor element molded with a resin package having a main surface and a side surface, and a plurality of terminals extending from the side surface and being...

20060202324 - Semiconductor power module: A semiconductor power module has insulative substrate which is configured with a metal wiring pattern formed on an upper first surface thereof, a metal conductor formed on a rear face, opposite the first surface and an insulative layer between the metal wiring pattern and the metal conductor. A semiconductor chip...

20060202326 - Heat spreader and package structure utilizing the same: A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the...

20060202325 - Method and structure to provide balanced mechanical loading of devices in compressively loaded environments: An integrated circuit chip mounting structure includes a chip carrier electrically connected to a circuit board with an integrated circuit chip mounted on the chip carrier. In addition, a thermally conductive device is thermally connected to the chip and a set of compressible support members are provided to transmit a...

20060202328 - Memory module and memory configuration with stub-free signal lines and distributed capacitive loads: In a memory module for a memory configuration having a bus system made up of a plurality of signal lines, each signal line has respectively been produced essentially without any stub continuously from a supplying contact device to a discharging contact device, disposed close to the supplying contact device, in...

20060202327 - Semiconductor device, semiconductor body and method of manufacturing thereof: The invention relates to a semiconductor device (10) comprising a semiconductor body (11) in which an IC is formed and which has a number of connection regions (1) for the IC on its surface, including at least two connection regions (I A) for a supply connection, the lower side of...

20060202329 - Chip package and fabricating method thereof: A chip package and fabricating method thereof are provided to maintain the thermal dissipating efficiency and reduce the damage to the chip. The edge of the exposed portion would be cracked caused by external force because of the substrate of the chip is brittle. The crack in the edge of...

20060202330 - Chip with cleaning cavity: A chip comprising at least one cleaning cavity adapted for collecting material when a moveable device is contacted to and moved relative to the chip....

20060202331 - Conductive bump structure of circuit board and method for fabricating the same: A conductive bump structure of a circuit board and a method for fabricating the same are proposed. The circuit board with a plurality of electrical connection pads is provided. An insulating protective layer and a resist layer are successively applied on the circuit board, wherein openings are formed in the...

20060202334 - Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same: Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI) and a semiconductor chip and a mount structure using the method to minimize a pad...

20060202333 - Package of a semiconductor device with a flexible wiring substrate and method for the same: A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer on the bump, and a...

20060202332 - Semiconductor chip packaging apparatus and method of manufacturing semiconductor chip package: Example embodiments of a semiconductor chip packaging apparatus and method thereof are disclosed. The packaging apparatus includes a plating unit that is disposed in a direction to form a conductive plating layer on external terminals of the semiconductor chip package; and a reflow unit that is disposed with the plating...

20060202335 - Tape ball grid array package with electromagnetic interference protection and method for fabricating the package: A tape ball grid array (TBGA) package and method for fabricating the package utilizes at least one electrical connection between a conductive stiffener and a patterned metal layer of a tape substrate, which is connected to a solder ball that is designated to be connected to AC ground, so that...

20060202336 - Semiconductor device and method of fabricating a semiconductor device: A semiconductor device includes a semiconductor substrate, a first interconnection layer formed above the semiconductor substrate via a first interlayer insulating film, the first interconnection layer having Cu as a main material, a second interconnection layer formed above the first interlayer insulating film and the first interconnection layer via a...

20060202337 - Electronic device and use thereof: The electronic device (100) comprises a semiconductor element (1) (e.g. a transistor), an encapsulation (5) and an electrically conductive layer (3) with a first and a second contact pad (11,12), used as signal pads, and a third contact pad (13) used as ground pads. Due to the shape of the...

20060202338 - Integrated interconnect arrangement: Integrated interconnect arrangement An explanation is given of an integrated interconnect arrangement (12) having a plurality of interconnects (LB1 to LB3) that cross over one another at two crossover sections (20, 24). By virtue of this measure, it is possible to achieve a uniform current flow in all three interconnects...

20060202339 - Method of forming a semiconductor device having a diffusion barrier stack and structure thereof: A diffusion barrier stack is formed by forming a layer comprising a metal over a conductor that includes copper; and forming a first dielectric layer over the layer, wherein the dielectric layer is of a thickness that alone it can not serve as a diffusion barrier layer to the conductor...

20060202342 - Method to fabricate interconnect structures: A method includes forming a barrier layer on a substrate surface including at least one contact opening; forming an interconnect in the contact opening; and reducing the electrical conductivity of the barrier layer. A method including forming a barrier layer on a substrate surface including a dielectric layer and a...

20060202343 - Oxygen doped sic for cu barrier and etch stop layer in dual damascene fabrication: A method of forming a dual damascene structure with improved performance is described. A first etch stop layer comprised of oxygen doped SiC is deposited on a SiC barrier layer to form a composite barrier/etch stop layer on a substrate. The remainder of the damascene stack is formed by sequentially...

20060202344 - Printed wiring board and method for manufacturing the same: In a printed wiring board, an odd number (n) of conductive layers (11-13) and insulating layers (21-23) are alternately laminated upon another. The first conductive layer (11) is constituted as a parts connecting layer and the n-th conductive layer (13) is constituted as an external connecting layer which is connected...

20060202340 - Semiconductor device and method of manufacturing the same: Wirings including first conductive layer patterns and insulating mask layer patterns are formed on a substrate. Insulating spacers are formed on sidewalls of the wirings. Self-aligned contact pads including portions of a second conductive layer are formed to contact with surfaces of the insulating spacers and to fill up a...

20060202341 - Semiconductor device, and method of manufacturing the same: A defective opening caused by the shortage of light amounts at performing exposure for forming a contact or a via is controlled. The cross-sectional shape of the contact plug 17 includes a plurality of first regions 302 arranged at a predetermined distance in the longitudinal direction, and a second region...

20060202345 - Barrier layers for conductive features: Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material....

20060202346 - Copper interconnection with conductive polymer layer and method of forming the same: A conductive polymer between two metallic layers acts a glue layer, a barrier layer or an activation seed layer. The conductive polymer layer is employed to encapsulate a copper interconnection structure to prevent copper diffusion into any overlying layers and improve adhesive characteristics between the copper and any overlying layers....

20060202348 - Semiconductor device and manufacturing method thereof: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor...

20060202347 - Through electrode, package base having through electrode, and semiconductor chip having through electrode: A through electrode extends through a silicon substrate from the upper surface to the lower surface of the substrate to accomplish electrical conduction between the upper and lower surfaces of the substrate. The through electrode includes a plurality of slender through holes formed in a through electrode forming area of...

20060202349 - Circuit substrate and its manufacturing method: A circuit substrate has a flexible thin film, electric wires supported on the film, and an electronic component supported on the film and positioned between the wires so that the wires and the component are electrically connected serially. Also, a thickness of the component is less than that of the...

20060202350 - Semiconductor device: Disclosed is a semiconductor device including an organic material substrate, a semiconductor chip flip chip connected to substantially a center of one surface of the organic material substrate, and a semiconductor package mounted on another surface of the organic material substrate in a manner to avoid a position opposing to...

20060202351 - Underfilling efficiency by modifying the substrate design of flip chips: A substrate structure comprising a substrate; a solder mask is formed over the substrate; and a metal trace structure formed within the solder mask. The metal trace structure including a channel therein for the receipt of underfill. The metal trace structure further including a central portion with arms radiating outwardly...

20060202352 - Magnetron sputtered metallization of a nickel silicon alloy, especially useful as solder bump barrier: A nickel silicon alloy barrier layer formed between a metal bonding pad on an integrated circuit and a tin-based solder ball, for example, a lead-free solder. The nickel silicon alloy contains at least 2 wt % silicon and preferably less than 20 wt %. An adhesion layer may be formed...

20060202353 - Semiconductor device and method of manufacturing the same: A plurality of semiconductor chips are bonded to an adhesive layer formed on a base plate. Then, first to third insulating films, first and second underlying metal layers, first and second re-wirings, and a solder ball are collectively formed for the plural semiconductor chips. In this case, the first and...

20060202354 - Configuration for testing the bonding positions of conductive drops and test method for using the same: Configuration for testing the bonding positions of conductive drops and test method by using the same is disclosed. In the invention, a special configured contact pad for setting a conductive drop and an associated wire pattern are useful for knowing the drop condition of single or several displaying panels. The...

20060202356 - Material for forming insulating film with low dielectric constant, low dielectric insulating film, method for forming low dielectric insulating film and semiconductor device: A material for forming an insulating film with low dielectric constant of this invention is a solution including a fine particle principally composed of a silicon atom and an oxygen atom and having a large number of pores, a resin and a solvent....

20060202355 - Nanostructured friction enhancement using fabricated microstructure: Described herein are fabricated microstructures to adhere in shear to a contact surface. A fabricated microstructure comprises a substrate and a plurality of nano-fibers attached to the substrate. The nano-fibers have an elasticity modulus E, an interfacial energy per unit length of contact w, a length L, a radius R,...

20060202357 - Wired circuit board: A wired circuit board having terminals that can ensure large electrical connection areas while preventing shorting of adjacent terminals, to ensure that the terminals are electrically connected with external terminals through molten metal. An insulating base layer 3 is formed on a supporting board 2 so that insulating concave portions...

20060202358 - Antisymmetric nanowire crossbars: Various embodiments of the present invention are directed to antisymmetric nanowire-crossbar-circuit designs. Antisymmetric nanowire crossbars are composed, in certain embodiments of the present invention, of two or more microregions that receive input signals and two or more microregions that send output signals. Antisymmetric nanowire crossbars may include a nanowire-crossbar network...

20060202359 - Apparatus and method for predetermined component placement to a target platform: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by...

20060202360 - Semiconductor device featuring overlay-mark used in photolithography process: In a semiconductor device, an insulating layer formed on a substrate and a wiring pattern layer is formed on the insulating layer. A lower mark element is defined as a groove formed in the insulating layer, and defines an overlay mark in conjunction with an upper mask element formed in...

20060202361 - Layout structure for memory arrays with soi devices: A layout structure of a static random access memory (SRAM) cell array includes at least one SRAM cell area, oxide defined (OD) area and strapping cell area. The SRAM cell area has a longitudinal side being at least twice longer than a transverse side thereof. The oxide defined (OD) area...

20060197076 - Carbon nanotube resonator transistor and method of making same: A resonant transistor includes a substrate, a source and a drain formed on the substrate, an input electrode and a carbon nanotube gate. A gap is formed between the source and the drain. The input electrode is formed on the substrate. The carbon nanotube gate is clamped on one end...

20060197081 - Light-emitting device and method for manufacturing the same: The present invention provides an organic light-emitting element where a lower electrode, an organic compound layer and an upper electrode are laminated on a substrate, wherein the upper electrode of the organic EL element is formed by a laminate of at least a conductive first inorganic film, a conductive organic...

20060197077 - Metal complex compound and organic electroluminescent device using same: A metal complex compound having a special structure containing metals such as iridium. An organic electroluminescence device which comprises at least one organic thin film layer sandwiched between a pair of electrode consisting of an anode and a cathode, wherein the organic thin film layer comprises the above metal complex...

20060197079 - Method of manufacturing thin film transistor, thin film transistor manufactured by the method, and display device employing the same: A method of manufacturing a thin film transistor is capable of enhancing pattern precision of an organic semiconductor layer and simplifying a patterning process. The method includes forming an organic insulating film on a substrate and forming a bank having the first and second concave portions and a third concave...

20060197078 - Organic light-emitting display device having high light utilization: An organic light-emitting display device includes a light-emitting layer (10), a light permeable layer (20) and a prismatic film (40). The light permeable layer is positioned on the light-emitting layer, and the prismatic film is placed on the light permeable layer. The prismatic film includes a plurality of prisms (42)....

20060197080 - Thin film forming device, method of forming a thin film, and self-light-emitting device: Measure of forming an EL layer by selectively depositing through evaporation a material for forming the EL layer at a desired location is provided. When a material for forming an EL layer is deposited, a mask (113) is provided between a sample boat (111) and a substrate (110). By applying...

20060197082 - Transistor including physical property-changing layer, method of operating transistor, and method of manufacturing transistor: A transistor using a physical property-changing layer, a method of operating the transistor, and a method of manufacturing the transistor are provided. The transistor may include an insulation layer formed on a substrate, the first and second conductive layer patterns, the physical property-changing layer, a dielectric layer, for example, a...

20060197083 - Optical sensor: The present invention aims at providing a photodetector which can detect the incident light intensity with a high speed while having a wide dynamic range for incident light intensity detection. Each photodiode PDm,n generates electric charges Q by an amount corresponding to the intensity of light incident thereon. An electric...

20060197084 - Organic semiconductor device: An organic semiconductor device includes at least p-type and n-type channel organic semiconductor elements. Each organic semiconductor element includes a pair of a source electrode and a drain electrode which are facing each other, an organic semiconductor layer deposited between the source electrode and the drain electrode such that a...

20060197086 - Organic light emitting diode display and manufacturing method thereof: An organic light emitting display according to an embodiment of the invention includes: a substrate; a first electrode disposed on the substrate; a first partition disposed on the first electrode and having an opening exposing the first electrode; a second partition that is disposed on the first partition, wider than...

20060197088 - Semiconductor device and manufacturing method of the same: It is an object of the present invention to manufacture a minute TFT having an LDD region through process with the reduced manufacturing steps, and form a TFT having a structure suitable for each circuit. It is also an object of the present invention to secure an ON current even...

20060197087 - Thin film transistor: A thin film transistor (TFT) and a manufacturing method thereof are provided. The thin film transistor (TFT) comprises a substrate, a gate, an inter-gate dielectric layer, a channel layer and source/drain regions. A gate is formed over the substrate. An inter-gate dielectric layer is formed over the substrate covering the...

20060197085 - Thin film transistor array panel: A thin film transistor (“TFT”) array panel is provided, which includes: first and second gate lines transmitting gate signals to adjacent pixel rows and disposed adjacent to each other, a data line insulated from the first and the second gate lines and the data line; a first thin film transistor...

20060197089 - Semiconductor device and its manufacturing method: A semiconductor device and its manufacturing method are disclosed. The nitrogen flow is gradually changed to form a semiconductor device with a gate or a source/drain having a nitrified gradient layer structure. Different extents of nitrification inside the nitrified gradient layer structure provide protection and buffering to prevent the undercut...

20060197090 - Pyramid-shaped capacitor structure: A capacitor structure which has a generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on...

20060197091 - Pyramid-shaped capacitor structure: A capacitor structure which has generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on the...

20060197093 - Semiconductor device including semiconductor thin films having different crystallinity, substrate of the same, and manufacturing method of the same, and liquid crystal display and manufacturing method of the same: A method of manufacturing a thin-film semiconductor device substrate includes a step of forming a non-single crystalline semiconductor thin film on a base layer, and an annealing step of irradiating the non-single crystalline semiconductor thin film with an energy beam to enhance crystallinity of a non-single crystalline semiconductor constituting the...

20060197092 - System and method for forming conductive material on a substrate: A method for forming a conductive material on a substrate includes laser annealing a selected portion of a blanket coated material to form a conductive region....

20060197095 - Organic electroluminescent device, method of manufacturing organic electroluminescent device, and electronic apparatus: An organic electroluminescent device includes a first member: a light-emitting element that is formed on the first member; a second member that has a second region bonded to the first region of the first member, and forms a sealing space for sealing the light-emitting element between the first member and...

20060197094 - Semiconductor light emitting device, semiconductor light emitting apparatus, and method of manufacturing semiconductor light emitting device: Disclosed is a semiconductor light emitting device comprising: a substrate having first and second major surfaces and being translucent to light in a first wavelength band; and a semiconductor stacked body provided on the first major surface and including a light emitting layer that emits light in the first wavelength...

20060197096 - Substrate with refractive index matching: This invention provides a composite substrate that has a transparent mechanical support, for example of glass or quartz, a film or thin layer of monocrystalline semi-conductive material and an intermediate antireflective layer located between the thin layer or the semi-conductive film and the support. The composition of the intermediate antireflective...

20060197097 - Image pickup device with color filter: An image pickup device is characterized by including a plurality of pixels having a plurality of photoelectric conversion units, convex interlayer lenses with respect to incident light, the convex interlayer lenses being arranged correspondingly to a photoelectric conversion devices and color filters being arranged for each color on the interlayer...

20060197098 - Light emitting device and illumination apparatus using said light emitting device: A light emitting device including a blue-system semiconductor light emitting element, a green-system semiconductor light emitting element, a yellow fluorescent member which absorbs a part of blue light from the blue-system semiconductor light emitting element and emits yellow-system light as excitation light, and a red fluorescent member which absorbs a...

20060197099 - Semiconductor light emitting device: A semiconductor light emitting device can be configured to prevent diffusion migration of components constituting a linear electrode. The semiconductor light emitting device can include a substrate, at least one semiconductor layer formed on the substrate and having a topmost semiconductor layer, a pad electrode formed from a plurality of...

20060197100 - Reverse polarization light emitting region for a semiconductor light emitting device: A semiconductor light emitting device includes a light emitting layer disposed between an n-type region and a p-type region. The light emitting layer may be a wurtzite III-nitride layer with a thickness of at least 50 angstroms. The light emitting layer may have a polarization reversed from a conventional wurtzite...

20060197101 - Light source module of light emitting diode: A light source module for a light emitting diode (LED) is provided. In the present invention, a common printed circuit board (PCB) is utilized to provide electric current and isolated from the heat dissipation mechanism, and the thermal conductive element, protruding from the LED package structure, is connected to another...

20060197102 - Semiconductor composite apparatus, led, led printhead, and image forming apparatus: A semiconductor composite apparatus includes a substrate and a planarizing layer, and a semiconductor thin film. The planarizing layer is formed on the substrate either directly or indirectly. The planarizing layer includes a first surface that faces the substrate, and a second surface that is on the side of the...

20060197103 - Surface-mountable light-emitting diode structural element: A surface-mountable light emitting diode structural element in which an optoelectronic chip is attached to a chip carrier part of a lead frame, is described. The lead frame has a connection part disposed at a distance from the chip carrier part, and which is electrically conductively connected with an electrical...

20060197104 - Semiconductor device and fabrication method thereof: A semiconductor device includes a first nitride semiconductor layer formed on a substrate and a second nitride semiconductor layer formed on the first nitride semiconductor layer so as to be in contact with the first nitride semiconductor layer. The first nitride semiconductor layer contains a p-type impurity. The second nitride...

20060197105 - Power semiconductor switch: A SiC JFET that includes a plurality of trenches formed in a SiC semiconductor body of one conductivity each trench having a region of another conductivity formed in the bottom and sidewalls thereof....

20060197106 - Semiconductor switches and switching circuits for microwave: The purpose of the present invention is to provide a small-sized switch attaining high isolation of not less than 80 dB, maintaining low insertion loss also in high frequencies not less than 60 GHz. A semiconductor switch according to the present invention utilizes FETs a gate electrode, a source electrode,...

20060197107 - Semiconductor device and production method thereof: A semiconductor device formed from a III-V nitride family semiconductor is disclosed that has a reduced gate leakage current and good interface characteristics between the III-V nitride family semiconductor and a gate insulating film. The semiconductor device includes a semiconductor layer formed from the III-V nitride family semiconductor, a gate...

20060197108 - Total ionizing dose suppression transistor architecture: A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the...

20060197109 - High electron mobility transistor: A HEMT device including a GaN channel structure including a very thin (Al,In,Ga)N subchannel layer that is disposed between a first GaN channel layer and a second GaN channel layer, to effect band bending induced from the piezoelectric and spontaneous charges associated with the (Al,In,Ga)N subchannel layer. This GaN channel/(Al,In,Ga)N...

20060197110 - Semiconductor integrated circuit device using four-terminal transistors: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the...

20060197111 - Semiconductor lsi circuit and a method for fabricating the semiconductor lsi circuit: Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain regions of the nMOSFET and the pMOSFET are...

20060197112 - Optical coupling device: In various aspects, an optical coupling device may include a light emitting element configured to emit an optical signal; a photo receiving element having a serial connected of photo diodes, the photo receiving element configured to receive the optical signal and generate an electrical signal; and a control circuit having...

20060197113 - Solid-state imaging device and method for fabricating same: A solid-state imaging device includes a plurality of pixels two-dimensionally arrayed in a well region disposed on a semiconductor substrate, each pixel including a photoelectric conversion section having a charge accumulation region which accumulates signal charge; an element isolation layer which is disposed on the surface of the well region...

20060197114 - Solid-state image sensor: A solid-state image sensor capable of suppressing blooming and increase of a dark current also when an n-type impurity concentration in a transfer channel region is increased is obtained. In this solid-state image sensor, gate electrodes of a prescribed pixel and another pixel adjacent to the prescribed pixel are provided...

20060197115 - Phase change memory device: A phase change memory device has a semiconductor substrate; a plurality of cell arrays stacked above the semiconductor substrate, each cell array having memory cells arranged in a matrix manner for storing resistance values as data that are determined by phase change of the memory cells, bit lines each commonly...

20060197116 - Electro-optical device: An object of the present invention is to realize a numerical aperture higher than that of a pixel having a conventional construction by using a pixel circuit having a novel construction in an electro-optical device. Therefore, it is utilized that the electric potential of a gate signal line in a...

20060197117 - Stacked semiconductor device and method of fabrication: A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the...

20060197118 - Detection of molecular interactions using a field effect transistor: A sensor for use in the detection of a molecular interaction comprises a field effect transistor (FET) having a core structure and an extended gate structure, the core structure and the extended gate structure being located on substantially separate regions of a substrate, the extended gate structure including an exposed...

20060197119 - Method for forming suspended transmission line structures in back end of line processing: A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the...

20060197121 - Abrupt channel doping profile for fermi threshold field effect transistors: A Fermi threshold voltage FET has Germanium implanted to form a shallow abrupt transition between the semiconductor substrate dopant type, or well dopant type, and a counter doping layer of opposite type closely adjacent the surface of the semiconductor substrate. Germanium is a charge neutral impurity in silicon that significantly...

20060197122 - Charge trapping device: A silicon based semiconductor device and method uses charge trapping to alter a density of carriers available in a channel of a field effect transistor (FET) for conduction. The charge trapping mechanism can be controlled by a source-drain bias voltages applied to the FET, so that the device can be...

20060197124 - Double gate strained-semiconductor-on-insulator device structures: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication....

20060197120 - Gate electrode for semiconductor devices: The present invention provides an MIS type semiconductor device, comprising a semiconductor substrate and a gate electrode formed on the gate insulating film and formed of gate material. The gate electrode comprises: a first layer of activated crystalline gate material having a first side oriented towards a substrate and a...

20060197125 - Methods for forming double gate strained-semiconductor-on-insulator device structures: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication....

20060197123 - Methods for forming strained-semiconductor-on-insulator bipolar device structures: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication....

20060197126 - Methods for forming structures including strained-semiconductor-on-insulator devices: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication....

20060197127 - Semiconductor device: An object is to increase the amount of substrate noise absorbed in a guard ring, and to prevent a malfunction caused by the substrate noise in a semiconductor device including an SOI substrate provided with the guard ring. Then, there is provided a semiconductor device, including: an SOI substrate in...

20060197128 - Ferromagnetic-semiconductor spin polarizer of electrons in nonmagnetic semiconductors: An efficient spin polarizer in nonmagnetic semiconductors is provided. Previous spin injection devices suffered from very low efficiency (less than 35%) into semiconductors. An efficient spin polarizer is provided which is based on ferromagnetic-semiconductor heterostructures and ensures spin polarization of electrons in nonmagnetic semiconductors close to 100% near the ferromagnetic-semiconductor...

20060197129 - Buried and bulk channel finfet and method of making the same: One embodiment of a fin-field effect transistor includes a material stack including a non-inverting su surface channel, a fin of semiconductor material positioned on the material stack, the fin including first and second opposing side surfaces, and a gate electrode positioned on the first and second opposing side surfaces of...

20060197131 - Dram device and method of manufacturing the same: In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation...

20060197130 - Phase change memory devices and fabrication methods thereof: In a memory device, a transistor may be formed on a substrate, and a first electrode may be electrically connected thereto. A phase change material film may be vertically formed on the first electrode, and a second electrode may be formed on the phase change material film....

20060197132 - Sram cell structure and manufacturing method thereof: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over...

20060197133 - Mim capacitor including ground shield layer: An MIM capacitor includes a substrate, a capacitor part having a structure in which a bottom electrode, a dielectric layer and a top electrode are laminated in order, and a ground shield layer formed between the bottom electrode of the capacitor part and the substrate and connected to a predetermined...

20060197134 - Method of manufacturing a metal-insulator-metal capacitor using an etchback process: The present invention provides a method for manufacturing a metal-insulator-metal (MIM) capacitor, a method for manufacturing an integrated circuit having a metal-insulator-metal (MIM) capacitor, and an integrated circuit having a metal-insulator-metal (MIM) capacitor. The method for manufacturing the metal-insulator-metal (MIM) capacitor, among other steps and without limitation, includes providing a...

20060197135 - Semiconductor device having a cylindrical capacitor element: A semiconductor device includes a cylindrical capacitor having a bottom electrode, a capacitor insulator film and a top electrode. The top electrode includes first and second electrode portions insulated from each other and opposing the inner surface and outer surface, respectively, of the bottom electrode. The second electrode portion is...

20060197137 - Memory devices, transistors, memory cells, and methods of making same: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel...

20060197136 - Semiconductor memory device: According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines;...

20060197138 - Use of selective epitaxial silicon growth in formation of floating gates: Apparatus utilizing epitaxial silicon growth on a base structure of a floating gate of a floating-gate memory cell to increase the available coupling area of the floating gate while reducing the spacing between adjacent memory cells. The epitaxial silicon growth facilitates a reduction in spacing between adjacent cells beyond the...

20060197143 - Apparatus and method for split transistor memory having improved endurance: The present invention includes floating gate transistor structures used in non-volatile memory devices such as flash memory devices. In one embodiment, a system includes a CPU and a memory device including an array having memory cells having columnar structures and a floating gate structure interposed between the structures that is...

20060197141 - Charge trapping semiconductor memory element with improved trapping dielectric: A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of a second conduction type provided in the semiconductor substrate, a second doping region of the second conduction type provided in the semiconductor substrate, a channel...

20060197139 - Non-volatile memory device having improved band-to-band tunneling induced hot electron injection efficiency and manufacturing method thereof: A semiconductor device includes a semiconductor substrate having a first conductivity type. The semiconductor substrate includes a first diffusion region having the first conductivity type, a second diffusion region having the first conductivity type, and a channel region between the first diffusion region and the second diffusion region. The device...

20060197142 - Semiconductor storage device, manufacturing method therefor, and portable electronic equipment: A semiconductor storage device has a semiconductor layer having a first conductivity type region and two second conductivity type regions separated from each other by the first conductivity type region, a memory function body formed on a surface of the semiconductor layer, and a gate electrode. The memory function body...

20060197140 - Vertical transistor nvm with body contact structure and method: A semiconductor device (151) is provided which comprises (a) a semiconductor substrate (103); (b) a fin (109) comprising a semiconductor material and being in electrical contact with the substrate; (c) a first floating gate (121) disposed on a first side of said fin; and (d) a control gate (107)....

20060197144 - Nitride storage cells with and without select gate: In the past the high voltage needs and cell leakage currents have limited the scalability of the Nitride cell and made the poly silicon floating gate cell the primary contender for Non-Volatile memories. As the process development has matured and technology has scaled to smaller and smaller dimensions, the Poly-silicon...

20060197145 - Non-volatile memory and manufacturing method and operating method thereof: A non-volatile memory having a plurality of memory units is provided. Each memory unit includes a first memory cell and a second memory cell. The first memory cell is disposed on the substrate. The second memory cell is disposed on one sidewall of the first memory cell and the substrate....

20060197146 - Semiconductor device: A semiconductor device comprises a semiconductor substrate having an upper surface and a lower surface. A semiconductor layer is formed on the upper surface of the semiconductor substrate. A base region of a first conduction type is formed in the semiconductor layer. A source region of a second conduction type...

20060197147 - Improved double gate isolation: A double-gated fin-type field effect transistor (FinFET) structure has electrically isolated gates. In a method for manufacturing the FinFET structure, a fin, having a gate dielectric on each sidewall corresponding to the central channel region, is formed over a buried oxide (BOX) layer on a substrate. Independent first and second...

20060197149 - Semiconductor device and fabrication process thereof, and application thereof: An LDMOS transistor includes a gate insulation film formed on a semiconductor substrate, a gate electrode formed on the gate insulation film, a drain well of a first conductivity type formed in the substrate so as to include a gate region covered with the gate electrode, a channel well of...

20060197148 - Trench power moset and method for fabricating the same: A method for fabricating a trench power MOSFET, comprising an epitaxial layer and a mask layer formed over a substrate, a trench formed in the epitaxial layer and the mask layer, a gate oxide layer formed on the trench, then the mask layer removed, a body well region formed in...

20060197150 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed...

20060197152 - Semiconductor device: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the...

20060197151 - Semiconductor device and method for manufacturing the same: A semiconductor device include a plurality of active element cells including first element regions of a first conductivity type and second element regions of a second conductivity type, the second element regions disposed between the first element regions; and isolation regions disposed between the active element cells so as to...

20060197153 - Vertical transistor with field region structure: A structure of a vertical transistor with field region is provided. The vertical transistor comprises a field-doping region formed in a substrate next to a core region of the vertical transistor. By modulating the doping density, length, and geometrical pattern of the field region, and by connecting the field region...

20060197155 - Nonvolatile memory and manufacturing method thereof: Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFTs. This enables...

20060197156 - Power semiconductor and method of fabrication: This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and methods for their fabrication. A power semiconductor, the semiconductor comprising: a power device, said power device having first and second electrical contact regions and...

20060197154 - Semiconductor component and method of manufacture: A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material,...

20060197158 - Advanced cmos using super steep retrograde wells: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of...

20060197157 - Semiconductor device and method for manufacturing the same: There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate...

20060197159 - Semiconductor device and method of fabricating: Aspects of the present invention include a semiconductor device and method. In a transition region of a semiconductor material region, a near-surface compensation doping area with a conductivity type, which is different than the conductivity type of a transition doping area of the semiconductor material region, is provided in the...

20060197160 - Nonvolatile semiconductor memory device: A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in...

20060197161 - Semiconductor device and semiconductor integrated circuit device: In each of a p-channel MOS transistor and an n-channel MOS transistor, a channel direction is set in the <100> direction and a first stressor film accumulating therein a tensile stress is formed in a STI device isolation structure. Further, a second stressor film accumulating therein a tensile stress is...

20060197162 - Semiconductor devices having a buried and enlarged contact hole and methods of fabricating the same: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit...

20060197163 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device comprising: a semiconductor layer having a film formation face in a side wall, the side wall being film-formed with epitaxial-growth; a gate electrode arranged on the side wall of the semiconductor layer; a source layer arranged in one side of the gate electrode, the source layer being...

20060197164 - Epitaxially deposited source/drain: An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode....

20060197166 - Semiconductor device and method of manufacturing the same: A semiconductor device which includes a field effect transistor having a gate electrode on the upper side of a semiconductor substrate, with a gate insulation film therebetween, wherein at least the gate insulation film side of the gate electrode includes a film containing hafnium and silicon....

20060197165 - Semiconductor device having a dual gate electrode and methods of forming the same: A semiconductor device having a dual gate electrode and a method of forming the same are provided. The semiconductor device includes a substrate including first and second regions. A first gate electrode formed of a first metal silicide is disposed on the substrate of the first region. A second gate...

20060197167 - Electromagnetic actuator: An electromagnetic actuator comprises an driven member and magnetostrictive elements which change the dimensions thereof when activated or deactivated by selectively applying magnetic flux therein. The driven member is moved in a selected direction when the appropriate elements are activated and deactivated in a controlled manner....

20060197168 - Semiconductor device, magnetic sensor, and magnetic sensor unit: A semiconductor device, comprising a semiconductor chip; a pad electrode; an electrode portion; a wiring portion. An insulating portion is formed from electrically insulating material, covering the surface of the semiconductor chip and sealing the sensor element, wiring portion and electrode portion, in a state which exposes at least the...

20060197169 - Method and structure to reduce optical crosstalk in a solid state imager: Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away and disposed of as waste during fabrication are left as conserved sections. These conserved sections are used to amend the properties and performance of the imager...

20060197170 - Dye-sensitized solar cell: A dye-sensitized solar cell with high conversion efficiency is provided. The dye-sensitized solar cell according to the present invention has, between an electrode (2) formed on a surface of a transparent substrate (1) and a counter electrode (6), a light-absorbing layer (3) containing light-absorbing particles carrying dye and an electrolyte...

20060197171 - System and method to improve image sensor sensitivity: A method is disclosed for forming at least one image sensor with improved sensitivity along with at least one transistor device. The method comprises forming at least a portion of the transistor device on a substrate, forming the image sensor by doping a predetermined area separated from the transistor device...

20060197172 - Solid-state image pick-up device of photoelectric converting film lamination type: A solid-state image pick-up device of a photoelectric converting film lamination type comprising: a semiconductor substrate; and at least three layers of photoelectric converting films each of which is interposed between a common electrode film and pixel electrode films, the pixel electrode films corresponding to pixels respectively, wherein said at...

20060197173 - Movable sensor device: A movable sensor device includes a laminate body in which a micromechanical acting layer having a movable sensor structure and a coating layer coated on the micromechanical acting layer is successively laminated on a substrate. A draft portion penetrates through the laminate body in the lamination direction. The draft portion...

20060197174 - Semiconductor device and inspection method thereof: A semiconductor device is disclosed. The device has a photodiode isolated by element isolating regions (Ia, 14a, 14b) characterized by the following facts: on the principal surface of first semiconductor layer 11 of the first electroconductive type, second semiconductor layer 12 of the second electroconductive type is formed; element isolating...

20060197175 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with...

20060197176 - Electronic subassembly having conductive layer, conductive film and method of making the same: The present invention relates to an electronic subassembly having a conductive layer, a conductive film and a method of making the same. The conductive film includes a supporting layer (31), a conductive layer (32) and a connection layer (33), all of which are orderly stacked. The connection layer (33) is...

20060197177 - Semiconductor devices having line type active regions and methods of fabricating the same: In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line...

20060197178 - Electrical fuses with redundancy: The present disclosure provides an electrical fuse cell with redundancy features and the method for operating the same. The fuse cell includes a first set of electrical fuses having at least one electrical fuse contained therein, and a second set of electrical fuses having at least one electrical fuse for...

20060197179 - Dense semiconductor fuse array: The present invention provides a dense semiconductor fuse array having common cathodes. The dense semiconductor fuse array of the present invention occupies less area than conventional semiconductor fuse arrays, can comprise integrated diodic components, and can require only one metal wiring layer for making electrical connections to the fuse array....

20060197181 - Semiconductor device, stacked structure, and manufacturing method: An array of electrically conductive members, formed around the edges of a semiconductor device or chip, penetrate from one major surface of the device to the other major surface. In an area located inward of this array, a multiplicity of thermally conductive members also penetrate from one major surface to...

20060197180 - Three-dimensional memory structure and manufacturing method thereof: A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n-type polysilicon layer. The first stack layer is patterned to form...

20060197182 - High frequency integrated circuits: The specification describes a silicon-on-silicon interconnection arrangement to implement high performance RF impedance matching using off-chip passive components. The RF sections of the system are dis-integrated into separate RF functional chips, and the functional chips are flip-chip mounted on a high resistivity silicon intermediate interconnect substrate (SIIS). The passive devices...

20060197184 - Capacitor parts: A capacitor parts of the present invention, includes a substrate, a plurality of capacitor elements arranged on the substrate and composed of a lower electrode, a dielectric layer, and an upper electrode respectively, a lower electrode rewiring layer formed over the plurality of capacitor elements and connected electrically to lower...

20060197183 - Improved mim capacitor structure and process: An improved MIM capacitor structure and method where a selective plating process is used to form the capping layer on the copper capacitor electrodes. The metallic passivation layers prevent copper diffusion and enhance the reliability of the MIM capacitor....

20060197185 - Bipolar device compatible with cmos process technology: The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the...

20060197186 - Light valve and method for manufacturing the same: This invention relates to a light valve (100) and a method for manufacturing the same. The light valve includes a substrate (10), a first comb-shaped electrode (40) and a second comb-shaped electrode (50). The substrate has a first through hole (13). The first comb-shaped electrode is formed on the substrate...

20060197187 - Semiconductor device and method for producing same: The semiconductor device includes a semiconductor body having a first and an opposite second main surface and side faces connecting the main surfaces, a circuit region in the semiconductor body adjacent to the first main surface, having a circuit contact terminal, a metallization region extending from the circuit contact terminal...

20060197188 - Photodiode array and method for making thereof: Disclosed is a photodiode array comprising a semiconductor substrate; a plurality of photodiodes formed on the semiconductor substrate; and crystal fused regions losing crystallinity by fusing a semiconductor material of the photodiodes between the plurality of photodiodes....

20060197189 - Varactor device: A varactor device includes a capacitance circuit having a capacitor set and a first transistor connected across the capacitor set; a first variable resistor; and a second transistor coupled to the first transistor and connected in series to the first variable resistor for feeding an output signal generated by applying...

20060197190 - Method of fabricating wafer-level packaging with sidewall passivation and related apparatus: A chip-scale or wafer-level package having passivation layers on substantially all surfaces thereof to form a hermetically sealed package is provided. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a...

20060197191 - Chip structure and wafer structure: A chip structure comprising a substrate, a circuitry unit, a plurality of bonding pads, a first passivation layer and a redistribution layer is provided. The circuitry unit is disposed on the substrate, and the bonding pads are disposed on the circuitry unit. Moreover, the first passivation layer is disposed on...

20060197192 - Semiconductor device: A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type provided on the semiconductor layer, the first semiconductor region being one of an anode region and a cathode region; a second semiconductor region of the first conductivity type provided...

20060197193 - Superconductor wires for back end interconnects: An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the electrically conductive interconnects are formed of the superconducting material. In some...

20060197194 - Laser-based technique for the fabrication of embedded electrochemical cells and electronic components: A method is provided for embedding electronic components including electrochemical cells within a circuit board substrate. The method includes micromachining the printed circuit board substrate to a selective depth to form a recess. A component is inserted into the recess and an electrical connection is established between the electrical component...

20060197195 - Integrated circuit package: The specification describes a leadframe that is aimed at high-performance digital IC devices with high-pin counts, and packaged using wire bond technology. According to the invention the configuration of the paddle is modified to add a new dimension to the leadframe design. In a preferred embodiment, one or more slots...

20060197196 - Semiconductor device: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal....

20060197197 - Surface acoustic wave device and manufacruring method thereof: In the surface acoustic wave device including a lead frame made of metal in which a plurality of inner leads 9 are formed, wherein a chip 1 comprising at least one piezoelectric substrate is mounted on a resin base 3 into which a lead frame is molded integrally, are provided...

20060197198 - Semiconductor package with passive device integration: A system is provided for an integrated circuit package including a leadframe with a lead finger. A groove is in a lead finger for a conductive bonding agent and a passive device is in the groove to be held by the conductive bonding agent....

20060197199 - Leadframe, coining tool, and method: Semiconductor leadframes are provided with selected coined and uncoined areas. The coined areas are arranged to coincide with connection sites for electrical couplings, and the uncoined areas are arranged to provide a secure mechanical bond between leadframe and die attach material or leadframe and encapsulant. Methods are disclosed for forming...

20060197200 - Semiconductor device: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal....

20060197203 - Die structure of package and method of manufacturing the same: A die structure of a package is provided. The die structure of the package includes a carrier and a die. The die includes a first portion and a second portion. The top surface of the first portion is an active surface. The second portion is configured below the first portion....

20060197201 - Image sensor structure: An image sensor structure includes a substrate, a photosensitive chip, a plurality wires, a plurality of ball elements, a transparent layer, and a glue layer. The substrate has an upper surface and a lower surface. The photosensitive chip has a plurality of bonding pads, and is mounted on the upper...

20060197202 - Photo detector package: A photo detector package is provided. The photo detector package includes a carrier, a photo sensor and a calibration module. The photo sensor having an active surface is disposed on the carrier. The calibration module is disposed on the carrier. The calibration module is electrically connected to the photo sensor....

20060197204 - Semiconductor device: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a...

20060197208 - Chip-packaging with bonding options having a plurality of package substrates: Chip-packaging with bonding options having a plurality of package substrates. The chip-packaging includes first and second package substrates, a chip, and a lead frame. The chip having a plurality of bonding pads is mounted on the first package substrate. One of these bonding pads is connected to the first package...

20060197207 - Integrated circuit package system with die and package combination: An integrated package system with die and package combination including forming a leadframe having internal leads and external leads, encapsulating a first integrated circuit on the leadframe, and encapsulating a second integrated circuit over the first integrated circuit....

20060197211 - Semiconductor device and method of stacking semiconductor chips: In a semiconductor device, two or more semiconductor chips are stacked, a first semiconductor chip has electrical contact pads at such positions that form a mirror image of electrical contact pads provided on a second semiconductor chip; and the electrical contact pads on the first semiconductor chip are positioned opposite...

20060197212 - Semiconductor device, method for designing the same and recording medium that can be read by computer in which program for designing semiconductor device is recorded: A semiconductor device of the present invention comprises a first semiconductor chip that includes a first internal circuit and at least one first conductive pad which is provided on its upper surface and is not connected to the first internal circuit, a second semiconductor chip provided on the first. semiconductor...

20060197210 - Stack semiconductor package formed by multiple molding and method of manufacturing the same: Provided are a stack semiconductor package manufactured by multiple molding that can prevent the breakage due to stress concentration at a connecting portion between separate semiconductor packages and a method of manufacturing the same. The stacked semiconductor packages are combined together through sealing resins by molding them multiple times, resulting...

20060197206 - Stacked device package for peripheral and center device pad layout device: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device is disclosed. An outer peripheral portion of the second semiconductor device overhangs both the...

20060197209 - Stacked integrated circuits package system with dense routability and high thermal conductivity: A stacked integrated circuits package system is provided providing a first substrate, mounting a first integrated circuit on a second substrate, attaching the first integrated circuit, by a side opposite the second substrate, to the first substrate, mounting a second integrated circuit to the second substrate, connecting the second integrated...

20060197205 - Stacked semiconductor packages and method therefor: A stackable semiconductor package and method includes providing a first semiconductor package having a first plurality of lower leads and a first plurality of upper leads. A second semiconductor package having a second plurality of lower leads is provided. The second plurality of lower leads is attached to the first...

20060197213 - Magnetic self-assembly for integrated circuit packages: An integrated circuit package may include a substrate and an integrated circuit. The substrate may include at least one region, and a first magnetic material associated with the at least one region. The integrated circuit may have a second magnetic material associated therewith. The second magnetic material may be attracted...

20060197214 - Integrated circuit chip: An integrated circuit chip is provided. The chip includes a silicon substrate, a circuit, a seal ring, a ground ring and a guard ring. The circuit is formed on the silicon substrate and has an input/output (I/O) pad. The seal ring is formed on the silicon substrate and surrounds the...

20060197215 - Hermetic mems package and method of manufacture: A swage hermetic sealing of a MEMS or microdevice or nanodevice package using high force. A cutting and flowing edge 430 is formed on a package cover which is pressed into a mating , integral gasket 425 on a package base. A material extension of the package cover 450 is...

20060197216 - Semiconductor package structure and method for manufacturing the same: A semiconductor package structure comprises a chip, a plurality of via holes, a lid, an adhesive ring and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surfaces; the via holes penetrate the chip and are electrically connected...

20060197217 - Semiconductor package structure and method for manufacturing the same: A semiconductor package structure comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surface; pad extension traces are electrically connected to...

20060197219 - Heat sink and package structure: A heat sink for conducting a coolant is provided. The heat sink includes a casing and a porous material layer. The porous material layer is disposed inside the casing, and the coolant is conducted into the porous material layer. Moreover, a package structure that dissipates heat by use of a...

20060197218 - Hip package structure: A chip package structure is provided, including a package substrate, a chip, a heat spreader, and a molding compound. The chip is disposed on a surface of the package substrate, and electrically connected thereof. The heat spreader is disposed on the surface of the package substrate, and the heat spreader...

20060197220 - Semiconductor device having a plastic housing and external connections and method for producing the same: A semiconductor device having a plastic housing and external connections, and to a method for producing the same is disclosed. In one embodiment, the plastic housing has a housing external contour made of plastic external areas with a top side, an underside opposite to the top side, and edge sides....

20060197221 - Integrated circuit having memory disposed thereon and method of making thereof: An integrated circuit having memory disposed thereon and method of making thereof includes a standard dimension carrier substrate and an information router integrated on the carrier substrate. Further included therein is at least one system memory integrated on the carrier substrate and in electrical communication with the information router across...

20060197222 - Arrangement of an electrical component placed on a substrate, and method for producing the same: An electrical component is placed on a substrate. At least one film comprising a plastic material is connected to the component and to the substrate in such a way that a surface contour defined by the component and the substrate is represent is represented in a surface contour of the...

20060197223 - System for different bond pads in an integrated circuit package: An integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is over the substrate. A second metallurgy layer is over the first metallurgy layer. A protective layer is over the first contact pad....

20060197224 - Multilayered cap barrier in microelectronic interconnect structures: Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures...

20060197225 - Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines: The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate....

20060197226 - Nonvolatile semiconductor memory device having element isolating region of trench type: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer...

20060197227 - Semiconductor structures and methods for fabricating semiconductor structures comprising high dielectric constant stacked structures: Semiconductor structures, and methods for fabricating semiconductor structures, comprising high dielectric constant stacked structures are provided. A stacked dielectric structure (16) in accordance with one exemplary embodiment of the present invention has a first amorphous dielectric layer (18) comprising HfXZr1-XO2, where 0≦X≦1. An amorphous interlayer (20) overlies the first amorphous...

20060197229 - Semiconductor device: According to the present invention, one or more reinforcing vias (7) or reinforcing metal layers are disposed on the inner side of connecting electrodes (5). With this configuration, strength increases relative to a load applied for mounting a semiconductor element (3) and the sinking of the connecting electrodes (5) is...

20060197228 - Single mask process for variable thickness dual damascene structures, other grey-masking processes, and structures made using grey-masking: By using a multiple grey tone mask with at least two greys in semiconductor manufacture, multiple wiring thicknesses can now be made in a single level where previously only one wiring thickness could be provided. For example, power and signal wires of different thicknesses in a single layer can be...

20060197231 - Backend metallization method and device obtained therefrom: A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant material. The mask prevents etchant from etching an area within a dielectric material near a conductive plug. The mask may be formed of a...

20060197230 - Semiconductor device and manufacturing method thereof: A semiconductor device comprises a first insulating film formed over a semiconductor substrate, a second insulating film formed on the first insulating film, a contact plug made of a conductive material vertically penetrating the first and second insulating films and extending on the second insulating film, and a conductor film...

20060197233 - Die attach material for tbga or flexible circuitry: An attachment material is provided between the die and the solder balls of a TBGA or other flexible circuitry package that is sufficiently compliant to absorb pressure between the two, so as not to apply stress to the solder balls. The attachment material is also sufficiently rigid, with a low...

20060197232 - Planar microspring integrated circuit chip interconnection to next level: An interconnect structure for interconnecting an integrated circuit (IC) chip to a next level, a method of fabricating the interconnect at wafer level, and a method of interconnecting an integrated circuit (IC) chip to the next level. The interconnect structure comprises one or more planar micro-spring elements formed on a...

20060197234 - Semiconductor device including a semiconductor chip with signal contact areas and supply contact areas, and method for producing the semiconductor device: A semiconductor device includes a semiconductor chip, where the semiconductor chip includes signal contact areas and supply contact areas. The signal contact areas are arranged on edge regions of the active top side of the semiconductor chip and are electrically connected to external signal exterior connections of the semiconductor device...

20060197235 - Electronic device components including protective layers on surfaces thereof: An electronic device component, such as a semiconductor element device or semiconductor device component includes on selected portions of a surface thereof. One or more conductive features may be exposed through the protective element. The protective element includes a plurality of adjacent, mutually adhered regions. The adjacent, mutually adhered regions...

20060197236 - Curable composition having low coefficient of thermal expansion, method of making an integrated circuit, and an integrated circuit made there from: wherein X is an aromatic ring or a six membered cycloaliphatic ring, m is from about 0 to about 2, n is from about 1 to about 3, Z is an epoxy group of empirical formula: C2H3O, p is a number from about 2 to about 3, and (ii) a...

20060197237 - Semiconductor device and semiconductor wafer: A semiconductor device comprises a semiconductor substrate having a first surface and a second surface, and a first multilayer laminated structure film which is formed in the first surface of the semiconductor substrate and has a first layer having a first refractive index, a second layer formed on the first...

20060197076 - Carbon nanotube resonator transistor and method of making same: A resonant transistor includes a substrate, a source and a drain formed on the substrate, an input electrode and a carbon nanotube gate. A gap is formed between the source and the drain. The input electrode is formed on the substrate. The carbon nanotube gate is clamped on one end...

20060197081 - Light-emitting device and method for manufacturing the same: The present invention provides an organic light-emitting element where a lower electrode, an organic compound layer and an upper electrode are laminated on a substrate, wherein the upper electrode of the organic EL element is formed by a laminate of at least a conductive first inorganic film, a conductive organic...

20060197077 - Metal complex compound and organic electroluminescent device using same: A metal complex compound having a special structure containing metals such as iridium. An organic electroluminescence device which comprises at least one organic thin film layer sandwiched between a pair of electrode consisting of an anode and a cathode, wherein the organic thin film layer comprises the above metal complex...

20060197079 - Method of manufacturing thin film transistor, thin film transistor manufactured by the method, and display device employing the same: A method of manufacturing a thin film transistor is capable of enhancing pattern precision of an organic semiconductor layer and simplifying a patterning process. The method includes forming an organic insulating film on a substrate and forming a bank having the first and second concave portions and a third concave...

20060197078 - Organic light-emitting display device having high light utilization: An organic light-emitting display device includes a light-emitting layer (10), a light permeable layer (20) and a prismatic film (40). The light permeable layer is positioned on the light-emitting layer, and the prismatic film is placed on the light permeable layer. The prismatic film includes a plurality of prisms (42)....

20060197080 - Thin film forming device, method of forming a thin film, and self-light-emitting device: Measure of forming an EL layer by selectively depositing through evaporation a material for forming the EL layer at a desired location is provided. When a material for forming an EL layer is deposited, a mask (113) is provided between a sample boat (111) and a substrate (110). By applying...

20060197082 - Transistor including physical property-changing layer, method of operating transistor, and method of manufacturing transistor: A transistor using a physical property-changing layer, a method of operating the transistor, and a method of manufacturing the transistor are provided. The transistor may include an insulation layer formed on a substrate, the first and second conductive layer patterns, the physical property-changing layer, a dielectric layer, for example, a...

20060197083 - Optical sensor: The present invention aims at providing a photodetector which can detect the incident light intensity with a high speed while having a wide dynamic range for incident light intensity detection. Each photodiode PDm,n generates electric charges Q by an amount corresponding to the intensity of light incident thereon. An electric...

20060197084 - Organic semiconductor device: An organic semiconductor device includes at least p-type and n-type channel organic semiconductor elements. Each organic semiconductor element includes a pair of a source electrode and a drain electrode which are facing each other, an organic semiconductor layer deposited between the source electrode and the drain electrode such that a...

20060197086 - Organic light emitting diode display and manufacturing method thereof: An organic light emitting display according to an embodiment of the invention includes: a substrate; a first electrode disposed on the substrate; a first partition disposed on the first electrode and having an opening exposing the first electrode; a second partition that is disposed on the first partition, wider than...

20060197088 - Semiconductor device and manufacturing method of the same: It is an object of the present invention to manufacture a minute TFT having an LDD region through process with the reduced manufacturing steps, and form a TFT having a structure suitable for each circuit. It is also an object of the present invention to secure an ON current even...

20060197087 - Thin film transistor: A thin film transistor (TFT) and a manufacturing method thereof are provided. The thin film transistor (TFT) comprises a substrate, a gate, an inter-gate dielectric layer, a channel layer and source/drain regions. A gate is formed over the substrate. An inter-gate dielectric layer is formed over the substrate covering the...

20060197085 - Thin film transistor array panel: A thin film transistor (“TFT”) array panel is provided, which includes: first and second gate lines transmitting gate signals to adjacent pixel rows and disposed adjacent to each other, a data line insulated from the first and the second gate lines and the data line; a first thin film transistor...

20060197089 - Semiconductor device and its manufacturing method: A semiconductor device and its manufacturing method are disclosed. The nitrogen flow is gradually changed to form a semiconductor device with a gate or a source/drain having a nitrified gradient layer structure. Different extents of nitrification inside the nitrified gradient layer structure provide protection and buffering to prevent the undercut...

20060197090 - Pyramid-shaped capacitor structure: A capacitor structure which has a generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on...

20060197091 - Pyramid-shaped capacitor structure: A capacitor structure which has generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on the...

20060197093 - Semiconductor device including semiconductor thin films having different crystallinity, substrate of the same, and manufacturing method of the same, and liquid crystal display and manufacturing method of the same: A method of manufacturing a thin-film semiconductor device substrate includes a step of forming a non-single crystalline semiconductor thin film on a base layer, and an annealing step of irradiating the non-single crystalline semiconductor thin film with an energy beam to enhance crystallinity of a non-single crystalline semiconductor constituting the...

20060197092 - System and method for forming conductive material on a substrate: A method for forming a conductive material on a substrate includes laser annealing a selected portion of a blanket coated material to form a conductive region....

20060197095 - Organic electroluminescent device, method of manufacturing organic electroluminescent device, and electronic apparatus: An organic electroluminescent device includes a first member: a light-emitting element that is formed on the first member; a second member that has a second region bonded to the first region of the first member, and forms a sealing space for sealing the light-emitting element between the first member and...

20060197094 - Semiconductor light emitting device, semiconductor light emitting apparatus, and method of manufacturing semiconductor light emitting device: Disclosed is a semiconductor light emitting device comprising: a substrate having first and second major surfaces and being translucent to light in a first wavelength band; and a semiconductor stacked body provided on the first major surface and including a light emitting layer that emits light in the first wavelength...

20060197096 - Substrate with refractive index matching: This invention provides a composite substrate that has a transparent mechanical support, for example of glass or quartz, a film or thin layer of monocrystalline semi-conductive material and an intermediate antireflective layer located between the thin layer or the semi-conductive film and the support. The composition of the intermediate antireflective...

20060197097 - Image pickup device with color filter: An image pickup device is characterized by including a plurality of pixels having a plurality of photoelectric conversion units, convex interlayer lenses with respect to incident light, the convex interlayer lenses being arranged correspondingly to a photoelectric conversion devices and color filters being arranged for each color on the interlayer...

20060197098 - Light emitting device and illumination apparatus using said light emitting device: A light emitting device including a blue-system semiconductor light emitting element, a green-system semiconductor light emitting element, a yellow fluorescent member which absorbs a part of blue light from the blue-system semiconductor light emitting element and emits yellow-system light as excitation light, and a red fluorescent member which absorbs a...

20060197099 - Semiconductor light emitting device: A semiconductor light emitting device can be configured to prevent diffusion migration of components constituting a linear electrode. The semiconductor light emitting device can include a substrate, at least one semiconductor layer formed on the substrate and having a topmost semiconductor layer, a pad electrode formed from a plurality of...

20060197100 - Reverse polarization light emitting region for a semiconductor light emitting device: A semiconductor light emitting device includes a light emitting layer disposed between an n-type region and a p-type region. The light emitting layer may be a wurtzite III-nitride layer with a thickness of at least 50 angstroms. The light emitting layer may have a polarization reversed from a conventional wurtzite...

20060197101 - Light source module of light emitting diode: A light source module for a light emitting diode (LED) is provided. In the present invention, a common printed circuit board (PCB) is utilized to provide electric current and isolated from the heat dissipation mechanism, and the thermal conductive element, protruding from the LED package structure, is connected to another...

20060197102 - Semiconductor composite apparatus, led, led printhead, and image forming apparatus: A semiconductor composite apparatus includes a substrate and a planarizing layer, and a semiconductor thin film. The planarizing layer is formed on the substrate either directly or indirectly. The planarizing layer includes a first surface that faces the substrate, and a second surface that is on the side of the...

20060197103 - Surface-mountable light-emitting diode structural element: A surface-mountable light emitting diode structural element in which an optoelectronic chip is attached to a chip carrier part of a lead frame, is described. The lead frame has a connection part disposed at a distance from the chip carrier part, and which is electrically conductively connected with an electrical...

20060197104 - Semiconductor device and fabrication method thereof: A semiconductor device includes a first nitride semiconductor layer formed on a substrate and a second nitride semiconductor layer formed on the first nitride semiconductor layer so as to be in contact with the first nitride semiconductor layer. The first nitride semiconductor layer contains a p-type impurity. The second nitride...

20060197105 - Power semiconductor switch: A SiC JFET that includes a plurality of trenches formed in a SiC semiconductor body of one conductivity each trench having a region of another conductivity formed in the bottom and sidewalls thereof....

20060197106 - Semiconductor switches and switching circuits for microwave: The purpose of the present invention is to provide a small-sized switch attaining high isolation of not less than 80 dB, maintaining low insertion loss also in high frequencies not less than 60 GHz. A semiconductor switch according to the present invention utilizes FETs a gate electrode, a source electrode,...

20060197107 - Semiconductor device and production method thereof: A semiconductor device formed from a III-V nitride family semiconductor is disclosed that has a reduced gate leakage current and good interface characteristics between the III-V nitride family semiconductor and a gate insulating film. The semiconductor device includes a semiconductor layer formed from the III-V nitride family semiconductor, a gate...

20060197108 - Total ionizing dose suppression transistor architecture: A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the...

20060197109 - High electron mobility transistor: A HEMT device including a GaN channel structure including a very thin (Al,In,Ga)N subchannel layer that is disposed between a first GaN channel layer and a second GaN channel layer, to effect band bending induced from the piezoelectric and spontaneous charges associated with the (Al,In,Ga)N subchannel layer. This GaN channel/(Al,In,Ga)N...

20060197110 - Semiconductor integrated circuit device using four-terminal transistors: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the...

20060197111 - Semiconductor lsi circuit and a method for fabricating the semiconductor lsi circuit: Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain regions of the nMOSFET and the pMOSFET are...

20060197112 - Optical coupling device: In various aspects, an optical coupling device may include a light emitting element configured to emit an optical signal; a photo receiving element having a serial connected of photo diodes, the photo receiving element configured to receive the optical signal and generate an electrical signal; and a control circuit having...

20060197113 - Solid-state imaging device and method for fabricating same: A solid-state imaging device includes a plurality of pixels two-dimensionally arrayed in a well region disposed on a semiconductor substrate, each pixel including a photoelectric conversion section having a charge accumulation region which accumulates signal charge; an element isolation layer which is disposed on the surface of the well region...

20060197114 - Solid-state image sensor: A solid-state image sensor capable of suppressing blooming and increase of a dark current also when an n-type impurity concentration in a transfer channel region is increased is obtained. In this solid-state image sensor, gate electrodes of a prescribed pixel and another pixel adjacent to the prescribed pixel are provided...

20060197115 - Phase change memory device: A phase change memory device has a semiconductor substrate; a plurality of cell arrays stacked above the semiconductor substrate, each cell array having memory cells arranged in a matrix manner for storing resistance values as data that are determined by phase change of the memory cells, bit lines each commonly...

20060197116 - Electro-optical device: An object of the present invention is to realize a numerical aperture higher than that of a pixel having a conventional construction by using a pixel circuit having a novel construction in an electro-optical device. Therefore, it is utilized that the electric potential of a gate signal line in a...

20060197117 - Stacked semiconductor device and method of fabrication: A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the...

20060197118 - Detection of molecular interactions using a field effect transistor: A sensor for use in the detection of a molecular interaction comprises a field effect transistor (FET) having a core structure and an extended gate structure, the core structure and the extended gate structure being located on substantially separate regions of a substrate, the extended gate structure including an exposed...

20060197119 - Method for forming suspended transmission line structures in back end of line processing: A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the...

20060197121 - Abrupt channel doping profile for fermi threshold field effect transistors: A Fermi threshold voltage FET has Germanium implanted to form a shallow abrupt transition between the semiconductor substrate dopant type, or well dopant type, and a counter doping layer of opposite type closely adjacent the surface of the semiconductor substrate. Germanium is a charge neutral impurity in silicon that significantly...

20060197122 - Charge trapping device: A silicon based semiconductor device and method uses charge trapping to alter a density of carriers available in a channel of a field effect transistor (FET) for conduction. The charge trapping mechanism can be controlled by a source-drain bias voltages applied to the FET, so that the device can be...

20060197124 - Double gate strained-semiconductor-on-insulator device structures: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication....

20060197120 - Gate electrode for semiconductor devices: The present invention provides an MIS type semiconductor device, comprising a semiconductor substrate and a gate electrode formed on the gate insulating film and formed of gate material. The gate electrode comprises: a first layer of activated crystalline gate material having a first side oriented towards a substrate and a...

20060197125 - Methods for forming double gate strained-semiconductor-on-insulator device structures: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication....

20060197123 - Methods for forming strained-semiconductor-on-insulator bipolar device structures: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication....

20060197126 - Methods for forming structures including strained-semiconductor-on-insulator devices: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication....

20060197127 - Semiconductor device: An object is to increase the amount of substrate noise absorbed in a guard ring, and to prevent a malfunction caused by the substrate noise in a semiconductor device including an SOI substrate provided with the guard ring. Then, there is provided a semiconductor device, including: an SOI substrate in...

20060197128 - Ferromagnetic-semiconductor spin polarizer of electrons in nonmagnetic semiconductors: An efficient spin polarizer in nonmagnetic semiconductors is provided. Previous spin injection devices suffered from very low efficiency (less than 35%) into semiconductors. An efficient spin polarizer is provided which is based on ferromagnetic-semiconductor heterostructures and ensures spin polarization of electrons in nonmagnetic semiconductors close to 100% near the ferromagnetic-semiconductor...

20060197129 - Buried and bulk channel finfet and method of making the same: One embodiment of a fin-field effect transistor includes a material stack including a non-inverting su surface channel, a fin of semiconductor material positioned on the material stack, the fin including first and second opposing side surfaces, and a gate electrode positioned on the first and second opposing side surfaces of...

20060197131 - Dram device and method of manufacturing the same: In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation...

20060197130 - Phase change memory devices and fabrication methods thereof: In a memory device, a transistor may be formed on a substrate, and a first electrode may be electrically connected thereto. A phase change material film may be vertically formed on the first electrode, and a second electrode may be formed on the phase change material film....

20060197132 - Sram cell structure and manufacturing method thereof: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over...

20060197133 - Mim capacitor including ground shield layer: An MIM capacitor includes a substrate, a capacitor part having a structure in which a bottom electrode, a dielectric layer and a top electrode are laminated in order, and a ground shield layer formed between the bottom electrode of the capacitor part and the substrate and connected to a predetermined...

20060197134 - Method of manufacturing a metal-insulator-metal capacitor using an etchback process: The present invention provides a method for manufacturing a metal-insulator-metal (MIM) capacitor, a method for manufacturing an integrated circuit having a metal-insulator-metal (MIM) capacitor, and an integrated circuit having a metal-insulator-metal (MIM) capacitor. The method for manufacturing the metal-insulator-metal (MIM) capacitor, among other steps and without limitation, includes providing a...

20060197135 - Semiconductor device having a cylindrical capacitor element: A semiconductor device includes a cylindrical capacitor having a bottom electrode, a capacitor insulator film and a top electrode. The top electrode includes first and second electrode portions insulated from each other and opposing the inner surface and outer surface, respectively, of the bottom electrode. The second electrode portion is...

20060197137 - Memory devices, transistors, memory cells, and methods of making same: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel...

20060197136 - Semiconductor memory device: According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines;...

20060197138 - Use of selective epitaxial silicon growth in formation of floating gates: Apparatus utilizing epitaxial silicon growth on a base structure of a floating gate of a floating-gate memory cell to increase the available coupling area of the floating gate while reducing the spacing between adjacent memory cells. The epitaxial silicon growth facilitates a reduction in spacing between adjacent cells beyond the...

20060197143 - Apparatus and method for split transistor memory having improved endurance: The present invention includes floating gate transistor structures used in non-volatile memory devices such as flash memory devices. In one embodiment, a system includes a CPU and a memory device including an array having memory cells having columnar structures and a floating gate structure interposed between the structures that is...

20060197141 - Charge trapping semiconductor memory element with improved trapping dielectric: A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of a second conduction type provided in the semiconductor substrate, a second doping region of the second conduction type provided in the semiconductor substrate, a channel...

20060197139 - Non-volatile memory device having improved band-to-band tunneling induced hot electron injection efficiency and manufacturing method thereof: A semiconductor device includes a semiconductor substrate having a first conductivity type. The semiconductor substrate includes a first diffusion region having the first conductivity type, a second diffusion region having the first conductivity type, and a channel region between the first diffusion region and the second diffusion region. The device...

20060197142 - Semiconductor storage device, manufacturing method therefor, and portable electronic equipment: A semiconductor storage device has a semiconductor layer having a first conductivity type region and two second conductivity type regions separated from each other by the first conductivity type region, a memory function body formed on a surface of the semiconductor layer, and a gate electrode. The memory function body...

20060197140 - Vertical transistor nvm with body contact structure and method: A semiconductor device (151) is provided which comprises (a) a semiconductor substrate (103); (b) a fin (109) comprising a semiconductor material and being in electrical contact with the substrate; (c) a first floating gate (121) disposed on a first side of said fin; and (d) a control gate (107)....

20060197144 - Nitride storage cells with and without select gate: In the past the high voltage needs and cell leakage currents have limited the scalability of the Nitride cell and made the poly silicon floating gate cell the primary contender for Non-Volatile memories. As the process development has matured and technology has scaled to smaller and smaller dimensions, the Poly-silicon...

20060197145 - Non-volatile memory and manufacturing method and operating method thereof: A non-volatile memory having a plurality of memory units is provided. Each memory unit includes a first memory cell and a second memory cell. The first memory cell is disposed on the substrate. The second memory cell is disposed on one sidewall of the first memory cell and the substrate....

20060197146 - Semiconductor device: A semiconductor device comprises a semiconductor substrate having an upper surface and a lower surface. A semiconductor layer is formed on the upper surface of the semiconductor substrate. A base region of a first conduction type is formed in the semiconductor layer. A source region of a second conduction type...

20060197147 - Improved double gate isolation: A double-gated fin-type field effect transistor (FinFET) structure has electrically isolated gates. In a method for manufacturing the FinFET structure, a fin, having a gate dielectric on each sidewall corresponding to the central channel region, is formed over a buried oxide (BOX) layer on a substrate. Independent first and second...

20060197149 - Semiconductor device and fabrication process thereof, and application thereof: An LDMOS transistor includes a gate insulation film formed on a semiconductor substrate, a gate electrode formed on the gate insulation film, a drain well of a first conductivity type formed in the substrate so as to include a gate region covered with the gate electrode, a channel well of...

20060197148 - Trench power moset and method for fabricating the same: A method for fabricating a trench power MOSFET, comprising an epitaxial layer and a mask layer formed over a substrate, a trench formed in the epitaxial layer and the mask layer, a gate oxide layer formed on the trench, then the mask layer removed, a body well region formed in...

20060197150 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed...

20060197152 - Semiconductor device: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the...

20060197151 - Semiconductor device and method for manufacturing the same: A semiconductor device include a plurality of active element cells including first element regions of a first conductivity type and second element regions of a second conductivity type, the second element regions disposed between the first element regions; and isolation regions disposed between the active element cells so as to...

20060197153 - Vertical transistor with field region structure: A structure of a vertical transistor with field region is provided. The vertical transistor comprises a field-doping region formed in a substrate next to a core region of the vertical transistor. By modulating the doping density, length, and geometrical pattern of the field region, and by connecting the field region...

20060197155 - Nonvolatile memory and manufacturing method thereof: Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFTs. This enables...

20060197156 - Power semiconductor and method of fabrication: This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and methods for their fabrication. A power semiconductor, the semiconductor comprising: a power device, said power device having first and second electrical contact regions and...

20060197154 - Semiconductor component and method of manufacture: A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material,...

20060197158 - Advanced cmos using super steep retrograde wells: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of...

20060197157 - Semiconductor device and method for manufacturing the same: There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate...

20060197159 - Semiconductor device and method of fabricating: Aspects of the present invention include a semiconductor device and method. In a transition region of a semiconductor material region, a near-surface compensation doping area with a conductivity type, which is different than the conductivity type of a transition doping area of the semiconductor material region, is provided in the...

20060197160 - Nonvolatile semiconductor memory device: A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in...

20060197161 - Semiconductor device and semiconductor integrated circuit device: In each of a p-channel MOS transistor and an n-channel MOS transistor, a channel direction is set in the <100> direction and a first stressor film accumulating therein a tensile stress is formed in a STI device isolation structure. Further, a second stressor film accumulating therein a tensile stress is...

20060197162 - Semiconductor devices having a buried and enlarged contact hole and methods of fabricating the same: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit...

20060197163 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device comprising: a semiconductor layer having a film formation face in a side wall, the side wall being film-formed with epitaxial-growth; a gate electrode arranged on the side wall of the semiconductor layer; a source layer arranged in one side of the gate electrode, the source layer being...

20060197164 - Epitaxially deposited source/drain: An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode....

20060197166 - Semiconductor device and method of manufacturing the same: A semiconductor device which includes a field effect transistor having a gate electrode on the upper side of a semiconductor substrate, with a gate insulation film therebetween, wherein at least the gate insulation film side of the gate electrode includes a film containing hafnium and silicon....

20060197165 - Semiconductor device having a dual gate electrode and methods of forming the same: A semiconductor device having a dual gate electrode and a method of forming the same are provided. The semiconductor device includes a substrate including first and second regions. A first gate electrode formed of a first metal silicide is disposed on the substrate of the first region. A second gate...

20060197167 - Electromagnetic actuator: An electromagnetic actuator comprises an driven member and magnetostrictive elements which change the dimensions thereof when activated or deactivated by selectively applying magnetic flux therein. The driven member is moved in a selected direction when the appropriate elements are activated and deactivated in a controlled manner....

20060197168 - Semiconductor device, magnetic sensor, and magnetic sensor unit: A semiconductor device, comprising a semiconductor chip; a pad electrode; an electrode portion; a wiring portion. An insulating portion is formed from electrically insulating material, covering the surface of the semiconductor chip and sealing the sensor element, wiring portion and electrode portion, in a state which exposes at least the...

20060197169 - Method and structure to reduce optical crosstalk in a solid state imager: Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away and disposed of as waste during fabrication are left as conserved sections. These conserved sections are used to amend the properties and performance of the imager...

20060197170 - Dye-sensitized solar cell: A dye-sensitized solar cell with high conversion efficiency is provided. The dye-sensitized solar cell according to the present invention has, between an electrode (2) formed on a surface of a transparent substrate (1) and a counter electrode (6), a light-absorbing layer (3) containing light-absorbing particles carrying dye and an electrolyte...

20060197171 - System and method to improve image sensor sensitivity: A method is disclosed for forming at least one image sensor with improved sensitivity along with at least one transistor device. The method comprises forming at least a portion of the transistor device on a substrate, forming the image sensor by doping a predetermined area separated from the transistor device...

20060197172 - Solid-state image pick-up device of photoelectric converting film lamination type: A solid-state image pick-up device of a photoelectric converting film lamination type comprising: a semiconductor substrate; and at least three layers of photoelectric converting films each of which is interposed between a common electrode film and pixel electrode films, the pixel electrode films corresponding to pixels respectively, wherein said at...

20060197173 - Movable sensor device: A movable sensor device includes a laminate body in which a micromechanical acting layer having a movable sensor structure and a coating layer coated on the micromechanical acting layer is successively laminated on a substrate. A draft portion penetrates through the laminate body in the lamination direction. The draft portion...

20060197174 - Semiconductor device and inspection method thereof: A semiconductor device is disclosed. The device has a photodiode isolated by element isolating regions (Ia, 14a, 14b) characterized by the following facts: on the principal surface of first semiconductor layer 11 of the first electroconductive type, second semiconductor layer 12 of the second electroconductive type is formed; element isolating...

20060197175 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with...

20060197176 - Electronic subassembly having conductive layer, conductive film and method of making the same: The present invention relates to an electronic subassembly having a conductive layer, a conductive film and a method of making the same. The conductive film includes a supporting layer (31), a conductive layer (32) and a connection layer (33), all of which are orderly stacked. The connection layer (33) is...

20060197177 - Semiconductor devices having line type active regions and methods of fabricating the same: In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line...

20060197178 - Electrical fuses with redundancy: The present disclosure provides an electrical fuse cell with redundancy features and the method for operating the same. The fuse cell includes a first set of electrical fuses having at least one electrical fuse contained therein, and a second set of electrical fuses having at least one electrical fuse for...

20060197179 - Dense semiconductor fuse array: The present invention provides a dense semiconductor fuse array having common cathodes. The dense semiconductor fuse array of the present invention occupies less area than conventional semiconductor fuse arrays, can comprise integrated diodic components, and can require only one metal wiring layer for making electrical connections to the fuse array....

20060197181 - Semiconductor device, stacked structure, and manufacturing method: An array of electrically conductive members, formed around the edges of a semiconductor device or chip, penetrate from one major surface of the device to the other major surface. In an area located inward of this array, a multiplicity of thermally conductive members also penetrate from one major surface to...

20060197180 - Three-dimensional memory structure and manufacturing method thereof: A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n-type polysilicon layer. The first stack layer is patterned to form...

20060197182 - High frequency integrated circuits: The specification describes a silicon-on-silicon interconnection arrangement to implement high performance RF impedance matching using off-chip passive components. The RF sections of the system are dis-integrated into separate RF functional chips, and the functional chips are flip-chip mounted on a high resistivity silicon intermediate interconnect substrate (SIIS). The passive devices...

20060197184 - Capacitor parts: A capacitor parts of the present invention, includes a substrate, a plurality of capacitor elements arranged on the substrate and composed of a lower electrode, a dielectric layer, and an upper electrode respectively, a lower electrode rewiring layer formed over the plurality of capacitor elements and connected electrically to lower...

20060197183 - Improved mim capacitor structure and process: An improved MIM capacitor structure and method where a selective plating process is used to form the capping layer on the copper capacitor electrodes. The metallic passivation layers prevent copper diffusion and enhance the reliability of the MIM capacitor....

20060197185 - Bipolar device compatible with cmos process technology: The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the...

20060197186 - Light valve and method for manufacturing the same: This invention relates to a light valve (100) and a method for manufacturing the same. The light valve includes a substrate (10), a first comb-shaped electrode (40) and a second comb-shaped electrode (50). The substrate has a first through hole (13). The first comb-shaped electrode is formed on the substrate...

20060197187 - Semiconductor device and method for producing same: The semiconductor device includes a semiconductor body having a first and an opposite second main surface and side faces connecting the main surfaces, a circuit region in the semiconductor body adjacent to the first main surface, having a circuit contact terminal, a metallization region extending from the circuit contact terminal...

20060197188 - Photodiode array and method for making thereof: Disclosed is a photodiode array comprising a semiconductor substrate; a plurality of photodiodes formed on the semiconductor substrate; and crystal fused regions losing crystallinity by fusing a semiconductor material of the photodiodes between the plurality of photodiodes....

20060197189 - Varactor device: A varactor device includes a capacitance circuit having a capacitor set and a first transistor connected across the capacitor set; a first variable resistor; and a second transistor coupled to the first transistor and connected in series to the first variable resistor for feeding an output signal generated by applying...

20060197190 - Method of fabricating wafer-level packaging with sidewall passivation and related apparatus: A chip-scale or wafer-level package having passivation layers on substantially all surfaces thereof to form a hermetically sealed package is provided. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a...

20060197191 - Chip structure and wafer structure: A chip structure comprising a substrate, a circuitry unit, a plurality of bonding pads, a first passivation layer and a redistribution layer is provided. The circuitry unit is disposed on the substrate, and the bonding pads are disposed on the circuitry unit. Moreover, the first passivation layer is disposed on...

20060197192 - Semiconductor device: A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type provided on the semiconductor layer, the first semiconductor region being one of an anode region and a cathode region; a second semiconductor region of the first conductivity type provided...

20060197193 - Superconductor wires for back end interconnects: An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the electrically conductive interconnects are formed of the superconducting material. In some...

20060197194 - Laser-based technique for the fabrication of embedded electrochemical cells and electronic components: A method is provided for embedding electronic components including electrochemical cells within a circuit board substrate. The method includes micromachining the printed circuit board substrate to a selective depth to form a recess. A component is inserted into the recess and an electrical connection is established between the electrical component...

20060197195 - Integrated circuit package: The specification describes a leadframe that is aimed at high-performance digital IC devices with high-pin counts, and packaged using wire bond technology. According to the invention the configuration of the paddle is modified to add a new dimension to the leadframe design. In a preferred embodiment, one or more slots...

20060197196 - Semiconductor device: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal....

20060197197 - Surface acoustic wave device and manufacruring method thereof: In the surface acoustic wave device including a lead frame made of metal in which a plurality of inner leads 9 are formed, wherein a chip 1 comprising at least one piezoelectric substrate is mounted on a resin base 3 into which a lead frame is molded integrally, are provided...

20060197198 - Semiconductor package with passive device integration: A system is provided for an integrated circuit package including a leadframe with a lead finger. A groove is in a lead finger for a conductive bonding agent and a passive device is in the groove to be held by the conductive bonding agent....

20060197199 - Leadframe, coining tool, and method: Semiconductor leadframes are provided with selected coined and uncoined areas. The coined areas are arranged to coincide with connection sites for electrical couplings, and the uncoined areas are arranged to provide a secure mechanical bond between leadframe and die attach material or leadframe and encapsulant. Methods are disclosed for forming...

20060197200 - Semiconductor device: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal....

20060197203 - Die structure of package and method of manufacturing the same: A die structure of a package is provided. The die structure of the package includes a carrier and a die. The die includes a first portion and a second portion. The top surface of the first portion is an active surface. The second portion is configured below the first portion....

20060197201 - Image sensor structure: An image sensor structure includes a substrate, a photosensitive chip, a plurality wires, a plurality of ball elements, a transparent layer, and a glue layer. The substrate has an upper surface and a lower surface. The photosensitive chip has a plurality of bonding pads, and is mounted on the upper...

20060197202 - Photo detector package: A photo detector package is provided. The photo detector package includes a carrier, a photo sensor and a calibration module. The photo sensor having an active surface is disposed on the carrier. The calibration module is disposed on the carrier. The calibration module is electrically connected to the photo sensor....

20060197204 - Semiconductor device: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a...

20060197208 - Chip-packaging with bonding options having a plurality of package substrates: Chip-packaging with bonding options having a plurality of package substrates. The chip-packaging includes first and second package substrates, a chip, and a lead frame. The chip having a plurality of bonding pads is mounted on the first package substrate. One of these bonding pads is connected to the first package...

20060197207 - Integrated circuit package system with die and package combination: An integrated package system with die and package combination including forming a leadframe having internal leads and external leads, encapsulating a first integrated circuit on the leadframe, and encapsulating a second integrated circuit over the first integrated circuit....

20060197211 - Semiconductor device and method of stacking semiconductor chips: In a semiconductor device, two or more semiconductor chips are stacked, a first semiconductor chip has electrical contact pads at such positions that form a mirror image of electrical contact pads provided on a second semiconductor chip; and the electrical contact pads on the first semiconductor chip are positioned opposite...

20060197212 - Semiconductor device, method for designing the same and recording medium that can be read by computer in which program for designing semiconductor device is recorded: A semiconductor device of the present invention comprises a first semiconductor chip that includes a first internal circuit and at least one first conductive pad which is provided on its upper surface and is not connected to the first internal circuit, a second semiconductor chip provided on the first. semiconductor...

20060197210 - Stack semiconductor package formed by multiple molding and method of manufacturing the same: Provided are a stack semiconductor package manufactured by multiple molding that can prevent the breakage due to stress concentration at a connecting portion between separate semiconductor packages and a method of manufacturing the same. The stacked semiconductor packages are combined together through sealing resins by molding them multiple times, resulting...

20060197206 - Stacked device package for peripheral and center device pad layout device: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device is disclosed. An outer peripheral portion of the second semiconductor device overhangs both the...

20060197209 - Stacked integrated circuits package system with dense routability and high thermal conductivity: A stacked integrated circuits package system is provided providing a first substrate, mounting a first integrated circuit on a second substrate, attaching the first integrated circuit, by a side opposite the second substrate, to the first substrate, mounting a second integrated circuit to the second substrate, connecting the second integrated...

20060197205 - Stacked semiconductor packages and method therefor: A stackable semiconductor package and method includes providing a first semiconductor package having a first plurality of lower leads and a first plurality of upper leads. A second semiconductor package having a second plurality of lower leads is provided. The second plurality of lower leads is attached to the first...

20060197213 - Magnetic self-assembly for integrated circuit packages: An integrated circuit package may include a substrate and an integrated circuit. The substrate may include at least one region, and a first magnetic material associated with the at least one region. The integrated circuit may have a second magnetic material associated therewith. The second magnetic material may be attracted...

20060197214 - Integrated circuit chip: An integrated circuit chip is provided. The chip includes a silicon substrate, a circuit, a seal ring, a ground ring and a guard ring. The circuit is formed on the silicon substrate and has an input/output (I/O) pad. The seal ring is formed on the silicon substrate and surrounds the...

20060197215 - Hermetic mems package and method of manufacture: A swage hermetic sealing of a MEMS or microdevice or nanodevice package using high force. A cutting and flowing edge 430 is formed on a package cover which is pressed into a mating , integral gasket 425 on a package base. A material extension of the package cover 450 is...

20060197216 - Semiconductor package structure and method for manufacturing the same: A semiconductor package structure comprises a chip, a plurality of via holes, a lid, an adhesive ring and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surfaces; the via holes penetrate the chip and are electrically connected...

20060197217 - Semiconductor package structure and method for manufacturing the same: A semiconductor package structure comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surface; pad extension traces are electrically connected to...

20060197219 - Heat sink and package structure: A heat sink for conducting a coolant is provided. The heat sink includes a casing and a porous material layer. The porous material layer is disposed inside the casing, and the coolant is conducted into the porous material layer. Moreover, a package structure that dissipates heat by use of a...

20060197218 - Hip package structure: A chip package structure is provided, including a package substrate, a chip, a heat spreader, and a molding compound. The chip is disposed on a surface of the package substrate, and electrically connected thereof. The heat spreader is disposed on the surface of the package substrate, and the heat spreader...

20060197220 - Semiconductor device having a plastic housing and external connections and method for producing the same: A semiconductor device having a plastic housing and external connections, and to a method for producing the same is disclosed. In one embodiment, the plastic housing has a housing external contour made of plastic external areas with a top side, an underside opposite to the top side, and edge sides....

20060197221 - Integrated circuit having memory disposed thereon and method of making thereof: An integrated circuit having memory disposed thereon and method of making thereof includes a standard dimension carrier substrate and an information router integrated on the carrier substrate. Further included therein is at least one system memory integrated on the carrier substrate and in electrical communication with the information router across...

20060197222 - Arrangement of an electrical component placed on a substrate, and method for producing the same: An electrical component is placed on a substrate. At least one film comprising a plastic material is connected to the component and to the substrate in such a way that a surface contour defined by the component and the substrate is represent is represented in a surface contour of the...

20060197223 - System for different bond pads in an integrated circuit package: An integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is over the substrate. A second metallurgy layer is over the first metallurgy layer. A protective layer is over the first contact pad....

20060197224 - Multilayered cap barrier in microelectronic interconnect structures: Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures...

20060197225 - Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines: The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate....

20060197226 - Nonvolatile semiconductor memory device having element isolating region of trench type: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer...

20060197227 - Semiconductor structures and methods for fabricating semiconductor structures comprising high dielectric constant stacked structures: Semiconductor structures, and methods for fabricating semiconductor structures, comprising high dielectric constant stacked structures are provided. A stacked dielectric structure (16) in accordance with one exemplary embodiment of the present invention has a first amorphous dielectric layer (18) comprising HfXZr1-XO2, where 0≦X≦1. An amorphous interlayer (20) overlies the first amorphous...

20060197229 - Semiconductor device: According to the present invention, one or more reinforcing vias (7) or reinforcing metal layers are disposed on the inner side of connecting electrodes (5). With this configuration, strength increases relative to a load applied for mounting a semiconductor element (3) and the sinking of the connecting electrodes (5) is...

20060197228 - Single mask process for variable thickness dual damascene structures, other grey-masking processes, and structures made using grey-masking: By using a multiple grey tone mask with at least two greys in semiconductor manufacture, multiple wiring thicknesses can now be made in a single level where previously only one wiring thickness could be provided. For example, power and signal wires of different thicknesses in a single layer can be...

20060197231 - Backend metallization method and device obtained therefrom: A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant material. The mask prevents etchant from etching an area within a dielectric material near a conductive plug. The mask may be formed of a...

20060197230 - Semiconductor device and manufacturing method thereof: A semiconductor device comprises a first insulating film formed over a semiconductor substrate, a second insulating film formed on the first insulating film, a contact plug made of a conductive material vertically penetrating the first and second insulating films and extending on the second insulating film, and a conductor film...

20060197233 - Die attach material for tbga or flexible circuitry: An attachment material is provided between the die and the solder balls of a TBGA or other flexible circuitry package that is sufficiently compliant to absorb pressure between the two, so as not to apply stress to the solder balls. The attachment material is also sufficiently rigid, with a low...

20060197232 - Planar microspring integrated circuit chip interconnection to next level: An interconnect structure for interconnecting an integrated circuit (IC) chip to a next level, a method of fabricating the interconnect at wafer level, and a method of interconnecting an integrated circuit (IC) chip to the next level. The interconnect structure comprises one or more planar micro-spring elements formed on a...

20060197234 - Semiconductor device including a semiconductor chip with signal contact areas and supply contact areas, and method for producing the semiconductor device: A semiconductor device includes a semiconductor chip, where the semiconductor chip includes signal contact areas and supply contact areas. The signal contact areas are arranged on edge regions of the active top side of the semiconductor chip and are electrically connected to external signal exterior connections of the semiconductor device...

20060197235 - Electronic device components including protective layers on surfaces thereof: An electronic device component, such as a semiconductor element device or semiconductor device component includes on selected portions of a surface thereof. One or more conductive features may be exposed through the protective element. The protective element includes a plurality of adjacent, mutually adhered regions. The adjacent, mutually adhered regions...

20060197236 - Curable composition having low coefficient of thermal expansion, method of making an integrated circuit, and an integrated circuit made there from: wherein X is an aromatic ring or a six membered cycloaliphatic ring, m is from about 0 to about 2, n is from about 1 to about 3, Z is an epoxy group of empirical formula: C2H3O, p is a number from about 2 to about 3, and (ii) a...

20060197237 - Semiconductor device and semiconductor wafer: A semiconductor device comprises a semiconductor substrate having a first surface and a second surface, and a first multilayer laminated structure film which is formed in the first surface of the semiconductor substrate and has a first layer having a first refractive index, a second layer formed on the first...