Active solid-state devices (e.g., transistors, solid-state diodes) inventions 08/06

20060192193 - Phase-change ram and method for fabricating the same: A PRAM and a fabricating method thereof are provided. The PRAM includes a transistor and a data storage capability. The data storage capability is connected to the transistor. The data storage includes a top electrode, a bottom electrode, and a porous PCM layer. The porous PCM layer is interposed between...

20060192194 - Electronic device contact structures: Electronic device contact structures are disclosed....

20060192195 - Nitride semiconductor light emitting device: A nitride semiconductor light emitting device is provided. The nitride semiconductor light emitting device includes: an n-type nitride semiconductor layer; an Incontaining super lattice structure layer formed above the n-type nitride semiconductor layer; a first electrode contact layer formed above the super lattice structure layer; a first cluster layer formed...

20060192196 - Method of increasing efficiency of thermotunnel devices: The present invention comprises a tunneling device in which the collector electrode is modified so that tunneling of higher energy electrons from the emitter electrode to the collector electrode is enhanced. In one embodiment, the collector electrode is contacted with an insulator layer, preferably aluminum or silicon nitride, disposed between...

20060192199 - Celluloses and devices thereof: An electronic device including a dielectric layer including a cellulose derivative is disclosed....

20060192198 - Light-emitting copolymers and electronic devices using such copolymers: The invention provides novel pentaphenylene copolymers which are useful in electronic devices....

20060192197 - Organic thin film transistor: An organic thin film transistor utilizing an organic semiconductor film is composed of a first substrate, a gate electrode, a gate insulation film, an organic semiconductor film, a source electrode, a drain electrode, a protective film and a second substrate, and produced by forming a gate electrode, a gate insulation...

20060192200 - Test key structure: A test key structure includes a substrate, a closed loop, a plurality of spacers, a plurality of first and second doping regions and a plurality of contacts. The closed loop having two conductive lines and two connection portions is located on the substrate. Each connection portion connects to one end...

20060192201 - Display device: The present invention provides an active matrix type display device having a high aperture ratio and a required auxiliary capacitor. A source line and a gate line are overlapped with part of a pixel electrode. This overlapped region functions to be a black matrix. Further, an electrode pattern made of...

20060192202 - Semiconductor device forming method: In thin film transistors (TFTS) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate....

20060192205 - Electro-optical device and electronic device: The switching TFT 201 formed within a pixel has a multi-gate structure, which is a structure which imposes an importance on reduction of OFF current value. Further, the current control TFT 202 has a channel width wider than that of the switching TFT to make a structure appropriate for flowing...

20060192203 - Solid-state image pickup device: An imaging area is provided on a surface of a semiconductor substrate, and light-receiving portions and transfer channels are provided in the imaging area. A group of transfer electrodes extends in a direction crossing the transfer channels on the imaging area. A group of transfer signal lines, which are provided...

20060192204 - Thin film transistor panel: A thin film transistor panel including: a transparent substrate; scanning lines made of a light blocking electroconductive material to be formed on the transparent substrate; data lines formed on the transparent substrate to be perpendicular to the scanning lines and made of a light blocking electroconductive material; thin film transistors,...

20060192206 - Flip-chip type nitride semiconductor light emitting diode: Disclosed herein is a flip-chip type nitride semiconductor light emitting diode. The light emitting diode comprises an n-type nitride semiconductor layer formed on a transparent substrate and having a substantially rectangular upper surface, an n-side electrode which comprises at least one bonding pad adjacent to at least one corner of...

20060192212 - High brightness light emitting diode and fabrication method thereof: A light emitting diode includes a substrate tilted toward first and second directions simultaneously, a first cladding layer formed with a semiconductor material of a first conductive type on the substrate, an active layer formed on the first cladding layer, and a second cladding layer formed with a semiconductor material...

20060192211 - Light emitting diode and method for fabricating same: wherein t1 is a film thickness [nm] of the AlGaAs layer, t2 is a film thickness [nm] of the AlInP layer, λ0 is a wavelength [nm] of a light to be reflected, n1 is a refractive index of the AlGaAs layer to the wavelength of the light to be reflected,...

20060192213 - Light-emitting device: A light-emitting device includes electron emitters for planarly emitting electrons, collector electrodes disposed to face corresponding one electron emitter, and a phosphor formed near the collector electrodes. During a period when electrons are emitted from the electron emitter, a collector voltage is applied to each of the collector electrodes in...

20060192210 - Light-emitting element, light-emitting device, and electronic apparatus: A light-emitting element includes a first electrode, a second electrode, and a light-emitting layer disposed between the first electrode and the second electrode, the light-emitting layer including an inorganic semiconductor material, a first material, and a second material, at least one of the first material and the inorganic semiconductor material...

20060192207 - Nitride semiconductor light emitting device: Provided is a nitride semiconductor light emitting device having enhanced output power and resistance to electrostatic discharge. The light emitting device comprises an n-side contact layer formed on a substrate, a current diffusion layer formed on the n-side contact layer, an active layer formed on the current diffusion layer, and...

20060192209 - Optical integrated semiconductor light emitting device: An optical integrated semiconductor light emitting device with improved light emitting efficiency is provided by preventing leak current from flowing through a high defect region of the substrate. The optical integrated semiconductor light emitting device includes: a substrate, in which in a low defect region made of crystal having a...

20060192214 - Semiconductor device, led print head, that uses the semiconductor, and image forming apparatus that uses the led print head: A semiconductor device includes a substrate, conductive layer, semiconductor thin films, and individual electrodes. The conductive layer is formed on the substrate and serves as a common electrode. The thin films are bonded on the conductive layer. Each of the plurality of semiconductor thin films includes at least one active...

20060192208 - Wavelength-convertible light emitting device: The present invention provides a wavelength-convertible LED which has first and second surfaces, including first and second conductivity-type cladding layers and an active layer formed between the first and second conductivity-type cladding layers to emit a specific wavelength light. The invention also includes at least a piezoelectric layer on at...

20060192215 - Light emitting device and light emitting system: A light emitting device in accordance with the present invention includes a light emitting element and a light sensor for detecting the luminous intensity of the light emitted from the light emitting element. The light emitting element includes a lower electrode, a light emitting material layer including at least a...

20060192216 - Semiconductor light emitting device and surface light emitting device: A semiconductor light emitting device may include a first supporting member having a main surface; a semiconductor light emitting element having a light emitting layer and provided on the main surface of the first supporting member, the light emitting layer being substantially parallel to the main surface of the first...

20060192217 - High efficiency light emitting diode (led) with optimized photonic crystal extractor: A high efficiency, and possibly highly directional, light emitting diode (LED) with an optimized photonic crystal extractor. The LED is comprised of a substrate, a buffer layer grown on the substrate (if needed), an active layer including emitting species, one or more optical confinement layers that tailor the structure of...

20060192218 - Nitride semiconductor light emitting device, and method of fabricating nitride semiconductor light emitting device: In a nitride semiconductor light emitting device, a first conductivity type nitride semiconductor layer is provided on a support base and a second conductivity type nitride semiconductor layer is provided on the support base. An active region is provided between the first conductivity type nitride semiconductor layer and the second...

20060192221 - Methods, apparatus, and systems with semiconductor laser packaging for high modulation bandwidth: Semiconductor packaging methods, systems and apparatus for semiconductor lasers to achieve high modulation bandwidth. Systems, methods and apparatus for minimizing the inductance of wire bond interconnects and impedance matching in a semiconductor laser package. Systems, methods and apparatus for monitoring a photocurrent in order to provide automatic power control (APC)...

20060192219 - Novel red phosphors for solid state lighting: A red phosphor composition in combination with a semiconductor light emitting device (e.g., VCSEL, LED, or LD), preferably a GaN based device, that emits light at a bright violet- blue light range, i.e., having a wavelength in the range of 400 nm to 600 nm, which can be further combined...

20060192220 - Organic el panel: Each pixel includes a region where a lower reflection film is not present. In each pixel, there is a region where a microcavity structure is formed between a counter electrode and a lower reflection film and another region where the microcavity structure is not formed. The regions differentiated in cavity...

20060192222 - Light emitting device: A light emitting device is provided. The light emitting device includes a substrate, at least one light emitting chip and a first heat dissipation element. The substrate has a top surface and a bottom surface, and contacts are disposed on the top surface. The light emitting chip disposed on the...

20060192223 - Nitride semiconductor light emitting device: The invention relates to a flip-chip nitride semiconductor LED. In the LED, a light emitting structure has first and second conductivity type nitride semiconductor layers and an active layer interposed therebetween. Each of plurality of first and second electrodes has a bonding pad placed adjacent to a top corner of...

20060192224 - Semiconductor light emitting device: A semiconductor light emitting device includes a mold resin having a cup shape portion on an upper surface of the mold resin. One or more holes penetrate through the cup shape portion to outside of the mold resin and/or one or more trenches extend from the cup-shaped portion to outside...

20060192225 - Light emitting device having a layer of photonic crystals with embedded photoluminescent material and method for fabricating the device: A light emitting device and method for fabricating the device utilizes a layer of photonic crystals with embedded photoluminescent material over a light source. The layer of photonic crystals with the embedded photoluminescent material can be used in different types of light emitting devices, such as lead frame-mounted light emitting...

20060192226 - Liquid container: There are disclosed a cap or lid for a container which has a light emitter that generates zestful reflected light enabling recognition of a content even in a dark place, a container to which a light emitter is attached to generate zestful reflected light, a base member disposed at a...

20060192227 - Composition for preparing electron emitter, electron emitter produced by using the composition, and electron emission device comprising the electron emitter: A composition for preparing an electron emitter, an electron emitter produced by using the composition, and an electron emission device comprising the electron emitter are provided. The composition for preparing an electron emitter includes carbon-based materials and vehicles, wherein the vehicles comprise a polymer having a vinyl pivalate monomer. The...

20060192228 - Compound semiconductor epitaxial substrate and method for manufacturing same: A compound semiconductor epitaxial substrate having a pseudomorphic high electron mobility field effect transistor structure including an InGaAs layer as a strained channel layer and an AlGaAs layer containing n type impurities as a front side electron-donating layer, wherein said substrate contains an InGaP layer in an orderly state on...

20060192229 - Semiconductor device and electronic apparatus using the same: A semiconductor device with high function, multifunction and high added value. The semiconductor device includes a PLL circuit that is provided over a substrate and outputs a signal with a correct frequency. By providing such a PLL circuit over the substrate, a semiconductor device with high function, multifunction and high...

20060192230 - Image sensor packages and frame structure thereof: A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice...

20060192231 - Field effect transistor and its manufacturing method: The present invention is an object to provide a high-performance vertical field effect transistor having a microminiaturized structure in which the distance between the gate and the channel is made short not through a microfabrication process, having a large gate capacitance, and so elaborated that the gate can control the...

20060192232 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/drain regions formed on the extension regions, wherein a...

20060192233 - Body potential imager cell: An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to...

20060192234 - Solid-state imaging device: Pixels have a photodiode 1, a transfer gate electrode 2 for transferring charges accumulated in the photodiode 1, a floating diffusion section 3 for accumulating the charge transferred by the transfer gate electrode 2, an amplification transistor 15 in which a gate electrode is connected to the floating diffusion section...

20060192235 - System and method for reducing shorting in memory cells: An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and,...

20060192237 - Magnetic elements with ballistic magnetoresistance utilizing spin-transfer and an mram device using such magnetic elements: A method and system for providing a magnetic element is disclosed. The method and system include providing a pinned layer, a magnetic current confined layer, and a free layer. The pinned layer is ferromagnetic and has a first pinned layer magnetization. The magnetic current confined layer has at least one...

20060192236 - Semiconductor device: The present invention provides a semiconductor device comprising: a semiconductor substrate having a DRAM portion and a Logic portion; a first transistor in said DRAM portion; a second transistor in said Logic portion; a first insulating layer covering said DRAM portion and said Logic portion; a first contact plug formed...

20060192238 - Intermediate semiconductor device structure including multiple photoresist layers: The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the...

20060192239 - Permeable capacitor electrode: The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors without excessive etching back of the periphery of the use of sacrificial spacers. The present teachings further describe a method of forming at least one capacitor structure on...

20060192240 - Low power memory subsystem with progressive non-volatility: The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that have read/write speeds and charge retention times that are different from the other memory arrays of the system. Each of the memory cells...

20060192242 - Low power memory subsystem with progressive non-volatility: The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that have read/write speeds and charge retention times that are different from the other memory arrays of the system. Each of the memory cells...

20060192241 - Non-volatile memory and manufacturing method thereof: A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap...

20060192243 - Embedded trap direct tunnel non-volatile memory: The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant layer is formed over the...

20060192245 - Semiconductor memory device and method for manufacturing the same: When an insulating material deposited in a device isolation trench is etched, an etching process is performed to make a surface height of the insulating film lower than that of the device forming region. As a result, when a polysilicon film for a floating gate electrode is formed on a...

20060192246 - Semiconductor memory device that uses metal nitride as trap site and method of manufacturing the same: In one embodiment, a memory device includes a gate structure comprising a metal nitride material in a charge storing layer on a semiconductor substrate. The gate structure is disposed between a first dopant region and a second dopant region formed on the semiconductor substrate. The metal nitride material is structured...

20060192244 - Symmetrical and self-aligned non-volatile memory structure: A memory structure in a semiconductor substrate essentially comprises a first conductive line, two conductive blocks, two first dielectric spacers, a first dielectric layer, and a second conductive line. The first conductive line, e.g., a polysilicon line, is formed above the semiconductor substrate, and the two conductive blocks composed of...

20060192248 - Memory device and method of manufacturing including deuterated oxynitride charge trapping structure: A method for manufacturing a charge storage stack including a bottom dielectric layer, a charge trapping structure on the bottom dielectric layer, and a top dielectric layer, each comprising silicon oxynitride, are formed using reactant gases that comprise hydrogen, where the hydrogen comprises at least 90 percent deuterium isotope. The...

20060192247 - Nitride semiconductor light-emitting device and method for fabrication thereof: A nitride semiconductor light-emitting device includes a substrate and a nitride semiconductor layer including a light-emitting layer stacked on the substrate, wherein a normal line relative to a lateral face of the nitride semiconductor layer is not perpendicular to a normal line relative to a principal plane of the substrate....

20060192249 - Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same: In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body...

20060192250 - Complementary metal-oxide-semiconductor image sensor and method for fabricating the same: A complementary metal-oxide-semiconductor (CMOS) image sensor and a method for fabricating the same are provided. The CMOS image sensor includes: a pixel region provided with a plurality of unit pixels, each including a buried photodiode and a floating diffusion region; and a logic region provided with CMOS devices for processing...

20060192251 - Bipolar-based scr for electrostatic discharge protection: A system and method is disclosed for implementing a new bipolar-based silicon controlled rectifier (SCR) circuit for an electrostatic discharge (ESD) protection. The SCR circuit comprises a bipolar device to be formed on a semiconductor substrate. The bipolar device comprises at least an N-well for providing a high resistance and...

20060192252 - Semiconductor device allowing modulation of a gain coefficient and a logic circuit provided with the same: In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonuniform gate length at...

20060192253 - Semiconductor device, electrode member and electrode member fabrication method: A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an...

20060192254 - Semiconductor memory device: In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistors, first and second load...

20060192255 - Self-aligned semiconductor contact structures and methods for fabricating the same: A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window...

20060192256 - High-voltage power semiconductor device: A semiconductor device, such as a metal-oxide semiconductor field-effect transistor, includes a semiconductor substrate, a drift layer formed on the substrate, a first and a second source region, and a JFET region defined between the first and the second source regions. The JFET region may have a short width and/or...

20060192257 - Semiconductor device and fabrication method thereof: A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized during an open/short checkup of a semiconductor device. The semiconductor...

20060192258 - Semiconductor device: A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a...

20060192259 - Bonded assembly having improved adhesive bond strength: A bonded assembly is provided. The bonded assembly comprises: (a) a first substrate having a plurality of etched trenches defined in a first bonding surface; and (b) a second substrate having a second bonding surface. The second bonding surface is bonded to the first bonding surface with an adhesive and...

20060192260 - Process for packaging micro-components using a matrix: A process for packaging a number of micro-components on the same substrate wafer, in which each micro-component is enclosed in a cavity. This process includes making a covering plate comprising a re-useable matrix, a polymer layer, and a metal layer; covering the wafer with the covering plate; applying a contact...

20060192261 - Active pixel sensor: An active pixel sensor is proposed by the invention. The position of the gate of the reset transistor is kept away from the interface of the isolation region and the silicon so that the depletion region does not reach the isolation. Accordingly, dark currents caused by isolation region damages can...

20060192262 - Cmos image sensor: Unit cells 2n1 and 2n2 arranged two-dimensionally in a row direction and a column direction includes a cell with four pixels as a set arranging pixels having an oblong shape and lengthwise shape alternatively with floating junctions FJ1 and FJ2 taken as centers; a plurality of reading transistors (Tr1 to...

20060192263 - Solid-state imaging device: In each photosensitive cell, a photodiode 101, a transfer gate 102, a floating diffusion layer section 103, an amplifier transistor 104, and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is...

20060192264 - Contact assembly and socket for use with semiconductor packages: In a contact assembly, a first set of contacts (30-1 through 30-5) is arranged on a first surface and a second set of contacts (40-5 through 4-1) is arranged on a second surface with respective contacts of each set used as pairs. A plurality of first and second sets are...

20060192265 - System-on-chip with shield rings for shielding functional blocks therein from electromagnetic interference: A system-on-chip (SoC) that is immune to electromagnetic interference has block shield rings fabricated therein. The SoC includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated...

20060192266 - Semiconductor memory having charge trapping memory cells and fabrication method thereof: A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated...

20060192267 - Inductor fabricated with dry film resist and cavity and method of fabricating the inductor: An inductor fabricated with a dry film resist and a cavity and a method of fabricating the inductor. The cavity can be formed in a substrate to minimize a parasitic capacitance generated by structures of upper electrodes, an insulating layer, and a lower electrode and minimize energy loss caused by...

20060192268 - Semiconductor varactor with reduced parasitic resistance: A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layers (50) over the well...

20060192269 - Substrate assembly for stressed systems: A substrate-assembly having a mechanical stress absorption system. The assembly includes two substrates, one of which has a mechanical stress absorbing system, such as a plurality of motifs that absorb thermoelastic stresses, to prevent cracking or destruction of the substrates or separation of one substrate from the other....

20060192270 - Semiconductor integrated circuit device and process for manufacturing the same: A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region...

20060192271 - Method of manufacturing a dielectric layer and corresponding semiconductor device: A polycrystalline dielectric layer is formed wherein the dielectric layer comprises a first dielectric material containing an oxide or nitride and a second material contributing to less than 1% in weight to the dielectric layer, forming a non-conductive oxide or nitride having an enthalpy lower than the enthalpy of the...

20060192272 - Wafer level hermetically sealed mems device: A hermetically sealed microelectromechanical system (MEMS) package includes a MEMS switch having a movable portion and a stationary portion with an electrical contact thereon. A glass lid is anodically bonded to the MEMS switch to form a sealed cavity over the movable portion of the MEMS switch. The glass lid...

20060192273 - Integrated circuit package and method of manufacture thereof: An integrated circuit (IC) package 100 comprises an IC 102 and leads 104 coupled to the IC. Each lead has a first end 106 configured to be coupled to the integrated circuit and a second end 108 configured to pass through one of a plurality of mounting holes 110 extending...

20060192274 - Semiconductor package having double layer leadframe: A leadframe chip scale package includes a double leadframe assembly. The first leadframe has a central die paddle and peripheral leads, and the second leadframe, superimposed over the first leadframe in the package, has peripheral leads. The peripheral leads of both leadframes are situated in at least one row along...

20060192275 - Encapsulation method for semiconductor device having center pad: Apparatus and center pad die and substrate assemblies configured to provide for molding, in a single molding step, both an attached center pad die and other features on a die attach side of the substrate, and wire bonds an associated bond pads and other features on the opposite side of...

20060192276 - Integrated circuit and wireless ic tag: In a wireless IC tag, on which an integrated circuit and a small antenna are integrally mounted, a radiation-shielding material covers only the integrated circuit (IC chip) portion. Thus, the area of the small antenna covered by the radiation-shielding material is minute, and it is possible to minimally suppress a...

20060192277 - Chip stack employing a flex circuit: A chip stack employing BGA or FBGA integrated circuit chip packages is provided. Two chip packages have bottom surfaces attached with sets of electrical contacts, which are oriented towards each other and are electrically connected to conductive patterns formed within the same flex substrate. One set contacts a conductive pattern...

20060192278 - Interface module for connecting lsi packages, and lsi-incorporating apparatus: An interface module for connecting LSI packages includes a connecting member which is to be mounted on an LSI package including an LSI chip and which includes lines to be electrically connected to the LSI package, an optoelectronic transducer which is mounted on the connecting member, which is connected to...

20060192279 - Ultra thin dual chip image sensor package structure and method for fabrication: A stacked image sensor package contains an image sensor chip and a peripheral chip. A support pad for the peripheral chip adheres to a top surface of the peripheral chip, eliminating the need for a support member that otherwise would contribute to the thickness of the package. Thermal dissipation is...

20060192280 - Method of forming electronic devices: A method of forming polymer reinforced solder-bumped containing device or substrate is described. The method comprises the following steps: providing a device or substrate having at least one solder bump formed thereon; coating a predetermined portion of the device or substrate with a curable polymer reinforcement material forming a layer...

20060192281 - Methods for sealing chambers of microelectronic packages: Microelectronic packages having chambers and sealing materials, and methods of making the packages, and sealing the chambers, are disclosed. An exemplary package may include a first surface, a second surface, a solid sealing material including an intermetallic compound, such as, for example, of gallium or another relatively low melting material,...

20060192282 - Semiconductor device: A mounting board has a plurality of semiconductor memory devices operated in sync with a clock signal, and a semiconductor data processing device which access-controls the semiconductor memory devices. Layouts of data-system terminals of the semiconductor memory devices with respect to memory access terminals of the semiconductor data processing device...

20060192283 - Semiconductor wafer assemblies: An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming and using such a structure. In one embodiment, a wafer edge ring is formed using a stereolithography (STL) process. In another embodiment, a...

20060192285 - Method for producing a plurality of electronic devices: An electronic device has external contact elements projecting from at least one external contact side of a plastic housing. The external contact elements have an internal section and an external section. The external section has an external contact region tapering away from the external contact side. An external contact element...

20060192284 - Method of forming an encapsulation layer on a back side of a wafer: A manufacturing method of forming an encapsulation layer on a back surface of a wafer, the method comprising the steps of: providing the wafer having the back surface and an active surface opposing to the back surface; providing an encapsulation disposed only on the back surface of the wafer, and...

20060192289 - Integrated connection arrangements: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer...

20060192287 - Interconnecting substrate and semiconductor device: An interconnecting substrate is provided with a base insulating film having a sunken section in a bottom surface thereof, a first interconnection provided in the sunken section, a via hole formed in the base insulating film, and a second interconnection which is connected to the first interconnection via a conductor...

20060192286 - Semiconductor device: Disclosed herein is a semiconductor device having a multi-layer wiring structure includes a plurality of wiring layers laminated on a substrate, the wiring layers each including a buried wiring and a via formed by filling with a conductive material the inside of a wiring trench formed on the face side...

20060192288 - Semiconductor integrated device and method of providing shield interconnection therein: A method of providing shield interconnection, the method shielding an interconnection pattern to be shielded with shield interconnection patterns for shielding on the substrate of a semiconductor integrated device, is disclosed. The method includes the steps of disposing multiple interconnection layers having the corresponding shield interconnection patterns formed therein so...

20060192290 - Connection technology for power semiconductors comprising a layer of electrically insulating material that follows the surface contours: A layer of electrically insulating material is applied to a substrate and a component located thereon, in such a way that said layer follows the surface contours....

20060192291 - Electronic device: An electronic device according to an embodiment of the invention includes a pair of members which are connected to each other by a connecting portion layer interposed between connecting portions respectively formed thereon and have thermal expansion coefficients different from each other, wherein the connection layer is formed by diffusion...

20060192292 - Semiconductor chip package and method of manufacture: A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive...

20060192296 - Chip carrier and system including a chip carrier and semiconductor chips: A chip carrier includes a first surface and a second surface that opposes the first surface. The chip carrier acts as a heat sink for semiconductor chips arranged on it. A first recess is provided in the first surface, and a second recess is provided in the second surface. First...

20060192294 - Chip scale package having flip chip interconnect on die paddle: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has interconnection between the active site of the die and the die paddle. Also, methods for making the package are disclosed....

20060192293 - Electronic device, standoff member, and method of manufacturing electronic device: An electronic device comprises a semiconductor device having a package substrate with bumps. The semiconductor device is bonded to a mounting substrate by flip-chip bonding. A standoff member supports the package substrate on the mounting substrate with a predetermined standoff between the package substrate and the mounting substrate. The standoff...

20060192295 - Semiconductor package flip chip interconnect having spacer: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed....

20060192298 - Semiconductor device with surface-mountable outer contacts, and process for producing it: A semiconductor device with surface-mountable outer contacts and to a process for producing it is disclosed. In one embodiment, surface-mountable outer contacts are arranged on outer contact connection surfaces on the underside of the semiconductor device. In their respective center region, the outer contact connection surfaces have at least one...

20060192297 - System and method for reducing voltage drops in integrated circuits: In one embodiment, a die arrangement is disclosed in which a wire-bond pad may be operatively coupled to a power supply via a wire bond. A first pad may be operatively coupled to the wire-bond pad. A second pad may be operatively coupled to the first pad via a redistribution...

20060192299 - Manufacturing method for electronic device: A manufacturing method for electronic device, includes: forming a first interconnection on a substrate; disposing a pedestal having a predetermined shape on the substrate; and forming a second interconnection connecting to the first interconnection, extending onto the pedestal....

20060192300 - Integrated circuit with staggered differential wire bond pairs: An integrated circuit comprises an integrated circuit package and one or more circuit elements disposed within the integrated circuit package. The integrated circuit also comprises at least two differential wire bond pairs providing connections for at least one of the one or more circuit elements. Proximate differential wire bond pairs...

20060192301 - Semiconductor device with a protected active die region and method therefor: A semiconductor device includes a semiconductor die having a plurality of contact pad sites, a plurality of contact pads, an encapsulant barrier, and an encapsulant. A plurality of contact pads is in electrical contact with a predetermined corresponding different one of the contact pad sites. An encapsulant barrier is positioned...

20060192302 - Self-compensating mark design for stepper alignment: A system and method for fabricating integrated circuits using four fine alignment targets per stepper shot. The four alignment targets are disposed within the scribe line on each side of a four-sided stepper shot. The targets on opposites sides of the region are located in mirror-image positions. For example, in...

20060192303 - Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus: To easily determine an orientation of a semiconductor device, a semiconductor device includes a substrate including electrode electrically connected to an integrated circuit, an external terminal electrically connected to the electrode, and a light transmissive insulation layer provided on the external terminal side of the substrate, and a mark provided...

20060192304 - Magnetic annealing sequences for patterned mram synthetic antiferromagnetic pinned layers: A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an antiferromagnetic pinning layer over a substrate and a ferromagnetic pinned layer over the pinning layer, the pinned layer having a first thickness. The fixed layer...

20060186394 - Snse-based limited reprogrammable cell: Methods and apparatus for providing a memory device that can be programmed a limited number of times. According to exemplary embodiments, a memory device and its method of formation provide a first electrode, a second electrode and a layer of a chalcogenide or germanium comprising material between the first electrode...

20060186396 - Optical element and method for manufacturing the same: An optical element has: an emission section including a first semiconductor layer of a first conductivity type, an active layer formed above the first semiconductor layer and a second semiconductor layer of a second conductivity type formed above the active layer; an interlayer dielectric layer; and an electrostatic breakdown prevention...

20060186395 - Thin-film capacitative element and electronic circuit and electronic equipment including the same: A thin film capacitive element according to the present invention includes between a first electrode layer and a second electrode layer a dielectric layer formed of a dielectric material containing a bismuth layer structured compound having a composition represented by the stoichiometric compositional formula: (Bi2O2)2+(Am−1BmO3m+1)2− but containing bismuth (Bi) in...

20060186397 - Semiconductor substrates having useful and transfer layers: A semiconductor substrate that includes a relatively thin monocrystalline useful layer, an intermediate layer transferred from a source substrate, and a relatively thick layer of a support present on one of the useful layer of the intermediate layer. The support is made of a deposited material that has a lower...

20060186401 - Carbonyl-functionalized thiophene compounds and related device structures: Carbonyl-functionalized oligo/polythiophene compounds, and related semiconductor components and related device structures....

20060186400 - Organic photodiode and method for manufacturing the organic photodiode: In an organic photodiode, in a gap between a transparent anode formed on a glass substrate, and a reflection cathode formed oppositely thereto, a plurality of light receiving parts as layers of light absorbing composition, and partition walls for insulating between transparent anode and reflection cathode and insulating between adjacent...

20060186398 - Organic semiconductor device with multiple protective layers and the method of making the same: An organic semiconductor device with multiple protective layers and the method of making the same are described. A first protective layer is formed by vapor phase deposition on an organic thin-film transistor. A second protective layer is then formed on the first protective layer. Therefore, the organic thin-film transistor is...

20060186402 - Providing driving current arrangement for oled device: A method of making a current type active matrix OLED device, includes providing a semiconductor layer, a conductive layer, and an insulator layer therebetween over a substrate, providing an organic light emitting diode over either the semiconductor layer or over the conductive layer for each pixel, and forming a first...

20060186399 - Semiconductor apparatus and fabrication method of the same: It is an object of the present invention to provide a semiconductor device capable of preventing deterioration due to penetration of moisture or oxygen, for example, a light-emitting apparatus having an organic light-emitting device that is formed over a plastic substrate, and a liquid crystal display apparatus using a plastic...

20060186404 - Dummy wafer: A dummy wafer including a carbon fiber reinforced plastic (CFRP). Specifically the dummy wafer has a wafer substrate including CFRP, the substrate has two skin layers disposed on respective principal surface side and a core layer interposed between the skin layers, and each of the skin layers has multiple one-dimensionally...

20060186406 - Method and system for qualifying a semiconductor etch process: A method of manufacturing a semiconductor device by qualifying an etch process. A semiconductor substrate is subjected to a predefined etch process to produce a partially-etched film. A scatterometry signature of the partially-etched film is produced. The scatterometry signature is used to determine if a physical property of the partially-etched...

20060186403 - Semiconductor device: The present invention is such that a semiconductor device has, on a substrate (10), a first functional area (1) (for example, a storage element area) and a second functional area (2) (for example, a driving circuitor signal processing circuit), wherein, if the substrate (10) is viewed in a planar fashion,...

20060186405 - Semiconductor device and manufacturing process therefor: A semiconductor device 100 has a probing mark 111 forming region; a bonding pad 110 having a bonding region 113; and a check mark 120 separate from the bonding pad 110. In the configuration, the probing mark 111 forming region and the bonding region 113 can be identified on the...

20060186407 - Device for measuring the reflection factor: A device for measuring the reflection factor by irradiating a measurement area of a microchip with light, and in which a light receiving part is made to receive light reflected from the measurement area for determination of the reflection factor of the measurement area. The light receiving part is located...

20060186409 - Liquid crystal display device and method for manufacturing the same: The invention provides a novel technology where a TFT array substrate for a display device is formed with three photomasks. The invention is achieved by using the novel technology in combination with a well-known four-masks process. For the novel technology, during the lithography process where a photosensitive acrylic resin film...

20060186408 - Solid-state imaging device: A solid-state imaging device is provided and has a plurality of pixel parts including three photoelectric conversion layers stacked above a semiconductor substrate, the plurality of pixel parts being arranged above the semiconductor substrate. The three photoelectric conversion layers, respectively, included in one pixel part are interposed between pixel electrode...

20060186410 - Thin film transistor and flat panel display device including the same: A thin film transistor including a stop layer is disclosed. In one embodiment, the thin film transistor includes a substrate, a gate electrode formed on the substrate, a source electrode and a drain electrode insulated from the gate electrode, a semiconductor layer insulated from the gate electrode and having: a...

20060186411 - Thin film transistor array substrate, manufacturing method thereof, and mask: A thin film transistor array substrate including a gate pattern having a gate electrode, a gate line connected to the gate electrode, and a gate pad connected to the gate line, a source/drain pattern having a source electrode, a drain electrode, a data line connected to the source electrode, and...

20060186412 - Crystallization method, crystallization apparatus, processed substrate, thin film transistor and display apparatus: There are provided a crystallization method which can design laser beam having a light intensity and a distribution optimized on an incident surface of a substrate, form a desired crystallized structure while suppressing generation of any other undesirable structure area and satisfy a demand for low-temperature processing, a crystallization apparatus,...

20060186414 - Array substrate, display apparatus having an array substrate, and method for manufacturing an array substrate: A substrate includes an array area and a data pad area adjacent to the array area. A gate line, a data line and a switching device are formed in the array area of the substrate. A data pad extending from an end of the data line and a supporter provided...

20060186413 - Display device and manufacturing method of the same: It is an object of the present invention to provide a method for manufacturing a display device in which unevenness generated under a light-emitting element does not impart an adverse effect on the light-emitting element. It is another object of the invention to provide a method for manufacturing a display...

20060186415 - Thin film semiconductor device, method of manufacturing the same, and display: Irradiation with laser light is conducted, whereby an external region of a semiconductor thin film located on the outer side relative to a pattern of a light absorbing layer is thermally melted, and the light absorbing layer is heated, without melting an internal region of the semiconductor thin film located...

20060186416 - Multiple layer and crystal plane orientation semiconductor substrate: A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer,...

20060186418 - External extraction light emitting diode based upon crystallographic faceted surfaces: A light emitting diode is disclosed that includes a support structure and a Group III nitride light emitting active structure mesa on the support structure. The mesa has its sidewalls along an indexed crystal plane of the Group III nitride. A method of forming the diode is also disclosed that...

20060186417 - Light emitting diode and method making the same: A light emitting diode and the method of the same are provided. The light emitting diode includes a light emitting structure and a metal reflective layer. The light emitting structure includes two semiconductor layers and an active layer. Oxide elements are added into the metal reflective layer to improve the...

20060186419 - Light-emitting device: A light-emitting device includes a first electrode, a second electrode, a porous layer and an electrolyte. The first electrode comprises a first surface. The second electrode comprises a second surface. The porous layer is formed of n-type semiconductor and provided on the first surface of the first electrode or the...

20060186420 - Semiconductor device such as semiconductor laser device and manufacturing method therefor, and optical transmission module and optical disk unit employing the semiconductor laser device: After a p-type cladding layer, an etching rate reducing layer and a p-type contact layer are formed in order on an n-type substrate, an etching mask is formed. Then, by using the etching mask, the p-type contact layer, the etching rate reducing layer and the p-type cladding layer are partially...

20060186421 - Schottky diode with low leakage current and fabrication method thereof: A low leakage Schottky diode and fabrication method thereof. The Schottky diode includes a n-type semiconductor; an anode having a circular periphery formed in a region above the n-type semiconductor; and a cathode formed in a region above the n-type semiconductor and having a pattern surrounding and set apart from...

20060186422 - Etching a nitride-based heterostructure: An improved solution for producing nitride-based heterostructure(s), heterostructure device(s), integrated circuit(s) and/or Micro-Electro-Mechanical System(s) is provided. A nitride-based etch stop layer that includes Indium (In) is included in a heterostructure. An adjacent layer of the heterostructure is selectively etched to expose at least a portion of the etch stop layer....

20060186425 - Led lamp: An LED lamp 100 according to the present invention includes: a substrate 20 with an upper surface; a plurality of LED chips 10, which are arranged on the upper surface of the substrate 20; and a reflector 30, which has reflective surfaces that reflect emissions of the respective LED chips...

20060186423 - Method of making optical light engines with elevated leds and resulting product: An optical light engine is fabricated by providing a thermally conductive base having one or more mounting pedestals for elevating one or more LED die above the base's surface. The LED die are mounted on the pedestals, electrically connected, and a mold having a molding surface for molding a dome...

20060186426 - Optical device, surface emitting type device and method for manufacturing the same: The present invention provides an optical device and a surface emitting type device which have high efficiency and a stable operation and are manufactured at high manufacturing yield. The optical device and the surface emitting type device are characterized in that they have a distributed Bragg reflector (DBR) including a...

20060186424 - White led and manufacturing method therefor: A white LED includes an LED chip formed on one main surface of a sapphire substrate, the LED chip being formed in a semiconductor stack structure including a light emitting layer and emitting light of a predetermined wavelength, a light extracting film applied on the other main surface of the...

20060186427 - Side-view type light emitting device: A side-view type light emitting device capable of effectively releasing heat generated on the surface of the substrate is provided. The side-view type light emitting device 1 comprising a substrate 1-1, a positive surface electrode 1-2, a negative surface electrode 1-3, a light emitting element 1-4, a sealing member 1-5...

20060186431 - Light emitting device provided with lens for controlling light distribution characteristic: The light emitting device comprises a substrate (2), a positive electrode (6) and a negative electrode (4) formed on the substrate (2), a light emitting diode (8) connected to the positive electrode (6) and the negative electrode (4), the transparent resin (12 and 14) that covers the light emitting diode...

20060186428 - Light emitting device with enhanced encapsulant adhesion using siloxane material and method for fabricating the device: A light emitting device and method for fabricating the device utilizes an adhesive layer of siloxane material to enhance the adhesion of an encapsulant to a light source, one or more leadframes and/or a reflector cup surface. The siloxane layer can be used in different types of light emitting devices,...

20060186430 - Light emitting diode package and fabrication method thereof: The present invention provides an LED package and the fabrication method thereof. The present invention provides an LED package including a submount silicon substrate and insulating film and electrode patterns formed on the submount silicon substrate. The LED package also includes a spacer having a through hole, formed on the...

20060186429 - Semiconductor light emitting device and method of manufacture: A light-emitting diode (“LED”) device has an LED chip attached to a substrate. The terminals of the LED chip are electrically coupled to leads of the LED device. Elastomeric encapsulant within a receptacle of the LED device surrounds the LED chip. A second encapsulant is disposed within an aperture of...

20060186432 - Polarized radiation source using spin extraction/injection: Spin-polarized electrons can be efficiently extracted from an n-doped semiconductor layer (n-S) by forming a modified Schottky contact with a ferromagnetic material (FM) and a δ-doped layer at an interface under forward bias voltage conditions. Due to spin-selection property of the FM-S junction, spin-polarized carriers appear in the n-doped semiconductor...

20060186433 - Surface-spintronics device: A surface-spintronic device operating on a novel principles of operations may be implemented as a spin conducting, a spin switching or a spin memory device. It includes a magnetic atom thin film (13) layered on a surface of a solid crystal (12) and a drain and a source electrodes (14)...

20060186434 - Vertical-conduction and planar-structure mos device with a double thickness of gate oxide and method for realizing power vertical mos transistors with improved static and dynamic performance and high scaling down density: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the...

20060186435 - Semiconductor device and method of producing the same, and power conversion apparatus incorporating this semiconductor device: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement...

20060186436 - Semiconductor device: A semiconductor device includes a gate electrode formed on a silicon substrate in correspondence to a channel region via a gate insulation film, and source and drain regions of p-type formed in the silicon substrate at respective outer sides of sidewall insulation films on the gate electrode, a pair of...

20060186437 - Bipolar transistor: A bipolar transistor, wherein a outgoing electrode is made of a polycrystalline Si film, and C atom, or Ge atom together with C atom are added in the polycrystalline Si film....

20060186438 - Device for thermal sensing: The present invention provides a device for thermal sensing which uses a replaceable or disposable substrate comprising channels for receiving a sample to be measured. The device according to the invention is cost-effective as the replaceable or disposable substrate can be reused....

20060186439 - Semiconductor device, a manufacturing method thereof, and a camera: A semiconductor device includes a transfer channel for transferring charge generated by photoelectric conversion, an insulating film formed on the transfer channel, and a transfer electrode for applying a transfer voltage to the transfer channel via the insulating film. The insulating film has a first thickness and a second thickness...

20060186440 - Phase change memory device and method of manufacture thereof: A method of manufacturing a memory device is provided. The method includes forming an electrode over a substrate. The method also includes forming an opening in the electrode to provide a tapered electrode contact surface proximate the opening. The method further includes forming a phase change feature over the electrode...

20060186441 - Light-emitting device, liquid-crystal display device and method for manufacturing same: The present invention provides a structure of a semiconductor device that realizes low power consumption even where increased in screen size, and a method for manufacturing the same. The invention forms an insulating layer, forms a buried interconnection (of Cu, Au, Ag, Ni, Cr, Pd, Rh, Sn, Pb or an...

20060186442 - Image sensor and method for fabricating the same: An image sensor and a method for fabricating the image sensor are provided. The image sensor includes a doped layer of a first conductivity type formed in a photodiode region defined in a semiconductor substrate, a first epitaxial layer of a second conductivity type and a second epitaxial layer of...

20060186445 - Bias-adjusted giant magnetoresistive (gmr) devices for magnetic random access memory (mram) applications: A bias-adjusted giant magnetoresistive (GMR) device includes a ferromagnetic reference layer, which has a magnetization that remains relatively fixed when a range of magnetic fields is applied, and a ferromagnetic switching layer, which has a magnetization that can be changed by applying a relatively small magnetic field. In MRAM applications,...

20060186443 - Magnetic memory: A TMR element has a free first magnetic layer, a second magnetic layer with a magnetization direction B fixed, a nonmagnetic insulating layer provided between the first magnetic layer and the second magnetic layer, a third magnetic layer provided above a surface of the first magnetic layer and having a...

20060186444 - Spin polarization amplifying transistor: An embodiment of the invention is a transistor formed in part by a ferromagnetic semiconductor with a sufficiently high ferromagnetic transition temperature to coherently amplify spin polarization of a current. For example, an injected non-polarized control current creates ferromagnetic conditions within the transistor base, enabling a small spin-polarized signal current...

20060186446 - 3-dimensional flash memory device and method of fabricating the same: In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on...

20060186448 - Semiconductor device memory cell: A circuit provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process. A hard mask is formed on the bit line upper surface and a side wall formed on the side surface of the bit line by...

20060186447 - Semiconductor memory and method for fabricating the same: A semiconductor memory includes: a semiconductor substrate having a protrusion; a gate insulating film formed on an upper surface of the protrusion; a gate electrode formed on the gate insulating film; diffusion regions formed in portions of the substrate on both sides of the protrusion, the diffusion regions being disposed...

20060186449 - Semiconductor device and manufacturing method therof: A semiconductor device and a manufacturing method thereof which enable to secure high yield and increase the capacity of a capacitor are provided. The semiconductor device according to the present invention includes: a plurality of capacitor layers laminated, each capacitor layer including a plurality of storage electrodes, a capacity insulating...

20060186450 - Integrated high voltage capacitor and a method of manufacture therefor: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over...

20060186451 - Memory device for storing electric charge, and method for fabricating it: The present device relates to memory devices for storing electric charge having memory cells and transistors arranged spatially next to them, and relates in particular to memory devices having memory cells with a high capacitance. In the memory cells which form a memory device to which the invention relates, there...

20060186452 - Capacitor of semiconductor device and method of fabricating the same: Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper...

20060186453 - Semiconductor device having a capacitor and a fabrication method thereof: In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate and an insulating layer on the semiconductor substrate, a contact plug electrically connected to the semiconductor substrate and formed in the contact hole, a buffer conductive layer pattern electrically...

20060186454 - Semiconductor device and fabricating method thereof: A method of fabricating a semiconductor device is described. A substrate having a memory cell region and a high voltage circuit region are provided. First and second source/drain regions are formed in the substrate within these two regions. A silicon oxide layer, a first conductive layer and a top layer...

20060186458 - Germanium-silicon-carbide floating gates in memories: The use of a germanium carbide (GeC), or a germanium silicon carbide (GeSiC) layer as a floating gate material to replace heavily doped polysilicon (poly) in fabricating floating gates in EEPROM and flash memory results in increased tunneling currents and faster erase operations. Forming the floating gate includes depositing germanium-silicon-carbide...

20060186457 - Methods for programming a floating body nonvolatile memory: A technique to speed up the programming of a non-volatile memory device that has a floating body actively removes holes from the floating body that have accumulated after performing hot carrier injection (HCI). The steps of HCI and active hole removal can be alternated until the programming is complete. The...

20060186455 - Nand-type non-volatile memory: A non-volatile memory includes a substrate, a plurality of data storage elements positioned on the substrate, a plurality of control gates positioned above the data storage elements, an insulating layer positioned on surfaces and sidewalls of the control gates, and a bit-line positioned on the insulating layer to cross the...

20060186459 - Non-volatile memory and manufacturing method thereof: A non-volatile memory is provided. An assist gate structure is formed on a substrate such that the width at the bottom of the assist gate structure is greater than the width at the top of the assist gate structure. A floating gate is formed on one side of the assist...

20060186462 - Nonvolatile memory device and method of fabricating the same: Provided are example embodiments of fabrication methods and resulting structures suitable for use in nonvolatile memory devices formed on semiconductor substrates. The example embodiments of the gate structures include a first insulating film formed on the semiconductor substrate, a storage node formed on the first insulating film for storing charges,...

20060186456 - Nvm cell on soi and method of manufacture: A non-volatile memory (NVM) device formed in a semiconductor-on-insulator (SOI) substrate has a trap region on the source side only to speed up the process of programming. During programming of an NVM device in partially depleted SOI, holes are generated that slow down the formation of electrons hot enough to...

20060186461 - Semiconductor device and method of manufacturing the same: According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffusion layer formed in the semiconductor substrate, a predetermined portion of the gate...

20060186460 - Split gate flash memory device having self-aligned control gate and method of manufacturing the same: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain...

20060186464 - Nonvolatile semiconductor memory device having adjacent selection transistors connected together: A semiconductor memory device comprising a semi-conductor substrate, a plurality of cell transistors provided on the substrate, a plurality of selection gates provided on the substrate, and element-isolation regions provided between the cell transistors and between the selection gates. Each cell transistor has a floating gate provided on a gate...

20060186463 - Nonvolatile semiconductor memory devices and the fabrication process of them: The present invention enables to avoid a reduction in coupling ratio in a nonvolatile semiconductor memory device. The reduction is coupling ratio is caused due to difficulties in batch forming of a control gate material, an interpoly dielectric film material, and a floating gate material, the difficulties accompanying a reduction...

20060186465 - Dmos device having a trenched bus structure: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide...

20060186466 - Vertical gate semiconductor device and method for fabricating the same: A first region 11 functioning as a transistor includes a drain region 111, a body region 112 formed over the drain region 111, a source region 113A formed over the body region 112 and a trench formed through the body region 112 and having a gate electrode 120 buried therein....

20060186467 - System and method for making a ldmos device with electrostatic discharge protection: A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity...

20060186468 - Semiconductor device and a method for manufacturing the same: Provided is a manufacturing method of a semiconductor device which has the following steps of forming a plurality of layered patterns obtained by stacking an insulating film, a conductor film for forming a floating gate electrode and another insulating film over a semiconductor substrate in the order of mention, forming...

20060186469 - Semiconductor device: A semiconductor device has a source region, a channel region and a drain region formed in order along a surface of a substrate, a vertical type bipolar transistor formed from the source region below the substrate, a base contact region of the vertical type bipolar transistor, a buried layer connected...

20060186471 - Manufacturing method for semiconductor device: A semiconductor device with simple device structure enables reduction in the number of manufacturing steps and the manufacturing cost. A gate insulation film and a gate electrode are formed in a certain area on a semiconductor substrate. A semiconductor substrate non-removed section is formed under the gate insulation film, and...

20060186470 - Strained transistor with hybrid-strain inducing layer: A semiconductor device having a hybrid-strained layer and a method of forming the same are discussed. The semiconductor device comprises: a gate dielectric over a substrate; a gate electrode over the gate dielectric; an optional pair of spacers along the sidewalls of the gate dielectric and the gate electrode; a...

20060186473 - Method of forming an implantable electronic device chip level hermetic and biocompatible electronics package using soi wafers: The invention is directed to a hermetically packaged and implantable integrated circuit for electronics that is made my producing streets in silicon-on-insulator chips that are subsequently coated with a selected electrically insulating thin film prior to completing the dicing process to yield an individual chip. A thin-layered circuit may transmit...

20060186476 - Method of manufacturing thin film transistor: On a glass substrate an insulating protective layer comprising SiO2 film is formed, and an active layer comprising a p-Si film is formed thereon. Further, a first gat insulating film comprising an SiN film which serves as a lower layer and a second gate insulating film comprising an SiN film...

20060186472 - Semiconductor apparatus and complimentary mis logic circuit: A configuration is adopted comprising an NchMOS transistor 1 equipped with an insulating isolation layer 4 providing insulation and isolation using an SOI structure, and a capacitor formed using an insulating film, with a silicon substrate B being made thin and substrate capacitance being reduced. The NchMOS transistor 1 is...

20060186474 - Semiconductor device and method of manufacturing the same: It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain...

20060186475 - Thin film transistor having high mobility and high on-current and method for manufacturing the same: An image input apparatus includes an insulating substrate; polycrystalline silicon islands formed on said insulating substrate; pixels each including thin film transistors and a photodiode formed above said thin film transistors, each of the thin film transistors have a source region, a channel region and a drain region foamed in...

20060186477 - Semiconductor device: In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type...

20060186478 - Method for optimising transistor performance in integrated circuits: A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent...

20060186479 - Semiconductor memory device having local etch stopper and method of manufacturing the same: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate...

20060186480 - Charge-trapping memory device and method for production: A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the...

20060186481 - Non-volatile memory and manufacturing method and operating method thereof: A non-volatile memory having many memory cell columns is provided. Each memory cell column includes a plurality of memory cells formed on a substrate. A deep p-type well is disposed in the substrate and an n-type well is disposed on the deep p-type well. A shallow p-type well isolated by...

20060186483 - Phase change memory devices employing cell diodes and methods of fabricating the same: Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the...

20060186482 - Shared contacts for mosfet devices: In one aspect, the present invention provides electronic devices that comprise a doped semiconductor shared contact between (a) a gate conductor region of at least one transistor and (b) a source/drain diffusion region of at least one transistor. One specific example of such as shared contact, among many others, is...

20060186484 - Field effect transistor with narrow bandgap source and drain regions and method of fabrication: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a...

20060186485 - Nand-type flash memory devices and fabrication methods thereof: In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interconnection contact plugs are formed of the same conductive layer through the...

20060186487 - Pmos transistor with increased effective channel length in the peripheral region and method of manufacturing the same: In manufacturing a PMOS transistor, a semiconductor substrate having an active region and a field region is formed with a hard mask layer, which covers a center portion of the active region on the substrate in a lengthwise direction of a channel. The hard mask layer exposes the center portion...

20060186486 - Semiconductor device and method for manufacturing the same: A semiconductor device includes (i) a semiconductor layer, (ii) a first insulating film formed in the semiconductor layer, (iii) a conductive film continuously formed on the semiconductor layer and the first insulation film in a line shape, (iv) a second insulating film formed between the conductive film and the semiconductor...

20060186488 - Semiconductor device and method of manufacturing semiconductor device: Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an electrode formed above the insulating film....

20060186489 - Semiconductor device and method of manufacturing semiconductor device: Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an electrode formed above the insulating film....

20060186490 - Metal carbide gate structure and method of fabrication: A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal...

20060186491 - Methods of forming semiconductor devices having metal gate electrodes and related devices: Methods of forming semiconductor devices and the devices so formed include forming an oxidation barrier pattern to cover sidewalls of a metal-containing pattern. The metal-containing pattern is located on a gate polysilicon layer and includes a metal silicide pattern, a metal barrier pattern and a gate metal pattern which are...

20060186493 - Laminated structure, method of manufacturing the same and ultrasonic transducer array: A laminated structure with less breakage of an insulative layer due to stress and easy interconnection. The laminated structure includes at least a first electrode layer, a dielectric layer and a second electrode layer stacked in this order. The first electrode layer includes a first electrode material disposed such that...

20060186492 - Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers: Microelectronic imagers with shaped image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device comprises an imaging die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry...

20060186494 - Semiconductor relay: A semiconductor relay includes an essentially parallelepiped-shaped housing that has a fastening side and four lateral surfaces, which are perpendicular thereto, and has a front side, which is opposite the fastening side. These lateral surfaces and front side serve as connecting sides. At least one electrical connecting element and at...

20060186495 - Low power magnetoelectronic device structures utilizing enhanced permeability materials: A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating a magnetoelectronic device (102) and depositing a conducting line (104). A layer of enhanced permeability dielectric material (106) having a permeability no less than approximately 1.5 is formed, wherein after the step of fabricating a...

20060186496 - System and method for processing a wafer including stop-on-alumina processing: Magnetic tunnel junction (MTJ) devices can be fabricated by a stop-on-alumina process whereby the tunnel junction layer serves as the stop layer during plasma overetching of the upper magnetic layer. The resulting side walls of the MTJ device are non-vertical in the vicinity of the tunnel junction layer which serves...

20060186497 - Photoelectric conversion device and manufacturing method of the same, and a semiconductor device: It is an object of the present invention to provide a photo-sensor having a structure which can suppress electrostatic discharge damage. Conventionally, a transparent electrode has been formed over the entire surface of a light receiving region; however, in the present invention, the transparent electrode is not formed, and a...

20060186498 - Microminiature moving device and method of making the same: In a microminiature moving device that has disposed, on a single-crystal silicon substrate, movable elements (a movable rod 46, a movable comb electrode 49, etc.) displaceable in parallel to the substrate surface and stationary parts (a stationary part 40a, etc.), the stationary parts are fixedly secured to the single-crystal silicon...

20060186499 - Solid-state imaging device and method of manufacturing said solid-state imaging device: It is an object to provide solid-state imaging device, which can easily be manufactured and has a high reliability, and a method of manufacturing the solid-state imaging device. In the present invention, a manufacturing method comprises the steps of forming a plurality of IT-CCDs on a surface of a semiconductor...

20060186500 - Laser diode packaging: A laser diode package includes a heat sink, a laser diode, and an electrically nonconductive (i.e. insulative) substrate. The laser diode has an emitting surface and a reflective surface opposing the emitting surface. The laser diode further has first and second side surfaces between the emitting and reflective surfaces. The...

20060186501 - Semiconductor photodetector device and manufacturing method therefor: A laminated structure including an InGaAs light absorption layer and an InP window layer on a n-type InP substrate. A p-type diffusion layer region is formed in an InP window layer. A depletion layer between the n-type InP substrate and the p-type diffusion layer region is formed when a voltage...

20060186503 - Edge viewing photodetector: An edge viewing semiconductor photodetector may be provided. Light may be transmitted through an optical fiber conduit comprising a core region surrounded by a cladding region. The light may be received at the edge viewing semiconductor photodetector having an active area. The active area may be substantially contained within a...

20060186502 - Solar cell using carbon nanotubes and process for producing the same: A solar cell includes a p-type semiconductor substance, and an n-type semiconductor substance. The p-type semiconductor substance and the n-type semiconductor substance form a pn junction or a pin junction, and the p-type semiconductor substance or the n-type semiconductor substance includes a structure film having a plurality of carbon nanotubes...

20060186504 - Cmos image sensor for reducing partition noise: A CMOS image sensor according to an embodiment of the present invention includes a unit pixel, including a transfer transistor controlled by a transfer control signal; and a transfer control signal controller for controlling a rising and a falling times of the transfer control signal, wherein the falling time of...

20060186505 - Image sensor cells: A structure (and method for forming the same) for an image sensor cell. The structure includes (a) a semiconductor substrate; (b) a charge collection well on the substrate, the charge collection well comprising a semiconductor material doped with a first doping polarity; (c) a surface pinning layer on and in...

20060186506 - Schottky barrier diode and manufacturing method thereof: To reduce a reverse leakage current in a Schottky barrier diode with achieving a lower forward voltage Vf and a smaller capacitance than in the related art, a Schottky barrier diode includes a semiconductor layer of a first conductivity type, a first electrode which is a metal layer forming a...

20060186507 - Semiconductor device: In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across an upper surface of the N-type buried diffusion layer over a wide range to form a PN junction region for...

20060186508 - Reverse blocking semiconductor device and a method for manufacturing the same: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state...

20060186509 - Shallow trench isolation structure with active edge isolation: A method of fabricating a shallow trench isolation (STI) structure with active edge isolation and increased radiation hardening is presented. The invention comprises forming a pad oxide layer on a substrate. Then a masking layer is formed on the pad oxide and is patterned to define the STI structure trench...

20060186510 - Strained-semiconductor-on-insulator bipolar device structures: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication....

20060186511 - Monolithically integrated capacitor and method for manufacturing thereof: A monolithically integrated capacitor having a variable capacitance, comprising a first semiconductor region structure doped to a first doping type, a second semiconductor region structure doped to a second doping type opposite the first doping type, a first electrode of the capacitor connected to the semiconductor region structure, and a...

20060186512 - Flexible device and method of manufacturing the same: The rollable device of the invention comprises a substrate of an insulating material (12) with apertures (15) extending from a first to a second side. On the first side switching elements (13) are present, as well as interconnect lines and the like, covered by a coating of organic material (3)....

20060186513 - High frequency unit: A high frequency unit (e.g., an RF signal selection switch) includes, as its external terminals, a terrestrial input terminal, a CATV input terminal, an RF output terminal, a selection signal terminal, a power supply terminal and a ground potential terminal. The external terminals are attached to a shielding case surrounding...

20060186515 - Dual row leadframe and fabrication method: A semiconductor package is provided. A leadframe including a die attach paddle, a number of inner leads, and a number of outer leads, and a number of extended lead tips on the number of outer leads. The inner edges of the number of extended lead tips are in substantial alignment...

20060186514 - Package stacking lead frame system: The present invention provides a package stacking lead frame system comprising forming a lead frame interposer including a dual row of terminal leads positioned around a die attach pad, mounting a first die on the die attach pad, wherein the first die is connected to the dual row of terminal...

20060186516 - Semiconductor device with semiconductor chip mounted in package: A semiconductor device including a semiconductor chip having first and second principal surfaces is disclosed. The semiconductor chip includes a first electrode formed on the first principal surface and a second electrode formed on the second principal surface. A first lead frame includes a first connecting portion connected to the...

20060186517 - Semiconductor package having improved adhesiveness and ground bonding: A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the package body. A plurality of tabs are formed...

20060186518 - Module card structure: A module card structure includes a structure, a first chip, a second chip, an adhered layer, and a compound layer. The substrate has an upper surface on which a plurality of golden finger are formed, and a lower surface. The first chip is mounted on the upper surface of the...

20060186520 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a solder dam for restricting the flow of solder during manufacturing. The device includes a semiconductor chip bonded to a first side of a circuit board, a metal base for dissipating heat produced by the semiconductor chip, the metal base being bonded to a second side...

20060186519 - Semiconductor device and unit equipped with the same: A semiconductor device comprises columnar electrodes including columnar portions and ball-shaped low-melting point layers joined to the top surfaces of columnar portions. The amount of plating of the low-melting point layer and the cross-sectional area of the columnar portion are adjusted in such a way that the relationship represented by...

20060186521 - Semiconductor packages and methods for making and using same: A semiconductor package is provided which includes a substrate having a plurality of semiconductor dice mounted thereon. The substrate is divided into segments by grooves formed in the bottom surface of the substrate. Each semiconductor die is electrically connected to the substrate by electrical connections which extend from bond pads...

20060186522 - Molded part and electronic device using the same: An integrally multiple-molded part for electronic devices is provided capable of absorbing and relieving the internal stresses of a multiple-molded part, preventing the occurrence of clearances between the bonding side face of each electrical connection terminal and a resin, obtaining stable frictional force at the contact region between the bonding...

20060186523 - Chip-type micro-connector and method of packaging the same: The chip-type micro-connector includes a package substrate, a micro-connector disposed on the package structure, a plurality of chips, and a cap layer disposed on the micro-connector and the chips. The micro-connector includes a connection substrate, a plurality of connecting wires disposed in the connection substrate, and a plurality of contact...

20060186525 - Electronic component with stacked semiconductor chips and method for producing the same: A semiconductor component includes a first module component and a second module component stacked one on top of the other, and a spacer arranged between the two module components. The module components are electrically connected to one another and/or to a higher-level circuit carrier by connecting elements. At at least...

20060186524 - Semiconductor device: A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided...

20060186526 - Semiconductor device and its wiring method: A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire connecting between the...

20060186527 - Array substrate for liquid crystal display device and method for manufacturing the same: An array substrate for a liquid crystal display device includes a flexible substrate, a buffer layer on the flexible substrate, a thin film transistor including a gate electrode, a source electrode and a drain electrode on the buffer layer, and a pixel electrode on the thin film transistor....

20060186529 - Lead frame, sensor including lead frame and method of forming sensor including lead frame: A lead frame includes a frame body defining an internal region, a plurality of leads extending from the frame body, and first and second stages that are disposed in the internal region. The first and second stages are sloped and are parallel to a first line along which a primary...

20060186528 - Semiconductor device: The present invention can supply power for each circuit section by separating and connecting bus-bar (21d) for each circuit section inside the semiconductor chip (22), and, in addition, can increase the number of pads (22a) for power supply or can use the lead (21a) conventionally used for power supply for...

20060186530 - Memory device power distribution in memory assemblies: A memory assembly has a memory package with a plurality of interconnect pins having a plurality of first power input pins located on a first side of the memory package, the first power input pins independent of each other. A lead-over-chip leadframe has a plurality of leads coupled to the...

20060186532 - High frequency arrangement: A high frequency arrangement is provided that includes an integrated high frequency circuit, a first bond pad, which is electrically connected by a first electrical supply line, in particular a bond wire and/or a solder bump, to a housing terminal and/or another circuit, wherein the first bond pad adjoins a...

20060186531 - Package structure with chip embedded in substrate: A package structure with chip embedded in substrate includes: a carrier having a stepped cavity; a semiconductor chip (or a chip set) received in the cavity of the carrier; a dielectric layer formed on the semiconductor chip and the carrier and filled in a gap between the semiconductor chip and...

20060186533 - Chip scale package with heat spreader: A dense semiconductor flip-chip device assembly is provided with a heat sink/spreading/dissipating member that is formed as a paddle of a metallic paddle frame in a strip of paddle frames. Semiconductor dice are bonded to the paddles by, e.g., conventional die attach methods, enabling bump attachment and testing to be...

20060186534 - Lid made of resin for case for accommodating solid-state imaging device and solid-state imaging apparatus: This method of manufacturing a lid made of a transparent resin comprises a step of introducing a resin into a cavity for molding a protrusion continuous with a cavity for molding a lid in a die; a step of forming a molded body including a lid and a protrusion continuous...

20060186535 - Semi-conductor die mount assembly: A die mount assembly including a semiconductor die and die mount is provided. The semiconductor die may be a light emitting diode die that is attached to the die mount forming an electrical and thermal connection. The die mount includes a first set of pads and a second set of...

20060186536 - Substrate assembly with direct electrical connection as a semiconductor package: A substrate assembly with direct electrical connection as a semiconductor package is disclosed, which includes a carrier structure formed with at least a cavity; at least a semiconductor chip received in the cavity of the carrier structure having a plurality of electrically connecting pads formed thereon; at least a build-up...

20060186537 - Delamination reduction between vias and conductive pads: Vias and conductive pads configured and coupled in a manner to reduce delamination are described herein. The via and the conductive pads may be located in a substrate such as a carrier substrate, a die, or a printed circuit board....

20060186538 - Land grid array package: A land grid array package has a construction in which a device-side ground electrode 6 and a substrate-side ground electrode 9, as well as device-side peripheral electrodes 7 and substrate-side peripheral electrodes 10 are soldered by eutectic solder 16. The land grid array package is characterized in that one or...

20060186541 - Method and system for bonding a semiconductor chip onto a carrier using micro-pins: An anisotropically conductive layer ‘ACL’ for mechanical and electrical bonding of two circuit containing structures, such as a flip chip and carrier is disclosed. The ACL is formed of a rigid insulating substrate or membrane with a top and bottom planar surfaces formed with a plurality of pins therein. The...

20060186540 - Method to create flexible connections for integrated circuits: A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the...

20060186542 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor substrate which has an integrated circuit formed on a front surface thereof, and a rough surface with a height difference of 1 to 5 μm on a rear surface thereof. A protective film is provided on the rear surface of the semiconductor substrate....

20060186539 - Trace design to minimize electromigration damage to solder bumps: A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology...

20060186544 - Copper bonding wire for semiconductor packaging: Provided is a copper bonding wire formed of a high purity copper of 99.999% or more including at least one of P and Nb within a range between 20 wt ppm and 100 wt ppm and at least one of Zr, Sn, Be, Nd, Sc, Ga, Fr, and Ra within...

20060186543 - Semiconductor devices having plated contacts, and methods of manufacturing the same: A mask layer is applied to a surface of a semiconductor structure or a seed layer deposited on the surface. The mask layer has a submicron width opening with a high aspect ratio that exposes a portion of the surface or seed layer. Conductive material is conformed to the opening,...

20060186545 - Semiconductor chip capable of implementing wire bonding over active circuits: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the...

20060186546 - Nonvolatile semiconductor memory device: A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between...

20060186547 - Light shield for cmos imager: System and method for providing a light shield for a CMOS imager is provided. The light shield comprises a structure formed above a point between a photo-sensitive element and adjacent circuitry. The structure is formed of a light-blocking material, such as a metal, metal alloy, metal compound, or the like,...

20060186548 - Method of manufacturing semiconductor device and semiconductor device: The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film, a second insulating film, a first-mask forming layer, a second-mask forming...

20060186549 - Semiconductor device and method of manufacturing the same: A first gas including a silicon-containing compound is introduced into a vacuum chamber, to expose a semiconductor substrate placed in the chamber to the first gas atmosphere (silicon processing step). Then the pressure inside the vacuum chamber is reduced to a level lower than the pressure at the time of...

20060186550 - Semiconductor device and manufacturing method thereof: In a semiconductor module connecting a semiconductor element and a passive element to a printed board, each of connection portions between the semiconductor element and the printed board and between the passive element and the printed board includes a metal with a melting point of 260° C. or higher and...

20060186551 - Flip chip package with advanced electrical and thermal properties for high current designs: A QFN package and method of making same is provided comprising a substrate having a metal line extending from a connection element on a perimeter region of the substrate to a high current contact pad on interior region of the substrate. A semiconductor chip having an active surface generally faces...

20060186552 - High reflectivity p-contacts for group lll-nitride light emitting diodes: A flip-chip LED device (10) includes a plurality of group III-nitride semiconductor layers (22) defining a p/n junction and including a top p-type group III-nitride layer (28), and a p-contact (30, 30′, 30″) for flip-chip bonding the top p-type group III-nitride layer. The p-contact includes an aluminum layer (32) disposed...

20060186553 - Semiconductor device: An improved reliability of a junction region between a bonding wire and an electrode pad in an operation at higher temperature is presented. A semiconductor device 100 includes a semiconductor chip 102 provided on a lead frame 121, which are encapsulated with an encapsulating resin 115. Lead frames 119 are...

20060186554 - Semiconductor device with a number of bonding leads and method for producing the same: A semiconductor device (7) has a number of bonding leads (1, 2, 3) with more than one individual bonding lead (1) being arranged on an individual contact area (4) of a semiconductor chip (5) or a wiring component (6) of the semiconductor device (7). The bonding leads (1, 2 and...

20060186555 - Semiconductor device with chip-on-board structure: A semiconductor device may include a chip-on-board (COB) substrate having bonding patterns. A semiconductor chip having bonding pads may be electrically connected to the bonding patterns and may be arranged on the COB substrate, and the semiconductor chip may have a square shape and the bonding pads of the semiconductor...

20060186556 - Semiconductor-on-diamond devices and methods of forming: The present invention provides semiconductor-on-diamond devices, and methods for the formation thereof. In one aspect, a mold is provided which has an interface surface configured to inversely match a configuration intended for the device surface of a diamond layer. An adynamic diamond layer is then deposited upon the diamond interface...

20060186558 - Methods of fabricating scalable two transistor memory devices: A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a...

20060186557 - Semiconductor integrated circuit device and fabrication process thereof: A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, the p-channel MOS transistor including a second...

20060186559 - Semiconductor device, and method for manufacturing the same: The invention is characterized by attaining a lower dielectric constant and including an inorganic dielectric film which is formed on the surface of a substrate and has a cyclic porous structure having a pore ratio of 50% or higher....

20060186560 - Back-illuminated imaging device and method of fabricating same: A method for fabricating a back-illuminated semiconductor imaging device on a thin semiconductor-on-insulator substrate, and resulting imaging device. Resulting device has a monotonically varying doping profile which provides a desired electric field and eliminates a dead band proximate to the backside surface....

20060180803 - Phase change memory devices and fabrication methods thereof: In a memory device, at least one conductive contact having a width of less than, or equal to, about 30 nm may be formed on a first electrode. A dielectric layer may be formed on the sides of the at least one conductive contact, and a phase change material film...

20060180804 - Thin-film semiconductor component and production method for said component: A semiconductor component having a thin-film semiconductor body (2) arranged on a germanium-containing carrier (4). A method for producing such a semiconductor component includes producing a semiconductor component having a thin-film conductor body arranged on a carrier, having the steps of growing the thin-film semiconductor body on a substrate, applying...

20060180810 - Composition of conducting polymer and organic opto-electronic device employing the same: A composition including a conducting polymer and an ionomer, and an opto-electronic and an electronic device including the composition are provided. The composition is prepared by doping a conducting polymer with an ionomer which has a low water uptake, has a low content of by-products decomposed by a reaction with...

20060180807 - Electroluminescent device with homogeneous brightness: The invention describes an electroluminescent device equipped with a substrate, a metallic structure and a layer assembly comprising at least a first electrode, an electroluminescent layer and a second electrode. The metallic structure, which is in electrical contact with the first electrode, exhibits a lower layer resistance than the first...

20060180805 - Film comprising organic semiconductors: The invention concerns a film (1), in particular a stamping or laminating film, and a process for the production of such a film. At least one component produced using organic semiconductor technology, in particular one or more organic field effect transistors, is integrated into a film (1)....

20060180812 - Light emitting element and light emitting device: The present invention provides a light emitting element whose driving voltage is low, and a light emitting element having longer lifetime. Moreover, the invention provides a light emitting element with high manufacturing yield. A light emitting element has a layer containing an organic material and an inorganic material, wherein activation...

20060180806 - Organic electroluminescence device: An organic electroluminescence device comprising a cathode, an anode and, sandwiched between the cathode and the anode, at least a hole transporting layer and a light emitting layer containing a phosphorescent light emitting material and a host material, wherein the hole transporting layer comprises a hole transporting material having a...

20060180809 - Organic insulator composition comprising high dielectric constant insulator dispersed in hyperbranched polymer and organic thin film transistor using the same: An organic insulator composition comprising a high dielectric constant insulator dispersed in a hyperbranched polymer and an organic thin film transistor using the insulator composition. More specifically, the organic thin film transistor comprises a substrate, a gate electrode, a gate insulating layer, a source electrode, a drain electrode and an...

20060180808 - Organic semiconductor element having multi protection layers and process of making the same: An organic semiconductor element having multi protection layers and process of making the same are provided. Firstly, forming a first protection layer on the thin film transistor. Next, forming a second protection layer which is thick enough to serve as the photo spacers on said first protection layer. The multi...

20060180811 - Precursor, thin layer prepared including the precursor, method of preparing the thin layer and phase-change memory device: A Te precursor containing Te, a 15-group compound (for example, N) and/or a 14-group compound (for example, Si), a method of preparing the Te precursor, a Te-containing chalcogenide thin layer including the Te precursor, a method of preparing the thin layer; and a phase-change memory device. The Te precursor may...

20060180813 - Liquid crystal display apparatus with wide viewing angle: A liquid crystal display with an improved reference viewing angle is presented. A pixel electrode includes first and second sub-pixel electrodes. A first switching device is connected to the first sub-pixel electrode, one of gate lines, and one of the data lines. A voltage of the second sub-pixel electrode relative...

20060180814 - Thin film transistor-liquid crystal display and manufacturing method therefor: This invention relates to a TFT-LCD and a manufacturing method therefor which etches triple layer patterns in a single process step. As a result, the number of masking processes is reduced and a high quality device is produced with less defects. The method comprises the steps of: depositing a gate...

20060180815 - Flexible active matrix display backplane and method: An active matrix display backplane is formed by annealing a flexible dielectric substrate, and then forming one or more thin-film-transistors (TFTs), one or more pixel electrodes, and an interconnect on a surface of the annealed substrate. The interconnect includes individual, spaced apart electrodes that are electrically coupled to one another....

20060180817 - Silicon phosphor electroluminescence device with nanotip electrode: An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and...

20060180816 - Wide wavelength range silicon electroluminescence device: A method is provided for forming a Si electroluminescence (EL) device for emitting light at short wavelengths. The method comprises: providing a substrate; forming a first insulator layer overlying the substrate; forming a silicon-rich silicon oxide (SRSO) layer overlying the first insulator layer, embedded with nanocrystalline Si having a size...

20060180818 - Semiconductor light emitting device, light emitting module and lighting apparatus: An LED array chip (2) includes blue LEDs (6) and red LEDs (8). The blue LEDs (6) are formed by epitaxial growth on an SiC substrate (4). Bonding pads (46 and 48) are formed on the SiC substrate (4) in a wafer fabrication process. The red LEDs (8) are separately...

20060180819 - Reflective electrode and compound semiconductor light emitting device including the same: A reflective electrode and a compound semiconductor light emitting device including the same are provided. The reflective electrode formed on a p-type compound semiconductor layer of a compound semiconductor light emitting device including an n-type compound semiconductor layer, an active layer, and the p-type compound semiconductor layer, has an ohmic...

20060180820 - Light-emitting semiconductor chip and method for the manufacture thereof: A semiconductor chip, particularly a radiation-emitting semiconductor chip, comprises an active thin-film layer in which a photon-emitting zone is formed, and a carrier substrate for the thin-film layer is arranged at a side of the thin-film layer faces away from the emission direction and is connected to it. At least...

20060180822 - Interchangeable led bulbs and light string assembly therewith: There is disclosed a type of interchangeable LED (light emitting diode) bulb as well as methods for making the said type of interchangeable LED bulb. A resistor is connected in series to an LED to form an interchangeable LED bulb. Two interchangeable LED bulbs are coupled in parallel and with...

20060180821 - Light-emitting diode thermal management system: A device 101 for thermal management of an LED 120 employs a heatsink 160, a substrate 111, a trace layer 130 and a via 180. The via 180 includes a sidewall 182 defining a channel 181 extending through substrate 110. The channel 181 is beneath the trace layer 130 and...

20060180826 - El display device and a method of manufacturing the same: To provide a high throughput film deposition means for film depositing an organic EL material made of polymer accurately and without any positional shift. A pixel portion is divided into a plurality of pixel rows by a bank, and a head portion of a thin film deposition apparatus is scanned...

20060180824 - High power led housing and fabrication method thereof: An LED housing, in which a heat conducting part has a chip mounting area, a heat connecting area opposed to the chip mounting area and a neck between them. Fixing parts have first ends engaged with the neck. An electrical connecting part has a wire connecting area placed adjacent to...

20060180825 - Ic chip coating material and vacuum fluorescent display device using same: An IC chip coating material includes first metal oxide particles; a metal alkoxide; an organic solvent; and second metal oxide particles and/or flat particles of a composite oxide, the second metal oxide particles having a composition identical to or different from that of the first metal oxide particles and also...

20060180823 - Optical semiconductor device package and optical semiconductor device: An optical semiconductor device package includes a disc-shaped stem, metallic leads in rod form penetrating the stem in the direction of the thickness to protrude from a main surface of the stem, and a mount extending vertically from the main surface of the stem, with a plane part of the...

20060180827 - Led light set: An LED light set comprising at least one LED dice and two conductive wires covered by insulated layer, a holder is installed on the wires at every certain distance, one LED dice is installed on every holder; each of the LED dice connects to two conductive wires with very thin...

20060180828 - Light source apparatus and fabrication method thereof: A light source apparatus and a fabrication method thereof can prevent light interference between light emitting devices adjacent to each other and increase the luminous efficiency by collecting light emitted from the side of the light emitting device toward the front of a metal stem by forming grooves at a...

20060180829 - Tunneling gap diodes: The present invention discloses a tunneling diode having a band gap material as the collector. This increases the tunneling of electrons having greater energy than the Fermi level from emitter to collector, leading to an increase in the efficiency of heat pumping or power generation by the diode. In a...

20060180830 - Resonant cavity enhanced multi-quantum well light modulator and detector: Multi-quantum well (MQW) spatial light modulator devices are disclosed that are capable of achieving reasonable quantum efficiencies and high contrast ratios in order to close an optical communication link by resolving the logical on or off state. The device both modulates and detects light through the use of the quantum...

20060180831 - Field effect transistor and method for fabricating the same: A field effect transistor includes a nitride semiconductor layer; an InxAlyGa1-x-yN layer (wherein 0<x<1, 0<y<1 and 0<x+y<1) formed on the nitride semiconductor layer; and a source electrode and a drain electrode formed on and in contact with the InxAlyGa1-x-yN layer. The lower ends of the conduction bands of the nitride...

20060180832 - Method of forming a semi-insulating region: A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the...

20060180833 - Semiconductor material having bipolar transistor structure and semiconductor device using same: In an epitaxial substrate (20) comprising a collector layer (22), a base layer (23) and an emitter layer (24) formed on a semi-insulating GaAs substrate (21), a hole barrier layer (22C) is provided in the collector layer (22) to prevent influx of holes from the base layer (23), whereby the...

20060180834 - High-voltage compatible, full-depleted ccd: A charge coupled device for detecting electromagnetic and particle radiation is described. The device includes a high-resistivity semiconductor substrate, buried channel regions, gate electrode circuitry, and amplifier circuitry. For good spatial resolution and high performance, especially when operated at high voltages with full or nearly full depletion of the substrate,...

20060180835 - Semiconductor component with integrated backup capacitance: On embodiment of the invention provides a semiconductor component with at least one thin oxide transistor, the gate of which is directly connected to a first electrical potential by means of a connecting element. The connecting element contains a thermal desired breaking point. In order to realize an integrated backup...

20060180836 - Semiconductor device and manufacturing method thereof: In the present invention, in a pattern in which gate electrodes are provided in a stripe shape and source regions are provided in a ladder shape, body regions are provided in a stripe shape parallel to the gate electrodes. A first body region is exposed to a surface of a...

20060180837 - Tft substrate for display device and manufacturing method of the same: Disclosed is a TFT substrate for a display apparatus comprising a gate wiring including a gate electrode, a data wiring including a data line, a source electrode connected to the data line, and a drain electrode connected to a pixel electrode, and a semiconductor layer disposed between the gate wiring...

20060180838 - Amorphous high-k thin film and manufacturing method thereof: An amorphous high-k thin film for a semiconductor device and a manufacturing method thereof are provided. The amorphous high-k thin film includes Bi, Ti, Al, and O. Since a BTAO based amorphous dielectric thin film is used as a dielectric material of a DRAM capacitor, a dielectric constant is more...

20060180839 - Magnetoresistance device including layered ferromagnetic structure, and method of manufacturing the same: A layered ferromagnetic structure is composed of a first ferromagnetic layer positioned over a substrate; a second ferromagnetic layer positioned over the first ferromagnetic layer; and a first non-magnetic layer placed between the first and second ferromagnetic layers. The top surface of the first ferromagnetic layer is in contact with...

20060180841 - Edram-type semiconductor device including logic circuit section featuring large capacitance capacitor, and capacitor dram section featuring small capacitance capacitor: In an eDRAM-type semiconductor device, a dynamic random access memory (DRAM) section and a logic circuit section are formed on a semiconductor substrate, and an insulating layer is formed on the semiconductor substrate. A first capacitor is formed in the insulating layer at the DRAM section, the first capacitor defining...

20060180840 - Switched capacitor circuit and semiconductor integrated circuit thereof: A rectangular parallelepiped projecting portion (21) having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion (21), thereby generating a MOS transistor....

20060180842 - Capacitor, method of making the same, filter using the same, and dielectric thin film used for the same: The capacitor (10) in accordance with the present invention comprises a lower electrode (14A), a dielectric layer (16) including an SiO2 layer (20) formed on the lower electrode (14A) and an Si3N4 layer (22) formed on the SiO2 layer (20), and an upper electrode (14B) formed on the dielectric layer...

20060180843 - Methods of forming electronic devices including electrodes with insulating spacers thereon: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the...

20060180844 - Integrated circuitry and method of forming a capacitor: The invention comprises integrated circuitry and to methods of forming capacitors. In one implementation, integrated circuitry includes a capacitor having a first capacitor electrode, a second capacitor electrode and a high K capacitor dielectric region received therebetween. The high K capacitor dielectric region has a high K substantially amorphous material...

20060180845 - Memory device with silicon rich silicon oxide layer and method of manufacturing the same: A memory device with a silicon rich oxide layer and a method of manufacturing the same are provided. The memory device with a silicon rich oxide layer may include a semiconductor substrate, source/drain regions formed on the semiconductor substrate, and a gate structure formed on the semiconductor substrate. The gate...

20060180846 - Semiconductor memory device: In a cell contact pad method, a consecutive dummy cell contact pad intersecting with a cell gate electrode is formed at an outer peripheral portion of the memory cell array. The dummy cell contact pad blocks liquid and gas to intrude through a void, and prevents the cell contact pad...

20060180847 - Two-bit non-volatile memory devices including independently-controllable gate electrodes and methods for fabricating the same: A non-volatile integrated circuit memory device includes a substrate including first and second source/drain regions therein and a channel region therebetween, a first memory cell on the channel region adjacent the first source/drain region, and a second memory cell on the channel region adjacent the second source/drain region. The first...

20060180848 - Wing gate transistor for integrated circuits: A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the...

20060180851 - Non-volatile memory devices and methods of operating the same: Non-volatile memory devices and methods of operating the same are disclosed. A non-volatile memory device includes a semiconductor substrate. A tunnel insulating layer and a gate electrode are on the semiconductor substrate. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple...

20060180849 - Non-volatile semiconductor memory device, drive method and manufacturing method: A MONOS type non-volatile semiconductor memory device has a memory cell array. The memory cell array includes a plurality of pairs of bit line and control line. These bit line-control line pairs are parallel to the channel on the substrate. The memory cell array also includes a plurality of memory...

20060180850 - Process for manufacturing a memory with local electrical contact between the source line and the well: A process for manufacturing a memory having a plurality of memory cells includes the steps of forming a well (having a first type of conductivity) within a wafer of semiconductor material, defining active regions within the well extending in a first direction, forming memory cells within the active regions (each...

20060180852 - Non-volatile semiconductor memory device and its manufacturing method: There is provided a high-reliability nano-dots memory by forming the nano dots uniformly. Also, there is provided the high-speed and high-reliability nano-dots memory by employing a silicon-oxide-film alternative material as a tunnel insulating film. The nano-dots memory includes the tunnel insulating film and silicide nano-dots of CoSi2 or NiSi2. Here,...

20060180853 - Sonos memory device having side gate stacks and method of manufacturing the same: In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region,...

20060180854 - Multiple gate field effect transistor structure: A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said...

20060180855 - Power mos device: A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in...

20060180856 - Semicondutor device and a method of manufacturing the same: s

20060180857 - Semiconductor device edge termination structure and method: In one embodiment, an edge termination structure is formed in a semiconductor layer of a first conductivity type. The termination structure includes an isolation trench and a conductive layer in contact with the semiconductor layer. The semiconductor layer is formed over a semiconductor substrate of a second conductivity type. In...

20060180858 - Superjunction semiconductor device structure and method: In one embodiment, a charge compensation region is formed in a body of semiconductor material. A conductive layer is coupled to the charge compensation layer. In a further embodiment, the charge compensation region comprises a trench filled with opposite conductivity type semiconductor layers....

20060180860 - Image sensor: An image sensor including an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical...

20060180859 - Metal gate carbon nanotube transistor: A top metal gate carbon nanotube transistor may be provided which has acceptable electrical characteristics. The transistor may be formed over a structure including a semiconductor substrate made of an epitaxial layer and covered with an insulating layer. The carbon nanotubes may be deposited thereover, source and drains defined, and...

20060180861 - Semiconductor device and method for manufacturing semiconductor device: In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is...

20060180862 - Semiconductor device, driver circuit and manufacturing method of semiconductor device: The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n− type semiconductor...

20060180863 - Novel implantation method to improve esd robustness of thick gate-oxide grounded-gate nmosfet's in deep-submicron cmos technologies: An implantation method to improve ESD robustness of thick-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies. Based on standard process flow in DGO, a thick gate-oxide ESD device is improved. Instead of using the standard I/O device, the ESD device uses the thin-oxide N-LDD implantation, and thus its ESD robustness is...

20060180864 - Semiconductor device: Signal lines which provide electric connections from an internal circuit formed on a main surface of a semiconductor chip and including, for example, MIS transistor to protective elements constituted by, for example, diodes are drawn out from outlet ports formed on wiring lines disposed between the protective elements, and a...

20060180865 - Semiconductor device: An electrostatic discharge protected transistor of the present invention includes transistors in an active region composed of a p-type semiconductor substrate and surrounded by element isolation regions. On the active region composed of the p-type semiconductor substrate, an on-source silicide film and an on-drain silicide film are provided. The on-drain...

20060180867 - Field effect transistor and method of fabricating the same: Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of...

20060180866 - Structure and method for manufacturing strained finfet: A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is selectively...

20060180869 - Primitive cell that is robust against esd: A primitive cell having a gate pattern that is robust against ESD is provided. The primitive cell comprises: a high finger PMOS transistor and a low finger NMOS transistor. The high finger PMOS transistor has a first terminal connected to a high power source, and a gate to which a...

20060180868 - Structure and method for improved diode ideality: A device is provided which includes a single-crystal semiconductor region disposed in a substrate. The single-crystal region includes a first semiconductor material and a diode disposed in the single-crystal region. The diode includes an anode region including a first alloy region, being an alloy of the first semiconductor material with...

20060180870 - Semiconductor device: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide...

20060180871 - Semiconductor device: An N-type deep well is used to protect a circuit from a noise. However, a noise with a high frequency propagates through the N-type deep well, and as a result, the circuit that should be protected malfunctions. To reduce the area of the N-type deep well. For instance, in the...

20060180872 - Semiconductor device and method of manufacturing the same: A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The first and third transistors share a common n-type channel MOS...

20060180874 - Etching metal silicides and germanides: A metal silicide may be selectively etched by converting the metal silicide to a metal silicate. This may be done using oxidation. The metal silicate may then be removed, for example, by wet etching. A non-destructive low pH wet etchant may be utilized, in some embodiments, with high selectivity by...

20060180873 - Shallow junction semiconductor: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A suicide layer is on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide layer incorporates a substantially uniformly distributed and concentrated...

20060180875 - Ohmic layer, semiconductor device including an ohmic layer, method of forming an ohmic layer and method of forming a semiconductor device including an ohmic layer: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to...

20060180876 - High density stepped, non-planar nitride read only memory: A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer and a pair of source/drain regions that are shared with adjacent cells in a column. The...

20060180878 - Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first...

20060180877 - Semiconductor device, process for producing the same and process for producing metal conmpound thin film: A high dielectric gate insulating film having the structure that a high-nitrogen layer, a low-nitrogen layer, and a high-nitrogen layer are layered in this order from a silicon-substrate side....

20060180879 - Method to enhance the initiation of film growth: The present invention relates generally to integrated circuit (IC) fabrication processes. The present invention relates more particularly to the treatment of surfaces, such as silicon dioxide or silicon oxynitride layers, for the subsequent deposition of a metal, metal oxide, metal nitride and/or metal carbide layer. The present invention further relates...

20060180880 - Magnetic shielding for magnetically sensitive semiconductor devices: A magnetic shielding device is provided for protecting at least one magnetically sensitive component on a substrate according to embodiments of the present invention. The device comprises a first shield having a top portion, and one or more side portions, wherein the top and side portions along with the substrate...

20060180882 - Mems device and manufacturing method of mems device: A MEMS device includes a wiring laminated through an interlayer insulating film on a semiconductor substrate, the interlayer insulating film partially opened up to an upper portion of the substrate, and a structure disposed in the opening, wherein on a sidewall of the interlayer insulating film exposed in the opening...

20060180881 - Probe head and method of fabricating the same: A probe head includes a sensor unit having: as sensor which records or reads data on or from a predetermined medium; first and second shields disposed on both sides of the sensor at a predetermined distance from each other; and first and second intermediate layers respectively interposed between the sensor...

20060180883 - Micro-oscillating element and method of making the same: A micro-oscillating element includes a frame, a movable functional portion, and a torsional joint for joining the frame and the functional portion. The micro-oscillating element also includes first and second comb-tooth electrodes for generation of the driving force for the oscillating motion of the movable functional portion about the torsional...

20060180884 - Material and uses thereof: A composition of a magnetic material and uses thereof A material comprising cobalt (Co), platinum (Pt) and phosphorus (P) having a composition of 94-98 wt % Co, 0-1 wt % Pt and 2-4 wt % P. The material may be subjected to annealing at a temperature between 100 and 500...

20060180886 - Ambient light filter structure: An ambient light filter structure and its response are disclosed. The ambient light filter structure comprises a silicon substrate, a first silicon nitride (Si3N4: 3200A+−200) component layer, a first silver (Ag: 285A+−35) component layer, a second silicon nitride (Si3N4: 920A+−50) component layer, a second silver (Ag: 285A+−35) component layer, and...

20060180885 - Image sensor using deep trench isolation: An image sensor that has a pixel array formed on a semiconductor substrate is disclosed. The pixel array may also be formed on an epitaxial layer formed on the said semiconductor substrate. A plurality of pixels are arranged in a pattern and formed on the epitaxial layer or directly on...

20060180887 - Semiconductor device and production method thereof: In a semiconductor device, a spacer layer is formed around an imaging element on a semiconductor substrate and a glass lid is combined to the spacer layer via an adhesive layer. A space is made between the semiconductor substrate and the glass lid so as to be positioned at a...

20060180888 - Optical sensor package and method of manufacture: A semiconductor package for optical sensing and method of manufacture thereof is disclosed. The semiconductor package comprises a substrate for transmitting radiation and an integrated circuit chip for sensing the radiation. A plurality of connectors for electrical transmission is disposed on the substrate and a plurality of pillars for facilitating...

20060180889 - Detecting pixel matrix integrated into a charge reader circuit: A matrix of detection pixels and a photoelectric detector that includes a matrix of detection pixels and a reading circuit of loads detected by the detection pixels of the matrix. A detection pixel includes a photosensitive semi-conductor area with a first face covered with a first electrode and a second...

20060180890 - Top emission flat panel display with sensor feedback stabilization: The present invention discloses novel top emitter pixel circuitry for flat panel displays. Sensor material is deposited above a substrate. A pixilated opaque cathode is deposited above the sensor material. Organic light emitting diode material is deposited above the cathode. A transparent anode is deposited above the OLED material. Some...

20060180891 - Semiconductor storage device, semiconductor device, and manufacturing method therefor: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal...

20060180892 - Integrated circuit having a schottky diode with a self-aligned floating guard ring and method for fabricating such a diode: c

20060180893 - Device isolation for semiconductor devices: Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in the semiconductive substrate by being aligned to the first trench; and an insulation...

20060180894 - Semiconductor memory device and its manufacturing method: A semiconductor memory device, which prevents the penetration of hydrogen or moisture to a ferroelectric capacitor from its surrounding area including a contact plug portion, comprises a ferroelectric capacitor formed above a semiconductor substrate, a first hydrogen barrier film formed on an upper surface of the ferroelectric capacitor to work...

20060180895 - Capacitor device with vertically arranged capacitor regions of various kinds: A capacitor device selectively combines MOM, MIM and varactor regions in the same layout area of an IC. Two or more types of capacitor regions arranged vertically on a substrate to form the capacitor device. This increase the capacitance per unit of the capacitor device, without occupying an extra layout...

20060180898 - Hybrid type semiconductor integrated circuit and method of manufacturing the same: A hybrid type semiconductor integrated circuit includes a semiconductor active region provided in a first area of a substrate; an insulating region surrounding side surfaces of the semiconductor active region; a mechanical electrode provided in a second area adjacent to the first area and surrounded by a part of the...

20060180896 - Sensor system: Rather than increasing the mass of the structure, the structure in a sensor system suspends its substrate from some mechanical ground. Motion of the substrate relative to the mechanical ground thus provides the movement information. To those ends, the sensor system includes a base, a substrate, and a flexible member...

20060180897 - Silicon-based rf system and method of manufacturing the same: A RF system which includes a silicon substrate formed with at least one via-hole filled with conductive material so that both sides of the silicon substrate are electrically connected with one another; at least one flat device formed on one side of the silicon substrate; and at least one RF...

20060180899 - Semiconductive chip device having insulating coating layer and method of manfacturing the same: Disclosed herein is a semiconductive chip device having an insulating coating layer, which includes a multi-crystalline semiconductive chip requiring surface insulation properties, outer electrodes formed at both ends of the semiconductive chip, and an insulating coating layer formed by fusing glass powder to a silane coupling agent on the surface...

20060180900 - Organo-silsesquioxane polymers for forming low-k dielectrics: A low dielectric constant polymer, comprising monomeric units derived from a compound having the general formula I (R1—R2)n—Si—(X1)4-n, wherein each X1 is independently selected from hydrogen and inorganic leaving groups, R2 is an optional group and comprises an alkylene having 1 to 6 carbon atoms or an arylene, R1 is...

20060180901 - Method and apparatus for increasing the immunity of new generation microprocessors from esd events: A method and apparatus for increasing the immunity of new generation microprocessors from electrostatic discharge events involve shielding the microprocessors at the die level. A gasket of a lossy material is provided on the substrate upon which the microprocessor is mounted. The gasket surrounds the microprocessor to protect it from...

20060180903 - Semiconductor device and process for fabrication thereof: A semiconductor chip is attached to a lead frame with a filmy organic die-bonding material having a water absorption of 1.5% by volume or less; having a saturation moisture absorption of 1.0% by volume or less, having a residual volatile component in an amount not more than 3.0% by weight,...

20060180902 - Semiconductor package with low and high-speed signal paths: The semiconductor package includes two electrical contacts and a semiconductor device coupled to opposing sides of a substrate. The substrate defines at least one via extending at least partially there through. The semiconductor device includes a semiconductor low-speed interface electrically coupled to one of the electrical contacts through the via,...

20060180904 - Non-leaded integrated circuit package system: A non-leaded integrated circuits package system is provided including etching differential height lead structures having inner leads at a paddle height, providing mold locks at the bending points of the differential height lead structures, etching an elevated paddle at a same height as the inner leads, mounting a first integrated...

20060180906 - Chip package and producing method thereof: A chip package and a producing method thereof are provided. The producing method of the chip package includes following steps. First, a bottom surface of a chip is disposed on a carrier, and a top surface of the chip is wire-bonded to the carrier. Then, a first molding compound is...

20060180905 - Ic package with signal land pads: In one embodiment, an integrated circuit package comprises a substrate including a first surface having a plurality of signal land pads and a second surface having a plurality of signal die pads; a plurality of signal connectors arranged to electrically couple the plurality of the signal land pads to the...

20060180907 - Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectonic devices: Packaged microelectronic devices, interconnecting units for packaged microelectronic devices, and methods and apparatuses for packaging microelectronic devices with pressure release elements. In one aspect of the invention, a packaged microelectronic device includes a microelectronic die, an interconnecting unit coupled to the die, and a protective casing over the die. The...

20060180908 - Resin composition, heat-resistant resin paste and semiconductor device using these and method of preparing the same: There are disclosed a resin composition comprising (A) a heat-resistant resin soluble in a solvent at room temperature, (B) a heat-resistant resin which is insoluble in a solvent at room temperature but becomes soluble by heating, and (C) a solvent; a heat-resistant resin paste further containing (D) particles or liquid...

20060180909 - Optical device package: Systems and methods for providing a housing for an optical device. In one implementation, a frame for a device package is provided. The frame includes a rectangular sheet. The rectangular sheet includes an aperture, a curved interface along an interior of the aperture, an elongated portion along an outer edge...

20060180910 - Three-dimensional circuit module and method of manufacturing the same: A three-dimensional circuit module has a three-dimensional structure in which a second board is bonded to a first board at a predetermined angle. The first board has a first notched concave part formed at an edge to be a bonding surface S1 and a second notched concave part formed at...

20060180913 - Input stage of semiconductor device with multiple pads of common function, and multi-chip package having the same: An input stage of a semiconductor device includes at least two pads, input buffers, a current source, and a logic operation circuit. The at least two pads, to which the input buffers respectively correspond, perform a common function. The current source provides a current to the respective at least two...

20060180912 - Stacked ball grid array package module utilizing one or more interposer layers: A multilayer module comprised of stacked IC package layers is disclosed. A plurality of layers preferably having ball grid array I/O are stacked and interconnected using one or more interposer layers for the routing of electronic signals to appropriate locations in the module through angularly depending leads. The stack is...

20060180911 - Stacked integrated circuit and package system: A stacked integrated circuit and package system including attaching a first top integrated circuit over an upper surface of a top substrate, attaching a second top integrated circuit over a lower surface of the top substrate, forming top electrical connectors on the lower surface of the top substrate, and connecting...

20060180914 - Stacked die package system: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top...

20060180915 - Semiconductor package using terminals formed on a conductive layer of a circuit board: A small package is provided for a flash EEPROM memory. The small package uses terminals which are part of a bottom conductive layer of a circuit board. In this manner, the final package can be quite thin. The circuit board can be connected to the integrated circuits and passive devices...

20060180917 - Circuit board for reducing crosstalk of signals: A circuit board includes a first group of layers located close to a top side of the circuit board, and a second group of layers located close to an underside of the circuit board. Signals which are fed to input and output contact terminals on the top side of the...

20060180916 - Ground arch for wirebond ball grid arrays: A structure provides for the control of bond wire impedance. In an example embodiment, there is an integrated circuit device (100) comprising an integrated circuit (130) having a plurality (115) of grounding pads, signal pads, and power pads and a package (110) for mounting the integrated circuit and includes a...

20060180918 - Semiconductor device and method of manufacturing the same: To prevent an electrostatic noise from entering a non-connected power supply pad from a round power supply wiring, there is provided a semiconductor device, including: a round power supply wiring; a plurality of power supply pads that are connected to the same potential through internal power supply wirings; a signal...

20060180919 - Fine pitch low cost flip chip substrate: A package, comprising a substrate having a surface comprising metal traces, a solder mask covering at least a portion of the surface of the substrate, and a first aperture through the solder mask exposing a plurality of metal traces....

20060180920 - Semiconductor device and manufacturing method thereof: After an interlayer insulation film (1) and a CMP stopper film are formed, wiring trenches are formed. Next, after a barrier metal film (4) and a Cu film (5) are buried in the wiring trenches, the Cu film (5) and the barrier metal film (4) are planarized by CMP or...

20060180921 - Method for producing an fbga component and substrate for carrying out the method: A semiconductor component includes a substrate having a chip side and a solder ball side. A semiconductor chip is mounted on the chip side of a substrate. The semiconductor chip is electrically conductively connected to a conductor structure on the substrate. Ball pads are disposed over the solder ball side...

20060180922 - Dielectric material: A dielectric material formed by contacting a low dielectric constant polymer with liquid or supercritical carbon dioxide, under thermodynamic conditions which maintain the carbon dioxide in the liquid or supercritical state, wherein a porous product is formed. Thereupon, thermodynamic conditions are changed to ambient wherein carbon dioxide escapes from the...

20060180923 - Heat sink: A heat sink includes a plurality of plate members combined together. Each plate member has a flat rectangular body provided with mounting holes, two sidewalls extending from a first side and a second side of the flat rectangular body, and a plurality of mounting lugs respectively provided at bottom side...

20060180924 - Apparatus and methods for cooling semiconductor integrated circuit chip packages: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for...

20060180925 - Led housing and fabrication method thereof: The invention relates to an LED housing and its fabrication method. In the LED housing, a heat conducting part has a chip mounting area, a heat connecting area opposed to the chip mounting area and a groove formed adjacent to the heat connecting area. An electrical connecting part has a...

20060180926 - Heat spreader clamping mechanism for semiconductor modules: The semiconductor module includes a circuit board substrate, multiple semiconductor devices, a layer of thermal interface material, a heat spreader, and a heat spreader clamping mechanism. Each semiconductor device has a semiconductor first side coupled to the substrate, and a semiconductor second side opposing the semiconductor first side. The thermal...

20060180927 - Contact structure and method for manufacturing the same: A contact structure includes contact members having leg portions which are deflected using internal stresses. Since the internal stress is used, the leg portions of the contact members are easily and reliably deflected even when the size of the contact members is reduced in accordance with the size reduction of...

20060180928 - Semiconductor chip having solder bump: A semiconductor chip comprises a silicon substrate on which semiconductor elements are formed, pads, each of which is formed on the silicon substrate and electrically connected to at least one of the semiconductor elements, a first insulating layer having an opening over each one of the pads, a first wiring...

20060180929 - Substrate for an fbga semiconductor component: An FBGA semiconductor component has a chip side for receiving a semiconductor chip, a solder ball side for applying solder balls on ball pads, and a bonding channel embodied as an opening between the chip side and the solder ball side and serving for leading through wire bridges between the...

20060180932 - Component arrangement for series terminal for high-voltage applications: One embodiment of the invention relates to a component arrangement having a semiconductor chip, a chip carrier, a contact piece and a package. The semiconductor chip includes a first load terminal, a second load terminal and a control terminal, with the first load terminal and the second load terminal being...

20060180930 - Reliability and functionality improvements on copper interconnects with wide metal line below the via: The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure....

20060180933 - Semiconductor device and manufacturing method of the same: The invention is directed to prevent corrosion of a semiconductor device. In the semiconductor device manufacturing method of the invention, a semiconductor substrate is etched from its back surface in a position corresponding to a first wiring formed on the semiconductor substrate with a first insulation film therebetween, to form...

20060180931 - Semiconductor package with plated connection: A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of...

20060180934 - Wiring structures for semiconductor devices: Wiring structures of semiconductor devices and fabrication methods thereof. A metal layer electrically connected to at least one vertical connection formed in an insulating layer is provided. A dummy dielectric layer is formed in a portion of the metal layer. The dummy dielectric layer is located in a region adjacent...

20060180936 - Fluoropolymer dielectric composition for use in circuitized substrates and circuitized substrate including same: A dielectric composition for forming a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like, the composition including at least two fluoropolymers and two inorganic fillers. A circuitized substrate including at least one such dielectric layer and at least one conductive layer thereon is also...

20060180935 - Semiconductor device: A structure of a semiconductor device provided with a surface electrode can be simplified. Cu, which is a solderable metal, is employed for the gate electrode 101 and the source electrode 104 in a semiconductor device 100. Therefore, unlike as in the conventional technology, it is not necessary to separately...

20060180937 - Electronic module, methods of manufacturing and driving the same, and electronic instrument: An electronic module includes an EL section; a first substrate on which the EL section is formed; a second substrate attached to the first substrate; an integrated circuit chip mounted on the second substrate; a plurality of first power supply interconnects formed on the first substrate, extending through a pair...

20060180938 - Semiconductor device, method of manufacturing the same, capacitor structure, and method of manufacturing the same: A semiconductor device is disclosed that includes an interposer and a semiconductor chip. The interposer includes a Si substrate; multiple through vias provided through an insulating material in corresponding through holes passing through the Si substrate; a thin film capacitor provided on a first main surface of the Si substrate...

20060180939 - Tamper-resistant semiconductor device: The semiconductor device of the present invention includes: first defensive wiring provided above a diffusion isolation layer formed in a substrate or a well, arranged at a minimum wiring pitch allowable in fabrication to cover the diffusion isolation layer; a plurality of signal wiring layers formed above the first defensive...

20060180940 - Semiconductor devices and in-process semiconductor devices having conductor filled vias: At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element forming a conductive structure of the semiconductor substrate. The backside of the semiconductor substrate is exposed to an electroplating solution...

20060180941 - Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements: A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hole may be substantially filled with dielectric...

20060180942 - Semiconductor device: There is provided a small and high-performance System in Package (SiP) suitable for high-density mounting. A System in Package (SiP) has a stack structure such that two memory chips are stacked and mounted over the main surface of a wiring substrate, a microcomputer chip is stacked and mounted over the...

20060180943 - Semiconductor device: The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor...

20060180944 - Flip chip ball grid array package with constraint plate: A flip chip ball grid array package is provided. In one embodiment, a flip chip ball grid array package comprises a substrate having an upper surface and a lower surface opposite the upper surface and a microelectronic element comprising a set of solder balls being secured to the upper surface...

20060180945 - Forming a cap above a metal layer: In one embodiment, the present invention includes an apparatus having a metal layer with a pad disposed above a substrate; and a cap disposed above the metal layer having a first portion to provide for contact with a probe and a second portion to provide a bonding surface, and the...

20060180946 - Bond pad structure for integrated circuit chip: An integrated circuit chip is provided, which includes a bond pad structure. The bond pad structure includes a bond pad, a first metal plate, and a second metal plate. The first metal plate is located under the bond pad. The first metal plate has a first outer profile area. The...

20060180947 - Semiconductor device having deep trench charge compensation regions and method: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers....

20060175596 - Phase change memory cell with high read margin at low power operation: The present invention includes a memory cell device and method that includes a memory cell, a first electrode, a second electrode, phase-change material and an isolation material. The phase-change material is coupled adjacent the first electrode. The second electrode is coupled adjacent the phase-change material. The isolation material adjacent the...

20060175597 - Phase change memory cell with high read margin at low power operation: A memory cell device includes a first electrode, a heater adjacent the first electrode, phase-change material adjacent the heater, a second electrode adjacent the phase-change material, and isolation material adjacent the phase-change material for thermally isolating the phase-change material....

20060175598 - Memory device including barrier layer for improved switching speed and data retention: The present memory device includes a first electrode, a passive layer on and in contact with the first electrode, the passive layer including copper sulfide, a barrier layer on and in contact with the passive layer, an active layer on and in contact with the barrier layer, and a second...

20060175599 - Phase change memory cell with high read margin at low power operation: A memory cell device includes a first electrode, phase-change material adjacent the first electrode, a second electrode adjacent the phase-change material, a diffusion barrier adjacent the phase-change material, and isolation material adjacent the diffusion barrier for thermally isolating the phase-change material. The diffusion barrier prevents diffusion of the phase-change material...

20060175600 - Gallium nitride compound semiconductor device and manufacturing method: A light-emitting element using GaN. On a substrate (10), formed are an SiN buffer layer (12), a GaN buffer layer (14), an undoped GaN layer (16), an Si-doped n-GaN layer (18), an SLS layer (20), an undoped GaN layer (22), an MQW light-emitting layer (24), an SLS layer (26), and...

20060175601 - Nanoscale wires and related devices: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length,...

20060175603 - Compound used to form a self-assembled monolayer, layer structure, semiconductor component having a layer structure, and method for producing a layer structure: Embodiments of the invention provide a semiconductor component and a method of manufacture thereof. A semiconductor component comprises: a gate electrode layer adjacent a substrate, and a gate dielectric layer adjacent the gate electrode layer. The gate dielectric layer comprises a monolayer of at least one compound, wherein the compound...

20060175604 - Novel type of attachment of organic molecules to a silicon surface for producing memory elements having organic constituents: A nonvolatile memory element in a semiconductor structure comprises at least two contacts, of which one comprises silicon, and a monolayer of conductive organic molecules producing a conductive connection between the two contacts. The organic molecule comprise alternating ethynyl and aryl groups and have at least one group selected from...

20060175602 - Organic electroluminescent display: An invention relates to an organic electroluminescent display. The organic electroluminescent display comprises a substrate, a bonding pad, and an FPC (Flexible Print Circuit). The substrate comprises a luminescent surface and a non-luminescent surface. An organic electroluminescent (EL) structure is disposed on the non-luminescent surface to provide the organic EL...

20060175605 - Organometallic light-emitting material: wherein E=Group 16 elements (including sulphur); M=Group 10 metal (including platinum); R1-R14 are each independently selected from the group consisting of hydrogen; halogen; alkyl; substituted alkyl; aryl; substituted aryl, with substituents selected from the group consisting of halogen, lower alkyl and recognized donor and acceptor groups. R1 can also be...

20060175607 - Semiconductor device, device forming substrate, wiring connection testing method, and manufacturing method of the semiconductor device: A semiconductor device includes a substrate, a semiconductor element formed on the substrate, and a wiring connection testing structure which is formed on the substrate and which includes an electron beam irradiation area where an electron beam is irradiated so that a wiring connection is tested. The wiring connection testing...

20060175606 - Subthreshold design methodology for ultra-low power systems: A system and method for enabling a device to function at a subthreshold voltage level of the device is provided. Generally, the system contains a subthreshold data memory capable of functioning when a supply voltage is within the subthreshold voltage level of the device. The system also contains control logic...

20060175608 - Relaxation of a strained layer using a molten layer: A method for making a crystalline wafer, in which an interface layer is associated with a support substrate. A first layer is associated with the interface layer in a strained state. The interface layer is melted sufficiently to substantially uncouple the first layer from the support substrate to relax the...

20060175612 - Semiconductor device and fabrication method thereof: Regions 106 which can be regarded as being monocrystalline are formed locally by irradiating with laser light, and at least the channel-forming region 112 is constructed using these regions. With thin-film transistors which have such a construction it is possible to obtain characteristics which are similar to those which employ...

20060175610 - Signal line, thin film transistor array panel with the signal line, and method for manufacturing the same: System and techniques for providing signal lines comprising copper alloys including at least one of molybdenum, tungsten, and chromium. The present disclosure provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line;...

20060175611 - Thin film transistor circuit device, production method thereof and liquid crystal display using the thin film transistor circuit device: A thin film transistor circuit device and the production method thereof is demanded for a thin film transistor circuit device, which contains wiring having a structure of an aluminum alloy in a lower layer and a molybdenum alloy in an upper layer, wherein corrosion in air of the molybdenum alloy...

20060175609 - Vertical thin film transistor with short-channel effect suppression: A vertical this film transistor (TFT) structure allows for a channel length to be scaled down, below that allowed by lateral TFT structures, to nanoscale (i.e., below 100 nm). However, while reducing the channel length, short-channel effects have been found in previous VTFT structures. Aspects of the new vertical TFT...

20060175613 - Method of manufacturing an epitaxial semiconductor substrate and method of manufacturing a semiconductor device: In an example embodiment of the method of manufacturing an epitaxial semiconductor substrate, a gettering layer is grown over a semiconductor substrate. An epitaxial layer may then be formed over the gettering layer, and a semiconductor device may be formed on the epitaxial layer....

20060175614 - Cmos imager having on-chip rom: A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing results and repair solutions are written to the ROM after production testing. A simple circuit for writing information to...

20060175619 - Aluminum nitride single-crystal multi-layered substrate: An aluminum nitride single-crystal multi-layered substrate comprising an aluminum nitride single-crystal layer formed by direct reduction nitridation on a single-crystal α-alumina substrate such as a sapphire substrate and an edge-type dislocation layer having a thickness of 10 nm or less in the vicinity of the interface between the both crystals....

20060175616 - Pre-oxidized protective layer for lithography: An optical component for use in, e.g., an extreme ultraviolet (EUV) lithography system, may include a pre-oxidized protective layer. The protective layer may be photocatalytic, and may be substantially amorphous to provide a diffusion barrier. The protective layer may be, e.g., a metal oxide such as titanium dioxide or molybdenum...

20060175618 - Semiconductor device: A semiconductor device, which can accurately control carrier density, includes: a single crystal substrate; a semiconductor layer which is made of hexagonal crystal with 6 mm symmetry and is formed on the single crystal substrate; a source electrode, a drain electrode and a gate electrode which are formed on the...

20060175617 - Surface emitting type device, and method for manufacturing the same: A surface-emitting type device includes a rectification section including a substrate and a first semiconductor layer formed above the substrate, and an emission section including a second semiconductor layer of a first conductivity type formed above the rectification section, an active layer formed above the second semiconductor layer and a...

20060175615 - System and method for increasing the surface mounting stability of a lamp: In one embodiment, an LED is constructed with its entire contact structure is stamped and inserted into the molded lamp as a single structure. A portion of the contact structure is imbedded in the molded lamp such that the bottom surface of the contacts do not extend below the base...

20060175620 - Epitaxial wafer for light emitting diode: An epitaxial wafer for LED is provided with a layered structure by sequentially growing a p-type AlGaAs active layer 2, and a n-type AlGaAs window layer 1 on a p-type GaAs substrate 3 by liquid phase epitaxy (LPE) growth using Boat method. A maximum value of a dislocation density in...

20060175621 - Semiconductor light-emitting device light-emitting display method for manufacturing semiconductor light-emitting device and method for manufacturing light-emitting display: A semiconductor light-emitting device includes substrate (3), a plurality of light-emitting-element-layers (10a, 10b, 10c, . . . ) of semiconductor material formed on the substrate (3) so as to be isolated from each other and having a wider band gap than the substrate (3), and phosphors (15a, 15b, 15c, ....

20060175622 - Micromirror-based projection system and a method of making the same: A projection system is disclosed herein. The projection system employs a spatial light modulator comprising an array of individually addressable pixels for modulating the incident light based on image data. The modulated light is projected on a screen for viewing....

20060175623 - Light-source apparatus and image display apparatus: The present invention provides an image display apparatus including a light-source apparatus and a light-source apparatus in which a plurality of light-emitting devices are uniformly cooled to prevent any variation in brightness. The light-source apparatus includes a plurality of light-emitting devices for emitting illumination light, a holding member for holding...

20060175624 - Semiconductor light-emitting device: A semiconductor light-emitting diode, and method of fabricating same, wherein an indium (In)-containing light-emitting layer, as well as subsequent device layers, is deposited on a textured surface. The resulting device is a phosphor-free white light source....

20060175625 - Light emitting element, lighting device and surface emission illuminating device using it: In a non-sealed type light emitting device in which a diode structure on a face of a transparent substrate by lamination of an n-type semiconductor layer and a p-type semiconductor layer, an outer face of the transparent substrate is made not in parallel with a most outer face of the...

20060175626 - Beam shutter in led package: A beam shutter is disclosed that is affixed to an LED die submount or circuit board to sharply define the emitted pattern. The beam shutter may be a solid piece of aluminum or any other opaque material to block a portion of the light emitted from the LED die. The...

20060175627 - Power supply, multi chip module, system in package and non-isolated dc-dc converter: A power supply includes a non-isolated DC-DC converter for use in a power source system having a high side switch and a low side switch, in which HEMT or HFET or gallium nitride device with low capacity and low on-resistance is used for the high side switch and a vertical...

20060175628 - Nitride-based semiconductor device of reduced voltage drop, and method of fabrication: A light-emitting diode is built on a silicon substrate which has been doped with a p-type impurity to possess sufficient conductivity to provide part of the current path through the LED. The p-type silicon substrate has epitaxially grown thereon a buffer region of n-type AlInGaN. Further grown epitaxially on the...

20060175629 - Vertical thyristor for esd protection and a method of fabricating a vertical thyristor for esd protection: A vertical thyristor for ESD protection comprises an anode (10), a cathode (16), a first gate electrode (12) and a second gate electrode (14). The first (12) and second (14) gate electrodes are arranged between the anode (10) and the cathode (16), wherein the first gate electrode (12) is an...

20060175630 - Electronic power module comprising a rubber seal and corresponding production method: An aim of an embodiment is to reduce the volume of power modules, especially for electronic motor control devices. An area is formed between cooling elements with the aid of an annular shaped rubber seal. A semi-conductor device is sealed with a sealing compound therein. Both sides of the semi-conductor...

20060175633 - Iii-nitride integrated schottky and power device: A III-nitride power device that includes a Schottky electrode integrated with a power switch. The combination is used in power supply circuits such as a boost converter circuit....

20060175631 - Monolithic integrated circuit having enhanced breakdown voltage: A field effect transistor structure is provided having: a III-V substrate structure; an InGaAs layer disposed over the substrate structure; an AlGaAs layer disposed on the InGaAs layer; an semiconductor layer disposed on the AlGaAs layer, where the bandgap energy of the semiconductor layer is greater than 1.8 eV; an...

20060175632 - Monolithic integrated circuit having enhancement mode/depletion mode field effect transistors and rf/rf/microwave/milli-meter wave milli-meter wave field effect transistors: A semiconductor structure having: a III-V substrate structure; an enhancement mode transistor device disposed in a first region of the structure; a depletion mode transistor device disposed in a laterally displaced second region of the structure; and a RF/microwave/milli-meter wave transistor device formed in a laterally displaced third region thereof....

20060175634 - Redundant interconnect high current bipolar device and method of forming the device: A device. The device includes two bipolar transistors electrically connected to each other. Each bipolar transistor of the two bipolar transistors may include a base contact and an emitter contact surrounding the base contact, wherein the emitters contacts of the two bipolar transistor are in electrical contact with each other....

20060175635 - Semiconductor device: A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors...

20060175636 - Integrated circuit: An integrated circuit (51) comprises a power distribution network having a power pad (53) and a ground pad (55) arranged at diagonally opposite comers of the integrated circuit (51). Apower bus (67, 69) and a ground bus (71, 73) supply power to circuit elements on the integrated circuit, for example...

20060175637 - Power line layouts of a macro cell and combined layouts of a macro cell and a power mesh: A power line layout of a macro cell includes power lines arranged on a plane of the macro cell in a diagonal direction. A combined layout of a macro cell and a power mesh includes a power mesh on which first power lines are formed in a vertical direction and...

20060175638 - Semiconductor device and a method for manufacturing the same: The difficulty of miniaturization of large-scale integrated circuits in electric devices based on the conventional techniques involving three-dimensional device structures or the introduction of novel materials is solved. Wires 2 and 3 are disposed to intersect one another in midair in a matrix. The ends of the wires 2 and...

20060175639 - Electrode structure comprising an improved output compatibility and method for producing said structure: For a component operating with acoustic waves, it is proposed to arrange the electrode structure over a mechanically stable adaptation layer that serves to dissipate the electromechanical stresses. Further improvements of the output compatibility are achieved with additional intermediate layers and passivation layers applied on the sides or the entire...

20060175640 - Semiconductor memory device, memory cell array, and method for fabricating the same: A semiconductor memory device suitable for use in a memory cell array includes a solid electrolyte memory cell including: a first electrode device, a second electrode device, and a solid electrolyte material region between the first and second electrode devices. The solid electrolyte material region is materially cohesive, and the...

20060175641 - Raised photodiode sensor to increase fill factor and quantum efficiency in scaled pixels: An image pixel cell with a doped, hydrogenated amorphous silicon photosensor, raised above the surface of a substrate is provided. Methods of forming the raised photosensor are also disclosed. Raising the photosensor increases the fill factor and the quantum efficiency of the pixel cell. Utilizing hydrogenated amorphous silicon decreases the...

20060175643 - Ferroelectric element and method of manufacturing ferroelectric element: Additional elements of Ca, Sr, and Ir are added to a single layer lead lanthanum zirconate titanate (PLZT), thereby decreasing a c/a ratio to within a range from 1.00 to 1.008 smaller than a general c/a of a range from about 1.01 to 1.03 generally used in a lead lanthanum...

20060175644 - Ferroelectric recording medium and writing method for the same: A ferroelectric recording medium and a writing method for the same are provided. The ferroelectric recording medium includes a ferroelectric layer which reverses its polarization when receiving a predetermined coercive voltage. A nonvolatile anisotrophic conduction layer is formed on the ferroelectric layer. A resistance of the anisotrophic conduction layer decreases...

20060175645 - Semiconductor device and its manufacturing method: A semiconductor device includes a switching element formed on a semiconductor substrate, a first interconnect layer formed on the semiconductor substrate and having a first wiring connected to one terminal of the switching element, a ferroelectric capacitor formed on the first interconnect layer and having a first electrode connected to...

20060175642 - Semiconductor device and method of manufacturing the same: In a ferroelectric capacitor structure 30 in which a lower electrode and an upper electrode are coupled capacitively with each other through a ferroelectric film, when the upper electrode is formed into a two-layer structure in which a conductive oxide film and an oxidation-resistant metal film are stacked, a protective...

20060175648 - Memory device and manufacturing method thereof: As for a memory element implemented in a semiconductor device typified by an RFID, it is an object of the present invention to reduce manufacturing steps and to provide a memory element and a memory circuit having the element with reduced cost. It is a feature of the present invention...

20060175646 - Memory element using active layer of blended materials: The present memory device has first and second electrodes, a passive layer between the first and second electrodes and on and in contact with the first electrode, and an active layer between the first and second electrodes and on and in contact with the passive layer and second electrode, for...

20060175647 - Semiconductor product having a semiconductor substrate and a test structure and method: A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is disclosed. Methods are disclosed for making an electrical measurement, to...

20060175649 - Sram devices, and electronic systems comprising sram devices: The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystalline layer, and in particular aspects an entirety of the active...

20060175650 - Memory cells with vertical transistor and capacitor and fabrication methods thereof: Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a...

20060175651 - Semiconductor integrated circuit device and process for manufacturing the same: Formation of an WNX film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNX film 24 is suppressed in the heat treatment step after the formation...

20060175652 - Non-volatile memory and operating method thereof: A non-volatile memory having memory cell columns is provided. Each memory cell column includes many memory cells having a charge-trapping layer and a column select unit. There are no gaps between the memory cells and between the column select unit and the memory cells. A source region and a drain...

20060175653 - Nonvolatile nanochannel memory device using mesoporous material: A nonvolatile nanochannel memory device using a mesoporous material. Specifically, a memory device is composed of a mesoporous material that is able to form nanochannels, in which a memory layer having metal nanoparticles or metal ions fed into the nanochannels is disposed between an upper electrode and a lower electrode....

20060175654 - Flash memory: A method for fabricating a flash memory is described. A mask layer having openings to expose a portion of the substrate is formed on the substrate. A tunneling dielectric layer is formed at the bottom surface of the openings. Conductive spacers are formed on the sidewalls of the openings. The...

20060175655 - Non-volatile memory and method for manufacturing non-volatile memory: A coupling oxide film is formed on a silicon substrate, a polysilicon film is further formed thereupon, and a low-temperature oxide film is deposited to a thickness of 10 nm, for example. Next, a silicon nitride film is formed on this low-temperature oxide film, and selectively removed by dry etching....

20060175656 - Non-volatile memory devices: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply...

20060175657 - Advanced cmos using super steep retrograde wells: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of...

20060175658 - High voltage laterally double-diffused metal oxide semiconductor: A high voltage laterally double-diffused metal oxide semiconductor (LDMOS) structure is characterized as follows: the second source electrode metal layer connected to the first source electrode metal layer protrudes out of a certain length relative to the first source electrode metal layer of the source electrode region connected thereto. The...

20060175659 - A cmos structure for body ties in ultra-thin soi (utsoi) substrates: The present invention provides a semiconducting structure including a substrate having an UTSOI region and a bulk-Si region, wherein the UTSOI region and the bulk-Si region have a same crystallographic orientation; an isolation region separating the UTSOI region from the bulk-Si region; and at least one first device located in...

20060175661 - Soi mosfet device with reduced polysilicon loading on active area: Silicon-on-insulator (SOI) devices with reduced polysilicon loading on an active area uses at least one dielectric layer resistant to silicidation to separate at least one body contact region from source/drain regions, thus reducing gate capacitance and improving device performance. The SOI devices may be used in full depletion type transistors...

20060175660 - Vertical body-contacted soi transistor: A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region...

20060175663 - Electrostatic discharge circuit and method of dissipating an electrostatic current: An electrostatic discharge circuit between a first pad and a second pad including an electrostatic discharge circuit element, including a bipolar transistor path and a resistor path, the electrostatic discharge circuit element alternately discharging an electrostatic current through the bipolar transistor path and the resistor path....

20060175662 - Reverse blocking semiconductor component with charge compensation: The invention relates to a field effect controllable semiconductor component, comprising a semiconductor body with a first terminal zone and a second terminal zone, a channel zone formed between the two terminal zones, a control electrode, and also a plurality of compensation zones. The semiconductor component furthermore has additional doping...

20060175665 - Design and optimization of nmos drivers using self-ballasting esd protection technique in fully salicided cmos process: Design and optimization of NMOS drivers using a self-ballasting ESD protection technique in a fully silicided CMOS process. Silicided NMOS fingers which include segmented drain diffusion. Specifically, the segmented drain diffusion provides self-ballasting resistors which improves the ESD performance. Preferably, the width of the each diffusion resistor is relatively small,...

20060175666 - Integrated circuit arrangement with low-resistance contacts and method for production thereof: An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a...

20060175664 - Semiconductor constructions, and methods of forming metal silicides: The invention includes methods of forming metal silicide. A layer consisting essentially of one or more metal nitrides is formed directly against a silicon-containing region. A layer comprising one or more metals is formed over the one or more metal nitrides. Silicon is transferred from the silicon-containing region, through the...

20060175667 - Mosfet-type semiconductor device, and method of manufacturing the same: A MOSFET-type semiconductor device includes a monocrystalline semiconductor layer formed in a shape of a thin wall on a insulating film, a gate electrode straddling over the semiconductor layer around the middle portion of the wall-shaped semiconductor layer via a gate insulating film, source and drain regions formed at the...

20060175668 - Analytic structure for failure analysis of semiconductor device: In an analytic structure for failure analysis of a semiconductor device, a plurality of analytic regions are arranged in regions of a semiconductor substrate. A plurality of semiconductor transistors having an array structure are arranged in each of the analytic regions. A plurality of interconnection structures connect the semiconductor transistors,...

20060175669 - Semiconductor device including finfet having metal gate electrode and fabricating method thereof: Provided are a semiconductor device including a FinFET having a metal gate electrode and a fabricating method thereof. The semiconductor device includes: an active area formed in a semiconductor substrate and protruding from a surface of the semiconductor substrate; a fin including first and second protrusions formed of a surface...

20060175670 - Field effect transistor and method of manufacturing a field effect transistor: A field effect transistor includes a source electrode (30) and a drain electrode (29) formed to be spaced apart from each other on a semiconductor substrate (2), a gate electrode (22) disposed between the source electrode (30) and the drain electrode (29), and a field plate electrode (24, 26) disposed...

20060175671 - Mosfet having a channel mechanically stressed by an epitaxially grown, high k strain layer: A transistor, such a MOSFET, having an epitaxially grown strain layer disposed over a channel region of a substrate for stressing the channel region to increase the carrier mobility in the channel, and method for making same. The strain layer is composed of a high dielectric constant material....

20060175672 - Semiconductor device and method of manufacturing the same: According to an aspect of the present invention, there is disclosed a semiconductor device comprising a semiconductor substrate, and a gate insulating film of a P-channel MOS transistor, formed on the semiconductor substrate. The gate insulating film has an oxide film (SiO2), and a diffusion preventive film (BN) containing boron...

20060175673 - System and device including a barrier layer: Systems and devices are disclosed utilizing a silicon-containing barrier layer. A semiconductor device is disclosed and includes a substrate, a gate oxide, a silicon-containing barrier layer and a gate electrode. The gate oxide is formed over the substrate. The silicon-containing barrier layer is formed over the gate oxide by causing...

20060175675 - Double-decker mram cell with rotated reference layer magnetizations: A double-decker MRAM cell is provided, including a stacked structure of first and second magnetic tunnel junctions. Each magnetic tunnel junction includes first and second free and fixed magnetic regions made of magnetic material separated by a first and second tunneling barrier layers made of non-magnetic material. The fixed magnetic...

20060175674 - Integrated sensor having a magnetic flux concentrator: An integrated sensor has a magnetic field sensing element and first and second relatively high magnetically permeable members forming a gap, wherein the magnetic field element is disposed within the gap. The magnetically permeable members provide an increase in the flux experienced by the magnetic field sensing element in response...

20060175676 - Optical modulator module: A high frequency substrate, on which a high frequency substrate transmission line for connecting a chip carrier transmission line and a package substrate transmission line is formed, is mounted while being inclined with respect to a package, so that each distance between the transmission lines can be reduced. Thereby, the...

20060175677 - Fabrication of low leakage-current backside illuminated photodiodes: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or...

20060175678 - Drain extended mos transistors with multiple capacitors and methods of fabrication: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A...

20060175679 - Semiconductor device and method for manufacturing the same: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to...

20060175680 - Balun: A balun in which the phase shift may be reduced significantly is disclosed. The balun has three lines, i.e. a first line b, a second line a and a third line c, arranged in parallel with the ground surface. The second line a and the third line c are arranged...

20060175681 - Method to grow iii-nitride materials using no buffer layer: Disclosed is a method for growing nitride compound semiconductors on sapphire substrates where no low-temperature buffer layer is used. The nitride based compound semiconductor materials and devices grown by the method of the present invention have crystallinity and surface morphology at practical levels with high quality, high stability, and high...

20060175682 - Transparent electrode: A transparent electrode for use in a gallium nitride-based compound semiconductor light-emitting device having an emission wavelength of 440 nm or less, includes a metal layer disposed in contiguity to a p-type semiconductor layer and a current diffusion layer disposed on the metal layer. The transparent electrode contains substantially no...

20060175683 - Composition for forming low dielectric thin film including siloxane monomer or siloxane polymer having only one type of stereoisomer and method of producing low dielectric thin film using same: Disclosed herein is a composition for forming a low dielectric thin film, which includes silane monomers having only any one of stereoisomer, or a siloxane polymer produced by polymerizing the monomers, and a method of producing the low dielectric thin film using the same. When using the composition, mechanical properties...

20060175685 - Composition for forming low-dielectric constant film comprising fullerene, low-dielectric constant film formed from the composition and method for forming the low-dielectric constant film: A composition for forming a low-dielectric constant film comprising a substituted fullerene, a low-dielectric constant film formed from the composition, and a method for forming the low-dielectric constant film are provided. The low-dielectric constant film has superior mechanical properties, such as hardness and elastic modulus, and excellent thermal conductivity....

20060175684 - Organosilicon compound: Since the majority of conventional organic/inorganic composite materials are obtained by mechanical blending of a silsesquioxane and an organic polymer or other means, it was extremely difficult to control the structure of the composite as a molecular agglomerate. In order to solve such a problem, the invention is to provide...

20060175686 - Semiconductor device and fabrication method thereof: A semiconductor device fabrication method comprises the steps of: (a) forming a pad electrode on the semiconductor device; (b) coating the surface of the semiconductor device with an organic dielectric film so as to expose the center portion of the pad electrode; (c) treating the exposed surface of the pad...

20060175687 - Method and device for integrating an illumination source and detector into the same ic package that allows angular illumination with a common planar leadframe: An optical navigation device includes an integrated package. The integrated package includes a planar leadframe, a light source die mounted on the leadframe, and a sensor die mounted on the leadframe to be coplanar with the light source die. The integrated package may be mounted at an angle or parallel...

20060175688 - Stacked integrated circuit package system: An integrated circuit package system having stacked lead frames including providing a first stackable lead frame package having a first integrated circuit therein and a second stackable lead frame package with a second integrated circuit therein. The first stackable lead frame package having a plurality of leads including protrusions is...

20060175689 - Multi-leadframe semiconductor package and method of manufacture: A multi-leadframe semiconductor package and method of manufacture includes a first leadframe having a die pad and a plurality of contact leads around the periphery of the die pad. A die is attached to the die pad and electrically connected to the plurality of contact leads. A heat spreader leadframe...

20060175690 - Interposer configured to reduce the profiles of semiconductor device assemblies, packages including the same, and methods: An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may include first and second sets of contact pads carried by the substrate. The interposer may also include conductive traces carried by the substrate to electrically connect...

20060175691 - Semiconductor device with gold coatings, and process for producing it: A semiconductor device (7) has gold coatings (1 to 5) which are applied to metallic or ceramic components (6) of the semiconductor device (7). The gold coatings (1 to 4) have a multifunctional multilayer metal coating (8) with a minimal gold layer (9). The gold layer has a thickness dG...

20060175692 - Substrate structure with embedded semiconductor chip and fabrication method thereof: A substrate structure with embedded semiconductor chip and a fabrication method thereof are provided. The method includes: providing a carrier board having a first surface and an opposing second surface, wherein a first opening and an opposing second opening are formed in the first and second surfaces respectively, and a...

20060175695 - Integrated circuit package system using interposer: An integrated circuit package system is provided in which an interposer of predetermined thickness is formed. A central portion of the interposer is removed, thereby forming a cavity. Additionally, one or more contacts are formed around the central cavity on the interposer. The interposer is employed for connecting first and...

20060175696 - Nested integrated circuit package on package system: A package on package system is provided including providing a first substrate having a first integrated circuit thereon and a second substrate having a second integrated circuit thereon, the second substrate having a recess provided therein. The first and second substrates are mounted having the first integrated circuit at least...

20060175697 - Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof: Chips are stacked and mounted on a circuit board having external connection electrodes and mounted thereon by wire bonding. At least one of the chips stacked on the chip includes overhung portions each of which has a start point inside bonding pads, is made thinner in a direction towards the...

20060175694 - Stacked structure of integrated circuits and method for manufacturing the same: A stacked structure of integrated circuits includes a substrate, a frame layer, an upper integrated circuit, a plurality of first wires, a plurality of spacer elements, a lower integrated circuit, a plurality of second wires, and a compound. The substrate has a first surface and a second surface on which...

20060175693 - Systems, methods, and apparatus for generating ball-out matrix configuration output for a flex circuit: Systems, methods, and apparatus for generating a ball-out matrix configuration for a flex circuit are provided. An exemplary processor implemented method for generating a ball-out matrix configuration for at least one flex circuit includes retrieving a set of ball-out matrix constraints for the flex circuit. The method further includes processing...

20060175698 - Semiconductor device: A semiconductor device includes a pad composed of plural wiring layers and a power supply ring to provide a power supply provided through the pad for the power supply to an internal circuit, and the pad for the power supply and the power supply ring are connected by vias provided...

20060175699 - Interposers with flexible solder pad elements: Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes flexible solder pad elements that are formed from a core material of the interposer, such that the interposer may absorb thermally induced stresses and conform to warped...

20060175700 - Semiconductor device and method of manufacturing the same: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded...

20060175701 - Dissociated fabrication of packages and chips of integrated circuits: A method of fabricating a semiconductor component includes providing a prefabricated frame that includes metal traces and lead-through contacts. A semiconductor chip is mounted into the prefabricated frame such that the semiconductor chip is embedded within a rim of the prefabricated frame. Contact regions on a surface of the semiconductor...

20060175702 - Ball grid array package: A circuit assembly comprising a first circuit board and a second circuit board and an electrical connection between the first board and the second board, wherein the electrical connection comprises an outer coating of a electrically conductive first material and two inner cores of a second material, the first material...

20060175703 - Thermally responsive pressure relief plug and method of making the same: A preformed pressure relief plug for insertion into a cavity of a vessel or valve. The plug may be formed of a eutectic alloy of bismuth, indium and tin....

20060175704 - Current collecting structure and electrode structure: An object of this invention is to achieve the current collecting structure and the electrode structure with good electrical conductivity and ionic conductivity which are comprised of the current collecting substrate and the current collecting structure or the electrode structure that are covered with the carbon material or the electrode...

20060175705 - Semiconductor device and method for fabricating the same: A semiconductor device has a first insulating film formed on a substrate and having a first trenched portion, a second insulating film formed on the first insulating film, a third insulating film formed on the second insulating film and having a specific dielectric constant of 3 or less, and a...

20060175706 - Tft array panel and fabricating method thereof: Disclosed is display part such as a TFT array panel comprising an aluminum layer, and a molybdenum layer formed on the aluminum layer. The thickness of the molybdenum layer may be about 10% to about 40% the thickness of the aluminum layer. As a result, a top surface of the...

20060175707 - Wafer level packaging cap and fabrication method thereof: A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with...

20060175709 - Integrated circuits and interconnect structure for integrated circuits: A method for reducing parasitic resistance in an integrated circuit, comprises connecting first and second terminals of a first transistor to second and first plane-like metal layers, respectively; connecting third and fourth terminals of a second transistor to said first and a third plane-like metal layer, respectively; and connecting first,...

20060175708 - Semiconductor device and method of manufacturing the same: A nitrided metal cap film 35 is provided in the upper portion of the metal cap 34 including CoWP. The metal cap 34 and the nitrided metal cap film 35 can be, for example, 1 nm to 100 nm in layer thickness. A ratio of the layer thickness of the...

20060175710 - Consolidated flip chip bga assembly process and apparatus: A flip chip packaging technique and associated apparatus that consolidates many or all of the steps in a conventional flip chip packaging process results in substantially decreased packaging time, e.g., only one to two hours, complexity, e.g., requiring fewer pieces and much simpler equipment, and cost, arising from reduced equipment...

20060175711 - Structure and method for bonding an ic chip: A method for bonding an IC chip to a substrate where the method comprises the steps of providing an IC chip with a plurality of bumps each having a buffer layer and a conductive layer, providing a substrate having a plurality of conductive elements arranged corresponding to the plurality of...

20060175712 - High performance ic package and method: A novel wire-based interconnect IC package is described as well as the method of designing and the method of producing the IC package. The IC package includes one or more signal carrying wires as well as ground return wires associated with each signal carrying wire to electrically couple a chip...

20060175713 - Liquid crystal display panel: A COG type liquid crystal display panel 10 in which a rectangular chip mounting area MA for mounting an IC chip 14 is provided on one of a pair of substrates 11, 12 on which a plurality of electrodes are provided, a plurality of extraction electrodes 20 that are severally...

20060175714 - Semiconductor device: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad...

20060175716 - Molded package and semiconductor device using molded package: A molded package comprises at least a first metal member, a second metal member, and a third metal member. Each member includes an end portion inserted into a mold member where a recess is formed and another end portion protruding from an outer wall of the mold member. A portion...

20060175715 - Semiconductor device and capsule type semiconductor package: An interposer substrate having electrodes on the front surface and on the rear surface thereof, respectively, is prepared, and at least one memory chip having electrodes connected to an internal circuit is prepared. Then, the rear surface of the memory chip is bonded to the front surface of the interposer...

20060175717 - Semiconductor device and method of making the same: A semiconductor device and a method of making a semiconductor device are provided, wherein the device includes a die-pad, a semiconductor chip and a sealing resin. The die-pad has a first surface and a second surface opposite to the first surface. The second surface includes an exposed portion and a...

20060175718 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate having a first element isolation trench with a first opening width and a second element isolation trench with a second opening width larger than the first opening width, the first and second element isolation trenches having respective inner surfaces, the second element isolation...

20060169968 - Pillar phase change memory cell: The present invention includes a phase-change memory cell device and method that includes a memory cell, a selection device, a contact, and a sublithographic pillar. The contact is coupled to the selection device. The phase-change pillar is coupled to the contact. The sublithographic pillar is coupled to the contact. The...

20060169969 - Bandgap cascade cold cathode: A bandgap cascade cold cathode is obtained by constructing a wide bandgap Si/C superlattice thin film; depositing Si on the epitaxial silicon surface under CVD or ALD; depositing on the Si/C surface a first metal effective to form a metal-silicide electrode; etching away the silicon substrate to form an effectively...

20060169970 - Creation of anisotropic strain in semiconductor quantum well: Methods and devices for creating an anisotropic strain in a semiconductor quantum well structure to induce anisotropy thereof are disclosed herein. Initially, a substrate is provided, and a quantum well structure formed upon the substrate. A first crystalline layer (e.g., a GaAs layer) having a first crystalline phase can then...

20060169971 - Energy conversion film and quantum dot film comprising quantum dot compound, energy conversion layer including the quantum dot film, and solar cell including the energy conversion layer: An energy conversion film and a quantum dot film which contain a quantum dot compound, an energy conversion layer including the quantum dot film, and a solar cell including the energy conversion layer. The films act as cut-off filters blocking light of a particular energy level using the light absorption...

20060169972 - Vertical carbon nanotube transistor integration: A hybrid semiconductor structure which includes a horizontal semiconductor device and a vertical carbon nanotube transistor, where the vertical carbon nanotube transistor and the horizontal semiconductor device have at least one shared node is provided. The at least one shared node can include, for example, a drain, source or gate...

20060169975 - Lipid bilayers on nano-templates: A lipid bilayer on a nano-template comprising a nanotube or nanowire and a lipid bilayer around the nanotube or nanowire. One embodiment provides a method of fabricating a lipid bilayer on a nano-template comprising the steps of providing a nanotube or nanowire and forming a lipid bilayer around the polymer...

20060169973 - Semiconductor device, electronic device, and method of manufacturing semiconductor device: To provide a semiconductor device and a display device which can be manufactured through a simplified process and the manufacturing technique. Another object is to provide a technique by which a pattern of wirings or the like which is partially constitutes a semiconductor device or a display device can be...

20060169974 - Thin film transistor, a method of manufacturing the same, and a flat panel display device including the thin film transistor: Provided are a thin film transistor, a method of manufacturing the same, and a flat panel display device including the thin film transistor. The thin film transistor includes: a gate electrode; source and drain electrodes insulated from the gate electrode; an organic semiconductor layer that is insulated from the gate...

20060169976 - Semiconductor device: A semiconductor device comprises: a first semiconductor chip having a first MIS transistor of a first conductivity type and a second semiconductor chip having a second MIS transistor of the first conductivity type. The first MIS transistor has a source electrode formed on a first face. The second MIS transistor...

20060169977 - Liquid detection end effector sensor and method of using the same: Liquid detection sensors are attached to both sides of a robotic arm end effector of a semiconductor wafer process system. The sensor mechanism or probe is situated on the front side and backside of the end effector, designed with electrical lines that are traced onto a polyester base material. The...

20060169978 - Solid-state image pickup device and method for producing the same: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation...

20060169980 - Electrochromic display: An electrochromic display is disclosed which comprises an array-side substrate (10) wherein a TFT (14) and a pixel electrode (15) connected with the TFT (14) are formed, a color filter-side substrate (50) wherein a counter electrode (53) is formed, and an electrolyte layer (80) injected between the array-side substrate (10)...

20060169979 - Light emitting device and electronic device: The invention is made in view of solving problems in reduction in yield and an aperture ratio in accordance with an increase in the number of transistors which form a pixel, increase in power consumption for holding predetermined luminance to provide a light emitting device having a noble pixel configuration....

20060169981 - Thin film transistor array panel for organic electro luminescent display: The light emitting efficiency of an organic electro luminance substance depends on the selected electro luminescent (EL) material. Each color of organic EL substances has a different light emitting efficiency from another color. The current source of a pixel having an EL layer with good light emitting efficiency is shared...

20060169982 - Liquid crystal display with noise filtering capacitor: A liquid crystal display device includes a first substrate, a second substrate opposite to the first substrate, a liquid crystal layer sandwiched between the first and second substrate. One of the substrates (3) includes a first metal layer (31), an insulative layer (32), and a second metal layer (33) disposed...

20060169983 - Active matrix substrate and its manufacturing method: An active matrix substrate with a high aperture ratio is provided, which is capable of preventing electrical short circuits between pixel electrodes and auxiliary capacitive electrodes. Gate lines and auxiliary capacitive electrodes are formed on an insulated substrate. The auxiliary capacitive electrodes have holes formed therethrough. To cover the gate...

20060169984 - Thin film transistor array panel: A thin film transistor array panel is provided. The array panel includes a storage capacitance that is substantially uniform, and allows for a relatively large capacitance in a relatively small area. In some embodiments, the panel includes: a substrate; a plurality of semiconductor regions on the substrate, including a plurality...

20060169985 - Electrode for p-type sic: A p-type electrode containing a first electrode material exhibiting an eutectic reaction at a temperature of 600° C. or lower, and a second electrode material of aluminum (Al)....

20060169989 - Deformable organic devices: A device is provided. The device includes a substrate, an inorganic layer disposed over the substrate, and an organic layer disposed on the inorganic conductive or semiconductive layer, such that the organic layer is in direct physical contact with the inorganic conductive or semiconductive layer. The substrate is deformed such...

20060169990 - Group iii nitride-based compound semiconductor light-emitting device and method for producing the same: The invention relates to a Group III nitride-based compound semiconductor light-emitting device having a well layer, a first layer formed on one surface of the well layer, a second layer formed on the other surface of the well layer, a first region provided in the vicinity of the interface between...

20060169986 - Red emitting phosphor materials for use in led and lcd applications: Phosphor compositions including those having the formulas A2-xEuxW1-yMoyO6, where A is selected from Y, Gd, Lu, La, and combinations thereof; and where 0.5≦x≦1.0, 0.01≦y≦1.0; MmOnX, wherein M is selected from the group of Sc, Y, a lanthanide, an alkali earth metal and mixtures thereof; X is a halogen; 1≦m≦3; and...

20060169987 - Semiconductor device and manufacturing method thereof: A high quality silicon carbide (SiC) layer being substantially lower in threading dislocation density than a prior layer is formed on silicon (Si) substrate. A semiconductor device is fabricated in such a way that a semiconductor buffer layer containing Si in part and being higher in defect density than a...

20060169988 - Single crystal wafer for semiconductor laser: A surface of the single crystal wafer 5 for semiconductor laser having an orientation flat formed by cleaving is polished by using the abrasive cloth 8 with high hardness under the optimized pressure for pushing the wafer and polishing rate, such that the polishing rate on the whole surface of...

20060169991 - Light emitting diode: An LED including a substrate having a pair of terminal electrodes, at least one LED element mounted on the substrate, a frame disposed on the substrate, holes provided in the substrate, concave portions provided in positions of the frame facing the holes, and a pair of conductive elastic members provided...

20060169992 - Light receiving or light emitting modular sheet and process for producing the same: A light receiving or light emitting modular sheet having a plurality of spherical elements arranged in matrix. It is constituted only of acceptable spherical elements and photoelectric conversion efficiency therof is enhanced. The light receiving modular sheet (1) comprises a plurality of spherical solar cell elements (2) arranged in matrix,...

20060169993 - Micro-led based high voltage ac/dc indicator lamp: An AC/DC indicator lamp based on an array of micro-LEDs may be powered by a standard high voltage AC or DC power source. The indicator lamp has a low power consumption. The micro-LEDs are serially connected on a substrate with the total device area and power consumption compatible with a...

20060169994 - Light emitting device and manufacture method thereof: A flip-chip LED including a light emitting structure, a first dielectric layer, a first metal layer, a second metal layer, and a second dielectric layer is provided. The light emitting structure includes a first conductive layer, an active layer, and a second conductive layer. The active layer is disposed on...

20060169996 - Crystalline composition, wafer, and semi-conductor structure: A crystalline composition is provided. The crystalline composition may include gallium and nitrogen; and the crystalline composition may have an infrared absorption peak at about 3175 cm−1, with an absorbance per unit thickness of greater than about 0.01 cm−1....

20060169995 - Semiconductor light emitting device: A semiconductor light emitting device includes a hetero-configuration having an active layer, a first clad layer, and a second clad layer, the active layer being interposed between the clad layers. The active layer emits light when charge carriers are injected. The first and second clad layers keep the injected charge...

20060169997 - Semiconductor light-emitting device: A semiconductor light-emitting device is provided. The semiconductor light-emitting device includes a laminated semiconductor structure portion composed of at least a first conductivity type first cladding layer, an active layer and a second conductivity type second cladding layer, wherein an outer peripheral surface of this laminated semiconductor structure portion is...

20060169998 - Red line emitting phosphor materials for use in led applications: Light emitting devices including a light source and a phosphor material including a complex fluoride phosphor activated with Mn4+ which may comprise at least one of (1) A2[MF6]:Mn4+, where A is selected from Li, Na, K, Rb, Cs, NH4, and combinations thereof; and where M is selected from Ge, Si,...

20060169999 - Led package frame and led package having the same: The invention relates to an LED package frame and an LED package incorporating the same. The LED package frame comprises an LED chip; and a heat conductive member made of a lump of high heat conductivity material. The heat conductive member has a receiving part at a lateral portion, and...

20060170000 - Nitride-based compound semiconductor substrate and method for fabricating the same: A nitride-based compound semiconductor substrate mainly used for an epitaxial growth of a nitride semiconductor and a method for fabricating the same are disclosed. The nitride-based compound semiconductor substrate has a composition of AlxGa1-xN (0<x<1), a principal plane of C face, an area of 2 cm2 or more, and a...

20060170001 - Semiconductor light-emitting device: A semiconductor light-emitting device is provided. In an InGaN-based semiconductor light-emitting device including an Ag electrode, a semiconductor layer on the contact side of at least the Ag electrode is a dislocation semiconductor layer of which dislocation density is selected to be less than 1×107 (1/cm2) and thereby short-circuit caused...

20060170002 - Adjustable ccd charge splitter: An adjustable charge coupled device (CCD) charge splitter includes a channel control structure and an associated plurality of output channels. Control signals applied to the channel control structure determine an amount of charge, which passes into each one of the plurality of output channels....

20060170003 - Nitride semiconductor device: A multi-layered structure in which a p-3C-SiC layer 102 is formed above a p-Si substrate 101 is formed, above which an I-GaN layer (channel layer) 103, an n-AlGaN layer (barrier layer) 104 are formed. A source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above...

20060170004 - Semiconductor device and manufacturing method of the same: A bipolar transistor for communication apparatus having improved power gain and high frequency output characteristics is described. The bipolar transistor includes an outer base layer connecting an intrinsic base region with a base electrode, with a planar shape thereof being in a U form. The long sides of the collector...

20060170005 - Semiconductor device and method of manufacturing the same: Provided are a semiconductor device, adapted to be capable of fabricating the device having improved resistance characteristic by decreasing dishing of solid phase epitaxy (SPE) silicon during planarization in a landing plug forming process via use of SPE silicon, and a method of manufacturing the same. The method of manufacturing...

20060170006 - Semiconductor device and method of manufacturing the same: An MIS transistor includes a gate electrode located to intersect a device region of a semiconductor substrate isolated by a device isolation region, and source and drain regions formed in the semiconductor substrate at both sides of the gate electrode region and elevated source and drain located above the source...

20060170007 - Solid-state image sensor: A solid-state image sensor capable of suppressing color mixture while suppressing increase of load capacitances of transfer gates and a short circuit between two adjacent transfer gates is provided. This solid-state image sensor comprises a plurality of transfer gates and a shielding material line blocking light incident from above a...

20060170008 - Cold cathode field emission display: s

20060170009 - Solid state image sensing device and production method therefor, and method of driving solid state image sensing device: The solid-state imaging device has such a structure that an electrode 8 for reading a signal charge is provided on one side of a light-receiving sensor portion 11 constituting a pixel; a predetermined voltage signal V is applied to a light-shielding film 9 formed to cover an image pickup area...

20060170010 - Electrical component and switching mechanism: Electrical component and switching mechanism with the component The invention relates to an electrical component with a sequence of ceramic layers (1, 11, 12) stacked one on top of the other that form a base body with electrode layers (21, 22, 23, 24, 25) arranged between the ceramic layers (1,...

20060170011 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a gate-all-around MOSFET structure comprises a first semiconductor layer which is formed on a support substrate and which has a recess formed on a surface thereof, a second semiconductor layer formed on the first semiconductor layer and which has a part thereof formed to cross over...

20060170014 - Capacitive micromachined ultrasound transducer fabricated with epitaxial silicon membrane: A capacitive micromachined ultrasound transducer (cMUT) cell is presented. The cMUT cell includes a lower electrode. Furthermore, the cMUT cell includes a diaphragm disposed adjacent to the lower electrode such that a gap having a first gap width is formed between the diaphragm and the lower electrode, wherein the diaphragm...

20060170012 - Micromechanical component and suitable method for its manufacture: A micromechanical component having a substrate conductive in at least some regions; an elastically deflectable diaphragm, which is conductive in at least some regions, arches over a front side of the substrate, and is electrically insulated from the substrate, the diaphragm having an inner region (I; I′) and an edge...

20060170013 - Zno group epitaxial semiconductor device and its manufacture: A method for manufacturing a semiconductor device includes the steps of: (a) preparing a non-polar single crystal substrate; (b) epitaxially growing an MgO layer on the non-polar single crystal substrate to a thickness of 3 nm or thicker to have rocksalt structure at a substrate temperature of 500° C. to...

20060170015 - High temperature-stable sensor: A high temperature-stable sensor is provided in which electrodes on a substrate or an insulation layer are in contact with a sensitive layer, wherein the electrodes have platinum, rhodium, or iridium or an electrically conductive oxide layer. For this purpose, an intermediate product is provided as a platform chip, which...

20060170016 - Asymmetric spacers and asymmetric source/drain extension layers: A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures...

20060170017 - Semiconductor device and manufacturing method thereof: A method of manufacturing a semiconductor device includes forming a semiconductor layer containing a semiconductor material having a first oxide-generating Gibbs free energy required to become an oxide; forming a first material for a gate insulator on the semiconductor layer, said first material containing an element having a second oxide-generating...

20060170018 - Solid-state imaging device and manufacturing method for the same: A solid-state imaging device includes a semiconductor substrate including: a plurality of light-receptive portions that are arranged one-dimensionally or two-dimensionally; a vertical transfer portion that transfers signal electric charge read out from the light-receptive portions in a vertical direction; a horizontal transfer portion that transfers the signal electric charge transferred...

20060170021 - Ferroelectric capacitor: A ferroelectric capacitor including a lower electrode, a ferroelectric layer and an upper electrode. A part of at least any one of the lower and upper electrodes is formed of a material selected from the group consisting of TiOx, TaOx, ReOx, WOx, IrO2, PtO2, RuOx, PdOx, and OsOx....

20060170020 - Semiconductor memory device and method for fabricating the same: A semiconductor memory device includes: an insulating layer formed on a semiconductor substrate; a first plug formed inside a first hole formed in the insulating layer; an insulative first hydrogen barrier layer formed on the insulating layer and having a second hole communicating with the first hole; a second plug...

20060170019 - Semiconductor storage device and manufacturing method for the same: There is provided a semiconductor storage device comprising a ferroelectric capacitor superior in barrier capability against penetration of hydrogen from all directions including a transverse direction. The device comprises a transistor formed on a semiconductor substrate, the ferroelectric capacitor formed above the transistor and including a lower electrode, a ferroelectric...

20060170023 - Semiconductor integrated circuit device: To provide a semiconductor integrated circuit device capable of increasing a capacitor capacitance. A semiconductor integrated circuit device according to an embodiment of the present invention includes: a circuit element formed on a semiconductor substrate; and capacitors formed on the semiconductor substrate and including: a lower capacitance electrode formed of...

20060170022 - Silicon molecular hybrid storage cell:

20060170024 - Method of forming a mim capacitor for cu beol application: The present invention relates generally to integrated circuits, and particularly, but not by way of limitation, metal-insulator-metal (MIM) capacitors formed within a trench located within a metallization layer and in particular to MIM capacitors for Cu BEOL semiconductor devices....

20060170025 - Planarization of metal container structures: A conductive material is provided in an opening formed in an insulative material. The process involves first forming a conductive material over at least a portion of the opening and over at least a portion of the insulative material which is outside of the opening. Next, a metal-containing fill material...

20060170026 - Non-volatile memory and fabricating method and operating method thereof: A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are...

20060170028 - Non-volatile memory device, methods of fabricating and operating the same: A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through...

20060170027 - Nonvolatile memory device made of resistance material and method of fabricating the same: A nonvolatile memory device using a resistance material and a method of fabricating the same are provided. The nonvolatile memory device includes a switching element, and a data storage part electrically connected to the switching element. In the data storage part, a lower electrode is connected to the switching element,...

20060170029 - Novel process for erase improvement in a non-volatile memory device: A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate wherein the first mask layer has a plurality of openings in the cell region. Portions of the polycrystalline silicon...

20060170030 - Semiconductor device: A semiconductor device includes: a semiconductor layer; a first area and a second area which are demarcated by a separation insulating layer provided on the semiconductor layer; a nonvolatile memory provided on the first area; a plurality of MOS transistors provided on the second area; a first interlayer insulating layer...

20060170031 - Semiconductor device having transistor with vertical gate electrode and method of fabricating the same: A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the...

20060170032 - Scalable flash/nv structures and devices with extended endurance: Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K...

20060170034 - Non-volatile memory device and method of manufacturing the same: Provided are a non-volatile memory device having an improved electric characteristic and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a substrate having a sloped portion formed therein, a first gate electrode pattern having a stacked structure in which an electric charge tunneling layer...

20060170033 - Nonvolatile memory device and method of manufacturing the same: A nonvolatile memory device and a method of manufacturing the same are provided. The nonvolatile memory device includes a semiconductor substrate on which a source region, a drain region, and a channel region are formed, a silicon oxide layer formed on the channel region, a transition metal oxide layer having...

20060170035 - Semiconductor device: A plurality of nonvolatile memory cells that constitute a nonvolatile memory are disposed in array form. Selection MIS•FETs for memory cell selection are electrically connected every bits. Each of the nonvolatile memory cells has a MIS•FET for writing data, a MIS•FET for reading data, and a capacitance section. Gate electrodes...

20060170036 - Method of fabricating semiconductor device containing dielectrically isolated pn junction for enhanced breakdown characteristics: A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and...

20060170039 - Buried channel type transistor having a trench gate and method of manufacturing the same: In a method of manufacturing a buried channel type transistor, a trench is formed at a surface portion of a substrate. A first and a second threshold voltage control regions are formed at portions of the substrate beneath a bottom face of the trench and adjacent to a sidewall of...

20060170038 - Non-volatile memory and manufacturing and operating method thereof: A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A plurality of...

20060170037 - Vertical type semiconductor device: In a vertical type MOSFET device having a super junction structure, in which a N conductive type column region (2) and a P conductive type column region (3) are alternately aligned, regarding to a distance between a terminal end (17) of an active region (13) and a terminal end (16)...

20060170040 - Semiconductor device, semiconductor integrated circuit device, and semiconductor device fabrication method: A semiconductor device that can operate at plural kinds of power supply voltages. A pocket region which is adjacent to a source region and the conduction type of which is the same as that of a channel region formed between the source region and a drain region is formed. By...

20060170041 - Mosfet and optical coupling device having the same: In various aspects, a MOSFET may include a semiconductor region of a first conductivity type; a first semiconductor region of a second conductivity type provided in the semiconductor region; a second semiconductor region of the first conductivity type provided in the semiconductor region, the second semiconductor region having a higher...

20060170042 - Resonant gate drive circuits: A resonate gate drive circuit for driving at least one power switching devices recovers energy loss for charging and discharging the input capacitance of the power switching devices. The gate drive circuit charging and discharging the gate capacitor with a high level current, so the switching loss of the power...

20060170043 - Resonant gate drive circuits: A resonate gate drive circuit for driving at least one power switching device recovers energy loss for charging and discharging the gate capacitance of the power switching devices. The gate drive circuit uses a current source to charge and discharge the gate capacitance with a high current, reducing the switching...

20060170050 - Fully depleted silicon-on-insulator cmos logic: A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects....

20060170049 - Mosfet: In various aspects, a MOSFET may include an active region of a first conductivity type provided on an insulating layer, the active region having a first portion and a second portion, the first portion being thicker than the second portion; a base region of the first conductivity type provided on...

20060170044 - One-transistor random access memory technology integrated with silicon-on-insulator process: An one-transistor random access memory device integrated on a silicon-on-insulator (SOI) substrate has a capacitor structure buried in at least part of a capacitor trench in the SOI substrate, and a gate structure formed on the SOI substrate. A top electrode the capacitor structure is formed simultaneously with and of...

20060170051 - Semiconductor circuit constructions: The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first semiconductor substrate has a semiconductive material projection extending therefrom, and the second semiconductor substrate has...

20060170046 - Semiconductor device and manufacturing method thereof: A method for manufacturing a semiconductor device, including the steps of: forming a shielding film 38 on a first insulating film 37; sequentially forming a second insulating film 39 and an amorphous semiconductor film 40 on the shielding film 38; melting the amorphous semiconductor film 40 at least in portions...

20060170047 - Semiconductor device and method of manufacturing the same: A semiconductor device according to an embodiment of the present invention comprises a semiconductor substrate; and a plurality of MOSFETs which are formed on the semiconductor substrate, are the same conductivity type, and have gate insulating films of the same insulating material, with each gate insulating film having any one...

20060170045 - Semiconductor method and device with mixed orientation substrate: A semiconductor device includes a semiconductor body having semiconductor material of a first crystal orientation. A first transistor is formed in the semiconductor material of the first crystal orientation. An insulating layer overlies portions of the semiconductor body and a semiconductor layer overlies the insulating layer. The semiconductor layer has...

20060170048 - Thin film transistor array substrate and fabrication method thereof: A thin film transistor array substrate is disclosed. A gate electrode is disposed overlying a substrate. A gate dielectric layer covers the substrate and the gate electrode. A semiconductor layer is disposed overlying the gate dielectric layer, wherein the semiconductor layer comprises a channel. A source electrode electrically connects a...

20060170052 - Semiconductor device, method of manufacture thereof and semiconductor integrated circuit: An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth...

20060170053 - Accumulation mode multiple gate transistor: A transistor (1) having, a fin (2) and a gate electrode (3) extending on more than one side of the fin (2) to comprise more than one gate (9) of the transistor (1), and a dopant in each of a source (6), drain (7) and a channel region (8), comprising...

20060170054 - Device having a low-voltage trigger element: An electronic device having an LV-well element trigger structure that reduces the effective snapback trigger voltage in MOS drivers or ESD protection devices. A reduced triggering voltage facilitates multi-finger turn-on and thus uniform current flow and/or helps to avoid competitive triggering issues....

20060170055 - Drain extended mos transistors with multiple capacitors and methods of fabrication: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A...

20060170056 - Drain extended pmos transistor with increased breakdown voltage: A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region (125) of a p-type upper epitaxial layer (106), where the region (125) of...

20060170057 - Semiconductor device with omega gate and method for fabricating a semiconductor device: A substrate has an active region divided into storage node contact junction regions, channel regions and a bit line contact junction region. Device isolation layers are formed in the substrate isolating the active region from a neighboring active region Recess patterns are formed each in a trench structure and extending...

20060170058 - Amorphous carbon contact film for contact hole etch process: A semiconductor device including a contact etch stop layer and contact hole formation method for reduced underlying material loss and improved device performance, the method including providing a semiconductor substrate including an active region including a CMOS device, STI structures, and metal silicide regions; forming a fluorine doped amorphous carbon...

20060170059 - Semiconductor device having step gates and method for fabricating the same: The semiconductor device includes a substrate including a first active region and a second active region having a greater height than that of the first active region. A gate pattern has a step structure, which is formed on a border region between the first active region and the second active...

20060170060 - Semiconductor structure with high-voltage sustaining capability and fabrication method of the same: A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region...

20060170061 - Pulse output circuit, shift register, and display device: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential...

20060170062 - Self-aligned semiconductor contact structures and methods for fabricating the same: A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window...

20060170063 - Semiconductor memory device and corresponding programming method: A semiconductor cell includes, within a substrate region, four active zones that are mutually laterally isolated, the first active zone to be connected to a first voltage, the second active zone, of an opposite type of conductivity to that of the first active zone, to be connected to a second...

20060170064 - Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof: A semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layers; a first contact layer connected to one of the diffusion layer of the memory cell; a second contact layer connected to...

20060170065 - Semiconductor device and method for fabricating the same: In a semiconductor device according to the present invention, the power source voltage Vdd1 of a core transistor Tr1, the power source voltage Vdd2 of an I/O transistor Tr2, and the power source voltage Vdd3 of an I/O transistor Tr3 satisfy Vdd1<Vdd2<Vdd3. In a method for fabricating the semiconductor device,...

20060170067 - Electronic device, semiconductor device and manufacturing method thereof: The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the...

20060170066 - Hybrid-fet and its application as sram: A semiconductor device (51) is provided herein. The semiconductor device comprises (a) a substrate (57), a semiconductor layer (53) disposed on said substrate and comprising a horizontal region (54) and a fin which extends above, and is disposed adjacent to, said horizontal region, and (c) at least one channel region...

20060170068 - Magnetoelectronic devices utilizing protective capping layers and methods of fabricating the same: Magnetoelectronic device structures and methods for fabricating the same are provided. One method comprises forming a first and a second conductor. The first conductor is electrically coupled to an interconnect stack. A first insulating layer is deposited overlying the first conductor and the second conductor. A via is etched to...

20060170069 - Image sensor and method for forming the same: A method for forming an image sensor is provided. The method includes providing a semiconductor substrate having a pixel region and a peripheral circuit region, forming a photoelectric transformation section at the semiconductor substrate of the pixel region, forming a plurality of interlayer dielectrics over the semiconductor substrate with interconnections...

20060170070 - Cover, in particular for inscription fields: The invention relates to a cover, in particular for covering inscription fields, comprising a cover element which is provided for insertion into a base body which is in the form of a holder, with at least one hooking-in element being provided on the cover element which can be engaged with...

20060170072 - Circuit board and semiconductor device: A semiconductor device, includes: a semiconductor substrate; a multilayered interconnect structure formed on the semiconductor substrate; a terminal for flip-chip packaging arranged on the surface of the multilayered interconnect structure; and a spiral inductor formed to enclose the terminal for flip-chip packaging, in a plan view, which is not electrically...

20060170071 - Circuit substrate structure and circuit apparatus: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with:...

20060170073 - Capacitor with high breakdown field: The capacitor is a thin-film capacitor comprising two metal electrodes separated by a dielectric. The dielectric is formed by superposition of at least two sub-layers of preferably perovskite-based dielectric material. Two adjacent superposed dielectric sub-layers are separated by an electrically insulated metal intermediate layer, for example made of platinum. Using...

20060170074 - Semiconductor device: A semiconductor substrate includes an element isolation film arranged in a semiconductor substrate. An active region surrounded by the element isolation film functions as a collector layer. A conductive layer, which includes an alloy layer, is arranged on the active region. An emitter layer is arranged on the conductive layer....

20060170075 - Semiconductor device: A semiconductor device, including: a semiconductor substrate of the first conductivity type having a first surface and a second surface; a base region of the second conductivity type formed on the first surface of the semiconductor substrate; a guard ring region of the second conductivity type formed around the base...

20060170076 - Apparatus, system, and method for reducing integrated circuit peeling: An apparatus, system, and method are disclosed for reducing integrated circuit peeling. This invention reduces integrated circuit peeling by providing a wafer with a solventphilic layer and removing unwanted film using a solvent that is philic to the solventphilic layer. In one embodiment, a boundary is provided to reduce the...

20060170077 - Substrate having pattern and method for manufacturing the same, and semiconductor device and method for manufacturing the same: The present invention provides a method for manufacturing a substrate having a pattern that is capable of controlling the distance between adjacent film patterns, and also provides a method for manufacturing a substrate, particularly, having a pattern with a narrow width and a thickness that is capable of controlling the...

20060170078 - Silicon member and method of manufacturing the same: There is provided a silicon member that can prevent the resistivity of a member itself from varying in a semiconductor manufacturing process, in particular, in a plasma processing process, thereby making wafer processing uniform and being not an impurity contamination source to a wafer to be processed, and a method...

20060170082 - Chip packaging structure adapted to reduce electromagnetic interference: A chip packaging structure adapted to reduce EMI includes a chip having contacts provided on one side thereof, and a leadframe having a plurality of leads arranged in a predetermined manner and provided at a bottom side with a conducting protrusion each for electrically connecting to external elements. The leadframe...

20060170079 - Integrated circuit device having encapsulant dam with chamfered edge: An integrated circuit device is provided having a substrate, at least one integrated circuit element and a leadframe. The integrated circuit element and the leadframe are disposed on the substrate. The leadframe has at least one lead and at least one encapsulant dam disposed on the at least one lead....

20060170081 - Method and apparatus for packaging an electronic chip: An electronic packaging combines features of a MAP (molded array package) and a lead frame package. The package includes an electrically conductive substrate somewhat like a lead frame package but defines a grid of conductive pads rather than a multiplicity of leads as is common with a lead frame package....

20060170084 - Semiconductor device and a method of manufacturing the same: A memory card containing a resin sealed stacking of plural semiconductor chips which are rear surface mounted over a main surface of a base substrate, the rear surface of the substrate being provided with external connection terminals. The relatively lower ones of the stacked semiconductor chips include a memory circuit...

20060170080 - Semiconductor device having directly attached heat spreader: An apparatus consisting of a leadframe (301) and a metallic heat spreader (310). The leadframe, made of a planar metal sheet, includes a plurality of non-coplanar members (312) operable as mechanical couplers configured to grip inserted objects. The heat spreader has a central pad (310) suitable for mounting a heat-generating...

20060170083 - Side view led package having lead frame structure designed to improve resin flow: The invention relates to a side view LED package in use with an LCD backlight unit. The side view LED package comprises: an LED chip; and a strip-shaped lead frame having a toothed structure formed in a lateral edge thereof. The LED chip is mounted on a surface of the...

20060170085 - Semiconductor device and manufacturing method thereof: A semiconductor device such as a COF or the like is provided on a semiconductor chip on a film-like shaped flexile wiring substrate on which a wiring pattern is formed. Between the semiconductor chip and the flexile wiring substrate, a sealing resin is filled for protecting the semiconductor chip. In...

20060170087 - Semiconductor device: A semiconductor device according to the present invention includes a substrate having interconnections thereon, a first semiconductor chip mounted on the substrate such that the device formation surface thereof is faced to the substrate and a second semiconductor chip mounted on the first semiconductor chip, wherein an interconnection layer is...

20060170086 - Semiconductor package and method of manufacturing the same: Disclosed herein are a semiconductor package used in digital optical instruments and a method of manufacturing the same. The semiconductor package comprises a wafer made of a silicon material and having pad electrodes formed at one side surface thereof, an IR filter attached on the pad electrodes of the wafer...

20060170089 - Electronic device and method for fabricating the same: The electronic device comprises a first substrate 10 with an electric circuit element formed in a predetermined region of one primary surface, a second substrate 12 formed, opposed to said one primary surface of the first substrate 10, sealing portions 26, 40 formed between the first substrate 10 and the...

20060170091 - Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-down configuration....

20060170088 - Spacer structures for semiconductor package devices: Disclosed are novel spacer structures for stacked semiconductor package devices. In addition, methods of manufacturing spacers and stacked semiconductor package devices having such spacers are also disclosed. In one embodiment, a spacer includes a first mounting surface couplable to a longitudinal face of a first substrate, where the first mounting...

20060170090 - Stacked type semiconductor device and method of fabricating stacked type semiconductor device: A stacked type semiconductor device includes semiconductor devices, interposers by which the semiconductor devices are stacked, the interposers having electrodes provided on sides thereof, and a connection substrate connecting the electrodes together. The electrodes provided on the sides of the interposers may be connected to the connection substrate by one...

20060170092 - Semiconductor package system with cavity substrate: A semiconductor package system is provided including providing a cavity substrate having a cavity provided therein, attaching a metal die pad to the cavity substrate, attaching a semiconductor die in the cavity to the metal die pad, and attaching solder connectors to the cavity substrate for connection on the system...

20060170093 - Flip chip interconnection pad layout: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate...

20060170094 - Semiconductor package integral heat spreader: An integral heat spreader is disclosed wherein its physical characteristics are modified in regions between adjacent semiconductor devices. The modification improves the reliability of the semiconductor devices by reducing stiffness of the integral heat spreader....

20060170095 - Device package: Device packages often include walls build on a heat sink that surrounds a device die that thermally interacts with the heat sink. Use of raised or depressed feature on said heat sink that contacts the walls improves the cohesiveness of the package. By appropriately positioning these features contaminant infusion into...

20060170096 - Chip scale package and method for manufacturing the same: A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned...

20060170098 - Module structure having embedded chips: A module structure having embedded chips mainly comprises a dielectric layer, at least a semiconductor chip embedded in the dielectric layer, and at least a circuit structure formed on the surface of the dielectric layer, the circuit structure electrically connected to the semiconductor chip via a plurality of conductive structures...

20060170097 - Printed wires arrangement for in-line memory (imm) module: An inline memory module (IMM) architecture may include: a printed circuit board (PCB); a first array of memory devices on a first side of the PCB; a second array of memory devices on a second side of the PCB; at least some of the memory devices of the first array...

20060170099 - Transistor-level signal cutting method and structure: A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of the modifiable circuit structure, the interconnect portions, and the vias provide a...

20060170100 - Routing design to minimize electromigration damage to solder bumps: A novel pad structure for an integrated circuit component that utilizes a bump interconnect for connection to other integrated circuit components that produces a relatively uniform current distribution within the bump of the bump interconnect is presented. The pad structure includes an inner pad implemented on an inner conductive layer...

20060170102 - Bump structure of semiconductor device and method of manufacturing the same: In connection with a bump of a semiconductor device and a manufacturing method thereof, a groove is formed in a bump pad region of a semiconductor substrate. An under bump metal layer is then formed in the groove, and a lower end portion of the bump fills the groove on...

20060170101 - Low thermal resistance package: Techniques for arranging ball grid arrays for producing low thermal resistance packages. One embodiment is for a ball grid array package that comprises a substrate, the substrate having a top surface and a bottom surface. A plurality of thermal balls are coupled to the bottom surface of the substrate, and...

20060170103 - Semiconductor device and method of manufacturing the same: Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the inner surface of the opening, a diffusion barrier layer formed on the...

20060170104 - Method and structure for defect monitoring of semiconductor devices using power bus wiring grids: A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first...

20060170105 - Semiconductor device featuring probe area definition mark for defining probe area in electrode pad, and proof test system for proving proper contact of test probe with probe area: In a semiconductor device including a semiconductor substrate, a multi-layered wiring structure is formed on the semiconductor substrate, and an electrode pad is formed on the multi-layered wiring structure. There is a probe area definition mark element that defines a probe area in the electrode pad, with which a test...

20060170106 - Dual damascene with via liner: A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in the first dielectric insulator; lining the opening with a...

20060170107 - Semiconductor device preventing electrical short and method of manufacturing the same: A semiconductor device capable of preventing an electrical short between contacts and their adjacent contact pads and a method of manufacturing the same are provided. A first interlayer insulating layer is formed on the semiconductor substrate including the active region. Contact pads pass through the first interlayer insulating layer and...

20060170108 - Semiconductor device: Mechanical strength and moisture resistance of a multilayer interconnect structure is to be improved. A semiconductor device includes a circuit region and a seal ring region formed around the circuit region, on a semiconductor substrate. The seal ring region includes a plurality of interconnect layers including interconnect lines and a...

20060170109 - Semiconductor device: A semiconductor device is disclosed, which includes a first interlayer insulating film, a lower-layer interconnection in a first groove in the first film, a second interlayer insulating film over the first film, having a normal via hole opening to the lower-layer interconnection, a normal plug in the normal hole, a...

20060170110 - Through-substrate interconnect structures and assemblies: Through-substrate interconnect structures and assemblies are disclosed. A substrate includes at least one via passing therethrough. The via may have an enlarged central portion, and one or more end portions which taper to smaller end surfaces. The one or more via end portions may be trapezoidal in shape. The one...

20060170111 - Semiconductor device, electronic device, and method of manufacturing semiconductor device: Conductive layers having knots are adjacently formed with uniform distance therebetween. Droplets of the conductive layers are discharged to stagger centers of the droplets in a length direction of wirings so that the centers of the discharged droplets are not on the same line in a line width direction between...

20060170112 - Semiconductor device and method of manufacturing thereof: A connection method for materializing a high-performance semiconductor system which is small-sized and high dense, is capable to three-dimensionally connecting a plurality of different kinds of semiconductor chips through piercing electrodes with shortest wiring lengths. The connection method enables high-speed operation with low noise, so as to obtain reliable and...

20060170113 - Semiconductor device: A technology providing an improvement in the durability in the condition of changing the temperature, while ensuring characteristics such as the applicability to applications utilizing larger electric current, lower resistance and the like can be achieved. A semiconductor device 100 includes a ceramic multiple-layered interconnect substrate 120, a silicon chip...

20060170114 - Novel method for copper wafer wire bonding: A method of bonding a conductive wire on copper pad is presented. A passivation layer is formed on a copper pad. The passivation layer has an opening through which at least a portion of the copper pad is exposed. A nickel-copper-phosphorous (Ni—Cu—P) layer is formed on the copper pad by...

20060170115 - Means of mounting for electronic components, arrangement and procedure: A means of attachment for electrically contacting electronic components is disclosed. The means of attachment includes a carrier element and a number of elongated connecting elements. Each of the connecting elements is arranged on the carrier element and has an elongated body, which protrudes from the carrier element. Each of...

20060170117 - Semiconductor device and method for fabricating the same: A semiconductor device includes a transistor of a first conductivity type and a transistor of a second conductivity type. The transistor of the first conductivity type includes a first gate portion formed on a first region of a semiconductor substrate, a first sidewall formed on each side face of the...

20060170116 - Semiconductor device with asymmetric transistor and method for fabricating the same: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over...