Active solid-state devices (e.g., transistors, solid-state diodes) inventions 07/06

20060163553 - Phase change memory and fabricating method thereof: A phase change memory including a phase change layer, a first electrode, and a porous dielectric layer formed with a plurality of pores. The porous dielectric layer is formed between the phase change layer and the first electrode. Therefore, the phase change layer may make contact with the first electrode...

20060163554 - Electric device comprising phase change material: The electric device (1, 100) comprises a resistor (36, 250) comprising a phase change material which is able to be in a first phase and in a second phase. The resistor (36, 250) has an electrical resistance which has a first value when the phase change material is in the...

20060163555 - Led and a lighting apparatus using the led: Disclosed herein is a LED and a lighting apparatus, which employs a LED as a light source of low power and high efficiency for an optical projection system. The lighting apparatus comprises a reflection part together with the LED, and enhances light emitting directionality of the LED, thereby generating parallel...

20060163556 - Refractive index variable device: A refractive index variable device has a structure including quantum dots dispersed in a solid matrix, each of the quantum dots comprising a combination of a negatively charged accepter and a positively charged atom, where the outermost electron shell of the positively charged atom is fully filled with electrons so...

20060163558 - Mos transistor with elevated source/drain structure: In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction...

20060163557 - Semiconductor device and fabrication process thereof: A p-channel MOS transistor includes a strained SOI substrate formed of a SiGe mixed crystal layer and a strained Si layer formed on the SiGe mixed crystal layer via an insulation film, a channel region being formed in the strained Si layer, a gate electrode formed on the strained Si...

20060163561 - Electronic device and method of manufacturing thereof: Provided is a filed-effect transistor with an organic semiconductor material showing ambipolar behaviour. Thereto, the organic semiconductor material enabling the ambipolar behaviour is a material with a small band gap....

20060163560 - Led and fabrication method thereof: Disclosed is a quantum-dot LED and fabrication method thereof. The quantum-dot LED includes: a substrate; a n-type semiconductor layer formed on the substrate; an insulator layer formed on the n-type semiconductor layer and provided with a plurality of holes; quantum dots formed by filling the holes; and a p-type semiconductor...

20060163565 - Method of manufacturing substrate, method of manufacturing organic electroluminescent display device using the method, and organic electroluminescent display device: A method of manufacturing an organic electroluminescent display device includes preparing an auxiliary substrate, which has a flat side; forming a first protective layer on the auxiliary substrate; forming an organic electroluminescent unit on the first protective layer; bonding a flexible main substrate onto the organic electroluminescent unit; and etching...

20060163563 - Method to form a thin film resistor: Embodiments of methods, apparatuses, devices, and/or systems for forming thin film resistor are described....

20060163562 - Multifluorinated conductor material for leds for improving the light outcoupling: Conductor material for LEDs for improving the light outcoupling, wherein the conductor material is selected from the group comprising hole conductor material, electron conductor material and/or emitter material, the conductor material comprises at least one conductive fluorinated organic substance having at least one fluorinated alkyl substituent, one fluorinated alkenyl substituent...

20060163559 - Organic thin film transistor and manufacturing method thereof: There is provided an organic thin film transistor comprising: an organic substrate; a gate electrode; a gate insulating film; an organic semiconductor film; a source electrode; and a drain electrode, and in the organic thin film transistor, an average surface roughness Ra of the gate electrode which is in contact...

20060163564 - Use of dithiocarbamate esters and bis-dithiocarbamate esters in the preparation of organic-inorganic nanocomposites: in which X is the central body of the molecule, FUNC1 and FUNC2 independently of each other are molecular groups introducing a dipole moment and/or capable of forming intermolecular and/or intramolecular hydrogen bonding networks, and CON 1 and CON 2 independently of each other are molecular groups binding to nanostructured...

20060163566 - Method for forming semiconductor film and use of semiconductor film: The present invention provides a process for forming a semiconductor film, comprising the steps of applying a semiconductor particle dispersion liquid to a substrate surface by spray coating in such a manner that the atomized droplets of the dispersion liquid discharged from the spray coater have a mean diameter of...

20060163567 - Semiconductor electrode, method of manufacturing the same, and solar cell employing the same: Provided are a continuous-phase semiconductor electrode that can provide better photoelectric conversion efficiency by improving a pathway for electron transport, a method of manufacturing the same, and a solar cell employing the same. The semiconductor electrode includes a transparent conductive electrode, formed on a substrate, including a metal or a...

20060163570 - Aerodynamic jetting of aerosolized fluids for fabrication of passive structures: Method and apparatus for direct writing of passive structures having a tolerance of 5% or less in one or more physical, electrical, chemical, or optical properties. The present apparatus is capable of extended deposition times. The apparatus may be configured for unassisted operation and uses sensors and feedback loops to...

20060163568 - Integration system and the method for operating the same: An integration system for obtaining a set of overlay offset parameters of a first process layer which is going to be formed in an assigned photolithography tool with an assigned mask and an assigned pre-tool. By using the integration system, the set of overlay offset parameters of the first process...

20060163572 - Semiconductor memory testing device and test method using the same: A test device for a semiconductor memory device includes a clock frequency multiplier, a data input buffer, a test data generator and a data output buffer. The clock frequency multiplier multiplies an external clock signal having a relatively low frequency provided from an external test device to generate an internal...

20060163571 - Test element group structures having 3 dimensional sram cell transistors: A test element group structure having 3-dimensional SRAM cell transistors includes a bulk metal-oxide-semiconductor (MOS) transistor formed at a semiconductor substrate and a first interlayer insulating layer covering the bulk MOS transistor. A lower thin film transistor is disposed on the first interlayer insulating layer, and the lower thin film...

20060163569 - Test structure of semiconductor device: A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate...

20060163573 - Method for preparing ball grid array substrates via use of a laser: A method of using a laser to remove surface contamination and oxidation from a ball grid array substrate. The laser etching can be configured to cover the entire substrate or pinpointed to the epoxy molding compound/solder resist (EMC/SR) interfaces. Additionally, a laser can be used to roughen the surface of...

20060163574 - Semiconductor device and manufacturing method thereof: By performing the formation of the pixel electrode 127, the source region 123 and the drain region 124 by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor can be...

20060163577 - Area sensor and display apparatus provided with an area sensor: An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the...

20060163576 - Semiconductor device: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be...

20060163580 - Semiconductor device and a method of manufacturing the same: To provide a technique required for purifying the interface between an active layer and an insulating film. On a substrate (101), a gate wiring (103) is formed and the surface thereof is covered with a gate oxide film (104). Then, a first insulating film (105a), a second insulating film (105b),...

20060163579 - Thin film transistor matrix device and method for fabricating the same: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin...

20060163578 - Thin film transistor substrate and liquid crystal display: A TFT substrate comprises a substrate, a gate electrode and a lower electrode of a capacitor formed thereon, a first insulating layer formed thereon, a channel layer above the gate electrode and a lower layer of an upper electrode of the capacitor, a channel protection layer formed on an intermediate...

20060163575 - Thin film transistor with microlens structures: A thin film transistor with a microlens. A metal gate is formed on a substrate. A gate dielectric covers the metal gate. A semiconductor layer is formed on the gate dielectric. Source/drain metal layers respectively overlap ends of the top surface of the semiconductor layer such that the semiconductor layer...

20060163581 - Fabrication of strained silicon film via implantation at elevated substrate temperatures: A strained-silicon film is disclosed. A silicon-germanium film is made by ion implantation of germanium into an epitaxial silicon layer, preferably at a temperature in the range of 200 C to 400 C. The wafer is annealed in situ or optionally after implantation. A silicon film is applied to the...

20060163583 - Semiconductor device, liquid crystal device, electronic apparatus, and method of manufacturing semiconductor device: A semiconductor device includes: a substrate; a plurality of island-shaped light shielding films formed on the substrate; a first insulating film formed between the plurality of light shielding films; a second insulating film formed on the first insulating film and the plurality of light shielding films; and semiconductor elements each...

20060163582 - Thin film transistor substrate and method for forming metal wire thereof: The present invention relates to a thin film transistor substrate and a metal wiring method thereof, more particularly to a thin film transistor substrate comprising self-assembled monolayers between the substrate and the metal wiring, and a metal wiring method thereof. Since a thin film transistor substrate of the present invention...

20060163584 - Boron-doped diamond semiconductor: First and second synthetic diamond regions are doped with boron. The second synthetic diamond region is doped with boron to a greater degree than the first synthetic diamond region, and in physical contact with the first synthetic diamond region. In a further example embodiment, the first and second synthetic diamond...

20060163586 - Led with current confinement structure and surface roughening: An LED having a p-type layer of material with an associated p-contact, an n-type layer of material with an associated n-contact and an active region between the p-type layer and the n-type layer, includes a confinement structure that is formed within one of the p-type layer of material and the...

20060163585 - Light-emitting semicoductor device and a method of manufacturing it: In layer structure 20 of a semiconductor laser of a surface emitting type, 21 and 24 represent an n-type contact layer made of n-type GaN and a p-layer made of p-type AlGaN, respectively. In the laser, an n-type DBR layer 22 made of n-type InGaN and a DBR layer 25...

20060163587 - Packaging designs for leds: Light-emitting devices, and related components, processes, systems and methods are disclosed....

20060163588 - Boron phosphide-based semiconductor light-emitting device and production method thereof: A boron phosphide-based semiconductor light-emitting device, comprising: a crystalline substrate; a first semiconductor layer formed on said crystalline substrate, said first semiconductor layer including a light-emitting layer, serving as a base layer and having a first region and a second region different from the first region; a boron phosphide-based semiconductor...

20060163589 - Heterogeneous integrated high voltage dc/ac light emitter: A single-chip integrated LED particularly adapted for direct use with a high voltage DC or AC power sources comprises a plurality of electrically isolated LEDs on a generally transparent substrate and bonded to electrically conductive elements on a thermally conductive mount. A reflective coating may be applied to the area...

20060163590 - Packaging designs for leds: Light-emitting devices, and related components, processes, systems and methods are disclosed....

20060163591 - Oled device: An organic light-emitting device (OLED) comprising an organic active region which emits electromagnetic radiation, a conversion material which converts a portion of the radiation into light of a certain spectral range, and a filter material which transmits said light....

20060163594 - High electron mobility devices: The present invention is directed to high frequency, high power or low noise devices such as low noise amplifiers, amplifiers operating at frequencies in the range of 1 GHz up to 400 GHz, radars, portable phones, satellite broadcasting or communication systems, or other devices and systems that use high electron...

20060163592 - Light emitting diode and fabricating method thereof: A light emitting diode and its fabricating method are disclosed. A light emitting diode epitaxy structure is formed on a substrate, and then the light emitting diode epitaxy structure is etched to form a recess. The recess is then filled with a transparent dielectric material. An adhesive layer is utilized...

20060163593 - Semiconductor light emitting device: A semiconductor light emitting device includes a hetero-configuration having an active layer, a first clad layer, and a second clad layer, the active layer being interposed between the clad layers. The active layer emits light when charge carriers are injected. The first and second clad layers keep the injected charge...

20060163595 - Light emitting device: A light emitting device having a transparent substrate, a light emitting stack, and a transparent adhesive layer is provided. The light emitting stack is disposed above the transparent substrate and comprises a diffusing surface. The transparent adhesive layer is disposed between the transparent substrate and the diffusing surface of the...

20060163597 - Light emitting device and method for manufacturing the same: It is an object of the present invention to provide a high-contrast light-emitting device without using a polarization plate. In particular, it is an object of the present invention to make contrast control simpler for a light-emitting device provided with a color filter. A light-emitting device according to the present...

20060163596 - Two dimensional light source using light emitting diode and liquid crystal display device using the two dimensional light source: A two-dimensional light source includes a base substrate having holes, wires disposed on a lower surface of the base substrate, a light emitting diode (LED) chip disposed on an upper surface of the base substrate, plugs that connect two electrodes of the LED chip to the wires through the holes,...

20060163600 - Chip component and method for producing a chip component: A chip component (1) includes a semiconductor body (2), in which at least one switchable element (6, 62) is arranged in a partial region (24) of the semiconductor body (2). The partial region (24) can be reached by light of at least one wavelength. Furthermore, a circuit (9) integrated into...

20060163599 - Light emitting diode and fabricating method thereof: A light emitting diode and the method of the same are provided. A light emitting diode epitaxy structure is formed on a substrate, and then the light emitting diode epitaxy structure is etched to form a recess. The recess is then filled with a transparent dielectric material. An ohmic contact...

20060163598 - Light emitting diode lamp module: An LED lamps module is provided. The LED lamp module includes a plurality of LED lamps, a plurality of electric wires and a plurality of moisture-resisting members. In one embodiment of the present invention, each LED lamp includes a substrate with a circuitry, at least one LED chip disposed on...

20060163601 - Lighting module and method the production thereof: An illumination module with at least one thin-film light emitting diode chip which is applied on a chip carrier having electrical connecting conductors and has a first and a second electrical connection side and also an epitaxially fabricated semiconductor layer sequence. The semiconductor layer sequence has an n-conducting semiconductor layer,...

20060163602 - Optical semiconductor device: An optical semiconductor device (A1) comprises a light reflector (5) and an optical semiconductor chip (3). The reflector (5) includes two first reflecting surfaces (50a) spaced from each other in direction x, and two second reflecting surfaces (50b) spaced from each other in direction y. The chip (3) includes a...

20060163604 - Gallium nitride-based light emitting device having light emitting diode for protecting electrostatic discharge, and melthod for manufacturing the same: A gallium nitride-based light emitting device, and a method for manufacturing the same are provided. The light emitting device comprises a substrate; a main GaN-based LED including a first p-side electrode and a first n-side electrode, the main GaN-based LED formed in a first region on the substrate; and an...

20060163603 - Light-emitting diode device and production method thereof: A double hetero structure light-emitting diode device includes an active layer (6), a positive-electrode-side cladding layer, a negative-electrode-side cladding layer (4), a window layer (9) and an undoped AlInP layer. The positive-electrode-side cladding layer includes an undoped AlInP layer (7) grown to have a thickness of 0.5 μm and an...

20060163606 - Photonic crystal light emitting device: A photonic crystal structure is formed in an n-type region of a III-nitride semiconductor structure including an active region sandwiched between an n-type region and a p-type region. A reflector is formed on a surface of the p-type region opposite the active region. In some embodiments, the growth substrate on...

20060163605 - Substrate for thin film formation, thin film substrate, and light-emitting device: A substrate for forming a thin film composed mainly of gallium nitride, indium nitride or aluminum nitride, the substrate consisting of a sintered compact composed mainly of a ceramic material; and a thin-film substrate furnished with the thin film. The use of the sintered compact composed mainly of a ceramic...

20060163607 - Upside-down photo detector: The efficiency of photo diodes is according to a basic idea improved by using them upside-down through letting the light (20) enter via the substrate layer (1), and by using the surface layer (3) as a mirror. Then, the epitaxial layer (2) has an approximately doubled chance to convert photons...

20060163609 - Compound semiconductor switching circuit device: High resistance elements of 5 KΩ or more are connected near first and second control terminals between the first and second control terminals and respective crossing portion of first and second connectings. Even when a high frequency analog signal transmitted in a pad wire leaks to the first and second...

20060163608 - Protecting silicon germanium sidewall with silicon for strained silicon silicon mosfets: Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area....

20060163611 - Dc/dc converter using bipolar transistor, method of manufacturing the same and dc power supply module using the same: A DC/DC converter is comprised of a bipolar transistor, an inductor, a smoothing capacitor, an input terminal, an output terminal, and a grounded terminal. A base of the transistor includes a silicon germanium layer. The bipolar transistor has a high switching speed and a low on-state voltage through an optimization...

20060163610 - Semiconductor device: A semiconductor device is provided. In one example, a semiconductor device has a D-HBT structure which include a base layer formed from InGaAs and an emitter layer and a collector layer both formed from InGaP in such a way as to hold said base layer between them, wherein said InGaAs...

20060163612 - Sixsnyge1-x-y and related alloy heterostructures based on si, ge and sn: A novel method for synthesizing device-quality alloys and ordered phases in a Si—Ge—Sn system uses a UHV-CVD process and reactions of SnD4 with SiH3GeH3. Using the method, single-phase SixSnyGe1-x-y semiconductors (x≦0.25, y≦0.11) are grown on Si via Ge1-xSnx buffer layers The Ge1-xSnx buffer layers facilitate heteroepitaxial growth of the SixSnyGe1-x-y,...

20060163613 - Layout structure for sub word line drivers and method thereof: A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the...

20060163614 - Multi-layer memory arrays: Multi-layer memory arrays and methods are provided. A memory array has two or more layers of memory material, each layer of memory material having an array of memory cells. A first contact penetrates through each layer of memory material in a first plane and is electrically connected to each layer...

20060163615 - Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner: Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requiring a large area is not...

20060163616 - Semiconductor device having esd protection circuit: Provided is a semiconductor device in which a resistor and a capacitor are inserted in an input/output signal line that connects an input/output pad and an internal circuit at an input/output terminal in order to prevent damage of the internal circuit due to static electricity. The semiconductor device includes the...

20060163617 - Solid-state imaging device and its manufacturing method: A partial P type region 150 is provided at the predetermined position of a lower layer region of the vertical transfer register 124 and a channel stop region 126. This P type region 150 is used to adjust potential in the lower layer region of the vertical transfer register 124...

20060163618 - Image sensor with buried barrier layer having different thickness according to wavelength of light and method of forming the same: There is provided an image sensor and a method of forming the same in order to prevent cross talk and to improve sensitivity. The image sensor includes a plurality of pixels for embodying colors having different wavelengths, and each of pixels includes a photoelectric conversion unit and a buried barrier...

20060163620 - Charge coupled device and solid-state imaging apparatus: When capacity coupling between an output gate electrode (OG) and a last-stage transfer electrode is large at an output end of a CCD shift register, an electric potential of the OG is varied according to transfer clocks with the result that noise is liable to generate in an output signal....

20060163619 - Solid-state imaging device and method for producing solid-state imaging device: A solid state image pickup device in which an image pickup region composed of a plurality of light-receiving pixel portions 1 and a transfer register 2 for transferring in one direction the signal charges accumulated in the light-receiving pixel portions 1 is formed on the face layer portion side of...

20060163621 - Pre-insulating substrate, method of manufacturing substrate, method of manufacturing surface acoustic wave resonator, surface acoustic wave resonator, surface acoustic wave device, and electronic apparatus: A pre-insulating substrate includes a base including an electrically conductive portion on a surface of the base, and a protective film disposed on the surface of the base to cover part of the conductive portion so as to prevent insulating treatment from being implemented for the part of the conductive...

20060163622 - Apparatus and method for manufacturing thermal interface device having aligned carbon nanotubes: A method and apparatus for manufacturing a coupon of material having aligned carbon nanotubes. The coupon having aligned carbon nanotubes may be used as a thermal interface device in a packaged integrated circuit device....

20060163626 - High voltage transistor structure for semiconductor device: A high voltage MOS transistor has a thermally-driven-in first doped region and a second doped region that form a double diffused drain structure. Boundaries of the first doped region are graded. A gate-side boundary of the first doped region extends laterally below part of the gate electrode. The second doped...

20060163623 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor layer, an insulated-gate field effect transistor provided in the semiconductor layer, an etching stopper film provided above the insulated-gate field effect transistor, and an interlayer insulating layer provided above the etching stopper film; the insulated-gate field effect transistor including a gate insulating layer provided...

20060163624 - Semiconductor device, and manufacturing method thereof: The present invention provides a semiconductor device having a fully silicided gate electrode (full-silicide gate electrode) and a manufacturing method thereof, that has no problem of the increase in junction leak current, can increase a thickness of a metal silicide film formed on a source/drain region, and can form a...

20060163625 - Semiconductor layer and forming method thereof, and semiconductor device and manufacturing method thereof technical field: The present invention relates to a semiconductor layer applicable to a hetero-junction bipolar transistor, a forming method thereof, and a semiconductor device and a manufacturing method thereof, for example. The semiconductor layer and the forming method thereof according to the present invention includes a first SiGe film or SiGeC film...

20060163627 - Deuterated structures for image sensors and methods for forming the same: A pixel cell with a photo-conversion device and at least one structure includes a deuterated material adjacent the photo-conversion device....

20060163628 - Solid state imaging apparatus and method for fabricating the same: A semiconductor device of the present invention includes a substrate; an imaging region which is formed at part of the substrate and in which photoelectric conversion cells including photoelectric conversion sections are arranged in the form of an array; a control-circuit region which is formed at part of the substrate...

20060163629 - Rf field heated diodes for providing thermally assisted switching to magnetic memory elements: An exemplary array of thermally-assisted magnetic memory structures includes a plurality of magnetic memory elements, each magnetic memory element being near a diode. A diode near a selected magnetic memory element can be heated by absorbing energy from a radio frequency electromagnetic field. The heated diode can be used to...

20060163630 - Tic as a thermally stable p-metal carbide on high k sio2 gate stacks: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the...

20060163632 - Dielectric relaxation memory: A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as...

20060163633 - Dielectric relaxation memory: A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as...

20060163634 - Semiconductor storage device: A semiconductor storage device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first...

20060163631 - Vertical mosfet with dual work function materials: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell...

20060163635 - Capacitor below the buried oxide of soi cmos technologies for protection against soft errors: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and...

20060163637 - Semiconductor device having two-layered charge storage electrode: A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap...

20060163636 - Trench capacitor array having well contacting merged plate: According to an aspect of the invention, a structure is provided in which an array of trench capacitors includes a well contact to a merged buried plate diffusion region. The array, which is disposed in a substrate, includes a contact for receiving a reference potential. Each trench capacitor includes a...

20060163640 - Method of fabricating metal-insulator-metal capacitor and metal-insulator-metal capacitor manufactured by the method: In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming...

20060163638 - Semiconductor device and method for fabricating the same: A semiconductor device includes a first insulating film formed on a semiconductor substrate; a second insulating film formed on the first insulating film and having a recess corresponding to a capacitor region; a lower electrode formed in the recess; a capacitor dielectric film formed on the lower electrode; and an...

20060163639 - Semiconductor memory device and method for fabricating the same: A semiconductor memory device includes a memory cell and a dummy cell. The amount of leakage current per unit area in a capacitor in the dummy cell is larger than that in a capacitor in the memory cell....

20060163641 - Insulation film semiconductor device and method: A semiconductor device and method of its manufacturing method are provided for realizing smaller low voltage transistors while maintaining the characteristics of high voltage transistors. A first transistor formation region is separated by selectively leaving first element-separating insulator film. A second transistor formation region is separated by selectively oxidized second...

20060163643 - Double gate memory cell with improved tunnel oxide: Provides a double gate memory cell having a silicon substrate with an active region having a channel region and source/drain regions, the active region forming a ridgelike fin with at least the channel region. A tunnel oxide layer is formed at least partly on the surface of the ridgelike fin...

20060163642 - Self-aligned 2-bit \"double poly cmp\" flash memory cell: Fabrication of a memory cell, the cell including a first floating gate stack (A), a second floating gate stack (B) and an intermediate access gate (AG), the floating gate stacks (A, B) including a first gate oxide (4), a floating gate (FG), a control gate (CG; CGl, CGu), an interpoly...

20060163645 - Eeprom with split gate source side injection: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or...

20060163646 - Nonvolatile memory device using semiconductor nanocrystals and method of forming same: A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a...

20060163644 - Scalable high density non-volatile memory cells in a contactless memory array: A plurality of split gate non-volatile memory cells are formed vertically in a trench along the sidewalls. Each cell is comprised of a bistable element and an adjacent fixed gate threshold element that share a common respective control gate/access gate. The bistable element has a gate insulator stack that is...

20060163647 - Mos semiconductor device: While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor for increasing both MOS currents. In the MOS semiconductor...

20060163648 - Semiconductor component: A semiconductor component that is able to be produced simply, quickly, and yet reliably and that usable for power applications, and including a semiconductor chip, a lower, first main electrode layer formed on a first side of the semiconductor chip, a lower control electrode layer formed on the first side,...

20060163649 - Insulated gate semiconductor device and method of manufacturing the same: A trench MOSFET includes mesa regions between the trenches. The mesa regions are connected to an emitter electrode to fix the mesa region potential so that the mesa regions do not form a floating structure. P-type base regions are distributed in the mesa regions, and the distributed p-type base regions...

20060163650 - Power semiconductor device with endless gate trenches: A power semiconductor device which includes endless gate trenches....

20060163651 - Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor: The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate...

20060163653 - Semiconductor device: To present a semiconductor device capable of operating stably even at large current, by lessening current concentration into the corners of contact opening after switching off and suppressing local heat generation without raising the ON voltage. In an insulated gate transistor divided by P field region 111 and gate electrode...

20060163652 - Semiconductor device with sense structure: A power semiconductor device is described with a plurality of cells divided into power cells (14) and sense cells (16). A plurality of groups (30, 32) of sense cells (16) are provided. The device allows for compensation of effects caused at the edges of the groups of sense cells (16)....

20060163655 - Semiconductor device: An exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more compounds of the formula AxBxOx, wherein each A is selected from the group of Cu, Ag, Sb, each B is selected from the group of Cu, Ag, Sb, Zn, Cd, Ga, In,...

20060163654 - Silicon-on-insulator device: A Silicon on Insulator (SOI) device is disclosed wherein an extension of P-type doping (303) is implanted between the buried oxide layer of the device and the SOI layer. The extension is of a size and shape to permit the source (309) to be biased at a voltage significantly less...

20060163656 - Nonvolatile memory device with curved floating gate and method of fabricating the same: Disclosed is a nonvolatile memory device comprising: a tunnel oxide layer on a semiconductor substrate; a floating gate on the tunnel oxide layer; a gate interlevel insulation layer on the floating gate layer; a control gate on the gate interlevel insulation layer; a source region at a side of the...

20060163657 - Method to reduce leakage in a protection diode structure: A protection diode is used in a CMOS integrated circuit device to direct charged particles to benign locations and prevent damage to the device. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region...

20060163658 - Monolithic mosfet and schottky diode for mobile phone boost converter: A cell phone has a plurality of interconnected electronic components for performing the electrical functions of the phone. A DC/DC converter provides an operating voltage which is applied to power supply terminals of the plurality of interconnected electronic components. The DC/DC converter uses a monolithic semiconductor device containing a power...

20060163659 - Compound semiconductor switch circuit device: A high-resistance element is connected as a part of a control resistor between a control terminal pad and a protecting element, immediately near the control terminal pad. Thus, even if a high-frequency analog signal leaks to the control resistor, the leaked signal is attenuated by the high-resistance element. This substantially...

20060163660 - Electrostatic discharge (esd) protection circuit: An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs) each with a floating base and a metal oxide semiconductor (MOS) field transistor with a floating body is disclosed. The three transistors may be connected in parallel between a bond...

20060163663 - Metal gate engineering for surface p-channel devices: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in...

20060163661 - Selective doping and thermal annealing method for forming a gate electrode pair with different work functions: A semiconductor product and a method for fabricating the semiconductor product provide a pair of gate electrodes formed with respect to a pair of doped wells within a semiconductor substrate. One of the gate electrodes is formed of a first gate electrode material having a first concentration of an electrically...

20060163662 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate; a first gate electrode formed on the first gate insulation film and fully silicided; and a second gate electrode formed on the second...

20060163664 - Semiconductor device and manufacturing process thereof: The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is...

20060163665 - Dummy patterns in integrated circuit fabrication: An embodiment of the invention provides a semiconductor integrated circuit device having a dummy pattern for improving micro-loading effects. The device comprises an active region in a substrate and an isolation region in the substrate adjacent the active region. A plurality of dummy patterns are formed over the isolation region,...

20060163666 - Semiconductor integrated circuit having resistor: A semiconductor integrated circuit having a resistor is disclosed in which the resistor is formed by a series connection of one element having a positive temperature coefficient and another element having a negative temperature coefficient....

20060163667 - Mos transistors having low-resistance salicide gates and a self-aligned contact between them and method of manufacture: A method for forming a self-aligned contact between two MOS transistors is described. The method supports the use of low-resistivity suicides for the formation of contacts in nanometer applications that employ polycide techniques. Silicon nitride and photoresist material act as dual masks in the formation of the self-aligned contact....

20060163668 - Semiconductor device and method for manufacturing same: In the method for manufacturing the semiconductor device including a salicide film, prior to the process for forming the salicide film (S30), the operation for protecting the oxide film is conducted in order to prevent the scattering of the oxide film on silicon substrate (S10). Then, the operation for cleaning...

20060163669 - Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby: A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region...

20060163670 - Dual silicide process to improve device performance: A semiconducting structure and a method of forming thereof, includes a substrate having a p-type device region and an n-type device region; a first-type suicide contact to the n-type device region; the first-type suicide having a work function that is substantially aligned to the n-type device region conduction band; and...

20060163671 - Silicide cap structure and process for reduced stress and improved gate sheet resistance: A suicide cap structure and method of fabricating a suicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and...

20060163672 - High performance cmos device design: A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second...

20060163673 - Method and structure for providing tuned leakage current in cmos integrated circuits: A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjacent to the gate region, wherein the gate oxide layer...

20060163674 - Metal oxide semiconductor field effect transistor and method of fabricating the same: There are provided a MOSFET and a method for fabricating the same. The MOSFET includes a semiconductor substrate, a first epitaxial layer in a predetermined location of the semiconductor substrate, a second epitaxial layer doped with high concentration impurity ions on the first epitaxial layer, a gate structure on the...

20060163675 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film, a...

20060163676 - Insulating film and semiconductor device: An insulating film includes an oxide or an oxynitride of a constituent element having a positive valence. The oxide or the oxynitride contains an additive element having a larger valence than the constituent element in a range not less than 3×10−8 at % and less than 1.6×10−3 at %....

20060163677 - Methods of forming a semiconductor device having a metal gate electrode and associated devices: Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon...

20060163678 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device is provided which has insulating film side wall spacers having a barrier function. The semiconductor device comprises: a gate oxide film and a gate electrode formed on and above a semiconductor substrate; source/drain regions formed in the semiconductor substrate; and first laminated side wall spacers having two...

20060163679 - High performance mems packaging architecture: An apparatus and method for sensor architecture based on bulk machining of Silicon-On-Oxide wafers and fusion bonding that provides a symmetric, nearly all-silicon, hermetically sealed MEMS device having a sensor mechanism formed in an active semiconductor layer, and opposing silicon cover plates each having active layers bonded to opposite faces...

20060163680 - Micro-machined medical devices, methods of fabricating microdevices, and methods of medical diagnosis, imaging, stimulation, and treatment: A medical device may include a micro-machined substrate, at least one thermo-electric assembly associated with the substrate, and a cooling system configured to configured to remove heat from the a region of the substrate proximal the substrate. According to various aspects, a method of clearing plaque from a blood vessel...

20060163681 - Gallium-nitride based ultraviolet photo detector: A structure for a gallium-nitride (GaN) based ultraviolet photo detector is provided. The structure contains an n-type contact layer, a light absorption layer, a light penetration layer, and a p-type contact layer, sequentially stacked on a substrate from bottom to top in this order. The layers are all made of...

20060163682 - Semiconducting photo detector structure: An epitaxial structure for semiconducting photo detectors is provided. The epitaxial structure contains a substrate having a built-in electric circuit, a first and second metallic layers on top of said substrate electrically connected to the corresponding electrical input and output points of the substrate's electric circuit, and a semiconducting photo...

20060163683 - Luminescent body and optical device including the same: A luminous body of prolonged fluorescence lifetime characterized by comprising not only an activator but also at least one coactivator selected from the group consisting of La, Ce, Pr, Nd, Sm, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Bi, Sn, Sb and analogues thereof as a further luminescent center...

20060163684 - Solid-state image pickup apparatus: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel...

20060163685 - Thermo-mechanical cleavable structure: A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and...

20060163686 - Novel process to improve programming of memory cells: A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of...

20060163687 - Structure and method for mixed-substrate simox technology: The present invention provides a semiconductor structure that includes a substrate having a crystal lattice; a first structure formed in a first region of the substrate, the first structure includes at least a heterostructure that generates a lattice stress in said crystal lattice in the first region; and a second...

20060163688 - Multiple layer structure for substrate noise isolation: A method of forming a semiconductor structure, comprising: providing a substrate having a buried insulative layer and a heavily doped layer; forming a first trench within the substrate around a protected area; filling the first trench with an insulative material, wherein the first trench filled with the insulative material and...

20060163689 - Semiconductor device having reduced die-warpage and method of manufacturing the same: A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire surface of the substrate. A stress-relieving pattern exists in and traverses the first layer so as to partition the first layer...

20060163690 - Semiconductor having thick dielectric regions: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second mesas. The method also includes oxidizing sidewalls and bottoms of each...

20060163691 - High voltage sensor device and method therefor: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element....

20060163693 - Chip-type noise filter, manufacturing method thereof, and semiconductor package: In a chip-type noise filter having a signal line of a conductor and a magnetic body disposed so as to adhere to the signal line, the magnetic body is a sintered body containing mainly Fe2O3 and containing NiO in the rest. This enables to effectively absorb and damp noise of...

20060163692 - Inductive and capacitvie elements for semiconductor techinologies with minimum pattern density requirements: The present invention provides a semiconductor device comprising a plurality of layers, the semiconductor device comprising:—a substrate having a first major surface,—an inductive element fabricated on the first major surface of the substrate, the inductive element comprising at least one conductive line, and—a plurality of tilling structures in at least...

20060163695 - Inductors for integrated circuits: An inductor for an integrated circuit or integrated circuit package comprises a three-dimensional structure. In one embodiment the inductor is arranged on an integrated circuit substrate in at least two rows, each row comprising upper segments and lower segments, with the upper segments being longer than the lower segments. The...

20060163694 - Semiconductor device having spiral-shaped inductor: An element isolation region is formed in a surface region of a semiconductor substrate. A spiral-shaped inductor is formed above the element isolation region. A conductive region to which a constant potential is applied is formed inside the inner circumference of the inductor....

20060163697 - Bipolar transistor and related method of fabrication: Disclosed are a bipolar transistor comprising an emitter terminal and a base terminal having substantially equal heights, and a method of fabricating the same. The bipolar transistor comprises a silicon-germanium layer acting as a base and formed on a semiconductor layer acting as a collector. The bipolar transistor further comprises...

20060163696 - Metal base transistor and oscillator using the same: The most important task in realizing a downsized and low cost THz band spectroscopic and fluoroscopic instrument is to achieve downsizing and cost reduction of oscillators used in the instrument. A metal base transistor is used for an active element of the oscillator. In order to improve the maximum oscillation...

20060163698 - Method and apparatus for wafer to wafer bonding: Inter-wafer structures are formed using semiconductor fabrication methods so as to provide precise, uniform distance between die on a bottom wafer and die on a top wafer. An inter-wafer structure layer is patterned to form one or more inter-wafer structures surrounding an active circuit area on a bottom die, or...

20060163701 - Scribe-line structures and methods of forming the same: Scribe-line structures and methods of forming such scribe-line structures on a face of a semiconductor substrate are provided. By means of the scribe-line structures and the methods of this invention, physical shock and cracking tendencies along a semiconductor substrate can be minimized during performance of a cutting process on the...

20060163700 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation...

20060163699 - Semiconductor wafer, semiconductor device manufacturing method, and semiconductor device: A plurality of semiconductor elements and division regions are provided on a semiconductor substrate. A modification region is provided in the semiconductor substrate. A division guide pattern is provided at least in a portion of each division region. A cleavage produced from a starting point corresponding to the modification region...

20060163702 - Chip on board leadframe for semiconductor components having area array: A leadframe for semiconductor components includes leadfingers, interconnect bonding sites for wire bonding to a semiconductor die, terminal bonding sites for terminal contacts for the component in an area array, and bus bars which electrically connect selected leadfingers to one another. The interconnect bonding sites are located on the leadframe...

20060163703 - Lead frame and method of producing the same, and resin-encapsulated semiconductor device and method of producing the same: A resin-encapsulated semiconductor device includes a semiconductor chip, a plurality of inner leads that are connected to a group of electrodes of the semiconductor chip, respectively, and an encapsulating resin that encapsulates a connection part located between the semiconductor chip and the inner leads. Each of the inner leads includes...

20060163704 - Chip package and producing method thereof: A chip package including a carrier, a chip, a stiffener and a molding compound is provided. A producing method of the chip package includes the steps of disposing a bottom surface of the chip on the carrier; covering an edge of a top surface of the chip with the stiffener...

20060163705 - Surface mount semiconductor device: A surface mount semiconductor device using a lead frame can suppress stress applied to a package by a load in a forming process performed for the lead frame projecting from the package at a portion at which the lead frame projects the package. Concave portions can be provided in at...

20060163706 - Bilayer aluminum last metal for interconnects and wirebond pads: A method for connecting a microelectronic device to a wirebond comprises providing a substrate having a microelectronic circuit therein and forming a wiring layer over the substrate. The wiring layer includes a bilayer wiring structure comprising upper and lower electrically conductive layers separated by a protective electrically conductive layer. The...

20060163709 - Chip-scale monolithic load switch for portable applications: A chip-scale package houses a monolithic semiconductor die containing first and second lateral metal oxide semiconductor field effect transistors (MOSFETs) formed on a surface of the semiconductor die. The MOSFETs are formed using a lateral double diffused metal oxide semiconductor structure. The first MOSFET has a first conduction terminal coupled...

20060163707 - Method and apparatus for reducing stresses applied to bonded interconnects between substrates: A method (200) is provided for reducing stresses applied to one or more bonded interconnects (106) of a substrate (103) and a PCB (Printed Circuit Board) (104). The method comprises the steps of coupling (204) a compound (108) on a top surface of the substrate, wherein the compound has the...

20060163708 - Semiconductor device: A semiconductor device comprises: an envelope having a thermal conductivity; a semiconductor dies placed inside the envelope; and a sealing cap disposed so as to cover the envelope and having a thermal conductivity. The envelope is provided with a lead connection portion including a lead wire and a dies receiving...

20060163710 - Semiconductor device and manufacturing method thereof: A technique for manufacturing a low-cost, small volume, and highly integrated semiconductor device is provided. A characteristic of the present invention is that a semiconductor element formed by using a semiconductor thin film is transferred over a semiconductor element formed by using a semiconductor substrate by a transfer technique in...

20060163711 - Method to form an electronic device: An electronic device includes a substrate and at least one electronic component formed on the substrate. The device also includes a lid coupled to the substrate, in which the lid at least partially covers the electronic component. The lid is partially trenched using one or more micro-blasting processes....

20060163712 - System and method for direct-bonding of substrates: A MEMS package includes a first substrate having a bonding surface and a second substrate having a polished bonding surface facing the bonding surface of the first substrate. The MEMS package further includes a polished layer of bonding substrate material deposited onto the bonding surface of the first substrate and...

20060163713 - Semiconductor device: In an SiP constituted by laminating a plurality of chips, it is an object to reduce a thickness of the SiP without damaging a strength of a chip on an upper side and deteriorating a reliability due to dicing in the case in which the chip on the upper side...

20060163714 - Package structure and fabrication method thereof: A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the...

20060163715 - Flip chip interconnection pad layout: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate...

20060163716 - Semiconductor package with crossing conductor assembly and method of manufacture: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having...

20060163717 - Method for connection of an integrated circuit to a substrate, and a corresponding circuit arrangement: The present invention provides a method for connection of an integrated circuit (1), in particular of a chip, a wafer or a hybrid, to a substrate (10), which has the following steps: provision of an elastic intermediate layer (5) on the integrated circuit (1) and/or the substrate (10); structuring of...

20060163718 - Flexible wiring base material and process for producing the same: The flexible wiring substrate 10 includes an insulating substrate 11, a wiring pattern 12 formed on a surface of the insulating substrate 11, and a solder resist layer 17 covering a surface of the wiring pattern 12 excluding at least terminal portions of the wiring pattern 12, at least a...

20060163719 - Semiconductor device and method of manufacturing a semiconductor device: There is provided a semiconductor device including, a bed, a brazing filler metal formed on a first surface of the bed, a barrier metal film formed on a first surface of the brazing filler metal, a alloy film formed on a first surface of the barrier metal film, a semiconductor...

20060163720 - Semiconductor device: A semiconductor device is provided with a sealing ring 106 made of a metal which surrounds an integrated circuit part 102 and which is formed on a substrate 104 along an outer perimeter of the rectangular device. At least one corner part 108 of the sealing ring is formed to...

20060163721 - Electronic assembly with reduced leakage current: An electronic assembly includes a substrate and at least one surface mounted electronic component. The substrate includes a first side and a second side opposite the first side. The first side of the substrate includes a plurality of conductive traces formed thereon. The plurality of conductive traces includes a first...

20060163723 - Bump-less chip package: A bump-less chip package is provided. The bump-less chip package includes a chip, an interconnection structure and a panel-shaped component. The panel-shaped component has a plurality of electrical terminals on a first surface thereof. The back surface of the chip is disposed on the first surface of the panel-shaped component,...

20060163724 - Display apparatus: In a display apparatus, a display panel receives a driving signal from a driving chip through a pad and displays an image in response to the driving signal. The driving chip includes a terminal outputting the driving signal. The driving chip is mounted on the display panel using the anisotropic...

20060163722 - Semiconductor chip electrical connection structure: A semiconductor chip electrical connection structure includes electrode pads formed on a surface of a semiconductor chip, wherein the semiconductor chip is mounted via another surface thereof on a carrier; a plurality of conductive bumps formed on the electrode pads respectively, and exposed from a dielectric layer applied on the...

20060163726 - Spaced, bumped component structure: A spaced, bumped component structure including a first plate, a second plate spaced from the first plate by a first gap, a plurality of solder bumps interconnecting the plates and defining the first gap; at least one of the plates having an anomalous section including one of a raised platform...

20060163725 - Wiring board and production method thereof: It is an object of the present invention to provide a wiring board having high-density wiring with a controlled shape without masking by a resist film and a production method thereof. In the present invention, the production method of a wiring board having copper wiring on an insulating substrate includes...

20060163727 - Semiconductor device: The present invention relates to semiconductor devices. According to the present invention a semiconductor device is described, comprising: a substrate for carrying a semiconductor chip on a first surface of said substrate; said semiconductor chip being punctually attached to said substrate on said first surface of said substrate via a...

20060163728 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes: a semiconductor chip having a plurality of electrode pads formed on a principal surface thereof; a sealing resin, which covers both (i) side surfaces of the semiconductor chip and (ii) a surface of the semiconductor chip opposite to the principal surface; and external connection pads, which...

20060163729 - Structure and manufacturing method of a chip scale package: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip...

20060163732 - Copper interconnect systems which use conductive, metal-based cap layers: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least...

20060163731 - Dual damascene interconnections employing a copper alloy at the copper/barrier interface: A method of fabricating a dual damascene interconnection is provided. The method begins by forming on a substrate a dielectric layer and forming a via in the dielectric layer. The dielectric layer is partially etched to form a trench, which is connected to the via and in which interconnections will...

20060163730 - Electronic device and its manufacturing method: A first nitrogen-containing insulating film is formed under a low dielectric constant film, in which a via hole is formed, with a first nitrogen-non-containing insulating film interposed between the first nitrogen-containing insulating film and the low dielectric constant film. A second nitrogen-containing insulating film is formed over the low dielectric...

20060163733 - Semiconductor structure having multilayer of polysilicon and display panel applied with the same: A semiconductor structure includes a substrate, a first polysilicon (polysilicon) region, a second polysilicon region, an insulating layer and a third polysilicon region. The first and second polysilicon regions are formed on the substrate and spaced apart by a gap. The insulating layer formed on the substrate covers the first...

20060163735 - Damascene process at semiconductor substrate level: A damascene structure and process at semiconductor substrate level. A pre-metal dielectric layer is provided on a semiconductor substrate with an opening exposing a contact region on the substrate. A buffer metal layer is provided on the exposed contact region, and a barrier layer is provided on the interior of...

20060163734 - Fuse structure and method for making the same: Provided are a fuse structure and a method for manufacturing the fuse structure. In one example, the method includes providing a multilayer interconnect structure (MLI) over a semiconductor substrate. The MLI includes multiple fuse connection and bonding connection features. A passivation layer is formed over the MLI and patterned to...

20060163737 - Interconnections for integrated circuits: An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects....

20060163736 - Interconnections having double capping layer and method for forming the same: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer...

20060163738 - Dual damascene structure and methods of forming the same: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side...

20060163739 - Semiconductor device and method for production thereof: Disclosed herein is a semiconductor device with improved electromigration durability and a method for producing the semiconductor device. A semiconductor device includes: an interlayer insulating film formed on a first metal wiring; a second metal wiring formed by embedding in the interlayer insulating film; a metal contact formed by embedding...

20060163740 - Semiconductor mounting board: A semiconductor mounting board 80 is prepared by electrically joining an IC chip 70 via an interposer 60 of high rigidity to external pads 41 and internal pads 43, which are formed on the uppermost surface of a build-up layer 30. When the IC chip 70 generates heat, since pads...

20060163741 - Tft array panel and fabricating method thereof: A TFT array panel including a lower aluminum layer, an aluminum nitride layer formed on the lower aluminum layer, and an upper aluminum layer formed on the aluminum nitride layer is presented. This TFT array panel including an aluminum wiring line reduces or even prevents the formation of a hillock...

20060163742 - Semiconductor component with passivation layer: A semiconductor component has a semiconductor body and also a metal/insulation structure arranged above the semiconductor body and having a plurality of metal regions and insulation regions laterally adjoining one another. The metal regions serve for supplying the semiconductor body with electric current. Furthermore, the semiconductor component has a passivation...

20060163744 - Printable electrical conductors: An electrical conductor formed from one or more metallic inks. The electrical conductor comprises a network of interconnected metallic nodes. Each node comprises a metallic composition, e.g., one or more metals or alloys. The network defines a plurality of pores having an average pore volume of less than about 10,000,000...

20060163745 - Semiconductor device: In a semiconductor device according to the present invention, a first bare chip, and a second bare chip having a wider principal surface than that of the first bare chip are connected to one principal surface and the other principal surface of an interposer substrate, respectively. In the semiconductor device,...

20060163743 - Semiconductor device and method for manufacturing the same, and electric device: It is an object of the present invention to simplify steps needed to process a wiring in forming a multilayer wiring. In addition, when a droplet discharging technique or a nanoimprint technique is used to form a wiring in a contact hole having a comparatively long diameter, the wiring in...

20060163747 - Assembly including a circuit and an encapsulation frame, and method of making the same: An assembly for a circuit board includes a substrate, at least one circuit component formed on the substrate, and a frame. The frame comprises a first substantially planar surface attached to the substrate, and a hole formed through the frame and defined by a wall that surrounds the at least...

20060163746 - Barrier structure for semiconductor devices: An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along...

20060163748 - Semiconductor device: The semiconductor device includes a semiconductor substrate, a diffusion layer, an interconnect layer, a contact plug, a contact-inspection hole, a via plug, and a via-inspection hole. Similarly to a contact plug hole, the contact-inspection hole extends from the diffusion layer to the interconnect layer. The opening of the contact-inspection hole...

20060163749 - Ic chip package structure and underfill process: A novel integrated circuit (IC) chip package structure and underfill process which reduces stress applied to corners of a flip chip in an IC package structure during the application of an adhesive material between the flip chip and a carrier substrate is disclosed. The process includes providing a dam structure...

20060163750 - Semiconductor device and method for producing the same: A semiconductor device provided with a stabilized hollow structure. A semiconductor device 1 having a semiconductor chip 3 flip chip-mounted on a substrate 2 includes a plate-shaped member 4 arranged on a surface of the semiconductor chip 3 opposite to its flip chipped surface. The plate-shaped member is protruded more...

20060163751 - Integrated circuit package encapsulating a hermetically sealed device: An integrated circuit package is disclosed having a semiconductor chip, a hermetically sealed device supported by the semiconductor chip, and a molding compound sealing the semiconductor chip and the device together as a composite package. A method of manufacturing the package is also disclosed....

20060163752 - Storage assembly: A gas storage assembly that has an enclosure within which are disposed at least about 100 inorganic tubules are present for each cubic micron of volume of the enclosure. The assembly has a storage capacity of at least 20 grams of hydrogen per liter of volume of the enclosure....

20060157679 - Structure and method for biasing phase change memory array for reliable writing: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory...

20060157681 - Horizontal chalcogenide element defined by a pad for use in solid-state memories: A process for fabricating phase-change elements having ultra small cross-sectional areas for use in phase change memory cells specifically and in semiconductor devices generally in which pads are implemented to create horizontally aligned phase change elements is disclosed. The elements thus defined may be used within chalcogenide memory cells or...

20060157680 - Semiconductor integrated circuit device: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising...

20060157683 - Nonvolatile phase change memory cell having a reduced thermal contact area: The invention provides for a nonvolatile memory cell comprising a heater layer in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volume assists this phase change. In the present invention, a...

20060157682 - Write-once nonvolatile phase change memory array: The invention provides for a write-once nonvolatile memory array, the memory cells comprising a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. The initial, unprogrammed state of each memory cell is a crystalline, low-resistance state, while the programmed state is an...

20060157684 - Thin film multilayer with nanolayers addressable from the macroscale: A thin film multilayer device having a multilayer stack formation including an array of electrically conductive or optically transmissive nanolayers separated by insulating layers. The nanolayers have one end with nanometer size and spacing, and another end with macro-sized tab sections through which the array of nanolayers may be individually...

20060157686 - Quantum dot phosphor for light emitting diode and method of preparing the same: Disclosed herein is a quantum dot phosphor for light emitting diodes, which includes quantum dots and a solid substrate on which the quantum dots are supported. Also, a method of preparing the quantum dot phosphor is provided. Since the quantum dot phosphor of the current invention is composed of the...

20060157685 - Semiconductor device method of manfacturing a quantum well structure and a semiconductor device comprising such a quantum well structure: Consistent with example embodiments a semiconductor device and a method are disclosed for obtaining on a substrate a multilayer structure with a quantum well structure. The quantum well structure comprises a semiconductor layer sandwiched by insulating layers, wherein the material of the insulating layers has preferably a high dielectric constant....

20060157688 - Methods of forming semiconductor constructions and integrated circuits: The invention includes a TFT-based logic circuit construction. Such construction includes a pair of first transistor devices, and a pair of second transistor devices over the first transistor devices. The first transistor devices have first active regions extending into a first semiconductive material, and the second transistor devices have second...