Active solid-state devices (e.g., transistors, solid-state diodes) inventions 07/06

20060163553 - Phase change memory and fabricating method thereof: A phase change memory including a phase change layer, a first electrode, and a porous dielectric layer formed with a plurality of pores. The porous dielectric layer is formed between the phase change layer and the first electrode. Therefore, the phase change layer may make contact with the first electrode...

20060163554 - Electric device comprising phase change material: The electric device (1, 100) comprises a resistor (36, 250) comprising a phase change material which is able to be in a first phase and in a second phase. The resistor (36, 250) has an electrical resistance which has a first value when the phase change material is in the...

20060163555 - Led and a lighting apparatus using the led: Disclosed herein is a LED and a lighting apparatus, which employs a LED as a light source of low power and high efficiency for an optical projection system. The lighting apparatus comprises a reflection part together with the LED, and enhances light emitting directionality of the LED, thereby generating parallel...

20060163556 - Refractive index variable device: A refractive index variable device has a structure including quantum dots dispersed in a solid matrix, each of the quantum dots comprising a combination of a negatively charged accepter and a positively charged atom, where the outermost electron shell of the positively charged atom is fully filled with electrons so...

20060163558 - Mos transistor with elevated source/drain structure: In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction...

20060163557 - Semiconductor device and fabrication process thereof: A p-channel MOS transistor includes a strained SOI substrate formed of a SiGe mixed crystal layer and a strained Si layer formed on the SiGe mixed crystal layer via an insulation film, a channel region being formed in the strained Si layer, a gate electrode formed on the strained Si...

20060163561 - Electronic device and method of manufacturing thereof: Provided is a filed-effect transistor with an organic semiconductor material showing ambipolar behaviour. Thereto, the organic semiconductor material enabling the ambipolar behaviour is a material with a small band gap....

20060163560 - Led and fabrication method thereof: Disclosed is a quantum-dot LED and fabrication method thereof. The quantum-dot LED includes: a substrate; a n-type semiconductor layer formed on the substrate; an insulator layer formed on the n-type semiconductor layer and provided with a plurality of holes; quantum dots formed by filling the holes; and a p-type semiconductor...

20060163565 - Method of manufacturing substrate, method of manufacturing organic electroluminescent display device using the method, and organic electroluminescent display device: A method of manufacturing an organic electroluminescent display device includes preparing an auxiliary substrate, which has a flat side; forming a first protective layer on the auxiliary substrate; forming an organic electroluminescent unit on the first protective layer; bonding a flexible main substrate onto the organic electroluminescent unit; and etching...

20060163563 - Method to form a thin film resistor: Embodiments of methods, apparatuses, devices, and/or systems for forming thin film resistor are described....

20060163562 - Multifluorinated conductor material for leds for improving the light outcoupling: Conductor material for LEDs for improving the light outcoupling, wherein the conductor material is selected from the group comprising hole conductor material, electron conductor material and/or emitter material, the conductor material comprises at least one conductive fluorinated organic substance having at least one fluorinated alkyl substituent, one fluorinated alkenyl substituent...

20060163559 - Organic thin film transistor and manufacturing method thereof: There is provided an organic thin film transistor comprising: an organic substrate; a gate electrode; a gate insulating film; an organic semiconductor film; a source electrode; and a drain electrode, and in the organic thin film transistor, an average surface roughness Ra of the gate electrode which is in contact...

20060163564 - Use of dithiocarbamate esters and bis-dithiocarbamate esters in the preparation of organic-inorganic nanocomposites: in which X is the central body of the molecule, FUNC1 and FUNC2 independently of each other are molecular groups introducing a dipole moment and/or capable of forming intermolecular and/or intramolecular hydrogen bonding networks, and CON 1 and CON 2 independently of each other are molecular groups binding to nanostructured...

20060163566 - Method for forming semiconductor film and use of semiconductor film: The present invention provides a process for forming a semiconductor film, comprising the steps of applying a semiconductor particle dispersion liquid to a substrate surface by spray coating in such a manner that the atomized droplets of the dispersion liquid discharged from the spray coater have a mean diameter of...

20060163567 - Semiconductor electrode, method of manufacturing the same, and solar cell employing the same: Provided are a continuous-phase semiconductor electrode that can provide better photoelectric conversion efficiency by improving a pathway for electron transport, a method of manufacturing the same, and a solar cell employing the same. The semiconductor electrode includes a transparent conductive electrode, formed on a substrate, including a metal or a...

20060163570 - Aerodynamic jetting of aerosolized fluids for fabrication of passive structures: Method and apparatus for direct writing of passive structures having a tolerance of 5% or less in one or more physical, electrical, chemical, or optical properties. The present apparatus is capable of extended deposition times. The apparatus may be configured for unassisted operation and uses sensors and feedback loops to...

20060163568 - Integration system and the method for operating the same: An integration system for obtaining a set of overlay offset parameters of a first process layer which is going to be formed in an assigned photolithography tool with an assigned mask and an assigned pre-tool. By using the integration system, the set of overlay offset parameters of the first process...

20060163572 - Semiconductor memory testing device and test method using the same: A test device for a semiconductor memory device includes a clock frequency multiplier, a data input buffer, a test data generator and a data output buffer. The clock frequency multiplier multiplies an external clock signal having a relatively low frequency provided from an external test device to generate an internal...

20060163571 - Test element group structures having 3 dimensional sram cell transistors: A test element group structure having 3-dimensional SRAM cell transistors includes a bulk metal-oxide-semiconductor (MOS) transistor formed at a semiconductor substrate and a first interlayer insulating layer covering the bulk MOS transistor. A lower thin film transistor is disposed on the first interlayer insulating layer, and the lower thin film...

20060163569 - Test structure of semiconductor device: A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate...

20060163573 - Method for preparing ball grid array substrates via use of a laser: A method of using a laser to remove surface contamination and oxidation from a ball grid array substrate. The laser etching can be configured to cover the entire substrate or pinpointed to the epoxy molding compound/solder resist (EMC/SR) interfaces. Additionally, a laser can be used to roughen the surface of...

20060163574 - Semiconductor device and manufacturing method thereof: By performing the formation of the pixel electrode 127, the source region 123 and the drain region 124 by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor can be...

20060163577 - Area sensor and display apparatus provided with an area sensor: An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the...

20060163576 - Semiconductor device: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be...

20060163580 - Semiconductor device and a method of manufacturing the same: To provide a technique required for purifying the interface between an active layer and an insulating film. On a substrate (101), a gate wiring (103) is formed and the surface thereof is covered with a gate oxide film (104). Then, a first insulating film (105a), a second insulating film (105b),...

20060163579 - Thin film transistor matrix device and method for fabricating the same: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin...

20060163578 - Thin film transistor substrate and liquid crystal display: A TFT substrate comprises a substrate, a gate electrode and a lower electrode of a capacitor formed thereon, a first insulating layer formed thereon, a channel layer above the gate electrode and a lower layer of an upper electrode of the capacitor, a channel protection layer formed on an intermediate...

20060163575 - Thin film transistor with microlens structures: A thin film transistor with a microlens. A metal gate is formed on a substrate. A gate dielectric covers the metal gate. A semiconductor layer is formed on the gate dielectric. Source/drain metal layers respectively overlap ends of the top surface of the semiconductor layer such that the semiconductor layer...

20060163581 - Fabrication of strained silicon film via implantation at elevated substrate temperatures: A strained-silicon film is disclosed. A silicon-germanium film is made by ion implantation of germanium into an epitaxial silicon layer, preferably at a temperature in the range of 200 C to 400 C. The wafer is annealed in situ or optionally after implantation. A silicon film is applied to the...

20060163583 - Semiconductor device, liquid crystal device, electronic apparatus, and method of manufacturing semiconductor device: A semiconductor device includes: a substrate; a plurality of island-shaped light shielding films formed on the substrate; a first insulating film formed between the plurality of light shielding films; a second insulating film formed on the first insulating film and the plurality of light shielding films; and semiconductor elements each...

20060163582 - Thin film transistor substrate and method for forming metal wire thereof: The present invention relates to a thin film transistor substrate and a metal wiring method thereof, more particularly to a thin film transistor substrate comprising self-assembled monolayers between the substrate and the metal wiring, and a metal wiring method thereof. Since a thin film transistor substrate of the present invention...

20060163584 - Boron-doped diamond semiconductor: First and second synthetic diamond regions are doped with boron. The second synthetic diamond region is doped with boron to a greater degree than the first synthetic diamond region, and in physical contact with the first synthetic diamond region. In a further example embodiment, the first and second synthetic diamond...

20060163586 - Led with current confinement structure and surface roughening: An LED having a p-type layer of material with an associated p-contact, an n-type layer of material with an associated n-contact and an active region between the p-type layer and the n-type layer, includes a confinement structure that is formed within one of the p-type layer of material and the...

20060163585 - Light-emitting semicoductor device and a method of manufacturing it: In layer structure 20 of a semiconductor laser of a surface emitting type, 21 and 24 represent an n-type contact layer made of n-type GaN and a p-layer made of p-type AlGaN, respectively. In the laser, an n-type DBR layer 22 made of n-type InGaN and a DBR layer 25...

20060163587 - Packaging designs for leds: Light-emitting devices, and related components, processes, systems and methods are disclosed....

20060163588 - Boron phosphide-based semiconductor light-emitting device and production method thereof: A boron phosphide-based semiconductor light-emitting device, comprising: a crystalline substrate; a first semiconductor layer formed on said crystalline substrate, said first semiconductor layer including a light-emitting layer, serving as a base layer and having a first region and a second region different from the first region; a boron phosphide-based semiconductor...

20060163589 - Heterogeneous integrated high voltage dc/ac light emitter: A single-chip integrated LED particularly adapted for direct use with a high voltage DC or AC power sources comprises a plurality of electrically isolated LEDs on a generally transparent substrate and bonded to electrically conductive elements on a thermally conductive mount. A reflective coating may be applied to the area...

20060163590 - Packaging designs for leds: Light-emitting devices, and related components, processes, systems and methods are disclosed....

20060163591 - Oled device: An organic light-emitting device (OLED) comprising an organic active region which emits electromagnetic radiation, a conversion material which converts a portion of the radiation into light of a certain spectral range, and a filter material which transmits said light....

20060163594 - High electron mobility devices: The present invention is directed to high frequency, high power or low noise devices such as low noise amplifiers, amplifiers operating at frequencies in the range of 1 GHz up to 400 GHz, radars, portable phones, satellite broadcasting or communication systems, or other devices and systems that use high electron...

20060163592 - Light emitting diode and fabricating method thereof: A light emitting diode and its fabricating method are disclosed. A light emitting diode epitaxy structure is formed on a substrate, and then the light emitting diode epitaxy structure is etched to form a recess. The recess is then filled with a transparent dielectric material. An adhesive layer is utilized...

20060163593 - Semiconductor light emitting device: A semiconductor light emitting device includes a hetero-configuration having an active layer, a first clad layer, and a second clad layer, the active layer being interposed between the clad layers. The active layer emits light when charge carriers are injected. The first and second clad layers keep the injected charge...

20060163595 - Light emitting device: A light emitting device having a transparent substrate, a light emitting stack, and a transparent adhesive layer is provided. The light emitting stack is disposed above the transparent substrate and comprises a diffusing surface. The transparent adhesive layer is disposed between the transparent substrate and the diffusing surface of the...

20060163597 - Light emitting device and method for manufacturing the same: It is an object of the present invention to provide a high-contrast light-emitting device without using a polarization plate. In particular, it is an object of the present invention to make contrast control simpler for a light-emitting device provided with a color filter. A light-emitting device according to the present...

20060163596 - Two dimensional light source using light emitting diode and liquid crystal display device using the two dimensional light source: A two-dimensional light source includes a base substrate having holes, wires disposed on a lower surface of the base substrate, a light emitting diode (LED) chip disposed on an upper surface of the base substrate, plugs that connect two electrodes of the LED chip to the wires through the holes,...

20060163600 - Chip component and method for producing a chip component: A chip component (1) includes a semiconductor body (2), in which at least one switchable element (6, 62) is arranged in a partial region (24) of the semiconductor body (2). The partial region (24) can be reached by light of at least one wavelength. Furthermore, a circuit (9) integrated into...

20060163599 - Light emitting diode and fabricating method thereof: A light emitting diode and the method of the same are provided. A light emitting diode epitaxy structure is formed on a substrate, and then the light emitting diode epitaxy structure is etched to form a recess. The recess is then filled with a transparent dielectric material. An ohmic contact...

20060163598 - Light emitting diode lamp module: An LED lamps module is provided. The LED lamp module includes a plurality of LED lamps, a plurality of electric wires and a plurality of moisture-resisting members. In one embodiment of the present invention, each LED lamp includes a substrate with a circuitry, at least one LED chip disposed on...

20060163601 - Lighting module and method the production thereof: An illumination module with at least one thin-film light emitting diode chip which is applied on a chip carrier having electrical connecting conductors and has a first and a second electrical connection side and also an epitaxially fabricated semiconductor layer sequence. The semiconductor layer sequence has an n-conducting semiconductor layer,...

20060163602 - Optical semiconductor device: An optical semiconductor device (A1) comprises a light reflector (5) and an optical semiconductor chip (3). The reflector (5) includes two first reflecting surfaces (50a) spaced from each other in direction x, and two second reflecting surfaces (50b) spaced from each other in direction y. The chip (3) includes a...

20060163604 - Gallium nitride-based light emitting device having light emitting diode for protecting electrostatic discharge, and melthod for manufacturing the same: A gallium nitride-based light emitting device, and a method for manufacturing the same are provided. The light emitting device comprises a substrate; a main GaN-based LED including a first p-side electrode and a first n-side electrode, the main GaN-based LED formed in a first region on the substrate; and an...

20060163603 - Light-emitting diode device and production method thereof: A double hetero structure light-emitting diode device includes an active layer (6), a positive-electrode-side cladding layer, a negative-electrode-side cladding layer (4), a window layer (9) and an undoped AlInP layer. The positive-electrode-side cladding layer includes an undoped AlInP layer (7) grown to have a thickness of 0.5 μm and an...

20060163606 - Photonic crystal light emitting device: A photonic crystal structure is formed in an n-type region of a III-nitride semiconductor structure including an active region sandwiched between an n-type region and a p-type region. A reflector is formed on a surface of the p-type region opposite the active region. In some embodiments, the growth substrate on...

20060163605 - Substrate for thin film formation, thin film substrate, and light-emitting device: A substrate for forming a thin film composed mainly of gallium nitride, indium nitride or aluminum nitride, the substrate consisting of a sintered compact composed mainly of a ceramic material; and a thin-film substrate furnished with the thin film. The use of the sintered compact composed mainly of a ceramic...

20060163607 - Upside-down photo detector: The efficiency of photo diodes is according to a basic idea improved by using them upside-down through letting the light (20) enter via the substrate layer (1), and by using the surface layer (3) as a mirror. Then, the epitaxial layer (2) has an approximately doubled chance to convert photons...

20060163609 - Compound semiconductor switching circuit device: High resistance elements of 5 KΩ or more are connected near first and second control terminals between the first and second control terminals and respective crossing portion of first and second connectings. Even when a high frequency analog signal transmitted in a pad wire leaks to the first and second...

20060163608 - Protecting silicon germanium sidewall with silicon for strained silicon silicon mosfets: Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area....

20060163611 - Dc/dc converter using bipolar transistor, method of manufacturing the same and dc power supply module using the same: A DC/DC converter is comprised of a bipolar transistor, an inductor, a smoothing capacitor, an input terminal, an output terminal, and a grounded terminal. A base of the transistor includes a silicon germanium layer. The bipolar transistor has a high switching speed and a low on-state voltage through an optimization...

20060163610 - Semiconductor device: A semiconductor device is provided. In one example, a semiconductor device has a D-HBT structure which include a base layer formed from InGaAs and an emitter layer and a collector layer both formed from InGaP in such a way as to hold said base layer between them, wherein said InGaAs...

20060163612 - Sixsnyge1-x-y and related alloy heterostructures based on si, ge and sn: A novel method for synthesizing device-quality alloys and ordered phases in a Si—Ge—Sn system uses a UHV-CVD process and reactions of SnD4 with SiH3GeH3. Using the method, single-phase SixSnyGe1-x-y semiconductors (x≦0.25, y≦0.11) are grown on Si via Ge1-xSnx buffer layers The Ge1-xSnx buffer layers facilitate heteroepitaxial growth of the SixSnyGe1-x-y,...

20060163613 - Layout structure for sub word line drivers and method thereof: A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the...

20060163614 - Multi-layer memory arrays: Multi-layer memory arrays and methods are provided. A memory array has two or more layers of memory material, each layer of memory material having an array of memory cells. A first contact penetrates through each layer of memory material in a first plane and is electrically connected to each layer...

20060163615 - Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner: Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requiring a large area is not...

20060163616 - Semiconductor device having esd protection circuit: Provided is a semiconductor device in which a resistor and a capacitor are inserted in an input/output signal line that connects an input/output pad and an internal circuit at an input/output terminal in order to prevent damage of the internal circuit due to static electricity. The semiconductor device includes the...

20060163617 - Solid-state imaging device and its manufacturing method: A partial P type region 150 is provided at the predetermined position of a lower layer region of the vertical transfer register 124 and a channel stop region 126. This P type region 150 is used to adjust potential in the lower layer region of the vertical transfer register 124...

20060163618 - Image sensor with buried barrier layer having different thickness according to wavelength of light and method of forming the same: There is provided an image sensor and a method of forming the same in order to prevent cross talk and to improve sensitivity. The image sensor includes a plurality of pixels for embodying colors having different wavelengths, and each of pixels includes a photoelectric conversion unit and a buried barrier...

20060163620 - Charge coupled device and solid-state imaging apparatus: When capacity coupling between an output gate electrode (OG) and a last-stage transfer electrode is large at an output end of a CCD shift register, an electric potential of the OG is varied according to transfer clocks with the result that noise is liable to generate in an output signal....

20060163619 - Solid-state imaging device and method for producing solid-state imaging device: A solid state image pickup device in which an image pickup region composed of a plurality of light-receiving pixel portions 1 and a transfer register 2 for transferring in one direction the signal charges accumulated in the light-receiving pixel portions 1 is formed on the face layer portion side of...

20060163621 - Pre-insulating substrate, method of manufacturing substrate, method of manufacturing surface acoustic wave resonator, surface acoustic wave resonator, surface acoustic wave device, and electronic apparatus: A pre-insulating substrate includes a base including an electrically conductive portion on a surface of the base, and a protective film disposed on the surface of the base to cover part of the conductive portion so as to prevent insulating treatment from being implemented for the part of the conductive...

20060163622 - Apparatus and method for manufacturing thermal interface device having aligned carbon nanotubes: A method and apparatus for manufacturing a coupon of material having aligned carbon nanotubes. The coupon having aligned carbon nanotubes may be used as a thermal interface device in a packaged integrated circuit device....

20060163626 - High voltage transistor structure for semiconductor device: A high voltage MOS transistor has a thermally-driven-in first doped region and a second doped region that form a double diffused drain structure. Boundaries of the first doped region are graded. A gate-side boundary of the first doped region extends laterally below part of the gate electrode. The second doped...

20060163623 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor layer, an insulated-gate field effect transistor provided in the semiconductor layer, an etching stopper film provided above the insulated-gate field effect transistor, and an interlayer insulating layer provided above the etching stopper film; the insulated-gate field effect transistor including a gate insulating layer provided...

20060163624 - Semiconductor device, and manufacturing method thereof: The present invention provides a semiconductor device having a fully silicided gate electrode (full-silicide gate electrode) and a manufacturing method thereof, that has no problem of the increase in junction leak current, can increase a thickness of a metal silicide film formed on a source/drain region, and can form a...

20060163625 - Semiconductor layer and forming method thereof, and semiconductor device and manufacturing method thereof technical field: The present invention relates to a semiconductor layer applicable to a hetero-junction bipolar transistor, a forming method thereof, and a semiconductor device and a manufacturing method thereof, for example. The semiconductor layer and the forming method thereof according to the present invention includes a first SiGe film or SiGeC film...

20060163627 - Deuterated structures for image sensors and methods for forming the same: A pixel cell with a photo-conversion device and at least one structure includes a deuterated material adjacent the photo-conversion device....

20060163628 - Solid state imaging apparatus and method for fabricating the same: A semiconductor device of the present invention includes a substrate; an imaging region which is formed at part of the substrate and in which photoelectric conversion cells including photoelectric conversion sections are arranged in the form of an array; a control-circuit region which is formed at part of the substrate...

20060163629 - Rf field heated diodes for providing thermally assisted switching to magnetic memory elements: An exemplary array of thermally-assisted magnetic memory structures includes a plurality of magnetic memory elements, each magnetic memory element being near a diode. A diode near a selected magnetic memory element can be heated by absorbing energy from a radio frequency electromagnetic field. The heated diode can be used to...

20060163630 - Tic as a thermally stable p-metal carbide on high k sio2 gate stacks: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the...

20060163632 - Dielectric relaxation memory: A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as...

20060163633 - Dielectric relaxation memory: A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as...

20060163634 - Semiconductor storage device: A semiconductor storage device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first...

20060163631 - Vertical mosfet with dual work function materials: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell...

20060163635 - Capacitor below the buried oxide of soi cmos technologies for protection against soft errors: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and...

20060163637 - Semiconductor device having two-layered charge storage electrode: A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap...

20060163636 - Trench capacitor array having well contacting merged plate: According to an aspect of the invention, a structure is provided in which an array of trench capacitors includes a well contact to a merged buried plate diffusion region. The array, which is disposed in a substrate, includes a contact for receiving a reference potential. Each trench capacitor includes a...

20060163640 - Method of fabricating metal-insulator-metal capacitor and metal-insulator-metal capacitor manufactured by the method: In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming...

20060163638 - Semiconductor device and method for fabricating the same: A semiconductor device includes a first insulating film formed on a semiconductor substrate; a second insulating film formed on the first insulating film and having a recess corresponding to a capacitor region; a lower electrode formed in the recess; a capacitor dielectric film formed on the lower electrode; and an...

20060163639 - Semiconductor memory device and method for fabricating the same: A semiconductor memory device includes a memory cell and a dummy cell. The amount of leakage current per unit area in a capacitor in the dummy cell is larger than that in a capacitor in the memory cell....

20060163641 - Insulation film semiconductor device and method: A semiconductor device and method of its manufacturing method are provided for realizing smaller low voltage transistors while maintaining the characteristics of high voltage transistors. A first transistor formation region is separated by selectively leaving first element-separating insulator film. A second transistor formation region is separated by selectively oxidized second...

20060163643 - Double gate memory cell with improved tunnel oxide: Provides a double gate memory cell having a silicon substrate with an active region having a channel region and source/drain regions, the active region forming a ridgelike fin with at least the channel region. A tunnel oxide layer is formed at least partly on the surface of the ridgelike fin...

20060163642 - Self-aligned 2-bit \"double poly cmp\" flash memory cell: Fabrication of a memory cell, the cell including a first floating gate stack (A), a second floating gate stack (B) and an intermediate access gate (AG), the floating gate stacks (A, B) including a first gate oxide (4), a floating gate (FG), a control gate (CG; CGl, CGu), an interpoly...

20060163645 - Eeprom with split gate source side injection: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or...

20060163646 - Nonvolatile memory device using semiconductor nanocrystals and method of forming same: A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a...

20060163644 - Scalable high density non-volatile memory cells in a contactless memory array: A plurality of split gate non-volatile memory cells are formed vertically in a trench along the sidewalls. Each cell is comprised of a bistable element and an adjacent fixed gate threshold element that share a common respective control gate/access gate. The bistable element has a gate insulator stack that is...

20060163647 - Mos semiconductor device: While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor for increasing both MOS currents. In the MOS semiconductor...

20060163648 - Semiconductor component: A semiconductor component that is able to be produced simply, quickly, and yet reliably and that usable for power applications, and including a semiconductor chip, a lower, first main electrode layer formed on a first side of the semiconductor chip, a lower control electrode layer formed on the first side,...

20060163649 - Insulated gate semiconductor device and method of manufacturing the same: A trench MOSFET includes mesa regions between the trenches. The mesa regions are connected to an emitter electrode to fix the mesa region potential so that the mesa regions do not form a floating structure. P-type base regions are distributed in the mesa regions, and the distributed p-type base regions...

20060163650 - Power semiconductor device with endless gate trenches: A power semiconductor device which includes endless gate trenches....

20060163651 - Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor: The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate...

20060163653 - Semiconductor device: To present a semiconductor device capable of operating stably even at large current, by lessening current concentration into the corners of contact opening after switching off and suppressing local heat generation without raising the ON voltage. In an insulated gate transistor divided by P field region 111 and gate electrode...

20060163652 - Semiconductor device with sense structure: A power semiconductor device is described with a plurality of cells divided into power cells (14) and sense cells (16). A plurality of groups (30, 32) of sense cells (16) are provided. The device allows for compensation of effects caused at the edges of the groups of sense cells (16)....

20060163655 - Semiconductor device: An exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more compounds of the formula AxBxOx, wherein each A is selected from the group of Cu, Ag, Sb, each B is selected from the group of Cu, Ag, Sb, Zn, Cd, Ga, In,...

20060163654 - Silicon-on-insulator device: A Silicon on Insulator (SOI) device is disclosed wherein an extension of P-type doping (303) is implanted between the buried oxide layer of the device and the SOI layer. The extension is of a size and shape to permit the source (309) to be biased at a voltage significantly less...

20060163656 - Nonvolatile memory device with curved floating gate and method of fabricating the same: Disclosed is a nonvolatile memory device comprising: a tunnel oxide layer on a semiconductor substrate; a floating gate on the tunnel oxide layer; a gate interlevel insulation layer on the floating gate layer; a control gate on the gate interlevel insulation layer; a source region at a side of the...

20060163657 - Method to reduce leakage in a protection diode structure: A protection diode is used in a CMOS integrated circuit device to direct charged particles to benign locations and prevent damage to the device. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region...

20060163658 - Monolithic mosfet and schottky diode for mobile phone boost converter: A cell phone has a plurality of interconnected electronic components for performing the electrical functions of the phone. A DC/DC converter provides an operating voltage which is applied to power supply terminals of the plurality of interconnected electronic components. The DC/DC converter uses a monolithic semiconductor device containing a power...

20060163659 - Compound semiconductor switch circuit device: A high-resistance element is connected as a part of a control resistor between a control terminal pad and a protecting element, immediately near the control terminal pad. Thus, even if a high-frequency analog signal leaks to the control resistor, the leaked signal is attenuated by the high-resistance element. This substantially...

20060163660 - Electrostatic discharge (esd) protection circuit: An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs) each with a floating base and a metal oxide semiconductor (MOS) field transistor with a floating body is disclosed. The three transistors may be connected in parallel between a bond...

20060163663 - Metal gate engineering for surface p-channel devices: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in...

20060163661 - Selective doping and thermal annealing method for forming a gate electrode pair with different work functions: A semiconductor product and a method for fabricating the semiconductor product provide a pair of gate electrodes formed with respect to a pair of doped wells within a semiconductor substrate. One of the gate electrodes is formed of a first gate electrode material having a first concentration of an electrically...

20060163662 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate; a first gate electrode formed on the first gate insulation film and fully silicided; and a second gate electrode formed on the second...

20060163664 - Semiconductor device and manufacturing process thereof: The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is...

20060163665 - Dummy patterns in integrated circuit fabrication: An embodiment of the invention provides a semiconductor integrated circuit device having a dummy pattern for improving micro-loading effects. The device comprises an active region in a substrate and an isolation region in the substrate adjacent the active region. A plurality of dummy patterns are formed over the isolation region,...

20060163666 - Semiconductor integrated circuit having resistor: A semiconductor integrated circuit having a resistor is disclosed in which the resistor is formed by a series connection of one element having a positive temperature coefficient and another element having a negative temperature coefficient....

20060163667 - Mos transistors having low-resistance salicide gates and a self-aligned contact between them and method of manufacture: A method for forming a self-aligned contact between two MOS transistors is described. The method supports the use of low-resistivity suicides for the formation of contacts in nanometer applications that employ polycide techniques. Silicon nitride and photoresist material act as dual masks in the formation of the self-aligned contact....

20060163668 - Semiconductor device and method for manufacturing same: In the method for manufacturing the semiconductor device including a salicide film, prior to the process for forming the salicide film (S30), the operation for protecting the oxide film is conducted in order to prevent the scattering of the oxide film on silicon substrate (S10). Then, the operation for cleaning...

20060163669 - Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby: A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region...

20060163670 - Dual silicide process to improve device performance: A semiconducting structure and a method of forming thereof, includes a substrate having a p-type device region and an n-type device region; a first-type suicide contact to the n-type device region; the first-type suicide having a work function that is substantially aligned to the n-type device region conduction band; and...

20060163671 - Silicide cap structure and process for reduced stress and improved gate sheet resistance: A suicide cap structure and method of fabricating a suicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and...

20060163672 - High performance cmos device design: A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second...

20060163673 - Method and structure for providing tuned leakage current in cmos integrated circuits: A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjacent to the gate region, wherein the gate oxide layer...

20060163674 - Metal oxide semiconductor field effect transistor and method of fabricating the same: There are provided a MOSFET and a method for fabricating the same. The MOSFET includes a semiconductor substrate, a first epitaxial layer in a predetermined location of the semiconductor substrate, a second epitaxial layer doped with high concentration impurity ions on the first epitaxial layer, a gate structure on the...

20060163675 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film, a...

20060163676 - Insulating film and semiconductor device: An insulating film includes an oxide or an oxynitride of a constituent element having a positive valence. The oxide or the oxynitride contains an additive element having a larger valence than the constituent element in a range not less than 3×10−8 at % and less than 1.6×10−3 at %....

20060163677 - Methods of forming a semiconductor device having a metal gate electrode and associated devices: Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon...

20060163678 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device is provided which has insulating film side wall spacers having a barrier function. The semiconductor device comprises: a gate oxide film and a gate electrode formed on and above a semiconductor substrate; source/drain regions formed in the semiconductor substrate; and first laminated side wall spacers having two...

20060163679 - High performance mems packaging architecture: An apparatus and method for sensor architecture based on bulk machining of Silicon-On-Oxide wafers and fusion bonding that provides a symmetric, nearly all-silicon, hermetically sealed MEMS device having a sensor mechanism formed in an active semiconductor layer, and opposing silicon cover plates each having active layers bonded to opposite faces...

20060163680 - Micro-machined medical devices, methods of fabricating microdevices, and methods of medical diagnosis, imaging, stimulation, and treatment: A medical device may include a micro-machined substrate, at least one thermo-electric assembly associated with the substrate, and a cooling system configured to configured to remove heat from the a region of the substrate proximal the substrate. According to various aspects, a method of clearing plaque from a blood vessel...

20060163681 - Gallium-nitride based ultraviolet photo detector: A structure for a gallium-nitride (GaN) based ultraviolet photo detector is provided. The structure contains an n-type contact layer, a light absorption layer, a light penetration layer, and a p-type contact layer, sequentially stacked on a substrate from bottom to top in this order. The layers are all made of...

20060163682 - Semiconducting photo detector structure: An epitaxial structure for semiconducting photo detectors is provided. The epitaxial structure contains a substrate having a built-in electric circuit, a first and second metallic layers on top of said substrate electrically connected to the corresponding electrical input and output points of the substrate's electric circuit, and a semiconducting photo...

20060163683 - Luminescent body and optical device including the same: A luminous body of prolonged fluorescence lifetime characterized by comprising not only an activator but also at least one coactivator selected from the group consisting of La, Ce, Pr, Nd, Sm, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Bi, Sn, Sb and analogues thereof as a further luminescent center...

20060163684 - Solid-state image pickup apparatus: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel...

20060163685 - Thermo-mechanical cleavable structure: A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and...

20060163686 - Novel process to improve programming of memory cells: A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of...

20060163687 - Structure and method for mixed-substrate simox technology: The present invention provides a semiconductor structure that includes a substrate having a crystal lattice; a first structure formed in a first region of the substrate, the first structure includes at least a heterostructure that generates a lattice stress in said crystal lattice in the first region; and a second...

20060163688 - Multiple layer structure for substrate noise isolation: A method of forming a semiconductor structure, comprising: providing a substrate having a buried insulative layer and a heavily doped layer; forming a first trench within the substrate around a protected area; filling the first trench with an insulative material, wherein the first trench filled with the insulative material and...

20060163689 - Semiconductor device having reduced die-warpage and method of manufacturing the same: A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire surface of the substrate. A stress-relieving pattern exists in and traverses the first layer so as to partition the first layer...

20060163690 - Semiconductor having thick dielectric regions: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second mesas. The method also includes oxidizing sidewalls and bottoms of each...

20060163691 - High voltage sensor device and method therefor: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element....

20060163693 - Chip-type noise filter, manufacturing method thereof, and semiconductor package: In a chip-type noise filter having a signal line of a conductor and a magnetic body disposed so as to adhere to the signal line, the magnetic body is a sintered body containing mainly Fe2O3 and containing NiO in the rest. This enables to effectively absorb and damp noise of...

20060163692 - Inductive and capacitvie elements for semiconductor techinologies with minimum pattern density requirements: The present invention provides a semiconductor device comprising a plurality of layers, the semiconductor device comprising:—a substrate having a first major surface,—an inductive element fabricated on the first major surface of the substrate, the inductive element comprising at least one conductive line, and—a plurality of tilling structures in at least...

20060163695 - Inductors for integrated circuits: An inductor for an integrated circuit or integrated circuit package comprises a three-dimensional structure. In one embodiment the inductor is arranged on an integrated circuit substrate in at least two rows, each row comprising upper segments and lower segments, with the upper segments being longer than the lower segments. The...

20060163694 - Semiconductor device having spiral-shaped inductor: An element isolation region is formed in a surface region of a semiconductor substrate. A spiral-shaped inductor is formed above the element isolation region. A conductive region to which a constant potential is applied is formed inside the inner circumference of the inductor....

20060163697 - Bipolar transistor and related method of fabrication: Disclosed are a bipolar transistor comprising an emitter terminal and a base terminal having substantially equal heights, and a method of fabricating the same. The bipolar transistor comprises a silicon-germanium layer acting as a base and formed on a semiconductor layer acting as a collector. The bipolar transistor further comprises...

20060163696 - Metal base transistor and oscillator using the same: The most important task in realizing a downsized and low cost THz band spectroscopic and fluoroscopic instrument is to achieve downsizing and cost reduction of oscillators used in the instrument. A metal base transistor is used for an active element of the oscillator. In order to improve the maximum oscillation...

20060163698 - Method and apparatus for wafer to wafer bonding: Inter-wafer structures are formed using semiconductor fabrication methods so as to provide precise, uniform distance between die on a bottom wafer and die on a top wafer. An inter-wafer structure layer is patterned to form one or more inter-wafer structures surrounding an active circuit area on a bottom die, or...

20060163701 - Scribe-line structures and methods of forming the same: Scribe-line structures and methods of forming such scribe-line structures on a face of a semiconductor substrate are provided. By means of the scribe-line structures and the methods of this invention, physical shock and cracking tendencies along a semiconductor substrate can be minimized during performance of a cutting process on the...

20060163700 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation...

20060163699 - Semiconductor wafer, semiconductor device manufacturing method, and semiconductor device: A plurality of semiconductor elements and division regions are provided on a semiconductor substrate. A modification region is provided in the semiconductor substrate. A division guide pattern is provided at least in a portion of each division region. A cleavage produced from a starting point corresponding to the modification region...

20060163702 - Chip on board leadframe for semiconductor components having area array: A leadframe for semiconductor components includes leadfingers, interconnect bonding sites for wire bonding to a semiconductor die, terminal bonding sites for terminal contacts for the component in an area array, and bus bars which electrically connect selected leadfingers to one another. The interconnect bonding sites are located on the leadframe...

20060163703 - Lead frame and method of producing the same, and resin-encapsulated semiconductor device and method of producing the same: A resin-encapsulated semiconductor device includes a semiconductor chip, a plurality of inner leads that are connected to a group of electrodes of the semiconductor chip, respectively, and an encapsulating resin that encapsulates a connection part located between the semiconductor chip and the inner leads. Each of the inner leads includes...

20060163704 - Chip package and producing method thereof: A chip package including a carrier, a chip, a stiffener and a molding compound is provided. A producing method of the chip package includes the steps of disposing a bottom surface of the chip on the carrier; covering an edge of a top surface of the chip with the stiffener...

20060163705 - Surface mount semiconductor device: A surface mount semiconductor device using a lead frame can suppress stress applied to a package by a load in a forming process performed for the lead frame projecting from the package at a portion at which the lead frame projects the package. Concave portions can be provided in at...

20060163706 - Bilayer aluminum last metal for interconnects and wirebond pads: A method for connecting a microelectronic device to a wirebond comprises providing a substrate having a microelectronic circuit therein and forming a wiring layer over the substrate. The wiring layer includes a bilayer wiring structure comprising upper and lower electrically conductive layers separated by a protective electrically conductive layer. The...

20060163709 - Chip-scale monolithic load switch for portable applications: A chip-scale package houses a monolithic semiconductor die containing first and second lateral metal oxide semiconductor field effect transistors (MOSFETs) formed on a surface of the semiconductor die. The MOSFETs are formed using a lateral double diffused metal oxide semiconductor structure. The first MOSFET has a first conduction terminal coupled...

20060163707 - Method and apparatus for reducing stresses applied to bonded interconnects between substrates: A method (200) is provided for reducing stresses applied to one or more bonded interconnects (106) of a substrate (103) and a PCB (Printed Circuit Board) (104). The method comprises the steps of coupling (204) a compound (108) on a top surface of the substrate, wherein the compound has the...

20060163708 - Semiconductor device: A semiconductor device comprises: an envelope having a thermal conductivity; a semiconductor dies placed inside the envelope; and a sealing cap disposed so as to cover the envelope and having a thermal conductivity. The envelope is provided with a lead connection portion including a lead wire and a dies receiving...

20060163710 - Semiconductor device and manufacturing method thereof: A technique for manufacturing a low-cost, small volume, and highly integrated semiconductor device is provided. A characteristic of the present invention is that a semiconductor element formed by using a semiconductor thin film is transferred over a semiconductor element formed by using a semiconductor substrate by a transfer technique in...

20060163711 - Method to form an electronic device: An electronic device includes a substrate and at least one electronic component formed on the substrate. The device also includes a lid coupled to the substrate, in which the lid at least partially covers the electronic component. The lid is partially trenched using one or more micro-blasting processes....

20060163712 - System and method for direct-bonding of substrates: A MEMS package includes a first substrate having a bonding surface and a second substrate having a polished bonding surface facing the bonding surface of the first substrate. The MEMS package further includes a polished layer of bonding substrate material deposited onto the bonding surface of the first substrate and...

20060163713 - Semiconductor device: In an SiP constituted by laminating a plurality of chips, it is an object to reduce a thickness of the SiP without damaging a strength of a chip on an upper side and deteriorating a reliability due to dicing in the case in which the chip on the upper side...

20060163714 - Package structure and fabrication method thereof: A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the...

20060163715 - Flip chip interconnection pad layout: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate...

20060163716 - Semiconductor package with crossing conductor assembly and method of manufacture: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having...

20060163717 - Method for connection of an integrated circuit to a substrate, and a corresponding circuit arrangement: The present invention provides a method for connection of an integrated circuit (1), in particular of a chip, a wafer or a hybrid, to a substrate (10), which has the following steps: provision of an elastic intermediate layer (5) on the integrated circuit (1) and/or the substrate (10); structuring of...

20060163718 - Flexible wiring base material and process for producing the same: The flexible wiring substrate 10 includes an insulating substrate 11, a wiring pattern 12 formed on a surface of the insulating substrate 11, and a solder resist layer 17 covering a surface of the wiring pattern 12 excluding at least terminal portions of the wiring pattern 12, at least a...

20060163719 - Semiconductor device and method of manufacturing a semiconductor device: There is provided a semiconductor device including, a bed, a brazing filler metal formed on a first surface of the bed, a barrier metal film formed on a first surface of the brazing filler metal, a alloy film formed on a first surface of the barrier metal film, a semiconductor...

20060163720 - Semiconductor device: A semiconductor device is provided with a sealing ring 106 made of a metal which surrounds an integrated circuit part 102 and which is formed on a substrate 104 along an outer perimeter of the rectangular device. At least one corner part 108 of the sealing ring is formed to...

20060163721 - Electronic assembly with reduced leakage current: An electronic assembly includes a substrate and at least one surface mounted electronic component. The substrate includes a first side and a second side opposite the first side. The first side of the substrate includes a plurality of conductive traces formed thereon. The plurality of conductive traces includes a first...

20060163723 - Bump-less chip package: A bump-less chip package is provided. The bump-less chip package includes a chip, an interconnection structure and a panel-shaped component. The panel-shaped component has a plurality of electrical terminals on a first surface thereof. The back surface of the chip is disposed on the first surface of the panel-shaped component,...

20060163724 - Display apparatus: In a display apparatus, a display panel receives a driving signal from a driving chip through a pad and displays an image in response to the driving signal. The driving chip includes a terminal outputting the driving signal. The driving chip is mounted on the display panel using the anisotropic...

20060163722 - Semiconductor chip electrical connection structure: A semiconductor chip electrical connection structure includes electrode pads formed on a surface of a semiconductor chip, wherein the semiconductor chip is mounted via another surface thereof on a carrier; a plurality of conductive bumps formed on the electrode pads respectively, and exposed from a dielectric layer applied on the...

20060163726 - Spaced, bumped component structure: A spaced, bumped component structure including a first plate, a second plate spaced from the first plate by a first gap, a plurality of solder bumps interconnecting the plates and defining the first gap; at least one of the plates having an anomalous section including one of a raised platform...

20060163725 - Wiring board and production method thereof: It is an object of the present invention to provide a wiring board having high-density wiring with a controlled shape without masking by a resist film and a production method thereof. In the present invention, the production method of a wiring board having copper wiring on an insulating substrate includes...

20060163727 - Semiconductor device: The present invention relates to semiconductor devices. According to the present invention a semiconductor device is described, comprising: a substrate for carrying a semiconductor chip on a first surface of said substrate; said semiconductor chip being punctually attached to said substrate on said first surface of said substrate via a...

20060163728 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device includes: a semiconductor chip having a plurality of electrode pads formed on a principal surface thereof; a sealing resin, which covers both (i) side surfaces of the semiconductor chip and (ii) a surface of the semiconductor chip opposite to the principal surface; and external connection pads, which...

20060163729 - Structure and manufacturing method of a chip scale package: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip...

20060163732 - Copper interconnect systems which use conductive, metal-based cap layers: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least...

20060163731 - Dual damascene interconnections employing a copper alloy at the copper/barrier interface: A method of fabricating a dual damascene interconnection is provided. The method begins by forming on a substrate a dielectric layer and forming a via in the dielectric layer. The dielectric layer is partially etched to form a trench, which is connected to the via and in which interconnections will...

20060163730 - Electronic device and its manufacturing method: A first nitrogen-containing insulating film is formed under a low dielectric constant film, in which a via hole is formed, with a first nitrogen-non-containing insulating film interposed between the first nitrogen-containing insulating film and the low dielectric constant film. A second nitrogen-containing insulating film is formed over the low dielectric...

20060163733 - Semiconductor structure having multilayer of polysilicon and display panel applied with the same: A semiconductor structure includes a substrate, a first polysilicon (polysilicon) region, a second polysilicon region, an insulating layer and a third polysilicon region. The first and second polysilicon regions are formed on the substrate and spaced apart by a gap. The insulating layer formed on the substrate covers the first...

20060163735 - Damascene process at semiconductor substrate level: A damascene structure and process at semiconductor substrate level. A pre-metal dielectric layer is provided on a semiconductor substrate with an opening exposing a contact region on the substrate. A buffer metal layer is provided on the exposed contact region, and a barrier layer is provided on the interior of...

20060163734 - Fuse structure and method for making the same: Provided are a fuse structure and a method for manufacturing the fuse structure. In one example, the method includes providing a multilayer interconnect structure (MLI) over a semiconductor substrate. The MLI includes multiple fuse connection and bonding connection features. A passivation layer is formed over the MLI and patterned to...

20060163737 - Interconnections for integrated circuits: An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects....

20060163736 - Interconnections having double capping layer and method for forming the same: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer...

20060163738 - Dual damascene structure and methods of forming the same: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side...

20060163739 - Semiconductor device and method for production thereof: Disclosed herein is a semiconductor device with improved electromigration durability and a method for producing the semiconductor device. A semiconductor device includes: an interlayer insulating film formed on a first metal wiring; a second metal wiring formed by embedding in the interlayer insulating film; a metal contact formed by embedding...

20060163740 - Semiconductor mounting board: A semiconductor mounting board 80 is prepared by electrically joining an IC chip 70 via an interposer 60 of high rigidity to external pads 41 and internal pads 43, which are formed on the uppermost surface of a build-up layer 30. When the IC chip 70 generates heat, since pads...

20060163741 - Tft array panel and fabricating method thereof: A TFT array panel including a lower aluminum layer, an aluminum nitride layer formed on the lower aluminum layer, and an upper aluminum layer formed on the aluminum nitride layer is presented. This TFT array panel including an aluminum wiring line reduces or even prevents the formation of a hillock...

20060163742 - Semiconductor component with passivation layer: A semiconductor component has a semiconductor body and also a metal/insulation structure arranged above the semiconductor body and having a plurality of metal regions and insulation regions laterally adjoining one another. The metal regions serve for supplying the semiconductor body with electric current. Furthermore, the semiconductor component has a passivation...

20060163744 - Printable electrical conductors: An electrical conductor formed from one or more metallic inks. The electrical conductor comprises a network of interconnected metallic nodes. Each node comprises a metallic composition, e.g., one or more metals or alloys. The network defines a plurality of pores having an average pore volume of less than about 10,000,000...

20060163745 - Semiconductor device: In a semiconductor device according to the present invention, a first bare chip, and a second bare chip having a wider principal surface than that of the first bare chip are connected to one principal surface and the other principal surface of an interposer substrate, respectively. In the semiconductor device,...

20060163743 - Semiconductor device and method for manufacturing the same, and electric device: It is an object of the present invention to simplify steps needed to process a wiring in forming a multilayer wiring. In addition, when a droplet discharging technique or a nanoimprint technique is used to form a wiring in a contact hole having a comparatively long diameter, the wiring in...

20060163747 - Assembly including a circuit and an encapsulation frame, and method of making the same: An assembly for a circuit board includes a substrate, at least one circuit component formed on the substrate, and a frame. The frame comprises a first substantially planar surface attached to the substrate, and a hole formed through the frame and defined by a wall that surrounds the at least...

20060163746 - Barrier structure for semiconductor devices: An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along...

20060163748 - Semiconductor device: The semiconductor device includes a semiconductor substrate, a diffusion layer, an interconnect layer, a contact plug, a contact-inspection hole, a via plug, and a via-inspection hole. Similarly to a contact plug hole, the contact-inspection hole extends from the diffusion layer to the interconnect layer. The opening of the contact-inspection hole...

20060163749 - Ic chip package structure and underfill process: A novel integrated circuit (IC) chip package structure and underfill process which reduces stress applied to corners of a flip chip in an IC package structure during the application of an adhesive material between the flip chip and a carrier substrate is disclosed. The process includes providing a dam structure...

20060163750 - Semiconductor device and method for producing the same: A semiconductor device provided with a stabilized hollow structure. A semiconductor device 1 having a semiconductor chip 3 flip chip-mounted on a substrate 2 includes a plate-shaped member 4 arranged on a surface of the semiconductor chip 3 opposite to its flip chipped surface. The plate-shaped member is protruded more...

20060163751 - Integrated circuit package encapsulating a hermetically sealed device: An integrated circuit package is disclosed having a semiconductor chip, a hermetically sealed device supported by the semiconductor chip, and a molding compound sealing the semiconductor chip and the device together as a composite package. A method of manufacturing the package is also disclosed....

20060163752 - Storage assembly: A gas storage assembly that has an enclosure within which are disposed at least about 100 inorganic tubules are present for each cubic micron of volume of the enclosure. The assembly has a storage capacity of at least 20 grams of hydrogen per liter of volume of the enclosure....

20060157679 - Structure and method for biasing phase change memory array for reliable writing: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory...

20060157681 - Horizontal chalcogenide element defined by a pad for use in solid-state memories: A process for fabricating phase-change elements having ultra small cross-sectional areas for use in phase change memory cells specifically and in semiconductor devices generally in which pads are implemented to create horizontally aligned phase change elements is disclosed. The elements thus defined may be used within chalcogenide memory cells or...

20060157680 - Semiconductor integrated circuit device: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising...

20060157683 - Nonvolatile phase change memory cell having a reduced thermal contact area: The invention provides for a nonvolatile memory cell comprising a heater layer in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volume assists this phase change. In the present invention, a...

20060157682 - Write-once nonvolatile phase change memory array: The invention provides for a write-once nonvolatile memory array, the memory cells comprising a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. The initial, unprogrammed state of each memory cell is a crystalline, low-resistance state, while the programmed state is an...

20060157684 - Thin film multilayer with nanolayers addressable from the macroscale: A thin film multilayer device having a multilayer stack formation including an array of electrically conductive or optically transmissive nanolayers separated by insulating layers. The nanolayers have one end with nanometer size and spacing, and another end with macro-sized tab sections through which the array of nanolayers may be individually...

20060157686 - Quantum dot phosphor for light emitting diode and method of preparing the same: Disclosed herein is a quantum dot phosphor for light emitting diodes, which includes quantum dots and a solid substrate on which the quantum dots are supported. Also, a method of preparing the quantum dot phosphor is provided. Since the quantum dot phosphor of the current invention is composed of the...

20060157685 - Semiconductor device method of manfacturing a quantum well structure and a semiconductor device comprising such a quantum well structure: Consistent with example embodiments a semiconductor device and a method are disclosed for obtaining on a substrate a multilayer structure with a quantum well structure. The quantum well structure comprises a semiconductor layer sandwiched by insulating layers, wherein the material of the insulating layers has preferably a high dielectric constant....

20060157688 - Methods of forming semiconductor constructions and integrated circuits: The invention includes a TFT-based logic circuit construction. Such construction includes a pair of first transistor devices, and a pair of second transistor devices over the first transistor devices. The first transistor devices have first active regions extending into a first semiconductive material, and the second transistor devices have second...

20060157687 - Non-planar mos structure with a strained channel region: An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate...

20060157689 - Forming a carbon layer between phase change layers of a phase change memory: A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized...

20060157691 - Memory device including dendrimer: A memory device including an organic material layer between an upper electrode and a lower electrode. The organic material layer includes a dendrimer containing at least one electron-donating group and at least one electron-accepting group. The disclosed memory device is advantageous in that it shows a nonvolatile property, has high...

20060157690 - Organic insulator, organic thin film transistor array panel including organic insulator, and manufacturing method therefor: m

20060157692 - Organic transistor and manufacturing method thereof: There is provided an organic transistor having a bottom gate structure, composed of a substrate, a gate electrode, a gate insulating layer, source and drain electrodes and an organic semiconductor layer, wherein the gate insulating layer is formed so as to have a low surface energy in a portion thereof...

20060157693 - Reactive mesogenic azulenes: The invention relates to new reactive mesogenic azulene derivatives, their use as semiconductors or charge transport materials, in optical, electro-optical or electronic devices like for example liquid crystal displays, optical films, organic field effect transistors (FET or OFET) for thin film transistor liquid crystal displays and integrated circuit devices such...

20060157695 - Electronic devices formed on substrates and their fabrication methods: The present invention relates to semiconductor electronic devices including molybdenum oxide formed on substrates which consist of materials which are used in known semiconductor electronic devices. The present invention relates to also a new method to fabricate said electronic devices on substrates made of materials which have been used in...

20060157694 - Metal oxide alloy layer, method of forming the metal oxide alloy layer, and methods of manufacturing a gate structure and a capacitor including the metal oxide alloy layer: A metal oxide alloy layer comprises a first layer including a first metal oxide and having a first thickness, and a second layer formed on the first layer, the second layer including a second metal oxide and having a second thickness, wherein a value of the first thickness is such...

20060157696 - Photonic devices formed on substrates and their fabrication methods: The present invention directed to photonic devices which emit or absorb light with a short wavelength formed using molybdenum oxide grown on substrates which consist of materials selected from element semiconductors, III-V or II-IV compound semiconductors, IV compound semiconductors, organic semiconductors, metal crystal and their derivatives or glasses. New inexpensive...

20060157703 - Charged plate,cdm simulator and test method: Disclosed is a simulator in which there are provided a field plate for electrostatically charging a device under test, which comprises a first substrate (high resistance substrate) having a relatively high resistance and a substrate having a predetermined dielectric constant; and a ground plate for discharging the charged device which...

20060157701 - Integrated sensor chip unit: The invention relates to a sensor module, in particular a measured-value pickup (2) for determining measurement data and a circuit arrangement (3) for enabling a wire-free power supply and interrogation of the measurement data. The measured-value pickup is formed as an integrable sensor (2), and the circuit arrangement is formed...

20060157702 - Kerf with improved fill routine: A semiconductor disk which exhibits chip areas arranged next to one another and separated from one another by a kerf. The chip areas in each case exhibit a multiplicity of similar device patterns, such that at least one fill area with fill patterns is arranged in the kerf, and the...

20060157698 - Semiconductor manufacturing system, semiconductor device and method of manufacture: A semiconductor manufacturing system for accurately recognizing the timing of maintenance of the system includes a processing chamber (101) and a movable member (107) moving in and out of the processing chamber (101). The movable member (107) has a sensor (106) for observing a state in the processing chamber (101)....

20060157700 - Semiconductor wafer with test structure: The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to one another in a second direction (Y), having useful regions (10) which in...

20060157697 - System and method for adjusting a manufacturing condition of an electronic device and method for manufacturing an electronic device: A system for adjusting a manufacturing condition of an electronic device includes: an inspection tool configured to inspect a plurality of protrusions on a substance layer for manufacturing an electronic device; a height calculation unit configured to calculate each of heights of the protrusions, based on the inspection result; and...

20060157699 - Test structure for integrated electronic circuits: A test structure for integrated electronic circuits having a substantially planar substrate coated with a plurality of metallization layers comprises a switching element formed on the surface of the substrate. It also comprises a tunnel formed in one or more metallization layers between the top of the switching element and...

20060157704 - Display device: The present invention provides a display device including a scanning line (3) formed on an insulating substrate, an auxiliary capacitance line (4), a signal line (8), a gate electrode (2) connected to the scanning line, a source electrode (7) connected to the signal line, a switching element (1) formed of...

20060157705 - Thin film transistor array panel: A thin film transistor array panel is provided, comprising: a gate line on an insulating substrate; a storage electrode line on the insulating substrate; a gate insulating layer over the gate line and the storage electrode line; a semiconductor layer on the gate insulating layer; a data line and a...

20060157708 - Single crystalline structure, method of forming the same, semiconductor device having the single crystalline structure, and method of manufacturing the semiconductor device: A single crystalline structure includes a first insulation interlayer pattern, a first epitaxial layer pattern, a second insulation interlayer pattern, and a second epitaxial layer pattern. The first insulation interlayer pattern includes a contact hole that exposes a single crystalline seed. The first epitaxial layer pattern fills up the contact...

20060157706 - Structure and method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels: The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact...

20060157707 - Thin film transistor: A thin film transistor, comprising a first N-type LDD (Lightly Doped Drain) and a second N-type LDD, is provided. The two N-type LDDs are formed in a semiconductor layer by tilted implantation with a gate electrode serving as a mask. The two N-type LDDs are adjacent to source/drain regions, respectively....

20060157710 - Sensor, thin film transistor array panel, and display panel including the sensor: A sensor is provided, which includes a substrate, an insulating layer formed on the substrate, a semiconductor formed on the insulating layer, an ohmic contact formed on the semiconductor, a sensor input electrode and a sensor output electrode formed on the ohmic contact, and a passivation layer formed on the...

20060157709 - Thin film transistor: A method of fabricating a TFT comprises: etching a base layer structure (9) on a substrate (1) so as to form a gate (4) with inclined side edges (4a, 4b) that extend towards an apex region (12) with a tip (13) of a radius of a few nanometers, depositing an...

20060157711 - Thin film transistor array panel: A thin film transistor (TFT) array display panel is provided, which includes: a substrate; a plurality of semiconductor islands formed on the substrate (including a plurality of transistor source, channel, and drain regions); a gate insulating layer covering the semiconductor islands; a plurality of gate lines (including gate electrodes overlapping...

20060157712 - Thin film transistor array panel and methods for manufacturing the same: Disclosed is a simplified method for manufacturing a liquid crystal display. A gate wire including a gate line, a gate pad, and a gate electrode are formed on a substrate. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited, and a photoresist layer is...

20060157713 - Structures formed in diamond: N-V centers in diamond are created in a controlled manner. In one embodiment, a single crystal diamond is formed using a CVD process, and then annealed to remove N-V centers. A thin layer of single crystal diamond is then formed with a controlled number of N-V centers. The N-V centers...

20060157716 - method of manufacturing semiconductor device: A semiconductor device has a two-dimensional slab photonic crystal structure in which a substrate supports a sheet-like slab layer including, sequentially stacked, a lower cladding layer, an active layer, and an upper cladding layer. A periodic refractive index profile structure, in surfaces of the stacked layers, introduces a linear defect...

20060157714 - Nitride semiconductor light emitting device: The present invention relates to a nitride semiconductor light emitting device including a plurality of nitride semi-conductor layers with a p-type nitride semiconductor formed using as nitrogen precursor ammonia together with hydrazine-based material which upon thermal decomposition generates a radical being combined with a hydrogen radical to eliminate the hydrogen...

20060157715 - Semiconductor device and method of manufacturing the same: A semiconductor device having a vertical gate and method of manufacturing the same are disclosed. An example semiconductor device includes a pair of first source/drain regions formed apart from each other by a predetermined distance on a silicon substrate, a first silicon epitaxial layer formed on the pair of first...

20060157717 - Light emitting device: A light emitting device having a simple structure that can be easily manufactured, attaining high light emitting efficiency stably for a long time is obtained, which light emitting device includes: a GaN substrate as a nitride semiconductor substrate and, on a first main surface of the nitride semiconductor substrate, an...

20060157718 - Gallium nitride-based light emitting device having esd protection capacity and method for manufacturing the same: A gallium nitride-based light emitting device, and a method for manufacturing the same are disclosed. The light emitting device comprises an n-type GaN-based clad layer, an active layer, a p-type GaN-based clad layer and a p-side electrode sequentially stacked on a substrate. The device further comprises an n-side electrode formed...

20060157719 - Semiconductor light emitting diode having textured structure and method of manufacturing the same: A semiconductor light emitting diode having a textured structure and a method of manufacturing the semiconductor light emitting diode are provided. The method includes forming a first semiconductor layer on a substrate; forming a textured structured first semiconductor layer by penetrating a material of a material layer into the first...

20060157723 - Light emitting device: A light emitting device has a resonant cavity LED (RCLED) (1) within encapsulation (24). The encapsulation has a convex spherical surface (26) forming a lens for emitted light. The diode's cavity (14, 15, 16) is of a length to provide detuning of 20 nm for an emission wavelength of 650...

20060157720 - Nanocrystals including iii-v semiconductors: Semiconductor nanocrystals including III-V semiconductors can include a core including III-V alloy. The nanocrystal can include an overcoating including a II-VI semiconductor....

20060157722 - Semiconductor light emitting device: Various semiconductor light emitting devices are described. In one aspect, the semiconductor light emitting device may include, an insulating substrate having an electrode pattern; a metal body provided on the insulating substrate, the metal body having a through-hole; an adhesive layer provided between the insulating substrate and the metal body;...

20060157721 - Systems and methods for producing white-light light emitting diodes: A vertical light emitting diode (LED) includes a metal substrate; a p-electrode coupled to the metal substrate; a p-contact coupled to the p-electrode; a p-GaN portion coupled to the p electrode; an active region coupled to the p-GaN portion; an n-GaN portion coupled to the active region; and a phosphor...

20060157725 - Led assembly having overmolded lens on treated leadframe and method therefor: An LED assembly is manufactured by providing a base on a leadframe, installing an LED within the base, and treating the leadframe with the base thereon to prepare for overmolding. A cover is overmolded onto the leadframe with the base thereon to encapsulate the LED....

20060157724 - Light-emitting diode, backlight device and method of manufacturing the light-emitting diode: A light-emitting diode includes a transparent substrate having a main surface and serving as a substrate, a light-emitting diode element mounted on the main surface, and a substantially semicylindrical resin sealing portion made of transparent resin and arranged on the main surface to sealingly cover the light-emitting diode element. The...

20060157726 - Semiconductor light emitting device mounting substrates including a conductive lead extending therein and methods of packaging same: A mounting substrate for a semiconductor light emitting device includes a thermally conductive mounting block. The mounting block has, in a first face thereof, a cavity that is configured to mount a semiconductor light emitting device therein and to reflect light that is emitted by the semiconductor light emitting device...

20060157727 - Semiconductor photodetector: A semiconductor photodetector which can achieve spectral sensitivity characteristics close to relative luminous characteristics at low cost while using a light receiving element of a semiconductor made from such as silicon, has a semiconductor light receiving element having high spectral sensitivity in a wavelength range between approximately 400 nm to...

20060157730 - Nitride-based semiconductor device of reduced voltage drop: A light-emitting device has a main semiconductor region formed via an n-type AlInGaN buffer region on a p-type silicon substrate, the latter being sufficiently electroconductive to provide part of the current path through the device. Constituting the primary working part of the LED, the main semiconductor region comprises an n-type...

20060157728 - Organic light-emitting device: An organic light-emitting device is provided, comprising a bottom electrode, at least two emissive units disposed on the bottom electrode, at least one charge-generation layer disposed between two adjacent emissive units, and a top electrode disposed on the emissive units. The charge-generation layer comprises fullerene or a derivative thereof, and...

20060157729 - Semiconductor device: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13...

20060157731 - Method of providing a cmos output stage utilizing a buried power buss: A method of providing a CMOS output stage is disclosed. The method includes providing a substrate, providing at least two wells above the substrate, providing a plurality of slots through the at least two wells into the substrate, oxidizing each of the plurality of slots, and filling each of the...

20060157732 - Fabrication of mos-gated strained-si and sige buried channel field effect transistors: A method of fabricating semiconductor heterostructures including the steps of: (a) positioning a silicon wafer in a suitable environment and (b) processing the silicon substrate by applying several processing steps. A first optional processing step includes growing a graded buffer layer on a silicon substrate by low-energy plasma-enhanced chemical vapor...

20060157733 - Complex oxides for use in semiconductor devices and related methods: in which the elemental oxide components, (AmOn) and (BqOr) are combined so that h=j or, equivalently, ma=bq, and a, b, h, j, k, m, n, q and r are non-zero integers; and wherein: A is an element of the lanthanide rare earth elements of the periodic table or the trivalent...

20060157734 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate....

20060157735 - Compound semiconductor device: At a gate electrode formed on a compound semiconductor layer with a Schottky junction, a diffusion preventing layer made of TixW1−xN (0<x<1) for suppressing the metal of a low-resistance metal layer from diffusing to the compound semiconductor layer is provided between a Ni layer forming a Schottky barrier with the...

20060157736 - Radiation hardened bipolar junction transistor: A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is formed on the first dielectric...

20060157737 - Semiconductor memory device: A semiconductor memory device comprises a cell region including a plurality of unit memory cells, and a peripheral circuit region, the peripheral circuit region including a plurality of peripheral circuit devices for operating the plurality of memory cells and at least one operating capacitor formed adjacent to at least one...

20060157738 - Semiconductor memory device and its manufacturing method: According to one aspect of the present invention, a semiconductor memory device has: a semiconductor layer formed on an insulating film; and a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of...

20060157739 - Semiconductor integrated circuit, layout method, layout apparatus and layout program: An intermediate wiring layer, lowermost vias and uppermost vias of a semiconductor integrated circuit are disposed within a zone of wiring tracks, which are superposed by wiring traces of an uppermost wiring layer and wiring traces of a lowermost wiring layer, as seen from the direction normal to the plane....

20060157740 - Semiconductor integrated circuit and method of manufacturing the same: A semiconductor integrated circuit (1) having an integrated circuit region (1a), and a plurality of I/O cells (6) each having an element formation region for external electrical connection from the element formation region. An input/output signal electrode pad (3), a power supply electrode pad (4) and a GND electrode pad...

20060157743 - Borderless contact structures: A borderless contact structure and method of fabricating the structure, the method including: (a) providing a substrate; (b) forming a polysilicon line on the substrate, the polysilicon line having sidewalls; (c) forming an insulating sidewall layer on the sidewalls of the polysilicon line; (d) removing a portion of the polysilicon...

20060157741 - Semiconductor device including gate insulation film that is formed of pyroceramics, and method of manufacturing the same: A semiconductor device includes a gate insulation film that is formed of pyroceramics including an amorphous matrix layer, which is provided on a major surface of a silicon substrate, and crystalline phases lines with a high dielectric constant, which are dispersed in the amorphous matrix layer. The semiconductor device further...

20060157742 - Semiconductor device with epitaxial c49-titanium silicide (tisi2) layer and method for fabricating the same: The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of...

20060157744 - Method and circuit of plasma damage protection: A protection circuit to discharge plasma-induced charges in a semiconductor device or integrated circuit includes a PMOS transistor and a diode. The PMOS transistor includes a substrate, a drain, a source, and a gate, the source being coupled to receive the plasma-induced charges. The diode has a positive terminal coupled...

20060157745 - Vertical unipolar component with a low leakage current: A TMBS-type Schottky diode including main electrodes on active areas on the upper surface side and a main electrode on the lower surface side, including on the upper surface side conductive fingers penetrating between the active areas and biased, directly or indirectly, like the active areas. The fingers includes closer...

20060157746 - Cmos image sensor with asymmetric well structure of source follower: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the...

20060157749 - Fin-type semiconductor device with low contact resistance and its manufacture method: A semiconductor device comprises a fin-type semiconductor region (fin) on a support substrate, having a pair of generally vertical side walls and an upper surface coupling the side walls; an insulated gate electrode structure traversing an intermediate portion of the fin and having side walls in conformity with the side...

20060157747 - Forming field effect transistors from conductors: A nanotube transistor, such as a carbon nanotube transistor, may be formed with a top gate electrode and a spaced source and drain. Conduction along the transistor from source to drain is controlled by the gate electrode. Underlying the gate electrode are at least two nanotubes. In some embodiments, the...

20060157748 - Metal junction diode and process: A junction diode includes a substrate having first and second cathode regions separated by an anode region. Metal silicide layers contact the first and second cathode regions and the anode regions. The anode region has a doping concentration sufficient to create a depletion region in the anode region adjacent to...

20060157751 - Metal oxide semiconductor field effect transistor and method of fabricating the same: There are provided a MOSFET and a method for fabricating the same. The MOSFET includes a semiconductor substrate, a germanium layer formed by implanting germanium (Ge) ions into the semiconductor substrate, an epitaxial layer doped with high concentration impurities over the germanium layer, a gate structure on the epitaxial layer,...

20060157752 - Method of manufacturing semiconductor device having side wall spacers: Gate insulating films 12A and 12B of different thickness are formed in element openings 16a and 16b in the isolation film 16 of a wafer 10. The gate insulating film 12B is the thinnest gate insulating film. A dummy insulating film having the same thickness as the thinnest gate insulating...

20060157753 - Multi-bit nonvolatile memory devices and methods of manufacturing the same: Multi-bit nonvolatile memory devices and related methods of manufacturing the same are described. In some multi-bit nonvolatile memory devices, a semiconductor substrate has a recessed region defined therein. An insulating layer, which can include an ONO layer, is configured to store data within programming regions therein, and covers a sidewall...

20060157750 - Semiconductor device having etch-resistant l-shaped spacer and fabrication method thereof: Provided is a semiconductor device having an etch-resistant L-shaped spacer and a fabrication method thereof. The semiconductor device comprises a semiconductor substrate, a gate insulating layer formed on the semiconductor substrate, a gate electrode formed on the gate insulating layer, an L-shaped lower spacer conformally formed on sidewalls of the...

20060157754 - Semiconductor device including high-k insulating layer and method of manufacturing the same: A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected...

20060157755 - Transistor of volatile memory device with gate dielectric structure capable of trapping charges and method for fabricating the same: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure...

20060157757 - Image display device: The present invention provides an image display device which can enhance the overlapping positional accuracy of both substrates and can exhibit a prolonged lifetime and a high quality display by suppressing the generation of sparks. A plurality of island-like electrodes are arranged on a back substrate, the island-like electrodes are...

20060157756 - Solid-state imaging device and manufacturing method thereof: An object of the present invention is to provide a solid-state imaging device which can increase the amount of signal charge accumulation in a photodiode, and a manufacturing method thereof. The solid-state imaging device according to the present invention includes: a gate electrode formed on a p-type semiconductor substrate; an...

20060157759 - Image pickup device, its control method, and camera: An image pickup device, wherein a part of the carriers overflowing from the photoelectric conversion unit for a period of photoelectrically generating and accumulating the carriers may be flowed into the floating diffusion region, and a pixel signal generating unit generating a pixel signal according to the carriers stored in...

20060157758 - Image sensor and pixel having an optimized floating diffusion: An active pixel includes a a photosensitive element formed in a semiconductor substrate. A transfer transistor is formed between the photosensitive element and a floating diffusion and selectively operative to transfer a signal from the photosensitive element to the floating diffusion. The floating diffusion is formed from an n-type implant...

20060157761 - Image sensor with self-boosting and methods of operating and fabricating the same: Disclosed is a image sensor (e.g., a CMOS image sensor) including pixels each having a transfer transistor and a drive transistor, in which the gate of at least one of the transistors has a boosting gate disposed over it comprised of a conductive film pattern with interposing an insulation film....

20060157760 - Imaging apparatus and imaging method: An imaging apparatus using a solid-state image sensor that reads out a signal of each pixel by an XY address method to capture an image includes a mechanical shutter configured to block light incident on a light receiving surface of the solid-state image sensor; and control means for simultaneously resetting...

20060157763 - Feram device and method for manufacturing the same: An embodiment of the FeRAM includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer, and a top electrode. Strontium ruthenium oxide is formed between the bottom electrode and the ferroelectric layer and between the ferroelectric layer and the top electrode. A diffusion barrier layer including strontium ruthenium oxide...

20060157765 - Magnetic random access memory designs with controlled magnetic switching mechanism: An MRAM array is formed of MTJ cells shaped so as to have their narrowest dimension at the middle of the cell. A preferred embodiment forms the cell into the shape of a kidney or a peanut. Such a shape provides each cell with an artificial nucleation site at the...

20060157764 - Methods and apparatuses for producing a polymer memory device: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form...

20060157762 - Semiconductor device having ferroelectric capacitor and its manufacture method: A semiconductor device includes: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate and having an insulated gate and source/drain regions on both sides of the insulated gate; a ferroelectric capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode;...

20060157767 - Dynamic random assess memory circuitry and integrated circuitry: A method of forming a conductive contact to a conductive structure includes forming a conductive structure received within and projecting outwardly from a first insulative material. A second different insulative material is deposited. The second insulative material is anisotropically etched effective to form a sidewall etch stop for the conductive...

20060157766 - Metal-insulator-metal capacitor and method of fabricating the same: In a metal-insulator-metal (MIM) capacitor and a method of fabricating the MIM capacitor, a metal-insulator-metal (MIM) capacitor comprises: a lower electrode pattern which is formed on a substrate and includes a conductive layer having a portion as a lower interconnect; a dielectric layer on the lower electrode pattern; a first...

20060157768 - Semiconductor device and method for fabricating the same: In a method for fabricating a semiconductor device according to the present invention, gate injection for an n-type MIS transistor region is performed with an n-type decoupling capacitor region covered. Thus, compared to a known method, an n-type impurity concentration in a capacitor electrode in the n-type decoupling capacitor region....

20060157769 - Semiconductor device and method for fabricating the same: A semiconductor device of the present invention includes a plurality of lower electrodes covering the entire surfaces of a plurality of trenches formed in a first interlayer insulating film, a capacitive insulating film covering the entire surfaces of the plurality of lower electrodes, and an upper electrode covering the surfaces...

20060157770 - Metal-to-metal capacitor: A metal-to-metal capacitor including a plurality of first metal blocks formed apart from each other in a vertical direction and arranged in an array format, and a plurality of second metal blocks formed apart from each other in a vertical direction and alternately arranged with the array of the first...

20060157771 - Integrated circuit memory devices and capacitors having carbon nanotube electrodes and methods of forming same: An integrated circuit capacitor includes first and second electrodes and at least one dielectric layer extending between the first and second electrodes. The first electrode includes at least one carbon nanotube. The capacitor further includes an electrically conductive catalyst material. This catalyst material may be selected from the group consisting...

20060157773 - Non-volatile electrically alterable memory cell for storing multiple data and manufacturing thereof: A memory cell that includes two control gates disposed laterally between two floating gates where each floating gate is capable of holding data. The memory cell is formed by placing a first polysilicon on a substrate of semiconductor material, on which a well is placed. The control gates are preferably...

20060157772 - Nonvolatile memory device: Provided is a nonvolatile memory device including: a storage element; a switching element electrically connected to the storage element; and a plurality of lead wirings electrically connected to the switching element, all of which are arranged on a substrate having an insulating surface, wherein the switching element includes an organic...

20060157775 - Byte-operational nonvolatile semiconductor memory device: Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed...

20060157774 - Memory cell: A memory cell is provided as including a substrate, a tunneling dielectric layer, a charge trapping layer, an inter-gate dielectric layer, a metal gate layer, and a source/drain region. The source/drain region is formed in the substrate besides the gate structure that includes the tunneling dielectric layer, charge trapping layer,...

20060157777 - Semiconductor device doped with sb,ga or bi and method of manufacturing the same: A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in...

20060157776 - System and method for contact module processing: System and method for improving the process performance of a contact module. A preferred embodiment comprises improving the process performance of a contact module by reducing surface variations of an interlayer dielectric. The interlayer dielectric comprises a plurality of layers, a first layer (for example, a contact etch stop layer...

20060157778 - Semiconductor device: A power MOSFET includes an n-type drift layer and a p-type base layer formed in a layered manner on the n-type drift layer. Trench gates are formed to penetrate the p-type base layer to reach the n-type drift layer. On the p-type base layer, n+-type source regions and p+-type regions...

20060157779 - Semiconductor device and manufacturing method of the same: The on-resistance of a semiconductor device having a power transistor with a trench gate structure is reduced. A power MIS-FET with a trench gate structure is so formed that the relation expressed as 0≦b≦a holds, where a is the distance between an end of an interlayer insulating layer over the...

20060157780 - Semiconductor device and method for fabricating the same: The semiconductor device includes a first semiconductor region of a first conductivity type partially extending to a top face of a semiconductor substrate; a second semiconductor region of a second conductivity type formed on the first semiconductor region; a third semiconductor region of the first conductivity type formed on the...

20060157781 - Lateral double-diffused mos transistor and manufacturing method therefor: The lateral double-diffused MOS transistor includes a drift region of a first conductive type provided on a semiconductor substrate of a second conductive type, and a body diffusion region of the second conductive type formed on the surface within the drift region. The MOS transistor includes a gate electrode formed...

20060157782 - Trench fet with self aligned source and contact: A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the...

20060157784 - Mos field effect transistor and manufacture method therefor: A method of manufacturing an MOS field effect transistor, which achieves a faster operation and lower power consumption by using a thin film SOI structure, is provided. The method of manufacturing an MOS field effect transistor to be formed on a semiconductor substrate having a channel layer on a buried...

20060157786 - Semiconductor device and manufacturing method thereof: A semiconductor device of the present invention includes: an SOI substrate that is a semiconductor wafer on which a semiconductor active layer is formed via a laminated insulating film; an insulating film which is arranged in a device isolation region surrounding an element forming region of the SOI substrate, and...

20060157783 - Semiconductor device having trench isolation for differential stress and method therefor: A semiconductor device has trenches for defining active regions. After a thin diffusion barrier is deposited in the trenches, some of the trenches are selectively etched to leave different areas in the trench. One of the areas has the diffusion barrier completely removed so that the underlying layer is exposed....

20060157785 - Semiconductor storage device: According to the present invention, there is provided a semiconductor storage device having a memory cell, comprising: a buried electrode formed on a semiconductor substrate; a semiconductor layer formed on said buried electrode via a buried insulating film; a surface electrode formed on said semiconductor layer via an insulating film;...

20060157787 - Thin film transistor having double-layered gate electrode and method of manufacturing the thin film transistor: A thin film transistor (TFT) that can prevent damage to a silicon layer under a gate electrode in an annealing process by using a first gate electrode having high thermal resistance and a second gate electrode having high reflectance and a method of manufacturing the TFT are provided. The method...

20060157788 - Sram memories and microprocessors having logic portions implemented in high-performance silicon substrates and sram array portions having field effect transistors with linked bodies and methods for making same: The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concerns CMOS SRAM cell architectures where at least one pair of adjacent NFETs in an...

20060157789 - Semiconductor device with a cavity therein and a method of manufacturing the same: A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities....

20060157790 - Electrostatic discharge device integrated with pad: A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad...

20060157791 - Esd protection device: An ESD protection device. A first-type well is formed on an insulating layer. First and second second-type doped regions are formed on the first-type well. A first body-tie region is formed on the first-type well and is connected to one side of the first and the second second-type doped regions....

20060157792 - Laminated thin film capacitor and semiconductor apparatus: The laminated thin film capacitor has the configuration in which the electrode layers of one polarity 2a to 2c and the electrode layers of the other polarity 4a and 4b are alternately laminated on a supporting substrate 1 with the corresponding thin film dielectric layers 3a to 3d being sandwiched...

20060157793 - Mos field effect transistor and manufacture method therefor: A method of manufacturing an MOS field effect transistor which reduces a leak current between a source and a drain, thereby reducing power consumption in a standby mode, so that the power consumption can be reduced without impairing the fast operation of the transistor circuit. The method includes the steps...

20060157794 - Non-planar mos structure with a strained channel region: An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate...

20060157797 - Insulated gate field-effect transistor and a method of manufacturing the same: The invention aims at precisely making an effective junction depth sufficiently small with respect to a substrate surface having a steep PN junction stable in its configuration and having a channel formed therein in relation to an extension portion. Gate electrodes are formed on a P-type well and an N-type...

20060157796 - Semiconductor device having dual gate electrode and related method of formation: A dual gate electrode semiconductor device and related method of formation are disclosed. The semiconductor device comprises a first gate electrode made of a metal silicide layer and a second gate electrode made of a metal layer, wherein the metal suicide is formed from the same metal as the metal...

20060157795 - Structure and method to optimize strain in cmosfets: A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N...

20060157798 - Semiconductor device and method for manufacturing same: [Means for Solving Problems] MOSFETs are formed on a semiconductor substrate 1 in regions isolated by an element isolation film 2. A plurality of low-permittivity insulator rods including a low-permittivity insulator embedded therein and penetrating a first interlevel dielectric film 4 to reach the internal of the silicon substrate are...

20060157799 - Low trigger voltage, low leakage esd nfet: A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region...

20060157800 - Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology: A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-layer to a bi-silicide...

20060157801 - Nonvolatile semiconductor memory device and method for manufacturing the same: A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of...

20060157802 - Electric device using sold electrolyte: The present invention relates to a transistor for selecting a storage cell and a switch using a solid electrolyte. In a storage cell, a metal is stacked on a drain diffusion layer of a field-effect transistor formed on a semiconductor substrate surface. The solid electrolyte using the metal as a...

20060157803 - Conductive channel pseudo block process and circuit to inhibit reverse engineering: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the...

20060157804 - Field effect transistor and method for manufacturing the same: A first SiO2 thin film, a tungsten gate electrode, and a second SiO2 thin film are selectively formed on a first n+-type GaN contact semiconductor layer in that order and in a multilayer film structure having the three layers, a stripe-shaped opening is formed. Via the opening, an undoped GaN...

20060157805 - Structure and method of forming a notched gate field effect transistor: A structure and method of forming a notched gate MOSFET. A gate dielectric is formed on the surface of an active area on the semiconductor substrate. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium. The sidewalls...

20060157806 - Multilayered semiconductor susbtrate and image sensor formed thereon for improved infrared response: An image sensor is formed on a multilayered substrate to improve infrared response. The multilayered substrate uses a silicon-germanium alloy to improve infrared response. In one embodiment, the silicon-germanium alloy has a germanium concentration gradient such that an upper portion of the silicon-germanium alloy has a lower germanium concentration than...

20060157808 - Electronic component having micro-electrical mechanical system: An electronic component includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a cavity that penetrates from the first surface to the second surface of the semiconductor substrate, and an electrical mechanical element that has a movable portion formed above the first...

20060157807 - Three dimensional high aspect ratio micromachining: Multi-level structures are formed in a semiconductor substrate by first forming a pattern of lines or structures of different widths. Width information on the pattern is decoded by processing steps into level information to form a MEMS structure. The pattern is etched to form structures having a first floor. The...

20060157810 - Cpp magneto-resistive element, method of manufacturing cpp magneto-resistive element, magnetic head, and magnetic memory apparatus: A CPP magneto-resistive element includes a substrate and an antiferromagnetic layer, a fixed magnetic layer, a non-magnetic intermediate layer, and a free magnetic layer that are sequentially formed on the substrate, wherein the antiferromagnetic layer includes an alloy of Mn and at least one element of a group including Pd,...

20060157809 - Vertical hall effect device: A vertical Hall effect apparatus, including methods thereof. A substrate layer can be provided upon which an epitaxial layer is formed. The epitaxial layer is surrounded vertically by one or more isolation layers. Additionally, an oxide layer can be formed above the epitaxial layer. A plurality of Hall effect elements...

20060157811 - Fabrication of low leakage-current backside illuminated photodiodes: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or...

20060157812 - Infrared solid-state image pickup apparatus and a production method thereof: An infrared solid-state image pickup apparatus includes an SOI substrate having a silicon oxide film layer and an SOI layer on a silicon substrate, a detecting portion which is provided with a PN junction diode formed on the SOI substrate and converts a temperature change generated by an incident infrared...

20060157813 - Power semiconductor device and method of manufacturing the same: A power semiconductor device has a first main electrode formed along a surface of a substrate, a first semiconductor layer of first conductive type electrically connected to the first main electrode, a cyclic structure section which is formed on the first semiconductor layer and has second semiconductor layers of first...

20060157814 - Circuit structures and methods of forming circuit structures with minimal dielectric constant layers: An apparatus including a contact point formed on a device layer of a circuit substrate or an interconnect layer on the substrate; a first dielectric material; and a different second polymerizable dielectric material on the substrate and separated from the device layer or the interconnect layer by the first dielectric...

20060157815 - Integrated circuit including power diode: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor...

20060157816 - Isolation structure in field device: A semiconductor device. The semiconductor device comprises an isolation structure and two heavily doped regions of a second conductivity type spaced apart from each other by the isolation structure. The isolation structure comprises an isolation region in a semiconductor substrate and a heavily doped region of the first conductivity type....

20060157817 - Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode: A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed...

20060157818 - Modular bipolar-cmos-dmos analog integrated circuit and power transistor technology: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of...

20060157819 - Efuse structure: A surface of a semiconductor substrate comprises at least one electrical conduction structure and at least one eFuse. The electrical conduction structure comprises a first poly silicon layer and a first poly silicide layer formed in the first poly silicon layer. The eFuse comprises a second poly silicon layer and...

20060157820 - Production of an integrated capacitor: A process for producing a capacitor integrated into an electronic circuit comprises the formation of a trench in a substrate through a conductive portion similar to an MOS transistor gate. Alternating conductive, insulating and conductive layers are deposited inside the trench T in order to form a lower electrode, a...

20060157821 - Spray coating of cathode onto solid electrolyte capacitors: A process for forming a capacitor. The process includes the steps of forming an anode of a valve metal. A dielectric layer is formed on the valve metal. A conducting layer is formed on the dielectric layer wherein the conducting layer is the cathode. A carbon layer is sprayed onto...

20060157822 - Semiconductor integrated circuit having a reduced parasitic capacitance and short start-up time: A semiconductor integrated circuit that includes a circuit element with a reduced parasitic capacitance and has a short start-up time. A well of the different type of conduction from that of the substrate is formed in the area of the surface of the semiconductor substrate under the circuit element. A...

20060157823 - High performance integrated vertical transistors and method of making the same: A complementary bipolar transistor is fabricated using an available a portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors...

20060157824 - Semiconductor device and method having multiple subcollectors formed on a common wafer: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices...

20060157825 - Semiconductor device and manufacturing the same: The invention is directed to improve resistance to destruction of a semiconductor device. A protection circuit having a plurality of bipolar transistors which are Darlington connected between outputs (collector and emitter) of an amplification circuit of a high output is electrically connected in parallel with the amplification circuit. The amplification...

20060157826 - Multi-path printed circuit board having heterogeneous layers and power delivery system including the same: A multi-path printed circuit board (PCB) comprising separate direct current (DC) and alternating current (AC) paths, and a power delivery system including the same are provided. The multi-path PCB comprises a plurality of planar layers, each comprising a metal layer, and a plurality of insulators interposed between the planar layers....

20060157827 - Semiconductor device, display module, and manufacturing method of semiconductor device: A semiconductor device is provided that includes wiring patterns on a substrate formed of an organic insulating film, and a semiconductor chip mounted on the substrate. A liquid crystal display panel and a PW board are electrically connected to each other with an anisotropic conductive adhesive. At least one surface...

20060157829 - Lead frame, semiconductor device comprising the lead frame and method of manufacturing a semiconductor device with the leadframe: A semiconductor element (3) is mounted on a flat lead frame (11, 11 A) which is provided with two connection conductors (4, 5) in between which the element (3) is attached, and the element (3) is positioned on the first conductor (4) and the second conductor is brought to a...

20060157828 - Leadframe - based housing, leadframe strip, surface - mounted optoelectronic -component, and production method: The invention describes a leadframe-based housing for a surface-mountable component, particularly a radiation-emitting component. Said leadframe-based housing comprises electrical connector strips and at least one chip mounting area, and provided according to the invention in one of the connector strips is an injection aperture that enables a leadframe-based housing to...

20060157830 - Semiconductor package using flexible film and method of manufacturing the same: A semiconductor package and a method of manufacturing the same: The package includes a substrate, an external connection terminal portion on at least one edge thereof; a semiconductor chip bonded to the substrate, the semiconductor chip including a plurality of bonding pads; and a flexible film, which electrically connects the...

20060157831 - Low profile ball-grid array package for high power: A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder...

20060157838 - Multimedia card and transfer molding method: A semiconductor card is made using a method which, in one molding step, forms a plastic body on a substrate attached to a surrounding frame by narrow connecting segments spanning a peripheral opening. The connecting segments are motivated downward by pins outside of the card periphery, holding the substrate against...

20060157834 - Plastic molding die: A plastic molding die provided with a cavity where a plastic material is put in, wherein a part of an inner surface of the cavity is configured with an elastic body. A molding portion corresponding to a molding surface of a molded product is disposed on the inner surface of...

20060157832 - Printed circuit board including embedded chips and method of fabricating the same: A printed circuit board having embedded chips, composed of a central layer having an embedded chip, an insulating layer formed on one surface or both surfaces of the central layer and having a via hole filled with conductive ink, and a circuit layer formed on the insulating layer and having...

20060157835 - Semiconductor device and method of fabricating same: A semiconductor device has a bottomless package and a semiconductor chip. The semiconductor chip is disposed in a chip installation-side opening in a chip storage space of the package. The semiconductor device also has a sealing lid that lies opposite the upper face of the semiconductor chip and covers the...

20060157833 - Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device: A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (≧2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in...

20060157837 - Solid state image pickup device and its manufacture method: PROBLEM To provide a high quality solid state image pickup device. SOLUTION Impurities are implanted into a semiconductor substrate to form vertical transfer channels for transferring electric charges in a first direction and to form a drain near each of the vertical transfer channels via a gate which forms a...

20060157836 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a thin film transistor including a gate electrode, a drain electrode, a source electrode and a semiconductor on a substrate; forming a first passivation layer on the drain and the source electrodes; forming a transparent...

20060157839 - Re-assembly process for mems structures: Methods of fabricating an array of aligned microstructures on a substrate are disclosed. The microstructures may be spring contacts or other microelements. The methods disclosed include construction of an alignment substrate, alignment of die elements with the alignment substrate, and fixation of the aligned die elements to a backing substrate....

20060157840 - High temperature interconnects for high temperature transducers: A silicon wafer is fabricated utilizing two or more semiconductor wafers. The wafers are processed using conventional wafer processing techniques and the wafer contains a plurality of output terminals which essentially are platinum titanium metallization or high temperature contacts. A glass cover member is provided which has a plurality of...

20060157841 - Miniature silicon condenser microphone and method for producing the same: A silicon condenser microphone package includes a transducer unit, a substrate, and a cover. The substrate includes an upper surface transducer unit is attached to the upper surface of the substrate and overlaps at least a portion of the recess wherein a back volume of the transducer unit is formed...

20060157842 - Inverted csp stacking system and method: Two or more integrated circuits are stacked into a high density circuit module. The lower IC is inverted. Electrical connection to the integrated circuits is made by module contacts on a flexible circuit extending along the lower portion of the module. In one embodiment, the flexible circuit provides a balanced...

20060157843 - Stacked semiconductor package having interposing print circuit board: A stacked semiconductor package including a number of solder ball pads formed on a lower surface of an interposing print circuit board, which is smaller than that of solder ball pads formed on an upper surface thereof, a pitch of the solder ball pads formed on the lower surface of...

20060157844 - Electrode structure, part mounting structure and liquid crystal display unit equipped with the part mounting structure: An electrode structure includes at least a contact button portion that has a portion of multilayer structure of two or more conductor layers stacked and enlarged in area. A part mounting structure includes a substrate, a contact button portion which is formed on the substrate and on which a part...

20060157845 - Semiconductor device: When an integrated circuit is formed in a semiconductor wafer, the integrated circuit is formed only in the central part of each chip region. In a case where packaging other than a chip size package is made, only the central part in which the integrated circuit is formed is cut...

20060157846 - Multi-surface ic packaging structures and methods for their manufacture: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated....

20060157847 - Chip package: A chip package is provided. The chip package includes at least one chip, an interconnection structure, a plurality of second pads and at least one panel-shaped component, wherein the chip includes a plurality of first pads on a surface thereof. The interconnection structure is disposed on the chip, and the...

20060157848 - Structure and method for joining a semiconductor package to a substrate using solder column: In one embodiment, a semiconductor package and a package mounting substrate are joined using a conductive material column such as a solder column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating...

20060157849 - Electronic component with semiconductor chip and semiconductor wafer with contact pads, and method for the production thereof: An electronic component with semiconductor chips and a semiconductor wafer with contact pads are described, as well as methods of forming such structures. The contact pads on the semiconductor chip include mesa structures that are dimensioned in such a way that they are adapted to the sizes of compression heads...

20060157850 - Semiconductor device and manufacturing method thereof: A semiconductor device of the present invention is furnished with (a) a first protection film, formed on a substrate, having an opening section on an electrode pad, (b) a protrusion electrode, connected on the electrode pad at the opening section, whose peripheral portion is formed to overlap the first protection...

20060157852 - Circuit barrier structure of semiconductor packaging substrate and method for fabricating the same: A circuit barrier structure of a semiconductor packaging substrate and a method for fabricating the same, forming a metal conductive layer on an insulating layer of the substrate and a patterned resist layer on the metal conductive layer. The patterned resist layer has a plurality of holes to expose predetermined...

20060157851 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a first insulating film, a second insulating film and a third insulating film that are stacked in this order, and a first wiring formed in a first wiring trench formed in the stacked insulating films. The first insulating film is made of a film whose dielectric...

20060157857 - Metal capped copper interconnect: A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more...

20060157854 - Semiconductor device featuring copper wiring layers of different widths having metal capping layers of different thickness formed thereon, and method for manufacturing the same: In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large...

20060157856 - Semiconductor device including multiple rows of peripheral circuit units: In a semiconductor device including an internal circuit, multiple rows of peripheral circuit units are electrically connected to the internal circuit and arranged on at least one peripheral edge of the internal circuit. Also, a plurality of pads are arranged on the peripheral edge of the internal circuit. Each of...

20060157853 - Thermal bonding structure and manufacture process of flexible printed circuit board: A thermal bonding structure and manufacture process of a flexible printed circuit (FPC) board are disclosed, and the thermal bonding structure includes a laminated structure having a first insulating layer with a solder pad area and showing parts of a first conductive layer, the first conductive layer, a second insulating...

20060157855 - Wiring substrate, electro optic device and electronic equipment: A wiring substrate includes; a wiring composed of a conductive film and formed on a substrate; and an insulating layer, wherein the insulating layer is arbitrarily arranged among the conductive films....

20060157859 - Led packaging method and package structure: A LED packaging method is disclosed. The LED packaging method includes the steps of forming a high reflectivity alloy layer on an electrode layer of a support; coating a polymer adhesive on a portion of the upper surface of the high reflectivity alloy layer to form an adhering point; and...

20060157860 - Semiconductor constructions: The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H2, at least one H2-activating catalyst, and at least one metal-containing precursor dispersed therein. A metal-containing film is formed across the...

20060157858 - Structure for cooling a surface: An apparatus for cooling a surface having a metal structure made of a material with high thermal conductivity, and designed to provide efficient cooling of the surface while minimizing mechanical stress between the metal structure and the surface....

20060157861 - Ti precursor, method of preparing the same, method of preparing ti-containing thin layer by employing the ti precursor and ti-containing thin layer: X1 and X2 are independently F, Cl, Br or I; n is 0, 1, 2, 3, 4 or 5; m is 0, 1, 2, 3, 4, 5, 6 or 7; and R1 and R2 are independently a linear or branched C1-10 alkyl group. The Ti precursor for forming the Ti-containing...

20060157862 - Semiconductor device and method for producing the same: A high-reliability power semiconductor device uses a lead-free solder layer to connect a semiconductor chip such as an IGBT to an insulating substrate having a ceramic board and conductor layers, and a lead-free solder layer to connect the insulating substrate to a radiating base. Before the insulating substrate and the...

20060157865 - Circuit board and manufacturing method therefor and semiconductor package and manufacturing method therefor: A circuit board includes a circuit board body having a semiconductor device mounting area for mounting a semiconductor device, a wiring pattern to be electrically connected to a semiconductor device to be mounted on the semiconductor device mounting area, and an insulating layer for covering the wiring pattern, the insulating...

20060157864 - Electronic device package and method of manufacturing the same: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a...

20060157863 - Nucleation method for atomic layer deposition of cobalt on bare silicon during the formation of a semiconductor device: A method used to form a cobalt metal layer on a silicon surface using an atomic layer deposition (ALD) process comprises a treatment of the silicon surface prior to cobalt formation. Treatment includes serial exposure to one or more cycles comprising a titanium nitride precursor or a tantalum nitride precursor,...

20060157866 - Signal redistribution using bridge layer for multichip module: A multichip module (MCM) comprises a first integrated circuit and a second integrated circuit, a bridge layer over at least a portion of the second integrated circuit, one or more first interconnects conductively coupled between one or more contact areas of the first integrated circuit and one or more first...

20060157867 - Flip-chip package structure with direct electrical connection of semiconductor chip: A flip-chip package structure with direct electrical connection of a semiconductor chip has at least a dielectric layer; the semiconductor chip having electrical connection pads on an active surface thereof and connecting the dielectric layer via the active surface; and at least a wiring layer formed on a side of...

20060157868 - Flip-chip semiconductor device with improved power pad arrangement: A semiconductor device is composed of a power supply interconnection extending from a certain starting point in a first direction and also extending from the starting point in a second direction orthogonal to the first direction, a plurality of power pads, and connecting interconnections providing electrical connection between the power...

20060157869 - Semiconductor substrate with conductive bumps having a stress relief buffer layer formed of an electrically insulating organic material: A microelectronic structure is provided having a semi-conducting substrate comprising circuits therein and a top surface, and at least one first conductive bump situated on the top surface. The conductive bump provides electrical communication to the circuits. The at least one conductive bump has a stress relief buffer layer formed...

20060157870 - Electronic component, electro-optical device, and electronic apparatus: Provided is an electronic component including a pad provided on an active surface of a rectangular chip substrate, a resin protrusion provided along sides of the chip substrate, and a conductive portion which is electrically connected to the pad and which is formed out of a conductive film covering the...

20060157871 - Methods and apparatus for determining pad height for a wire-bonding operation in an integrated circuit: An integrated circuit having an integrated circuit die and at least one height-sensing pad disposed on a top surface of the integrated circuit die and electrically isolated from the die circuitry. At least one bond pad is disposed on a top surface of the integrated circuit die and electrically connected...

20060157872 - Epoxy resin composition and semiconductor device: wherein R1 and R2 are independently hydrogen or alkyl having 1 to 4 carbon atoms and two or more R1s or two or more R2s are the same or different; a is integer of 0 to 4; b is integer of 0 to 4; c is integer of 0 to...

20060157873 - Topographically indexed support substrates: The present invention provides an indexed support substrate. The support substrate comprises at least one set of indexing features that are distinguishable from one another and from the surrounding substrate. The support substrate also comprises a set of useful domains. The indexing features are positioned on the substrate in such...

20060151771 - Phase-change-type semiconductor memory device: A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell includes a chalcogenide...

20060151772 - Support device for monolithically integrated circuits: A carrier device for a monolithic integrated circuit has portions for the connection of bonding wires in the form of pedestals that rise above a chip connection area on the carrier device and have steep sides....

20060151773 - Solid-state imager and method for manufacturing same: A solid-state imager is disclosed wherein isolation regions (4) are covered with power supply lines (8), a light-transmitting lens film (24) whose surface forms continuous convex portions above the isolation regions (4) convex towards channel regions (5) is provided, and a light-transmitting material having a refractive index lower than that...

20060151774 - Field emitter array and method for manufacturing the same: A field emitter array, and a method for manufacturing the same are provided. The field emitter array comprises a nickel substrate, and a plurality of nano-pillars extending perpendicular to the nickel substrate. Each of the nano-pillars comprises a nickel nano-pillar body integrated to the nickel substrate and extending perpendicular to...

20060151775 - Solid state charge qubit device: Ionisation of one of a pair of dopant atoms (11, 12) in a substrate (13) creates a double well potential, and a charge qubit is realised by the location of one or more electrons or holes (14) within this potential. The dopant atoms may comprise phosphorous atoms, located in a...

20060151776 - Semiconductor integrated circuit and fabrication process thereof: A semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel MOS transistor formed on a second device region of the silicon substrate, wherein the n-channel MOS transistor includes a first gate electrode carrying a pair of first...

20060151777 - Multi-layer thin film in a ballistic electron emitter: An electron emitter that includes a metal film having a set of layers that are selected and arranged to adhere the metal film to a remainder of a structure of the electron emitter while avoiding electron loss in the metal film. A multiple layer metal film according to the present...

20060151780 - Hybrid silicon-molecular memory cell with high storage density: A nonvolatile memory cell including a substrate, a first electrode and a second electrode, and an active layer between the first and second electrodes. The active layer includes a self-assembled monolayer of an organic compound, and the second electrode is constructed from carbon-containing materials....

20060151779 - Novel thiophene-thiazole derivatives and organic thin film transistors using the same: Novel thiophene-thiazole derivatives and organic thin film transistors using the derivatives. The thiophene-thiazole derivatives are organic polymer semiconductor materials in which a thiophene having p-type semiconductor characteristics is joined to a thiazole having n-type semiconductor characteristics in an alternating manner to have a head-to-tail structure. The use of the thiophene-thiazole...

20060151781 - Organic thin film transistor including fluorine-based polymer thin film and method of fabricating the same: An organic thin film transistor including a fluorine-based polymer thin film and method of fabricating the same. The organic thin film transistor may include a gate electrode, a gate insulating layer, an organic semiconductor layer, source electrode, and a drain electrode formed on a substrate wherein a fluorine-based polymer thin...

20060151778 - Organic-inorganic hybrid transistors: A new class of organic-inorganic materials for thin film semiconducting devices that exhibit good stability in air and water, as well as a new purification technique for thin film semiconducting devices that contain impurities, such as ionic species....

20060151782 - Polymers for use in optical devices: Optical devices fabricated from solvent processible polymers suffer from susceptibility to solvents and morphological changes. A semiconductive polymer capable of luminescence in an optical device is provided. The polymer comprises a luminescent film-forming solvent processible polymer which contains cross-linking so as to increase its molar mass and to resist solvent...

20060151784 - Photonic devices and pics including sacrificial testing structures and method of making the same: A testing structure formed on a photonic integrated circuit including a plurality of first photonic components and having a given functionality corresponding to a given interconnectivity of the first photonic components, the testing structure including: at least one second photonic component being suitable for testing at least one of the...

20060151785 - Semiconductor device with split pad design: A semiconductor device includes a device body, a pad and a signal distribution runner. The device body includes a plurality of parallel cells and at least one integrated electronic component. The pad is located on a surface of the device body and includes a first portion and a second portion...

20060151783 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a digital circuit part and an analog circuit part that are disposed on a surface of one semiconductor substrate. A dummy layer part made of polysilicon that is the same as polysilicon composing a gate of a transistor is disposed between the digital circuit...

20060151786 - Ion doping system, ion doping method and semiconductor device: An ion doping system includes a chamber 11, an exhausting section 13 for exhausting gases from the chamber, an ion source 12 provided for the chamber, and an accelerating section 23 for extracting the ions, generated in the ion source 12, from the ion source 12 and accelerating the ions...

20060151787 - Low concentration sige buffer during strained si growth of ssgoi material for dopant diffusion control and defect reduction: A method and structure for fabricating a strained semiconductor on a relaxed SiGe substrate which has dopant diffusion control and defect reduction are provided. Specifically, the dopant diffusion control and defect reduction is achieved in the present invention by providing a SiGe buffer layer between the strained semiconductor and the...

20060151792 - Electro-optical device and driving method for the same: A grey tone display and a driving method are described. The display comprises a light influencing layer, an electrode pad located adjacent to the layer at one side of the layer in order to define a pixel in the layer, an n-channel field effect transistors connected to the electrode pad...

20060151789 - Light emitting device and method of manufacturing the same: A light emitting device is provided which has a structure for preventing degradation of a light emitting element due to water and oxygen contained in an interlayer insulating film formed between a TFT and the light emitting element. A TFT is formed on a substrate, an inorganic insulating film is...

20060151791 - Semiconductor device and method of fabricating the same: There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same....

20060151788 - Tft substrate for liquid crystal display apparatus and method of manufacturing the same: There are provided a TFT substrate for an LCD apparatus and a method of manufacturing the same. A substrate (10), a diffusion barrier layer (11) and a copper alloy layer (12) are formed on the TFT substrate, consecutively. The copper alloy includes a material from about 0.5 at % to...

20060151790 - Thin film transistor: A thin film transistor includes a semiconductor layer arranged on a substrate, a first insulating layer arranged on the substrate and the semiconductor layer, a gate electrode arranged on the first insulating layer, and a second insulating layer formed on the first insulating layer and the gate electrode. The width...

20060151794 - Photonic crystal light emitting device: A photonic crystal structure is formed in an n-type layer of a III-nitride light emitting device. In some embodiments, the photonic crystal n-type layer is formed on a tunnel junction. The device includes a first layer of first conductivity type, a first layer of second conductivity type, and an active...

20060151793 - Semiconductor light emitting device, method of manufacturing the same, and lighting apparatus and display apparatus using the same: The present invention aims to provide a semiconductor light emitting device (1) that may be firmly attached to a substrate with maintaining excellent light emitting efficiency, and a manufacturing method of the same, and a lighting apparatus and a display apparatus using the same. In order to achieve the above...

20060151795 - Solid state relay, electronic device, and method for manufacturing solid state relays: A light-receiving element for receiving a signal light from a light-emitting element and a load-controlling power element are mounted on an output-side lead frame of a solid state relay. A first electrode of the light-receiving element is connected to a first control terminal and a second electrode of the light-receiving...

20060151796 - Photo-detection device and manufacturing method thereof: This invention relates to a photodetection device, etc., equipped with a structure that efficiently cools a CCD reading part and can realize a downsizing of the entire device. The photodetection device comprises: a semiconductor substrate having a back surface which serves as a light-incident surface, and a front surface which...

20060151797 - Wafer structure and epitaxial growth method for growing the same: A wafer structure and epitaxial growth method for growing the same. The method may include forming a mask layer having nano-sized areas on a wafer, forming a porous layer having nano-sized pores on a surface of the wafer by etching the mask layer and a surface of the wafer, and...

20060151798 - Semiconductor light emitting element and semiconductor light emitting device: For the purpose of enhancing the light extracting efficiency, improving the production yield and elongating the lifetime of a semiconductor light emitting element or a semiconductor light emitting device using the element, a semiconductor light emitting element comprises: a light emitting layer that emits light; and a substrate transparent to...

20060151799 - Surface mount led: In a surface mount LED, circuit patterns can be formed on selective portions of the bottom and inner circumferential surfaces of a recess in a substrate in which an LED chip is mounted. A sealant material composed of a light transmissive resin can be applied to cover the LED chip...

20060151802 - Gallium nitride compound semiconductor device: A GaN compound semiconductor device can be capable of free process design and can have optimum device characteristics. The device can include a group III nitride compound semiconductor laminate structure including an n-type GaN compound semiconductor layer and a p-type GaN compound semiconductor layer. An n electrode can be formed...

20060151801 - Light emitting diode with thermo-electric cooler: Systems and methods for fabricating a light emitting diode include depositing one or more metal layers on a substrate; forming an n-gallium nitride (n-GaN) layer above the metal layer; and depositing a thermoelectric cooler in the metal layer to dissipate heat....

20060151800 - Surface mountable light emitting device: This invention relates to a surface mountable light emitting device in which the lead frame is exposed over a substantial portion of the underside of the device so as to allow greater thermal conductivity to any device on which it may be mounted. The LED provides the lens and a...

20060151803 - Diamond electrode and method for production thereof: The invention relates to a diamond electrode with synthetically produced, electrically conductive (doped) diamonds. The surface has diamond particles (5) embedded in a metal or metal alloy layer so as to produce a conductive connection to the metal or metal alloy....

20060151804 - Versatile system for cross-lateral junction field effect transisor: The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122)...

20060151805 - Power semiconductor device: A power semiconductor device comprises a semiconductor substrate, a gate electrode region (control electrode region), a cathode electrode region (first main electrode region), an anode electrode region (second main electrode region) and a guard ring. The semiconductor substrate has a side surface portion having a vertical portion formed substantially vertical...

20060151806 - Semiconductor device and power converter, driving inverter, general-purpose inverter and high-power high-frequency communication device using same: In a semiconductor device that uses a silicon carbide semiconductor substrate having p type, n type impurity semiconductor regions formed by ion implantation, the electrical characteristics of the end semiconductor device can be improved by decreasing the roughness of the silicon carbide semiconductor substrate surface. The semiconductor device of this...

20060151807 - Msm type photodetection device with resonant cavity comprising a mirror with a network of metallic electrodes: This invention relates to an MSM type photo-detection device designed to detect incident light and comprising reflecting means (2) superposed on a support (1), to form a first mirror for a Fabry-Pérot type resonant cavity, a layer of material (3) that does not absorb light, an active layer (4) made...

20060151808 - Mosfet device with localized stressor: MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material...

20060151809 - Optical semiconductor unit: An optical semiconductor device includes an optical semiconductor chip, a light permeable member covering the chip, and a reflector formed with an accommodation space for accommodating the light permeable member. The light permeable member includes a convex lens for converging light emitted from the optical semiconductor chip. The reflector includes...

20060151810 - Semiconductor device and computer program product for designing the same: A semiconductor device has: a plurality of first power supply wires formed in a first wiring layer; a plurality of second power supply wires formed in a second wiring layer; and a plurality of vias connecting between the first wiring layer and the second wiring layer. The plurality of second...

20060151811 - Floating gate memory device and method of manufacturing the same: Disclosed herein is a method of forming a floating gate in a non-volatile memory device having a self-aligned shallow trench isolation (SA-STI) structure. First, a tunnel oxide layer is formed on a semiconductor substrate having a SA-STI structure. Next, a first floating gate layer is formed on the tunnel oxide...

20060151812 - Solid-state imaging device and method of manufacturing the same: A solid-state imaging device including: a semiconductor substrate on which an imaging region having a light receiving section is formed; and a predetermined layer formed on the semiconductor substrate by planarization processing using liquid containing a metal element, wherein at least a first diffusion protection film is formed between the...

20060151813 - Substrate for forming a solid-state image pickup element, solid-state image pickup element using the same, and method of producing the same: A substrate for a solid-state image pickup element, comprising: an n-type silicon substrate; and an n-type epitaxial growth layer formed on a surface of the n-type silicon substrate, wherein the substrate is configured to form a solid-state image pickup element in the n-type epitaxial growth layer, the solid-state image pickup...

20060151814 - Optical semiconductor device: Since a plurality of light-receiving elements have heretofore led an electrode from a semiconductor substrate through an impurity-diffused and -buried region, series resistance has been relatively high, so that it has been difficult to improve the frequency characteristics of the light-receiving element. The present invention reduces parasitic capacitance by isolating...

20060151815 - Weighted gradient method and system for diagnosing disease: A method for detecting and diagnosing disease states in a body part is described. The method starts with a preparatory step of modeling the body part as a grid of many finite elements, then calculating an electrical property between two finite elements at which current from two corresponding electrodes flows...

20060151816 - Semiconductor device: A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating region of the FET can be attenuated...

20060151817 - Cmos image sensor having test pattern therein and method for manufacturing the same: The method for manufacturing a test pattern for use in a CMOS image sensor is employed to measure a sheet resistivity of each ion implantation region, respectively. The method includes steps of: forming an FOX area on a semiconductor substrate so as to define an active area; forming a first...

20060151818 - Solid state imaging device and production method therefor: The present invention relates to a CMOS-type solid-state imaging device and a method for manufacturing thereof, and provides a solid-state imaging device capable of optimally condensing light by a single intra-layer lens and a manufacturing method capable of forming an intra-layer lens with high precision. The solid-state imaging device according...

20060151819 - Self-aligned v0-contact for cell size reduction: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an...

20060151820 - Large-area nanoenabled macroelectronic substrates and uses therefor: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor...

20060151821 - Memory device having trapezoidal bitlines and method of fabricating same: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion...

20060151822 - Dram with high k dielectric storage capacitor and method of making the same: A dynamic random access memory cell that includes a transistor formed in a semiconductor body. A capacitor is coupled to the transistor and includes a first capacitor plate formed from silicon. A metal layer is adjacent to and electrically coupled to the first capacitor plate. A capacitor dielectric layer is...

20060151823 - High dielectric constant materials: A capacitor (10) includes a substrate (12) and two metal electrodes (14, 18). A dielectric layer (16) is formed between the electrodes. Preferably, the dielectric layer has a dielectric constant greater than 25 and an adequate conduction band offset with silicon. Exemplary embodiments proposed use the following material systems: HfuTivTawOxNy,...

20060151824 - Flash memory devices having self aligned shallow trench isolation structures: Flash memory devices are provided including an integrated circuit substrate and a stack gate structure on the integrated circuit substrate. A trench isolation region is provided on the integrated circuit substrate adjacent the stack gate structure. A portion of the stack gate structure adjacent a trench sidewall of the trench...

20060151825 - Gate structure in flash memory cell and method of forming the same, and method of forming dielectric film: The present invention relates to a gate structure of a flash memory cell and method of forming the same, and method of forming a dielectric film. The method of forming the dielectric film in the flash memory cell comprises the steps of preparing a wafer including a tunnel oxide film...

20060151826 - Semiconductor device having a barrier layer and method of manufacturing the same: A semiconductor device may include a gate structure having a gate insulation layer formed on a substrate, and a gate electrode formed on the gate insulation layer. A composite barrier layer may be formed on the gate structure....

20060151827 - Semiconductor device and a method of manufacturing the same: A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with...

20060151828 - Semiconductor device: In a semiconductor device in which gate trenches and source trenches are formed, when the semiconductor device is flatly viewed, N+ type source areas are formed in parallel with the gate trenches to ease the miniaturization of the semiconductor device. P+ type diffusion areas are separately formed in a direction...

20060151829 - Semiconductor device and a method for manufacturing therefor: An object of the present invention is to provide a semiconductor device capable of radiating electron-beams only to a desired region without forming a layer for restricting the radiating rays. A source electrode 22 made of aluminum prevents the generation of bremsstrahlung even when the electron-beams are radiated to the...

20060151830 - Electrical devices with multi-walled recesses: The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate receptacle that may facilitate a more uniform gate oxide layer. One embodiment relates to a storage cell that is disposed in the recess along with an...

20060151831 - Semiconductor device and method of fabricating the same: A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the semiconductor substrate 101, there is formed a parallel pn...

20060151832 - Semiconductor transistor having a stressed channel: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the...

20060151834 - High mobility plane finfet with equal drive strength: An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. The top of the first-type FinFET and...

20060151835 - Semiconductor device and method of fabricating same: There are disclosed TFTs having improved reliability. An interlayer dielectric film forming the TFTs is made of a silicon nitride film. Other interlayer dielectric films are also made of silicon nitride. The stresses inside the silicon nitride films forming these interlayer dielectric films are set between −5×109 and 5×109 dyn/cm2....

20060151833 - Transistor structure having stressed regions of opposite types underlying channel and source/drain regions: An integrated circuit and method of fabrication are provided in which the integrated circuit includes a field effect transistor (FET) having a channel region and source and drain regions adjacent to the channel region. A first stressed region having a first type of stress is provided to underlie the channel...

20060151836 - Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply: An electrostatic discharge (ESD) device and method is provided. The ESD device can comprise a substrate doped to a first conductivity type, an epitaxial region doped to the second conductivity type, and a first well doped to the first conductivity type disposed in the substrate. The first well can comprise...

20060151837 - In situ doped embedded sige extension and source/drain for enhanced pfet performance: Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained...

20060151838 - Enhanced pfet using shear stress: A semiconductor device structure includes a gate structure disposed on a portion of substrate, source and drain regions disposed adjacent to the portion so as to form a channel region in the portion, and trench isolation regions located immediately adjacent to the source and drain regions. At least portions of...

20060151839 - Gate structure of semiconductor device and method for forming the same: Disclosed herein is a method for forming a gate structure of a semiconductor device. The method comprises forming a plurality of gates including a first gate dielectric film, a first gate conductive film, and a gate silicide film sequentially stacked on a silicon substrate having a field oxide film, forming...

20060151840 - Semiconductor device and a method of manufacturing thereof: A semiconductor device has a semiconductor substrate, a pair of diffusion layers formed in a predetermined regions of the semiconductor substrate, a gate insulation film formed on a region of the semiconductor substrate being interposed between the pair of the diffusion layers, a gate electrode formed on the gate insulation...

20060151841 - Pillar nonvolatile memory layout methodology: A pillar nonvolatile memory layout methodology includes an arrangement of multiple pillar transistors spaced at intervals on a chip; surrounded in sequence by a SiO2 layer, a floating gate, a dielectric, and a control gate; a separation layer being formed between any two abutted pillar transistors; one up two surfaces...

20060151842 - Apparatus and method for reducing gate leakage in deep sub-micron mos transistors using semi-rectifying contacts: An apparatus and method for the reduction of gate leakage in deep sub-micron metal oxide semiconductor (MOS) transistors, especially useful for those used in a cross coupled static random access memory (SRAM) cell, is disclosed. In accordance with the invention, the active element of the SRAM cell is used to...

20060151843 - Hot carrier degradation reduction using ion implantation of silicon nitride layer: A method of reducing hot carrier degradation and a semiconductor structure so formed are disclosed. One embodiment of the method includes depositing a silicon nitride layer over a transistor device, ion implanting a species into the silicon nitride layer to drive hydrogen from the silicon nitride layer, and annealing to...

20060151846 - Method of forming hfsin metal for n-fet applications: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer...

20060151845 - Method to control interfacial properties for capacitors using a metal flash layer: A capacitor can be formed by depositing a metal flash layer (e.g., Ti) over a substrate (e.g., silicon). A dielectric layer (e.g., a high K dielectric) is formed over the metal flash layer. A conductive layer is formed over the dielectric layer such that the conductive layer is capacitively coupled...

20060151844 - Self-aligned process for nanotube/nanowire fets: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention...

20060151847 - Image sensor device and method of manufacturing same: An image sensor device including a protective plate may be manufactured from an image sensor chip having an active surface and a back surface opposite to the active surface. The image sensor chip may include chip pads formed in a peripheral region of the active surface, a microlens formed in...

20060151848 - Photogate with improved short wavelength response for a cmos imager: A photogate-based photosensor for use in a CMOS imager exhibiting improved short wavelength light response. The photogate is formed of a thin conductive layer about 50 to 3000 Angstroms thick. The conductive layer may be a silicon layer, a layer of indium and/or tin oxide, or may be a stack...

20060151849 - Phase change memory that switches between crystalline phases: A phase change memory may transition between two crystalline states. In one embodiment, the phase change material is a chalcogenide which transitions between face centered cubic and hexagonal states. Because these states are more stable, they are less prone to drift than the amorphous state conventionally utilized in phase change...

20060151850 - Method of forming a power amplifier: In a bipolar junction transistor (BJT) process, according to the linearity of an implant dosage and the output characteristics of a power amplifier, the implant dosage in the poly-silicon layer is selected and controlled in order to form different power level silicon germanium (SiGe) based power amplifiers. Cost, complexity, and...

20060151851 - On-pad broadband matching network: A chip is provided in which an on-chip matching network has a first terminal conductively connected to a bond pad of the chip and a second terminal conductively connected to a common node on the chip. A wiring trace connects the on-chip matching network to a circuit of the chip....

20060151852 - In-situ formation of metal insulator metal capacitors cross reference to related applications: The invention describes an in-situ method of fabricating a metal insulator metal (MIM) capacitor and products formed by the same. The method utilizes atomic layer deposition (ALD) or metal-organic chemical vapor deposition (MOCVD). In the method, a metal precursor is sequentially reacted with a nitrogen source, oxidant, and then a...

20060151853 - Variable capacitor, circuit module, and communications apparatus: A variable capacitor includes a supporting substrate and a plurality of variable capacitance elements, and bias lines. The plurality of variable capacitance elements is formed on the supporting substrate, each of which is composed of a lower-laid first electrode layer, an upper-laid second electrode layer, and a dielectric layer sandwiched...

20060151854 - Polishing composition and rinsing composition: A polishing composition and a rinsing composition according to the present invention can effectively suppress wafer contamination caused by metal impurities. The polishing composition includes a chelating agent, an alkali compound, silicon dioxide and water. The rinsing composition includes a chelating agent, an alkali compound and water. The chelating agent...

20060151855 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate including an isolation trench provided on a surface thereof, an isolation film provided in the isolation trench, the isolation film including a coating film and a silicon oxide film provided on the coating film, and an oxide film provided between the isolation trench...

20060151856 - Thermal barrier coating material, thermal barrier member, and member coated with thermal barrier and method for manufacturing the same: Provided are a thermal barrier coating material and a member coated with thermal barrier that can suppress the separation when used at a high temperature, and have a high thermal barrier effect; a method for manufacturing the member coated with thermal barrier; a turbine member coated with the thermal barrier...

20060151857 - Thermoadhesive multi-layer film: A thermoadhesive multi-layer film is described having at least four layers. The first and second layers are formed from a paper or a plastic film providing a support or “carrier.” The third layer is a colored film layer formed from at least one polymer-based material and is able to “float”...

20060151858 - Leadframe and semiconductor package made using the leadframe: Metal leadframes, semiconductor packages made using the leadframes, and methods of making the leadframes and packages are disclosed. In one embodiment, the leadframe includes a rectangular frame. A chip pad and a plurality of leads are within the frame. The lower side of the chip pad and the leads includes...

20060151859 - Component packaging and assembly: A packaging layer (200) for a wafer level assembly is fabricated from a glass material comprising both inorganic and organic components. This allows matching between the coefficient of thermal expansion of the packaging layer and that of other materials in the wafer assembly, particularly electrical interconnect materials. It is also...

20060151860 - Lead frame routed chip pads for semiconductor packages: A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a...

20060151862 - Lead-frame-based semiconductor package and lead frame thereof: A lead-frame-based semiconductor package and a lead frame thereof are proposed. The semiconductor package includes: the lead frame having at least one die pad and a plurality of leads around the die pad, wherein a plurality of grooves and runners are formed on a surface of the die pad, and...

20060151861 - Method to manufacture a universal footprint for a package with exposed chip: A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer...

20060151863 - Capacitor material for use in circuitized substrates, circuitized substrate utilizing same, method of making said circuitized substrate, and information handling system utilizing said circuitized substrate: A material for use as part of an internal capacitor within a circuitized substrate includes a polymer (e.g., a cycloaliphatic epoxy or phenoxy based) resin and a quantity of nano-powders of ferroelectric ceramic material (e.g., barium titanate) having a particle size substantially in the range of from about 0.01 microns...

20060151864 - Mems packaging with improved reaction to temperature changes: A large-scale MEMS device includes a MEMS die supported by at least one compliant die mount. The compliant die mount couples the MEMS die to a support structure. The support structure is positioned within a package. In accordance with an aspect of the invention, the package is substantially symmetrical about...

20060151866 - Multi-chip package for reducing test time: A multi-chip package is provided. The multi-chip package includes semiconductor chips. The multi-chip package receives selection signals for selecting two or more chips in response to the selection signals. Any number of chips may be simultaneously selected for a test and the test time can be reduced....

20060151865 - Semiconductor chip stack package having dummy chip: A chip stack package may have a circuit substrate, a first IC chip provided on the circuit substrate, and a second IC chip provided on the first IC chip. The second IC chip may be larger in size than the first IC chip and have overhang portions that may extend...

20060151867 - Semiconductor multipackage module including processor and memory package assemblies: A semiconductor multi-package module includes a processor and a plurality of memory packages mounted on a surface of the multipackage module substrate. In some embodiments the memory packages include stacked die packages, and in some embodiments the memory packages include stacked memory packages. In some embodiments the processor is situated...

20060151868 - Package for gallium nitride semiconductor devices: A packaged semiconductor device, in particular a gallium nitride semiconductor structure including a lower semiconductor layer and an upper semiconductor layer disposed over a portion of the lower semiconductor layer. The semiconductor structure includes a plurality of mesas projecting upwardly from the lower layer, each of the mesas including a...

20060151869 - Printed circuit boards and the like with improved signal integrity for differential signal pairs: A printed circuit board with improved signal integrity for one or more differential signal pairs incorporates one or more conductive regions. In an exemplary embodiment, via structures for the differential pair that interconnect signal traces are isolated from the conductive region by an antipad area around the via structures and...

20060151870 - Semiconductor device, wiring substrate, and method for manufacturing wiring substrate: The reliabilities of a wiring substrate and a semiconductor apparatus are improved by reducing the internal stress caused by the difference of thermal expansion coefficients between a base substrate and a semiconductor chip. A wiring layer (5) is provided on one surface of a silicon base (3). An electrode as...

20060151871 - High temperature, stable sic device interconnects and packages having low thermal resistance: A method of forming packages containing SiC or other semiconductor devices bonded to other components or conductive surfaces utilizing transient liquid phase (TLP) bonding to create high temperature melting point bonds using in situ formed ternary or quaternary mixtures of conductive metals and the devices created using TLP bonds of...

20060151872 - Connection between a semiconductor housing and a base plate comprising a passage opening for fastening to a heat sink: A semiconductor module has a housing (2) and a metal base plate (3). A reliable yet easily producible force-transmitting connection between a semiconductor module and an external heat sink is provided by a mechanical pressure-proof counterpart (4) which is incorporated into the housing (2) and forms a firm connection (14)...

20060151873 - Thermal interconnect systems methods of production and uses thereof: A thermal transfer material is described herein that includes: a heat spreader component, wherein the heat spreader component comprises a top surface, a bottom surface and at least one heat spreader material, and at least one solder material, wherein the solder material is directly deposited onto the bottom surface of...

20060151874 - Active rectifier module for three-phase generators of vehicles: A rectifier for rectifying alternating current into direct current is described, in which a three-phase generator includes a three-phase stator winding. The phases of the stator winding are triggered via switching elements of a power circuit. The power circuit is controlled via a control part, which includes a controller component....

20060151875 - Fabrication of semiconductor integrated circuit chips: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. Each of the plurality of active circuit die areas has four...

20060151876 - Electronic basic unit for a system on chip: An electronic basic unit for a system on chip comprises a semiconductor substrate and an area on the semiconductor substrate. The area is bounded by a geometric basic shape and the electronic basic unit is formed on the semiconductor substrate and has the form of an integrated circuit. The electronic...

20060151879 - Electronic component and leadframe for producing the component: An electronic component includes a semiconductor chip and a leadframe. The leadframe includes a metal coating pattern on its underside to facilitate the application of solder to the electronic component. The metal coating pattern includes wetting regions that are wettable with solder material and anti-wetting regions that are unwettable with...

20060151878 - Semiconductor chip packaging apparatus and method of manufacturing semiconductor chip package: Example embodiments of a semiconductor chip packaging apparatus and method thereof are disclosed. The packaging apparatus may include a plating unit to perform a conductive plating process to form a conductive plating layer on external terminals of a semiconductor chip package, and a reflow unit adapted to melt the conductive...

20060151877 - Semiconductor device and manufacturing method thereof: In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in...

20060151880 - Interconnect structures with bond-pads and methods of forming bump sites on bond-pads: Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further...

20060151882 - Method for producing an air bag: The invention relates to a method for the production of an air bag, more particularly a one-piece woven (OPW) air bag, comprising single layer and double layer areas, a top and bottom outer surface and a coating in at least certain areas. The invention is characteristic in that the single...

20060151881 - Semiconductor device and method of manufacture thereof: A semiconductor device comprises a semiconductor element formed in a semiconductor substrate, a plurality of insulating films stacked on the semiconductor substrate, a plurality of wiring layers each of which is formed in a respective one of the insulating films, and a barrier metal formed to continuously cover each of...

20060151883 - Semiconductor integrated circuit: A semiconductor integrated circuit having a plurality of interconnect layers and at least one via connecting interconnects of two adjacent interconnect layers, wherein each interconnect layer has a plurality of first interconnect groups and second interconnect groups arranged respectively in a row and a column in a matrix. The first...

20060151884 - Insulatng film material containing organic silane or organic siloxane compound, method for produing sane, and semiconductor device: A material for insulating film comprising an organosilicon compound which is one of an organosilane compound in which a secondary hydrocarbon group and an alkenyl group, or an alkenyl group, is directly bonded to a silicon atom, or an organosiloxane compound in which a secondary hydrocarbon group and/or an alkenyl...

20060151887 - Interconnection structure having double diffusion barrier layer and method of fabricating the same: An interconnection structure and a method of fabricating the same are provided. The interconnection structure includes an interlayer insulating layer having a structure comprising a via hole structure or a trench-shaped line structure. A conformal metal diffusion barrier layer is disposed inside the via hole structure or the trench-shaped line...

20060151888 - Manufacturing method of a semiconductor device: A manufacturing method of a semiconductor device comprises: providing a first insulating film whose relative dielectric constant is at most a predetermined value above a substrate; providing a second insulating film whose relative dielectric constant is greater than the predetermined value on a surface of the first insulating film; forming...

20060151886 - Semiconductor device and manufacturing method thereof: A semiconductor device includes an inter-metal dielectric (IMD) formed on a substrate and having at least one via hole, a via hole formed by filling the via hole with a first metal, a reductant layer formed on the via plug and the inter-metal dielectric to a predetermined thickness, and a...

20060151885 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device consistent with embodiments of the present invention includes forming a first insulation layer on a semiconductor substrate provided with an isolation layer and an active region; exposing a part of the active region by patterning the first insulation layer; forming a second insulation...

20060151889 - Semiconductor apparatus and manufacturing method: Pb free solder is used in die bonding. A thermal stress reduction plate is disposed between a semiconductor chip and a die pad made of a Cu alloy. The semiconductor chip and the thermal stress reduction plate are joined and the thermal stress reduction plate and the die pad are...

20060151890 - Overlay measurement target: In an overlay metrology method used during semiconductor device fabrication, an overlay alignment mark facilitates alignment and/or measurement of alignment error of two layers on a semiconductor wafer structure, or different exposures on the same layer. A target is small enough to be positioned within the active area of a...

20060145133 - Recovery of computer systems: Techniques for enabling remote recovery of computer system is disclosed. OOB communication with a provisioning server is established using a wireless communication device on a computer system that fails. The computer system includes an OOB controller. The OOB communication is authenticated. A disk image is downloaded from a server. Operations...

20060145134 - Non-planarized, self-aligned, non-volatile phase-change memory array and method of formation: A method for fabrication and a structure of a self-aligned (crosspoint) memory device comprises lines (wires) in a first direction and in a second direction. The wires in the first direction are formed using a hard mask material that is resistant to the pre-selected etch processes used for creation of...

20060145135 - Phase-change multi-level cell and operating method thereof: A phase-change multi-level memory cell is described, including a semiconductor substrate, a gate structure, two S/D regions, and two phase-change storing units electrically connected to the two S/D regions respectively. One phase-change storing unit can be programmed to one of many phases having different electrical resistances, and combination variations of...

20060145136 - Quantum dot memory: Provided is a method for fabricating self-assembled regions of silicon as well as semiconductor memory cells based thereon. By structuring a layer of silicon prior to thermal formation of the self-assembled regions under vacuum conditions control of location of these regions is achieved. A chargeable self-assembled region of silicon acts...

20060145137 - Quantum dot/quantum well light emitting diode: A quantum dot/quantum well light emitting diode (LED) is provided with a LED at one side of a substrate, and a second light emitting layer and a third light emitting layer at the other side of the substrate. When a proper forward bias is applied to the LED to emit...

20060145138 - Semiconductor nanoparticle surface modification method: Semiconductor nanoparticles having high luminescence properties that are preferable for applications and uses of biotechnology are provided. With the use of electric charges on the surfaces of particles, the particles and selected polymers are allowed to electrostatically bind to each other, such that the surfaces of the particles are coated....

20060145143 - Electronic device and process for forming same: An electronic device includes a substrate and a well structure overlying the substrate and defining an array of openings. From a cross-sectional view, the well structure, at the openings has a negative slope. From a plan view, each opening corresponds to an organic electronic component. Each opening within the array...

20060145141 - Field effect transistor and method of manufacturing the same: Provided is a field effect transistor having an organic semiconductor layer, in which the organic semiconductor layer contains at least a tetrabenzo copper porphyrin crystal and has peaks at two or more of Bragg angles (2θ) in CuKα X-ray diffraction of 8.4°±0.2°, 10.2°±0.2°, 11.80°±0.20°, and 16.90°±0.20°, and the tetrabenzo copper...

20060145150 - Flat panel display device and method of fabricating the same: An organic light emitting device, and a method of fabricating the same, has a cathode electrode that can prevent oxygen or moisture from infiltrating. The organic light emitting device of the present invention has a lower electrode, an organic thin film layer and an upper electrode successively formed on the...

20060145149 - Integrated circuit comprising an organic semiconductor, and method for the production of an integrated circuit: An embodiment of the invention provides an integrated circuit having an organic field effect transistor (OFET) with a dielectric layer. The dielectric layer is prepared from a polymer formulation comprising: about 100 parts of at least one crosslinkable base polymer, from about 10 to about 20 parts of at least...

20060145151 - Metal complex of heterocyclic aromatic compound: A novel metal complex of a heterocyclic aromatic compound which shows a low activation energy, is stabilized structurally, is capable of modulation of the structure thereof, and capable of preferably functioning as a molecular device in technological fields. The metal complex of a heterocyclic aromatic compound comprises a transition metal...

20060145148 - Method for forming organic semiconductor layer and organic thin film transistor: A method for forming an organic semiconductor layer especially for an organic thin film transistor in which a part of the organic semiconductive material thin film formed on a substrate is subjected to a pretreatment and then further subjected to a heating treatment....

20060145146 - Method of forming conductive pattern, thin film transistor, and method of manufacturing the same: A method of forming a conductive pattern in which the conductive pattern can be easily formed at a low temperature without a photolithography process by forming the conductive pattern using a laser ablation method and an inkjet method, an organic thin film transistor manufactured using the method, and a method...

20060145140 - Organic field effect transistor and integrated circuit: Organic field effect transistor and integrated circuit The invention relates to an organic field effect transistor (OFET) and/or to an organically based integrated circuit having a high switching frequency. Joining the two ends of the current channel results in compact and fast circuit layouts....

20060145147 - Organic light emitting display (oled) and its fabrication method: An Organic Light Emitting Display (OLED) and its fabrication method has a pixel defining layer provided on a first electrode which is formed with a gas vent groove to allow gas to vent when the pixel defining layer is being formed, so that gas is not left in a pixel...

20060145139 - Organic semiconductor device and its manufacturing method: There are provided an organic semiconductor device and a method of manufacturing the same, which make it possible to easily form a dense polymeric insulating film with high insulating properties as a gate insulating film, without using a vacuum apparatus, and to dispense with the step of patterning the gate...

20060145145 - Tertiary amine compounds, organic semiconductor devices using the same and organic electroluminescence devices using the same: An object of the present invention is to provide an organic semiconductor device comprising a semiconductor layer containing a compound with improved cohesive force, controllable molecular orientation, high packing property, high overall electrical conduction, high durability and high time-dependent stability. An organic semiconductor device comprising a substrate, a gate electrode,...

20060145144 - Vertical organic thin film transistor and organic light emitting transistor: A vertical organic thin film transistor is provided along with an organic light-emitting transistor, which is characterized in that an active layer is formed of a p-type organic semiconductor compound having a dielectric constant of 3.5 or more, and work function values of an anode and a cathode are different...

20060145142 - Volatile metal beta-ketoiminate and metal beta-diiminate complexes: Metal ketoiminate or diiminate complexes, containing copper, silver, gold, cobalt, ruthenium, rhodium, platinum, palladium, nickel, osmium, or indium, and methods for making and using same are described herein. In certain embodiments, the metal complexes described herein may be used as precursors to deposit metal and metal-containing films on a substrate...

20060145152 - Composite pattern for monitoring various defects of semiconductor device: A composite monitor is capable of determining a variety of defects of a semiconductor device. The composite monitor has an isolation region in a well region, an active region pattern in the well region and defined by the isolation region, and a metal line pattern partially overlying the active region...

20060145153 - Semiconductor device and method of manufacturing the same: A semiconductor device having a CMOS structure, wherein, in manufacturing a CMOS circuit, an impurity element which imparts p-type conductivity to the active layer of the p-channel type semiconductor device is added before forming the gate insulating film. Then, by applying thermal oxidation treatment to the active layer, the impurity...

20060145154 - Tft array substrate and the fabrication method thereof: A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor...

20060145155 - Tft array substrate and the fabrication method thereof: A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the...

20060145158 - Poly-crystalline silicon thin film transistor: Provided is a silicon thin film transistor (TFT) including: a substrate; a silicon channel layer formed on the substrate with a source and a drain on both sides thereof; a gate insulating layer formed on the silicon channel layer; and a gate formed on the gate insulating layer, wherein the...

20060145157 - Tft array substrate and fabrication method thereof: A TFT array substrate is provided. The TFT array substrate includes a gate electrode connected to a gate line; a source electrode connected to a data line, the data line crossing the gate line to define a pixel region; a drain electrode facing the source electrode with a channel interposed...

20060145156 - Thin film transistor array panel and method manufacturing thereof: A thin film transistor array panel according to the present invention includes: an insulating substrate; a gate wire formed on the insulating substrate and including a plurality of gate portions and a gate connection connecting the gate portions; a data wire insulated from the gate wire and intersecting the date...

20060145159 - Light-emitting device, method of manufacturing the same, and display unit: Light-emitting devices capable of preventing separation or alteration of a first electrode to obtain high performance, methods of manufacturing the light-emitting device, and display units are provided. A first electrode as an anode, an insulating film, an organic layer including a light-emitting layer, and a second electrode as a cathode...

20060145161 - Liquid crystal display device and method for fabricating the same: A liquid crystal display device according to the present invention includes a gate line on a substrate; a data line crossing the gate line with a gate insulating film to define a pixel area; a thin film transistor connected to the gate line and the data line; a semiconductor pattern...

20060145160 - Liquid crystal display device and method of fabricating the same: A thin film transistor substrate of a poly-silicon liquid crystal display device and a simplified method of fabricating the same are disclosed. A liquid crystal display device according to the present invention includes a gate line and a data line connected to a thin film transistor; a gate pad connected...

20060145162 - Liquid crystal display device and method of manufacturing the same: An LCD and a method of manufacturing the same using at most six mask processes are provided. An active layer and a storage electrode are simultaneously formed by diffraction exposure. Multiple ion implantations are performed using a photoresist or the gate electrode to mask different areas of an underlying semiconductor....

20060145163 - Organic elctroluminescent display and method for manufacturing organic electroluminescent display: An organic light emitting diode device of the present invention comprises a substrate, a light-transmissive electrode formed on the substrate, a coating-film-formative function layer including a hole transport material and an electron transport material, the function layer being formed on the substrate, trench patterns formed on the function layer, dopant...

20060145164 - Semiconductor chip for optoelectronics: An optoelectronic semiconductor chip has an active layer containing a photon-emitting zone. The active layer is attached to a carrier member at a bonding side of the active layer. The active layer has at least one recess therein with a cross-sectional area that decreases with increasing depth into said active...

20060145165 - Semiconductor light emitting device and fabrication method thereof: The present invention relates to a semiconductor light emitting device comprising a sapphire substrate 11; a u-GaN layer 12 that is formed on top of the substrate 11 and that comprises a plurality of concave portions 121 formed into band-like shapes with predetermined intervals therebetween; a regrown u-GaN layer 13...

20060145166 - Semiconductor apparatus, method for growing nitride semiconductor and method for producing semiconductor apparatus: A semiconductor apparatus includes a substrate made of a diboride single crystal expressed by a chemical formula XB2, in which X includes at least one of Ti, Zr, Nb and Hf, a semiconductor buffer layer formed on a principal surface of the substrate and made of AlyGa1-yN (0<y≦1), and a...

20060145167 - Electronic device including a guest material within a layer and a process for forming the same: A process for forming an electronic device includes forming a first layer over a substrate and placing a first liquid composition over a first portion of the first layer. The first liquid composition includes at least a first guest material and a first liquid medium. The first liquid composition comes...

20060145168 - Light-emitting device and method of manufacturing same: The present invention has an object to provide a method of raising a re-coupling efficiency of carriers in an EL element to thereby provide a light-emitting device having high emission efficiency. The method is that the electron trap region 106 and the hole trap region 107 are formed in the...

20060145169 - Light emitting diode: A light emitting diode (LED) is added aluminum atom in every layer of InGaN light emitting diode to emit a UV light with wavelength between 300 nm and 380 nm which is not able to see by humans. This LED can co-operate with different colors of luminescent material layer or...

20060145170 - Nitride based semiconductor light emitting device: The present invention provides a nitride-based semiconductor light emitting device basically comprising a first conductivity type nitride semiconductor layer, active layer and second conductivity type nitride semiconductor layer, which are sequentially formed on a light-permeable substrate in this order. The light emitting device further comprises an insulating light-scattering layer formed...

20060145171 - Semiconductor light emitting element and semiconductor light emitting device: For the purpose of enhancing the light extracting efficiency, improving the production yield and elongating the lifetime of a semiconductor light emitting element or a semiconductor light emitting device using the element, a semiconductor light emitting element comprises: a light emitting layer that emits light; and a substrate transparent to...

20060145176 - Cmos image sensor and fabricating method thereof: A CMOS ;image sensor and fabricating method thereof can enhance the quality of the image sensor by preventing unnecessary diffused reflection of light by providing an opaque filter layer next to a microlens. The CMOS image sensor includes a photodiode, an insulating interlayer, a metal line, a device protecting layer,...

20060145175 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same prevent a lifting effect of microlenses. Also, a diffused reflection of microlenses is prevented. The CMOS image sensor includes photodiodes, an interlayer insulating layer, metal lines formed in the interlayer insulating layer to electrically connect the respective photodiodes with...

20060145174 - High output light emitting diode and method for fabricating the same: A high output light emitting diode (LED) and a method for fabricating the LED is disclosed. The LED includes a sidewall or surface that is inclined. A reflective film is formed on the inclined sidewall or surface to allow light to reflect from the reflective film and to emit the...

20060145173 - Light emitting diode package and process of making the same: A light emitting diode (LED) package includes at least one LED chip, a carrier, a light reflection element and at least one outside connection electrode. The LED chip is disposed on the carrier and a conductive line or a flip chip method is used to connect the electrodes of the...

20060145172 - Light emitting diode with a quasi-omnidirectional reflector: A light emitting diode with a quasi-omnidirectional reflector comprises a luminescent gel which is coated surrounding a UV light LED chip and a quasi-omnidirectional reflector which is disposed above the luminescent gel. The quasi-omnidirectional reflector is a wild angle cut-off filter which is made by a cooperation of a method...

20060145179 - High-brightness gallium-nitride based light emitting diode structure: A GaN-based LED structure is provided so that the brightness and luminous efficiency of the GaN-based LED are enhanced effectively. The greatest difference between the GaN-based LEDs according to the invention and the prior arts lies in the addition of a masking buffer layer and a roughened contact layer on...

20060145180 - Led lighting assembly: The present invention provides a lighting head assembly that incorporates a high intensity LED package into an integral assembly including a heat sink and circuit board for further incorporation into other useful lighting devices. The present invention primarily includes a heat sink member that also serves as a mounting die...

20060145177 - Light emitting device and process for fabricating the same: A light emitting device 100 of the invention is the one using a first main surface of a compound semiconductor layer portion, having a light emitting layer section 24 therein, as a light extraction surface, and having, on the second main surface side of the compound semiconductor layer, a device-substrate...

20060145178 - System and method for mounting electrical devices: In one embodiment an electronic device, such as an optical sensor, is attached to a substrate upon which wire logouts and, if desired, other components are constructed. A frame, or cover, is attached to the substrate surrounding the attached device. An aperture in the cover allows wireless signals to pass...

20060145181 - Opto-electronic memory element on the basis of organic metalloporphyrin molecules: A memory cell for opto-electronic applications includes a substrate, a first electrode and a second electrode, and an active layer arranged between the first and the second electrodes, wherein the active layer includes a metalloporphyrin derivative, and wherein the second electrode is transparent and includes ZnO, which is doped with...

20060145183 - Method of manufacturing a semiconductor device having a photon absorption layer to prevent plasma damage: A MOSFET device structure and a method of manufacturing the same, in which a photon absorption layer is formed over a gate structure and a substrate in order to avoid plasma induced damage to the gate oxide during high density plasma deposition of a interlayer dielectric layer. The device structure...

20060145182 - Nitride semiconductor element and method for manufacturing thereof: Disclosed is a method for the preparation of a nitride semiconductor device having a nitride semiconductor layer composed of InN on which a high quality layer of a semiconductor of a nitride of a group III element typified by InN or GaN is grown as traversing dislocation or an interfacing...

20060145184 - Reverse mos (rmos) transistor, and methods of making and using the same: A metal-oxide-semiconductor transistor having a reverse current control mechanism (RMOS transistor) is described. The RMOS transistor generally includes a semiconductor substrate, a gate electrode on an oxide layer on the substrate, source and drain electrodes at opposite sides of the gate electrode, and a carrier region having a carrier with...

20060145185 - Ldmos gate controlled schottky diode: An improved diode is disclosed. The diode comprises a Schottky diode and a LDMOS device coupled in series with the Schottky diode. In a preferred embodiment, a forward current from the Schottky diode is allowed to flow through the channel of a depletion mode LDMOS that allows gate control over...

20060145186 - Buffer structure for modifying a silicon substrate: A buffer structure comprising a compositionally graded layer of a nitride alloy comprising two or more Group IIIB elements, for example La, Y, Sc or Ac, is used to modify a silicon substrate to produce a universal substrate on which a range of target materials, for example GaN, may be...

20060145187 - Gallium nitride semiconductor and method of manufacturing the same: The present invention provides to a gallium nitride (GaN) semiconductor and a method of manufacturing the same, capable of reducing crystal defects caused by a difference in lattice parameters, and minimizing internal residual stress. In particular, since a high-quality GaN thin film is formed on a silicon wafer, manufacturing costs...

20060145188 - Semiconductor wafer having a silicon-germanium layer, and method for its production: A semiconductor wafer has a monocrystalline silicon layer and a graded silicon-germanium layer adjacent thereto, of thickness d and composition Si1-xGex, where x represents the proportion of germanium and 0<x≦1, and where x assumes greater values with increasing distance a from the monocrystalline silicon layer, wherein the relationship between the...

20060145189 - Iii-nitride power semiconductor with a field relaxation feature: A III-nitride power semiconductor device that includes a field relaxation feature to relax the electric fields around the gate thereof to improve the breakdown voltage of the device....

20060145190 - Surface passivation for iii-v compound semiconductors: A structure and method of fabrication are disclosed for improving surface passivation of III-V compound semiconductors. The invention exploits certain anion-rich compound semiconductors to form a high quality interface with a dielectric when anion mobility is increased during an annealing step. Low post-annealing surface state densities result in a low...

20060145191 - Semiconductor device and method of manufacturing such a device: The invention relates to a so-termed punchthrough diode (10) with a stack of, for example, n++, n−, p+, n++ regions (1,2,3,4). In the known diode, these semiconductor regions (1,2,3,4) are positioned in said order on a substrate (11). The diode is provided with connection conductors (5,6). Such a diode does...

20060145192 - Denise array structure for non-volatile semiconductor memories: The present invention describes an array structure (10) for non-volatile semiconductor memory elements (14, 16) with a high area density. This high density is obtained by the combination of a commonly used virtual ground scheme and a 2-dimensional array of memory elements (14, 16). Wordlines (18, 20) connecting memory elements...

20060145193 - Dual-mode decoder circuit, integrated circuit memory array incorporating same, and related methods of operation: In an embodiment of the invention an integrated circuit includes a memory array having a first plurality of decoded lines traversing across the memory array and a pair of dual-mode decoders, each decoder coupled to each of the plurality of decoded lines a respective location along said decoded lines, such...

20060145195 - Backgated finfet having different oxide thicknesses: A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced...

20060145194 - Method for creating a functional interface between a nanoparticle, nanotube or nanowire, and a biological molecule or system: A field effect transistor and a method for making the same. In one embodiment, the field effect transistor comprises a source; a drain; a gate; at least one carbon nanotube on the gate; and a dielectric layer that coats the gate and a portion of the at least one carbon...

20060145197 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same provides a microlens pattern profile with a rectangular shape to facilitate a reflow process of a microlens and improve its curvature, thereby improving concentration efficiency of light and improving characteristics of the image sensor. The CMOS image sensor includes...

20060145196 - High-sensitivity image sensor and fabrication method thereof: A method of fabricating a high-sensitivity image sensor is disclosed. The disclosed method comprises: etching a predetermined region of active silicon and a buried oxide layer by using a mask over an SOI substrate to expose an N-type silicon substrate; implanting P-type ions into the exposed N-type silicon substrate to...

20060145198 - Magnetic ram: A memory element for a magnetic RAM, contained in a recess of an insulating layer, the recess including a portion with slanted sides extending down to the bottom of the recess, the memory element including a first magnetic layer portion substantially conformally covering the bottom of the recess and the...

20060145199 - Thin film layer, heating electrode, phase change memory including thin film layer and methods for forming the same: A thin film layer, a heating electrode, a phase change memory including the thin film layer, and methods for forming the same. The method of forming the thin film layer by atomic layer deposition (ALD) may include injecting a titanium (Ti) source, a nitrogen (N) source, and/or an aluminum (Al)...

20060145200 - Gate structure of a semiconductor device: Disclosed herein is a method for forming a gate structure in a semiconductor device. The method comprises forming a SiGe film on a predetermined region of a silicon substrate corresponding to a bit-line node portion where a bit-line junction is formed, growing a silicon film over the silicon substrate having...

20060145201 - Semiconductor device and field-effect transistor: A Schottky electrode including a WNx layer on an n-type GaN layer. A crystal plane of the n-type GaN layer is in contact with a crystal plane of the WNx layer. The crystal plane of the n-type GaN layer is a (0001)-plane, and the crystal plane of the WNx layer...

20060145204 - Cmos image sensor and method for fabricating the same: A CMOS image sensor includes a passivation layer including an etch stop layer, the passivation layer having a color filter array pattern formed to a depth determined by the etch stop layer, the color filter array pattern including separately defined color filter regions; and a color filter array including a...

20060145205 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a method for manufacturing the same improves signal efficiency by reducing a dark signal, and includes a substrate having a first conductive type comprising an image area and a circuit area, a STI isolation layer in the substrate for electrical isolation within the circuit area,...

20060145202 - Image sensor and method for forming isolation structure for photodiode: An image sensor provided with: a plurality of photodiodes arranged on a surface of a semiconductor substrate, the photodiodes each including a first region of a first conductivity type provided on the semiconductor substrate, a second region of a second conductivity type provided on the first region, the second conductivity...

20060145203 - Method and apparatus for controlling charge transfer in cmos sensors with an implant by the transfer gate: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit....

20060145210 - Cmos image sensor: A CMOS image sensor includes a photo-transistor capable of performing photo-sensing and active amplification. The photo-transistor is installed to improve low illustration characteristics while maintaining an existing pixel operation. The CMOS image sensor also includes a reset transistor connected to the photo-transistor and adapted to perform a reset function, a...

20060145206 - Cmos image sensor and method for fabricating the same: A CMOS image sensor having a transistor and a method for fabricating the same is provided. The CMOS image sensor includes a semiconductor substrate; a gate electrode of the transistor formed on the semiconductor substrate; and an ion-implantation blocking layer formed as part of the gate electrode. The CMOS image...

20060145212 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and fabricating method can reduce leakage current of a photodiode reduced by configuring a triangular shape of a photodiode area to minimize an interface contacting the STI or performing deuterium annealing to remove dangling bonds from an interface contacting with oxide. The CMOS image sensor includes...

20060145211 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a method for manufacturing the same are provided, in which a nitride layer for passivation is used as a microlens to reduce topology. The CMOS image sensor includes an upper metal layer partially deposited on a dielectric layer; a first nitride layer deposited on the...

20060145213 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a method for manufacturing the same improve light-receiving efficiency and maintain a margin in the design of a metal line. The CMOS image sensor includes a transparent substrate including an active area having a photodiode region and a transistor region and a field area for...

20060145207 - Image sensor capable of increasing photosensitivity and method for fabricating the same: An image sensor capable of overcoming a decrease in photo sensitivity resulted from using a single crystal silicon substrate, and a method for fabricating the same are provided. An image sensor includes a single crystal silicon substrate, an amorphous silicon layer formed inside the substrate, a photodiode formed in the...

20060145208 - Photodiode in cmos image sensor and method of manufacturing the same: A CMOS image sensor is provided in which a P-type impurity containing layer is formed in a blue photodiode region and a P-type diffusion region is formed by diffusion such that a junction depth is reduced and blue light is efficiently received to improve image quality. A method of manufacturing...

20060145209 - Photodiode of cmos image sensor and method for manufacturing the same: A photodiode of a CMOS image sensor and a method for manufacturing the same are provided, in which ions implanted in the vicinity of a device isolation film are prevented from being diffused into a photodiode region to reduce a dark current. The photodiode of a CMOS image sensor includes...

20060145214 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a method for manufacturing the same are disclosed, in which a blue photodiode is imparted with a greater thickness to improve sensitivity of blue light. The blue photodiode of a CMOS image sensor includes a first lightly doped P-type epitaxial layer formed on a heavily...

20060145215 - Image sensor having 3-dimensional transfer transistor and its method of manufacture: In an embodiment, an image sensor includes an isolation layer disposed in a semiconductor substrate to define a first active region and a second active region extending from the first active region. A photodiode is disposed in a portion of the first active region. A floating diffusion region is provided...

20060145216 - Cmos image sensor and fabricating method thereof: A CMOS image sensor and fabricating method thereof enable enhanced photo-response characteristics and protect a microlens in packaging by embedding the microlens in a passivation layer pattern. The image sensor may include a semiconductor substrate, a photodiode, a metal line, an insulating layer, a passivation layer pattern, and a microlens...

20060145219 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are disclosed, in which light that transmits through a microlens is prevented from being beyond a photodiode region to minimize loss of incident light and to improve low illumination characteristics of the CMOS image sensor. The CMOS image sensor...

20060145220 - Cmos image sensor and method for fabricating the same: Provided are a CMOS image sensor which has an infrared ray cut-off filter formed therein such that the size of a camera module of a portable telephone can be reduced and manufacturing yield can be improved and a method of manufacturing the same. The CMOS image sensor includes a color...

20060145221 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same can ensure isolation characteristics using a shallow trench isolation (STI) process and a selective epitaxy method. The CMOS image sensor and method for fabricating the same can also reduce pixel size. The CMOS image sensor includes a semiconductor substrate,...

20060145224 - Cmos image sensor and method for fabricating the same: Provided are a CMOS image sensor in which microlenses are formed in a remaining space in a patterned light shielding layer to improve image sensor characteristics and to protect the microlenses during packaging, and a method of fabricating the same. The CMOS image sensor may include: a semiconductor substrate; at...

20060145217 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a method for manufacturing the same improves photosensitivity and prevent loss of light by forming a photo-sensing unit under a color filter. The CMOS image sensor may include a plurality of transistors formed on a semiconductor substrate, a metal line formed over the plurality of...

20060145222 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor includes a photodiode in a semiconductor substrate; an insulating interlayer over the semiconductor substrate including the photodiode; a passivation layer pattern on the insulating interlayer corresponding to the photodiode; a first light-shielding layer pattern on the insulating interlayer between each passivation layer pattern; a second light-shielding...

20060145223 - Image sensor capable of adjusting focusing length for individual color and fabrication method thereof: An image sensor and a fabrication method thereof are provided. The image sensor includes: a first photodiode formed in a substrate and receiving a first color; a second photodiode formed in the substrate apart from the first photodiode and receiving a second color with a wavelength longer than that of...

20060145218 - Microlens of cmos image sensor and method of manufacturing the same: A method of a microlens of a CMOS image sensor eliminates a flattened gap between the curvatures of adjacent microlenses. A plurality of color filter layers is formed on a semiconductor substrate on which a photodiode region, a gate electrode, an interlayer insulating layer, and a metal interconnection are formed....

20060145225 - Fast remanent resistive ferroelectric memory: The invention relates to a memory element comprised of an electrode (2), of a ferroelectric layer (3), which is adjacent thereto, of a layer (4), which is made of a non-ferroelectric material and which is adjacent to said ferroelectric layer (3), and of an electrode (5), which is made of...

20060145226 - Magnetic ram: A memory element for a magnetic RAM, having a first magnetic portion in a first recess of a first insulating layer; and a non-magnetic portion and a second magnetic portion in a second recess of a second insulating layer covering the first insulating layer, the second recess exposing the first...

20060145227 - Method for producing semiconductor memory devices and integrated memory device: The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory...

20060145229 - Cylinder-type capacitor and storage device, and method(s) for fabricating the same: A one cylinder storage device and a method for fabricating a capacitor are disclosed, realizing simplified fabrication by overexposure with a mask having a plurality of holes, in which the method includes forming a contact hole in an insulating layer on a semiconductor substrate forming a conductive layer on the...

20060145228 - Semiconductor device: A semiconductor memory device comprising a semiconductor substrate, element isolating regions formed on the semiconductor substrate, an element forming region provided between the element isolating regions on the semiconductor substrate, the element forming region having a protruding portion, a transistor having a channel formed in the protruding portion of the...

20060145230 - Power semiconductor switching element: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type...

20060145231 - Distributed capacitor array: A capacitor structure in an integrated circuit includes a capacitor region defined within the boundaries thereof with an active circuit layer formed on the surface of the semiconductor substrate. A planarization layer is disposed over the active circuit layer and electrically isolated therefrom in at least the capacitor region. A...

20060145232 - Method for manufacturing semiconductor device including mim capacitor: A semiconductor device including a metal-insulator-metal (MIM) capacitor is manufactured such that a via for connecting upper and lower conductive layers is formed through an insulating interlayer after a silicon nitride layer is deposited as a thick layer on the insulating interlayer. This protects an edge of a MIM structure...

20060145233 - Method of fabricating a semiconductor device capacitor having a dielectric barrier layer and a semiconductor device capacitor having the same: A method of forming a capacitor of a semiconductor device is provided. In the method, a capacitor lower electrode is deposited on a semiconductor substrate and then a dielectric layer is deposited on the lower electrode. A dielectric barrier layer is deposited on an upper part of the dielectric layer....

20060145234 - Capacitor and method for fabricating the same: A capacitor structure and a method of fabricating the capacitor structure wherein. The lower electrode and the upper electrode are constructed to be separated from each other by a predetermined interval and to be engaged with each other using a series of alternating ridges so that an effective surface area...

20060145235 - Erasable nonvolatile memory with sidewall storage: A nonvolatile storage cell, integrated circuit (IC) including the cells and method of manufacturing the cells. A layered spacer (ONO) is formed at least at one sidewall of cell gates. Source/drain diffusions at each layered spacer underlap the adjacent gate. Charge may be stored at a layer (an imbedded nitride...

20060145236 - Flash memory device and fabricating method thereof: A flash memory device includes a floating gate formed on a substrate, sidewall gates formed on sidewalls of the floating gate, an interlayer insulating layer formed the floating gate and the sidewall gates, and a control gate formed on the interlayer insulating layer. The fabricating method of a flash memory...

20060145237 - Non-volatile memory device and method of manufacturing the same: Provided are a non-volatile memory device and a method of manufacturing the same. The non-volatile memory device includes a gate insulating layer having a tunneling window formed therein. The tunneling window has a predetermined width parallel to a channel length direction and has a predetermined length perpendicular to the channel...

20060145238 - Diode structure for word-line protection in a memory circuit: One embodiment of the invention is an integrated circuit having: (i) an array of flash transistors formed on a substrate and arranged in one or more rows, each flash transistor having a control gate, wherein, in each row, the control gates are connected to a word line; and (ii) for...

20060145239 - Flash eeprom device and method for fabricating the same: In a flash EEPROM device, and method for fabricating the same, no bit line contact is made, thereby minimizing a design rule between a contact and a gate. Thus, cell size may be reduced. The flash EEPROM device includes a semiconductor substrate having an active area defined in a bit...

20060145240 - Memory devices and methods of operating the same: A memory device may include a first memory unit and a second memory unit. The first memory unit may include a first storage node storing data using a first method. The second memory unit may include a second storage node using a second method. The second method may be different...

20060145241 - Non-planar flash memory array with shielded floating gates on silicon mesas: A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions....

20060145242 - Semiconductor memory device and method of fabricating the same: A silicon nitride film for storing electric charge is formed on a semiconductor substrate while placing a tunnel oxide film in between, and the silicon nitride film is then subjected to hydrogen plasma treatment so as to effectively erase unnecessary charge stored therein during various process steps in fabrication of...

20060145243 - Non-volatile memory device and manufacturing method and operating method thereof: A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate. The p type...

20060145244 - Sonos device and method of manufacturing the same: A SONOS device and a method of manufacturing the same is provided. A tunnel dielectric layer, a charge trap layer, and a charge blocking layer are formed on a semiconductor substrate, and the charge blocking layer is formed on the charge trap layer such that the charge blocking layer is...

20060145245 - Field-effect transistor, its manufacturing method, and complementary field-effect transistor: A field effect transistor comprises: a semiconductor substrate; a semiconductor layer provided on the semiconductor substrate, the semiconductor layer including a body region which contains an impurity of a first conductivity type; a gate dielectric film provided on the semiconductor layer; a gate electrode provided on the gate dielectric film;...

20060145246 - Integrated dram-nvram multi-level memory: An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory...

20060145247 - Trench transistor and method for producing it: A trench transistor and method of making a trench transistor is disclosed. In one embodiment, the trench transistor has a semiconductor body in which a plurality of cell array trenches separated from one another by mesa regions are formed. Electrodes are embedded in the cell array trenches. A source region,...

20060145248 - Ldmos transistor: A lateral double-diffused MOS (LDMOS) transistor is provided with a trench source structure. The LDMOS transistor includes a semiconductor substrate of a first conductivity, the semiconductor substrate having a trench formed in a surface region corresponding to a source of the transistor; a body of a second conductivity, the body...

20060145249 - Ldmos transistor: A lateral double-diffused metal oxide semiconductor transistor (LDMOS) transistor includes a semiconductor substrate of a first conductivity; an extended drain region of the first conductivity formed in a surface region of the semiconductor substrate; and a depletion region, formed in the extended drain region, including first and second impurity regions...

20060145250 - Ldmos transistor: An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a surface of the epitaxial layer of a second conductivity type, a lightly doped drain region within the epitaxial layer of a second conductivity type, a channel located...

20060145251 - Semiconductor device having high-voltage transistor and pip capacitor and method for fabricating the same: A semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a method for fabricating the same are provided. A current flow path of the high-voltage transistor is widened to reduce on-resistance of the device. Thus, electric characteristics of the device are enhanced. The semiconductor device includes a...

20060145252 - Power semiconductor device and method of manufacturing the same: A low on-state resistance power semiconductor device has a shape and an arrangement that increase the channel density and the breakdown voltage. The power semiconductor device comprises a plurality of individual cells formed on a semiconductor substrate (62). Each individual cell comprises a plurality of radially extending branches (80) having...

20060145253 - Mos transistor and method of manufacturing the same: A manufacturing method of a double LDD MOS transistor includes forming a gate electrode on a semiconductor substrate; forming a first LDD area by implanting and thermally annealing impurity ions using the gate electrode as a mask; forming a first spacer on both lateral walls of the gate electrode; forming...

20060145254 - Semiconductor devices including carrier accumulation layers and methods for fabricating the same: A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the...

20060145255 - Thin film transistor substrate: Disclosed are a thin film transistor substrate of an LCD device and a method of manufacturing the same. The thin film transistor substrate includes a nickel-silicide layer formed on an insulating layer pattern including silicon and a metal layer formed on the nickel-silicide layer. Nickel is coated on the insulating...

20060145257 - Method of fabricating a semiconductor device having full depletion type logic transistors and partial depletion type memory transistors: A semiconductor device includes a semiconductor substrate, an insulating layer, a silicon layer, full depletion type transistors, and partial depletion type transistors. The insulating layer is formed on the Semiconductor substrate. The silicon layer has a first region and a second region. The silicon layer is formed on the insulating...

20060145256 - Prevention of parasitic channel in an integrated soi process: A Silicon on Insulator device is disclosed wherein a parasitic channel (110) induced in a thin film portion of the device is prevented from allowing current flow between the source (101) and drain (101) by a Deep N implant directly below the source or drain. The deep N implant prevents...

20060145259 - Fin field-effect transistor and method for fabricating the same: A fin field-effect transistor and a method of fabricating the same provide a fin structure with rounded edges that may prevent a localized thinning of a gate insulating layer formed over the fin structure and to thereby prevent the occurrence of electrical shorts between the fin and a conductive layer...

20060145258 - Semiconductor device and manufacturing method thereof: A semiconductor device and method of manufacturing the same are disclosed. An example semiconductor device includes a semiconductor substrate having a first well, a first source electrode, a drain electrode, and a first gate insulation layer formed on the semiconductor substrate, and a gate electrode formed on the first gate...

20060145260 - Electro-static discharge protection circuit and method for fabricating the same: An ESD protection circuit using an N-type extended drain silicon controlled rectifier (N-EDSCR) and a method for fabricating the same are provided. An electro-static discharge (ESD) protection circuit includes a substrate, a well formed in the substrate, a drift region having a predetermined portion overlapped with the well, a plurality...

20060145261 - Electrostatic discharge protection: An electrostatic discharge (“ESD”) protection device, which includes a thyristor circuit, in the ESD case increases a resistance of the ESD protection device in comparison with a non-ESD case, by means of a switch. An ESD protection arrangement may include a ESD protection device to protects circuits with multiple voltage...

20060145262 - Tunable esd device for multi-power application: A tunable ESD device for multi-power application. The ESD device comprises a substrate, at least one first well of a first conductivity, and a doped region of a second conductivity. The first wells of the first conductivity are located in the substrate. The doped region of the second conductivity substantially...

20060145263 - Plasma damage protection circuit for protecting multiple word lines or strapped word lines of a memory device: A memory device is connectable to a protection circuit for plasma-induced charge damage protection and includes a memory array including a plurality of word lines and a plurality of diodes each coupled between a corresponding one of the word lines and the protection circuit....

20060145265 - Cmos semiconductor device: While forming an N-type MOSFET 118 and a P-type MOSFET 120 within regions operating using the same power supply voltage, thickness of a gate insulating film 106a of an N-type MOSFET 118 is made to be thicker than thickness of a gate insulating film 106b of a P-type MOSFET 120....

20060145266 - Semiconductor integrated circuit: A semiconductor integrated circuit, whose MOS transistors' layout structure is determined in consideration of the size of a device active region in a gate length direction, in which each transistor is formed. When stresses coming from the device isolation region, etc. are taken into account, for a circuit whose current...

20060145264 - Stressed field effect transistors on hybrid orientation substrate: A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has...

20060145268 - Semiconductor device and method for fabricating the same: An inventive method for fabricating a semiconductor device includes the steps of: a) forming trenches in an actual element region and a dummy pattern region of a substrate by using a mask; b) depositing an insulator over the substrate, thereby forming an insulating film that fills at least the trenches;...

20060145267 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same are disclosed, in which an insulating layer may be formed in a strained silicon layer under source/drain regions to substantially overcome conventional problems resulting from a channel decrease in the semiconductor device. A method for manufacturing the semiconductor device may...

20060145269 - Semiconductor device having a capping layer including cobalt and method of fabricating the same: A semiconductor device, and a method of fabricating the same, includes cobalt as a capping layer. An interconnection structure of the semiconductor device has an improved via resistance. In the semiconductor device, a single cobalt layer or a composite film including a cobalt layer and a titanium nitride layer is...

20060145271 - Semiconductor device having low parasitic resistance and small junction leakage characteristic: A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes....

20060145270 - Semiconductor device having silicide-blocking layer and fabrication method thereof: A semiconductor device having a silicide-blocking layer is provided. The device includes a field oxide layer defining an active region, source/drain regions in the active region of a substrate, a gate oxide layer and a gate electrode on the substrate between the source/drain regions, dielectric spacers on sidewalls of the...

20060145272 - Mask rom and fabricating method thereof: A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance characteristics are enhanced....

20060145273 - Device with stepped source/drain region profile: Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the...

20060145275 - Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance: An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location of silicide formation...

20060145274 - Nfets using gate induced stress modulation: A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a gate polysilicon of the n-type field effect transistor, such...

20060145276 - Optical semiconductor device and fabrication method therefor: An optical semiconductor device such as, for example, a quantum dot SOA and a fabrication method therefor are disclosed wherein an active layer and a current constriction structure can be formed leftwardly and rightwardly symmetrically to minimize the polarization dependency. The fabrication method for an optical semiconductor device includes the...

20060145278 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor includes a plurality of photodiodes in a semiconductor substrate; an insulating interlayer on the semiconductor substrate including the plurality of photodiodes; a metal line in the insulating interlayer; a passivation layer on the insulating interlayer; an adhesive layer on the passivation layer; and a plurality of...

20060145279 - Electro-optic integrated circuits with connectors and methods for the production thereof: An electro-optic integrated circuit including an integrated circuit substrate at least one optical signal providing element and at least one discrete reflecting optical element mounted onto the integrated circuit substrate, cooperating with the at least one optical signal providing element and being operative to direct light from the at least...

20060145277 - Image sensor and method for fabricating the same: The image sensor includes a semiconductor substrate, a first color filter pattern formed over the substrate, the first color filter pattern having an edge portion with a first slope, and a second color filter pattern formed next to the first color filter pattern, the second color filter pattern having an...

20060145280 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are provided, in which an N type region of a photodiode is prevented from adjoining a device isolation film and a dark current is reduced. The CMOS image sensor includes an interlayer dielectric film formed between a gate poly...

20060145281 - Semiconductor device, liquid crystal device, electronic apparatus, and method of manufacturing semiconductor device: A semiconductor device includes a substrate that is provided with a first main surface and a second main surface, a light shielding film that is disposed in a groove formed in the first main surface, and a semiconductor element that has a semiconductor film. The light shielding film is disposed...

20060145282 - Light sensor located above an integrated circuit: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity...

20060145283 - Gallium nitride semiconductor device: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of...

20060145284 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes steps of injecting a hole current into an N drift region while a constant voltage is applied to a P+ anode of a lateral insulated gate bipolar transistor, such that a majority of the hole current passes through a P+ cathode of...

20060145285 - Ldmos transistor: A lateral DMOS transistor having a uniform distribution of channel impurity concentration includes a drift region of a first conductivity; a body of a second conductivity, the body being disposed in the drift region and has a channel thereon; and a source region of the first conductivity, the source region...

20060145286 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first...

20060145287 - Method for forming shallow trench isolation in semiconductor device: A method for forming shallow trench isolation in a semiconductor device. The method includes forming a trench in a predetermined depth on a semiconductor substrate, filling the trench with a first filing oxide, injecting an impurity into a portion of the first filling oxide inside the trench, removing the portion...

20060145288 - Method of forming shallow trench isolation of semiconductor device: A method of forming a shallow trench isolation (STI) of a semiconductor device is disclosed. The method includes the steps of (a) serially forming a pad oxide layer and a pad nitride layer on a silicon substrate, and serially etching the pad nitride layer, the pad oxide layer, and the...

20060145289 - Semiconductor device and method for fabricating the same: A semiconductor device and a method for fabricating the same selectively forms a nitride layer having high tensile stress in an NMOS transistor area, to thereby form a strained-silicon structure in an NMOS channel region, whereby electron mobility is improved and drain current is increased. The semiconductor device includes an...

20060145290 - Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type: A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity...

20060145291 - Structure and programming of laser fuse: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the dielectric layer. The fuse link electrically connects...

20060145292 - Antifuse having uniform dielectric thickness and method for fabricating the same: Disclosed are an antifuse having a uniform amorphous silicon (antifuse material) thickness and a method for fabricating such an antifuse device. The antifuse is located between overlying and underlying conductive layers, and includes: a contact and/or via hole in an insulating layer on the underlying conductive layer; a lower metal...

20060145295 - Metal-insulator-metal (mim) capacitor: A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a substrate. A portion of the first metal layer is utilized as the lower plate of the MIM capacitor. An etch stop dielectric layer is used during...

20060145294 - Methods of forming capacitors: A method of forming a capacitor includes forming a conductive metal first electrode layer over a substrate, with the conductive metal being oxidizable to a higher degree at and above an oxidation temperature as compared to any degree of oxidation below the oxidation temperature. At least one oxygen containing vapor...

20060145293 - Semiconductor device and method for fabricating the same: A semiconductor device and a method for fabricating the same are provided. The method includes: forming a contact plug passing through an inter-layer insulation layer; sequentially forming a lower electrode layer, a dielectric layer and an upper electrode layer on the inter-layer insulation layer; patterning the upper electrode layer; patterning...

20060145296 - Tunable temperature coefficient of resistance resistors and method of fabricating same: Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the same polarity and different magnitude TCRs or having opposite polarity and about...

20060145297 - Voltage-dividing resistor and semiconductor device having the same: A voltage-dividing resistor enables a multi-step voltage division. The voltage-dividing resistor includes a polysilicon layer formed on a semiconductor substrate; a metal layer formed on a partial area of the polysilicon layer; an insulating interlayer covering the polysilicon layer and the metal layer; a first electrode for applying a first...

20060145298 - Semiconductor device: According to the present invention, there is provided a semiconductor device including a MOSFET, comprising: a second-conductivity-type semiconductor layer selectively formed in one surface portion of a first first-conductivity-type semiconductor layer; a second first-conductivity-type semiconductor layer selectively formed in a surface portion of said second-conductivity-type semiconductor layer; a first main...

20060145299 - Method for improving the electrical properties of active bipolar components: A method for improving electrical characteristics of active bipolar components is provided. In conventional methods for improving the electrical characteristics of active bipolar components, the controllability of an input signal via an output signal is significantly affected, or the transient behaviour, in particular in the high-frequency range, is only slightly...

20060145300 - Method for forming a one mask hyperabrupt junction varactor using a compensated cathode contact: A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction....

20060145301 - Semiconductor chip and semiconductor device: A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from...

20060145302 - Coating composition for electronic devices: Disclosed herein is an coating composition for electromagnetic wave shielding, which can effectively solve the problems of electromagnetic interference (EMI) and radio frequency interference (RFI) caused by electromagnetic waves generated from the internal elements of various electronic devices. The composition contains a silver-coated copper particles having fine particle size, so...

20060145303 - Impurity doped uv protection layer: An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the...

20060145304 - Forming a porous dielectric layer and structures formed thereby: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a dielectric layer utilizing a plasma, wherein the plasma comprises a porogen and substantially no oxidizing agent, and then applying energy to the dielectric layer, wherein the porogen disposed within the dielectric layer decomposes to form...

20060145305 - Forming a porous dielectric layer and structures formed thereby: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a dielectric layer utilizing a plasma, wherein the plasma comprises a porogen and substantially no oxidizing agent, and then applying energy to the dielectric layer, wherein the porogen disposed within the dielectric layer decomposes to form...

20060145306 - Composition for forming low dielectric thin film comprising porous nanoparticles and method of preparing low dielectric thin film using the same: A composition for forming a low dielectric thin film, which includes a silane polymer, porous nanoparticles and an organic solvent, and a method of preparing a low dielectric thin film using the same. The low dielectric thin film prepared using the composition of the current invention may exhibit a low...

20060145307 - High aspect-ratio pn-junction and method for manufacturing the same: A semiconductor device having high-aspect-ratio PN-junctions is provided. The semiconductor device includes a conducting layer. The semiconductor device further includes a plurality of first doped regions formed over the conducting layer. The sidewalls of the doped regions are doped to form PN-junctions. The semiconductor device also includes a plurality of...

20060145308 - On-chip circuit pad structure: Shielded circuit pad is provided where the parasitic capacitance is tuned out by the inclusion of a shunt transmission line stub which reduces the substrate induced loss in millimeter-wave applications. The circuit pad is located on the substrate, with a shield located beneath the circuit pad, and the shunt transmission...

20060145310 - Device for detecting rf power and fabrication method thereof: Disclosed herein is a low-cost low power-consumed RF power detecting device used as a core component necessary for intelligence, miniaturization and downpricing of a wireless communication system, and a fabrication method thereof. The RF power detecting device according to the present invention comprises: an upper substrate including a signal transmission...

20060145309 - Line element and semiconductor circuit applied with line element: A semiconductor circuit in which low impedance characteristics required for a decoupling circuit are ensured up to a band of several hundreds of MHz or above in the situation where digital circuits are rushing into GHz age, and a semiconductor circuit exhibiting low impedance characteristics even in a band of...

20060145312 - Dual flat non-leaded semiconductor package: A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled...

20060145311 - Low cost lead-free preplated leadframe having improved adhesion and solderability: A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a stack adherent to the base metal. The stack comprises a nickel layer (201) in contact with the base metal, a palladium...

20060145313 - Semiconductor package device having reduced mounting height and method for manufacturing the same: A semiconductor package device including a lead frame including a die pad to which a semiconductor chip is attached and a plurality of terminals for electrical interconnection of the semiconductor chip to an external device. The device also includes a plurality of bonding wires for electrically interconnecting the terminals to...

20060145315 - Flexible substrate for package: The invention provides a flexible substrate for package of a semiconductor die. The flexible substrate includes a flexible insulating film, a plurality of first leads substantially formed on the flexible insulating film, and at least one loop-shaped second lead substantially formed on the flexible insulating film. The at least one...

20060145314 - Tape for tape carrier package: The invention provides a tape for a tape carrier package. The tape includes a flexible insulating film. The flexible insulating film is divided into a plurality of units arranged successively, and each of the units has a device hole and a plurality of leads. The plurality of leads are formed...

20060145316 - Semiconductor package having enhanced heat dissipation and method of fabricating the same: A semiconductor package comprising a semiconductor chip and a first heat spreader adhered to the upper surface of the semiconductor chip is provided. The first heat spreader comprises a flat metal plate and a plurality of metal balls adhered to the flat metal plate. A method of fabricating the semiconductor...

20060145318 - Dfn semiconductor package having reduced electrical resistance: A DFN semiconductor package is disclosed. The package includes a leadframe having a die bonding pad formed integrally with a drain lead, a source lead bonding area and a gate lead bonding area, the source lead bonding area and the gate lead bonding area being of increased area, a die...

20060145317 - Leadframe designs for plastic cavity transistor packages: The specification describes a plastic cavity package for semiconductor devices that provides additional mechanical integrity for leads that extend from the plastic housing. Portions of the leads that are within the plastic housing are provided with cutouts. When the plastic housing is formed, or when the cavity is filled with...

20060145322 - Circuit device and portable device: To provide a circuit device freed from constrains of a mounting direction. The circuit device according to the present invention includes: a conductive pattern for forming a die pad, a first bonding pad, and a second bonding pad; and a semiconductor element (TR) attached to the conductive pattern. The circuit...

20060145320 - Embedded heat spreader: In some embodiments an apparatus may comprise a semiconductor die, an elastomer layer attached to the die, a tape lead attached to the elastomer, a portion of the tape lead exposed through the elastomer to connect with the die, a polymer resin attached to the tape lead, and a thermally...

20060145319 - Flip chip contact (fcc) power package: This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip...

20060145321 - Microcomponent holder and method for manufacture thereof: Provided is a microcomponent holder for retaining a micro-scale component. The microcomponent holder includes at least one aperture for receiving a micro-scale component therein. At least one loop-shaped support member is disposed about the aperture for contacting the micro-scale component to retain the micro-scale component within the microcomponent holder. The...

20060145323 - Multi-chip package mounted memory card: A multi-chip package mounted memory card includes at least one multi-chip package mounted on a printed circuit board, and card connectors connected to electrode terminals on the multi-chip package via a wiring on the printed circuit board. The same or different types of multi-chip packages may be mounted on the...

20060145324 - Semiconductor package security features using thermochromatic inks and three-dimensional identification coding: Numerous embodiments of an apparatus and method for generating an identification feature are described. In one embodiment of the present invention, portions of an identification character printed with thermochromatic ink are distributed within a three-dimensional matrix of a multi-layer patch. The multi-layer patch may be disposed above a substrate....

20060145325 - Fbga and cob package structure for image sensor: A structure of package comprises a die placed on printed circuit board. A glass substrate is adhered on an adhesive film pattern to form an air gap area between the glass substrate and the chip. Micro lens are disposed on the chip. A lens holder is fixed on printed circuit...

20060145326 - Nano ic packaging: A package for an integrated circuit includes a chip having a plurality of nodes adapted to receive signals from or to output signals to an external circuit; and a frame having a plurality of contact points each coupled to one node of the chip and to a pad, wherein each...

20060145327 - Microelectronic multi-chip module: A method of fabricating a microelectronic multi-chip module comprises: providing a cavity down ball grid array having a die and solder balls on a die side thereof; providing a package including at least one die thereon on a die side thereof; stacking the package onto the backside of the ball...

20060145328 - Three dimensional package structure with semiconductor chip embedded in substrate and method for fabricating the same: A three dimensional package structure with semiconductor chip embedded in substrate and a method for fabricating the same are proposed. A carrier with at least one cavity is mounted on a first insulating layer, and at least one semiconductor chip is mounted on the first insulating layer and received in...

20060145329 - Lead frame for semiconductor device: A lead frame for semiconductor device has at least one bed frame capable of supporting a dual-pin-type chip, a plurality of suspension pin frames which extend from the bed frame in a first direction, and are disposed apart from each other in a second direction, and at least two beam...

20060145330 - Multilayer board and a semiconductor device: Preparing a bottom grounding layer eliminates grounding pins, thereby the number of signal pins can be increased in a multilayer board that includes a grounding layer, a signal layer, a power supply layer, a grounding via, a signal via, a power supply via and the like in the insulation material...

20060145331 - Printed circuit board including embedded chips and method of fabricating the same using plating: A method of fabricating a printed circuit board (PCB) including embedded chips, composed of forming a hollow portion for chip insertion through a substrate, inserting the chip into the hollow portion, fixing the chip to the substrate by use of a plating process to form a central layer having an...

20060145332 - Semiconductor devices having post passivation interconnections with a second connection pattern: An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the...

20060145334 - Semiconductor device: A semiconductor device includes an intermediate layer provided between a semiconductor element and a heat sink. The intermediate layer moderates thermal stress resulting from a difference between thermal expansion of the semiconductor element and thermal expansion of the heat sink arising due to heat produced by the semiconductor element. This...

20060145333 - Semiconductor device with a cooling element: A semiconductor device comprising a semiconductor component (12), particularly a power laser diode bar, disposed on a cooling element (20), wherein the cooling element (20) contains in its interior a cooling channel (26) for conducting a coolant. The coolant channel (26) comprises in at least one region (32) microstructures for...

20060145335 - Method for manufacturing semiconductor device having a pair of heat sinks: A semiconductor device includes a heater element; a first heat sink disposed on one side of the heater element; a second heat sink disposed on the other side of the heater element; and a resin mold for molding the heater element and the first and second heat sinks. The first...

20060145336 - Heat sink: A heat sink is formed of a plurality of plate members stacked together. Each plate member includes a body, a first sidewall extending from a lateral side of the body, a second sidewall extending from another lateral side of the body, two retaining members which are provided at the first...

20060145337 - Memory module with different types of multi chip packages: In an embodiment, a memory module includes a first group of multi chip packages, including one or more non-volatile memories, and a second group of multi chip packages, including one or more volatile memories, wherein the first and second groups of multi chip packages are electrically connected to a substrate....

20060145338 - Thin film with mems probe circuits and mems thin film probe head using the same: A flexible one-piece thin film with microelectro-mechanical systems (MEMS) probe circuits has a flexible non-conducting dielectric layer made from polyimide or silica, various electrical circuits arranged in multi-layered structure all embedded inside the dielectric layer, plural probes and circuit contacts protected by the dielectric layer from damage by way of...

20060145339 - Semiconductor package: A semiconductor package includes a semiconductor device and a passive component mounted and electrically coupled to a substrate. The passive component is disposed within a cavity portion formed on an upper surface of the substrate and the semiconductor device is disposed across the cavity portion of the substrate above the...

20060145340 - Substrate and method for fabricating the same: A substrate having a metallic panel and an insulator is provided. The metallic panel comprises two patterned metallic layers. The two patterned metallic layers are disposed on the respective sides of the metallic panel and connected with each other. The metallic panel has an upper surface and a lower surface....

20060145341 - Mounting pad structure for wire-bonding type lead frame packages: A chip package having a lead frame, a chip, a plurality of bonding wires, and an insulation material is provided. The lead frame comprises a die pad, a plurality of leads, a plurality of signal pads and a plurality of non-signal pads. The signal pads and non-signal pads are underneath...

20060145342 - Power semiconductor component and method for the production thereof: A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result,...

20060145343 - Bga package having half-etched bonding pad and cut plating line and method of fabricating same: A ball grid array (BGA) package having a half-etched bonding pad and a cut plating line and a method of fabricating the same. In the BGA package, the plating line is cut to form a predetermined uneven bonding pad using half-etching, thereby increasing the contact area between the bonding pad...

20060145344 - Semiconductor device: The miniaturization of a semiconductor device is aimed at. A package substrate have a plurality of terminals formed on the main surface, a plurality of lands formed on the back surface, through holes which are formed by laser beam machining and have been arranged at the upper part of each...

20060145345 - Bga package substrate and method of fabricating same: Disclosed is a ball grid array (BGA) package substrate, in which a wire bonding pad and a solder ball pad are formed on a via hole, making high freedom in design of a circuit pattern and a high density circuit pattern possible, and a method of fabricating the same....

20060145346 - Solid-state imaging device and method for making the same: A solid-state imaging device includes a semiconductor substrate, one or more wiring interlayer films disposed on or above the semiconductor substrate, and one or more metal wires embedded in the wiring interlayer films. The one or more wiring interlayer films are composed of a diffusion preventing material that prevents the...

20060145347 - Semiconductor device and method for fabricating the same: A semiconductor device includes a semiconductor element formed on a semiconductor substrate, a first interconnect formed over the semiconductor substrate so as to be electrically connected with the semiconductor element, and a second interconnect formed over the first interconnect with an interlevel insulation film made of an insulator having a...

20060145348 - Semiconductor device using metal nitride as insulating film and its manufacture method: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A...

20060145349 - Device comprising multi-layered thin film having excellent adhesive strength and method for fabricating the same: A device comprises a multi-layered thin film having excellent adhesion due to the method of fabricating the same. More particularly, the device includes a multi-layered thin film consisting of a tantalum nitride layer, a tantalum layer formed on the tantalum nitride layer, and a gold thin film formed on the...

20060145351 - Adhesion of a metal layer to a substrate and related structures: Methods and resulting structures are described in which a metal layer is adhered to a surface of a substrate. The methods involve applying a sacrificial acidic organic layer to the surface of the substrate prior to depositing the metal layer onto the substrate. During deposition of the metal layer, the...

20060145350 - High frequency conductors for packages of integrated circuits: High frequency conductors can be used with packages of integrated circuits. It includes metal traces on the surface of a semiconductor chip with integrated circuits as well as electrical connections of chips in a stack to an interposer or other interfaces which must comply with requirements for high frequencies such...

20060145352 - Electronic device: In an electronic device which realizes high-temperature-side solder bonding in temperature-hierarchical bonding, a bonding portion between a semiconductor device and a substrate is formed of metal balls made of Cu, or the like, and compounds formed of metal balls and Sn, and the metal balls are bonded together by the...

20060145353 - Semiconductor interconnect having dome shaped conductive spring contacts: An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for...

20060145354 - Diode: A diode having a press-fit base includes an axially extending mounting region for a semiconductor chip and a head wire affixed to the semiconductor chip. The head wire has a stepped wire connection or a region which forms a sealed housing together with the press-fit base and a sleeve. The...

20060145355 - Plug filling without step-height difference for dual damascene process: A method for manufacturing a dual damascene structure on a semiconductor substrate is provided. The method includes forming an insulator above the substrate and patterning the insulator to include a plurality of plug openings. A plug-filler material is used for filling one or more of the plug openings and extending...

20060145356 - On-chip cooling: A method and structure for forming an integrated circuit chip that forms thermal conductors in a second wafer, and bonds the second wafer to a first wafer. Then circuits are formed in the first wafer. The thermal conductors in the second wafer have a higher coefficient of thermal conductivity than...

20060145359 - Electronic parts packaging structure and method of manufacturing the same: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection...

20060145357 - Flip chip package structure: The invention provides a flip chip package structure. The flip chip package structure includes a substrate, a flip chip, a plurality of bumps, a first sealing material, and a second sealing material. The substrate has an upper surface and a plurality of pads formed on the upper surface. The flip...

20060145358 - Printed circuit board having reduced mounting height: A printed circuit board including an opening for receiving a semiconductor package having a plurality of external connections which protrude externally from side surfaces of the semiconductor package. The board also includes a plurality of board connectors electrically interconnected to the plurality of external connections of the package and formed...

20060145360 - Wound capacitor: A wound capacitor has a lead configuration that enables enhanced control over equivalent series resistance (ESR) and equivalent series inductance (ESL). The capacitor has a case and a wound foil disposed within the case. A ball-and-lead configuration is coupled to the foil and extends from the case....

20060145363 - Semiconductor device fabricating apparatus and semiconductor device fabricating method: A semiconductor device fabricating method comprises a substrate forming step of forming a plurality of separate conductive pads 20 on an adhesive layer included in an adhesive sheet 50, and a semiconductor chip mounting step of bonding semiconductor chips to the adhesive sheet 50 with surfaces thereof not provided with...

20060145361 - Semiconductor device package and manufacturing method thereof: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The...

20060145362 - Semiconductor package and fabrication method of the same: A semiconductor package and a fabrication method of the same are proposed. A chip formed with a plurality of electrode pads on an active surface thereof, and a substrate having a first surface, a corresponding second surface and at least one opening penetrating therethrough are provided. A part of the...

20060145364 - Filling paste structure and process for wl-csp: A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate....

20060145365 - Combined information display and information input device: A combined information display and information input device comprising a matrix of independently addressable light emitting devices and a plurality of light sensing devices, the light emitting devices comprising organic light emitting diodes comprising organic light emitting material positioned between a low work function electrode and a high work function...