Active solid-state devices (e.g., transistors, solid-state diodes) inventions 06/06

20060138392 - Mild methods for generating patterned silicon surfaces: The invention provides methods for making self-assembling monolayers on silicon surfaces using mild conditions....

20060138393 - Ge precursor, gst thin layer formed using the same, phase-change memory device including the gst thin layer, and method of manufacturing the gst thin layer: Provided are a Ge precursor for low temperature deposition containing Ge, N, and Si, a GST thin layer doped with N and Si formed using the same, a memory device including the GST thin layer doped with N and Si, and a method of manufacturing the GST thin layer. The...

20060138394 - Structure having pores, device using the same, and manufacturing methods therefor: A minute structure is provided in which electroconductive paths are only formed in nanoholes, and a material is filled in the nanoholes, which are disposed in a specific area, by using the electroconductive paths. The minute structure comprising pores comprises a) a substrate, b) a plurality of electroconductive layers formed...

20060138395 - Semiconductor photoelectric surface and its manufacturing method, and photodetecting tube using semiconductor photoelectric surface: A semiconductor photocathode of the present invention is provided with: a support substrate 10; a photoelectric surface 30 which is formed of a plurality of semiconductor layers layered on this support substrate 10 and which emits photoelectrons from a photoelectron emitting surface 341 in response to the incidence of light...

20060138396 - Quantum-dot infrared photodetector: A quantum-dot infrared photodetector comprises a semiconductor substrate; a buffer layer formed on the semiconductor substrate; an undoped first obstructing layer formed on the buffer layer; a first quantum-dot layer formed on the first barrier layer; a heavily doped first contact layer formed on the first quantum-dot layer; a second...

20060138397 - Manipulation of conductive and magnetic phases in an electron trapping semiconducting: A semiconductor strip array that can be configured to exhibit distinct electrical and/or magnetic phase characteristics according to the many-body effects phenomenon in electron gases is disclosed. The strip array can be incorporated into a MOSFET architecture and utilized in amplifier and memory cell applications. Significantly, the strip array can...

20060138398 - Semiconductor device and fabrication method thereof: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and...

20060138409 - (4,5,9,10-tetrahydro-pyren-2-yl)-carbamic acid 4-(2-methylsulfanyl-alkyl)-3,5-dinitro-benzyl ester, method of synthesizing thereof, and molecular electronic device using the same: A new compound derivative that can be used to form a unit molecular film as a rectifier in a molecular electronic device, a new rectifying compound (4,5,9,10-tetrahydro-pyren-2-yl)-carbamic acid 4-(2-methylsulfanyl-alkyl)-3,5-dinitro-benzyl ester and its derivative (4,5,9,10-Tetrahydro-pyren-2-yl)-carbamic acid 4-(2-methylsulfanyl-alkyl)-3,5-dinitro-benzyl ester, and methods of synthesizing the compounds are provided....

20060138401 - Electronic devices comprising conductive members that connect electrodes to other conductive members within a substrate and processes for forming the electronic devices: An electronic device includes a substrate including a pixel driving circuit, a first conductive member, and a second conductive member. The first and second conductive members are spaced apart, the first conductive member is connected to the pixel driving circuit, and the second conductive member can be part of a...

20060138407 - Method for manufacturing semiconductor device having super junction construction: A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to...

20060138408 - Multifunctional linker molecules for tuning electronic charge transport through organic-inorganic composite structures and uses thereof: in which X is the central body of the molecule, FUNC1 and FUNC2 independently of each other are molecular groups introducing a dipole moment and/or capable of forming intermolecular and/or intramolecular hydrogen bonding networks, and CON1and CON2 independently of each other are molecular groups binding to nanostructured units comprising metal...

20060138400 - Novel compounds capable of forming photoconvertible organic thin film and articles having organic thin film: The present invention relates to a compound which is flexibly amenable to the alteration, without impairing its photosensitivity, of its structural moiety which affects film forming ability and the resulting surface properties, the compound being capable of undergoing surface alteration by irradiation with relatively low energy wavelength, and of forming...

20060138406 - Ofet structures with both n- and p-type channels: The present invention provides a dual organic field-effect transistor (OFET) structure and a method of fabricating the structure. The dual OFET structure includes an n-type organic semiconductor layer and a p-type organic semiconductor layer in contact with each other along an interface and forming a stack. The dual OFET structure...

20060138402 - Organic electronic device and method to manufacture same: An organic electronic device to emit or receive radiation includes a cathode, a first layer including a salt, a second layer including an active organic material, and an anode. A method to manufacture an organic electronic device to emit or receive radiation includes depositing a cathode, depositing a first layer...

20060138403 - Organic electronic devices including pixels: An organic electronic device includes a pixel. The pixel includes a first transistor and a capacitive electronic component. In one embodiment, the first transistor is an under-gated TFT, and a first portion of a first conductive member is a gate electrode of the first transistor. A second portion of the...

20060138404 - Organic-inorganic composite insulating material for electronic element, method of producing same and field-effect transistor comprising same: A method of producing an organic-inorganic composite insulating material for electronic element comprises subjecting a mixture of an organic polymer or its solution and a metal alkoxide or its solution as a starting material to sol-gel reaction of the metal alkoxide in the presence of the organic polymer....

20060138399 - Removing solution: The present invention provides a resist-removing solution for low-k film and a cleaning solution for via holes or capacitors, the solutions comprising hydrogen fluoride (HF) and at least one member selected from the group consisting of organic acids and organic solvents. The invention also provides a method of removing resist...

20060138405 - Thin film transistor, flat panel display including the thin film transistor, and method for manufacturing the thin film transistor and the flat panel display: A thin film transistor having a transformed region that provides the same result as patterning a semiconductor layer, a flat panel display having the thin film transistor and a method for manufacturing the thin film transistor and the flat panel display are disclosed. The thin film structure includes a gate...

20060138410 - Method for measuring information about a substrate, and a substrate for use in a lithographic apparatus: A method for measuring information provided by a substrate is disclosed. The substrate includes a feature that has been created by a lithographic apparatus. The method includes projecting a beam of light onto a marker disposed above and/or near the feature on the substrate, and detecting information provided by the...

20060138411 - Semiconductor wafer with a test structure, and method: The invention proposes a semiconductor wafer with a test structure for detecting parasitic contact structures on the semiconductor wafer, in which a first interconnect plane (A) contains interconnects (1) running parallel to one another and a second interconnect (2) that is arranged between the latter. The two first interconnects (1)...

20060138412 - Cmos image sensor and fabricating method thereof: A CMOS image sensor and fabricating method thereof are provided, in which a microlens is additionally formed on a planarizing layer prior to a color filter forming step and by which transmission efficiency of light incident on a photodiode enhances performance of the image sensor. The CMOS image sensor includes...

20060138413 - Method of manufacturing semiconductor device: Disclosed is a method of manufacturing a semiconductor device, comprising forming a gate electrode on a main surface of a semiconductor substrate via a gate insulating film, laminating sequentially a first insulating film with oxidation resistance and a silicon film on the main surface of the semiconductor substrate on which...

20060138424 - Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion: A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the...

20060138420 - Display, array substrate, and display manufacturing method: Each pixel of a display includes a first thin film transistor whose source is connected to a first power supply terminal, a second thin film transistor which is different in conduction type from the first thin film transistor and whose source and drain are connected to the drain of the...

20060138419 - Liquid crystal display and panel therefor: A thin film transistor array panel according to an embodiment of the present invention includes: a gate line; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor; and a shielding...

20060138417 - Liquid crystal display device and fabricating method thereof: A thin film transistor substrate and a fabricating method thereof for simplifying a process are disclosed. In a liquid crystal display device according to the present invention, a gate line is provided on a substrate. A data line crosses the gate line with having a gate insulating film therebetween to...

20060138416 - Liquid crystal display device and method of fabricating the same: A display device includes a substrate having a display region and a driver region; a gate line and a data line crossing each other to define a pixel region in the display region, the pixel region having a pixel electrode; an insulation layer between the gate line and the data...

20060138418 - Organic light emitting display and method of fabricating the same: An organic light emitting display (OLED) and a method of fabricating the same are provided. The method includes forming the OLED having upper and lower substrates that emit different colors from each other and coupling the upper and lower substrates together....

20060138421 - Photoelectric conversion element and display device including the same: A photoelectric conversion element includes a semiconductor layer including a pair of p+ regions in which p-type impurities are doped, and a p− region which is disposed between the p+ regions and has a lower p-type impurity concentration than the p+ regions. A gate electrode is formed over the p−...

20060138415 - Pixel structure, thin film transistor and fabricating method thereof: A method of fabricating a pixel structure is disclosed. A substrate having a color filter layer thereon and a leveling layer further covers the color filter layer is provided. A first metal layer is formed over the leveling layer. The first metal layer is patterned to define a source/drain. A...

20060138414 - Thin film transistor panel for multi-domain liquid crystal display: A thin film transistor array panel is provided, which includes: an insulating substrate; a plurality of first signal lines formed on the insulating substrate; a plurality of second signal lines formed on the insulating substrate and intersecting the first wire in an insulating manner; a pixel electrode formed in a...

20060138422 - Thin film transistor substrate of horizontal electric field type liquid crystal display device and fabricating method thereof: A thin film transistor substrate of horizontal electric field type includes: a gate line and a first common line formed on a substrate to be in parallel to each other; a data line crossing the gate line and the first common line with a gate insulating film therebetween to define...

20060138423 - Thin-film transistor, thin-film transistor sheet and their manufacturing method: Disclosed are a process of manufacturing a thin-film transisitor sheet and a thin-sheet transistor sheet manufactured by the process, the process comprising providing a gate busline on a substrate, providing, on the surface of the substrate on the gate busline side, an insulation layer capable of receiving a fluid electrode...

20060138425 - Methods of forming semiconductor constructions: Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed crystalline lattice. The relaxed crystalline lattice...

20060138427 - Hybrid circuit and electronic device using same: There is disclosed a hybrid circuit in which a circuit formed of TFTs in integrated with an RF filter. The TFTs are fabricated on a quartz substrate. A ceramic filter forming the RF filter is fabricated on another substrate. Terminals extend through the quartz substrate. The TFTs are connected with...

20060138426 - Liquid crystal display device and fabricating method thereof: A liquid crystal display device according to an embodiment of the present invention includes: a gate line formed on a substrate; a data line to provide a pixel area by crossing the gate line with a gate insulating film therebetween; a common line formed in parallel to the gate line;...

20060138428 - Liquid crystal display device and fabricating method thereof, and thin film patterning method applied thereto: A liquid crystal display device, including: a gate line on a substrate; a data line crossing the gate line with a gate insulating film therebetween to define a pixel area; a thin film transistor connected to the gate line and the data line; a semiconductor pattern which forms a channel...

20060138429 - Liquid crystal display device and method for fabricating the same: A liquid crystal display device according to an embodiment of the present invention a includes: a gate line on a substrate; a data line crossing the gate line to define a pixel area; a thin film transistor connected to the gate line and the data line; a semiconductor pattern extended...

20060138430 - Heteroisomer boron carbide devices: Semiconductor devices formed using boron carbide heteroisomer junctions or interfaces are provided. The boron carbide heteroisomer junction devices can be incorporated into diodes and transistors....

20060138431 - Light emitting device structure having nitride bulk single crystal layer: The object of this invention is to provide a high-output type nitride light emitting device. The nitride light emitting device comprises an n-type nitride semiconductor layer, a p-type nitride semiconductor layer and an active layer therebetween, wherein the light emitting device comprises a gallium-containing nitride semiconductor layer prepared by crystallization...

20060138433 - Optical combiner/decombiner with reduced insertion loss: A photonic integrated circuit that includes a plurality of active and passive components on a substrate where one of the components is an optical combiner/decombiner having at least one free space coupler region and a plurality of longitudinal ridge waveguides each extending in the circuit from a first region of...

20060138432 - Semiconductor light emitting device and method of manufacturing the same: Provided is a nitride semiconductor light emitting diode and a method of manufacturing the same. The method includes sequentially forming a first semiconductor layer, an active layer, and a second semiconductor layer on a substrate, in-situ depositing a mask layer on a region of the surface of the second semiconductor...

20060138434 - Semiconductor optical devices: A semiconductor optical device (e.g. a resonant cavity device in this form of an LED or a laser) comprises a single substrate arranged for emitting light (O) for incidence on a sample or other element and also responsive to light (D), e.g. of a different wavelenght, received back from this...

20060138435 - Multiple component solid state white light: A white light emitting lamp is disclosed comprising a solid state ultra violet (UV) emitter that emits light in the UV wavelength spectrum. A conversion material is arranged to absorb at least some of the light emitting from the UV emitter and re-emit light at one or more different wavelengths...

20060138439 - High radiance led chip and a method for producing same: The invention concerns a light-emitting diode chip comprising a radiation-emitting active region and a window layer. To increase the luminous efficiency, the cross-sectional area of the radiation-emitting active region is smaller than the cross-sectional area of the window layer available for the decoupling of light. The invention is further directed...

20060138437 - Lens and led using the lens to achieve homogeneous illumination: A lens and an LED using the lens to achieve homogeneous illumination include a region. The region around the optical axis of a lens is designed to be concave and form a divergent surface. The upper surface of the lens is a continuous curved surface to diverge the high-intensity light...

20060138436 - Light emitting diode package and process of making the same: A light emitting diode (LED) package and process of making the same includes a silicon-on-insulator (SOI) substrate that is composed of two silicon based materials and an insulation layer interposed therebetween. The two silicon based materials of silicon-on-insulator substrate are etched to form a reflective cavity and an insulation trench,...

20060138440 - Light-emitting diode lamp and light-emitting diode display device: The light-emitting diode lamp has a light-emitting diode chip mounted on a cup-shaped mounting portion of a lead frame. The mounting portion is formed at one end of a lead portion of the lead frame. The light-emitting diode chip and the mounting portion are embedded in a convex shape lens...

20060138438 - Method for manufacturing color element film-equipped substrate, color element film-equipped substrate, electro-optical device, and electronic device: A method for manufacturing a color element film-equipped substrate includes: forming a bank, in which a first layer and a photo-curing second layer are laminated over a base, and parts of the first layer and the second layer are removed after exposing and developing the first layer and the second...

20060138442 - Diode housing: A housing accommodating a semiconductor chip is set out. The housing and chip may be used for sending and/or receiving radiation. Popular applications of the housing may be in light emitting diodes. The housing includes a conductor strip that is punched into two electrically isolated portions. The housing further includes...

20060138441 - Light source module and method for production thereof: A light source module having a plurality of LEDs connected to a metal carrier (4) by means of an insulating layer (3). In order to afford protection against mechanical effects and in order to form a reflector, the LEDs are surrounded by a frame (10), which is segmented into a...

20060138443 - Encapsulation and packaging of ultraviolet and deep-ultraviolet light emitting diodes: Disclosed are the materials and methods used to package and encapsulate UV and DUV LEDs. These LEDs have emission wavelengths in the range from around 360 nm to around 200 nm. The UV/DUV LED die or its flip-chip bonded subassembly are disposed in a low thermal resistance packaging house. Either...

20060138444 - Flip-chip bonding structure of light-emitting element using metal column: A flip-chip bonding structure of a light-emitting element is provided. The structure improves a heat emission efficiency by using a metal column having a high thermal conductivity instead of a solder bump. The structure includes a light-emitting element, a sub-mount, and a metal column. The metal column connects the light-emitting...

20060138445 - Gan-based and zno-based led: Light emitting diodes (LEDs) with various electrode structures which preferably provide increased performance. In some embodiments the LEDs are GaN-based and in some embodiments the LEDs are ZnO-based, with a sapphire substrate or a ZnO substrate. In some embodiments the LEDs are hybrid GaN-based ZnO based LEDs....

20060138446 - Algainn based optical device and fabrication method thereof: The present invention relates to an AlGaInN based optical device fabricated by a new p-type AlGalnN:Mg growth method and method for manufacturing the same, including a p-type nitride semiconductor layer that is grown using both NH3 and a hydrazine based source as a nitrogen precursor, thereby an additional subsequent annealing...

20060138448 - Compound semiconductor and compound semiconductor device using the same: A back electrode 6 is formed in the back of a Si single crystal substrate 2 of a compound semiconductor in which an n-type 3C-SiC single crystal buffer layer 3 having a thickness of 0.05-2 μm, a carrier concentration of 1016-1021/cm3, a hexagonal InwGaxAl1-w-xN single crystal buffer layer 4 (0≦w<1,...

20060138449 - Gallium nitride based light-emitting device: A manufacturing method and a thus produced light-emitting structure for a white colored light-emitting device (LED) and the LED itself are disclosed. The white colored LED includes a resonant cavity structure, producing and mixing lights which may mix into a white colored light in the resonant cavity structure, so that...

20060138447 - Light emitting diode: The invention relates to a light emitting diode having at least one (semi)conductive electroluminescent active layer which comprises at least two different electroluminescent functionalities, wherein the emission spectrum of the diode exhibits at least two intensity maxima. The invention further relates to a detector which comprises a light emitting diode...

20060138450 - Schottky diode with a vertical barrier: A Schottky diode with a vertical barrier extending perpendicularly to the surface of a semiconductor chip having a vertical central metal conductor in contact on the one hand with the substrate of the semiconductor chip with an interposed interface forming a Schottky barrier, and on the other hand with radially-extending...

20060138451 - Structure having light modulating film and light control device using the same: A structure includes a substrate and a light modulating film formed on top of the substrate. The light modulating film is made of polycrystalline PLZT containing Pb, Zr, Ti, and La as constituent elements. The film has a La concentration in the range of 5 at % to 30 at...

20060138452 - Power semiconductor module: A power semiconductor module (1) with a housing (2) and at least one semiconductor chip (3, 3′) located in it is devised. At least one semiconductor chip (3, 3′) has a first main electrode side (31) and a second main electrode side (32) opposite the first main electrode side, the...

20060138453 - Organic photosensitive optoelectronic device having a phenanthroline exciton blocking layer: An organic photosensitive optoelectronic device, having an anode, a cathode, and an organic blocking layer between the anode and the cathode is described, wherein the blocking layer comprises a phenanthroline derivative, and at least partially blocks at least one of excitons, electrons, and holes....

20060138454 - Semiconductor device using a nitride semiconductor: A semiconductor device includes: a first semiconductor layer represented by a composition formula AlxGa1-xN (0≦x≦1); a first conductivity type or non-doped second semiconductor layer represented by a composition formula AlyGa1-yN (0≦y≦1, x<y) and formed on the first semiconductor layer; a second conductivity type third semiconductor layer represented by a composition...

20060138456 - Insulating gate algan/gan hemt: AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer...

20060138457 - Nitride-based semiconductor device of reduced current leakage: A high electron mobility transistor is disclosed which has a double-layered main semiconductor region formed on a silicon substrate via a multilayered buffer region. The multilayered buffer region is in the form of alternations of an aluminum nitride layer and a gallium nitride layer. The main semiconductor region, buffer region,...

20060138455 - Silicon carbide on diamond substrates and related devices and methods: A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide...

20060138458 - Semiconductor device and method of manufacturing the same: This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up HBT, reduction in base-collector junction capacity....

20060138460 - Semiconductor device and radio communication device: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (seven) of the unit transistors Q, and transistor...

20060138459 - Semiconductor device, manufacturing method of the same and electronic device: The HBT according to the present invention is obtained by successively forming, over the main surface of a substrate made of a compound semiconductor, a sub-collector layer, a collector layer, a base layer, an emitter layer, a collector electrode electrically connected to the collector layer, a base electrode electrically connected...

20060138461 - Electrode wiring substrate and display device: An electrode-wiring substrate includes first routing wires (108) made of gate material for forming gate electrode wires (105) and second routing wires (110) made of source material for forming source electrode wires (106). The first routing wires (108) and the second routing wires (110) are arranged alternately so as not...

20060138462 - Method of making a semiconductor device: Disclosed is a method of making a semiconductor device in which a main pattern is formed through a photolithography process over a low-density pattern area having a relatively small number of patterns to be formed in certain areas as compared to the other areas. According to the method at least...

20060138463 - Semiconductor integrated circuit devices including sram cells and flash memory cells and methods of fabricating the same: Semiconductor integrated circuit devices having SRAM cells and flash memory cells are provided. The devices include an integrated circuit substrate having an SRAM cell region, a flash memory cell region and a logic circuit region. An isolation layer is provided in a predetermined region of the substrate. The isolation layer...

20060138464 - Standard cell, standard cell library, semiconductor device, and placing method of the same: Of a plurality of standard cells in which an N-well region and a P-well region are vertically formed, some standard cells have a border line between the N-well region and the P-well region which is set to be a low height (first height), and other standard cells have a border...

20060138465 - 3-d column select circuit layout in semiconductor memory devices: A column select circuit in a Static Random Access Memory (SRAM) having a three-dimensional layout can include a lower CMOS layer in a substrate and an upper NMOS layer above the lower layer. An intermediate PMOS layer is located between the upper NMOS layer and the lower CMOS layer....

20060138466 - Layout of semiconductor memory device and method of controlling capacitance of dummy cell: Provided are a layout of a semiconductor memory device capable of minimizing an occupation area of a dummy cell array and a method of controlling capacitance of a dummy cell to be same with that of the memory cell. The layout includes a dummy cell connected to one side of...

20060138467 - Method of forming a small contact in phase-change memory and a memory cell produced by the method: A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a width and an exposed length of a bottom electrode. The method allows the formation of very small phase-change memory cells....

20060138469 - Semiconductor device and fabricating method thereof: A semiconductor device and fabricating method thereof can prevent an electrical characteristic degradation of the semiconductor device when a boarderless type contact is formed. The device may include a transistor on a semiconductor substrate, an oxynitride layer on the semiconductor sustrate,an insulating interlayer on the oxynitride layer, a metal line...

20060138468 - Semiconductor device with increased channel length and method for fabricating the same: A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar active region; a gate insulation layer formed over the...

20060138470 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are disclosed, in which a dark current is prevented from being generated between a device isolation film and a photodiode region to improve characteristics of the image sensor....

20060138471 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are disclosed, in which a dead zone and a dark current are simultaneously reduced by selective epitaxial growth. The CMOS image sensor includes a first conductive type semiconductor substrate, a second conductive type impurity ion area, a gate electrode,...

20060138472 - Cmos image sensor: A CMOS image sensor includes a photo sensing device for generating photo charges, a floating diffusion region for storing the photo charges generated by the photo sensing device therein, a transfer transistor connected between the photo sensing device and the floating diffusion region for transferring the photo charges generated by...

20060138473 - Semiconductor device and manufacturing method thereof: A semiconductor device having a plurality of phase change devices rewritably storing data, comprising: an insulating film deposited on a semiconductor substrate using an insulating material having sufficient adhesion to a chalcogenide-based phase change material; a chalcogenide film formed by embedding the chalcogenide-based phase change material in a hole formed...

20060138474 - Recess gate and method for fabricating semiconductor device with the same: A recess gate and a method for fabricating a semiconductor device with the same are provided. The recess gate includes: a substrate; a recess formed with a predetermined depth in a predetermined portion of the substrate; a gate insulation layer formed over the substrate with the recess; a gate polysilicon...

20060138477 - Asymmetric recessed gate mosfet and method for manufacturing the same: Disclosed are an asymmetric recessed gate MOSFET, and a method for manufacturing the same. The asymmetric recessed gate MOSFET comprises: recess regions formed at a predetermined depth in a semiconductor; recessed gate electrodes formed at a predetermined height on a semiconductor substrate by gap-filling the recess regions, and misaligned with...

20060138476 - Dc amplifier and semiconductor integrated circuit therefor: A rectangular parallelepiped projecting portion 21 having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion 21. A source and a drain...

20060138475 - Method of manufacturing a semiconductor device and semiconductor device obtained by means of such a method: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (1) and a semiconductor body (2) comprising a first (N-MOS)PET (3) with a first channel region (3A) and a first gate electrode (3B) which includes a first conductor and which is separated from the channel...

20060138478 - Semiconductor device and method of forming same: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a gate spacer disposed on both sidewalls of the gate pattern, and a fixed charge layer disposed in the semiconductor substrate below the gate spacer. Elements generating fixed charges are injected into the fixed charge layer. A layer...

20060138479 - Tensile strained substrate: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a...

20060138480 - A cmos imager with cu wiring and method of eliminating high reflectivity interfaces therefrom: An image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal that traverses the...

20060138484 - Cmos image sensor and method for fabricating the same: A CMOS image sensor includes a first conductive type semiconductor substrate having an active region and a device isolation region, a device isolation film formed in the device isolation region of the semiconductor substrate, a second conductive type diffusion region formed in the active region of the semiconductor substrate, and...

20060138483 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor includes a semiconductor substrate with a first conductive type including a photodiode region and a transistor region, a gate electrode formed on the transistor region of the substrate, a first impurity region with a second conductive type formed in a portion of the semiconductor substrate between...

20060138482 - Cmos image sensor and method of fabricating the same: A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and an isolation layer. The present invention includes a first-conductivity-type doping area formed in the device isolation area of the substrate, the first-conductivity-type doping...

20060138481 - Solid-state imaging device and method for manufacturing the same: A solid-state imaging device includes a semiconductor substrate (1) with a photodetector portion (15). The photodetector portion (15) includes a p-type first impurity region (surface inversion layer) (6) formed in the semiconductor substrate (1) and an n-type second impurity region (photoelectric conversion region) (4) formed below the surface inversion layer...

20060138489 - Active pixel sensor with coupled gate transfer transistor: A complementary metal-oxide semiconductor (CMOS) active pixel sensor includes a photodiode, a transfer transistor with a coupled gate, a reset transistor and a signal transfer circuit, where the photodiode generates electric charges in response to incident light, the transfer transistor transfers the electric charges integrated in the photodiode to a...

20060138485 - Cmos image sensor and method for fabricating the same: A CMOS image sensor that includes a semiconductor substrate with a plurality of photodiodes arranged at fixed intervals on the semiconductor substrate. A light-shielding layer partially overlaping the plurality of photodiodes and an insulating interlayer are formed on an entire surface of the semiconductor substrate including the plurality of photodiodes....

20060138486 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same forms a trench-shaped transfer gate that serves to better transfer electrons generated by light incident on photodiodes, thus obtaining improved transfer characteristics. The CMOS image sensor includes a semiconductor substrate having at least one active region defined by a...

20060138487 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are disclosed, in which color filter layers are formed after microlenses are formed, to simplify process steps and maximize transmission efficiency of light, thereby improving performance of the image sensor. The CMOS image sensor includes a plurality of photodiodes...

20060138490 - Cmos image sensor and method for fabricating the same: A method for fabricating a CMOS image sensor includes forming a photodiode region, a gate electrode, an interlayer dielectric layer, a metal line, and a passivation layer on a semiconductor substrate having a pixel array region and a peripheral circuit region, forming a color filter layer having a plurality of...

20060138492 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are disclosed, in which an impurity ion area is formed in a semiconductor substrate to form a transfer path for optical charges. Dead zone and dark current characteristics are thereby simultaneously improved. The CMOS image sensor includes a first...

20060138493 - Cmos image sensor and method for fabricating the same: A CMOS image sensor includes a first conductive type semiconductor substrate defined by a photodiode area and a transistor area, a trench formed in the semiconductor substrate corresponding to a transfer transistor of the transistor area, a gate electrode of the transfer transistor, formed in the trench, a second conductive...

20060138488 - Image sensor test patterns for evaluating light-accumulating characteristics of image sensors and methods of testing same: An image sensor test pattern provides time efficient optical testing of CMOS image senors at a single luminous intensity. These test patterns include at least first and second arrays of pixels having different light-accumulating characteristics. The different light-accumulating characteristics may be achieved multiple different ways. In some cases, the photodiodes...

20060138495 - Method and apparatus for collecting photons in a solid state imaging sensor: A photon collector has a reflecting metal layer to increase photon collection efficiency in a solid state imaging sensor. The reflecting metal layer reflects incident light internally to a photosensor. A plurality of photon collectors is formed in a wafer substrate over an array of photosensors. The photon collector is...

20060138491 - Method for fabricating cmos image sensor: A CMOS image sensor and a method for fabricating the same are disclosed, in which transfer characteristics are improved. The method includes forming a photodiode region and a second conductive type ion region on a surface of a first conductive type substrate by implanting a second conductive type impurity ion...

20060138494 - Photodiode in cmos image sensor and fabricating method thereof: A photodiode in a CMOS image sensor and fabricating method thereof are disclosed, by which the charge accumulation capacity is enhanced by enlarging a size of a photodiode area. The sensor includes a first epitaxial layer on a semiconductor substrate, a first photodiode area in the first epitaxial layer, a...

20060138497 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are disclosed, in which double microlenses are formed using materials having different refractive indexes to improve concentration efficiency of light, thereby improving the characteristics of the image sensor....

20060138500 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and method for fabricating the same improve image characteristics by eliminating the thickness of a planarization layer. The CMOS image sensor includes a semiconductor substrate; a plurality of active devices, provided in a predetermined surface of the semiconductor substrate, for generating electrical charges according to an...

20060138498 - Cmos image sensor and method for manufacturing the same: Disclosed are a CMOS image sensor capable of improving the focusing capability of light and a method for manufacturing the same. The CMOS image sensor includes a plurality of first micro-lenses formed in the upper part of the planarization layer, each of the first micro-lenses arranged over a corresponding photodiode,...

20060138496 - Semiconductor device: A semiconductor device comprising: a first light shielded region including a first semiconductor element, the first light shielded region being defined by a first light shielding wall provided in the periphery thereof; a second light shielded region including a second semiconductor element, the second light shielded region being defined by...

20060138499 - Solid-state image sensor, method of manufacturing the same, and camera: A solid-state image sensor of the present invention is a solid-state image sensor in which pixel cells are arranged on a semiconductor substrate, wherein each of the pixel cells includes: a photoelectric conversion unit that performs photoelectric conversion of incident light; and a microlens formed above the photoelectric conversion unit,...

20060138507 - Ferroelectric film, method of manufacturing ferroelectric film, ferroelectric capacitor, and ferroelectric memory: A ferroelectric film having a ferroelectric shown by a general formula (Pb1-dBid)(B1-aXa)O3, B including at least one of Zr and Ti, X including at least one of Nb and Ta, “a” being in a range of “0.05≦a≦0.4”, and “d” being in a range of “0<d<1”....

20060138503 - Ferroelectric memory: A ferroelectric memory comprises a first transistor connected between N1 and N2 nodes, a second transistor connected between the N2 node and an N3 node, a first transistor connected between P1 and P2 nodes, a second transistor connected between the P2 node and a P3 node, a first wiring formed...

20060138502 - Field-effect transistor with spin-dependent transmission characteristics and non-volatile memory using same: When a gate voltage VGS is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region. However, down-spin electrons from the nonmagnetic contact (3b) are not injected because of...

20060138508 - Insulating film and electronic device: An insulating film comprising: a first barrier layer;a well layer provided; and a second barrier layer is proposed. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer is provided on the first. barrier layer, and consists of a material...

20060138504 - Nonvolatile ferroelectric memory device: A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line,...

20060138501 - Semi-conductor dielectric component with a praseodymium oxide dielectric: A semiconductor component having a silicon-bearing layer and a praseodymium oxide layer, wherein arranged between the silicon-bearing layer and the praseodymium oxide layer is a mixed oxide layer containing silicon, praseodymium and oxygen. The layer is of a thickness of a maximum of 5 nanometers. A production process for such...

20060138506 - Semiconductor memory device and method for manufacturing the same: A semiconductor memory device includes a substrate having a semiconductor element formed thereon, an interlayer dielectric layer formed above the substrate, a plug formed in the interlayer dielectric layer, an adhesion layer formed in a region including a region above the plug, and a ferroelectric capacitor formed above the adhesion...

20060138505 - Tunneling magnetoresistance device with high magnetoimpedance (mi) effect: A tunneling magnetoresistance device with high magnetoimpedance effect, comprising: a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer which is located between the first ferromagnetic layer and the second ferromagnetic layer. Wherein an alternating current is applied to the tunneling magnetoresistance device, the tunneling magnetoresistance device...

20060138509 - Magnetic random access memory with lower switching field through indirect exchange coupling: A magnetic random access memory with lower switching field through indirect exchange coupling. The memory includes a first antiferromagnetic layer, a pinned layer formed on the first antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, a ferromagnetic free layer formed on the tunnel barrier layer, a metal...

20060138510 - Method for forming a stroage cell capacitor compatible with high dielectric constant materials: An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a...

20060138511 - Methods of manufacturing a capacitor including a cavity containing a buried layer: Capacitors include an integrated circuit (semiconductor) substrate and an interlayer dielectric disposed on the integrated circuit substrate and including a metal plug therein. A lower electrode is disposed on the interlayer dielectric and contacting the metal plug. The lower electrode includes a cavity therein and a buried layer in the...

20060138513 - Capacitors for semiconductor memory devices and methods of forming the same: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region,...

20060138512 - Semiconductor storage device: A semiconductor storage device is provided, which inhibits shorts between cells to improve operational reliability and contributes to high-speed operation. An active region (7) where DRAM cells are formed is defined by an isolation trench (40) formed in a silicon substrate (1). The isolation trench (40) has an isolation insulating...

20060138514 - Capacitor for a semiconductor device and manufacturing method thereof: Disclosed is a capacitor for a semiconductor device, comprising: a lower electrode formed over a predetermined lower structure on a semiconductor substrate; an aluminum oxynitride film formed over the lower electrode and having a low leakage current characteristic; a yttrium oxynitride film formed over the aluminum oxynitride film and having...

20060138516 - Method of forming dram device having capacitor and dram device so formed: In a method of forming a DRAM device having a capacitor and a DRAM device so formed, an interlayer dielectric having at least one layer is formed on a semiconductor substrate. The interlayer dielectric layer and a predetermined portion of the semiconductor substrate are sequentially etched to form a storage...

20060138515 - Semiconductor device and fabricating method of the same: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of...

20060138517 - Capacitor structure and fabricating method thereof: Disclosed are a vertical-type capacitor and a formation method thereof. The capacitor includes a first electrode wall and a second electrode wall perpendicular to a semiconductor substrate, and at least one dielectric layer on the substrate to insulate the first electrode wall from the second electrode wall. The first electrode...

20060138518 - Semiconductor device with silicon-germanium gate electrode and method for manufacturing thereof: A semiconductor includes a gate electrode having a SiGe film on a a gate dielectric film that is on a silicon substrate. The gate dielectric film includes an underlying interfacial layer on the substrate and a high-k dielectric film having higher dielectric constant than the underlying interfacial layer. The gate...

20060138519 - Float gate memory device: A float gate memory device comprises a bottom word line, a float channel layer formed on the bottom word line and kept at a floating state, a float gate, and a top word line formed on the float gate in parallel with the bottom word line. In the float gate...

20060138520 - Nonvolatile ferroelectric memory device: A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line,...

20060138521 - Charge trap insulator memory device: A charge trap insulator memory device comprises a plurality of memory cells connected serially, a first switching device, and a second switching device. In the plurality of memory cells, data applied through a bit line depending on potentials applied to a top word line and a bottom word line are...

20060138524 - Flash memory cell and method for manufacturing the same: An active region and a trench region are formed on a semiconductor substrate. The trench region is filled with a dielectric material to form an isolation layer. Oxide and polysilicon layers are formed on the semiconductor substrate. A second polysilicon layer, a second oxide layer, and a first polysilicon layer...

20060138522 - Flash memory devices comprising pillar patterns and methods of fabricating the same: Flash memory devices include pillar patterns formed between selected pairs of floating gates and control gate extensions that penetrate between selected pairs of floating gates are provided. Methods of fabricating the flash memory devices are also provided....

20060138525 - Method of fabricating a floating gate for a nonvolatile memory: A method of fabricating a gate structure (such as a floating gate) of a nonvolatile (e.g., flash) memory is described. After a polysilicon layer and a mask layer (e.g., silicon nitride) are formed on a semiconductor substrate, the silicon nitride layer is patterned and the polysilicon layer is partially etched....

20060138526 - Semiconductor device and method of manufacturing the same: Disclosed is a semiconductor device comprising a first conductive film serving as a floating gate and formed on a semiconductor film via a first gate insulating film, a second conductive film serving as a control gate and formed on the first conductive film via a second gate insulating film, and...

20060138523 - Semiconductor memory device and method of manufacturing the semiconductor memory device: Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate. A dielectric layer pattern including metal oxide doped with Group III...

20060138527 - Semiconductor devices, and electronic systems comprising semiconductor devices: The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or floating plate over the Si/Ge, and a pair of source/drain regions. The source/drain regions can extend into the Si/Ge. The memory or logic devices...

20060138528 - Charge trap insulator memory device: A charge trap insulator memory device comprises a bottom word line, a P-type float channel formed at the bottom word line and kept at a floating state, a charge trap insulator formed on the P-type float channel, a top word line formed on the charge trap insulator in parallel with...

20060138529 - Method and apparatus for operating a non-volatile memory array: A string of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of the selected memory cell. The charge storage state of the charge trapping structure affects the measured...

20060138530 - Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell: A non-volatile memory cell able to be written in a first direction and read in a second direction is described. The memory cell includes one or two charge trapping regions located near either the source or the drain, or both the source and the drain. During a programming operation, electrons...

20060138531 - Method for fabricating vertical cmos image sensor: A method of fabricating a vertical CMOS image sensor is disclosed, to improve the integration with the decrease in size of pixel by minimizing the lateral diffusion, in which phosphorous and arsenic ions are implanted while controlling the dose and energy, the method including forming a first photodiode in a...

20060138532 - Semiconductor device and manufacturing method of the same: In a semiconductor device having a package structure in which lead terminals connected to electrodes on both of the upper and lower surfaces of a semiconductor chip are exposed from both of the upper and lower surfaces and side surfaces of a sealing body formed of resin, electrodes of the...

20060138534 - Nonvolatile memory device, method for fabricating the same, and method for programming/erasing data in the same: A nonvolatile memory device, a method for fabricating the same, and a method for programming/erasing data in the same are provided. At least one of a plurality of device isolation films is filled with polysilicon and used as an acceleration line. The nonvolatile memory device includes a semiconductor substrate defined...

20060138535 - Semiconductor device having trench gate structure and manufacturing method thereof: A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region....

20060138533 - Vertical trench transistor: A vertical trench transistor has a first electrode, a second electrode and also a semiconductor body arranged between the first and second electrodes, there being formed in the semiconductor body a plurality of transistor cells comprising source region, body region, drift region and gate electrode and also contact holes for...

20060138537 - Method for manufacturing a high integration density power mos device: A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised...

20060138538 - P-channel power mis field effect transistor and switching circuit: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe....

20060138536 - Semiconductor device and method of manufacturing the same: A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on...

20060138539 - Process for treating a semiconductor wafer with a gaseous medium, and semiconductor wafer treated by this process: A process for treating a semiconductor wafer with a gaseous medium containing hydrogen fluoride and at least one oxidizing agent which oxidizes the surface of the semiconductor wafer, involves flowing the gaseous medium onto the surface of the semiconductor wafer at a relative velocity in the range from 40 mm/s...

20060138541 - Semiconductor device and method of manufacturing same: A high-speed, low-power-consumption semiconductor device has a thin-film Si layer with a source/drain formed therein. The thin-film Si layer is curved from a region directly below a gate electrode toward a region near the source/drain. The curved thin-film Si layer develops strains in a channel region disposed directly below the...

20060138542 - Semiconductor on insulator substrate and devices formed therefrom: A semiconductor on insulator (SOI) device is comprised of a layer of a dielectric material having a perovskite lattice, such as a rare earth scandate. The dielectric material is selected to have an effective lattice constant that enables growth of semiconductor material having a diamond lattice directly on the dielectric....

20060138540 - Semiconductor wafer having a semiconductor layer and an electrically insulating layer beneath it, and process for producing it: The invention relates to a semiconductor wafer, which, at its surface comprises a semiconductor surface layer with a thickness in the range from 3 nm to 200 nm having no hole defects, and which comprises an adjoining electrically insulating layer beneath the semiconductor surface layer....

20060138543 - Silicon-on-sapphire semiconductor device with shallow lightly-doped drain: A semiconductor device is created in a doped silicon layer at most one-tenth of a micrometer thick formed on and having an interface with a sapphire substrate. An oppositely doped source region is formed in the silicon layer. A gate electrode is formed above part of the silicon layer. A...

20060138544 - Esd protection structure for i/o pad subject to both positive and negative voltages: An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor...

20060138545 - Protective circuit for protecting chip from misoperation: A protective circuit for a chip includes an input terminal for receiving a power supply voltage, an output terminal for outputting a working voltage to the chip, a first BJT and a second BJT. A base of the first BJT is connected to the input terminal and an emitter of...

20060138546 - Voltage regulator: A voltage regulator having a MOS transistor driver is disclosed. The voltage regulator comprises a p-channel MOS transistor at a voltage input terminal Vin and a p-channel MOS transistor at a voltage output terminal Vout. A drain of the input side p-channel MOS transistor is connected to the voltage input...

20060138547 - Reduced finger end mosfet breakdown voltage (bv) for electrostatic discharge (esd) protection: The present invention relates to electro static discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other...

20060138549 - High-voltage transistor and fabricating method thereof: A high-voltage transistor having a low on-resistance and fabricating method thereof are provided. The high-voltage transistor includes a substrate; a shallow-trench isolation layer provided to an upper part of the substrate to a prescribed depth to define an active area; an extended drain region enclosing the shallow-trench isolation layer; a...

20060138548 - Strained silicon, gate engineered fermi-fets: A field effect transistor includes a strained silicon channel in a substrate, source/drain regions in the substrate at opposite ends of the strained silicon channel, a gate insulating layer on the strained silicon channel, and a gate on the gate insulating layer. The doping of the strained silicon channel, the...

20060138552 - Nonplanar transistors with metal gate electrodes: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of...

20060138553 - Nonplanar transistors with metal gate electrodes: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of...

20060138550 - Semiconductor device with multiple gate dielectric layers and method for fabricating the same: Disclosed are a semiconductor device with dual gate dielectric layers and a method for fabricating the same. The semiconductor device includes: a silicon substrate divided into a cell region where NMOS transistors are formed and a peripheral region where NMOS and PMOS transistors are formed; a targeted silicon oxide layer...

20060138551 - Semiconductor device, manufacturing method thereof, and cmos integrated circuit device: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the...

20060138554 - Semiconductor device and fabricating method for the same: The present invention is intended to provide a semiconductor device having a gate electrode free from increasing of resistance of the gate electrode, from decreasing of capacitance of the insulation film due to depletion, and from penetrating of impurity. The semiconductor device comprises a silicon layer, a gate insulating film...

20060138556 - Gate dielectric and method: A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation....

20060138557 - Novel cmos device: A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress...

20060138555 - Semiconductor device and method of fabricating the same: According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising: forming a gate insulating film on a semiconductor substrate; forming a film containing a predetermined semiconductor material and germanium on the gate insulating film; oxidizing the film to form a first film having a...

20060138558 - Semiconductor memory device and method of fabricating the same: A semiconductor memory device includes: a semiconductor device base having an insulating substrate and a semiconductor layer overlying it; a cell array formed on the semiconductor device base with memory cells disposed in such a manner that each of source and drain regions is shared by adjacent two memory cells...

20060138559 - Flash memories having at least one resistance pattern on gate pattern and methods of fabricating the same: Flash memories and methods of manufacturing the same provide at least one resistance pattern on a gate pattern, and are capable of increasing a process margin in the semiconductor fabrication process. Gate patterns and bit line patterns are sequentially formed in a cell array region and a peripheral circuit region...

20060138560 - Metal oxide semiconductor transistor and method for manufacturing the same: A metal oxide semiconductor (MOS) transistor includes a source region having at least one source contact; a drain region having at least one drain contact; and a gate provided between the source region and the drain region, wherein the number of source contacts included in the source region is different...

20060138561 - Semiconductor device having raised cell landing pad and method of fabricating the same: A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode,...

20060138562 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having...

20060138564 - Electrical node of transistor and method of forming the same: According to example embodiments of the present invention, there are provided an electrical node of a transistor and a method of forming the same, which may reduce or minimize current leakage between the electrical node and a semiconductor substrate when a buried contact hole exposing at least the side of...

20060138563 - Nand flash memory device: A memory device capable of enlarging an interval between a source selection transistor and a memory cell adjacent to the source selection transistor, enlarging an interval between a drain selection transistor and a memory cell adjacent to the drain selection transistor, or enlarging the intervals between the source selection transistor...

20060138565 - Power metal oxide semiconductor transistor layout with lower output resistance and high current limit: A power metal oxide semiconductor transistor layout is disclosed. The power metal oxide semiconductor transistor layout uses network of conductive lead line as a connection or a network connection to connect source and drain regions thereby achieves advantages of a high uniformity of current, low Rds_on, much less power loss,...

20060138566 - Doped nitride film, doped oxide film and other doped films: Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the...

20060138567 - Semiconductor device and fabricating method thereof: A semiconductor device and fabricating method thereof in which a lightly doped drain junction is graded using a diffusion property of dopant implanted in heavily doped source/drain region are disclosed. An example semiconductor device includes a gate electrode having a gate insulating layer underneath and disposed on a semiconductor substrate;...

20060138568 - Semiconductor integrated circuit device and a methodof manufacturing the same: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width...

20060138569 - Semiconductor device and manufacturing method thereof: A semiconductor device according to a exemplary embodiment of the present invention includes a reverse spacer exposing a part of an epitaxial silicon layer on a silicon substrate, a gate oxide layer on at least the epitaxial silicon layer and a gate polysilicon layer on the gate oxide layer and...

20060138571 - Method of forming double gate dielectric layers and semiconductor device having the same: A method of forming double gate dielectric layers composed of an underlying oxide layer and an overlying oxy-nitride layer is provided to prevent degradation of gate dielectric properties due to plasma-induced charges. In the method, the oxide layer is thermally grown on a silicon substrate under oxygen gas atmosphere to...

20060138570 - Semiconductor device and fabricating method thereof: A semiconductor device and semiconductor device fabricating method may enhance device reliability by forming a chemical oxide buffer layer prior to forming a high-k gate oxide layer. The semiconductor device includes a semiconductor substrate; a chemical oxide buffer layer on the semiconductor substrate; a high-k gate oxide layer on the...

20060138572 - Semiconductor device and method for manufacturing the same: A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity...

20060138573 - Bi-directional released-beam sensor: An acceleration sensor includes a semiconductor substrate, a first layer formed on the substrate, a first aperture within the first layer, and a beam coupled at a first end to the substrate and suspended above the first layer for a portion of the length thereof. The beam includes a first...

20060138574 - Capacitive sensor: A pressure-sensitive capacitive sensor is provided that can easily remove noises delivered from a human body. The capacitive sensor includes a sensor unit having a first substrate where a plurality of vertical wiring lines is formed and a second substrate where a plurality of horizontal wiring lines is formed, the...

20060138575 - Semiconductor nanowire fluid sensor and method for fabricating the same: Nanowire fluid sensors are provided. The fluid sensors comprise a first electrode, a second electrode, and at least one nanowire between the first electrode and the second electrode. Each nanowire is connected at a first end to the first electrode and at a second end to the second electrode. Methods...

20060138576 - Self-aligned conductive lines for fet-based magnetic random access memory devices and method of forming the same: A conductive line structure for a field effect transistor (FET) based magnetic random access memory (MRAM) device includes a lateral metal strap conductively coupled to a lower metallization line. A magnetic tunnel junction (MTJ) stack is formed on the metal strap, and a metal shield is formed over the MTJ...

20060138578 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same in which characteristics of the image sensor are not affected even if a profile of microlenses is varied, so as to obtain a more reliable device. The CMOS image sensor of the present invention includes color filter layers formed...

20060138577 - Photoelectric conversion device and method for producing photoelectric conversion device: A photoelectric conversion device according to the present invention has a plurality of photoreceiving portions provided in a substrate, an interlayer film overlying the photoreceiving portion, a large refraction index region which is provided so as to correspond to the photoreceiving portion and has a higher refractive index than the...

20060138579 - Image sensor package, solid state imaging device, and fabrication methods thereof: An image sensor package and a solid state imaging device. The image sensor package includes an image sensor having an image sensor and connection pads on a wafer. A transparent plate is attached to the upper surface of the image sensor chip via an adhesive. The connection pads include connectors,...

20060138580 - Photo-detecting device and related method of formation: A photo-detecting device includes a buried doping layer of a first conductivity type and disposed at an upper portion of a silicon substrate. A first silicon epitaxial layer of first conductivity type is disposed on the buried doping layer, and a second silicon epitaxial layer of second conductivity type is...

20060138581 - Split transfer gate for dark current suppression in an imager pixel: A pixel with a photosensor and a transfer transistor having a split transfer gate. A first section of the transfer gate is connectable to a first voltage source while a second section of the transfer gate is connectable to a second voltage source. Thus, during a charge integration period of...

20060138582 - Digital temperature sensing device using temperature depending characteristic of contact resistance: A digital temperature sensing device uses temperature depending characteristic of contact resistance of a MOS transistor and a self-refresh driving device adjusts its self-refresh period depending on temperature using the digital temperature sensing device. The self-refresh driving device includes a first reference voltage generating unit for generating a reference voltage...

20060138583 - Method and structure for implanting bonded substrates for electrical conductivity: A partially completed multi-layered substrate, e.g., silicon on silicon. The substrate has a thickness of material from a first substrate. The thickness of material comprises a first face region. The substrate has a second substrate having a second face region. Preferably, the first face region of the thickness of material...

20060138584 - Semiconductor device: A semiconductor device includes a substrate including a high-voltage transistor area provided with a high-voltage transistor and a low-voltage transistor area provided with a low-voltage transistor; a LOCOS layer provided as a device isolation layer of the high-voltage transistor area; and a shallow-trench isolation layer provided as a device isolation...

20060138586 - Dielectric isolation type semiconductor device and method for manufacturing the same: A dielectric isolation type semiconductor device and a manufacturing method therefor achieve high dielectric resistance while preventing the dielectric strength of the semiconductor device from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A semiconductor substrate (1) and an n−...

20060138585 - Semiconductor device and method for fabricating the same: A semiconductor device capable of preventing a bridge generation during performing an etching process to form a plurality of gate structures on a substrate divided into an active region and a field region and an electrical short between a contact plug and the individual gate structure in the field region...

20060138587 - Semiconductor device and manufacturing method thereof: An semiconductor device and a manufacturing method minimizes the inductor area in a high frequency device by forming an inductor with a vertical spiral geometry. Accordingly, the device can be highly integrated. In addition, the inductor area overlapped with various devices on a substrate can be minimized so as to...

20060138588 - Self-configuring component by means of arcing: A component with an internal conductor is so configured that it is ruptured at a predetermined position while forming an arc, if predetermined current/voltage conditions occur at the terminals of the component. The component includes a circuit element which is so arranged that an arc formed at the predetermined position...

20060138589 - Semiconductor device with a fuse part and method of manufacturing the same: The present invention provides a semiconductor device with a fuse part and a method of forming the same. The method includes forming a selective metal layer on a via hole which is connected to a metal line in a semiconductor device, forming a fuse metal layer on the selective metal...

20060138593 - Capacitor of semiconductor device and manufacturing method thereof: In a capacitor of a semiconductor device, a bottom electrode is formed on a substrate and has an uneven top surface. An interlayer insulation layer is formed on the substrate and has a via hole exposing the top surface of the bottom electrode. A dielectric layer is formed unevenly on...

20060138590 - Electronic parts and method for manufacture thereof: An electronic device having an element body comprising an internal electrode layer, wherein the internal electrode layer includes an alloy, the alloy contains a nickel (Ni) element and at least one kind of element selected from ruthenium (Ru), rhodium (Rh), rhenium (Re) and platinum (Pt), and a content of each...

20060138592 - Method of forming on-chip decoupling capacitor with bottom electrode layer having surface roughness: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the...

20060138594 - Method of improved high k dielectric - polysilicon interface for cmos devices: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide...

20060138591 - Power core devices and methods of making thereof: The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply...

20060138595 - Semiconductor device and method of manufacturing the same: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor structure formed above the semiconductor substrate and comprising a first electrode, a second electrode provided below the first electrode, a third electrode provided below the second electrode, a first dielectric film provided between the first electrode and the second...

20060138596 - Semiconductor structures utilizing thin film resistors and tungsten plug connectors and methods for making the same: Semiconductor structures and methods for fabricating semiconductor structures are provided. The method comprises forming a first insulating layer having a substantially planar surface overlying a first conductive layer of an interconnect stack. A thin film resistor is formed overlying the first insulating layer and a second insulating layer is deposited...

20060138597 - Combined high reliability contact metal/ ballast resistor/ bypass capacitor structure for power transistors: A structure with the combined benefits of a highly reliable ohmic contact, ballast resistor, and ballast resistor bypass capacitor is provided. The benefit of these three features is combined into a single metal-semiconductor contact offering a reduction in space utilization, and complexity normally present in ballast networks associated with power...

20060138598 - Localized slots for stress relieve in copper: In accordance with the objectives of the invention a new method is provided for the creation of interconnect metal. Current industry practice is to uniformly add slots to wide and long copper interconnect lines, this to achieve improved CMP results. These slots, typically having a width in excess of 3...

20060138599 - Semiconductor members having a halogenated polymeric coating and methods for their formation: A coated semiconductor member is provided having a carbon-containing halogenated polymeric coating bonded to a surface thereof. The semiconductor member may take any of a number of forms, such as the form of a chip or a wafer containing one or more microelectronic devices. The coating may be bonded to...

20060138600 - Unit circuit, method of controlling unit circuit, electronic device, and electronic apparatus: A unit circuit includes: a capacitive element having a first electrode, a second electrode, and a dielectric layer interposed between the first and second electrodes; a transistor having a gate electrode connected to the first electrode; a first switching element that controls an electrical connection between the first electrode and...

20060138601 - Internally gettered heteroepitaxial semiconductor wafers and methods of manufacturing such wafers: A heteroepitaxial semiconductor wafer includes a heteroepitaxial layer forming the front surface of the wafer that includes a secondary material having a different crystal structure than that of the wafer primary material. The heteroepitaxial layer is substantially free of defects. A surface layer includes the primary material and is free...

20060138603 - Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures: A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant...

20060138602 - Device manufacturing method, top coat material and substrate: m

20060138604 - Low charging dielectric for capacitive mems devices and method of making same: An improved dielectric suitable for use in electronic and micro-electromechanical (MEMS) components. The dielectric includes silicon nitride having a percentage of Si:H bonds greater than a percentage of N:H bonds, in order to reduce the level of charge trapping of the silicon nitride....

20060138605 - Method for attaching chips in a flip-chip arrangement: Targeted heating is employed to essentially only heat a material that is used as a spacer and to bond a first chip of a flip-chip to a second chip thereof and not the rest of the chips. In order to heat only the spacer-bonding material, one or more wires are...

20060138606 - Photovoltaic device forming a glazing: The invention concerns a photovoltaic device (1) comprising a plurality of p-i-n type photovoltaic cells (2) arranged on a substrate (3), wherein said cells (2) are arranged, in the form of a single layer, parallel to one another and the electrical conductive layer (7) is arranged between the n layer...

20060138607 - Power semiconductor rectifier having broad buffer structure and method of manufacturing thereof: Impurity concentration (Nd(X)) in an n-drift layer in a diode is at a maximum at a position at a distance Xp from an anode electrode in a direction from the anode electrode to a cathode electrode, and gradually decreases from the position toward each of the anode electrode and the...

20060138610 - Ball grid array ic substrate with over voltage protection function: The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install protection devices at respective...

20060138608 - Ic substrate with over voltage protection function: The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install protection devices at respective...

20060138609 - Ic substrate with over voltage protection function: The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install protection devices at respective...

20060138611 - Ic substrate with over voltage protection function: The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install protection devices at respective...

20060138612 - Ic substrate with over voltage protection function: The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install protection devices at respective...

20060138616 - Adhesive film for semiconductor, lead frame and semiconductor device using the same, and method of producing semiconductor device: An adhesive film for semiconductor, which comprises at least one resin layer, and, after bonded to a lead frame, has at 25° C. a 90°-peel strength of at least 5 N/m between the resin layer and the lead frame, and, after a lead frame is bonded to the adhesive film...

20060138613 - Integrated circuit package with inner ground layer: An integrated circuit package includes a lead frame having a plurality of leads and a metal layer; an integrated circuit die having a plurality of power-level bond pads; a plurality of first bond wires electrically connected between the power-level bond pads and the metal layer, respectively; and a second bond...

20060138614 - Semiconductor device and method of fabricating the same: A semiconductor device 100 comprises a leadframe 104 having an island portion 102; two chips of a first semiconductor chip 110 and a second semiconductor chip 120, respectively having top surfaces having, in the peripheral areas thereof, pad portions respectively having a plurality of first bonding pads 112 and second...

20060138617 - Semiconductor integrated circuit device and method of manufacturing the same: A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 μm, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected....

20060138615 - Semiconductor package and lead frame therefor: A lead frame adapted to a semiconductor package, which is enclosed in a molded resin body and is connected with a board, is formed by processing a thin metal plate so as to include a stage for mounting a semiconductor chip thereon, a plurality of leads arranged to encompass the...

20060138618 - Method for wafer stacking using copper structures of substantially uniform height: A method for wafer stacking employing substantially uniform copper structures is described herein....

20060138619 - Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication: A conductive plastic lead frame and method of manufacturing the same, suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a...

20060138620 - Resin-encapsulated package, lead member for the same and method of fabricating the lead member: A resin-encapsulated package includes a semiconductor IC chip, wherein the ratio of the size of the semiconductor IC chip to the package size of the resin-encapsulated package including the semiconductor IC chip is large to miniaturize the resin-encapsulated package. The resin-encapsulated package includes a semiconductor IC chip sealed in a...

20060138622 - One step capillary underfill integration for semiconductor packages: The present invention relates to a semiconductor package containing a package substrate, integrated heat spreader, and semiconductor die. An underfill material is embedded in the semiconductor package serving both as underfill and sealant....

20060138621 - Optoelectronic component and a module based thereon: An optoelectronic component (1) having a semiconductor arrangement (4) which emits and/or receives electromagnetic radiation and which is arranged on a carrier (22) which is thermally conductively connected to a heat sink (12). External electrical connections (9) are connected to the semiconductor arrangement (4), where the external electrical connections (9)...

20060138624 - Semiconductor device package: Provided is a semiconductor device package in which instability of a bonding wire that may occur when a plurality of semiconductor chips are stacked is prevented and which obtains a light, thin and small structure. The semiconductor device package includes a substrate having a plurality of substrate pads on a...

20060138623 - Stacked-type semiconductor device: A stacked-type semiconductor device including a plurality of semiconductor elements stacked through a spacer is disclosed. The electrical characteristics with the bonding wires are improved and a narrow pitch is secured. The stacked-type semiconductor device includes a lower semiconductor element (2) fixed on a wiring board (1), an insulating spacer...

20060138625 - Storage apparatus, card type storage apparatus, and electronic apparatus: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate...

20060138626 - Microelectronic packages using a ceramic substrate having a window and a conductive surface region: A microelectronic package includes a microelectronic device, a unitary ceramic substrate, and a plurality of terminals. The microelectronic device has a front surface and a plurality of electrical contacts thereon. The substrate has first and second opposing surfaces. A window extends from a first opening on the first surface along...

20060138629 - Method of manufacturing semiconductor device, semiconductor device, stacked semiconductor device, circuit board and electronic instrument: A method of manufacturing a semiconductor device includes: preparing a semiconductor wafer; forming a conductive portion by forming holes in an active surface, forming an insulating film, and embedding a conductive material; forming a first groove; bonding the semiconductor water and a support body via an adhesive layer; thinning the...

20060138627 - Methods of vertically stacking wafers using porous silicon: A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers...

20060138631 - Multi-chip package structure: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate....

20060138628 - Stack chip package: An improved stack chip package comprising a lead frame, chip, plural leads and coating, among which: the lead frame is made of metal materials through impact extrusion forming two or four lines of rectangular plural pins comprising three lead segments making the pin -shaped; So install a chip on the...

20060138630 - Stacked ball grid array packages: An arrangement of ball grid array packages includes a flexible circuit board having first and second opposed surfaces defining a central portion to which first and second side portions are flexibly attached. A first package has a first array of solder ball pins attached to the first surface of the...

20060138632 - Package for semiconductor components and method for producing the same: The invention relates to a packaging for semiconductor components such as FBGA packages in BOC technology or the like, wherein at least the back and the lateral edges of a chip (2) mounted on a substrate are enclosed by a mold coating (6), the casting compound used for the mold...

20060138633 - Semiconductor device: A semiconductor device includes first and second semiconductor chips formed with electrodes on front and reverse sides, a first bus bar on which the first semiconductor chip is mounted so as the reverse side electrode to be connected thereto, a second bus bar, arranged parallel with the first bus bar,...

20060138634 - Method for determining the arrangement of contact surfaces on the active upper face of a semiconductor chip: In the case of a method according to the invention for determining the arrangement of contact areas on the active top side of a semiconductor chip arranged in or on a housing, firstly semiconductor chip data, contact area data, housing data and production data are read in, from which a...

20060138635 - Power semiconductor device: The present invention is directed to a power semiconductor device in which a control circuit controls a power switching element, comprising: a semiconductor substrate having a front surface and a back surface; a capacitor disposed on the front surface side of the semiconductor substrate and being comprised of a stacked...

20060138636 - Device for electrical connection of an integrated circuit chip: A device is provided for electrically connecting an integrated circuit chip. The device includes a main board, an intermediate board, and electrical connection balls in a space separating the boards. In the space, a peripheral zone comprises a peripheral matrix of balls, a central zone comprises a central matrix of...

20060138637 - Connection terminal and connector equipped therewith: The card edge connector includes a housing and a card edge terminal. A plurality of through holes is formed on the housing. A cable is electrically connected to the card edge terminal. The card edge terminal to which the cable is attached by crimping is pressed and inserted into a...

20060138639 - Capacitor pad network to manage equivalent series resistance: According to some embodiments, an apparatus includes a first conductive pad, a first conductive plane, first dielectric material disposed between the first conductive plane and the first conductive pad, a second conductive plane, second dielectric material disposed between the first conductive plane and the second conductive plane, and a first...

20060138640 - Multi-sheet conductive substrates for microelectronic devices and methods for forming such substrates: A substrate is provided having a plurality of sheets. Each sheet has a first major surface containing a plurality of electrically conductive regions and a second major surface that opposes the first major surface. The sheets are arranged such that the first major surface of a sheet faces the second...

20060138641 - Semiconductor device connector, semiconductor device carrier, semiconductor device socket using the same and probe card: A semiconductor device carrier comprising; a carrier housing having a housing portion for accommodating a semiconductor device; an electrode sheet disposed in the carrier housing, having a front surface wiring conductively arranged on a front surface of an insulation substrate, a rear surface wiring conductively arranged on a rear surface...

20060138638 - Substrate for semiconductor devices and semiconductor device: The present invention provides to a substrate for a semiconductor device, in which electric characteristics to high-speed signals are enhanced by facilitating the mounting of a circuit component, such as a decoupling capacitor, fabricated separately from the substrate. The substrate (30) for a semiconductor device, on which the circuit component...

20060138642 - Micromechanical getter anchor: One embodiment provides an anchor to hold getter materials in place within a micromechanical device package substrate, said anchor comprising: a first cavity face; and a second cavity face. The cavity faces define an anchor cavity and mechanically retain a getter away from a region holding the micromechanical device. Another...

20060138643 - One step capillary underfill integration for semiconductor packages: The present invention relates to a semiconductor package containing a package substrate, integrated heat spreader, and semiconductor die. An underfill material is embedded in the semiconductor package serving both as underfill and sealant....

20060138644 - Thermal interface structure with integrated liquid cooling and methods: A method and device for thermal conduction is provided. A thermal interface device and method of formation is described that includes advantages such as improved interfacial strength, and improved interfacial contact. Embodiments of thermal conduction structures are shown that provide composite thermal conduction and circulated liquid cooling. Embodiments are further...

20060138645 - High power light emitting diode device: A circuit element having a heat-conducting body having top and bottom surfaces, and a die having an electronic circuit thereon is disclosed. The die includes first and second contact points for powering the electronic circuit. The die is in thermal contact with the heat-conducting body, the die having a bottom...

20060138646 - Low cost electromechanical devices manufactured from conductively doped resin-based materials: Electromechanical devices are formed of a conductively doped resin-based material. The conductively doped resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers in a base resin host. The percentage by weight of the conductive powder(s), conductive fiber(s), or a combination thereof is...

20060138647 - Microelectronic package having stacked semiconductor devices and a process for its fabrication: A packaged microelectronic device having a first and second electrically interconnected microelectronic elements and a method for its manufacture. Conductive posts extend from one major surface of the first microelectronic element. The first microelectronic element is electrically interconnected to the second microelectronic element via the conductive posts. The first microelectronic...

20060138649 - Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (bga) package: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, and in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball...

20060138648 - Semiconductor package module without a solder ball and method of manufacturing the semiconductor package module: A semiconductor package module having no solder balls and a method of manufacturing the semiconductor package module are provided. The semiconductor package module includes a module board on which a plurality of semiconductor devices are able to be mounted, a semiconductor package bonded on the module board using an adhesive,...

20060138650 - Integrated circuit packaging device and method for matching impedance: An integrated circuit device is provided. The integrated circuit includes an integrated circuit chip (110) having a chip input/output element (240); a packaging component (220) having a package input/output element (270); two or more connection elements (260) for connecting the chip input/output element with the package input/output element; and a...

20060138651 - Native incorporation of rf id technology for the tracking of electronic circuitry: RF ID transmitter circuits are integrated into semiconductor chips during fabrication of the regular integrated circuits therein for providing identification capabilities for the semiconductor chips that comply with the IEEE family of standards 802. The RF ID transmitter circuit enables each chip to be identified in many different environments and...

20060138653 - Rfic chip, and position recognition system and security system using the same: Included are: a circuit unit having a non-volatile memory; a circuit unit having a volatile memory; a read-write circuit for reading data from, writing data into, the non-volatile memory, and for reading data from, writing data into, the volatile memory; an antenna and an RF amplifier which are first power...

20060138654 - Semiconductor device: A semiconductor device including; a bottom plate having a laminated structure in which between a first and a second metal plates a third metal plate harder than these metal plates is clipped, a concave portion formed by removing a part of the first metal plate laminated on the surface of...

20060138655 - Semiconductor device: A semiconductor device includes, a metal base plate, a semiconductor element mounted on the base plate, first and second dielectric plates are mounted on the base plate in the vicinity of the semiconductor element. The first and second dielectric plates are composed of such an insulator material as diamond having...

20060138652 - Solder for device package: A solder for device packaging including a plurality of cores, and a coating solder mixed with the cores. The cores are formed of a material having a higher thermal conductivity than the coating solder....

20060138656 - Electrode for an electronic device: An embodiment of the present invention pertains to an electrode that includes a metal oxide layer, and a conductive layer on that metal oxide layer. The metal oxide layer is an alkali metal oxide or an alkaline earth metal oxide that is formed by: (1) decomposing a compound that includes...

20060138657 - Semiconductor device and fabrication method thereof: A semiconductor device has rewiring that is electrically connected to circuit elements on a semiconductor substrate, and a plurality of posts electrically connected to the rewiring. The semiconductor device also has a sealing layer that seals the rewiring and the posts. A column-like identification protrusion whose cross-sectional shape is the...

20060138658 - Carbon nanotube interconnects in porous diamond interlayer dielectrics: A method and structure for using porous diamond interlayer dielectrics (ILDs) in conjunction with carbon nanotube interconnects is herein described. A diamond ILD is deposited on an underlaying layer. The diamond layer is optionally and selectively removed of non-sp3 bond to create a porous diamond film. Trenches and vias are...

20060138661 - Agglomeration control using early transition metal alloys: Structures and methods of fabricating portions of integrated circuit devices to reduce agglomeration tendencies of high surface-energy metals used in interconnects and contacts. Early transition metals having relatively low surface energies are chosen to form stable crystalline compounds rich in the high surface-energy metal. Agglomeration control layers containing such alloy...

20060138659 - Copper gate electrode of liquid crystal display device and method of fabricating the same: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy...

20060138660 - Copper interconnect: An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad...

20060138662 - Method of forming a bonding pad structure: A semiconductor device having a semiconductor substrate and a bonding pad portion formed on the semiconductor substrate, the bonding pad portion having: an insulating film formed on the semiconductor substrate and a first-level conductive pad layer of a large island shape formed on the insulating film; first-level to (n−1)-level (n...

20060138663 - Method of forming air gaps in a dielectric material using a sacrificial film and resulting structures: A method of forming air gaps surrounding conductors in a dielectric layer, the dielectric layer comprising, for example, part of the interconnect structure of an integrated circuit device. The air gaps are formed, in part, by depositing a sacrificial material within a trench and/or via that have been formed in...

20060138664 - Electron source device and display: An electron source device includes a porous layer (for example, porous alumina layer) which is composed of an insulator and has many microscopic holes provided in a direction perpendicular to a main surface, and first and second conductor layers placed on both sides of the porous layer, and is characterized...

20060138665 - Mechanically robust dielectric film and stack: A method for forming a mechanically robust dielectric film comprises depositing a dielectric film on a substrate and then inducing a compressive strain in a top surface of the dielectric film to form a compressive strained surface. The compressive strain may be induced using an ion implantation process that bombards...

20060138667 - Method for forming an intermetal dielectric layer in a semiconductor device using hdp-cvd, and a semiconductor device manufactured thereby: A method for forming an intermetal dielectric layer in a semiconductor device using high density plasma chemical vapor deposition (HDP-CVD), and a semiconductor device manufactured thereby. The method includes the steps of: (a) forming a metal wiring including at least one via-hole by patterning a metal layer formed on a...

20060138666 - Method for forming an intermetal dielectric layer using low-k dielectric material and a semiconductor device manufactured thereby: Disclosed are: (i) a method for forming an intermetal dielectric layer between metal wirings using a low-k dielectric material, and (ii) a semiconductor device with an intermetal dielectric layer comprising a low-k dielectric material. The method comprises the steps of: (a) forming a metal layer on a semiconductor substrate; (b)...

20060138670 - Method of forming copper line in semiconductor device: A method of forming a copper line in a semiconductor device may enhance reliability of the copper line. The method includes the steps of forming a trench in a substrate; forming a copper layer filling the trench; planarizing the copper layer with respect to the trench; annealing the planarized copper...

20060138668 - Passivation structure for semiconductor devices: A system and method for providing a passivation structure for semiconductor devices is provided. In an embodiment, the passivation structure comprises a first barrier layer and a second barrier layer, wherein the second barrier layer may comprise a material, such as cobalt and/or nickel, that is less pure than the...

20060138669 - Semiconductor devices and methods for manufacturing the same: Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact hole, a barrier metal layer including a first ruthenium layer, a ruthenium oxide layer and a second ruthenium layer, a seed copper layer...

20060138671 - Semiconductor device and fabrication method thereof: A semiconductor device includes a semiconductor substrate with circuit elements and electrode pads formed on one surface. This surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is deposited on the dielectric layer and patterned to form a conductive pattern with traces leading...

20060138672 - Electronic device and method of fabricating the same: An electronic device includes a package substrate made of an insulator, a device chip that is flip-chip mounted on the package substrate, and a seal portion sealing the device chip. The seal portion includes sidewalls made of solder. The whole seal portion including the sidewalls may be made of solder....

20060138674 - Method for fabricating thermally enhanced semiconductor package: A thermally enhanced semiconductor package and a fabrication method thereof are provided. A plurality of conductive bumps are formed on bond pads on an active surface of a chip. A heat sink is attached to an inactive surface of the chip and has a surface area larger than that of...

20060138673 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method manufacturing the same prevents copper from being exposed to a surface of a passivation film after a copper metal line formation, to avoid contamination of processing equipment and the process environment. The method includes providing a substrate with a scribe lane and a chip...

20060138675 - Solder structures for out of plane connections: Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the...

20060138676 - Fine terminal, its manufacturing method, and contact sheet: A micro terminal for inspection or installation with high connection reliability is provided at lower cost. A micro terminal according to the present invention has electrical conduction between the micro terminal and an electrode of an electronic device or an inspection device and includes a columnar contactor in contact with...

20060138677 - Layered microelectronic contact and method for fabricating same: A microelectronic spring contact for making electrical contact between a device and a mating substrate and method of making the same are disclosed. The spring contact has a compliant pad adhered to a substrate of the device and spaced apart from a terminal of the device. The compliant pad has...

20060138678 - Chip support of a leadframe for an integrated circuit package: The central region of a leadframe (101, 201, 301, 401, 501, 601, 701, 801, 901, 1001, 1101, 1201), is selectively etched to leave upright portions (104, 204, 304, 404, 504, 604, 704, 804, 904, 1004, 1104, 1204). Subsequently, during the packaging process, an integrated circuit (3) is located on the...

20060138679 - Semiconductor device having improved adhesion between bonding and ball portions of electrical connectors: A semiconductor device with improved the adhesion between bonding pads and ball portions of gold wires is provided to improve the reliability of a semiconductor device. About 1 wt. % of Pd is contained in gold wires for connection between electrode pads formed on a wiring substrate and electrode pads...

20060138680 - System for controlling semiconductor packaging particulate contamination: The present invention provides a system for controlling semiconductor packaging particulate contamination. According to the present invention, a semiconductor packaging component (102) is provided, having a first surface (104) along which a plurality of connection features (110, 112) are disposed or located, and an area (202) to which a semiconductor...

20060138681 - Substrate and lithography process using the same: Provided are substrates, e.g. semiconductor wafers, whereby the front side of the substrate and the back side of the substrate differ in surface roughness. Also provided are lithography processes using the substrates....

20060138682 - Substrate provided with an alignment mark in a substantially transmissive process layer, mask for exposing said mark, device manufacturing method, and device manufactured thereby: A substrate provided with an alignment mark in a substantially transmissive process layer overlying the substrate, said mark comprising high reflectance areas for reflecting radiation of an alignment beam of radiation, and low reflectance areas for reflecting less radiation of the alignment beam, wherein the high reflectance areas comprise at...

20060138683 - Fabrication method of light emitting diodes: The present invention discloses a fabrication method of light emitting diodes, which comprises the following steps: firstly, providing three sapphire wafers with each sapphire wafer having a substrate and an epitaxial layer; turning the sapphire wafers upside down and sticking an adhesive tape onto each epitaxial layer; attaching three sapphire...

20060131553 - Silicon semiconductor substrate and its manufacturing method: The present invention has been made in order to manufacture a silicon semiconductor substrate used for a semiconductor integrated circuit device, higher in carrier mobility, especially in electron mobility, which is a carrier of an n-type FET, on a {100} plane as a main surface, and provides a silicon semiconductor...

20060131554 - Nonvolatile memory device having two or more resistance elements and methods of forming and using the same: A nonvolatile memory device having two or more resistors and methods of forming and using the same. A nonvolatile memory device having two resistance layers, and more particularly, to a nonvolatile memory device formed and operated using a resistance layer having memory switching characteristics and a resistance layer having threshold...

20060131555 - Resistance variable devices with controllable channels: A memory element having a first electrode is provided, wherein the first electrode comprises at least one conductive nanostructure. The memory element further includes a second electrode and a resistance variable material layer between the first and second electrodes. The first electrode electrically is coupled to the resistance variable material....

20060131556 - Small electrode for resistance variable devices: A memory element comprising first and second electrodes is provided. The first electrode is tapered such that a first end of the first electrode is larger than a second end of the first electrode. A resistance variable material layer is located between the first and second electrodes, and the second...

20060131557 - Optical semiconductor device and method for fabricating the same: An optical semiconductor device includes an active layer having a quantum well structure including alternately stacked well layers and barrier layers with a larger band gap than the well layers. The band gap of each of the well layers and the barrier layers is constant, each well layer is uniformly...

20060131558 - Gallium-nitride-based light-emitting apparatus: A light-emitting apparatus employing a GaN-based semiconductor. The light-emitting apparatus comprises an n-type clad layer (124); an active layer (129) including an n-type first barrier layer (126), well layers (128), and second barrier layers (130); a p-type block layer (132); and a p-type clad layer (134). By setting the band...

20060131559 - Method of manufacturing a semiconductor device with a silicon-germanium gate electrode: A SiO2 film serving as a gate dielectric film is formed on a silicon substrate. A seed Si film is formed on the gate dielectric film. A thin SiGe film of a thickness of 50 nm or less is formed on the seed Si film at a temperature between 450°...

20060131568 - Device having an organic transistor integrated with an organic light-emitting diode's heterojunctions: A device having an organic transistor device integrated with an organic light-emitting diode's heterojunctions. This device at least comprises: a transparent substrate, an organic transistor and an organic light-emitting diode. The organic transistor at least includes an organic semiconductor layer, one of the organic semiconductor layers serves as the organic...

20060131564 - Fluorine-containing n,n'-diaryl perylene-based tetracarboxylic diimide compounds as n-type semiconductor materials for thin film transistors: A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide 3,4,9,10-perylene-based compound having, attached to each of the imide nitrogen atoms a carbocyclic or heterocyclic aromatic ring system substituted with one or more fluorine-containing groups. Such transistors can further comprise spaced apart first and second...

20060131572 - Light-emissive device and method of manufacture: A light-emissive device is prepared by depositing a polymer layer on a substrate. The deposition process utilizes a formulation comprising a conjugated polymer dissolved in a solvent, the solvent including a trialkyl-substituted aromatic hydrocarbon wherein at least two of the alkyl substituents are ortho to one another. The deposition of...

20060131566 - Organic electronic devices having two dimensional series interconnections: A device includes a plurality of organic electronic devices disposed on a substrate, wherein each of the plurality of organic electronic devices comprises a first electrode and a second electrode, and wherein each of the plurality of organic electronic devices is electrically coupled in series. Further, the device includes an...

20060131562 - Organic light-emitting device with improved layer structure: An organic light emitting device having a cathode, an anode and an organic layer structure disposed between the cathode and the anode, the organic layer structure comprising a hole injection layer doped with a p-type dopant, a hole transport layer, an emissive layer and an electron transport layer doped with...

20060131569 - Organic memory device and method of manufacturing the same: An organic memory device and a method of manufacturing the same are disclosed. The organic memory device includes an electron channel layer including an organic layer, in which nano particles of a uniform size are dispersed, interposed between metal electrodes, thus having electrical bistability. The organic memory device uses a...

20060131573 - Organic semiconductor device and process of manufacturing the same: The present invention is for providing a sophisticated active matrix type organic semiconductor device. A first electrode 102 is formed on an insulated surface. A second insulated film 104 is formed on the first electrode 102 via a first insulated film 103. An organic semiconductor film is formed on an...

20060131561 - Organic thin-film transistor and method for manufacturing same: It is an object of the present invention to provide an organic thin-film transistor exhibiting high carrier mobility and a manufacturing method thereof. Disclosed is an organic thin-film transistor prossessing a film having a contact angle against pure water of a surface of not less than 50°, wherein an organic...

20060131563 - Phase-separated composite films and methods of preparing the same: Composite films formed from blends of semiconducting and insulating materials that phase separate on patterned substrates are provided. Phase separation provides isolated and encapsulated areas of semiconductor on the substrate. Processes for preparing and using such composite films are also provided, along with devices including such composite films....

20060131560 - Rewritable nano-surface organic electrical bistable devices: A bistable electrical device that is convertible between a low resistance state and a high resistance state. The device includes at least one layer of organic low conductivity material that is sandwiched between two electrodes. A buffer layer is located between the organic layer and at least one of the...

20060131570 - Substituted anthracenes and electronic devices containing the substituted anthracenes: Substituted anthracene compounds and electronic devices containing the substituted anthracene compounds are provided....

20060131567 - Surface modified electrodes and devices using reduced organic materials: An electrooptic device and a surface modified electrode comprising a reduced organic material are provided. The reduced organic materials lower the work function of an electrode surface; they are also electro-active. These capabilities facilitate their use in production of more efficient electrooptic devices. The electrooptic device has at least a...

20060131565 - Surface modified electrodes for electrooptic devices: A surface modified electrode comprising at least one conductive layer, and at least one reduced polymeric material, wherein the reduced polymeric material comprises at least one additional electron relative to a corresponding neutral polymeric precursor; and at least one cationic species is provided. Coating compositions and coated articles comprising the...

20060131571 - Switchable circuit assemblies and semiconductor constructions: The invention includes a switchable circuit device. The device comprises a first conductive layer and a porous silicon matrix over the first conductive layer. A material is dispersed within pores of the porous silicon matrix, and the material has two stable states. A second conductive layer is formed over the...

20060131575 - Electronic device and manufacturing method thereof: An electronic device includes an element group which generates a specific identification number and is composed of a plurality of elements. The specific identification number is set based on irregular deviation in electric characteristic of the elements which is caused due to a random failure in a manufacturing process....

20060131577 - Isolation circuit: An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in...

20060131574 - Nanowire sensor and method of manufacturing the same: Provided are a nanowire sensor and a method of manufacturing the same. The nanowire sensor includes: a sensing target system comprising a target element to be detected; two electrodes separated from each other contained in the sensing target system; vanadium oxide (V2O5) nanowires incorporated in the sensing target system and...

20060131576 - Semiconductor device having overlay measurement mark and method of fabricating the same: There are provided a semiconductor device having an overlay measurement mark, and a method of fabricating the same. The semiconductor device includes a scribe line region disposed on a semiconductor substrate. A first main scale layer having a first group of line and space patterns and a second group of...

20060131578 - Structure of semiconductor substrate including test element group wiring: A structure of test element group wiring includes, in addition to an electrode on a substrate including one or more layers of insulating films, and real wirings electrically connected to the electrode, includes dummy wirings electrically isolated from the electrode and having a portion of the same shape as the...

20060131579 - Semiconductor photodetector, device for multispectrum detection of electromagnetic radiation using such a photodetector and method for using such a device: This semiconductor photodetector consists of a diode with at least two heterojunctions comprising two external layers, a first layer with a given kind or type of doping and a second layer with a kind or type of doping opposite to that of the first layer, the bandgap width of these...

20060131583 - Method for manufacturing a semiconductor device: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film....

20060131580 - Thin film transistor array panel and liquid crystal display: A thin film transistor array panel is provided, which includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer covering the gate line, a data line formed on the gate insulating layer, a lower passivation layer covering the data line, an upper passivation layer...

20060131582 - Thin film transistor array panel and manufacturing method thereof: A thin film transistor (TFT) array panel is presented. The TFT array panel includes: a gate line formed on an insulating substrate and a gate electrode; a storage electrode line on the insulating substrate; a gate insulating layer on the gate line and the storage electrode line; a first semiconductor...

20060131581 - Thin film transistor array panel and method for manufacturing the same: A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and...

20060131584 - Process to improve transistor drive current through the use of strain: The present invention provides, in one embodiment, a P-type Metal Oxide Semiconductor (PMOS) device (100). The device (100) comprises a tensile-strained silicon layer (105) located on a silicon-germanium substrate (110) and silicon-germanium source/drain structures (135, 140) located on or in the tensile-strained silicon layer (105). The PMOS device (100) further...

20060131585 - Thin film transistor array panel: A thin film transistor array panel is provided, which includes a substrate; a plurality of semiconductor islands formed on the substrate, the plurality of semiconductor islands including a plurality of first and second extrinsic regions, and a plurality of intrinsic regions; a gate insulating layer covering the semiconductor islands; a...

20060131587 - Method of manufacturing an active matrix substrate and an image display device using the same: The present invention provides a manufacturing method of a high performance active matrix substrate at a high throughput with a less expensive apparatus, and an image display device using the active matrix substrate. On a stage moving in the short axis direction X and long axis direction Y on a...

20060131586 - Organic thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, the method includes: a substrate; a data line disposed on the substrate; an interlayer insulating layer disposed on the data line; a gate line disposed on the interlayer insulating layer and including a gate electrode; a gate insulating...

20060131589 - Boron carbide particle detectors: Boron carbide heteroisomer semiconductor devices are used as particle detectors. The boron carbide semiconductor devices produce electric current in response to incident particles, such as alpha particles, neutrons, or photons....

20060131588 - Electrode and electron emission applications for n-type doped nanocrystalline materials: An electrode having a surface of an electrically conducting ultrananocrystalline diamond having not less than 1019 atoms/cm3 nitrogen with an electrical conductivity at ambient temperature of not less than about 0.1 (Ω·cm)−1 is disclosed as is a method of remediating toxic materials with the electrode. An electron emission device incorporating...

20060131591 - Light emitting apparatus: A first GaN group light emitting element that emits blue light, a second GaN group light emitting element that emits green light, and a third light emitting element that emits red light are provided on a first lead terminal, a second lead terminal, and a third lead terminal, respectively. These...

20060131590 - Nitride semiconductor light-emitting device and method for producing same: In a method for producing a nitride semiconductor light-emitting device according to the present invention, first, a nitride semiconductor substrate having groove portions formed is prepared. An underlying layer comprising nitride semiconductor is formed on the nitride semiconductor substrate including the side walls of the groove portions, in such a...

20060131592 - Image sensor pixel having a transfer gate formed from p+ or n+ doped polysilicon: An active pixel using a transfer gate that has a polysilicon gate doped with P+ is disclosed. The pixel includes a photosensitive element formed in a semiconductor substrate and an n-type floating node formed in the semiconductor substrate. An n-channel transfer transistor having a transfer gate is formed between the...

20060131593 - Semiconductor laser, manufacturing the same and semiconductor laser device: A semiconductor laser element capable of reducing the contact resistance and the thermal resistance and realizing a high reliability is provided. The semiconductor laser element includes: a semiconductor substrate, an active layer formed on the semiconductor substrate, a ridge having a clad layer formed on the active layer and a...

20060131594 - Led illumination light source: According to the present invention, a substrate 11, a cluster of LED chips, which are arranged two-dimensionally on the substrate 11, and a plurality of phosphor resin portions 13a, 13b that cover the respective LED chips are provided. The phosphor resin portion 13a, 13b includes a phosphor for transforming the...

20060131595 - Light emitting device and the use thereof: A light emitting device includes a die and a photostimulable luminescent substance. The die has a first semiconductor light-emitting layer emitting a first color light having a first wavelength range, and a second semiconductor light-emitting layer emitting a second color light having a second wavelength range different from the first...

20060131598 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same with improved light-receiving efficiency of the active device, e.g., a photodiode. The CMOS image sensor includes at least one photodiode positioned on a semiconductor substrate; and a microlens disposed above each photodiode, wherein the microlens is formed of a...

20060131596 - Illumination assembly and method of making same: An illumination assembly including a thermally conductive substrate, a reflective layer proximate a first major surface of the thermally conductive substrate, a patterned conductive layer positioned between the reflective layer and the first major surface of the thermally conductive substrate and electrically isolated from the thermally conductive substrate, and at...

20060131599 - Light emitting diodes including pedestals: Light emitting diodes include a substrate having first and second opposing faces and that is transparent to optical radiation in a predetermined wavelength range and that is patterned to define, in cross-section, a plurality of pedestals that extend into the substrate from the first face towards the second face. A...

20060131597 - Light-emitting diode and method for manufacturing the same: A light-emitting diode (LED) and a method for manufacturing the same are described. The light-emitting diode has a metal substrate, a first transparent conductive layer, a first contact layer, and an illuminating epitaxial structure stacked in sequence. An ohmic contact layer is located on a portion of the illuminating epitaxial...

20060131601 - Illumination assembly and method of making same: An illumination assembly including a thermally conductive substrate, a patterned conductive layer proximate a major surface of the thermally conductive substrate, a dielectric layer positioned between the patterned conductive layer and the major surface of the substrate, and at least one LED including a post that is attached to the...

20060131600 - Light transmitting window member, semiconductor package provided with light transmitting window member and method for manufacturing light transmitting window member: A light transmission window member capable of simplifying the structure and capable of simplifying manufacturing steps is obtained. This light transmission window member (10, 10a), which is a light transmission window member employed for a semiconductor package (30, 30a), comprises a flat metal frame (2) having an opening (2a) for...

20060131602 - Illumination assembly and method of making same: An illumination assembly including a thermally conductive substrate, a patterned conductive layer proximate a major surface of the thermally conductive substrate, a dielectric layer positioned between the patterned conductive layer and the major surface of the substrate, and at least one LED including a post that is attached to the...

20060131604 - Nitride semiconductor device: In the nitride semiconductor device of the present invention, an active layer 12 is sandwiched between a p-type nitride semiconductor layer 11 and an n-type nitride semiconductor layer 13. The active layer 12 has, at least, a barrier layer 2a having an n-type impurity; a well layer 1a made of...

20060131603 - Semiconductor laser diode: A semiconductor laser diode is provided. The semiconductor laser diode includes a substrate; a lower clad layer on a substrate; an active layer on the lower clad layer; and an upper clad layer on the active layer and having a ridge that protrudes in a vertical direction. In the upper...

20060131605 - Low capacitance two-terminal barrier controlled tvs diodes: A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the...

20060131606 - Lattice-mismatched semiconductor structures employing seed layers and related fabrication methods: Fabrication of monolithic semiconductor heterostructures and semiconductor devices based thereon employs isolated seed regions for facilitating elastic lattice conformation between the lattice-mismatched materials. Relative thicknesses of the materials are selected to introduce desirable strain distribution within the heterostructure for improved functionality and performance....

20060131607 - Compound semiconductor device and process for producing the same: A compound semiconductor device comprising a hetero junction bipolar transistor including a compound semiconductor substrate, and a sub-collector layer, a collector layer, a base layer and an emitter layer formed in this order as thin crystalline layers on the compound semiconductor substrate by vapor phase deposition, wherein the base layer...

20060131608 - Semiconductor device: Disclosed is a semiconductor device including an n+-type semiconductor layer formed on a substrate, a first n-type semiconductor layer formed on the n+-type semiconductor layer, a p-type semiconductor layer formed on the first n-type semiconductor layer and having a material having a first band gap, a second n-type semiconductor layer...

20060131609 - Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential: A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a filler cell is...

20060131610 - Electronic device and method for designing the same: The electronic device comprises a plurality of layout regions each including a plurality of patterns defined by a buried structure buried in a substrate. For each of the layout regions, in each of the layout regions, the minimum space between the patterns, and a maximum area percentage allowed for the...

20060131611 - Multi-layer printed circuit board comprising a through connection for high frequency applications: A high frequency multi-layer printed circuit board, according to the present invention, comprises a through connection having an impedance adapting structure surrounding the through connection and enabling an adjustment of the characteristic impedance of the through connection to a desired value. Thus, high frequency signals may be led through the...

20060131612 - Semiconductor device: A mesh source wiring composed of first source wirings, second source wirings, and contacts for mesh source wiring is connected, through contacts for strap source wiring, with strap source wirings formed on a wiring layer nearer a substrate than wiring layers where the mesh source wiring is formed. The cell...

20060131613 - Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines: A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the...

20060131614 - Memory cell structure: A memory structure that reduces soft-errors for us in CMOS devices is provided. The memory cell layout utilizes transistors oriented such that the source-to-drain axis is parallel a shorted side of the memory cell. The dimensions of the memory cell are such that it has a longer side and a...

20060131615 - Structures and methods for enhancing capacitors in integrated circuits: Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The...

20060131616 - Copperless flexible circuit: This invention relates to a copperless flexible circuit; more particularly, a two-sided copperless flexible circuit....

20060131617 - Frequency conversion circuit for direct conversion receiving, semiconductor integrated circuit therefor, and direct conversion receiver: A rectangular parallelepiped p-channel MOS transistor 21 having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the p-channel MOS transistor 21. A source and...

20060131618 - Chalcogenide random access memory and method of fabricating the same: A chalcogenide random access memory (CRAM) is provided. The CRAM includes a substrate, a first dielectric layer, a bottom electrode, a top electrode, a second dielectric layer, a modified chalcogenide spacer and an un-modified chalcogenide thin film. The first dielectric layer is disposed on the substrate and the bottom electrode...

20060131619 - Self-aligned schottky-barrier clamped planar dmos transistor structure and its manufacturing methods: The self-aligned Schottky-barrier clamped planar DMOS transistor structure comprises a self-aligned source region being surrounded by a planar gate region. The self-aligned source region comprises a moderately-doped p-base diffusion ring being formed in a lightly-doped N− epitaxial semiconductor layer, a heavily-doped n+ source diffusion ring being formed within the moderately-doped...

20060131620 - Monolithic microwave integrated circuit compatible fet structure: A field effect transistor structure includes a single crystal substrate having: a source, gate and drain electrodes disposed on an upper surface of the substrate, the gate electrode having a region thereof disposed between a region of the drain electrode and a region of the source electrode; a ground conductor...

20060131621 - Device using ambipolar transport in sb-mosfet and method for operating the same: A device using an ambipolar transport of an SB-MOSFET and a method for operating the same are provided. The SB-MOSFET includes: a silicon channel region; a source and a drain contacted on both sides of the channel region and formed of material including metal layer; and a gate formed on...

20060131622 - Semiconductor device having a silicon layer in a gate electrode: A CMOS device includes a silicon substrate, a gate insulating film, and a gate electrode including a silicon layer doped with boron and phosphorous, a tungsten nitride layer and a tungsten layer. A ratio of a maximum boron concentration to a minimum boron concentration in a boron concentration profile across...

20060131623 - Semiconductor device: A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring...

20060131625 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same in which color balance is enhanced by forming photodiodes to have a depth varied according to the wavelength of incident light to be received through a color filter layer. The predetermined depth varies, from shallow to deep, as the...

20060131624 - Solid-state imaging device: Capacitance between a detection capacitor and a reset transistor is the largest among the capacitances between the detection capacitor and transistors placed around the detection capacitor. In order to reduce this capacitance, it is effective to reduce the channel width of the reset transistor. It is possible to reduce the...

20060131626 - Semiconductor device: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element...

20060131627 - Ferroelectric material, its manufacture method and ferroelectric memory: BiFeO3 precursor solution is coated on the surface of an underlying member. Teat treatment is performed after the coating to form a dielectric film. The dielectric film is heated in a non-oxidizing atmosphere to crystallize the dielectric film. With this method, a ferroelectric material can be obtained which contains constituent...

20060131629 - Magnetic random access memory having magnetoresistive element with nonmagnetic metal layer: A magnetic random access memory in which a plurality of magnetoresistive elements are laid out in an array, the magnetoresistive element includes a lower ferromagnetic layer, an upper ferromagnetic layer which has a planar shape smaller than a planar shape of the lower ferromagnetic layer, a first nonmagnetic insulating layer...

20060131628 - Nonvolatile memory and fabrication method thereof: A nonvolatile memory and a fabrication method thereof. The nonvolatile memory includes a substrate, a bottom electrode deposited on the substrate, a resistor layer deposited on the bottom electrode, and a top electrode on the resistor layer. The bottom electrode includes LaNiO3 and the resistor layer includes doped SrZrO3....

20060131630 - Method for forming storage node of capacitor in semiconductor device: A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact...

20060131631 - Non-volatile transistor memory array incorporating read-only elements with single mask set: A memory array has memory elements of identical topology or footprint arranged in rows and columns. Some of the memory elements are EEPROM cells and other memory elements are read only memory cells but all are made using a mask set having the same length and width dimensions. In the...

20060131632 - Dram device having capacitor and method thereof: In a DRAM device having a capacitor and a method thereof, the capacitor included in the device is characterized to have a lower electrode that passes through a plurality of interlayer insulating layers. A first interlayer insulating layer is formed on a semiconductor substrate. A first contact plug layer is...

20060131633 - Integrated two device non-volatile memory: The non-volatile memory cell is comprised of the series integration of a fixed threshold element and a bistable element. The fixed threshold element is formed over a substrate with a gate insulator layer and an access gate having a nitride layer. The bistable element is formed adjacent to the fixed...

20060131635 - Flash memory device and manufacturing method thereof: A method of manufacturing a flash memory device is provided. Multiple stack structures each comprising a tunneling oxide layer and a first conductive layer are formed over a substrate. Thereafter, multiple embedded doping regions is formed in the substrate between the stack structures. A dielectric layer is formed over the...

20060131636 - Non-volatile memory device having improved erase efficiency and method of manufacturing the same: A non-volatile memory device having an improved erase efficiency and a method of manufacturing the same are provided. The method includes: forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate on a semiconductor substrate; and performing a post treatment...

20060131634 - Non-volatile memory, non-volatile memory cell and operation thereof: A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed...

20060131637 - Bit line structure and production method thereof: The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive...

20060131640 - Memory array of non-volatile electrically alterable memory cells for storing multiple data: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well....

20060131638 - Nonvolatile semiconductor memory and a fabrication method thereof: A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction...

20060131639 - Scalable flash eeprom memory cell with notched floating gate and graded source region: An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a...

20060131641 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on...

20060131642 - Semiconductor storage: In a semiconductor storage device, a gate insulating film (12) and a gate electrode (13) are laid on a first conductivity type semiconductor substrate (11), and charge holding portions (10A, 10B) are formed on both sides of the gate electrode (13). Second conductivity type first and second diffusion layer regions...

20060131643 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gate insulation layer is disposed on the silicon substrate in...

20060131644 - Power semiconductor device: A power semiconductor device includes second semiconductor layers of a first conductivity type and third semiconductor layers of a second conductivity type alternately disposed on a first semiconductor layer of the first conductivity type. The device further includes fourth semiconductor layers of the second conductivity type disposed in contact with...

20060131645 - Semiconductor device and manufacturing method thereof: In the present invention, an npn junction or a pin junction is formed in an element peripheral part surrounding an element part. In addition, the same potential as that of a source electrode in the element part is applied, and a breakdown voltage of the element peripheral part is set...

20060131647 - Connection, configuration, and production of a buried semiconductor layer: In one embodiment, a power transistor has a semiconductor volume including a plurality of transistor cells connected in parallel, a laterally oriented, highly conductive semiconductor layer buried below the transistor cells in the semiconductor volume, and at least one connection, via which the buried semiconductor layer can be contact-connected from...

20060131646 - Scalable planar dmos transistor structure and its fabricating methods: The scalable planar DMOS transistor structure of the present invention comprises a scalable source region surrounded by a planar gate region. The scalable source region comprises a p-base diffusion region being formed in a n− epitaxial semiconductor layer through a ring-shaped implantation window, a n+ source diffusion ring being formed...

20060131650 - Bipolar reading technique for a memory cell having an electrically floating body transistor: A technique of sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, the present inventions are directed to a...

20060131651 - Semiconductor substrate and its fabrication method: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate....

20060131649 - Semiconductor wafer with an epitaxially deposited layer, and process for producing the semiconductor wafer: A semiconductor wafer is formed of a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type, with a front surface and a back surface, contains a layer deposited epitaxially on the front surface of the substrate wafer. The substrate wafer additionally includes...

20060131648 - Ultra thin film soi mosfet having recessed source/drain structure and method of fabricating the same: There are provided an ultra thin film silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) having a recessed source/drain structure, and a method of fabricating the same. The ultra thin film SOI MOS transistor includes a semiconductor substrate; a buried insulating layer disposed on the semiconductor substrate,...

20060131653 - Cmos thin film transistor comprising common gate, logic device comprising the cmos thin film transistor, and method of manufacturing the cmos thin film transistor: A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film transistor includes a base substrate and a semiconductor layer...

20060131652 - Transistor device and method of manufacture thereof: A method of forming transistors and structures thereof. A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n type dopant. The NMOS device may be doped with either an n type or a p type dopant. The work function...

20060131654 - Diode with reduced forward-bias resistance and shunt capacitance: A diode having reduced forward-bias resistance and shunt capacitance. The diode includes a lightly doped region of a semiconductor substrate, a carrier injection region and an ohmic contact region. The carrier injection region is disposed within the lightly doped region and has a plurality of sides of substantially uniform length....

20060131656 - Cmos semiconductor devices having elevated source and drain regions and methods of fabricating the same: A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region...

20060131659 - Cmos transistor structure including film having reduced stress by exposure to atomic oxygen: A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress...

20060131655 - Formation of deep trench airgaps and related applications: A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to...

20060131658 - Mos device, cmos device, and fabricating method thereof: A MOS or CMOS device includes a substrate with an active area, a gate oxide layer on the substrate, a gate on the gate oxide layer, first sidewalls on sides of the gate, the first sidewalls contacting the gate oxide layer, spacers formed outside the second sidewalls, and a salicide...

20060131657 - Semiconductor integrated circuit device and method for the same: In a surface region of a semiconductor substrate, an element isolation region for isolating the substrate into a plurality of element regions is formed. In each of the plurality of element regions, a pair of trenches, which are formed apart from each other and each have a bottom surface and...

20060131660 - Semiconductor storage device and semiconductor integrated circuit: A semiconductor storage device according to the present invention, comprising: a first semiconductor layer formed on a substrate via a buried insulation layer; an FBC (Floating Body Cell) having a channel body of floating type formed on the first semiconductor layer, a main gate which forms a channel at a...

20060131661 - Semiconductor device full-wave rectifier circuit and half-wave rectifier circuit: Unnecessary leakage current to a semiconductor substrate is prevented when a forward current flows through a diode. An N-type well region is formed in a surface of a P-type semiconductor substrate. A P-type well region is formed in the N-type well region. An N+-type diffusion layer is formed in a...

20060131662 - Semiconductor device: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region...

20060131663 - Semiconductor device and method for manufacturing the same: In a transistor, trenches are formed between each of a source region and a drain region and a channel region under the gate electrode at the position sandwiched by them. Ion implantation of impurity is carried out on the surface of the trench to form a low-concentration doped region. When...

20060131665 - Method for forming an integrated circuit: A method is described for manufacturing an n-MOS semiconductor transistor. Recesses are formed in a semiconductor substrate adjacent a gate electrode structure. Silicon is embedded in the recesses via a selective epitaxial growth process. The epitaxial silicon is in-situ alloyed with substitutional carbon and in-situ doped with phosphorus. The silicon-carbon...

20060131664 - N-type schottky barrier tunnel transistor and manufacturing method thereof: An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal suicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on...

20060131666 - Field effect transistor with buried gate pattern: A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate...

20060131667 - Sram cell: An SRAM cell with four transistors and two resistors formed in a semiconductor substrate, the transistors being formed in pairs in two active regions of the substrate, the resistors being formed by leakage capacitors, a first electrode of the capacitors being common and formed of a high supply line of...

20060131668 - Methods and systems for improved current sharing between parallel power semiconductors in power converters: Methods and systems for current sharing between power semiconductors in an assembly are provided. The power semiconductor assembly includes a plurality of power semiconductors, each comprising at least one output conductor, the plurality of output conductors are electrically coupled together in parallel, an output bus network configured to transpose the...

20060131669 - Thin film transistor for imaging system: An annular thin film transistor includes an annular source electrode disposed above the layer of the semiconductor material, a drain electrode disposed above the layer of the semiconductor material within the annular source electrode, and an active channel between the drain electrode and the annular source electrode, wherein a surface...

20060131671 - Electronic device including dielectric layer, and a process for forming the electronic device: A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer can...

20060131670 - Semiconductor device and production method therefor: A semiconductor device provided with a MIS type field effect transistor comprising a silicon substrate, a gate insulating film having a high-dielectric-constant metal oxide film which is formed on the silicon substrate via a silicon containing insulating film, a silicon-containing gate electrode formed on the gate insulating film, and a...

20060131673 - Insulating film and electronic device: An insulating film comprising: a first barrier layer; a well layer provided; and a second barrier layer is proposed. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer is provided on the first barrier layer, and consists of a...

20060131674 - Insulating film and electronic device: An insulating film comprising: a first barrier layer; a well layer provided; and a second barrier layer is proposed. The first barrier layer consists of a material having a first bandgap and a first relative permittivity. The well layer is provided on the first barrier layer, and consists of a...

20060131672 - Nitrogen treatment to improve high-k gate dielectrics: A MOSFET having a nitrided gate dielectric and its manufacture are disclosed. The method comprises providing a substrate and depositing a non-high-k dielectric material on the substrate. The non-high-k dielectric comprises two layers. The first layer adjacent the substrate is essentially nitrogen-free, and the second layer includes between about 1015...

20060131675 - Semiconductor device and method for high-k gate dielectrics: A semiconductor device and process including a high-k gate dielectric is described. A substrate is provided, and a high-k gate dielectric material, preferably amorphous HfSiON, is deposited over the substrate. In preferred embodiments, the high-k dielectric material includes nitrogen. In a preferred embodiment, a silicon nitride layer is deposited using...

20060131676 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: a substrate having a silicon layer on at least a surface thereof; an insulating film formed on the silicon layer; a first electrode formed on the insulating film and including a first metal thin film and a film having silicon formed on the first metal thin...

20060131678 - Method of manufacturing surface acoustic wave device and surface acoustic wave device: A method of manufacturing a surface acoustic wave device formed in one chip and including over a semiconductor substrate at least an IC region and a surface acoustic wave element region that are horizontally disposed, the method including: forming in the IC region over the semiconductor substrate a semiconductor element...

20060131677 - Systems and methods for electrically coupling wires and conductors: A first device includes a micrometer-scale or smaller geometry first conductor. A second device includes a micrometer-scale or smaller second conductor. An actuator the first and second devices relative to each other between first and second positions. Signals are substantially coupled between the first and second conductors in the first...

20060131679 - Systems and methods for electrical contacts to arrays of vertically aligned nanorods: Systems and methods may provide electrical contacts to an array of substantially vertically aligned nanorods. The nanorod array may be fabricated on top of a conducting layer that serves as a bottom contact to the nanorods. A top metal contact may be applied to a plurality of nanorods of the...

20060131680 - Piezoelectric element and method for manufacturing: A lower electrode is formed on a silica glass substrate or a stainless substrate. Through a sputtering process, a thin film of aluminum nitride and/or zinc oxide is formed on the lower substrate so that the degree of dipole-orientation becomes 55% or more, and thereby a piezoelectric thin film is...

20060131681 - Semiconductor devices and methods of forming interconnection lines therein: An example disclosed semiconductor device includes a semiconductor substrate, a lower interlayer insulating layer formed on the substrate, a lower wire formed on the lower interlayer insulating layer, and an upper interlayer insulating layer which is formed on the lower interlayer insulating layer and has a via hole to expose...

20060131684 - Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same: An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio...

20060131682 - Lithographic apparatus and device manufacturing method: A lithographic apparatus arranged to transfer a pattern from a patterning device onto a substrate is disclosed. The apparatus includes an optics compartment that contains a patterned surface of the patterning device and an optical element, and a substrate compartment connected to the optics compartment by a connection that is...

20060131683 - Microlens array: A microlens array includes two or more microlenses, wherein the individual microlenses are arranged and sized so that there are no gaps or substantially no gaps between microlenses through which incident light can pass without passing through a microlens....

20060131685 - Semiconductor device and method of fabricating the same: A semiconductor device has a semiconductor device chip with upper and lower terminal electrodes, and upper and lower frames bonded to the upper and lower terminal electrodes, respectively, with solder material, wherein the semiconductor device chip includes: a semiconductor layer of a first conductivity type; a diffusion layer of a...

20060131686 - Locos-based junction-pinched schottky rectifier and its manufacturing methods: The LOCOS-based junction-pinched Schottky rectifier comprises a raised diffusion guard ring surrounded by an outer LOCOS field oxide layer, a raised diffusion grid or a plurality of raised diffusion rings or stripes surrounded by the raised diffusion guard ring, a plurality of recessed semiconductor surfaces formed on a lightly-doped epitaxial...

20060131687 - Method and structure for implanting bonded substrates for electrical conductivity: A process for forming multi-layered substrates, e.g., silicon on silicon. The process includes providing a first substrate, which has a thickness of material to be removed. The thickness of material to be removed includes a first face region. The process includes joining the first face region of the first substrate...

20060131689 - Semiconductor device and fabrication method thereof: A semiconductor device includes a device isolation structure formed in a substrate so as to define a device region and a semiconductor device formed in the device region, wherein the device isolation structure includes a device isolation trench formed in the substrate so as to define the device region and...

20060131688 - Trench isolation structure, semiconductor assembly comprising such a trench isolation, and method for forming such a trench isolation: The present invention provides a trench isolation structure, comprising a trench groove (4) in a semiconductor slab (1) with a buried layer (2). The trench groove (4) is lined with first insulating material (5), then filled with a first filler material (6) up to the level of the buried layer....

20060131690 - Fuse box of semiconductor device and fabrication method thereof: A fuse box includes a semiconductor substrate having a fuse region, and a lower line in the fuse region that has a first region and a second region. An upper line is placed on the upper part of the lower line to overlap the first region. A fuse is placed...

20060131691 - Electronic device, assembly and methods of manufacturing an electronic device: A semiconductor substrate comprises both vertical interconnects and vertical capacitors with a common dielectric layer. The substrate can be suitably combined with further devices to form an assembly. The substrate can be made in etching treatments including a first step on the one side, and then a second step on...

20060131693 - High-gain bipolar junction transistor compatible with complementary metal-oxide-semiconductor (cmos) process and method for fabricating the same: A method for forming a bipolar junction transistor comprises forming a first well of a second conductive type for forming a collector region in a substrate including device isolation layers, wherein the substrate comprises a first conductive type, forming a second well of the first conductive type for a metal-oxide-semiconductor...

20060131692 - Light-emitting device: An object of the present invention is to provide at a low cost a light emitting device capable of emitting light not only in a visible light region, but also in an ultraviolet ray region and an infrared ray region with a high luminance and, further, capable of being reduced...

20060131694 - Integrated circuit arrangement with npn and pnp bipolar transistors and corresponding production method: An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region...

20060131695 - Fabricating arrays of metallic nanostructures: A patterned array of metallic nanostructures and fabrication thereof is described. A plurality of nanowires is grown on a substrate, the plurality of nanowires being laterally arranged on the substrate in a predetermined array pattern. The plurality of nanowires is coated with a metal to generate a plurality of metal-coated...

20060131696 - Semiconductor wafer with id mark, equipment for and method of manufacturing semiconductor device from them: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products....

20060131697 - Semiconductor methods and structures: A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without...

20060131698 - Wafer-scale microcolumn array using low temperature co-fired ceramic substrate: Provided is a wafer-scale microcolumn array using a low temperature co-fired ceramic (LTCC) substrate. The microcolumn array includes a LTCC substrate having wirings and wafer-scale beam deflector arrays, which are attached to at least one side of the LTCC substrate and has an array of deflection devices deflecting electron beams....

20060131699 - Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a buried insulating layer: By using an implantation technique for forming a buried insulation layer, an SOI-type configuration may be achieved for hybrid orientation substrates, thereby significantly enhancing the further fabrication processes in forming circuit elements on differently oriented semiconductor regions. Consequently, process complexity for methodology and production steps is significantly reduced compared to...

20060131700 - Flexible electronic circuit articles and methods of making thereof: The present invention includes an electronic-circuit article that has a substrate, a plasma deposited layer disposed on the substrate, where the plasma deposited layer comprises at least about 10.0 atomic percent, and a patterned conductive layer disposed above the plasma deposited layer....

20060131701 - Use of a down-bond as a controlled inductor in integrated circuit applications: A Radio Frequency (RF) device includes a semi conductive die and a package in which the semi conductive die mounts. The semi conductive die includes a first portion of an RF circuit and a plurality of die pads formed thereon. The package includes a heat slug upon which the semi...

20060131702 - Novel transmission lines for cmos integrated circuits: Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based...

20060131703 - Polymeric conductor donor and transfer method: The present invention relates to a donor laminate for transfer of a conductive layer comprising at least one electronically conductive polymer on to a receiver, wherein the receiver is a component of a device. The present invention also relates to methods pertinent to such transfers....

20060131704 - Packages for encapsulated semiconductor devices and method of making same: A semiconductor device package comprises a container having a base and side walls of an electrically insulating material. A semiconductor device chip is disposed on the base, and a lead frame extends through the side walls. At least one electrical conductor couples the lead frame to the chip. A first...

20060131705 - Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of...

20060131706 - Methods of making and using a floating lead finger on a lead frame: A semiconductor device assembly includes a semiconductor device and a lead frame having lead fingers for connection to the semiconductor device. The lead frame may include floating NC lead fingers with inner portions of the floating NC lead fingers electrically isolated from the semiconductor device and the associated outer portion...

20060131707 - Semiconductor device package with reduced leakage: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into...

20060131710 - Advanced cavity structure for wafer level chip scale package: The present invention provides an advanced cavity structure for optically sensitive devices in wafer level chip scale package and methods of manufacturing thereof. Image sensor or light detection integrated circuits are formed on substrate. Substantially absorptive bleached cavity walls are formed about the image sensor or light detection integrated circuits....

20060131711 - Package for semiconductor device: A lid for sealing a ceramic container receiving a semiconductor device such as an acceleration sensor is provided. The lid has an electrodeposition coating layer having a thickness of approximately 10 μm, which is formed by plating the outer surface of the 42 alloy plate having a thickness of approximately...

20060131708 - Packaged electronic devices, and method for making same: In one embodiment, an electronic device is packaged by electrically connecting the electronic device to an electrical contact on a substrate; applying a binding agent to bind the electronic device to the electrical contact; and then removing at least a portion of the substrate to expose the electrical contact as...

20060131709 - Semiconductor die positioning system and a method of bonding a semiconductor die to a substrate: The present invention describes a process for bonding a semiconductor die to a selected substrate, including the formation of a die positioning structure on the substrate to receive and secure the semiconductor die. The substrate is selected from a number of materials, the properties of which render it penetrable by...

20060131712 - Semiconductor wafer, an electronic component, and a component carrier for producing the electronic component: An electronic component includes a semiconductor chip with a chip topside, an integrated circuit, and a chip backside. The chip backside includes a magnetic layer. The electronic component further includes a chip carrier with a magnetic layer on its carrier topside. At least one of the two magnetic layers is...

20060131713 - Semiconductor device manufacturing method, semiconductor device, laminated semiconductor device, circuit substrate, and electronic apparatus: A semiconductor device includes a semiconductor element, a penetrating electrode which penetrates the semiconductor element, and a resin layer which selectively covers side walls and corners of the semiconductor element....

20060131717 - Multi-chip package structure: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate....

20060131718 - Multi-chip package structure: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate....

20060131715 - Multi-level semiconductor module: A semiconductor module is formed by alternately stacking resin boards on which semiconductor chips are mounted and sheet members having openings larger than the semiconductor chips and bonded to the resin boards. One of the resin boards located at the bottom has a thickness larger than that of each of...

20060131719 - Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device: A semiconductor device includes a first semiconductor package, in which a first semiconductor chip is mounted and a second semiconductor package, in which a second semiconductor chip is mounted and which is supported above the first semiconductor package so as to extend off the first semiconductor package....

20060131714 - Signal conduction for doped semiconductors: A first device has a surface and includes a micrometer-scale or smaller geometry doped semiconductor region extending along the surface. A second device has a surface opposite the surface of the first device and includes a micrometer-scale or smaller wire extending through the second device to a position in proximity...

20060131716 - Stacking system and method: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected...

20060131720 - Coating for enhancing adhesion of molding compound to semiconductor devices: A method is provided for enhancing adhesion between a molding compound and a semiconductor device comprising a semiconductor chip attached on a carrier, such as a lead frame, by coating the semiconductor device with a polymer primer prior to molding the semiconductor device. Such coating may be performed by dipping,...

20060131721 - Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument: A semiconductor device includes: a semiconductor substrate having an active surface and a back surface; an integrated circuit formed on the active surface; a feedthrough electrode penetrating the semiconductor substrate, and projecting from the active surface and the back surface; a first resin layer formed on the active surface, having...

20060131723 - Manufacturing method of a quad flat no-lead package structure: The present invention provides a method for fabricating a quad flat no-lead package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive...

20060131722 - Package and method for saving space required by i/o of chip: A package and a method for saving space required by I/Os of a chip are described. In this method, a plurality of general I/Os and at least one special I/O are allocated in different areas. When the chip is attached to a circuit board, the special I/O is adjacent to...

20060131724 - Semiconductor apparatus and circuit apparatus: A semiconductor apparatus comprises a substrate, a semiconductor chip fixedly secured on one side of the substrate, a spirally shaped coil formed on the other side of the substrate and electrically connected to the semiconductor chip, and a conductive pattern formed on a surface of the one side of the...

20060131726 - Arrangement of input/output pads on an integrated circuit: Input/output pads are arranged on an integrated circuit. Input/output pads are placed around a perimeter of core circuitry. Each input/output pad has an input/output pad bond opening with a height in a direction perpendicular to the perimeter of the core circuitry and with a width in a direction parallel to...

20060131727 - Semiconductor device: Radiation noise is reduced, and any operation error is prevented by suppressing noise propagation between an input/output circuit and an internal circuit while preventing or minimizing an increase in the number of steps of semiconductor element design. A semiconductor device having an input/output circuit region and an internal circuit region...

20060131725 - System for implementing a configurable integrated circuit: The present invention provides a system for implementing a configurable integrated circuit (IC). Aspects of the invention include an IC die; a plurality of input/outputs (I/Os) coupled to the IC die; and a plurality power planes coupled to the IC die for providing power to the plurality of I/Os at...

20060131728 - Repairable three-dimensional semiconductor subsystem: A tightly packed three-dimensional electronic system or subsystem comprising multiple stacks of semiconductor elements is described. The system is repairable because the elements connect together using re-workable flip chip connectors; each flip chip connector comprises a conductive spring element on one side and a corresponding well filled with solder on...

20060131729 - Ball grid array substrate having window and method of fabricating same: Disclosed is a ball grid array substrate having a window formed on a core material instead of a thin core material, and wherein a semiconductor chip is mounted thereon, thereby reducing the thickness of a package, and a method of fabricating the same. The ball grid array substrate comprises a...

20060131730 - Semiconductor package and fabrication method: A semiconductor package and a fabrication method thereof are disclosed, whereby an environmental problem is solved by using external connection terminals or semiconductor element-mounting terminals containing a smaller amount of lead, while at the same time achieving a fine pitch of the terminals. The semiconductor package includes a board (20)...

20060131731 - Midair semiconductor device and manufacturing method of the same: A midair semiconductor device includes a Si substrate provided with an element part on its front surface side. An opening is formed in the Si substrate in such a manner that a rear surface of the element part is exposed. The opening is provided below the element part while penetrating...

20060131732 - Discrete electronic component arrangement including anchoring, thermally conductive pad: An electronic component arrangement includes a discrete electronic component having first and second terminals and a centre-exposed pad. A substrate has a first electrical conductor electrically connected to the first terminal, a second electrical conductor electrically connected to the second terminal, and a third electrical conductor. A thermally conductive element...

20060131735 - Hyper thermally enhanced semiconductor package system: A semiconductor package system is provided including mounting a semiconductor chip to a substrate having a substrate opening. A first heat slug is attached to a first surface of the semiconductor chip at least partially encapsulating the semiconductor chip. A second heat slug is attached to the second surface of...

20060131733 - Integrated circuit coolant microchannel with movable portion: According to some embodiments, a microchannel is provided to transport a coolant. The microchannel may be proximate to an integrated circuit to transfer heat from the integrated circuit to the coolant. Moreover, a movable portion may be provided to adjust a volume of a space associated with the microchannel (e.g.,...

20060131734 - Multi lead frame power package: According to an embodiment of the invention, a system, operable to facilitate dissipation of thermal energy, includes a mold compound, a die, a first lead frame, and a second lead frame. The die is disposed within the mold compound, and in operation generates thermal energy. The first lead frame is...

20060131736 - Package for a high-frequency electronic device: The electronic device comprises a substrate (1) with a cavity (6) in which an active device (8) is present. On the first side (2) of the substrate an interconnect structure (17) extends over the cavity and the substrate. On the second side (3) of the substrate to which the cavity...

20060131737 - Semiconductor chip having coolant path, semiconductor package and package cooling system using the same: The present invention relates to a semiconductor chip coolant path, a semiconductor package utilizing the semiconductor chip coolant path, and a cooling system for the semiconductor package. For effective dissipation of heat generated during semiconductor chip operation, a semiconductor chip having a coolant path formed through or adjacent to its...

20060131738 - Method and apparatus for chip cooling using a liquid metal thermal interface: In one embodiment, the present invention is a method and apparatus for chip cooling using a liquid metal thermal interface. One embodiment of an inventive thermal interface for facilitating thermal contact between opposing surfaces of an integrated circuit chip and a heat sink the thermal interface includes a liquid metal...

20060131739 - Semiconductor device and method of arranging pad thereof: A semiconductor device and method of forming a pad thereof are provided. The device includes: a substrate; at least one first active region disposed in a first region of the substrate; at least one second active region disposed in a second region adjacent to the first region of the substrate;...

20060131740 - Multi-level semiconductor module and method for fabricating the same: A semiconductor module is formed by alternately stacking resin boards 3 on which semiconductor chips 2 are mounted and sheet members having openings larger than the semiconductor chips 2 and bonded to the resin boards 3. The resin board 4 located at the bottom out of the resin boards 3...

20060131741 - Semiconductor device and manufacturing method of the same: The invention realizes excellent electrical and mechanical connection between electrodes in a packaging structure where a plurality of semiconductor chips having electrodes are connected with each other through the low-melting metallic members. Bump electrodes are formed on a front surface of a first semiconductor chip. Penetrating holes are formed in...

20060131742 - Packaged chip capable of lowering characteristic impedance: A packaged chip lowering characteristic impedance comprises a chip, a lead wire frame, a plurality of metal layers, adhesive layers, lead wires, and a mold, being formed into TSOP LOC and thin-small-sized packaging types; from a specified site above or under each row of leads of the lead wire frame,...

20060131748 - Ball limiting metallurgy split into segments: The present invention discloses a novel layout and process for a device with segmented BLM for the I/Os. In a first embodiment, each BLM is split into two segments. The segments are close to each other and connected to the same overlying bump. In a second embodiment, each BLM is...

20060131747 - Carrier with metal bumps for semiconductor die packages: A carrier for a semiconductor die package is disclosed. In one embodiment, the carrier includes a metal layer and a plurality of bumps formed in the metal layer. The bumps can be formed by stamping....

20060131743 - Changing chip function based on fuse states: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused...

20060131746 - Circuit device: A circuit device in which highly reliable sealing with a resin can be achieved is provided. A semiconductor chip is provided on one surface of an insulating resin film and a conductive layer that is electrically connected to the semiconductor chip is provided on another surface of the insulating resin...

20060131744 - Method and apparatus for providing a bga connection having improved drop test performance: A BGA (Ball Grid Array Structure) having improved drop test performance by increasing the area of the solder bond at the corner of the array using existing assembling machinery....

20060131745 - Semiconductor device and manufacturing method therefor: A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode...

20060131749 - Metal layer in semiconductor device and method of forming the same: Canting or falling of an upper metal line may be prevented by improving adhesion between an insulation layer and a metal layer. A method for forming a semiconductor which improves adhesion between an insulation layer and a metal layer includes: preparing a substrate formed with a lower metal layer; forming...

20060131750 - Protection of seedlayer for electroplating: The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing the protection layer and forming a conductor over the seed layer. The present invention further includes a structure having a...

20060131752 - Micro column electron beam apparatus formed in low temperature co-fired ceramic substrate: A micro column electron beam apparatus having a reduced number of interconnections is provided. The micro column electron beam apparatus includes: a low temperature co-fired ceramic (LTCC) substrate; a plurality of deflector electrodes attached to a predetermined top portion of the LTCC substrate; a pad electrode placed at a top...

20060131751 - Semiconductor device and method for manufacturing the same: Disclosed is a semiconductor device comprising a semiconductor substrate, a first insulating film formed above the semiconductor substrate, Cu wiring buried in the first insulating film, a second insulating film formed above the Cu wiring, and a discontinuous film made of at least one metal selected from the group consisting...

20060131753 - Materials and methods for forming hybrid organic-inorganic dielectric materials for integrated circuit applications: An integrated circuit is provided comprising a substrate and discrete areas of electrically insulating and electrically conductive material, wherein the electrically insulating material is a hybrid organic-inorganic material that has a density of 1.45 g/cm3 or more and a dielectric constant of 3.0 or less. The integrated circuit can be...

20060131754 - Semiconductor device having trench interconnection and manufacturing method of semiconductor device: A semiconductor device includes a first interconnection layer and a interlayer insulating layer. The first interconnection layer is formed on a upper side of a substrate, and includes a first interconnection. The interlayer insulating layer is formed on the first interconnection layer, and includes a via connected with the first...

20060131755 - Method of making circuitized substrate: A method of making a circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the dielectric...

20060131756 - Semiconductor device with a metal line and method of forming the same: A method of forming a metal line in a semiconductor device including forming a first insulation layer and a first etch stop layer on a conductive layer, and forming a first photosensitive layer pattern on the first etch stop layer; forming a first opening by etching the first etch stop...

20060131757 - Light emitting module: A light emitting module includes a substrate, a driving circuit chip, a light emitting element and a connector. By providing the connector with conductive bumps and arranging it as a flip chip to contact the conductive bumps with bond pads of the driving circuit chip and the light emitting element,...

20060131758 - Anchored non-solder mask defined ball pad: A ball grid pad for connecting a ball grid array package to a printed circuit board includes a circular pad area adhered on a ball grid connection surface. A solder mask on the ball grid connection surface has an opening surrounding and spaced apart from the circular pad area. The...

20060131759 - Bonding pad structure: A substrate has a bonding region and a sensing region. A first dielectric layer is formed overlying the substrate and has a dielectric island surrounded by a ring-shaped trench. A first conductive layer is formed in the ring-shaped trench of the first dielectric layer. A passivation layer is formed overlying...

20060131760 - Power semiconductor package: A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode....

20060124915 - Production of an optoelectronic component that is enclosed in plastic, and corresponding methods: The invention relates to a simplified method for assembling optoelectronic components that are enclosed in plastic and the construction thereof. The individual component unit contains a semiconductor chip (11) and an optical window (10). A hermetic inclusion of at least the optically active of the semiconductor chip via the window...

20060124916 - Self-aligned small contact phase-change memory method and device: The invention relates to a novel memory cell structure and process to fabricate chalcogenide phase change memory. More particularly, it produces a small cross-sectional area of a chalcogenide-electrode contact part of the phase change memory, which affects the current/power requirement of the chalcogenide memory. Particular aspects of the present invention...

20060124917 - Adapting short-wavelength led's for polychromatic, broadband, or \"white\" emission: An adapted LED is provided comprising a short-wavelength LED and a re-emitting semiconductor construction, wherein the re-emitting semiconductor construction comprises at least one potential well not located within a pn junction. The potential well(s) are typically quantum well(s). The adapted LED may be a white or near-white light LED. The...

20060124918 - Polychromatic led's and related semiconductor devices: A semiconductor device is provided comprising a first potential well located within a pn junction and a second potential well not located within a pn junction. The potential wells may be quantum wells. The semiconductor device is typically an LED, and may be a white or near-white light LED. The...

20060124919 - Ge-si quantum well structures: Si—Ge quantum wells where the well material has a lowest conduction band energy minimum at k=0 (the Γ point of the first Brillouin zone) are provided. Quantum well structures that satisfy this condition have “Kane-like” bands at and near k=0 which can provide physical effects useful for various device applications,...

20060124921 - Compound with indolocarbazole moieties and devices containing such compound: A compound composed of a plurality of optionally substituted indolocarbazole moieties which are the same or different from each other....

20060124922 - Conductive ink, organic semiconductor transistor using the conductive ink, and method of fabricating the transistor: Provided are a conductive ink, organic semiconductor transistor using the conductive ink, and method of fabricating the transistor. The conductive ink is used to form electrodes on an organic semiconductor while minimizing the damage of the organic semiconductor. The conductive ink is formed by mixing metal nanoparticles with a conductive...

20060124925 - Electron device, operational device and display device: An electron device includes at least an electrode layer, a semiconductor layer and an insulator layer laminated on a substrate, wherein the insulator layer contains a polyimide material obtained by using at least one of a polyamic acid and derivatives of the polyamic acid, the polyamic acid being obtained by...

20060124920 - Organic el device and organic el panel:

20060124924 - Thin film transistor and flat panel display including the same: Provided are a thin film transistor and an organic electrolumienscent display including the same. The organic electroluminescent display includes: a gate electrode; source and drain electrodes that are insulated from the gate electrode; an organic semiconductor layer that is insulated from the gate electrode and electrically connected to the source...

20060124923 - Thin film transistors including indolocarbazoles: A thin film transistor composed of a semiconductor layer including an optionally substituted indolocarbazole....

20060124926 - Iridium oxide nanostructure: A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas...

20060124928 - Integrated circuit disabling: A method and a circuit for protecting at least one element of an integrated circuit, including conditioning the operation of the element to be protected to the state of a signal conditioned by an irreversibly programmable element, the state of which is set during a probe test of the integrated...

20060124927 - Iridium oxide nanostructure: Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on...

20060124929 - Semiconductor substrate for solid-state image pickup device and producing method therefor: A semiconductor substrate for forming a pixel area provided surfacially with a plurality of pixels for photoelectric conversion, the semiconductor substrate, including a polysilicon film of a thickness of 0.5-2.0, on a rear surface of the pixel area-bearing surface, and having an oxygen concentration of 1.3-1.5E+18 atom/cm3 (old ASTM)....

20060124930 - Thin film transistor and method of making the same: A thin film transistor is characterized by having an island-in structure having a semiconductor layer with a channel region, a bottom heavily-doped semiconductor layer, and a top heavily-doped semiconductor layer. The bottom heavily-doped semiconductor layer is positioned on two opposite sides of the surface of the semiconductor layer beyond the...

20060124931 - Organic electroluminiscence display panel and manufacturing method thereof: A polysilicon layer is formed on an insulating substrate and a gate insulating layer is formed on the polysilicon layer. A gate line is formed on the gate insulating layer and an interlayer insulating film is formed on the gate line. A data line and a pixel electrode are formed...

20060124933 - Organic light emitting display device and method of fabricating the same: An organic light emitting display device and a method of fabricating the same. A dummy pattern is formed in an emission region to increase the step height of the emission region by an electrode material while a thin film transistor is fabricated, so that a distance between a pixel electrode...

20060124932 - Thin film transistor array panel for x-ray detector: A thin film transistor array panel for an X-ray detector includes a dummy pixel including a photo diode and a TFT for detecting leakage current. The photo diode includes first and second electrodes (178,195) facing each other and a photo-conductive layer (800) disposed between the first electrode and the second...

20060124934 - Thin film transistor, production method and production apparatus therefor: A thin film transistor produced through flattening a gate insulating film acquires the high mobility of a carrier, but has a problem of occasionally showing low resistivity, low withstanding voltage, and consequent low reliability. The present invention solves the above described problem and provides a thin film transistor having the...

20060124935 - Cmos inverter constructions: Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed crystalline lattice. The relaxed crystalline lattice...

20060124936 - Soi device with different crystallographic orientations: A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010]...

20060124937 - Patterned substrate, electro-optical device, and method for manufacturing an electro-optical device: A patterned substrate includes a laminated pattern having laminated patterns that are formed by drying droplets containing a pattern formation material. A lower layer pattern contains lyophilic microparticles that are lyophilic with respect to droplets that form an upper layer pattern....

20060124940 - Electro-optical device, method of manufacturing the same, and electronic apparatus: An electro-optical device includes a light-emitting layer provided with a white light-emitting element; and a reflective filter layer that is located at one side of the light-emitting layer and is provided with a reflective color filter....

20060124939 - Method for manufacturing gan-based light emitting diode using laser lift-off technique and light emitting diode manufactured thereby: A simplified manufacturing process for massive production of LEDs that have superior light emitting efficiency and superior heat discharging efficiency. The method employs a laser lift-off technique instead of the flip-chip bonding technique and it does not require a photolithography process, thereby substantially reducing the process steps and enhancing the...

20060124938 - Type ii broadband or polychromatic led's: An LED is provided comprising two or more light-emitting Type II interfaces wherein at least two of the Type II interfaces differ in transition energy by at least 5%, or more typically by at least 10%, and wherein at least one of the Type II interfaces is within a pn...

20060124941 - Thin gallium nitride light emitting diode device: Disclosed is a light emitting diode (LED) device that comprises a crystal structure of a sapphire substrate-free gallium nitride (GaN) LED, wherein the crystal structure is mounted on a first surface of a sub-mount substrate in the form of a unit chip, and the first surface of the sub-mount substrate...

20060124942 - Light-emitting semiconductor device, light-emitting system and method for fabricating light-emitting semiconductor device: A chip-type light-emitting semiconductor device includes: a substrate 4; a blue LED 1 mounted on the substrate 4; and a luminescent layer 3 made of a mixture of yellow/yellowish phosphor particles 2 and a base material 13 (translucent resin). The yellow/yellowish phosphor particles 2 is a silicate phosphor which absorbs...

20060124943 - Large-sized light-emitting diodes with improved light extraction efficiency: A light-emitting device with an array of window openings to enhance the light extraction efficiency from this device is provided. This array of window openings is employed to create a much larger sidewall area to enhance the light extraction from the sidewalls of these openings. With this array of window...

20060124944 - Pixel circuit and light emitting display using the same: A light emitting display includes a plurality of light emitting diodes within a pixel. A drive circuit is coupled to the plurality of light emitting diodes and generates a drive current flowing through the light emitting diodes corresponding to a data current. A switch circuit assembly is coupled to the...

20060124949 - Electrical conductors in an electroluminescent display device: Provided is an electroluminescent display device having a negligibly small voltage drop of a cathode, no external light reflection, and high contrast and luminance. The electroluminescent display device includes a rear substrate, a first electrode layer formed above the rear substrate, a second electrode layer formed above the first electrode...

20060124950 - Electrical conductors in an electroluminescent display device: Provided is an electroluminescent display device having a negligibly small voltage drop of a cathode, no external light reflection, and high contrast and luminance. The electroluminescent display device includes a rear substrate, a first electrode layer formed above the rear substrate, a second electrode layer formed above the first electrode...

20060124948 - Method of fabricating cmos image sensor: A method of fabricating a CMOS image sensor is provided, in which a trapezoidal microlens pattern profile is formed to facilitate reflowing the microlens pattern and by which a curvature of the microlens may be enhanced to raise its light-condensing efficiency. The method includes forming a plurality of photodiodes on...

20060124946 - Optical transmitter: The present invention provides an optical transmitter for transmitting an optical signal using an optical fiber as a transmission medium. The optical transmitter comprises: a substrate having a through hole; and a light-emitting element disposed on a rear surface of the substrate and having a light-emitting portion. The through hole...

20060124947 - Phosphor converted light emitting device: A semiconductor light emitting device is combined with a wavelength converting material. The semiconductor light emitting device is configured to emit first light of a first peak wavelength. The wavelength converting material is configured to absorb at least a portion of the first light and emit second light of a...

20060124945 - Radiation-emitting semiconductor component and method for the production thereof: A radiation-emitting semiconductor component having a radiation-transmissive substrate (1), on the underside of which a radiation-generating layer (2) is arranged, in which the substrate (1) has inclined side areas (3), in which the refractive index of the substrate (1) is greater than the refractive index of the radiation-generating layer, in...

20060124951 - Ceramic composite material for optical conversion and use thereof: A ceramic composite material for light conversion, which is a solidified body comprising two or more matrix phases with respective components being two or more oxides selected from the group consisting of metal oxides and complex oxides each produced from two or more metal oxides, wherein at least one of...

20060124952 - Light emitter: One embodiment of a light emitting microchip apparatus includes a substrate having an exposed depression therein and a filament positioned within the exposed depression....

20060124955 - Method of manufacturing surface-emitting backlight, by molding contact member integrally with molded case: A method of manufacturing a surface-emitting backlight is provided with the steps of forming a lead frame and resin-made molded case by insert molding, attaching light sources, which are red, blue and green LED dies, to contacts of the lead frame provided in a hollow space of the molded case,...

20060124954 - Semiconductor light emitting device and method for manufacturing the same: A semiconductor light emitting device having a semiconductor stacking structure bonded onto the support member and having excellent characteristics is provided by a preferable electrode structure. The semiconductor light emitting device comprising; a semiconductor stacking structure having a first semiconductor layer and a second semiconductor layer of conductivity types different...

20060124953 - Semiconductor light emitting device mounting substrates and packages including cavities and cover plates, and methods of packaging same: A mounting substrate for a semiconductor light emitting device includes a solid metal block having first and second opposing metal faces. The first metal face includes a cavity that is configured to mount at least one semiconductor light emitting device therein, and to reflect light that is emitted by at...

20060124956 - Quasi group iii-nitride substrates and methods of mass production of the same: The present invention discloses the large area high quality quasi group III-nitride substrates comprising two categories: electrically conductive and isolating. The methods manufacturing the same comprise the following process steps in the order presented: disposing a first intermediate layer on a large area silicon (Si) original growth substrate, disposing a...

20060124957 - Single-phase converter module: A converter module is described having a positive terminal (2), a negative terminal (4), and a phase terminal (3), as well as a first semiconductor chip (9) and a second semiconductor chip (9), the terminals (2-4) and the semiconductor chips (9) being situated on top of one another in a...

20060124958 - Cathode for an electrode source: A thermionic cathode (100) comprises an individual carbon nanotube (102) attached between two electrodes (104, 106). The electrodes (104, 106) each comprise a post (110, 112) and a carbon fibre (114, 116). A gap (118) narrower than the length of the nanotube (102) is provided between the two carbon fibres...

20060124959 - Low capacitance over-voltage protection thyristor device: An over-voltage protection thyristor has reduced junction capacitance making it suitable for use in high bandwidth applications. The reduced capacitance is achieved through the introduction of a deep base region. The deep base region has a graded doping concentration which reduces with depth into the substrate. The thyristor is useful...

20060124960 - Semiconductor device and method for fabricating the same: A semiconductor device includes a semiconductor substrate of n-type silicon including, in an upper portion thereof, a first polarity inversion region and a second polarity inversion regions spaced from each other and doped with a p-type impurity. A first HFET including a first active layer and a second HFET including...

20060124962 - Field effect transistor and method for fabricating the same: A field effect transistor includes a first semiconductor layer made of a multilayer of a plurality of semiconductor films and a second semiconductor layer formed on the first semiconductor layer. A source electrode and a drain electrode are formed on the second semiconductor layer to be spaced from each other....

20060124961 - Semiconductor substrate, manufacturing method thereof, and semiconductor device: A separation layer is formed on a silicon substrate. An SiGe layer serving as a strain induction layer and a silicon layer serving as a strained semiconductor layer are formed sequentially on the separation layer to prepare a first substrate. The first substrate is bonded to a second substrate made...

20060124963 - Transistor of semiconductor device and method of fabricating the same: Provided are a transistor of a semiconductor device and a method of fabricating the same. The transistor of a semiconductor device includes an epitaxial substrate having a buffer layer, a first silicon (Si) planar doped layer, a first conductive layer, a second Si planar doped layer having a different dopant...

20060124964 - Method of collector formation in bicmos technology: A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at...

20060124965 - Capacitor that includes high permittivity capacitor dielectric: A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative...

20060124966 - Array substrate, display apparatus having the same and method for repairing the same: In an array substrate, a display apparatus having the same and a method for repairing the same, a substrate includes a display area and a peripheral area that is adjacent to the display area. A plurality of signal transmitting lines are formed in the peripheral area of the substrate. A...

20060124967 - Nrom memory cell, memory array, related devices and methods: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store...

20060124968 - Method of estimating wiring complexity degree in semiconductor integrated circuit: A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, includes a step of predicting a power-supply wiring space used in the semiconductor integrated circuit, a step...

20060124969 - Mos transistor and manufacturing method thereof: A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer and the insulation layer. The transistor includes a deep extended source/drain region, a first source/drain region...

20060124972 - Cross-fill pattern for metal fill levels, power supply filtering, and analog circuit shielding: A cross-fill metal fill pattern technique is provided such that portions of a metal fill pattern are patterned to accomplish a secondary function. For instance, in the exemplary embodiments, ever other trace or line of interdigitated fingers is routed to a ground, while the interceding traces or lines of interdigitated...

20060124970 - Device for data exchange between a transmitter and a receiver: The inventive data exchange device comprises a transmitter (SA4) fed by a power supply (VDDA), an electric cable (C1) whose first conducting wire is connected to a fixed potential point (GNDA) of the transmitter and second conducting wire is connected to a variable potential point of the transmitter and a...

20060124971 - Semiconductor structure, semiconductor device, and method and apparatus for manufacturing the same: A semiconductor device includes a non-single-crystal semiconductor film, a support substrate that supports the non-single-crystal semiconductor film, and an active device having a part of the non-single-crystal semiconductor film as a channel region. In particular, the channel region has an oxygen concentration not higher than 1×1018 atoms/cm3 and a carbon...

20060124973 - Energy storage device, module thereof and electric vehicle using the same: An object of the present invention is to provide an energy storage device excellent in input/output characteristics at low temperatures, a module thereof and a vehicle using the module. The present invention provides an energy storage device comprising: a positive electrode having a region where a reaction accompanied by charge...

20060124974 - Structure and method to generate local mechanical gate stress for mosfet channel mobility modification: A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack...

20060124975 - Dual work function gate in cmos device: A transistor has a first silicon layer comprising a source region and a drain region separated by a channel region. A gate oxide is formed over the first silicon layer. A second silicon layer is formed over the gate oxide and comprises a dual work function gate. The dual work...

20060124976 - Recessed gate for an image sensor: A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side...

20060124977 - Solid-state image sensing device and camera system using the same: A solid-state image sensing device includes a plurality of pixels. Each pixel has a photodiode, a first transistor, and a second transistor. The photodiode is constituted by a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first and second conductivity types are opposite to each other. The first transistor...

20060124978 - Spin valve transistor with stabilization and method for producing the same: A method and structure for a spin valve transistor (SVT) comprises a magnetic field sensor, an insulating layer adjacent the magnetic field sensor, a bias layer adjacent the insulating layer, a non-magnetic layer adjacent the bias layer, and a ferromagnetic layer over the non-magnetic layer, wherein the insulating layer and...

20060124979 - Dram memory cell and method of manufacturing the same: A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that...

20060124981 - Dram technology compatible processor/memory chips: The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile...

20060124980 - Stacked capacitor-type semiconductor storage device and manufacturing method thereof: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film...

20060124982 - Low-cost deep trench decoupling capacitor device and process of manufacture: A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design....

20060124984 - Method for fabricating capacitor of semiconductor device: The present invention relates to a method for fabricating a capacitor of a semiconductor device. The semiconductor device includes: a bit line structure formed on a substrate and including stacked layers of a bit line, a hard mask and a spacer, the spacer formed along a profile containing the bit...

20060124983 - Semiconductor device and method for fabricating the same: A semiconductor device has contact plugs each for electrically connecting a capacitor element to the source/drain region of a transistor, conductive layers formed on the contact plugs and made of titanium nitride which is a nitride only of a refractory metal, and polycrystalline conductive oxygen barrier layers each composed of...

20060124985 - Methods of forming in package integrated capacitors and structures formed thereby: Methods of forming a microelectronic structure are described. Those methods comprise depositing a bottom electrode, depositing a dielectric layer on the bottom electrode, forming at least one via in the dielectric layer, wherein a bottom surface of the via does not contact a top surface of the bottom electrode, and...

20060124987 - Capacitor of semiconductor device and method for manufacturing the same: Provided is a capacitor of a semiconductor device. The capacitor includes a capacitor lower electrode disposed on a semiconductor substrate. A first dielectric layer comprising aluminum oxide (Al2O3) is disposed on the capacitor lower electrode. A second dielectric layer comprising a material having a higher dielectric constant than that of...

20060124986 - Cmos image sensor and manufacturing method thereof: A gate insulation layer with a high dielectric constant for a CMOS image sensor formed by a damascene process. A silicide layer on a gate electrode layer is formed in both a pixel region and a peripheral circuit region, and a silicide layer on a source/drain region is formed only...

20060124989 - Ballistic injection nrom flash memory: A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The nitride storage regions are isolated...

20060124988 - Methods of fabricating flash memory devices having self-aligned floating gate electrodes and related devices: A semiconductor memory device is fabricated by forming an active region protruding from a semiconductor substrate, forming an isolation layer on the substrate adjacent opposing sidewalls of the active region, and forming a floating gate electrode on a surface of the active region between the opposing sidewalls thereof. The floating...

20060124990 - Memory device with reduced cell area: The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region (220) is formed in the bulk substrate (210). A first active region (220) is formed in the first lightly doped region (220). A second lightly doped region (320) is formed in the bulk...

20060124992 - Nrom memory cell, memory array, related devices and methods: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store...

20060124991 - Semiconductor device: A semiconductor device includes a semiconductor region having a source region, a drain region, and a channel region provided between the source region and the drain region, a first tunnel insulation film formed on the channel region, a barrier layer formed on the first tunnel insulation film and having an...

20060124993 - Sidewall semiconductor transistors: A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the...

20060124994 - Vertical double-diffused metal oxide semiconductor (vdmos) device incorporating reverse diode: The present invention disclosed herein is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device incorporating a reverse diode. This device includes a plurality of source regions isolated from a drain region. A source region in close proximity to the drain region is a first diffusion structure in which a heavily...

20060124998 - Nrom memory cell, memory array, related devices and methods: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store...

20060124995 - Semiconductor device and manufacturing method for semiconductor device: A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor...

20060124997 - Semiconductor device and method of manufacturing the same: A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type impurities whose concentration is lower than the first portion region constituting...

20060124996 - Vertical trench gate transistor semiconductor device and method for fabricating the same: A first region functioning as a transistor includes a drain region, a body region formed over the drain region, a source region formed over the body region and a trench formed through the body region and having a gate electrode buried therein. A source region is formed over the body...

20060124999 - Drain extended pmos transistors and methods for making the same: Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness....

20060125000 - Field effect transistor and fabrication method: A field effect transistor (FET) and fabrication method are disclosed. The FET includes a drift region formed in a substrate. A trench adjoins the drift region and contains at least one control region and a connection region. An inversion channel region is isolated from the control region. A portion of...

20060125001 - Transistors having buried n-type and p-type regions beneath the source region and methods of fabricating the same: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided...

20060125003 - High voltage power mosfet having low on-resistance: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have...

20060125002 - Semiconductor structure for operation at high current: A semiconductor structure for operation at high current related to a small volume of semiconductor structure that could enhance the rated current of the prior art, especially used in high-power cells of integrated circuits like transistors in the power supply. The semiconductor structure uses the third metal layer for enhancing...

20060125004 - Transistor with reduced gate-to-source capacitance and method therefor: A power transistor, formed from transistors connected in parallel, each transistor is formed in an active region using a relatively long gate called a gate finger that is typically formed from polysilicon that accumulates resistance over its length. To alleviate this, the gate finger is strapped to a metal line...

20060125005 - Electrode contact section of semiconductor device: A p-type impurity layer is formed in an n-type semiconductor substrate. Since the p-type impurity layer has a low impurity concentration and a sufficiently shallow depth of 1.0 μm or less, the carrier injection coefficient can be reduced. In the p-type impurity layer, a p-type contact layer of a high...

20060125006 - Semiconductor device having a field effect transistor using a high dielectric constant gate insulating film and manufacturing method of the same: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating...

20060125007 - Local interconnect structure and method for a cmos image sensor: A self-aligned silicide (salicide) process is used to form a local interconnect for a CMOS image sensor consistent with a conventional CMOS image sensor process flow. An oxide layer is deposited over the pixel array of the image sensor. Portions of the oxide layer is removed and a metal layer...

20060125008 - Dual stressed soi substrates: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a...

20060125011 - Memory with split gate devices and method of fabrication: A DRAM fabricated on an SOI substrate employing single body devices as memory cells without relying on a field through the insulative layer of the SOI is described. Floating body devices are defined by orthogonally disposed lines with both a front gate and back gate for each body being formed...

20060125010 - Methods of forming transistor constructions: The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body region includes a charge trapping region. The memory cell can be TFT-SOI based, and can be supported by a substrate selected from a diverse assortment of materials....

20060125009 - Thin film transistors including indolocarbazoles: A thin film transistor composed of a semiconductor layer including an optionally substituted indolocarbazole....

20060125013 - Double silicon-on-insulator (soi) metal oxide semiconductor field effect transistor (mosfet) structures: A SOI MOSFET structure having a reduced step height between the various semiconductor layers without adversely affecting the junction capacitance of the semiconductor device formed on the uppermost semiconductor layer as well as a method of fabricating the same are provided. The structure of the present invention includes an elevated...

20060125012 - Varactor: A varactor having a capacitance includes a depletion mode transistor having a gate, a source, and a drain and an enhancement mode transistor also having a gate, a source, and a drain. The gates of the depletion mode transistor and the enhancement mode transistor are coupled together, the sources of...

20060125014 - Diode with low junction capacitance: A diode is comprised of a doped region formed with a first dopant of a first conductivity type. In addition, the diode further comprises a substrate doped with a second dopant of a second conductivity type opposite of the first conductivity type. The lightly doped substrate, instead of a well,...

20060125016 - Electrostatic discharge protection circuit using triple welled silicon controlled rectifier: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a...

20060125015 - Esd protection for high voltage applications: An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and the...

20060125017 - Stacked memory cell utilizing negative differential resistance devices: A memory cell includes two negative differential resistance (NDR) field effect transistors (FETs) forming a bistable latch, and an access transistor for allowing data to be passed to and from the storage node formed by the bistable latch. By stacking the NDR-FETs and the access transistor in two or more...

20060125020 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are disclosed, in which an incidence of void formation is reduced or prevented, to improve characteristics of the image sensor. The CMOS image sensor includes a plurality of photodiode areas in a semiconductor substrate at constant intervals, a dielectric...

20060125018 - Complementary metal-oxide semiconductor (cmos) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same: A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer....

20060125019 - Gate defined schottky diode: A Schottky diode exhibiting low series resistance is efficiently fabricated using a substantially standard CMOS process flow by forming the Schottky diode using substantially the same structures and processes that are used to form a field effect transistor (FET) of a CMOS IC device. Polycrystalline silicon, which is used to...

20060125021 - Methods of forming sram constructions: The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystalline layer, and in particular aspects an entirety of the active...

20060125022 - Semiconductor device and method for fabricating the same: The method for fabricating a semiconductor device comprises the step of forming a Co film 72 on a gate electrode 30 having a gate length Lg of below 50 nm including 50 nm; the first thermal processing step of making thermal processing to react the Co film 72 and the...

20060125023 - Semiconductor device including overcurrent protection element: A semiconductor device includes first, second, third, and fourth semiconductor regions, a gate electrode, and silicide layers. The first, second, and third semiconductor regions are formed in a semiconductor substrate while being spaced part from each other. The fourth semiconductor region is formed in the semiconductor substrate between the second...

20060125024 - Semiconductor device and a method of manufacturing the same: To improve reliability of FETs having element isolation regions for electrically isolating field effect transistors adjacent to each other in the gate length direction in a mask ROM region, the isolation regions are each constructed by field plate isolation formed simultaneously with gate electrodes of the field effect transistors. This...

20060125025 - Vertical field effect transistor and method for fabricating the same: A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region where electric carriers are transported; a lower electrode, connected to the bottom of the active region and functioning as one of source and drain regions; an upper electrode, connected to...

20060125029 - Method of manufacturing semiconductor device having oxide films with different thickness: After a first gate oxide film is formed on a substrate, a nitride layer is formed by a first oxynitriding process. The first gate oxide film is selectively removed from a thinner film part area of the substrate. A second gate oxide film forming process forms a second gate oxide...

20060125028 - Mosfet device with localized stressor: A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress...

20060125027 - Nonvolatile flash memory with hfo2 nanocrystal: In the present invention, an Hf-silicate film with small nanocrystal of high density is grown through a Rapidly Temperature Annealing (RTA) process, where its manufacturing procedure is simple and can be integrated into modern IC manufacturing procedure to be applied in related industries of memory and semiconductor, such as flash...

20060125026 - Semiconductor device with high-k dielectric layer: A semiconductor device comprises a substrate including isolation regions and active regions, and a high-k dielectric layer proximate the substrate. The high-k dielectric layer comprises a mixture formed by annealing at least one high-k material and at least one metal to oxidize the metal. The semiconductor device comprises a gate...

20060125030 - Hybrid ald-cvd of prxoy/zro2 films as gate dielectrics: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of praseodymium oxide (PrXOY) and zirconium oxide (ZrOZ) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. The nanolaminate layered dielectric...

20060125032 - Micro electro mechanical system apparatus: A MEMS (micro electro mechanical system) apparatus is equipped with a light-emitting circuit, having a light-emitting device, to emit light; a light-receiving circuit having a series circuit of series-connected light-receiving devices that receive the emitted light to generate a voltage; and a MEMS assembly driven by the generated voltage....

20060125031 - Microelectromechanical device having a common ground plane layer and a set of contact teeth and method for making aspects thereof: The present invention relates to MEM switches. More specifically, the present invention relates to a system and method for making MEM switches having a common ground plane. One method for making MEM switches includes: patterning a common ground plane layer on a substrate; forming a dielectric layer on the common...

20060125033 - Sensor platform using a non-horizontally oriented nanotube element: Sensor platforms and methods of making them are described. A platform having a non-horizontally oriented sensor element comprising one or more nanostructures such as nanotubes is described. Under certain embodiments, a sensor element has or is made to have an affinity for an analyte. Under certain embodiments, such a sensor...

20060125034 - Magnetoresistant device and magnetic memory device further comments: A magnetoresistive device has an arrangement including a pair of ferromagnetic layers (magnetization fixed layer 5 and magnetization free layer 7) being opposed to each other through an intermediate layer 6 to obtain variations in magnetoresistance by an electric current flowing in the direction perpendicular to the film plane. This...

20060125035 - Pinned photodiode fabricated with shallow trench isolation: A method and system is disclosed for reducing or eliminating leakage between a pinned photodiode and shallow trench isolation structure fabricated therewith while optimizing the sensitivity of the photodiode. Provided is a system with an N+ region implanted in a P-type substrate; a P-type well separating the N+ region from...

20060125037 - Semiconductor device and method for manufacturing the same: The semiconductor device according to this invention is chacterized by a package structure of a semiconductor substrate 100 equipped with a photoelectric converting portion, wherein a light-shading means 104 is arranged in an area corresponding to at least the photoelectric converting portion on the side of the rear surface of...

20060125036 - Solid-state imaging device and method for manufacturing solid-state imaging device: A plurality of optical sensors (4) are arranged in a surface region of a semiconductor substrate (6) in a matrix pattern, and electric charge generated by the optical sensors (4) is transferred by first and second transfer electrodes (12 and 14) embedded under the optical sensors (4). The semiconductor substrate...

20060125038 - Back-illuminated type solid-state imaging device: The back-illuminated type solid-state imaging device includes a structure 34 having a semiconductor film 33 on a semiconductor substrate 31 through an insulation film 32, in which a photoelectric conversion element PD that constitutes a pixel is formed in the semiconductor substrate 31, at least part of transistors 15, 16,...

20060125040 - Cobalt silicide schottky diode on isolated well: A Schottky diode is formed on an isolated well (e.g., a P-well formed in a buried N-well), and utilizes cobalt silicide (CoSi2) structures respectively formed on heavily doped and lightly doped regions of the isolated well to provide the Schottky barrier and backside (ohmic) contact structures of the Schottky diode....

20060125039 - Low parasitic capacitance schottky diode: A low parasitic capacitance Schottky diode including a lightly doped polycrystalline silicon island that is formed on a shallow trench isolation (STI) pad such that the polycrystalline silicon island is entirely isolated from an underlying silicon substrate by the STI pad. The resulting structure reduces leakage and capacitive coupling to...

20060125041 - Transistor using impact ionization and method of manufacturing the same: A transistor using impact ionization and a method of manufacturing the same are provided. A gate dielectric layer, a gate, and first and second spacers are formed on a semiconductor substrate. A first impurity layer is formed spaced from the first spacer and a second impurity layer is formed expanding...

20060125042 - Electronic component and panel for producing the same: One embodiment of the invention relates to an electronic component having stacked semiconductor chips, and to a panel for production of the component. In one case, the stack has a flat conductor structure with a chip island on which a stacked semiconductor chip is arranged, while a first semiconductor chip...

20060125044 - Methods of reducing floating body effect: Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a preferred embodiment, a word line is recessed into...

20060125043 - Trench insulation structures and methods: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited...

20060125045 - Process of fabricating semiconductor devices with isolation and sinker regions containing trenches filled with conductive material: A semiconductor structure includes a trench formed in an epitaxial layer that overlies a semiconductor substrate, the sides of the trench being lined with an oxide layer. The trench is filled with a conductive material, e.g., a metal or heavily-doped polysilicon, and the conductive is in contact with the substrate...

20060125046 - Integrated inductor and method of fabricating the same: Provided are an integrated inductor and a method of manufacturing the same. The integrated inductor includes: a silicon on insulator (SOI) wafer on which a substrate, an oxide layer, and an active layer are stacked; a first metal interconnection formed in a predetermined region on the SOI wafer; a second...

20060125047 - Interposer including at least one passive element at least partially defined by a recess formed therein, system including same, and wafer-scale interposer: An interposer for assembly with a semiconductor die and methods of manufacture are disclosed. The interposer may include at least one passive element at least partially defined by at least one recess formed in at least one dielectric layer of the interposer. The at least one recess may have dimensions...

20060125048 - Integrated semiconductor device and method of manufacturing the same: An integrated semiconductor device comprising an analog integrated circuit or mixed signal integrated circuit having a capacitor, wherein the dielectric film of the capacitor is a laminated film consisting of a first dielectric film essentially composed of aluminum oxide and a second dielectric film essentially composed of crystallized niobium oxide....

20060125049 - Resistive structure integrated in a semiconductor substrate: A resistive structure integrated in a semiconductor substrate and having a suitably doped polysilicon region that is completely surrounded by a dielectric region so that the resistive structure is isolated electrically from other components jointly integrated in the semiconductor substrate....

20060125050 - Semiconductor device manufacturing methods: Methods of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region are provided. An illustrated method includes forming, on a substrate, a gate pattern for a high-voltage device and a low-voltage device; implanting ions into opposite sides of the gate pattern, to form a lightly...

20060125051 - Method for metal gate structure for mos devices: A method for forming a gate structure includes forming a gate dielectric layer on a semiconductor substrate and a metal gate conductor on the gate dielectric layer. A cap layer is formed on the metal gate conductor. The method provides for patterning the cap layer, the gate metal layer and...

20060125052 - Lateral tunable capacitor and high frequency tunable device having the same: A lateral type tunable capacitor and a high frequency tunable device having the same are provided. The high frequency tunable device includes substrate; a signal line formed on the substrate; a plurality of tunable capacitors aligned on both sides of the signal line along the longitudinal direction of the signal...

20060125053 - Zener diode and methods for fabricating and packaging same: A zener diode and methods for fabricating and packaging same are disclosed, whereby contact hole forming process exposing a diffusion layer is removed to enable to simplify the fabricating process, and the diffusion length not contacting the electrode line is determined by the crosswise length toward which the impurity is...

20060125054 - Electrostatic discharge protection circuit using zener triggered silicon controlled rectifier: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). The ESD protection circuit using an SCR includes: a semiconductor substrate including a first well and a second well; first and second heavily doped regions disposed in...

20060125055 - Voltage-controlled bidirectional switch: A voltage-controlled vertical bi-directional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well...

20060125056 - Formation of nanowhiskers on a substrate of dissimilar material: A method for forming a nanowhisker of, e.g., a III-V semiconductor material on a silicon substrate, comprises: preparing a surface of the silicon substrate with measures including passivating the substrate surface by HF etching, so that the substrate surface is essentially atomically flat. Catalytic particles on the substrate surface are...

20060125057 - Method for the production of a composite sicoi-type substrate comprising an epitaxy stage: m

20060125058 - Semiconductor circuitry constructions: The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first semiconductor substrate has a semiconductive material projection extending therefrom, and the second semiconductor substrate has...

20060125060 - Semiconductor chip, and manufacturing method and application of the chip: The present invention provides a semiconductor chip that provides a semiconductor device with high reliability and low leak current, and a method of manufacturing such a semiconductor chip, and more specifically, provides a semiconductor chip comprising memory portions and a peripheral circuit portion, where the memory portions and the peripheral...

20060125059 - Semiconductor wafer with protection structure against damage during a die separation process: A semiconductor wafer includes one or more dies, each of which has a boundary surrounding an integrated circuitry for separating one from another. One or more pattern units are disposed adjacent to the die for monitoring a fabrication process thereof. A protection structure is disposed between the die and the...

20060125061 - Board or substrate for an organic electronic device and use thereof: The invention relates to a circuit board or a substrate for an electronic device, which is inexpensive to produce and easy to integrate in the production process for organic electronics. To this end, the novel intelligent circuit board comprises at least one active electronic component, for example an electrical circuit,...

20060125063 - Electrical-interference-isolated transistor structure: A transistor structure includes at least one chip; a packaging insulating layer, a first adhesive layer, a conducting layer, and a second adhesive layer sequentially provided on one side of the chip having electrical contacts thereon, so that the conducting layer is bonded between the first and the second adhesive...

20060125064 - Semiconductor device and a method of manufacturing the same: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a...

20060125062 - Semiconductor package having improved adhesion and solderability: A leadframe with a base metal structure (for example, copper) and first and second surfaces. A first metal layer, which is adhesive to polymeric materials such as molding compounds, is adherent to the first leadframe surface. The second leadframe surface is covered by a second metal layer for affinity to...

20060125065 - Multi-part lead frame with dissimilar materials: A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame semiconductor device assembly which utilizes equipment designed...

20060125066 - Self-adhesive frame applied in package of field emission display, the manufacturing method for the same and the package method by the same: A self-adhesive frame is applied in package of field emission display, the manufacturing method for the same and the package method by the same being also discussed in the specification. The self-adhesive frame can be designed as an independent component and suitable to be manufactured independently. The cathode plate and...

20060125067 - Flex circuit constructions for high capacity circuit module systems and methods: Provided circuit modules employ flexible circuitry populated with integrated circuitry (ICs). The flex circuitry is disposed about a rigid substrate. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. A strain relief portion of the flex circuitry has preferably fewer layers than the portion...

20060125069 - Integrated circuit with stacked-die configuration utilizing substrate conduction: An integrated circuit comprises a plurality of integrated circuit die arranged in a stack, with a given die other than a top die of the stack carrying current for itself and at least one additional die of the stack via substrate conduction. In one arrangement, each of the die other...

20060125071 - Memory module and method of mounting memory device on pcb for memory module: A memory module and a method of mounting memory devices on a PCB to form the memory module substantially reduce unnecessary routing space and improve signal attenuation characteristics. In the method of mounting and sequentially connecting at least two memory devices on a printed circuit board(PCB) having an axis of...

20060125068 - Photo-detector and related methods: An apparatus comprising at least one multilayer wafer includes a device layer adjacent to a barrier layer, and the device layer includes at least two photoconductive regions separated by an etched channel extending through the device layer. In some instances the apparatus may be an accelerometer having two photodiodes formed...

20060125072 - Semiconductor device having laminated semiconductor constructions and a manufacturing method thereof: A semiconductor device comprises a plurality of semiconductor constructions being mutually laminated each having a semiconductor substrate and a plurality of external connection electrodes arranged on the semiconductor substrate respectively, an insulating layer formed around the peripheries of the semiconductor constructions, an upper layer insulating film formed on an uppermost...

20060125070 - Semiconductor package, manufacturing method thereof and ic chip: A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bonding pads may...

20060125076 - Circuit boards, electronic devices, and methods of manufacturing thereof: A circuit board 3 includes a ceramic substrate 6 with an internal layer circuit 7 therein. The internal layer circuit 7 is used to electroplate a plurality of component electrodes 8, a plurality of terminal electrodes 9, and a loop electrode 10 that surrounds the component electrodes 8 on surfaces...

20060125075 - Flash preventing substrate and method for fabricating the same: A flash preventing substrate and a method for fabricating the same are proposed. A core defined with a plurality of substrate units is prepared. A circuit patterning process is performed to form circuit structures on the core corresponding to the substrate units, plating buses between the adjacent substrate units and...

20060125073 - Lead frame for semiconductor device: Lead frames of a Pd-PPF structure for use in a semiconductor device comprising inner leads and outer leads, wherein a whole surface of the substrate constituting the lead frame or at least the outer leads has a composite plated layer, and the composite plated layer comprises an underlayer consisting of...

20060125074 - Method of connecting internal silver traces to external gold to produce a gold external side metal for an ltcc package: A method of connecting internal silver traces to external gold to produce a gold external side metal for a low-temperature co-fired ceramic package includes the deposition of a ruthenium dioxide cermet barrier layer between layers of gold and silver. An LTCC package constructed in accord with the inventive method has...

20060125077 - Semiconductor device: A semiconductor device is provided that includes a semiconductor chip, a substrate on which the semiconductor chip is mounted, a mounting terminal that is arranged on a first side of the substrate, and a testing terminal that is arranged on a second side of the substrate which second side is...

20060125078 - Semiconductor device: A semiconductor device is provided which includes a semiconductor element having power pads for supplying a power potential, ground pads for supplying a ground potential, and signal pads for inputting and outputting a signal, all of which are formed on one main surface thereof. Power bumps for outside connection are...

20060125079 - High density package interconnect wire bond strip line and method therefor: In an example embodiment, an integrated circuit (105) is placed in a package (100), the package having signal pad connections, power connections, and ground connections. A lower strip line (110) is bonded by coupling a first ground connection (110a) of the IC (105) to a first package substrate ground connection...

20060125080 - Semiconductor package structure and method for fabricating the same: A semiconductor package structure and a method for fabricating the same are proposed. A carrier having at least one cavity is provided. At least one semiconductor chip having electrode pads is mounted in the cavity. A dielectric layer is applied on the carrier and the chip, and has vias for...

20060125081 - Printed circuit board: In a printed circuit board on which a first conductor pattern, a second conductor pattern of smaller area than the first conductor pattern and electronic components are mounted, a gap between a first through-hole connected to the first conductor pattern and a first lead pin inserted therein is defined to...

20060125082 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a base plate made of a material including at least a thermosetting resin, and having an opening, a vertical conductor filled and provided in the opening of the base plate, at least one semiconductor construct having a semiconductor substrate and a plurality of external connection electrodes...

20060125083 - Multi-layer interconnection circuit module and manufacturing method thereof: The present invention is directed to a multi-layer interconnection circuit module in which plural unit wiring layers are interlayer-connected to each other through a large number of via holes so that they are laminated and formed, wherein respective unit wiring layers (8) to (12) are adapted so that photo-lithographic processing...

20060125084 - Integration of micro-electro mechanical systems and active circuitry: A single integrated wafer package includes a micro-electro mechanical system (MEMS) wafer, an active device wafer, and a seal ring. The MEMS wafer has a first surface and includes at least one MEMS component on its first surface. The active device wafer has a first surface and includes an active...

20060125085 - Semiconductor device which prevents light from entering therein: A CSP type semiconductor device protects a circuit from the influences exerted by an external light on a circuit. In the CSP type semiconductor device, a light-shielding material, such as a silicone-based resin, an epoxy-based resin, or a metal, is deposited onto a side surface or a rear surface of...

20060125087 - Apparatus for effecting reliable heat transfer of bare die microelectronic device and method thereof: Apparatus and method include using a bare die microelectronic device; a heat sink assembly; a heat sink mounting assembly for mounting the heat sink assembly independently of the bare die microelectronic device; and, a force applying mechanism that compression loads, under controlled forces, a surface of the bare die into...

20060125086 - Modular heat sink decoupling capacitor array forming heat sink fins and power distribution interposer module: A modular heat sink decoupling capacitor array includes a plurality of modules, each defining parallel distributed decoupling plates, and each module forming a heat sink fin. Each module includes multiple spaced apart contacts for providing low inductance connections with an associated device. A power distribution interposer module is attached to...

20060125088 - Heat dissipating semiconductor package and fabrication method thereof: A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface...

20060125089 - Thermally enhanced package for an integrated circuit: A circuit assembly having an insulating base, a heat-conducting plate and a circuit containing die is disclosed. The die is in thermal contact with the heat-conducting plate, which is bonded to the insulating base. The insulating base includes heat-conducting channels that are in thermal contact with the heat-conducting plate. The...

20060125090 - Heat dissipation structure and method thereof: A semiconductor structure and method for dissipating heat away from a semiconductor device having a plurality of power lines is provided. The semiconductor structure includes a semiconductor substrate and a plurality of interconnect structures disposed on the substrate and in contact therewith and extending through the semiconductor device, the interconnect...

20060125091 - Connection structure of flexible wiring substrate and connection method using same: A wiring pattern having a plurality of terminal lands and leads independently respectively connected therewith is formed on one face of an insulator of a flexible wiring substrate. The insulator is provided with through-holes whereby the terminal lands are exposed on the other side. The terminal lands are electrically connected...

20060125092 - High density integrated circuit package architecture: An integrated circuit (IC) package includes a circuitry wafer having a substrate on which is carried an optical IC configured to emit an optical signal transversely to the substrate, the substrate having an optical signal path therethrough. The first optical IC is positioned for signal communication through the signal path....

20060125093 - Multi-chip module having bonding wires and method of fabricating the same: Provided herein are multi-chip modules (MCMs) having bonding wires and fabrication methods thereof. The multi-chip module includes a substrate and a plurality of chips sequentially stacked. At least one top chip, stacked above a lowest chip, has an insulating film that covers the backside thereof. Also, each of the stacked...

20060125094 - Solder interconnect on ic chip: A semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump. The bump is connected to the line and is adapted to be electrically connected to the line. A plane that is horizontal to an active surface of the semiconductor chip is defined....

20060125095 - Semiconductor device and manufacturing method thereof: A semiconductor device including a semiconductor substrate containing a plurality of electrode pads and a passivation film with an opening that exposes a central area of each of the electrode pads, and a bump electrically connected to each of the electrode pads, the bump being disposed to overlap the opening...

20060125096 - Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device: A method is provided to suppress detachment between semiconductor packages while preventing dislocation at the time of mounting a stacked semiconductor package on a motherboard. Semiconductor packages PK1 and PK2 are bonded to each other through protruding electrodes and resin is provided between the semiconductor packages PK1 and PK2. The...

20060125097 - Semiconductor apparatus: A semiconductor apparatus includes a printed circuit board, a peripheral type first semiconductor package which has a first group of ball electrodes arranged in a peripheral type first arrangement area and a first group of additional ball electrodes arranged inside the first arrangement area and which is arranged on a...

20060125098 - Transistor device having a delafossite material: A transistor device includes a channel of p-type substantially transparent delafossite material. Source and drain contacts are interfaced to the channel. Gate dielectric is between a gate contact and the channel....

20060125099 - Vapor deposition of tungsten nitride: Tungsten nitride films were deposited on heated substrates by the reaction of vapors of tungsten bis(alkylimide)bis(dialkylamide) and a Lewis base or a hydrogen plasma. For example, vapors of tungsten bis(tert-butylimide)bis(dimethylamide) and ammonia gas supplied in alternate doses to surfaces heated to 300° C. produced coatings of tungsten nitride having very...

20060125100 - Method of manufacturing semiconductor device, and semiconductor device: A method of manufacturing a semiconductor device, comprising a first step of forming a layer insulation film on a lower layer wiring provided on a substrate and forming a connection hole in the layer insulation film, a second step of forming an alloy layer composed of a first metallic material...

20060125101 - Semiconductor device, semiconductor substrate and fabrication process of a semiconductor device: A semiconductor device includes a first insulation layer including a first conductor pattern, a second insulation layer formed on the first insulation layer and including a second conductor pattern, and a third conductor pattern formed on the second insulation layer, wherein there is formed a first alignment mark part in...

20060125102 - Back end of line integration scheme: A semiconductor structure comprises: a first inter-layer dielectric (ILD) over a substrate; a first metal layer; a plurality of second ILDs over the first ILD; and a plurality of second metal layers, each of the second metal layers is over one of the second ILDs. The first ILD is not...

20060125103 - Information handling system: An information handling system which includes as part thereof a circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized...

20060125104 - Method for manufacturing a semiconductor protection element and a semiconductor device: A semiconductor protection element is provided in which no heat generation occurs in a concentrated manner, in a region having a high resistance value even when electrostatic discharge (ESD) is applied, without an increase in an area of the semiconductor device. The semiconductor protection element is made up of an...

20060125105 - Zinc-aluminum solder alloy: A high melting point solder alloy superior in oxidation resistance, in particular a solder alloy provided with both a high oxidation resistance and high melting point suitable for filling fine through holes of tens of microns in diameter and high aspect ratios and forming through hole filling materials, comprising a...

20060125106 - Method for fabricating semiconductor components with conductive spring contacts: An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for...

20060125107 - Test system for semiconductor components having conductive spring contacts: An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for...

20060125108 - Method of producing a microelectronic electrode structure, and microelectronic electrode structure: In a method for producing a microelectronic electrode structure a first wiring plane is prepared, an insulating region on the first wiring plane is provided, a through-hole in the insulating region is formed, a ring electrode in the through-hole is formed, and a second wiring plane is formed on the...

20060125109 - Methods of manufacture of a via structure comprising a plurality of conductive elements and methods of forming multichip modules including such via structures: A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hole may be substantially filled with dielectric...

20060125112 - Apparatus and method for manufacturing semiconductor device: An apparatus for manufacturing a semiconductor device comprises a planarization mechanism section which pressurizes a top of a bump that is provided onto at least one of a substrate and a semiconductor chip and makes the top of the bump flat, and a bonding mechanism section which bonds the substrate...

20060125114 - Electrical connection through nonmetal: A low resistance path extends from a first region of a semiconductor substrate to a second region thereof. The low resistance path is produced by depositing a metal such as aluminum on the surface of the substrate and then directing a laser beam onto the metal causing the metal and...

20060125111 - Flip chip device: A flip chip device made using LCD-COG (liquid crystal display-chip on glass) technique. The flip chip device comprises a substrate, a plurality of chips having surfaces with a plurality of compliant bumps thereon. The compliant bumps are centrally disposed in the center of the chips for electrically connecting the chips...

20060125113 - Flip chip package with anti-floating structure: A flip chip package with an anti-floating structure comprises a leadframe, a flip chip, and a plurality of solders. The leadframe comprises a plurality of leads and a fastening part. At least one locking hole is formed on an upper surface of the fastening part. The flip chip comprises an...

20060125110 - Method for solder bumping, and solder-bumping structures produced thereby: A method for solder bumping provides a substrate and forms a film on the substrate. The film has openings therethrough. A stencil is aligned on the film. The stencil has openings therethrough over the openings through the film. Solder paste is printed onto the substrate and into the openings through...

20060125115 - Wafer level ball grid array: A manufacturing technique that involves embedding one or more semiconductor die into a support substrate and forming conductive traces that lead from die contact pads to redistributed contact pads on the support substrate. Active surfaces of the dice and a working surface of the support substrate are substantially coplanar and...

20060125116 - Multi-chip module: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer...

20060125117 - Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is...

20060125118 - Semiconductor device having a bonding pad structure including an annular contact: A bonding pad structure in a semiconductor device includes a contact pad connected to an interconnect, a bonding pad overlying the contact pad with an intervention of an insulating film and exposed from an opening of a passivation film, and an annular contact disposed between the contact pad and the...

20060125119 - B-stageable underfill encapsulant and method for its application: A curable underfill encapsulant composition that is applied directly onto semiconductor wafers before the wafers are diced into individual chips. The composition comprises a thermally curable resin system comprising an epoxy resin, a phenol-containing compound such as phenol or phenolic resin, a solvent, an imidazole phosphate salt catalyst, inorganic fillers,...

20060125120 - Method of fabricating polycrystalline silicon: A method of fabricating polycrystalline silicon according to an embodiment includes forming a semiconductor layer of amorphous silicon on a substrate having a first region and a second region surrounding the first region; forming a plurality of flat align keys in the second region using a first mask; forming a...

20060125121 - Capacitor-less 1t-dram cell with schottky source and drain: A tunneling injection based Schottky source/drain memory cell comprising: a first semiconductor layer with a first conductivity type overlying an insulating layer, wherein the first semiconductor acts as a body region; a gate dielectric overlying the semiconductor layer; a gate electrode overlying the gate dielectric; a pair of spacers on...

20060125122 - Embedded non-volatile memory cell with charge-trapping sidewall spacers: An IC includes both “volatile” CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cells and the FETs are made up of a spacer material with local charge storage...

20060125123 - Dram layout with vertical fets and method of formation: DRAM cell arrays having a cell area of less than about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally...

20060113520 - Semiconductor integrated circuit device and method of manufacturing the same: Disclosed herein is a phase change memory semiconductor integrated circuit device using a chalcogenide film that solves a problem that the operation temperature capable of ensuring long time memory retention is low due to low phase change temperature is and, at the same time, a problem that power consumption of...

20060113521 - Chalcogenide memory having a small active region: A chalcogenide phase change memory cell has a substrate with a conductor line. The conductor line has a contact end. An insulating layer is located over the substrate and conductor line. An aperture is located in the insulating layer. The aperture extends to the substrate. A memory material is conformally...

20060113522 - Strained silicon fin structure: Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The...

20060113529 - Flat panel display: A flat panel display includes a pixel electrode, an organic emission layer, an opposite electrode, a phase shift layer and a reflecting layer disposed on a substrate. The phase shift layer and the reflecting layer are stacked on the opposite electrode to destructively interfere with reflected external light to realize...

20060113530 - Multifunctional linker molecules for tuning electronic charge transport through organic-inorganic composite structures and uses thereof: in which X is the central body of the molecule, FUNC1 and FUNC2 independently of each other are molecular groups introducing a dipole moment and/or capable of forming intermolecular and/or intramolecular hydrogen bonding networks, and CON1 and CON2 independently of each other are molecular groups binding to nanostructured units comprising...

20060113525 - Organic electroluminescent device:

20060113528 - Organic light-emitting device:

20060113523 - Organic semiconductor device: An organic semiconductor device that can be driven stably at low gate voltage is provided. The organic semiconductor device of the present invention is characterized by having a silsesquioxane skeleton in an insulating portion....

20060113526 - Organic semiconductor structure, manufacturing method of the same, and organic semiconductor device: A manufacturing method of an organic semiconductor device wherein an organic semiconductor layer being, a structural component of an organic semiconductor device is formed continuously with uniform performance over a sufficiently large area. The organic semiconductor structure comprises an organic semiconductor layer formed from an organic semiconductor material having a...

20060113524 - Polymer-based transistor devices, methods, and systems: One aspect of the present invention relates to a semiconductor transistor device with an annular gate surrounding, at least in part, a channel that conducts current between a first and second source/drain. Another aspect of the present invention relates to a semiconductor transistor device having an annular gate and containing...

20060113531 - Semiconductor component and method for the production thereof: An embodiment of the invention provides a semiconductor component and method of forming thereof. The component comprises a dielectric layer over a substrate, and a layer of an organic compound covalently bonded to the dielectric layer. The organic compound has a chemical functionality selected from the group consisting essentially of...

20060113527 - Star-shaped oligothiophene-arylene derivatives and organic thin film transistors using the same: A star-shaped oligothiophene-arylene derivative in which an oligothiophene having p-type semiconductor characteristics is bonded to an arylene having n-type semiconductor characteristics positioned in the central moiety of the molecule and forms a star shape with the arylene, thereby simultaneously exhibiting both p-type and n-type semiconductor characteristics. Further, an organic thin...

20060113532 - Multidirectional leakage path test structure: A test structure for testing a multidirectional current leakage path. A first doped region of a first conductivity is in the first well of the first conductivity in a substrate, in which the first doped region has a dopant concentration higher than the first well has. A first contact is...

20060113535 - Probe look ahead: testing parts not currently under a probehead: A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into dies on the substrate that are not currently...

20060113533 - Semiconductor device and layout design method for the same: In layout design of a semiconductor device including a device forming region formed on a substrate; an isolation region formed on the semiconductor substrate so as to surround the device forming region; a gate electrode formed on the device forming region; and a gate interconnect connected to the gate electrode...

20060113534 - Test structure of semiconductor device: A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed...

20060113536 - Display: An active matrix display comprising a light control device and a field effect transistor for driving the light control device. The active layer of the field effect transistor comprises an amorphous....

20060113537 - Electronic unit integrated into a flexible polymer body: A peel and stick electronic system comprises a silicone body, and at least one electronic unit operatively connected to the silicone body. The electronic system is produce by providing a silicone layer on a substrate, providing a metal layer on the silicone layer, and providing at least one electronic unit...

20060113539 - Field effect transistor: A novel field-effect transistor is provided which employs an amorphous oxide. In an embodiment of the present invention, the transistor comprises an amorphous oxide layer containing electron carrier at a concentration less than 1×10−18/cm3, and the gate-insulating layer is comprised of a first layer being in contact with the amorphous...

20060113541 - Process for fabricating semiconductor device: A process for fabricating a semiconductor device comprising the step of, after patterning the silicon film crystallized to a low degree by thermally annealing an amorphous silicon film into an island by etching, irradiating an intense light of a visible light or a near infrared radiation to effect a short-period...

20060113540 - Reflective active matrix liquid crystal display and apparatus: A liquid crystal display apparatus has a transparent substrate having a transparent common electrode formed thereon; an active matrix substrate having pixels with reflective pixel electrodes, the pixels being formed in column and row directions on the matrix substrate in a matrix fashion, each pixel having a switching transistor with...

20060113538 - Thin film transistor substrate and fabricating method thereof: A thin film transistor substrate and a fabricating method thereof wherein a contacting size between an electrode and an active layer can be reduced to provide a small and light panel. In the thin film transistor substrate, a conductive layer is formed on the substrate. A first insulating layer for...

20060113542 - Method for forming low defect density alloy graded layers and structure containing such layers: A structure and method of forming same, comprising a low threading density alloy graded layer, deposited according to a deposition temperature profile in correspondence with increasing alloy composition. In one embodiment, a first substantially relaxed alloy graded layer is deposited while varying a deposition temperature according to a first temperature...

20060113543 - Semiconductor device and method of fabricating the same: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having...

20060113544 - Semiconductor light-emitting device, method for manufacturing same, and linear light source: A semiconductor light-emitting device comprises an elongated light transmitter 2; a pair of metallic heat sinks 4 disposed at both ends 2a of light transmitter 2 in a perpendicular relation to light transmitter 2. A linear light source comprises an elongated light transmitter 2 having an irradiation surface 2e; semiconductor...

20060113546 - Diamond composite heat spreaders having low thermal mismatch stress and associated methods: A diamond composite heat spreader having a low thermal mismatch stress can improve reliability and cost of diamond-based heat spreaders. A diamond composite heat spreader can have a thermally conductive base and a diamond film in thermal contact with the thermally conductive base. The diamond film and the thermally conductive...

20060113547 - Methods of fabricating memory devices including fuses and load resistors in a peripheral circuit region: Methods of fabricating a semiconductor memory device include forming a plurality of memory cells in a cell region of a semiconductor substrate. An insulating layer is formed on the plurality of memory cells in the cell region and on a peripheral circuit region of the substrate, and a bit line...

20060113545 - Wide bandgap semiconductor layers on sod structures: Multi-layered structures containing GaN on SOD (silicon/diamond/silicon) substrates are described. The unique substrate/epilayer combination can provide electronic materials suitable for high-power and opto-electronic devices without commonly observed limitations due to excess heat during device operation. The resulting devices have built-in thermal heat spreading capability that result in better performance and...

20060113548 - Light emitting diode: A light emitting diode is provided, wherein a first semiconductor layer is disposed on a substrate, and a second semiconductor layer is disposed on the first semiconductor layer. The first and the second semiconductor layers are doped with different type dopants. In addition, a second electrode is disposed on the...

20060113550 - Light emitting diode and fabrication method thereof: A light emitting diode (LED) and a method for fabricating the same, capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer...

20060113549 - Light-emitting device: An object of the present invention is to provide a new light-emitting device with the use of an amorphous oxide. The light-emitting device has a light-emitting layer existing between first and second electrodes and a field effect transistor, of which the active layer is an amorphous....

20060113551 - Pixel circuit and light emitting display: A light emitting display includes a plurality of scan lines, a plurality of data lines, a plurality of first light emitting control lines, a plurality of second light emitting controls lines, a plurality of third light emitting control lines, and a plurality of pixels. Each of the pixels includes at...

20060113552 - Silicon optoelectronic device manufacturing method and silicon optoelectronic device manufactured by thereof and image input and/or output apparatus having the same: A method of manufacturing a silicon optoelectronic device, a silicon optoelectronic device manufactured by the method and an image input and/or output apparatus having the silicon optoelectronic device are provided. The method includes: preparing an n-type or a p-type silicon-based substrate; forming a polysilicon having a predetermined depth at one...

20060113553 - White light emitting phosphor blend for led devices: There is provided a white light illumination system including a radiation source, a first luminescent material having a peak emission wavelength of about 570 to about 620 nm, and a second luminescent material having a peak emission wavelength of about 480 to about 500 nm, which is different from the...

20060113554 - Method for producing a vertically emitting laser: The invention is directed to a vertically emitting laser and a method of manufacturing such a laser having a current aperture and a semiconductor relief. The semiconductor relief and the current aperture are defined in the same processing operation, thereby causing the semiconductor relief and the current aperture to be...

20060113555 - Light emitting diode chip with large heat dispensing and illuminating area: A light emitting diode chip has a large area of electricity conducting material applied to each of the P pole and the N pole and the etching process does not reduce the illuminating area so that the areas of illumination and reflection are increased and the efficiency for dispensing heat...

20060113556 - Method and apparatus for calibrating a metrology tool: A method and apparatus for calibrating a metrology tool are disclosed. The apparatus includes a substrate having at least one calibration site formed thereon. The calibration site includes a pattern of cells that have at least one feature disposed in a surface of the substrate. The feature provided for measurement...

20060113557 - Nanophotovoltaic devices: The present invention provides nanophotovoltaic devices having sizes in a range of about 50 nm to about 5 microns, and method of their fabrication. In some embodiments, the nanophotovoltaic device includes a semiconductor core, e.g., formed of silicon, sandwiched between two metallic layers, one of which forms a Schottky barrier...

20060113558 - Notched compound semiconductor wafer: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the...

20060113559 - Notched compound semiconductor wafer: There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the...

20060113561 - Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors: A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts...

20060113562 - Semiconductor power module having an electrically insulating heat sink and method of manufacturing the same: A semiconductor power module includes a lead frame having a first portion at a first level, a second portion surrounding the first portion at a second level, and a plurality of terminals connected to the second portion. The semiconductor power module further includes a power circuit mounted on a first...

20060113563 - Compound semiconductor epitaxial substrate and method for manufacturing the same: In a compound semiconductor epitaxial substrate used for a strain channel high electron mobility field effect transistor which comprises an InGaAs layer as a channel layer 9 and AlGaAs layers containing n-type impurities as electron supplying layers 6 and 12, the channel layer 9 has an electron mobility at room...

20060113564 - Heterostructure with rear-face donor doping: The present invention relates to a field effect transistor having heterostructure with a buffer layer or substrate. A channel is arranged on the buffer layer or on the substrate, and a capping layer is arranged on the channel. The channel consists of a piezopolar material and either the region around...

20060113565 - Electric elements and circuits utilizing amorphous oxides: Semiconductor devices and circuits with use of transparent oxide film are provided. The semiconductor device having a P-type region and an N-type region, wherein amorphous oxides with electron carrier concentration less than 1018/cm3 is used for the N-type region....

20060113566 - Structures and methods for fabricating vertically integrated hbt-fet device: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating...

20060113567 - Semiconductor integrated circuit and method of producing same: A semiconductor integrated circuit able to repair a defect of a circuit cell without greatly changing interconnects, that is, a semiconductor integrated circuit comprising a plurality of circuit cells aligned in a matrix and groups of interconnects connecting at least a part of the plurality of circuit cells other than...

20060113568 - Structure and method of applying stresses to pfet and nfet transistor channels for improved performance: A semiconductor device structure is provided which includes a first semiconductor device; a second semiconductor device; and a unitary stressed film disposed over both the first and second semiconductor devices. The stressed film has a first portion overlying the first semiconductor device, the first portion imparting a first magnitude compressive...

20060113569 - Control of threshold voltage in organic field effect transistors: A field effect transistor (FET) includes a substrate, and a gate layer formed on the substrate. An oxygen plasmarized polymeric gate dielectric is formed on the gate layer so as to increase the threshold voltage of the OFET. A semiconductor layer is formed on the oxygen plasmarized polymeric gate dielectric....

20060113570 - Implanting carbon to form p-type source drain extensions: The use of a carbon implant, in addition to the conventional fluorine implant, may significantly reduce the transient enhanced diffusion in P-type source drain extension regions. As a result, resistivity may be reduced, and dopant density may be increased, increasing current drive in some embodiments....

20060113571 - Semiconductor structure for isolating integrated circuits of various operation voltages: A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor substrate. The buried isolation layer interfaces with the isolation ring, thereby isolating...

20060113572 - Solid state imaging module: A CCD solid state imaging module comprises a CCD area sensor, a substrate bias voltage setting device formed on said CCD area sensor for outputting a voltage, and a substrate bias voltage outputting device formed on a chip other than said CCD area sensor for outputting a substrate bias voltage...

20060113573 - Phase change memory cell with transparent conducting oxide for electrode contact layer: The present invention provides a non-volatile phase change memory cell containing an electrode contact layer disposed between a metal electrode layer and a phase change material layer, the electrode contact layer being formed of a transparent conducting oxide-based material which has a high electric conductivity, a low thermal conductivity and...

20060113574 - Field effect transistor: On an SiC single crystal substrate, an electric field relaxation layer and a p− type buffer layer are formed. The electric field relaxation layer is formed between the p− type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p− type buffer layer,...

20060113575 - Storage electrode of a capacitor and a method of forming the same: In an embodiment, a storage electrode of a capacitor in a semiconductor device is resistant to inadvertent etching during its manufacturing processes. A method of forming the storage electrode of the capacitor is described. The storage electrode of the capacitor may include a first metal layer electrically connected with a...

20060113576 - Sacrificial self-aligned interconnect structure: A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A method for making the interconnect structure...

20060113577 - Semiconductor device: The leakage current generated due to the extension of the depleted layer to the end of the chip is reduced. In MOSFET 100, the depths of the trenches 112 in the gate pad portion 50 and the circumference portion 70 are larger than the depths of the trenches 111 in...

20060113578 - Metal-insulator-metal capacitors with a chemical barrier layer in a lower electrode and methods of fabricating the same: A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first...

20060113579 - Semiconductor device comprising capacitor and method of fabricating the same: A semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in...

20060113580 - Capacitor for a semiconductor device and method of forming the same: In a capacitor having a high dielectric constant, the capacitor includes a cylindrical lower electrode, a dielectric layer and an upper electrode. A metal oxide layer is formed on inner, top and outer surfaces of the lower electrode as the dielectric layer. A first sub-electrode is formed on a surface...

20060113581 - Semiconductor memory device: A semiconductor memory device having a memory cell array in which plural memory transistors and plural memory call capacitors, which are components of memory cells, are arranged, comprises a first wiring layer formed on the memory cell array, and a second wiring layer formed above the first wiring layer, wherein...

20060113582 - Semiconductor device and method for manufacturing the same: A semiconductor device according to the present invention includes a cylindrical capacitor. An amorphous silicon layer serving as a lower electrode of the cylindrical capacitor has a two-layer structure including a lower high-concentration impurity sublayer and an upper low-concentration impurity sublayer. The blockage of a cylinder is prevented by etching...

20060113583 - Twin eeprom memory transistors with subsurface stepped floating gates: A memory array with memory cells arranged in rows and columns with each cell having twin EEPROMs featuring subsurface stepped floating gates for electric field concentration. The twin EEPROMs employ only a single layer of poly, one portion being a floating gate of each EEPROM and another portion being word...

20060113584 - Manufacturing method of a semiconductor device: The first polysilicon film is formed on the semiconductor substrate with the gate insulation film between them. The second silicon nitride film with the first opening is further formed and the first polysilicon film is etched using the second silicon nitride film as a mask. Then, the spacer film with...

20060113585 - Non-volatile electrically alterable memory cells for storing multiple data: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well....

20060113586 - Charge trapping dielectric structure for non-volatile memory: An integrated circuit structure comprises a bottom dielectric layer on a substrate, a middle dielectric layer, and a top dielectric layer. The middle dielectric layer has a top surface and a bottom surface, and comprises a plurality of materials. Respective concentration profiles for at least two of the plurality of...

20060113587 - Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array: A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of...

20060113590 - Method of forming a recess structure, recessed channel type transistor and method of manufacturing the recessed channel type transistor: An isolation layer having a first depth is formed from an upper face of a substrate. Source/drain regions including junctions are formed in the substrate. Each of the junctions has a second depth substantially smaller than the first depth. A first recess is formed in the substrate by a first...

20060113588 - Self-aligned trench-type dmos transistor structure and its manufacturing methods: The self-aligned trench-type DMOS transistor structure comprises a self-aligned source region being surrounded by a trench gate region. The self-aligned source region comprises a moderately-doped p-base diffusion region formed in a lightly-doped epitaxial semiconductor substrate, a self-aligned heavily-doped n+ source diffusion ring formed in a side surface portion of the...

20060113589 - Top drain fet with integrated body short: A top drain MOSgated device has its drain on the top of semiconductor die and its source on the bottom of the die substrate. Spaced parallel trenches extend from the die top surface through a drift region, a channel region and terminate on the substrate region. The bottoms of each...

20060113591 - High performance cmos devices and methods for making same: An integrated circuit having high performance CMOS devices with good short channel effects may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the...

20060113592 - Robust demos transistors and method for making the same: Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between...

20060113593 - Normally-off integrated jfet power switches in wide bandgap semiconductors and methods of making: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics...

20060113598 - Device and method for fabricating double-sided soi wafer scale package with optical through via connections: A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide...

20060113595 - Rectangular substrate dividing apparatus: A rectangular substrate dividing apparatus, which can divide a rectangular substrate in a smaller space, accommodate devices, formed as individual pieces by the division, into device cases, and pick up the devices reliably and efficiently from a protective tape affixed to the back of the rectangular substrate, is provided. This...

20060113597 - Semiconductor device and manufacturing method thereof: In a semiconductor device, typically an active matrix display device, the structure of TFTs arranged in the respective circuits are made suitable in accordance with the function of the circuit, and along with improving the operating characteristics and the reliability of the semiconductor device, the manufacturing cost is reduced and...

20060113596 - Single crystal substrate and method of fabricating the same: A high quality single crystal substrate and a method of fabricating the same are provided. The method of fabricating a single crystal substrate includes: forming an insulator on a substrate; forming a window in the insulator, the window exposing a portion of the substrate; forming an epitaxial growth silicon or...

20060113594 - Soi wafer and production method therefor: An SOI wafer in which a base wafer and a bond wafer respectively consisting of silicon single crystal are bonded via an oxide film, and then the bond wafer is thinned to form a silicon active layer, wherein the base wafer is formed of silicon single crystal grown by Czochralski...

20060113599 - Semiconductor devices having self-aligned bodies and methods of forming the same: A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the...

20060113600 - Body-biased pmos protection against electrostatic discharge: A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably PMOS) in a substrate 205 (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground 203. The embodiment...

20060113601 - Dual-gate metal-oxide semiconductor device: An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region...

20060113605 - Hybrid fin field-effect transistor structures and related methods: Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide....

20060113603 - Hybrid semiconductor-on-insulator structures and related methods: Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide....

20060113604 - Methods for reduced circuit area and improved gate length control: Semiconductor devices (102) are presented along with fabrication methods (202) therefor, in which a conductive contact structure (116b) is formed with a lower contact surface (116c) having a lateral contact dimension (152), where the contact structure (116b) is at least partially coupled with a contact landing surface of a polysilicon...

20060113602 - Mos circuit arrangement: A MOS circuit arrangement includes a silicon substrate, a semiconductor device, a field oxide layer, and a poly-protective layer. The silicon substrate has a conductive doping incorporated therein, wherein the semiconductor device is electrically connected with the silicon substrate. The field oxide layer is formed on the silicon substrate at...

20060113606 - Semiconductor integrated circuit device and method of manufacturing the same: The invention provides a CMOS integrated circuit capable of carrying out an operation at a comparatively high supply voltage, comprising a first MOS type transistor having a drain profile to come in contact with a gate through a low concentration region having an impurity concentration which is equal to or...

20060113608 - Electron-emitting device and method for manufacturing same: An electron-emitting device includes an emitter section composed of a dielectric material, a lower electrode disposed on the lower side of the emitter section, and an upper electrode disposed on the upper side of the emitter section so as to be opposed to the lower electrode with the emitter section...

20060113609 - Semiconductor device and method for manufacturing the same: A semiconductor device, comprising: a first transistor of a second electric conductivity type formed in a substrate including impurities of a first electric conductivity type; and a second transistor of the second electric conductivity type formed in the substrate, a source region of the second transistor being shared with a...

20060113610 - Nonvolatile memory device and method for manufacturing the same: A nonvolatile memory device and a method of manufacturing the same are provided. An insulation layer having a high etching rate as compared with a pad oxide layer is formed as a buffer layer between a first STI film formed as a lower part of semiconductor substrate and a second...

20060113612 - Insulated-gate semiconductor device and approach involving junction-induced intermediate region: Semiconductor device performance is improved via an insulated-gate PIN-type structure that is adapted to abruptly switch between conductance states by modulating an electric field in the intermediate (I) region. According to an example embodiment of the present invention, an insulated gate-type structure includes a body with first and second end...

20060113613 - Semiconductor device: A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first...

20060113615 - Methods of fabricating a semiconductor device having a barrier metal layer and devices formed thereby: A semiconductor device is formed by forming a gate region, including a gate oxide layer, and impurity diffusion regions on a semiconductor substrate, forming a barrier metal layer on the gate region and the impurity diffusion regions of the semiconductor substrate, forming a passivation layer at an interface between the...

20060113614 - Nonvolatile memory device and method including resistor and transistor: A nonvolatile memory device including one resistor and one transistor. The resistor may correspond to a resistance layer electrically connected to a first impurity region and a second impurity region of the transistor....

20060113616 - Selective spacer layer deposition method for forming spacers with different widths: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer...

20060113617 - Organic el display: A top emission structure color organic EL (electroluminescent) display in which there are bonded together a substrate, having thin film transistors formed thereon, and a transparent substrate, having color-converting filters formed thereon, with an overcoat layer for adjusting the gap between the two substrates and also for relieving stress formed...

20060113618 - Microelectronic device with anti-stiction coating: One embodiment of a microelectronic device includes a movable plate including a lower surface, a bump positioned on the lower surface, and an anti-stiction coating positioned only on the bump....

20060113619 - Magnetic random access memory with reference magnetic resistance and reading method thereof: A magnetic random access memory having reference magnetic resistance is provided. The memory includes at least one magnetic memory cell having an antiferromagnet layer, a pinned layer formed thereon, a tunnel barrier layer formed thereon, and a free layer formed thereon. The pinned layer and free layer are arranged orthogonally...

20060113620 - Image sensor microlens structures and methods of forming the same: In one aspect, an image sensor is provided which includes an interlayer insulation film formed over a substrate including a light receiving device, a color filter formed over the interlayer insulation film, a protection film having a flat top face formed over the interlayer insulation film and the color filter,...

20060113621 - Methods for aligning semiconductor fabrication molds and semiconductor substrates: The invention includes methods of forming patterns in low-k dielectric materials by contact lithography. In a particular application, a mold having a first pattern is pressed into a low-k dielectric material to form a second pattern within the material. The second pattern is substantially complementary to the first pattern. The...

20060113622 - A damascene copper wiring image sensor: An image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu...

20060113623 - Image sensor and method for forming the same: In an image sensor and a method for forming the same, the method comprises: preparing a substrate having a pixel array region and a peripheral circuit region; sequentially stacking a gate electrode layer and a mask layer on the substrate; patterning the gate electrode layer and the mask layer to...

20060113624 - Locos-based schottky barrier diode and its manufacturing methods: The LOCOS-based Schottky barrier diode of the present invention comprises a raised diffusion guard ring surrounded by an outer LOCOS field oxide layer, a recessed semiconductor substrate with or without a compensated diffusion layer surrounded by the raised diffusion guard ring, a metal silicide layer formed over a portion of...

20060113625 - Semiconductor device having improved power density: An MOS device is formed including a semiconductor layer of a first conductivity type, and source and drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The source and drain regions are spaced apart relative to one another. A...

20060113626 - Integrated circuit arrangement comprising isolating trenches and a field effect transistor, and associated production method: A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches....

20060113627 - High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage: A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high...

20060113628 - Designing and fabrication of a semiconductor device: Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface into first sub-regions; optimizing a coverage ratio of hard-to-polish regions in the first sub-regions to fall in a first predetermined range...

20060113629 - Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a crystalline bulk substrate: By direct bonding of two crystalline semiconductor layers of different crystallographic orientation and/or material composition and/or internal strain, bulk-like hybrid substrates may be formed, thereby providing the potential for forming semiconductor devices in accordance with a single transistor architecture on the hybrid substrate....

20060113632 - Semiconductor device and voltage regulator: A semiconductor device having a chip size package is disclosed. The chip size package comprises a semiconductor chip having at least a bonding pad, at least a terminal of said chip size package and a reroute trace formed between the bonding pad and the terminal on said chip size package....

20060113631 - Structure of embedded capacitors and fabrication method thereof: A new structure is provided to replace the existing common planar capacitor structure used in printed circuit boards. The common planar capacitor structure utilizes a single dielectric layer and embedded capacitors with different capacitances are achieved by adjusting the sizes of the embedded capacitors' conductive terminals. Since general applications usually...

20060113630 - Vertically-stacked plate interdigital capacitor structure: A vertically-stacked interdigital plate capacitor structure includes at least a first conductive plate, at least a second conductive plate parallel to the first conductive plate, and an inter-metal dielectric layer disposed between the first conductive plate and the second conductive plate. The first conductive plate includes a plurality of first...

20060113633 - Semiconductor memory device having a decoupling capacitor: A semiconductor memory device comprises a cell capacitor having a first buried contact connected with a semiconductor substrate of a cell region and a first storage node connected with the first buried contact, and a decoupling capacitor for reducing a coupling noise, having a plurality of second buried contacts formed...

20060113634 - Bipolar junction transistor with improved extrinsic base region and method of fabrication: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal....

20060113635 - Semiconductor member, manufacturing method thereof, and semiconductor device: An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain induction porous layer or a porous silicon layer and strain induction porous layer. An SiGe layer and strained silicon layer...

20060113636 - Novel pitch multiplication process: A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the patterned mask layer has a first line width. The first layer can then be etched to form a first plurality of sloped sidewalls. After...

20060113637 - Semiconductor device, semiconductor wafer, chip size package, and methods of manufacturing and inspection therefor: A semiconductor wafer is manufactured in such a way that a main surface of a semiconductor substrate is partitioned into a plurality of semiconductor element forming regions defined by scribing regions, wherein at least one pattern for measuring a width of a cut region and its positional shift is formed...

20060113638 - Light emitting diodes and the manufacture thereof: An array of highly efficient micro-LEDs (100) and a manufacturing process are described. Each micro-LED (100) is an integrated diode structure in a mesa (105), in which the mesa shape and the light-emitting region (104) are chosen for optimum efficiency. A single one of the micro-LEDs (100) comprises, on a...

20060113639 - Integrated circuit including silicon wafer with annealed glass paste: An integrated circuit (IC) package comprises an IC wafer and an annealed glass paste (AGP) layer that is arranged adjacent to the IC wafer. A molding material encapsulates at least part of the IC wafer and the AGP layer. The AGP layer is arranged on at least one side of...

20060113640 - Method and apparatus for polymer dielectric surface recovery by ion implantation: In one embodiment, the disclosure relates to a method and apparatus for surface recovery of a polymer insulation layer through implantation. The method includes providing a substrate having thereon a conductive pad and an insulation layer, optionally processing the conductive pad to remove oxide layer formed on the conductive pad...

20060113641 - Method of forming a field effect transistor having a stressed channel region: A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined compressive intrinsic stress having an absolute value of about 1 GPa or more. Due to this high intrinsic stress, the stressed layer exerts considerable...

20060113642 - Semiconductor device: A semiconductor device is disclosed that includes a substrate, electronic components that are arranged at an electronic components mounting area of the substrate, a ground terminal that is arranged within the electronic components mounting area, transfer molded resin that covers the electronic components while exposing the ground terminal, a shield...

20060113643 - Simplified multichip packaging and package design: A multichip integrated circuit apparatus includes first and second integrated circuit die mounted on opposite sides of a leadframe die paddle, with at least one of the integrated circuit die extending further toward the leads than does the die paddle. With this arrangement, the active circuit areas of both integrated...

20060113644 - Method for reducing harmonic distortion in comb drive devices: Methods of fabricating comb drive devices utilizing one or more sacrificial etch-buffers are disclosed. An illustrative fabrication method may include the steps of etching a pattern onto a wafer substrate defining one or more comb drive elements and sacrificial etch-buffers, liberating and removing one or more sacrificial etch-buffers prior to...

20060113645 - Microelectronic assemblies incorporating inductors: Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap...

20060113650 - Bond pad rerouting element and stacked semiconductor device assemblies including the rerouting element: A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive...

20060113646 - Connection arrangement for micro lead frame plastic packages: A connection arrangement for a micro lead frame plastic (MLP) package is provided that includes a paddle configured to be connected to a circuit board and a first ground pad and a second ground pad each connected to the paddle. The first and second ground pads together with the paddle...

20060113649 - Light transmissive cover, device provided with same and methods for manufacturing them: A light transmissive cover for a device comprising: a cover member of light transmissive material; and a junction member joined to the cover member, the junction member being a member used to be joined to the body of the device and having a light interrupting film on the inner surface...

20060113648 - Semiconductor chip and tab package having the same: A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and input pads formed in the central area...

20060113647 - Semiconductor device with improved heat dissipation: The invention relates to a semiconductor module with at least one semiconductor modular printed circuit board, which offers an improvement of the heat dissipation or a more efficient heat transport from the semiconductor chip, e.g. a memory chip or a logic chip, to the modular printed circuit board. An intermediate...

20060113651 - Ic card: An IC card that has improved endurance and demonstrates increased resistance to cracking of the case and peeling of the substrate when a bending force acts upon the IC card. First protrusions and second protrusions are formed in a recess for fitting a LGA. The second protrusions are connected to...

20060113652 - Battery mounted integrated circuit device: The present invention relates to a battery mounted integrated circuit device where an integrated circuit and a solid state battery are formed on the same substrate. In this battery mounted integrated circuit device, a first diffusion layer containing an N-type impurity is formed between a region of a semiconductor substrate...

20060113654 - Package of a semiconductor device with a flexible wiring substrate and method for the same: A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer on the bump, and a...

20060113653 - Stack package for high density integrated circuits: A stack package for a high density memory module includes at least one memory chip, an ASIC and an interposer, wherein the interposer comprises a first surface having contacts arranged in electrical communication with corresponding contacts on the ASIC and a second, substantially opposite surface including contacts arranged in electrical...

20060113655 - Semiconductor die attachment for high vacuum tubes: There is described-novel bonding and interconnecting techniques for use with semiconductor die for the creation of thermally efficient, physically compliant Ultra High Vacuum Tubes and the novel tube resulting therefrom....

20060113656 - Composite conductive film and semiconductor package using such film: A composite conductive film and a semiconductor package using such film are provided. The composite conductive film is formed of a polymer-matrix and a plurality of nano-sized conductive lines is provided. The composite conductive film has low resistance, to connect between a fine-pitch chip and a chip in a low...

20060113657 - Designated mosfet and driver design to achieve lowest parasitics in discrete circuits: Apparatus are described for a pair of MOSFET power transistors, a MOSFET driver, and an idealized circuit layout utilized in a power stage such as that of a power conversion system. The power stage comprises a pair of MOSFET transistors having substantially identical electrical characteristics and complementary package configurations for...

20060113658 - Substrate core and method for fabricating the same: A substrate including a first patterned metallic layer, a second patterned metallic layer and an insulator is provided. One side of the first patterned metallic layer is connected to a corresponding side of the second patterned metallic layer. The first patterned metallic layer and the second patterned metallic layer are...

20060113660 - Chip package mechanism: A chip package mechanism. A substrate is disposed in a receiving chamber of a base. A chip is disposed on a target surface of the substrate. A plurality of supporting elements is disposed on the target surface and surrounds the chip. A gap for receiving the chip is created in...

20060113659 - Pulse transformer package and method for making the same: A pulse transformer package includes a substrate, a passive component, and a cap member. The substrate includes a surface layer, a base layer, a middle wiring layer between the surface and base layers, a set of bonding pads formed on the surface layer, and a set of connecting pads formed...

20060113661 - Cooling system of power semiconductor module: A cooling system of a power semiconductor module of the invention includes a temperature detection sensor provided in a semiconductor element as a heat source provided in a power semiconductor module, and a controller which estimates a change of a heat transfer coefficient from the power semiconductor module to cooling...

20060113662 - Micro heat pipe with wedge capillaries: A heat pipe is disclosed comprising an elongated hollow housing having a condenser end and an evaporator end. A corrugated wick is disposed within the housing. The wick comprises a plurality of wedge-shaped capillaries extending from the condenser end to the evaporator end. A liquid is set in fluid communication...

20060113663 - Heat stud for stacked chip package: A semiconductor package assembly is presented. The assembly comprises a first chip and a second chip. The back surfaces of the first and the second chips are thermally attached through a die attach material. The front surface of the first chip is attached to a substrate through bumps. A heat...

20060113664 - Semiconductor device: The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS • FET for a high-side switch and a power MOS • FET for a...

20060113665 - Wire bond interconnection: A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond...

20060113666 - Electronic component: A surface-mounted electronic component has an outer lead extending from a package for connection to a circuit pattern on a printed circuit board by using a connecting member. The outer lead has a hole having an opening at least on a connecting member facing side in a portion of the...

20060113667 - Bond pad structure for gold wire bonding to copper low k dielectric silicon devices: A bond pad structure which improves the reliability of the gold bonds, and thus, of the device. The bond pad structure allows for small gold bonds, which increases the density of the device. One design provides that the aluminum pad is connected to the copper IO strap at one end...

20060113668 - Substrate package structure and packaging method thereof: A substrate package structure includes bumps disposed on a surface side of a first substrate and a surface side of a second substrate. The bump at the first substrate and the bump at the second substrate are press-fitted to each other while the one surface of the first substrate and...

20060113669 - Printed circuit board and manufacturing method thereof: A multi-layer structure including a base insulating layer and a thin metal film layer (seed layer) is prepared. A plating resist layer is formed to have a prescribed pattern on the upper surface of the thin metal film layer. A metal plating layer is formed on the thin metal film...

20060113670 - Multi-layer wiring, method of manufacturing the same and thin film transistor having the same: A multi-layer wiring for use with thin film transistors (TFTs), methods of manufacturing the multi-layer wiring, and TFTs employing the multi-layer wiring are provided. In one embodiment, the multi-layer wiring includes a main wiring and a sub-wiring on the main wiring. The main wiring includes a first metal and the...

20060113671 - Semiconductor device and method for manufacturing the same: In a manufacturing process of a semiconductor device, electroplating and CMP have had a problem of increase in manufacturing costs for forming a wiring. Correspondingly, an opening is formed in a porous insulating film after a mask is formed thereover, and a conductive material containing Ag is dropped into the...

20060113672 - Improved hdp-based ild capping layer: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound...

20060113673 - Semiconductor device and fabrication method thereof: A semiconductor device and fabrication thereof. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 Å. A copper layer is formed over the...

20060113674 - Semiconductor device and manufacturing method of semiconductor device: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend...

20060113675 - Barrier material and process for cu interconnect: A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal rich surface. Embodiments preferably include...

20060113676 - Semiconductor device and method of manufacture thereof: A barrier metal layer having a two-layer structure of a titanium film and a titanium nitride film is formed on the inner surface of a through hole. The titanium film and the titanium nitride film are formed on a main surface of an interlayer insulating film as well. In forming...

20060113678 - Csp chip stack with flex circuit: A chip stack comprising a flex circuit including a flex substrate having a first conductive pattern disposed thereon and a plurality of leads extending therefrom. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may be electrically connected to the...

20060113677 - Multi-chip module: A multi-chip module is provided which allows memory space extension to improve function and performance. A first semiconductor chip is mounted on a mounting substrate, and a first semiconductor memory chip is mounted over the first semiconductor chip. A second semiconductor memory chip having the same circuitry and the same...

20060113679 - Semiconductor device: A semiconductor device includes a semiconductor chip, wirings, a substrate electrically connected to the semiconductor chip via the wirings and a plurality of discrete parts provided on a part of the substrate. The part is located closer to the center of the substrate than a wiring disposing area where the...

20060113680 - Microelectronic packages with solder interconnections: A soldered assembly for a microelectronic element includes a microelectronic element, solder columns extending from a surface of the microelectronic element and terminals connected to distal ends of the columns. The assembly can be handled and mounted using conventional surface-mount techniques, but provides thermal fatigue resistance. The solder columns may...

20060113681 - Reinforced solder bump structure and method for forming a reinforced solder bump: A reinforced solder bump connector structure is formed between a contact pad arranged on a semiconductor chip and a ball pad arranged on a mounting substrate. The semiconductor chip includes at least one reinforcing protrusion extending upwardly from a surface of an intermediate layer. The mounting substrate includes at least...

20060113682 - Semiconductor component having plate and stacked dice: A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back...

20060113683 - Doped alloys for electrical interconnects, methods of production and uses thereof: Lead free solder compositions are described herein that include at least one solder material; at least one dopant material, wherein the dopant is present in the material in an amount of less than about 1000 ppm, and wherein the solder composition is substantially lead free. Several doped solder compositions described...

20060113684 - Bond pad for ball grid array package: A device (100) and a method (200) for controlling resin bleed, the device comprising a substrate (105) having a surface (107), an integrated circuit (115) having a plurality of leads (120) extending therefrom, and an adhesive (125) comprising a plurality of components. The adhesive (125) generally resides between the surface...

20060113685 - Copper alloy for wiring, semiconductor device, method for forming wiring and method for manufacturing semiconductor device: A wiring metal contains a polycrystal of copper (Cu) as a primary element and an additional element other than Cu, and concentration of the additional element is, at crystal grain boundaries composing the Cu polycrystal and in vicinities of the crystal grain boundaries, higher than that of the inside of...

20060113686 -