Active solid-state devices (e.g., transistors, solid-state diodes) inventions 05/06

20060108572 - Stacked module systems and methods: The present invention provides methods for constructing stacked circuit modules and precursor assemblies with flexible circuitry. Using the methods of the present invention, a single set of flexible circuitry whether articulated as one or two flex circuits may be employed with CSP devices of a variety of configurations either with...

20060108573 - Single crystalline gallium nitride thick film having reduced bending deformation: The present invention relates to a freestanding, thick, single crystalline gallium nitride (GaN) film having significantly reduced bending deformation. The inventive GaN film having a crystal tilt angle of C-axis to the <0001> direction per surface distance of 0.0022 °/mm exhibits little bending deformation even at a thickness of 1...

20060108574 - Optoelectronic transmitter integrated circuit and method of fabricating the same using selective growth process: Provided are an optoelectronic (OE) transmitter integrated circuit (IC) and method of fabricating the same using a selective growth process. In the OE transmitter IC, a driving circuit, which includes a double heterojunction bipolar transistor (DHBT) and amplifies received electric signals to drive an electroabsorption (EA) modulator, and the EA...

20060108575 - Method of fabricating static random access memory: A method of fabricating a static random access memory device includes selectively removing an insulating film and growing a single crystalline silicon layer using selective epitaxy growth, the single crystalline silicon layer being grown in a portion from which the insulating film is removed; recessing the insulating film; and depositing...

20060108576 - Layer system comprising a silicon layer and a passivation layer, method for production a passivation layer on a silicon layer and the use of said system and method: A layer system is described including a silicon layer and a passivation layer which is applied at least regionally to the silicon layer's surface, the passivation layer having a first, at least largely inorganic partial layer and a second partial layer, the second partial layer being made of an organic...

20060108579 - Low-voltage organic transistors on flexible substrates using high-gate dielectric insulators by room temperature process: A transistor device includes a transparent substrate. A high K dielectric is formed on the transparent substrate and transferred onto a flexible substrate. An organic transistor is formed on the high K dielectric....

20060108577 - Nanocrystal protective layer for crossbar molecular electronic devices: A molecular device is provided. The molecular device comprises a junction formed by a pair of crossed electrodes where a first electrode is crossed by a second electrode at a non-zero angle and at least one connector species including at least one switchable moiety and connecting the pair of crossed...

20060108580 - Organic el device: Provided is an organic EL device, including: a transparent substrate having a front surface and a rear surface; a first electrode layer, an organic layer including a light emitting layer and a second electrode layer that are formed in order on the front surface of the transparent substrate; and a...

20060108582 - Organic field-effect transistor and method of making same based on polymerizable self-assembled monolayers: An organic field-effect transistor and a method of making the same include a self-assembled monolayer (SAM) of bifunctional molecules disposed between a pair of electrodes as a channel material. The pair of electrodes and the SAM of bifunctional molecules are formed above an insulating layer, in which each of the...

20060108578 - Organic photoelectric device with improved electron transport efficiency: An opto-electronic device, such as an OLED or organic solar cell, having an electrode structure for use as a cathode. The electrode structure includes an electrically conductive layer and an inorganic layer, wherein the inorganic layer is made of at least one oxide-based alkali or alkaline earth metal intercalation compound....

20060108581 - Organic thin film transistor, method of manufacturing the same, and flat panel display device with the organic thin film transistor: An organic thin film transistor that has good adhesiveness and good contact resistance as well as allows ohmic contact between an organic semiconductor layer and a source electrode and a drain electrode, and its manufacturing method. There is also provided a flat panel display device using the organic thin film...

20060108583 - System and method for removing film from planar substrate peripheries: A system for removing film from a planar substrate includes a shuttle which transports a film-coated substrate through a film removal station to a rotation station. At the rotation station, the substrate is removed from the shuttle and rotated to a new orientation. After being repositioned on the shuttle, the...

20060108584 - Display device: A display device including a first substrate, a first subpixel electrode, a second subpixel electrode corresponding to the first substrate, a second substrate and a common electrode formed on the second substrate is provided. The first subpixel electrode and the second subpixel electrode are formed on the first substrate. The...

20060108585 - Thin film transistors and fabrication methods thereof: Thin film transistors and fabrication methods thereof. A gate is formed overlying a portion of a substrate. A gate-insulating layer is formed overlying the gate. A vanadium oxide layer is formed between the gate and the substrate and/or the gate and the gate-insulating layer. A semiconductor layer is formed on...

20060108588 - Display device and electronic device: The invention provides a display device and an electronic device, each of which has one of a structure in which a substrate provided with a light emitting element which performs bottom light emission and a substrate provided with a light emitting element which performs top light emission are attached, and...

20060108586 - Display panels with anti-newton ring structures: A display panel with an anti-Newton ring structure is disclosed. The display panel includes a substrate with an array region and a display region defined thereon. A buffer layer is disposed on the substrate and at least one transistor is formed in the array region. The display panel further includes...

20060108587 - Thin film transistor array panel and manufacturing method thereof: A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor...

20060108589 - Semiconductor device: A semiconductor device (1) includes an n-type silicon carbide substrate (2) of a high impurity concentration, an n-type silicon carbide layer (3) of a low impurity concentration disposed on the substrate, a first n-type silicon carbide region (4) of a first impurity concentration disposed on the surface of the n-type...

20060108590 - Group iii-v nitride series semiconductor substrate and assessment method therefor: The group III-V nitride series semiconductor substrate has good-product yield when the band-edge peak light-emission intensity ratio α=N1/N2 is α<1, where N1 is a band-edge peak light-emission intensity at an arbitrary photoluminescence measurement position on the front side of the substrate, and N2 is a band-edge peak light-emission intensity on...

20060108591 - Method and apparatus for electroluminescence: Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure....

20060108592 - Organic electroluminescent apparatus: A red color filter layer is provided under an organic EL device. A green color filter layer, a blue color filter layer, and a region without a color filter layer are provided in this order under an organic EL device. Orange light from the organic EL device is transmitted through...

20060108593 - Gan-based compound semiconductor light emitting device: A GaN-based compound semiconductor light emitting device is provided. The semiconductor light emitting device includes a substrate; an n-type semiconductor layer formed on the substrate; an active layer formed on a first region of the n-type semiconductor layer; a p-type semiconductor layer formed on the active layer; a p-type electrode...

20060108594 - Led device and method for manufacturing the same: An LED device can include LED chips mounted with high density and encapsulated with a resin. The device may not be substantially affected by fluctuations in thermal stress generated in the encapsulating resin and can have reduced fluctuations in characteristics such as output power and a color tone and can...

20060108595 - Led fabrication via ion implant isolation: A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the...

20060108596 - Nitride semiconductor device and method of manufacturing the same: A P-type electrode material is provided on a top surface of a P-type contact layer. The P-type electrode material is formed with an AuGa film, an Au film, a Pt film, and an Au film. The AuGa film is provided on the P-type contact layer. The Au film is provided...

20060108597 - Light-emitting device and vehicle lamp: A light-emitting device in which a light-emitting element, such as an LED, and an electrostatic protection element for protecting the light-emitting element from electrostatic breakdown are connected in parallel. The light-emitting device is configured such that a connection wire member of the light-emitting element and a connection wire member of...

20060108598 - Gallium nitride-based light-emitting device: A light-emitting gallium nitride-based III-V group compound semiconductor device with enhanced brightness includes a substrate, a first-type conductive semiconductor layer, a light-emitting layer, a second-type conductive semiconductor layer, a transparent conductive layer, and two electrodes. During the manufacturing process of chips, a single or a pair of diamond scribing tool...

20060108599 - Triple well structure and method for manufacturing the same: The present invention discloses a triple well structure, which includes a substrate of a first conductive type, a deep buried well of a second conductive type, a well of a first conductive type, a well ring of a second conductive type, and a well ring of a first conductive type....

20060108600 - Semiconductor device and method for manufacturing the same: The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions...

20060108601 - Insulating substrate and semiconductor device: An insulating substrate includes a metal base as a base member, an insulating layer which is a room temperature, aerosol deposited shock solidification film formed on the metal base, and a circuit pattern which is a cold sprayed thermal spray coating formed on the insulating layer. A semiconductor device incorporates...

20060108602 - Field effect transistor and method of manufacturing the same: A field effect transistor includes an i-type first semiconductor layer and a second semiconductor layer that is formed on the first semiconductor layer and the band gap energy of that is higher in magnitude than that of the first semiconductor layer. The first semiconductor layer and second semiconductor layer are...

20060108603 - Group iii nitride compound semiconductor light emitting device: In a group III nitride compound semiconductor light emitting device comprising an n-type semiconductor layer, a p-type semiconductor layer having a superlattice structure in which a first layer comprising at least Al and a second layer having a different composition from that of the first layer are laminated repetitively, and...

20060108604 - Bipolar transistor and a method of fabricating said transistor: The invention proposes a bipolar transistor comprising a substrate, emitter, base, and collector layers and, if appropriate, contact layers. The base layer is formed from a GaAsSb material. The transistor also has at least one transition layer formed from a GaInP material between the emitter layer and the base layer....

20060108605 - Schottky barrier diode and integrated circuit using the same: A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a substrate; and a high-resistance region formed in the first semiconductor layer and the second semiconductor layer and having higher resistance than the first semiconductor layer and the second semiconductor layer. A Schottky...

20060108606 - Cap layers and/or passivation layers for nitride-based transistors, transistor structures and methods of fabricating same: High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include...

20060108607 - Integrated circuit component and mounting method thereof: Disclosed are an integrated circuit component capable of simply mounting at low cost a chip part which adjusts impedance of wiring patterns as well as capable of effectively reducing switching noise from an integrated circuit, and a method for mounting the chip part. The integrated circuit component of the present...

20060108609 - Barrier dielectric stack for seam protection: The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric...

20060108608 - Hetero bipolar transistor: The invention relates to a heterobipolar transistor, comprising an emitter which includes a first semiconductor layer (8) made of a first semiconductor material and a second semiconductor layer (9) made of a second semiconductor material, a band gap value of the first semiconductor material being smaller than a band gap...

20060108610 - Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method: In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer...

20060108611 - Image sensing device and method of: A two-dimensional, temporally modulated electromagnetic wavefield, preferably in the ultraviolet, visible or infrared spectral range, can be locally detected and demodulated with one or more sensing elements. Each sensing element consists of a resistive, transparent electrode (E) on top of an insulated layer (O) that is produced over a semiconducting...

20060108612 - Packaging: A packaging (10) containing a product (11). The product (11) may be a solar powered light device (110). The packaging (10) includes a switch (23) that is operable to activate the product (11) while the product (11) is still within the packaging (10) so that a user may observe operation...

20060108613 - Cmos image sensor: Provided is a CMOS image sensor including a pinned photodiode and a transfer transistor. The CMOS image sensor includes: a substrate; a gate electrode disposed on the substrate and electrically isolated from the substrate by a gate insulating layer; a first floating region disposed in the substrate of one side...

20060108614 - Cmos image sensor: A complementary metal-oxide semiconductor (CMOS) image sensor comprises a photodiode region generating electrical charges in response to incident light thereon. The CMOS image sensor further comprises a first floating diffusion layer adapted to receive the electrical charges from the photodiode region in response to a global transfer signal and a...

20060108615 - Liquid crystal display apparatus and driving method thereof: This invention relates to a liquid crystal display device that minimizes picture quality deterioration caused by signal distortion. The present invention selects an area within an image, which has a rapidly increasing or decreasing gamma voltage, identifies a border delineating two different intensity regions within the area, computes an average...

20060108616 - High-voltage metal-oxide-semiconductor transistor: A high-voltage metal-oxide-semiconductor (HV MOS) transistor is provided to form the decoder in a source driver of a display apparatus for substantially saving the layout area. The HV MOS transistor includes two doped regions with a first conductivity type disposed in a semiconductor substrate, and a gate region having a...

20060108617 - Solid-state image pickup device and manufacturing method for the same: A solid-state image pickup device includes, in a substrate, a plurality of photoelectric conversion regions for subjecting incoming light to photoelectric conversion, a reading gate for reading a signal charge from the photoelectric conversion regions, and a transfer register (vertical register) for transferring the signal charge read by the reading...

20060108618 - Cmos image sensor having buried channel mos transistors: A CMOS image sensor having buried channel MOS transistors is disclosed. The CMOS image sensor includes a photo converting device and a source follower transistor. The photo converting device generates a current signal and changes a voltage of a floating node in response to energy of an incident light. The...

20060108621 - Capacitor insulating film, method for fabricating the same, capacitor element, method for fabricating the same, semiconductor memory device, and method for fabricating the same: A capacitor insulating film is composed of a ferroelectric film formed on a substrate and containing an element functioning as a crystal nucleus which allows the growth of a crystal in a random crystal orientation....

20060108622 - Ferroelectric integrated circuit devices having an oxygen penetration path and methods for manufacturing the same: Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing...

20060108619 - Ferromagnetic iv group based semiconductor, ferromagnetic iii-v group based compound semiconductor, or ferromagnetic ii-iv group based compound semiconductor, and method for adjusting their ferromagnetic characteristics: Disclosed is a ferromagnetic group IV-based semiconductor or a ferromagnetic group III-V-based or group II-VI-based compound semiconductor, comprising a group IV-based semiconductor or a group III-V-based or group II-VI-based compound semiconductor, which contains at least one rare-earth metal element selected from the group consisting of Ce, Pr, Nd, Pm, Sm,...

20060108623 - Oxidative top electrode deposition process, and microelectronic device structure: A method of preventing oxygen deficiency in a ferroelectric or high ε film material having a top electrode layer deposited thereon. Process conditions are employed that either enable the top electrode layer to be formed without oxygen abstraction from the ferroelectric or high ε film material in the vicinity and...

20060108620 - Reduced power magnetoresistive random access memory elements: Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite...

20060108625 - Methods of programming non-volatile memory devices including transition metal oxide layer as data storage material layer and devices so operated: A method of programming a non-volatile memory device including a transition metal oxide layer includes applying a first electric pulse to the transition metal oxide layer for a first period to reduce a resistance of the transition metal oxide layer and applying a second electric pulse to the transition metal...

20060108624 - Semiconductor device: A semiconductor device comprises a capacitor including a bottom electrode, a top electrode, and a dielectric film, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third...

20060108627 - Nand flash memory devices including multi-layer memory cell transistor structures and methods of fabricating the same: An integrated circuit memory device on a multi-layer substrate includes first and second selection transistors, a first plurality of serially connected memory cell transistors on a first substrate layer, and a second plurality of serially connected memory cell transistors on a second substrate layer. The first plurality of serially connected...

20060108633 - Electrically erasable programmable read only memory (eeprom) cells and methods of fabricating the same: Electrically erasable programmable read only memory (EEPROM) cells and methods of fabricating the same are provided. An EEPROM cell includes an isolation layer formed at a semiconductor substrate to define an active region. A source region, a buried N+ region and a drain region are serially disposed at the active...

20060108631 - Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures: In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric (310) formed over control gates (134). The dielectric thickness...

20060108629 - Multi-bit non-volatile memory device, method of operating the same, and method of fabricating the same: A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be...

20060108628 - Multi-level split-gate flash memory: A multi-level split-gate flash memory is provided. The flash memory includes a substrate, a memory row, a dummy select gate, a source region and a drain region. The memory cell row includes a plurality of serially connected memory cells with each memory cell having a stacked gate structure and a...

20060108632 - Reducing delays in word line selection: Delays in selecting word lines of a NAND memory device are reduced by respectively connecting conductive straps to word lines of a subset of the word lines of the memory device....

20060108630 - Semiconductor memory and method for manufacturing the same: A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a P type silicon substrate, a control gate CG and a pair of electrically isolated floating gates. Plural projections are formed in the silicon substrate, and a pair of N type diffusion regions...

20060108634 - Semiconductor apparatus and method for manufacturing the same: A semiconductor apparatus comprises a gate electrode, a gate insulating layer, a drift region of a first conductivity type formed over a semiconductor substrate of the first conductivity type, a base region of a second conductivity type formed over the drift region, a source region of the first conductivity type...

20060108635 - Trenched mosfets with part of the device formed on a (110) crystal plane: This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming part of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed...

20060108636 - Amorphous oxide and field effect transistor: A novel amorphous oxide applicable, for example, to an active layer of a TFT is provided. The amorphous oxide comprises microcrystals....

20060108637 - Esd protection apparatus for an electrical device: An ESD protection apparatus for an electrical device with a circuit structure having an internal terminal, which is connected to an external terminal of the electrical device via a conductive connection, has a gas-filled cavity, through which the conductive connection extends at least partly, and a reference electrode in the...

20060108640 - Semiconductor integrated circuit: A semiconductor integrated circuit comprising: a pair of MOS transistors which are formed in a same well on a semiconductor substrate and arranged adjacent to each other with a distance such that charge exchange between capacitances of respective drain diffusion layers is possible; and a wiring structure which is formed...

20060108639 - Transistor, method of manufacturing transistor, and method of operating transistor: A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially...

20060108643 - Cmos on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding: A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to...

20060108641 - Device having a laterally graded well structure and a method for its manufacture: Provided are a device and method for its manufacture. In one example, the device includes a semiconductor substrate that includes a well region formed using a first-type dopant. First and second doped regions are formed in the well region using a second-type dopant, and the first and second doped regions...

20060108644 - Self-aligned double gate device and method for forming same: In a method of forming a double gate device, a buried insulating layer having a thickness of less than about 30 nm is formed on a first substrate. A second substrate is formed on the buried insulating layer. A pad layer is formed over the second substrate. A mask layer...

20060108646 - Nrom semiconductor memory device and fabrication method: This invention relates to a method for producing an NROM semiconductor memory device and a corresponding NROM semiconductor memory device. The inventive production method comprises the following steps: a plurality of spaced-apart U-shaped MOSFETS are provided along rows in a first direction and along gaps in a second direction inside...

20060108648 - Memory with self-aligned trenches for narrow gap isolation regions: Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second...

20060108647 - Self-aligned trench filling for narrow gap isolation regions: Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second...

20060108650 - Method of enlarging contact area of a gate electrode, semiconductor device having a surface-enlarged gate electrode, and method of manufacturing the same: A highly integrated semiconductor device operates at a high speed due to low resistance at the gate electrode and minimal parasitic capacitance between the gate electrode and substrate. A gate pattern is formed on a substrate, and an insulating layer is formed over the substrate including over the gate pattern....

20060108651 - Lowered source/drain transistors: A novel transistor structure and method for fabrication the same. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. The method for fabricating the transistor structure starts out with a planar...

20060108652 - Microelectromechanical systems, and methods for encapsulating and fabricating same: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes...

20060108653 - Preventing substrate deformation: A substrate prevented from being deformed due to thermal stress or deposition stress includes a deformation preventing layer arranged on one surface of the substrate. The substrate can include a thin film transistor arranged on one surface of the substrate and the deformation preventing layer, arranged on the another surface...

20060108654 - Hall sensor and method for the operation thereof: The invention relates to a Hall sensor on a semiconductor substrate (1), in which a Hall plate (2) is formed from a zone (33, 32) of one conduction type; in which a zone (33, 32) adjoining the Hall plate (2), which zone (33, 32) is separated from said Hall plate...

20060108655 - Mram layer having domain wall traps: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells...

20060108656 - Optical device: An optical device according to the present invention includes a device substrate, a translucent member, an optical element chip and a conductive portion. On a surface of the device substrate, an opening is provided so as to extend substantially in the vertical direction with respect to a surface of the...

20060108657 - Photodiode detector: The photodiode includes a substrate of a first semiconductor material and an isolating layer of a second semiconductor material. The second semiconductor material is of opposite doping character or type to the first semiconductor material. The isolating layer of the second semiconductor material is implanted with one or more wells...

20060108658 - Functional device and method for producing the same, and image pickup device and method for producing the same: A method of producing a functional device comprising an electrode layer provided as an upper layer of a layer containing an organic material, the layer being as a functional layer, wherein a step of patterning the electrode layer comprises a high speed etching step of etching the electrode layer at...

20060108659 - Schottky barrier diode and diode array: A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a semiconductor substrate with a buffer layer formed between the first and second semiconductor layers and the semiconductor substrate. A Schottky electrode and an ohmic electrode spaced from each other are formed on...

20060108660 - Amplifier circuit, control method of the same, and amplifier circuit module: An amplifier circuit includes an amplifier having an amplifying device composed of GaN or a GaN compound semiconductor used for an active region, and a distortion compensation circuit that is connected to the amplifier, has an attenuation characteristic, and has a negative phase distortion....

20060108661 - Semiconductor device having sti without divot and its manufacture: The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride film and having a window; depositing a second silicon nitride film covering an inner surface of the isolation...

20060108662 - An electrically programmable fuse for silicon-on-insulator (soi) technology: A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline...

20060108663 - Surface mount inductor with integrated componentry: Disclosed are inductor systems with reduced volume for use in larger electronic circuits. Embodiments of the invention are disclosed for a surface mount inductor system that includes an inductor having a niche for receiving an IC component interposed between the inductor and PCB. Preferably, the assembly is encapsulated to form...

20060108664 - Pre-matching of distributed and push-pull power transistors: Pre-matching of distributed push-pull and power transistors enabling the effective use of high-power and high-frequency transistor arrays. In accordance with the invention, a pre-matching element is connected between stages of multi-transistor arrays. The pre-matching element serves to transform the impedance at a connecting point between stages toward an impedance level...

20060108665 - Semiconductor device, manufacturing method of the same, and electronic device: The invention is directed to improve characteristics of an HBT (Hetero-junction Bipolar Transistor). An HBT has a collector layer, a base layer, and an emitter layer formed in order on a main surface of a substrate made of a compound semiconductor and a collector electrode, a base electrode, and an...

20060108666 - Semiconductor device and method of fabricating the same: A conductor layer is formed on one surface of a semiconductor substrate having a functional element formed therein, with an insulating layer interposed therebetween, and a through hole is then formed at a predetermined position in the semiconductor substrate. Furthermore, a support sheet is attached to the other surface of...

20060108667 - Method for manufacturing a small pin on integrated circuits or other devices: A method of forming a device comprises forming a structure with a side wall. A side wall spacer is formed on the side wall. The side wall spacer is etched according to a pattern to define the width of the side wall spacer. The width is sub-lithographic, including for example...

20060108668 - Tamper resistant packaging and approach: A tamper-resistant packaging approach protects non-volatile memory. According to an example embodiment of the present invention, an array of magnetic memory elements (130-132) in an integrated circuit (100) are protected from magnetic flux (122) by a package (106) including a magnet (120). Flux from the magnet is directed away from...

20060108670 - Leadframe designs for integrated circuit plastic packages: The specification describes a plastic cavity package design for high power transistor packages in which the leadframe is formed of a composite of materials. This allows the portions of the leadframe that require strength to be formed of a high strength material, e.g. steel, while the paddle portion of the...

20060108669 - Light emitting element: A light emitting element includes: a box-shaped case formed by an insulation material and having a space inside; a lead frame formed by a conductive material and fixed to the case; and a light emitting chip fixed to the lead frame. On the lead frame, a rise portion is formed...

20060108672 - Die bonded device and method for transistor packages: The specification describes a technique for die bonding that is tailored to air cavity plastic packages for high power devices. The die bonding method is simple and effective, and eliminates the step of placement of solder preforms in the die bonding operation. According to the invention the die that are...

20060108671 - Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side...

20060108673 - Method for forming an encapsulated device and structure: In one embodiment, an electronic device package (1) includes a leadframe (2) with a flag (3). An electronic chip (8) is attached to the flag (3) with a die attach layer (9). A trench (16) having curved sidewalls is formed in the flag (3) in proximity to the electronic chip...

20060108674 - Package structure of memory card and packaging method for the structure: A package structure of a memory card includes a substrate. The substrate has connection pads on a first surface and conductive lead structures respectively coupled with the connection pads and extending to a second surface of the substrate. At least one chip is disposed over the substrate at the first...

20060108675 - Apparatus and methods for encapsulating microelectromechanical (mem) devices on a wafer scale: Apparatus and methods are provided for enabling wafer-scale encapsulation of microelectromechanical (MEM) devices (e.g., resonators, filters) to protect the MEMs from the ambient and to provide either a controlled ambient or a reduced pressure. In particular, methods for wafer-scale encapsulation of MEM devices are provided, which enable encapsulation of MEM...

20060108677 - Multi-chip package and method of fabricating the same: A lower chip is fixed to a surface of an interposer by flip-chip bonding with an under fill acting as an adhesive applied to the surface. A lifted pad having a height of approximately 10 μm is provided on the surface of the interposer. A bonding wire connects the lifted...

20060108676 - Multi-chip package using an interposer: A method and apparatus for multi-chip packages that are closely coupled using an interposer is disclosed. A top single chip or multi-chip encapsulated package with bottom side contacts is formed and tested. A bottom single chip or multi-chip package substrate having bottom contacts is formed. Then a hollow center interposer...

20060108678 - Probe arrays and method for making: Embodiments of invention are directed to the formation of microprobes (i.e. compliant electrical or electronic contact elements) on a temporary substrate, dicing individual probe arrays, and then transferring the arrays to space transformers or other permanent substrates. Some embodiments of the invention transfer probes to permanent substrates prior to separating...

20060108679 - Method for testing a chip with a package and for mounting the package on a board: The invention relates to the fabrication and testing of a chip with a package (2) having connecting pins (1) as well as to mounting the package (2) on a board (5), whereby in order to combine the advantages of a package (2) with inline connecting pins (1) with the advantages...

20060108680 - Multi-layer printed circuit board wiring layout and method for manufacturing the same: A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle layer and the second wire layer. The manufacturing method includes the steps of providing a...

20060108681 - Semiconductor component package: A semiconductor component package and method of fabrication are disclosed. The package employs a heat dissipating element embedded within the protective material over the component. The heat dissipating element is preferably made by stamping, and is formed from an essentially uniform thickness heat conducting sheet. The element is formed so...

20060108683 - Semiconductor device, radiographic imaging apparatus, and method for manufacturing the same: A semiconductor device or a radiographic imaging apparatus includes a substrate and a supporting member, the substrate having a semiconductor element or a conversion element and being bonded to the supporting member with a laminating member. The semiconductor device or the radiographic imaging apparatus further includes at least one cushioning...

20060108684 - Power module, phase leg, and three-phase inverter: A power module includes a substrate that includes an upper layer, an electrical insulator and a thermal coupling layer. The upper layer includes an electrically conductive pattern and is configured for receiving power devices. The electrical insulator is disposed between the upper layer and the thermal coupling layer. The thermal...

20060108685 - Integrated circuit package and assembly thereof: An integrated circuit (IC) package and IC assembly. The IC assembly comprises the IC package, an insulating substrate and an adhesive film. The IC package comprises a chip body and a plurality of bumps. The bumps are disposed on a first surface of the chip body, each bump having a...

20060108686 - Semiconductor device for fingerprint recognition: A semiconductor device is disclosed that performs fingerprint recognition on the electrostatic-capacity principle. A finger sweeping across a fingerprint recognition area of a semiconductor chip provides positive fingerprint recognition operations with improved reliability. The semiconductor device includes the semiconductor chip having a sensor unit that performs fingerprint recognition, and a...

20060108687 - Using zeolites to improve the mechanical strength of low-k interlayer dielectrics: A method for impregnating the pores of a zeolite low-k dielectric layer with a polymer, and forming an interconnect structure therein, thus mechanically strengthening the dielectric layer and preventing metal deposits within the pores....

20060108688 - Large grained polycrystalline silicon and method of making same: A silicon structure includes a selective nucleating single phase epitaxial (SNSPE) template polysilicon layer containing crystallization catalyst residue, and a hot wire chemical vapor deposited (HWCVD) epitaxial polysilicon layer epitaxially grown on said template layer. The silicon structure may satisfy at least one of the following: 1) a thickness of...

20060108692 - Bit line structure and method for the production thereof: A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated...

20060108690 - Circuit board with reduced simultaneous switching noise: A circuit board with reduced simultaneous switching noise. The circuit board comprises a first conductor plane with a first fixed potential, a dielectric layer, at least a build-up via and a second conductor plane with a second fixed potential. The dielectric layer is formed on the first conductor plane. The...

20060108689 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device in a MLM process to reduce compression stress of a metal line or a HDP oxide film, and to reduce compression stress in a subsequent metal line thermal treatment process. It is thus possible to reduce generation of a crack caused by compression...

20060108691 - Semiconductor device and manufacturing method of the same: The first pad electrode layer is disposed on the surface of the semiconductor substrate with the first insulating film between them. Then, the second insulating film with the first via hole partially exposing the first pad electrode layer is formed over the first pad electrode layer. The plug is formed...

20060108693 - Solder for fabricating solder bumps and pumping process: A bumping process including following steps is disclosed. First, a wafer is provided, wherein the wafer has an active surface and bonding pads disposed on the active surface. Next, solder material is provided for forming solder posts on the bonding pads, wherein the solder material for forming the solder posts...

20060108694 - Circuit layout structure and method: A symmetrical circuit layout structure includes a number of signal wires, a ground wire and a dielectric layer. The signal wires include a first portion placed on a first plane and a second portion placed on a second plane. The ground wire includes a first portion placed above the first...

20060108695 - Semiconductor device and manufacturing method of the same: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to a pad...

20060108696 - Structure for reducing stress-induced voiding in an interconnect of integrated circuits: A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the...

20060108697 - Multi-chips semiconductor device assemblies and methods for fabricating the same: Multi-chip semiconductor device assemblies and methods for fabricating such assemblies are provided. An exemplary assembly comprises a first chip having a first surface and comprising a plurality of conductive pads disposed at the first surface and a plurality of circuits. Each of the pads is electrically coupled to one of...

20060108698 - Microelectronic assemblies and methods of making microelectronic assemblies: A microelectronic subassembly includes a substrate having a first surface, and one or more microelectronic elements positioned above the first surface of the substrate, each microelectronic element having a contact bearing face confronting the first surface of the substrate and a back surface remote therefrom. The subassembly includes a substantially...

20060108699 - Electronic part and method for manufacturing the same: A method for manufacturing an electronic part, including: cutting a wiring substrate, which contains a base substrate, a wiring pattern provided on a first surface of the base substrate, and a reinforcing member provided on a second surface of the base substrate, along a line intersecting with an outer circumference...

20060108700 - Semiconductor device, method and apparatus for fabricating the same: A semiconductor device has at least one semiconductor element, at least one radiator plate thermally connected with said semiconductor element, and a molded resin covering and sealing said semiconductor device and said radiator, wherein an outer main surface of the radiator plate and at least a part of the side...

20060102887 - Protection of active layers of memory cells during processing of other elements: A method of fabricating an electronic structure by providing a conductive layer, providing a dielectric layer over the conductive layer, providing first and second openings through the dielectric layer, providing first and second conductive bodies in the first and second openings respectively and in contact with the conductive layer, providing...

20060102888 - Semiconductor substrate and method of fabricating the same: A semiconductor substrate and a method of fabricating the same are provided. The semiconductor substrate includes: a Si substrate; a SiO2 layer having a predetermined width formed on the Si substrate; a SiGe layer having a first end portion and a second end portion at both sides and formed on...

20060102889 - Tri-gated molecular field effect transistor and method of fabricating the same: Provided is a tri-gated molecular field effect transistor (FET) and a method of fabricating the same. The tri-gated molecular field effect transistor includes a gate electrode formed on a substrate and having grooves in a source region, a drain region and a channel region, and at least one molecule inserted...

20060102890 - Dendrimer and electronic device element employing the same: An object of the invention is to provide a novel dendrimer serving as an organic semiconductor material which is isotropic and which exhibits remarkably high carrier conductivity. Another object of the invention is to provide an electronic device employing the dendrimer. These objects are attained by a dendrimer having a...

20060102894 - Electronic device, method of manufacturing an electronic device, and electronic apparatus: An electronic device including: a pair of electrodes; an organic semiconductor layer; and an organic film formed of organic compounds including nonconjugated organic compounds coupled to at least one of surfaces of the pair of electrodes....

20060102891 - Organic photovoltaic component and method for production thereof: The invention relates to an organic photovoltaic component, in particular an organic solar cell, in which one or more layers is (are) structured....

20060102896 - Organic thin film transistor: Organic TFTs having uniform characteristics and a flat panel display having the organic TFT, wherein the organic TFTs include an organic semiconductor layer formed by spin coating are disclosed. One embodiment of the organic TFT includes: a substrate, a gate electrode disposed on the substrate, a gate insulating film covering...

20060102897 - Organic thin film transistor and flat panel display including the same: An organic thin film transistor comprising an organic semiconductor layer that does not cause a coffee stain effect and can prevent an imperfect contact with source and drain electrodes, and a flat panel display apparatus comprising the organic thin film transistor are provided. The organic thin film transistor comprises a...

20060102895 - Precursor compositions for forming tantalum-containing films, and tantalum-containing barrier films and copper-metallized semiconductor device structures: Tantalum compositions of Formulae I-V hereof are disclosed, having utility as precursors for forming tantalum-containing films. The tantalum compositions are amenable to usage involving chemical vapor deposition and atomic layer deposition processes, to form semiconductor device structures, including a dielectric layer, a barrier layer overlying the dielectric layer, and copper...

20060102893 - Semiconductors containing trans-1,2-bis(acenyl)ethylene compoounds: Semiconductor devices are described that include a semiconductor layer that contains a trans-1,2-bis(acenyl)ethylene compound. The acenyl group is selected from 2-naphtyl, 2-anthracenyl, or 2-tetracenyl. Additionally, methods of making semiconductor devices are described that include depositing a semiconductor layer that contains a trans-1,2-bis(acenyl)ethylene compound....

20060102892 - Switching element: The present invention provides a switching element in which an organic bistable material is disposed between two electrodes, this element having a high ratio of ON current to OFF current, a high threshold voltage, and a small spread. A switching element in which an organic bistable material layer comprising an...

20060102900 - Flat panel display and its method of fabrication: A flat panel display device which can prevent line defects and voltage drops using a conductive substrate formed of metal foil as a power supply layer includes: a conductive substrate; a first insulating layer formed on one side of the substrate and having a contact hole exposing a part of...

20060102899 - Liquid crystal display device and method of fabricating the same: A liquid crystal display device, including: a gate line with a double conductive layer structure on a substrate; a data line crossing the gate line with an interlayer insulating film in between to define a pixel area; a pixel electrode formed of the double conductive layer structure in the pixel...

20060102898 - Vva-mode liquid crystal display: A VVA-mode LCD having improved transmittance and response speed includes upper and lower substrates positioned to face each other with a predetermined distance between them; a liquid crystal layer having negative anisotropy of dielectric constant interposed between the upper and lower substrates; a color resin layer formed on the inner...

20060102901 - Systems and methods for creating crystallographic-orientation controlled poly-silicon films: In accordance with one aspect, the present invention provides a method for providing polycrystalline films having a controlled microstructure as well as a crystallographic texture. The methods provide elongated grains or single-crystal islands of a specified crystallographic orientation. In particular, a method of processing a film on a substrate includes...

20060102902 - Thin film transistor array panel: A thin film transistor array panel is provided, which includes: a substrate including a plurality of pixel areas; a semiconductor layer formed on the substrate and including a plurality of pairs of first and second semiconductor portions in respective pixel areas; a first insulating layer formed on the semiconductor layer;...

20060102906 - Electro-optical device and electronic apparatus: An electro-optical device includes a pair of substrates that are disposed to face each other with a predetermined gap therebetween, one substrate of the pair of substrates extending from the other substrate on at least one side in plan view, display electrodes that are provided on one substrate, a circuit...

20060102905 - Liquid crystal display device and method of fabricating the same: A poly-silicon liquid crystal display device with an improved aperture ratio and a simplified method of fabricating the same are disclosed. A liquid crystal display device according to the present invention includes first and second substrates; a gate line on the first substrate; a data line crossing the gate line...

20060102904 - Pixel structure and manufacturing method thereof: A pixel structure controlled by a scan line and a data line on a substrate is provided. The pixel structure comprises a thin film transistor, a resistance wire, a first pixel electrode, and a second pixel electrode, which are disposed on the substrate. Additionally, the thin film transistor is electrically...

20060102903 - Thin film transistor array panel and liquid crystal display including the panel: A gate wire including a gate line extending in a transverse direction and a gate electrode connected to the gate line is form on an insulating substrate. A storage capacitor wire including a storage capacitor electrode line extending in the transverse direction and a storage electrode connected to the storage...

20060102907 - Thin film transistor array panel and method for manufacturing the same: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain...

20060102908 - Semiconductor device: A semiconductor device includes an SiC substrate, an SiC layer of a first conductivity type disposed on the upper surface of the SiC substrate, a first SiC region of a second conductivity type disposed on the SiC layer, a second SiC region of the first conductivity type disposed on a...

20060102909 - Light-emitting diode structure: A gallium-nitride based light-emitting diode structure includes a digital penetration layer to raise its reverse withstanding voltage and electrostatic discharge. The digital penetration layer is formed by alternate stacking layers of AlxInyGa1-x-yNzP1-z/AlpInqGa1-p-qNrP1-r, wherein 0≦x,y,z,p,q,r≦1, and AlxInyGa1-x-yNzP1-z has an energy gap greater than that of AlpInqGa1-p-qNrP1-r. The AlxInyGa1-x-yNrP1-z layers have increasing...

20060102910 - Method for manufacturing light emitting device: An object of the present invention is to provide a new light emitting element with little initial deterioration, and a display device in which initial deterioration is reduced and variation in deterioration over time is reduced by a new method for driving a display device having the light emitting element....

20060102912 - Light emitting device: There is provided a light emitting device having a plurality of luminous elements emitting with different colors respectively being improved in a luminous intensity deviation and a color deviation without deterioration of a luminous efficiency. In the light emitting device having a plurality of luminous elements respectively emitting with different...

20060102911 - Organic light emitting display and method of fabricating the same: An organic light emitting display including a pixel electrode arranged on a substrate, an organic layer arranged on the pixel electrode and including at least a hole injection layer, a hole acceleration layer, a hole transport layer, and an emission layer, and an opposite electrode arranged on the organic layer....

20060102913 - Full color oled and method of fabricating the same: A full color organic light emitting display device (OLED) and a method of fabricating the same are provided. The OLED includes an element substrate and an encapsulating substrate. The element substrate includes a color filter layer or a color conversion layer, as well as an organic layer with an emission...

20060102916 - Ii-vi/iii-v layered construction on inp substrate: A layered construction is provided comprising an InP substrate and alternating layers of II-VI and III-V materials. The alternating layers of II-VI and III-V materials are typically lattice-matched or pseudomorphic to the InP substrate. Typically the II-VI material is selected from the group consisting of ZnSe, CdSe, BeSe, MgSe, ZnTe,...

20060102915 - Wavelenght converted light emitting apparatus using phosphor and manufacturing method thereof: Disclosed herein is a wavelength converted light emitting apparatus comprising a substrate, a light emitting diode, and a phosphor layer. The substrate is formed at its upper surface with first and second conductive patterns. At a partial region of the first conductive pattern and at the second conductive pattern are...

20060102914 - Wide emitting lens for led useful for backlighting: Lenses and certain fabrication techniques are described. A wide-emitting lens refracts light emitted by an LED die to cause a peak intensity to occur within 50-80 degrees off the center axis and an intensity along the center axis to be between 5% and 33% of the peak intensity. The lens...

20060102919 - Display device and electronic appliance using the same: The present invention provides a display device including a nonvolatile memory circuit to which data can be added without increasing the number of manufacturing steps, and an electronic appliance using the display device. A display device of the present invention has a memory circuit that includes a memory element with...

20060102921 - High-brightness gallium-nitride based light emitting diode structure: A GaN-based LED structure is provided so that the brightness and lighting efficiency of the GaN-based LED are enhanced effectively. The greatest difference between the GaN-based LEDs according to the invention and the prior arts lies in the addition of a thin layer on top of the traditional structure. The...

20060102918 - Package structure of a surface mount device light emitting diode: A surface mount device (SMD) light emitting diode (LED) package structure is disclosed. The structure includes a cup-structure substrate, a lead frame, an LED chip, a set of conducting wires, and a transparent or semi-transparent seal. The inner or outer surface of the cup-structure substrate includes a plurality of indentations...

20060102917 - Semiconductor light emitting device, method for producing the same and reflector for semiconductor light emitting device: A semiconductor light emitting device comprises a metallic support plate 1; a light-reflective reflector 3 mounted on the support plate 1 and formed with a hole 3a; a semiconductor light emitting element 2 mounted on the support plate 1 within the hole 3a of the reflector 3, and a plastic...

20060102920 - Thin film electrode for forming ohmic contact in light emitting diodes and laser diodes using nickel-based solid solution for manufacturing high performance gallium nitride-based optical devices, and method for fabricating the same: Disclosed herein is a technique for forming a high quality ohmic contact utilizable in the fabrication of short-wavelength light emitting diodes (LEDs) emitting blue and green visible light and ultraviolet light, and laser diodes (LDs) using a gallium nitride (GaN) semiconductor. The ohmic contact is formed by depositing a nickel...

20060102922 - Led heat dissipation support: A light emitting diode chip carrier to improve heat dissipation by providing a thicker heat dissipation area between two supports that carry the light-emitting chip; and heat absorption and dissipation results by the metallic material help absorb the heat generated by the acting light emitting chip for the LED to...

20060102923 - Optical element housing package: In a package for housing an optical element, if the size of an optical element chip and of a metal cap increase, the flatness of a flange of the metal cap can be maintained when the metal cap is bonded by seam welding to the package body, and the optical...

20060102926 - Compound semiconductor device and the fabricating method of the same: A GaN layer functions as an electron transit layer and is formed to exhibit, at least at a portion thereof, A/B ratio of 0.2 or less obtained by a photoluminescence measurement, where “A” is the light-emission intensity in the 500-600 nm band, and “B” is the light-emission intensity at the...

20060102924 - Diboride single crystal substrate, semiconductor device using this and its manufacturing method: Disclosed are a diboride single crystal substrate which has a cleavage plane as same as that of a nitride compound semiconductor and is electrically conductive; a semiconductor laser diode and a semiconductor device using such a substrate and methods of their manufacture wherein the substrate is a single crystal substrate...

20060102925 - Light emitting diode structure and manufacturing method thereof: A LED structure including an epitaxy substrate, a semiconductor layer, a first bonding pad and a second bonding pad, is provided. The epitaxy substrate has a through hole and the semiconductor layer is disposed on the epitaxy substrate. The semiconductor layer includes a first type doped semiconductor layer, a light-emitting...

20060102927 - Switching element, line-switching device and logic circuit: A switching element for ON/OFF switching includes a pair of electrodes provided on a substrate separately from each other, a phase change film contacting the electrodes and having its resistance varied in accordance with the history of heating, and a heating mechanism for heating the phase change film....

20060102928 - Method of manufacturing semiconductor device and the semiconductor device manufactured by the method: The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that...

20060102929 - Field-effect transistor: A field plate portion (5) overhanging a drain side in a visored shape is formed in a gate electrode (2). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed beneath the field plate portion (5). The SiN film (21) is formed so that a...

20060102930 - High-brightness gallium-nitride based light emitting diode structure: A GaN-based LED structure is provided so that the brightness and lighting efficiency of the GaN-based LED are enhanced effectively. The greatest difference between the GaN-based LEDs according to the invention and the prior arts lies in the addition of a thin layer on top of the p-type contact layer...

20060102931 - Field effect transistor having a carrier exclusion layer: A field-effect transistor comprises a substrate, a channel layer over the substrate, a gate insulator, a gate separated from the channel layer by the gate insulator, and a carrier exclusion layer between the channel layer and the gate insulator, wherein the conduction band energy of the carrier exclusion layer is...

20060102932 - Field effect transistor: A semiconductor structure a structure with an enhancement mode transistor device disposed in a first region and depletion mode transistor device disposed in a laterally displaced second region. The structure has a channel layer for the depletion mode and enhancement mode transistor devices. An enhancement mode transistor device InGaP etch...

20060102933 - Iii-v group compound semiconductor light emitting device and manufacturing method thereof: A light emitting device including a III-V group compound semiconductor includes a first stacked body and a second stacked body. The first stacked body includes a III-V group compound semiconductor stacked body, and a reflection layer, a first diffusion suppressing layer and a first metal layer formed on one main...

20060102934 - Semiconductor integrated circuit device: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell....

20060102935 - Transistor-based biosensors having gate electrodes coated with receptor molecules: A device and method are presented for detecting analyte molecules in a medium. At least one FET (Field Effect Transistor) is provided being formed by at least one pair of source-drain electrodes and at least one gate electrode. The gate electrode is coated with a layer of receptor molecules that...

20060102936 - Lead frame for a semiconductor device: A lead frame (100) for a semiconductor device is formed by applying nickel plating (102), palladium plating (103), and gold flash plating (104) substantially entirely to lead frame body (101) such as copper thin plate in this order, and further applying silver plating (105) selectively to part of an inner...

20060102937 - Dielectric line and production method therefor: A dielectric line having a sufficient ensured strength and being suitable for mass production and a production method therefor are provided. The production method is a method for manufacturing a dielectric line having a dielectric strip which is provided between two conductive plates approximately parallel to each other and which...

20060102938 - Cmos image sensor providing uniform pixel exposure and method of fabricating same: An CMOS image sensor includes a photodiode region generating electrical charges in response to incident light received thereat. In one example, the CMOS image sensor further includes first and second transfer gates adapted to prevent or substantially prevent the electrical charges from overflowing into a floating diffusion region or a...

20060102939 - A cmos imager photodiode with enhanced capacitance: A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first...

20060102940 - Semiconductor device having a photodetector and method for fabricating the same: The present invention is directed to a semiconductor device having a photodetector and a method of fabricating the same. The photodetector includes a visible ray absorbing pattern disposed on a top and/or bottom surface of an interconnection formed at a light shielding area between adjacent photodetectors, which prevents obliquely incident...

20060102944 - Ferroelectric capacitor and method of manufacturing the same: A ferroelectric capacitor and a method of manufacturing the same are provided, wherein the ferroelectric capacitor of a semiconductor device, which sequentially includes a lower electrode, a ferroelectric layer, and an upper electrode on a conductive layer connected to a transistor formed on a semiconductor substrate, includes an oxidation preventing...

20060102942 - Ferroelectric memory and method for manufacturing the same: The ferroelectric memory includes a ferroelectric capacitor structure having a ferroelectric layer and formed on a first insulating film, a first barrier film formed to cover the ferroelectric capacitor structure and the first insulating film, a second insulating film formed on the first barrier film, a first buried contact formed...

20060102941 - Semiconductor device: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive...

20060102943 - Structure and manufacturing method of semiconductor memory device: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between...

20060102946 - Dynamic memory cell and method of manufacturing the same: A memory device has a plurality of memory cells, wherein each memory cell has a trench capacitor formed in a semiconductor substrate and an access transistor for it. Each access transistor has a first contact region connected to an internal electrode of the trench capacitor, a second contact region to...

20060102945 - Structure and method for accurate deep trench resistance measurement: A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a pair of deep trenches formed within a semiconductor substrate. The pair of deep trenches has a dielectric material formed on side and bottom surfaces thereof, and includes a conductive fill material therein....

20060102947 - Integration of silicon carbide into dram cell to improve retention characteristics: A DRAM memory cell and a method of making a DRAM memory cell are provided. The DRAM memory cell includes a semiconductor substrate, including a trench formed therein and a buried plate region, at least a first doped region and a second doped region provided on a sidewall of the...

20060102948 - Method of fabricating flash memory: A method of fabricating a flash memory is provided. The method includes forming a mask layer with first openings on the substrate. A tunneling dielectric layer is formed at bottom in the first openings. Strips of conductive spacers are formed on sidewalls of the first openings, and source/drain regions are...

20060102949 - Strapping word lines of nand memory devices: Conductive straps are connected to a subset of word lines of a memory device. Alternatively, first conductive straps are respectively connected only to first portions of first word lines of a memory device, and second conductive straps are respectively connected only to second portions of second word lines of the...

20060102950 - Semiconductor device including nonvolatile memory and method for fabricating the same: A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of...

20060102951 - Nonvolatile memory device and method for manufacturing the same: The present invention discloses a nonvolatile memory device which can improve the data storage capacity without increasing the surface area of the device, and a method for manufacturing the same. The nonvolatile memory device comprises: a gate of a stack type structure formed on an active region of a semiconductor...

20060102952 - Non-volatile memory devices with charge storage insulators and methods of fabricating such devices: A non-volatile memory device comprises a cell region defined at a substrate and a plurality of device isolation layers formed in the cell region to define a plurality of active regions. A charge storage insulator covers substantially the entire top surface of the cell region. A plurality of gate lines...

20060102953 - Semiconductor apparatus and method of manufacturing the same: A semiconductor apparatus includes a semiconductor substrate of a first conductivity type, a base region of a second conductivity type formed on a principal surface of the semiconductor substrate, a trench formed in a periphery of the base region, and an endless source region of the first conductivity type formed...

20060102954 - Organic thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; depositing an ITO layer at a temperature of about 20-35° C.; etching the ITO layer to form a data...

20060102955 - Semiconductor device employing an extension spacer and a method of forming the same: A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally...

20060102956 - Etch-stop layers for patterning block structures for reducing thermal protrusion: The present invention provides a thin-film structure that includes an etch-stop layer having a first side and a second side, a patterned compensation layer for dissipating thermal energy, and an etch-vulnerable layer, where the etch-stop layer substantially impedes etching. The patterned compensation layer is adjacent the first side of the...

20060102957 - Ser immune cell structure: A semiconductor chip is provided, which includes a memory device formed in a deep NWELL region. The memory device includes a memory cell. The memory cell includes a first storage node and a second storage node. The memory cell also includes a first resistor and a second resistor electrically connected...

20060102958 - Systems and methods for voltage distribution via multiple epitaxial layers: Systems and methods for voltage distribution via multiple epitaxial layers. In accordance with a first embodiment of the present invention, an integrated circuit comprises a wafer substrate of a connectivity type. A first epitaxial layer of a connectivity type is disposed upon a second epitaxial layer of an opposite connectivity...

20060102959 - Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same: Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same are provided. The semiconductor integrated circuit devices include an interlayer insulating layer formed on a semiconductor substrate and a single crystalline semiconductor plug penetrating the interlayer insulating layer. A single crystalline semiconductor body pattern...

20060102961 - Semiconductor device: At an element formation surface side of a p-type Si substrate, a digital circuit and an analog circuit are provided. The analog circuit includes a p-type well and n-type wells formed at the element formation surface side of the p-type Si substrate. The analog circuit includes a deep n-type well...

20060102960 - Systems and methods for voltage distribution via epitaxial layers: Systems and methods for voltage distribution via epitaxial layers. In accordance with a first embodiment of the present invention, an integrated circuit comprises an epitaxial layer of a connectivity type disposed upon a wafer substrate of an opposite connectivity type....

20060102962 - Semiconductor device and manufacturing method therefor: A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate insulation film, the area of the second gate electrode on the surface of the semiconductor substrate being larger than that...

20060102963 - Passive device and method for forming the same: An integrated circuit includes an active device, having a metal gate electrode, disposed on a substrate. A passive device, made of a semiconductor material, is disposed adjacent to the active device above the substrate. A dielectric layer is interposed between the passive device and the substrate for separating the same....

20060102964 - Passive device and method for forming the same: An integrated circuit includes an active device, having a metal gate electrode, disposed on a substrate. A passive device, made of a semiconductor material, is disposed adjacent to the active device above the substrate. A dielectric layer is interposed between the passive device and the substrate for separating the same....

20060102966 - Printable non-volatile passive memory element and method of making thereof: Passive memory devices comprising a support having at least one conductive surface or surface layer and having on at least one side of the support a passive memory element, the passive memory element comprising a first electrode system, an insulating system and a second electrode system, wherein the first electrode...

20060102965 - Semiconductor device: There is provided a semiconductor device which includes a projecting semiconductor layer provided on a substrate and having a first side surface and a second side surface opposed to the first side surface, a first gate insulating film provided on the semiconductor layer, a first gate electrode provided on the...

20060102967 - Semiconductor integrated circuit: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch...

20060102968 - Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide: A semiconductor structure is provided that includes a Vt stabilization layer between a gate dielectric and a gate electrode. The Vt stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with...

20060102971 - Magnetic random access memory with lower switching field: A magnetic random access memory with lower switching field is provided. The memory includes a first antiferromagnetic layer, a pinned layer formed on the first antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, a ferromagnetic free layer formed on the tunnel barrier layer, and a multi-layered metal...

20060102970 - Methods and structures for electrical communication with an overlying electrode for a semiconductor element: Structures for electrical communication with an overlying electrode for a semiconductor element and methods for fabricating such structures are provided. The structure for electrical communication with an overlying electrode comprises a first electrode having a lateral dimension, a semiconductor element overlying the first electrode, and a second electrode overlying the...

20060102969 - Spin scattering and heat assisted switching of a magnetic element: A method and system for providing a magnetic element is disclosed. The magnetic element include providing a pinned layer, a spacer layer, and a free layer. The method and system also include providing a heat assisted switching layer and a spin scattering layer between the free layer and the heat...

20060102972 - Optoelectronic devices, solar cells, methods of making optoelectronic devices, and methods of making solar cells: The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator being silicon-enriched silicon oxide and silicon-enriched silicon nitride), and includes solar cells containing one or more layers of semiconductor-enriched insulator. The invention also includes methods of forming optoelectronic devices and solar cells....

20060102973 - Photo-sensor and pixel array with backside illumination and method of forming the photo-sensor: An imaging sensor with an array of FET pixels and method of forming the imaging sensor. Each pixel is a semiconductor island, e.g., N-type silicon on a Silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode, e.g., a P-well cathode. A color filter may be attached to...

20060102974 - Contact image capturing structure: The present invention provides a contact image capturing structure comprising a substrate having a circuit layer, a detect chip located on the substrate and electrically connected to the circuit layer, a frame located on the substrate and surrounding the detect chip, a cavity is formed between the frame and the...

20060102975 - Semiconductor device structure and fabrication process: A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer...

20060102976 - Photovoltaic component and module: A photovoltaic component with a silicon wafer that has a basic doping, a light-receiving side, and an electric bonding side opposite the light-receiving side. At least one interdigital semiconductor structure is arranged on the electric bonding side. The interdigital semiconductor structure has at least one n-type semiconductor part-structure and at...

20060102977 - Low temperature process for polysilazane oxidation/densification: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane...

20060102978 - Semiconductor component with trench insulation and corresponding production method: The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation (STI, TTI) having a deep isolation trench with a covering insulation layer (10, 11), a side wall insulation layer (6) and an electrically conductive filling layer (7), which is electrically connected...

20060102979 - Sti structure and fabricating methods thereof: An STI structure and fabricating method thereof are disclosed. The STI fabricating method comprises forming a pad oxide layer and a first nitride layer on a substrate. A trench is formed by etching the first nitride layer, the pad oxide layer and the substrate. An oxide and a second nitride...

20060102980 - Semiconductor device: A semiconductor chip 100 includes a logic unit and an analog unit 153. Furthermore, the semiconductor chip 100 includes a silicon substrate 101; a first insulating film 123 to a sixth insulating film 143 formed on the silicon substrate 101; and an annular seal ring 105 consisting of a first...

20060102981 - Driving circuit: A driving circuit and a data-line driver is provided which are capable of improving the tolerance to noise between adjacent terminals by using a conventional CMOS process while keeping the chip size small, because a high-density N-diffusion layer (116) is provided in an isolation region (115) to minimize a collector...

20060102982 - Antifuse structure having an integrated heating element: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a...

20060102983 - Semiconductor device having a stacked capacitor: A stacked capacitor in a memory cell has a bottom electrode made of a metal or metal compound, a capacitor insulation film and a top electrode made of a metal or a metal compound. The capacitor insulation film includes an aluminum oxide film having a thickness of 2 to 4...

20060102984 - Passivation structure with voltage equalizing loops: A semiconductor device which includes a passivation structure formed with a conductive strip of resistive material that crosses itself once around the active region of the device to form a first closed loop, a continuous strip that loops around the first closed loop without crossing itself which crosses itself a...

20060102985 - Selection of optimal quantization direction for given transport direction in a semiconductor device: A technique for selecting an optimal quantization direction for a given transport direction in a semiconductor device such as a field effect transistor (FET), a method for preparing a wafer for fabricating such a semiconductor device, and the semiconductor device fabricated by the method. A switching time is calculated for...

20060102986 - Forming a reticle for extreme ultraviolet radiation and structures formed thereby: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a plurality of openings in a portion of a first side of a substrate, bonding a first silicon layer of a silicon on insulator wafer to the first side of the substrate, wherein the silicon on...

20060102987 - Marking method and sheet for both protective film forming and dicing: The invention provides a marking method in which marking is performed on a protective film formed on a work with a high accuracy while suppressing a warpage and, also, a sheet for both protective film forming and dicing which is advantageously used in the method. The marking method comprises irradiating...

20060102988 - Method for manufacturing a silicon-on-insulator (soi) wafer with an etch stop layer: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these...

20060102989 - Integrated circuit package system with leadframe substrate: A system for manufacturing an integrated circuit package system is provided. A dual-type leadframe having first and second rows of leads is formed. A first row of bumps is formed on an integrated circuit chip. Solder paste is placed on the first row of leads, and the first row of...

20060102990 - Carrier for substrate film: The invention relates to a carrier for supporting a substrate film during the chip-substrate assembly and bonding process. The carrier provides enhanced rigidity to the substrate film. The degree of rigidity and/or flexibility provided can be controlled by selection of the carrier dimensions, configuration and material choice. Advantages of embodiments...

20060102991 - Semiconductor apparatus: A semiconductor apparatus according to the present invention comprises a support member that has a recessed portion, one pair of positive and negative conductive wiring members that are provided on the support member, a semiconductor device that is electrically connected to the conductive wiring members and is disposed in the...

20060102992 - Multi-chip package: A multi-chip package includes a substrate having first and second substrate pads, ball pads electrically connected to the first and second substrate pads, a first chip attached on the substrate and having first chip pads flip-chip bonded to the first substrate pads, and a second chip attached on the first...

20060102995 - Apparatus for stacking electrical components using insulated and interconnecting via: An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on...

20060102998 - Flip-chip component: A flip-chip component includes a chip with pads located on the chip and a chip frame, wherein the chip frame is arranged around the chip and is attached to the chip so that the active surface of the chip is substantially planar with a surface of the chip frame. A...

20060102993 - Method and apparatus for stacking electrical components using via to provide interconnection: An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on...

20060102994 - Multi-chip semiconductor package and fabrication method thereof: A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper...

20060102997 - Semiconductor module and method of manufacturing the same: A semiconductor module and a method of manufacturing a semiconductor module including at least one chip package, at least one module board, at least one conductive element provided between the first chip package and the module board and a protector for applying pressure to the conductive element, the module board,...

20060102996 - Stack package using anisotropic conductive film (acf) and method of making same: Provided is a stack package using an anisotropic conductive film (ACF) for reducing thermal stresses exerted on chip scale packages (CSPs) during the initial manufacture of stack packages from a plurality of CSPs and for facilitating the repair and/or rework of stack packages incorporating CSPs while reducing the likelihood of...

20060102999 - Mechanical assembly for regulating the temperature of an electronic device, having a spring with one slideable end: A mechanical assembly, for regulating the temperature of an electronic device, includes a gimbal and a heat-exchanger which is attached to the gimbal. The gimbal includes a base member, a carrier member, and a spring which has—1) a first end with a rigid coupling to one of the base and...

20060103000 - Electronic device package and electronic equipment: This electronic device package includes a substrate upon which an electronic device is mounted, a plurality of device electrodes which are formed upon an electronic device, a plurality of substrate electrodes which are formed upon the substrate, and a plurality of connection lines, formed by a liquid drop ejection method,...

20060103001 - Configuration terminal for integrated devices and method for configuring an integrated device: A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that...

20060103002 - Semiconductor packages with asymmetric connection configurations: Provided are semiconductor devices and methods for configuring lead frames and/or device bonding pads to provide for the independent adjustment of the electrical characteristics of both fixed voltage lines, e.g., Vdd and Vss, and the signal lines, e.g., command, clock, data and address. In particular, the invention provides for adjusting...

20060103003 - Modular construction component with encapsulation: The invention concerns an ultrahigh frequency module, in particular a microwave or millimeter wave module, as well as a technique for housing such parts. The ultrahigh frequency module contains, for example, a) an active individual component, that in particular includes a diode, a transistor or an integrated circuit, and b)...

20060103004 - Wiring board for semiconductor integrated circuit package and semiconductor integrated circuit device using the same: It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board for a package, which comprises, on...

20060103005 - Metal-ceramic substrate for electric circuits or modules, method for producing one such substrate and module comprising one such substrate: The invention relates to a metal-ceramic substrate for electric circuits or modules, said substrate comprising a ceramic layer which is provided with at least one metallic layer of a first type applied to a surface of said ceramic layer in a plane manner. An insulating layer consisting of a glass-containing...

20060103006 - Substrate design to improve chip package reliability: A substrate design to improve chip package reliability is provided. The chip package includes a substrate having a ceramic layer formed in a recess. A die is attached to the substrate on the ceramic layer. The substrate may be attached to a printed circuit board. The substrate may be fabricated...

20060103007 - Heater for annealing trapped charge in a semiconductor device: A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heating element is formed within the bulk layer. A first...

20060103008 - Hyper thermally enhanced semiconductor package system: A semiconductor package system is provided including mounting a semiconductor chip to a substrate having a substrate opening. A first heat slug is attached to a first surface of the semiconductor chip at least partially encapsulating the semiconductor chip. A second heat slug is attached to the second surface of...

20060103009 - Integrated circuit package system with heat slug: An integrated circuit package system is provided including providing a substrate having a die attached and electrically bonded thereto. The system includes forming heat slug pillars on the substrate, positioning a heat slug on the heat slug pillars, and encapsulating the substrate, the die, the heat slug pillars, and the...

20060103010 - Semiconductor package system with substrate heat sink: A semiconductor package system is provided including: providing a substrate having substrate wiring and a cavity provided therein with a heat sink foil closing off the cavity; attaching a semiconductor die in the cavity to the heat sink foil; and bonding the semiconductor die to the substrate wiring....

20060103011 - Apparatus and methods for cooling semiconductor integrated circuit chip packages: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for...

20060103014 - Heat dissipating packages structure and method for fabricating the same: A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; an encapsulant formed on the chip carrier and for encapsulating the chip, with a non-active surface of the chip being exposed from the encapsulant; and a heat spreader having a...

20060103015 - Multi-chip electronic package and cooling system: A multi-chip electronic package comprised of a plurality of integrated circuit chips secured together in a stack formation. The chip stack is hermetically sealed in an enclosure. The enclosure comprises a pressurized, thermally conductive fluid, which is utilized for cooling the enclosed chip stack. A process and structure is proposed...

20060103012 - Solid-state semiconductor light emitting device: A solid-state semiconductor light emitting device is disclosed. A heat sink that comprises a receiving cup for receiving a chip is provided. A leadframe that comprises a connection base is mounted above the heat sink, wherein the chip is connected to the leadframe via a metal wire and a resin...

20060103013 - Techniques for cooling a circuit board component within an environment with little or no forced convection airflow: A dimpled heat spreader includes a central portion configured to couple to the circuit board component, an outer portion coupled to the central portion, and dimpled portions disposed within the outer portion. The outer portion is configured to extend from the central portion and support the dimpled portions beyond a...

20060103016 - Heat sinking structure: High performance integrated circuits generally have high heat generating capabilities. During powering up of these integrated circuits under typical operating conditions, heat generation is unavoidably accelerated. When the accumulated heat is not adequately dissipated, the high temperature of the integrated circuits will lead to overheating which in turn, causes irreversible...

20060103017 - Semiconductor device: A semiconductor device which comprises a wiring structure capable of reducing stress concentration at a boundary between a wiring and a low dielectric constant insulator even when the low dielectric constant insulator is used as an interlevel or interwiring insulator in a multilevel wiring, suppressing peeling-off of the insulator and...

20060103018 - Coating support and method for the selective coating of conductive tracks on one such support: The present invention concerns a lining support comprising a plurality of conductive pads (12) associated with a shared addressing contact (18) and means of selecting at least one pad to be lined by electrochemical means among the plurality of pads. In accordance with the invention, the selection means comprise means...

20060103019 - Socket grid array: Assembly methods and semiconductor device assemblies are disclosed in which corresponding IC sockets and PCB projections are used for alignment and bond formation between IC and PCB components of a completed assembly, for example, a BGA. Embodiments of the invention further provide the capability of disassembly and reassembly....

20060103021 - Bga package having substrate with exhaust hole: The present invention relates to a BGA package having a substrate with an exhaust hole. The BGA package comprises the substrate, a chip and a molding compound. The substrate comprises a plurality of plated through holes electrically connecting an upper surface and a lower surface of the substrate. At least...

20060103020 - Redistribution layer and circuit structure thereof: A circuit structure of a redistribution layer (RDL) is suitable for a chip to define the circuits and the contact window required by the following bump process. The RDL is disposed on the active surface of the chip. The circuit structure of the RDL mainly includes a first titanium layer,...

20060103022 - Semiconductor device with superimposed poly-silicon plugs: A semiconductor device includes a first insulating layer; a first poly-silicon plug formed in the first insulating layer; a second insulating layer, formed on the first insulating layer; and a second poly-silicon plug that is formed in the second insulating layer. At least one of the first and second insulating...

20060103023 - Methods for incorporating high k dielectric materials for enhanced sram operation and structures produced thereby: A hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip is described. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin...

20060103025 - Semiconductor device including sealing ring: A semiconductor device includes a low dielectric constant film having a copper interconnection formed therein, a silicon oxide film arranged above the low dielectric constant film, a surface protection film arranged above the silicon oxide film, a sealing ring formed to surround a circuit forming region, and a groove portion...

20060103024 - Tiled construction of layered materials: A method is described for combining the diverse strengths of two materials in a tiled film construction. The first material provides a foundation of intersecting grid lines on a substrate and the second material is contained within the grid lines and has a valued property for a particular application. In...

20060103026 - Amorphous carbon-based non-volatile memory: A resistance variable memory element and a method for forming the same. The memory element has an amorphous carbon layer between first and second electrodes. A metal-containing layer is formed between the amorphous carbon layer and the second electrode....

20060103027 - Electronic component and method for manufacturing the same: A method for manufacturing an electronic component includes: cutting a wiring substrate along a line intersecting with an outline of a reinforcing member, the wiring substrate including a base substrate, a wiring pattern provided to a first surface of the base substrate, and the reinforcing member provided to a second...

20060103028 - Electronic component unit: The present invention is an electronic part device in which a semiconductor element (flip chip) (3) is mounted on a wiring circuit substrate (1) under such a state that an electrode part for connection (joint ball) disposed on the semiconductor element (flip chip) (3) and a circuit electrode (5) disposed...

20060103029 - Flip chip system with organic/inorganic hybrid underfill composition: A system for underfilling in a chip package includes an underfill mixture that ameliorates the CTE mismatch that typically exists between a packaged die and a resin-impregnated fiberglass mounting substrate. In one embodiment, the system includes an underfill mixture that comprises a principal underfill composition of a rigid octaaminophenyl silsesquioxane...

20060103030 - Module substrate and disk apparatus: A module substrate includes an insulating substrate, a circuit pattern formed on at least a main surface of the insulating substrate, a protection film formed on the main surface of the insulating substrate including the circuit patter such as to expose a mount region of the circuit pattern, an active...

20060103031 - Semiconductor chip capable of implementing wire bonding over active circuits: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure, a metal-metal capacitor formed by at least a pair of metal electrodes on the same plane underneath the bonding pad structure, at least an interconnection metal layer, at...

20060103032 - Die attach material for tbga or flexible circuitry: An attachment material is provided between the die and the solder balls of a TBGA or other flexible circuitry package that is sufficiently compliant to absorb pressure between the two, so as not to apply stress to the solder balls. The attachment material is also sufficiently rigid, with a low...

20060103033 - Marker structure and method for controlling alignment of layers of a multi-layered substrate: The invention includes a lithographic system having a first source for generating radiation with a first wavelength and an alignment system with a second source for generating radiation with a second wavelength. The second wavelength is larger than the first wavelength. A marker structure is provided having a first layer...

20060103034 - Overlay mark for a non-critical layer of critical dimensions: An overlay mark for monitoring the critical dimension of a non-critical layer, comprising four first bars which are bar-shaped and separated from each other. The four first bars enclose to form a rectangle, and each first bar is correspondingly parallel to each side of the rectangle. The four second bars,...

20060103035 - Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor device: Disclosed are a semiconductor wafer, a semiconductor device, and a method of manufacturing the semiconductor device, which are capable of easily carrying out an alignment between a semiconductor substrate and an electron beam exposure apparatus. There is provided a method including steps of: forming an interlayer insulating film 25 on...

20060097239 - Multilevel phase-change memory, manufacture method and operating method thereof: A multilevel phase-change memory, manufacture method and operating method thereof are provided. The memory includes a first phase change layer, a second phase change layer, a first heating layer formed on one surface of the first phase change layer, a second heating layer formed between the first heating layer and...

20060097238 - Non-volatile memory element and production method thereof and storage memory arrangement: A nonvolatile memory element and to associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for...

20060097240 - Programmable matrix array with chalcogenide material: A memory element, a threshold switching element, or the series combination of a memory element and a threshold switching element may be used for coupling conductive lines in an electrically programmable matrix array. Leakage may be reduced by optionally placing a breakdown layer in series with the phase-change material and/or...

20060097241 - Novel class of superlattice materials and superlattice precursors, and method for their manufacture and use: The present disclosure concerns novel materials comprising at least two crystalline materials. In certain embodiments, at least one of the crystalline materials is a diffusion barrier, and at least one material has a high power factor. The disclosed materials are particularly useful as superlattices, particularly thermoelectric superlattices, and superlattice precursors....

20060097242 - Semiconductor light-emitting device: The present invention provides a semiconductor light-emitting device which exhibits small threshold current, high differential efficiency and good characteristics, by reducing electrons that overflow an electron barrier for trapping the electrons in an active layer. Of barrier layers that configure an active layer 20, a final barrier layer 1, which...

20060097243 - Semiconductor array and method for manufacturing a semiconductor array: A method for manufacturing a semiconductor array, particularly a high-frequency bipolar transistor, is provided, the method includes process steps, so that a dielectric is produced on a monocrystalline, first semiconductor region of a first conductivity type, a silicide layer is deposited and patterned in such a way that the silicide...

20060097244 - Optical enhancement of integrated circuit photodetectors: A semiconductor integrated circuit structure and method for fabricating. The semiconductor integrated circuit structure includes a light sensitive device integral with a semiconductor substrate, a cover dielectric layer disposed over the light sensitive device, and a lens-formation dielectric layer disposed over the cover dielectric layer. Light is transmittable though the...

20060097245 - Light emitting diode component: In a lighting package, a printed circuit board supports at least one light emitting die. A light transmissive cover is disposed over the at least one light emitting die. A phosphor is disposed on or inside of the light transmissive dome-shaped cover. The phosphor outputs converted light responsive to irradiation...

20060097249 - Composition for thermosetting organic polymeric gate insulating layer and organic thin film transistor using the same: Provided are a composition for thermosetting organic polymeric gate insulating layer and an organic thin film transistor using the same. The composition for thermosetting organic polymeric gate insulating layer contains a thermosetting material in polyvinyl phenol as an organic polymeric gate insulating layer material, to improve a chemical resistance and...

20060097248 - Compound having anchoring group, electronic device comprising the compound, and methods of producing them: o

20060097251 - Organic light emitting device and method of fabricating the same: In an organic light emitting device and method of fabricating the same, a hole is formed in a reflecting layer formed below a first electrode or the reflecting layer itself is patterned to form a reflecting layer pattern, and an opening is formed in the reflecting layer positioned below the...

20060097246 - Passive device structure: A method including forming a ceramic material directly on a sheet of a first conductive material; forming a second conductive material on the ceramic material; and sintering the ceramic material. A method including forming a ceramic material directly on a sheet of a first conductive material; forming a second conductive...

20060097247 - Photodetector using nanoparticles: The present invention relates to a photodetector using nanoparticles, and more particularly, to a novel photodetector wherein surfaces of nanoparticles synthesized by a wet colloidal process are capped with organic materials which then serve as channels for electron migration, or nanoparticles, from which organic materials capped on the surfaces of...

20060097250 - Semiconductor device, ic card, ic tag, rfid, transponder, paper money, valuable securities, passport, electronic device, bag, and clothes: It is an object to provide a semiconductor device the data writing of which can be performed except in manufacturing and the counterfeiting of which by rewriting can be prevented. Furthermore, it is another object of the invention to provide a semiconductor device constituted by an organic memory having a...

20060097252 - Interconnect including a pliable surface and use thereof: The present invention provides an interconnect. The interconnect comprises a pliable surface having a plurality of nanostructures disposed thereon, the pliable surface configured to allow the plurality of nanostructures to at least partially conform to a surface when the nanostructures come into contact therewith....

20060097253 - Structured semiconductor element for reducing charging effects: A semiconductor circuit element for reducing undesirable charging effects for a connection element of test structures for semiconductor circuits is disclosed. A surface of a semiconductor circuit element has interconnect structures that are electrically insulated from the remainder of the surface of the semiconductor circuit element, where exclusively the interconnect...

20060097254 - Organic thin-film transistor, method of fabricating the same, and flat panel display having the same: The present invention relates to an organic thin film transistor (OTFT), a method of fabricating the OTFT, and an organic electroluminescent display that has the OTFTs. The invention prevents surface damage of an organic semiconductor layer and reduces an off-current. The OTFT includes a substrate, a source electrode and a...

20060097256 - Electro-optical device and electronic device: The switching TFT 201 formed within a pixel has a multi-gate structure, which is a structure which imposes an importance on reduction of OFF current value. Further, the current control TFT 202 has a channel width wider than that of the switching TFT to make a structure appropriate for flowing...

20060097257 - Method of forming electrode for plasma display panel: A method of forming an electrode for a plasma display panel, in which the method includes the steps of forming a first metal film on a second metal film after formation of the second metal film on a substrate, forming a resist pattern on the laminated metal films, and etching...

20060097258 - Semiconductor device and manufacturing method thereof: By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase...

20060097255 - Thin film transistor array and repairing method thereof: A thin film transistor array including a plurality of lower electrodes and a plurality of common lines for the storage capacitor of pixels is provided. The plurality of lower electrodes is electrically connected to the plurality of common lines by a connecting conductive layer, and the lower electrodes and the...

20060097260 - Array substrates for use in liquid crystal displays and fabrication methods thereof: Array substrates for use in TFT-LCDs and fabrication methods thereof. A transparent conductive layer, a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer and a sacrificial layer are sequentially formed on a substrate. With a first photomask, a photoresist layer with various thicknesses is...

20060097261 - Liquid crystal display device and method of manufacturing the same: A liquid crystal display device including first and second active layers over a substrate, a storage line over the second active layer, a first insulating layer over the storage line, a gate electrode on the first insulating layer and corresponding to the first active layer, a second insulating layer over...

20060097259 - Thin-film photoelectric converter: A thin film photoelectric converter, especially an integrated thin film photoelectric converter having improved photoelectric conversion efficiency is provided by controlling an open-circuit voltage and a fill factor so as not be small in a thin film photoelectric converter including a crystalline silicon photoelectric conversion unit. The thin film photoelectric...

20060097264 - Light-emitting device having optical resonance layer: Provided is a light-emitting device which has a simple structure and can be manufactured in a simple process, has increased light coupling efficiency and brightness, and can reduce adverse effects of optical resonance on a view angle and emission spectrum. The light-emitting device includes a substrate; a light-emitting diode formed...

20060097263 - Organic electroluminescent display device: An organic electroluminescent display device (OELD) that prevents particles from creating blind spots by forming a recess or a groove in the surface of an insulating layer that covers edges of a pixel electrode. The OELD includes a lower electrode arranged on a substrate, an insulating layer arranged on the...

20060097262 - Thin film transistor array panel: A gate wire and a storage electrode wire extending in a transverse direction are provided, and a data wire extending in a longitudinal direction intersects the gate wire and the storage electrode wire. A plurality of pixel electrodes and a plurality of TFTs are provided on pixel areas defined by...

20060097265 - Thin film transistor array panel and method for manufacturing the same: Disclosed is a thin film transistor array panel comprising an insulating substrate and a gate line formed on the insulating substrate. The gate line includes a first metal layer that contains aluminum (Al), a first cover layer formed on the gate line and a gate insulating layer formed on the...

20060097266 - Large-diameter sic wafer and manufacturing method thereof: From the viewpoint of manufacturing an SiC semiconductor device economically, a present Si device manufacturing line is utilized to make it possible to handle a small-diameter SiC wafer. Polycrystal SiC is grown from at least one surface side of a small-diameter a-SiC single crystal wafer so as to be in...

20060097267 - Silicon carbide semiconductor device and method for manufacturing the same: A method for manufacturing a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate and first to third semiconductor layers; forming a trench in a cell region of the semiconductor substrate; forming a fourth semiconductor layer in the trench; forming an oxide...

20060097268 - Silicon carbide semiconductor device and method for manufacturing the same: A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and...

20060097269 - Method and structure for improved led light output: The efficiency of LEDs is increased by incorporating multiple active in series separated by tunnel junction diodes. This also allows the LEDs to operate at longer wavelengths....

20060097270 - Semiconductor light-emitting device, method for fabricating the same, lighting module and lighting apparatus having semiconductor light-emitting device: A semiconductor light-emitting device includes: a support; a semiconductor light-emitting element bonded to the support and comprising a first electrode, a second electrode, and a semiconductor layer including at least an active layer, at least one of the first and second electrodes overlying the semiconductor layer; and a wiring metal...

20060097271 - Gan-based radiation-emitting thin-layered semiconductor component: A radiation-emitting thin-film semiconductor component with a multilayer structure (12) based on GaN, which contains an active, radiation-generating layer (14) and has a first main area (16) and a second main area (18)—remote from the first main area—for coupling out the radiation generated in the active, radiation-generating layer. Furthermore, the...

20060097272 - High light efficiency of gan-series of light emitting diode and its manufacturing method thereof: A high light efficiency of GaN-series of light emitting diode and its manufacturing method thereof disclose a process and structure of a p-type semiconductor layer of surface texture structure generation. The optical waveguide effect can be interrupted and the possibility of hexagonal shaped pits defect generated can be reduced through...

20060097273 - Structure of gan light-emitting diode: A GaN LED structure with a short period superlattice contacting layer is provided. The LED structure comprises, from the bottom to top, a substrate, a double buffer layer, an n-type GaN layer, a short period superlattice contacting layer, an active layer, a p-type shielding layer, and a contacting layer. The...

20060097275 - Full-color active matrix organic electroluminescent device, fabrication method thereof and electronic devices employing the same: A full-color active matrix organic electroluminescent device and fabrication method thereof. The full-color active matrix organic electroluminescent device includes a substrate with a plurality of TFTs, a buffer layer formed on the substrate beyond the TFTs, a color filter formed on the buffer layer, a flat layer formed on the...

20060097274 - Light emitting device and method for fabricating the same: A light emitting device and a method for fabricating the same according to the present invention are advantageous in that since an LLO (Laser Lift Off) process is performed using a thick metal film grown through a growth process, an occurrence rate of a void is remarkably decreased due to...

20060097276 - Flip chip type led lighting device manufacturing method: A flip chip type LED lighting device manufacturing method includes the step of providing a strip, the step of providing a submount, the step of forming a metal bonding layer on the strip or submount, the step of bonding the submount to the strip, and the step of cutting the...

20060097277 - Method of fabricating vertical devices using a metal support film: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal techniques. Trenches that define the boundaries of the individual devices are formed through the semiconductor layers and into the insulating substrate, beneficially by inductive...

20060097278 - Gan semiconductor device: A GaN-based semiconductor laser device (50) is disclosed as an example of the GaN-based semiconductor light emitting device, and it is a semiconductor laser device having a structure such that a p-side electrode and an n-side electrode are provided on a multilayer structure of GaN-based compound semiconductor layers. The GaN-based...

20060097279 - Three-dimensional memory system-on-a-chip: The present invention discloses a three-dimensional memory (3D-M) system-on-a-chip (3DM-SoC) with half-3DM level(s), whose un-used space above the embedded memory is converted into 3D-M level(s). This conversion process, incurring little extra manufacturing cost, can significantly increase the SoC storage capacity. The present invention further discloses a 3DM-SoC with large basic...

20060097280 - Semiconductor diode and method for the production thereof: In a semiconductor system 20 made up of multiple sublayers, a sublayer over the largest part of a cross-sectional area BC in the interior of the semiconductor system borders immediately on the first sublayer, while bordering on a second sublayer only in a comparatively narrow edge region of the cross-sectional...

20060097281 - Strained semiconductor by wafer bonding with misorientation: One aspect of the present invention relates to a method for forming a strained semiconductor structure. In various embodiments, at least two strong bonding regions are defined for a desired bond between a crystalline semiconductor membrane and a crystalline semiconductor substrate. The two strong bonding regions are separated by a...

20060097282 - Multi-chip package: A multi-chip package is provided. A first die pad has a first chip attaching surface and a first unoccupied surface. A second die pad has a second chip attaching surface and a second unoccupied surface. The connecting structures are used for connecting the first die pad and the second die...

20060097283 - Group iii-nitride-based compound semiconductor device: In a group III-nitride-based compound semiconductor device 100, an intermediate layer 108 is 5 provided between a p-AlGaN layer 107 and a p-GaN layer 109, to each of which an acceptor impurity is added. On this occasion, the intermediate layer 108 is doped with a donor impurity in a concentration,...

20060097284 - Integrated circuit die with logically equivalent bonding pads: An integrated circuit (IC) die includes two bonding pads, that share a common logical function, such as signal input or signal output, separated by the width of the die, and preferably on opposite sides of the die. System-in-package devices are produced by steps including directly electrically connecting one or the...

20060097285 - Microcomputer chip with function capable of supporting emulation: A microcomputer chip includes a plurality of first electrode pads arranged in a chip circumferential section; a plurality of second electrode pads arranged inside from the plurality of first electrode pads; and an emulation circuit connected with the plurality of second electrode pads to interface with an external unit in...

20060097286 - Pad arrangement of driver ic chip for lcd and related circuit pattern structure of tab package: Output pads on an integrated circuit (IC) chip are arranged along a first longer side and are arranged along a second longer side with input pads. The output pads are connected to respective output patterns formed on top and bottom surfaces of a base film. All the output patterns may...

20060097287 - Semiconductor device and manufacturing method thereof: A semiconductor device of this invention comprises a semiconductor substrate, a plurality of memory regions provided on the semiconductor substrate, the plurality of memory regions having the same structure, and functional region provided on the semiconductor substrate, the functional region including a different function from the memory....

20060097288 - Cross-point nonvolatile memory devices using binary metal oxide layer as data storage material layer and methods of fabricating the same: A cross-point nonvolatile memory device using a binary metal oxide layer as a data storage material layer includes spaced apart doped lines disposed in a substrate. Spaced apart upper electrodes cross over the doped lines such that cross points are formed where the upper electrodes overlap the doped lines. Lower...

20060097289 - Method of forming ultra shallow junctions: A method of forming ultra shallow junctions in p-type devices uses aluminum ion to implant n-doped silicon, followed a low temperature anneal to activate and diffuse the aluminum. The use of aluminum provides numerous advantages over boron such as the ability to form shallower junctions, lower resistivity, and the ability...

20060097290 - Semiconductor structure for imaging detectors: There is disclosed a photo-detector array including a plurality of sub-arrays of photo-detectors, the photo-detectors of each sub-array being formed on a substrate with an active area of each photo-detector being formed on a surface of the substrate, there further being formed for each photo-detector a conductive via through the...

20060097291 - Illuminating device and method of fabricating the same: The illuminating device includes a lens formed of a resin mold and having a portion for receiving an LED which is formed on one surface thereof, the LED received in the receiving portion, and a wiring member deposited on the receiving-portion-forming surface of the lens, and light irradiated from the...

20060097293 - Esd structure: An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the...

20060097292 - Semiconductor device: A semiconductor device includes a second conductivity type layer selectively formed by changing impurity concentrations on a semiconductor substrate, a first conductivity type source region formed on the second conductivity type layer, a first conductivity type drain region formed on the second conductivity type layer apart from the first conductivity...

20060097294 - Semiconductor device and method for fabricating the same: Gate electrodes 5A through 5F are formed to have the same geometry, and protruding parts of the gate electrodes 5A through 5F extend across an isolation region onto impurity diffusion regions. The gate electrode 5B and P-type impurity diffusion regions 7B6 are connected through a shared contact 9A1 to a...

20060097295 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same are disclosed, in which the fabrication costs are reduced by reducing the number of photolithographic processes and yield is improved by obviating an alignment problem between color filter layers and microlenses. In one embodiment, the CMOS image sensor includes...

20060097297 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and fabricating method thereof enhances a light-receiving capability of an image sensor by preventing poor light-refraction characteristics at the peripheral part of a microlens. The CMOS image sensor includes at least one microlens formed by anistropic etching to have a focusing centerline, a central lens portion,...

20060097296 - Cmos image sensor and method of operating the same: A complementary metal oxide semiconductor (CMOS) image sensor and a method for operating the same are provided. The CMOS image sensor includes a pixel array unit having a matrix of pixels, wherein each pixel comprises a charge transfer element for transferring charge collected in a photoelectric conversion element to a...

20060097298 - Magnetic random access memory with reduced currents in a bit line and manufacturing method thereof: A magnetic random access memory with reduced currents in a bit line and a manufacturing method thereof. In one embodiment, the memory includes a bottom electrode, a first dielectric layer on the bottom electrode, a via in the first dielectric layer, a magnetic tunnel junction (MTJ) element that is aligned...

20060097299 - Semiconductor device including capacitor and method of fabricating same: A semiconductor device includes a capacitor having a bottom electrode, a dielectric layer formed on the bottom electrode, a top electrode formed on the dielectric layer, and a contact plug having a metal that is connected with the top electrode, wherein the top electrode includes a doped poly-Si1-xGex layer and...

20060097301 - High density memory devices having improved channel widths and cell size: A memory device having decreased cell size and having transistors with increased channel widths. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the pillars. The current path through the channel is...

20060097300 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate, at least two gate electrode sections formed adjacent to each other on the surface of the semiconductor substrate, a first diffusion region formed in the surface area of the semiconductor substrate, except in the gate electrode sections, a substrate contact layer formed between...

20060097302 - Quantum supercapacitor: A quantum supercapacitor having nanostrucutured material located between electrodes. The material includes clusters with tunnel-transparent gaps. The clusters have sizes within the range of 7.2517 nm≦r≦29.0068 nm, at which the resonant characteristics of the electron are exhibited. The size is determined by the circular radius of the electronic wave according...

20060097303 - Semiconductor device and its manufacturing method: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first...

20060097304 - Semiconductor memory devices including a vertical channel transistor and methods of manufacturing the same: Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain...

20060097305 - Capacitor with zirconium oxide and method for fabricating the same: A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO2) layer and an aluminum oxide (Al2O3) layer; and forming a plate...

20060097306 - Multi bits flash memory device and method of operating the same: A multi bits flash memory device and a method of operating the same are disclosed. The multi bits flash memory device includes: a stacked structure including: a first active layer with a mesa-like form disposed on a substrate; a second active layer, having a different conductivity type from the first...

20060097307 - Nonvolatile semiconductor memory and manufacturing method for the same: The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second...

20060097308 - Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing the multi-bit non-volatile memory device: Disclosed are a muli-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the muli-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper...

20060097309 - Non-volatile semiconductor memory device having memory cell array suitable for high density and high integration: First and second semiconductor regions are formed apart from each other on a semiconductor body. A stacked gate is formed on the semiconductor body between the first and second semiconductor regions. The stacked gate has a first side surface, a second side surface opposed to the first side surface, and...

20060097310 - Non-volatile memory devices including divided charge storage structures and methods of fabricating the same: A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and...

20060097311 - Semiconductor memory device: Flash memory is rapidly decreasing in price. There is a demand for a new memory system that permits size reduction and suits multiple-value memory. A flash memory of AND type suitable for multiple-value memory with multiple-level threshold values can be made small in area if the inversion layer is utilized...

20060097312 - Method for producing a vertical transistor component: Providing a semiconductor substrate (200), applying an auxiliary layer (210) to the semiconductor substrate (200), patterning the auxiliary layer (210) for the purpose of producing at least one trench (214) which extends as far as the semiconductor substrate (200), producing a monocrystalline semiconductor zone (230) in the at least one...

20060097313 - Semiconductor device and method of manufacturing same: A semiconductor device comprises a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar layer of a second conductivity type provided adjacent to the first semiconductor pillar layer; a...

20060097314 - Semiconductor device and method of manufacturing the same: After an element isolation region is formed using a field-forming silicon nitride film, the silicon nitride film and a semiconductor substrate are patterned. Thereafter, the silicon nitride film and the semiconductor substrate are patterned, thereby forming a gate trench reaching the semiconductor substrate in an active region. Next, after a...

20060097315 - Structure and method for strained channel field effect transistor pair having underlapped dual liners: A structure is provided in which a semiconductor device region has a first portion and a second portion, and a device disposed in the first and second portions. A current conducting member extends horizontally over the first portion but not over the second portion. A dielectric region, having a substantially...

20060097316 - Semiconductor structure and method for integrating soi devices and bulk devices: This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on...

20060097317 - Semiconductor substrate and process for producing it: A semiconductor substrate useful as a donor wafer is a single-crystal silicon wafer having a relaxed, single-crystal layer containing silicon and germanium on its surface, the germanium content at the surface of the layer being in the range from 10% by weight to 100% by weight, and a layer of...

20060097318 - Transistor with silicon and carbon layer in the channel region: A transistor and method of manufacturing thereof having stressed material layers formed in the channel to increase the speed and improve performance of the transistor. A layer of silicon and carbon is epitaxially grown in the channel region. A thin semiconductor material may be formed over the layer of silicon...

20060097319 - Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby: Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer...

20060097322 - Electrostatic discharge (esd) protection circuit: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes: a first conductivity type substrate; a second conductivity type well region formed in a predetermined portion of the substrate; a gate structure including a gate insulation layer and a gate electrode stacked on a selected surface portion...

20060097321 - Electrostatic discharge protection device: An electrostatic discharge (ESD) protection device is provided. The apparatus includes: a double diffused drain N-type metal oxide semiconductor field effect transistor (MOSFET); a P-type silicon controlled rectifier (SCR); a double diffused drain P-type MOSFET; and an N-type SCR, wherein: the double diffused drain N-type MOSFET is connected in parallel...

20060097323 - Method and apparatus for preventing microcircuit thermo-mechanical damage during an esd event: A method and apparatus for preventing thermo-mechanical damage to an electrostatic discharge (ESD) protection device is disclosed. The method and apparatus of the invention use materials with superior thermo-mechanical properties, in particular, the Coefficient of Thermal Expansion (CTE), melting temperature, tensile strength and fracture toughness. The thermo-mechanical energy absorber materials...

20060097320 - Protecting element and semiconductor device using the same: Between a terminal of an element to be protected and a GND terminal, a protecting element is connected, which includes a first n+ region, an insulating region and a second n+ region. The first n+ region is provided to have a columnar shape in a depth direction of a substrate,...

20060097324 - Semiconductor integrated circuit and method for designing the same: A first-conductive-type doped layer is provided on a second-conductive-type well, and a gate electrode of a MOS transistor and the first-conductive-type doped layer are connected to each other via a plug for filling a contact hole and a metal interconnect of Cu. Furthermore, a second-conductive-type doped layer is provided on...

20060097325 - One-time programmable read only memory and operating method thereof: A one-time programmable read only memory is provided. The memory includes a substrate, a select transistor, an electrode and a dielectric layer. The select transistor is formed on the substrate. The electrode is formed over the source region of the select transistor. The dielectric layer is formed between the electrode...

20060097326 - Mos transistor circuit: A reduction of a current capability of a MOS transistor (P1) is compensated by dynamically changing a substrate bias of the MOS transistor (P1) in response to a fluctuation of the power supply, and thus an operating speed is stabilized automatically. An NMOS transistor (N2) generates a current (I2) that...

20060097327 - Low resistance semiconductor process and structures: A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along each gate, a plurality of conductive...

20060097328 - Sram cells having landing pad in contact with upper and lower cell gate patterns and methods of forming the same: SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting...

20060097330 - Asymmetrical layout structure for esd protection: A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias...

20060097329 - Fin device with capacitor integrated under gate electrode: A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and...

20060097332 - Semiconductor device, carrier, card reader, methods of initializing and checking authenticity: The semiconductor device has a security coating with embedded magnetic particles and magnetoresistive sensors. This renders possible a measurement of the impedance of security elements defined by magnetoresistive sensors and security coating. If initial values of the impedance are stored, actual values can be compared therewith to see if the...

20060097331 - Sensor device: A sensor device includes a sensor chip having a movable portion on one surface, a circuit chip laminated with the sensor chip to be opposite to the movable portion of the sensor chip, and a bump located between the sensor chip and the circuit chip. In the sensor device, the...

20060097333 - Magnetic memory devices and methods of forming the same: A magnetic memory device includes bottom electrodes disposed on an interlayer dielectric on a substrate. The bottom electrodes are spaced apart from one another in one direction as much as a first distance. A planarized insulation layer fills spaces between the bottom electrodes and has a top surface coplanar with...

20060097334 - Method of manufacturing optical sensor: A cubic element of photonic crystal is integrally formed on the surface of a photo-detection element, and a portion of the photonic crystal cubic element is irradiated with ultraviolet rays thereby to change the refractive index of the portion of the cubic element that has been irradiated with ultraviolet rays....

20060097335 - Electronic package for image sensor, and the packaging method thereof: A semiconductor device package and method for its fabrication are provided. The semiconductor device package generally includes at least one semiconductor die and a substrate coupled to the semiconductor die. The semiconductor die is provided with a front side defining a sealing area, and a first solder sealing ring pad...

20060097336 - High-powered light emitting device with improved thermal properties: A light emitting device includes a first semiconductor layer of a first conductivity type, an active region, and a second semiconductor layer of a second conductivity type. First and second contacts are connected to the first and second semiconductor layers. In some embodiments at least one of the first and...

20060097337 - Methods of conducting wafer level burn-in of electronic devices: Methods of conducting wafer level burn-in (WLBI) of semiconductor devices are presented wherein systems are provided having at least two electrodes (210, 215). Electrical bias (920) and/or thermal power (925) is applied on each side of a wafer (100) having back and front electrical contacts for semiconductor devices borne by...

20060097338 - Temperature-compensated resistor and fabrication method therefor: A method for forming a temperature-compensated resistor on a semiconductor substrate is provided. A resistor element is formed on the semiconductor substrate. Terminal contacts are formed on the ends of the resistor element. A temperature-compensating configuration is formed, and is selected from an enlarged transverse portion in the resistor element...

20060097339 - Integrated circuits including auxiliary resources: In one embodiment, an integrated circuit chip includes a semiconductor substrate, a metal layer formed on the semiconductor substrate, and an unused auxiliary resource that is tied to ground or to a supply voltage such that current does not flow through the resource and power is not dissipated by the...

20060097340 - Chip resistor, process for producing the same, and frame for use therein: A chip resistor (A1) comprises a first insulation layer (2A) covering the regions between a plurality of electrodes (3) on a rear surface (10a) of a resistor (1), and a second insulation layer covering a pair of side faces of the resistor (1). Inadvertent adhesion of solder to an improper...

20060097341 - Forming phase change memory cell with microtrenches: A semiconductor substrate is covered by a dielectric region. The dielectric region accommodates a memory element and a selection element forming a phase change memory cell. The memory element is formed by a resistive element and by a storage region of a phase change material extending on and in contact...

20060097344 - Integrated thin film capacitor/inductor/interconnect system and method: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin...

20060097342 - Programmable matrix array with phase-change material: A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix array may be used in a programmable logic device. The...

20060097343 - Programmable matrix array with phase-change material: A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix array may be used in a programmable logic device. The...

20060097345 - Gate dielectric antifuse circuits and methods for operating same: A number of antifuse support circuits and methods for operating them are disclosed according to embodiments of the present invention. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a programming mode. An antifuse having a...

20060097346 - Structure for high quality factor inductor operation: A structure for high quality factor inductor operation formed on a semiconductor chip is disclosed. The structure comprises a plurality of pillars displaced from the semiconductor chip for forming an inductor. The plurality of pillar is arranged in an electrically inductive formation and at least one of the plurality of...

20060097347 - Novel slurry for chemical mechanical polishing of metals: A slurry for removing metals, useful in the manufacture of integrated circuits generally, and for the chemical mechanical polishing of noble metals particularly, may be formed by combining periodic acid, an abrasive, and a buffer system, wherein the pH of the slurry is between about 4 to about 8....

20060097348 - Structures having an electrode formed from a transition metal or a conductive metal-oxide: Structures having an electrode formed from a transition metal or a conductive metal oxide are disclosed. The structures may comprise a first electrode made of a material selected from the group consisting of transition metals, conductive metal-oxides, alloys thereof, and combinations thereof The first electrode may comprise a first non-smooth...

20060097349 - High performance diode-implanted voltage-controlled poly resistors for mixed-signal and rf applications: A p-type polysilicon resistor formed in the inter-level dielectric layer contains an implanted diode. A positive voltage applied to the diode modulates the depletion region of the diode and changes the absolute resistance of the p-type polysilicon resistor. This modulation occurs not only horizontally, but also vertically. The fact that...

20060097350 - Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide: Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base....

20060097351 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in a collector region 13 is formed on the surface of the semiconductor...

20060097352 - Bipolar transistor: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance....

20060097353 - Oxygen doping method to gallium nitride single crystal substrate and oxygen-doped n-type gallium nitride freestanding single crystal substrate: Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating...

20060097354 - Semiconductor composite apparatus, method for manufacturing the semiconductor composite apparatus, led head that employs the semiconductor composite apparatus, and image forming apparatus that employs the led head: A semiconductor composite apparatus includes a semiconductor thin film layer and a substrate. The semiconductor thin film layer and the substrate are bonded to each other with a layer of an alloy of a high-melting-point metal and a low-melting-point metal formed between the semiconductor thin film layer and the substrate....

20060097355 - Method and apparatus for leveling a semiconductor wafer, and semiconductor wafer with improved flatness: Semiconductor wafers are leveled by a) position-dependent measurement of a wafer-characterizing parameter to determine the position-dependent value of this parameter over an entire surface of the semiconductor wafer, b) etching the entire surface of the semiconductor wafer simultaneously under the action of an etching medium with simultaneous illumination of the...

20060097356 - Semiconductor substrate, manufacturing method of a semiconductor device and testing method of a semiconductor device: A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the...

20060097357 - Semiconductor device having through electrode and method of manufacturing the same: With a fluid insulating material applied on a convex substrate and a fluid insulating material applied on a concave substrate, a columnar conductive portion of the convex substrate is inserted into a hole of the concave substrate. With this, a conductive portion and an internal interconnection are electrically connected with...

20060097358 - Boron phosphide-based compound semiconductor device, production method thereof and light-emitting diode: A boron phosphide-based semiconductor device having a junction structure of a Group-III nitride semiconductor layer and a boron phosphide layer with excellent device properties is provided. The boron phosphide-based compound semiconductor device has a heterojunction structure comprising a Group-III nitride semiconductor layer and a boron phosphide layer, wherein the surface...

20060097359 - Low-k dielectric layer formed from aluminosilicate precursors: A method for forming a high mechanical strength, low k, interlayer dielectric material with aluminosilicate precursors so that aluminum is facilely incorporated into the silicon matrix of the material, and an integrated circuit device comprising one or more high-strength, low-k interlayer dielectric layers so formed....

20060097360 - Dielectric materials for electronic devices: A dielectric material prepared from a siloxy/metal oxide hybrid composition, and electronic devices such as thin film transistors comprising such dielectric material are provided herein. The siloxy/metal oxide hybrid composition comprises a siloxy component such as, for example, a siloxane or silsesquioxane. The siloxy/metal oxide hybrid composition is useful for...

20060097361 - Microprotrusion structure, and process for producing the same: A solution having a polymer dissolved in a hydrophobic organic solvent is cast on a substrate, said organic solvent is evaporated in a moist atmosphere to condense moisture contained in an atmosphere prevailing on a surface of said cast solution into micro-droplets, said micro-droplets are dispersed on the surface of...

20060097364 - Electro-optical device and electronic apparatus: An electro-optical device includes a substrate that holds an electro-optical material; and a flexible substrate that is connected to the substrate. The flexible substrate has a first connecting portion that is arranged on one surface of the substrate; and a second connecting portion that is arranged on the other surface...

20060097365 - Integrated circuit chip package having a ring-shaped silicon decoupling capacitor: A semiconductor package features a ring-shaped silicon decoupling capacitor that reduces simultaneous switching noise. The decoupling capacitor is fabricated on a substrate from silicon using a wafer fabrication process and takes the form of an annular capacitive structure that extends around a periphery of a substrate-mounted integrated circuit (IC). The...

20060097367 - Integrated circuit device having flexible leadframe: An integrated circuit device having a flexible leadframe, and techniques for fabricating the flexible leadframe and integrated circuit device, are provided. In one aspect of the invention, an integrated circuit device comprises a heat spreader having a top surface and a bottom surface. At least one integrated circuit die is...

20060097362 - Method and apparatus for fabricating and connecting a semiconductor power switching device: Fabrication processes for manufacturing and connecting a semiconductor switching device are disclosed, including an embodiment for dicing a wafer into individual circuit die by sawing the interface between adjacent die with a saw blade that has an angled configuration across its width, preferably in a generally V-shape so that the...

20060097363 - Semiconductor device having post-mold nickel/palladium/gold plated leads: A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The...

20060097366 - Semiconductor package including leadframe roughened with chemical etchant to prevent separation between leadframe and molding compound: A semiconductor package contains a metal leadframe that has been specially treated by roughening it with a chemical etchant. The roughening process enhances the adhesion between the leadframe and the molten plastic during the encapsulation of the leadframe and thereby reduces the tendency of the package to separate when exposed...

20060097368 - Flexible wiring substrate, semiconductor device and electronic device using flexible wiring substrate, and fabricating method of flexible wiring substrate: A flexible wiring substrate is provided which realizes a fine pitch of a wiring pattern and improves mechanical strength of the wiring pattern so as to prevent breaks or exfoliation of the wiring pattern. A flexible wiring substrate 3 of the present invention includes an insulation tape 6, and a...

20060097369 - Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is a step of forming electrodes (12) on a wafer (10); a step of...

20060097372 - Ic chip package with isolated vias: An IC chip package includes a substrate (2), a chip (5), a plurality of bonding wires (52), and a cover (6). The substrate has a top surface, a receiving chamber (23) having an opening at the top surface, a plurality of solder pads (3) arranged around the top surface and...

20060097371 - Resin-sealed semiconductor device, leadframe with die pads, and manufacturing method for leadframe with die pads: A resin-sealed semiconductor device with built-in heat sink prevents internal bulging and cracking caused by exfoliation of a semiconductor element from the heat sink when the vapor pressure of moisture absorbed into a gap between the semiconductor element and the heat sink rises during mounting of the semiconductor device to...

20060097370 - Stepped integrated circuit packaging and mounting: An electronic assembly and system and method implementing the same are disclosed herein. The electronic assembly includes an IC carrier package having circuitry contained within a housing unit. The IC carrier package includes a connector interface for electrically coupling the IC carrier package circuitry to a printed circuit board. The...

20060097373 - Electronic device package and electronic equipment: An electronic device to be loaded on an electronic equipment or an electronic component is mounted on a mount substrate, the mount substrate being made thin and flexible and having strong resistance to bending. An electronic device package including: a flexible substrate having a wiring pattern formed thereon; and an...

20060097375 - Interconnect shunt used for current distribution and reliability redundancy: In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated...

20060097374 - Multi chip package: A multi chip package includes a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted above the first semiconductor chip; a first bonding wire electrically coupled to a first bonding pad on the first semiconductor chip; and a second bonding wire electrically coupled to a...

20060097376 - Electronic product, a body and a method of manufacturing: The electronic product comprises a body with a three-dimensional shape that is derived from the product. The body is provided with a pattern of conductors including contact pads and at least one electric element, in which the conductors are mechanically anchored in the body. It is preferably provided with attachment...

20060097377 - Flip chip bonding structure using non-conductive adhesive and related fabrication method: A flip chip bonding structure has a non-conductive adhesive interposed between an integrated circuit (IC) chip and a circuit substrate. The IC chip has I/O pads on an active surface thereof, and the circuit substrate has bump pads on a first surface thereof. The non-conductive adhesive is provided on the...

20060097378 - Substrate having a penetrating via and wiring connected to the penetrating via and a method for manufacturing the same: A disclosed substrate includes a base member having a through-hole, and a conductive metal filling in the through-hole so as to form a penetrating via. The penetrating via contains a conductive core member that is substantially at the central axis of the through-hole....

20060097379 - Substrate for electrical device and methods for making the same: Substrate for electrical devices and methods of manufacturing such substrate are disclosed. An embodiment for the substrate comprised of an insulator and a plurality of conductive elements, wherein the conductive elements embedded in the insulator, and two surfaces of the conductive element exposed to two surfaces of the insulator for...

20060097381 - Chip package with grease heat sink: The present invention relates to enhanced protection of the active surface and the bond wires or ball array of a microelectronic device, and to thermal management of the microelectronic device as it is packaged with a printed circuit board (PCB) or other substrate. The enhanced protection and thermal management are...

20060097382 - High frequency module: A high frequency module includes an insulating substrate, an upper layer plated pattern (a signal line) formed on a main surface of the insulating substrate and electrically connected to a high frequency circuit to transmit a high frequency signal, a mounted part (an electronic component) mounted on the main surface...

20060097380 - Semiconductor module: A semiconductor module includes a parts-mounting or packaging substrate, a plurality of power metal insulator semiconductor (MIS) chips which have top surfaces and back surfaces and are mounted by flip chip bonding on or above the package substrate while letting the top surfaces face the package substrate, a drive-use integrated...

20060097383 - Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment,...

20060097384 - Method and apparatus for thermal characterization under non-uniform heat load: A method and apparatus for real-time thermal characterization of a fully operating cooling device (1002). A heat source (1004) is applied to one or more areas on a cooling device (1002) to produce non-uniform heating of the cooling device. Infrared (IR) temperature imaging (1006) detects and measures the thermal distribution...

20060097385 - Solid metal block semiconductor light emitting device mounting substrates and packages including cavities and heat sinks, and methods of packaging same: A mounting substrate for a semiconductor light emitting device includes a solid metal block having first and second opposing metal faces. The first metal face includes a cavity that is configured to mount at least one semiconductor light emitting device therein, and to reflect light that is emitted by at...

20060097386 - Semiconductor wafer with electrically connected contact and test areas: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated...

20060097387 - Staggered wirebonding configuration: The present invention discloses a staggered finger configuration comprising a plurality of first and second conducting wires alternately arranged on the substrate, wherein each of the first conducting wire connecting an inner and an outer fingers and each of the second conducting wire connecting an intermediate finger between the inner...

20060097388 - Electrical system, especially a microelectronic or microelectromechanical high frequency system: An electrical component is proposed, in particular a high-frequency microelectronic or microelectromechanical component having a base element that is provided with a feedthrough, a first conductive structure extending on an upper side of the base element being connected by the feedthrough, continuously for high-frequency electromagnetic waves, to a second conductive...

20060097389 - Nanowire interconnection and nano-scale device applications: A nano-colonnade structure-and methods of fabrication and interconnection thereof utilize a nanowire column grown nearly vertically from a (111) horizontal surface of a semiconductor layer to another horizontal surface of another layer to connect the layers. The nano-colonnade structure includes a first layer having the (111) horizontal surface; a second...

20060097390 - Semiconductor devices having a trench in a side portion of a conducting line pattern and methods of forming the same: A semiconductor device having a trench in the side portion of a conducting line pattern and methods of forming the same. The semiconductor device provides a way of preventing an electrical short between the conducting line pattern and a landing pad adjacent to the conducting line pattern. There are disposed...

20060097391 - Semiconductor device and a method of manufacturing the same: A thin semiconductor device difficult to cause breakage of a semiconductor chip is disclosed. The semiconductor device comprises a sealing member, a semiconductor chip positioned within the sealing member, the semiconductor chip having a source electrode and a gate electrode on a first main surface thereof and a drain electrode...

20060097392 - Wafer structure, chip structure and bumping process: A kind of wafer structure including a plurality of chip, first passivation layer, a plurality of buffer pad, second passivation layer, and a plurality of bump. Each chip has an active surface, on which a plurality of bonding pad are disposed. The first passivation layer is disposed on the active...

20060097394 - Detection of residual liner materials after polishing in damascene process: A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer...

20060097395 - Integrated circuit design for routing an electrical connection: An integrated circuit for routing of an electrical connection include a first metal layer having a first set of dummy conductive segments discretely arranged, and a second metal layer having a second set of dummy conductive segments discretely arranged. The segments of the first and second sets are interleaved with...

20060097393 - Low dielectric constant insulating material and semiconductor device using the material: The use of a material possessing a six-member borazine ring consisting of at least boron and nitrogen elements in the form of a low dielectric constant insulating film in a hard mask, a Cu diffusion barrier layer and an etching stopper which are necessary when low dielectric constant interlayer insulating...

20060097396 - Semiconductor device: In a semiconductor device including a multilayer pad, the multilayer pad comprises a first pad layer provided over a semiconductor substrate to have a first copper wiring region and a first intralayer insulating region provided within the first copper wiring region, and a second pad layer provided over the first...

20060097397 - Method for forming a dual layer, low resistance metallization during the formation of a semiconductor device: A method for providing a highly reliable, low resistance interconnect comprises forming a trench in a dielectric layer, forming a first liner in the trench then forming a resilient layer such as a tungsten layer within the trench. The resilient layer is etched back to remove the layer from a...

20060097398 - Method and structure to reduce risk of gold embrittlement in solder joints: A method for reducing gold embrittlement in solder joints, and a copper-bearing solder according to the method, are disclosed. Embodiments of the invention comprise adding copper to non-copper based solder, such as tin-lead solder. The embodiments may further comprise using the copper-bearing solder as a solder interconnect on a gold-nickel...

20060097399 - Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level...

20060097401 - Method for designing wiring connecting section and semiconductor device: First, an amount of a current flowing between a first wiring and a third wiring is estimated, and the number of stack vias required for connecting the first wiring and the third wiring is determined. Next, based on the number of stack vias, the number of virtual wirings for determining...

20060097400 - Substrate via pad structure providing reliable connectivity in array package devices: A substrate via pod structure providing reliable connectivity in array package devices. The reliability is attained by providing a protruding metal stud in the via area, with the stud being connected to a conductive metal trace (which provides conductive path to a bond pad of an integrated circuit). Due to...

20060097402 - Semiconductor device having flip-chip package and method for fabricating the same: A semiconductor device having a flip-chip package and a method for fabricating the same are provided. A flip-chip package after being tested to be functionally workable is mounted on a carrier and is electrically connected to the carrier by a plurality of first conductive elements, the flip-chip package having a...

20060097403 - No-flow underfill materials for flip chips: Systems and methods are described which include packaging semiconductor dies and next level packages using low viscosity no-flow underfills having fine fillers treated with surface treatment agents....

20060097405 - Ic chip package and method for packaging same: An IC (integrated circuit) chip package includes a substrate (2), a chip (3), a plurality of bonding wires (32), and a cover (5). The substrate has a top surface, a bottom surface, a receiving chamber (23) defined therein, a plurality of solder pads (24) arranged around the top surface and...

20060097404 - Semiconductor package with conductive molding compound and manufacturing method thereof: The present invention relates to a semiconductor package having a conductive molding compound to prevent static charge accumulation. By using a conductive molding compound heat conductivity is also increased and heat generated by the semiconductor chip is more effectively dissipated externally. Additionally, the conductive compound blocks electromagnetic waves making possible...

20060097407 - Integration type semiconductor device and method for manufacturing the same: A semiconductor device includes: a plurality of power MOS cells on a semiconductor substrate; a plurality of lead wires connecting to a source and a drain of each power MOS cell through a contact hole; a plurality of collecting electrodes connecting in parallel with the lead wires through a via...

20060097406 - Semiconductor chip capable of implementing wire bonding over active circuits: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the...

20060097408 - Semiconductor package device and method for fabricating the same: Disclosed are a semiconductor package device and a method for fabricating the semiconductor package device. The semiconductor package has a semiconductor chip including a plurality of bonding pads having a microscopic size and aligned at a minute interval, a planar layer formed on the semiconductor chip so as to expose...

20060097409 - Semiconductor device: In a semiconductor device, an average grain size of a filler contained in an adhesive agent applied to the first chip is larger than an interval between adjacent wires. When the second chip is pressed downward, the filler is caught between the wires, a larger number of filler grains is...

20060097410 - Semiconductor capacitor structure and method for manufacturing the same: In one embodiment, a semiconductor device comprises a base and a tapered wall formed on the base. The wall has a midline and also has an inner sidewall and an outer sidewall. The inner sidewall and the outer sidewall are substantially symmetrical with each other in relation to the midline....

20060091373 - Method for programming a multilevel phase change memory device: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at...

20060091374 - Multibit phase change memory device and method of driving the same: A multibit phase change memory device structured such that a plurality of individual phase change memory devices are aligned in a plan area or vertically, and a method of driving the same are provided. The multibit phase change memory device includes a phase change material layer having a plurality of...

20060091376 - Semiconductor light-emitting device with improved light extraction efficiency: The present invention provides a semiconductor light-emitting device. The light-emitting device comprises a first conductive clad layer, an active layer, and a second conductive clad layer sequentially formed on a substrate. In the light-emitting device, the substrate has one or more side patterns formed on an upper surface thereof while...

20060091375 - Systems and methods for quantum braiding: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the...

20060091377 - Hetero-integrated strained silicon n-and p-mosfets: The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions...

20060091379 - High-temperature devices on insulator substrates: Semiconductor devices, logic devices, libraries to represent logic devices, and methods for designing and fabricating the same are disclosed. The semiconductor devices include a substrate comprising sapphire or diamond, an active layer disposed on the substrate, the active layer having a thickness tSi and comprising a channel region having a...

20060091382 - Low dielectric constant material having thermal resistance, insulation film between semiconductor layers using the same, and semiconductor device: There is provided a low dielectric constant material, which is excellent in thermal resistance, has low dielectric constant, and is applicable to a semiconductor device or electric appliances, an insulation film between semiconductor layers using the same, and the semiconductor device. The material is the low dielectric constant material having...

20060091378 - Luminescent gold (iii) compounds, their preparation, and light-emitting devices containing same: represents an aromatic or heterocyclic 5- or 6-membered ring; α and β each independently represent a bridge for an aromatic or heterocyclic 5- or 6-membered ring or represent a break for non-cyclic moiety; C—X, C—Y and C-Z each independently represent a single bond or double bond; n represents a zero...

20060091381 - Organic electro-luminescence display device and fabricating method thereof: There are disclosed an organic electro luminescence display device that is adaptive for improving the conductivity of an anode electrode and the contrast ratio, and a fabricating method thereof. An organic electro luminescence display device according to an embodiment of the present invention includes a plurality of anode electrodes which...

20060091380 - Organic light-emitting device array and display: The present invention provides an organic light emitting device array which reduces the change of white balance even if an observation angle is changed. In an organic light emitting device array comprising a plurality of organic light emitting devices which emit lights of different colors, an optical path difference is...

20060091383 - Semiconductor structure and testing method thereof: A semiconductor structure and a testing method thereof are provided. The semiconductor structure comprises a substrate, a well, an isothermal heating layer, a first dielectric layer, an interconnection material layer and a second dielectric layer. Wherein, the well is disposed in the substrate, the isothermal heating layer is disposed over...

20060091384 - Substrate testing apparatus with full contact configuration: A substrate testing apparatus with full contact configuration. The apparatus includes a jig and a full-contact probe substrate. The jig has a conductive tape disposed thereon for fully electrically connecting a plurality of first connecting pads disposed on an upper surface of a substrate strip. The full-contact probe substrate has...

20060091385 - Selectable application of offset to dynamically controlled voltage supply: An electronic system. The system comprises a plurality of circuit paths. Each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage supply. The system further comprises a first circuit for providing a first value indicating a potential capability of operational speed of...

20060091386 - Transistor and method for manufacturing the same: In a process for manufacturing a thin film transistor having a semiconductor layer constituting source and drain regions and a channel forming region, by the semiconductor layer being made thinner in the source and drain regions than in the channel forming region a structure is realized wherein, at the boundary...

20060091388 - Display device and method for manufacturing the same: A display device including: a plurality of pixel lines each with a plurality of pixels; a pixel array consisting of said plurality of pixel lines; pixel transistors for driving said plurality of pixels; and a driving circuit for driving said plurality of pixel transistors, wherein: said plurality of pixel transistors...

20060091390 - Image pickup apparatus, radiation image pickup apparatus and radiation image pickup system: An image pickup apparatus or a radiation image pickup apparatus according to the present invention includes: a plurality of pixels which are two-dimensionally arranged on a substrate, each of the plurality of pixels including a set of a semiconductor conversion element that converts an incident electromagnetic wave into an electrical...

20060091387 - Semiconductor device: In order to realize a higher reliability TFT and a high reliability semiconductor device, an NTFT of the present invention has a channel forming region, n-type first, second, and third impurity regions in a semiconductor layer. The second impurity region is a low concentration impurity region that overlaps a tapered...

20060091389 - Thin film transistor array panel: A thin film transistor array panel according to an embodiment of the present invention includes: a gate electrode; a semiconductor layer; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode connected to the semiconductor layer; and a drain electrode connected to the semiconductor...

20060091391 - Thin film transistor array panel and liquid crystal display including the panel: A thin film transistor array panel is provided, which includes: a plurality of gate lines formed on a substrate and including a plurality of oblique portions and a plurality of gate electrodes; a first insulating layer on the gate line; a semiconductor layer formed on the first insulating layer; a...

20060091392 - Electrically conductive structure, method of forming the same, an array substrate using the electrically conductive structure and a liquid crystal display panel including the electrically conductive structure: An electrically conductive structure includes a layer of metal and a barrier layer. The layer of metal is disposed on an insulating body. The barrier layer covers an upper face and a side face of the metal layer and the barrier layer comprises a material having a melting point higher...

20060091393 - Isotopically pure silicon-on-insulator wafers and methods of making same: A semiconductor wafer structure having a device layer, an insulating layer, a semiconductor material layer and a substrate which is capable of supporting increased semiconductor device densities or increased semiconductor device power. One or more of the layers includes an isotopically enriched semiconductor material having a higher thermal conductivity than...

20060091394 - Semiconductor device and method for manufacturing the same: A semiconductor device having an island semiconductor film which is a channel formation region and a semiconductor film which is a source or drain region being in contact with a side face of the island semiconductor film, and a method for manufacturing the semiconductor device are disclosed. The manufacturing costs...

20060091395 - Organic electroluminescent display device having otft and method of fabricating the same: An organic electroluminescent display device having an organic thin film transistor (OTFT) and a method of fabricating the same is disclosed. The display device can maintain an insulation property of a TFT and concurrently, ensure a sufficient capacitance by using an organic insulating layer for a gate insulating layer and...

20060091399 - Active matrix type organic light emitting diode device and fabrication method thereof: An active matrix type organic light emitting diode (AMOLED) device and its fabrication method are discussed. In one embodiment, an OLED device includes an EL configured to emit light, a driving TFT configured to control the EL, a storage capacitor coupled to the driving TFT, and at least one insulation...

20060091397 - Display device and method for manufacturing the same: It is an object of the invention to manufacture a highly reliable display device at a low cost with high yield. A display device of the invention includes: a first reflective electrode layer; and a second transparent electrode layer with an electroluminescent layer interposed therebetween, wherein the electroluminescent layer has...

20060091398 - Semiconductor device and method for manufacturing the same: It is an object of the present invention to manufacture a TFT having a small-sized LDD region in a process with a few processing step and to manufacture TFTs each having a structure depending on each circuit separately. According to the present invention, a gate electrode is a multilayer, and...

20060091396 - Thin film transistor array panel and method for manufacturing the same: The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a...

20060091400 - Composite structure with high heat dissipation: A composite structure is disclosed that includes a support wafer and a layered structure on the support wafer. The layered structure includes at least one layer of a monocrystalline material and at least one layer of a dielectric material. In addition, the layered structure materials and the thickness of each...

20060091401 - Semiconductor device and method of fabricating the same: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench...

20060091402 - Silicon carbide single crystal, silicon carbide substrate and manufacturing method for silicon carbide single crystal: SiC single crystal that includes a first dopant functioning as an acceptor, and a second dopant functioning as a donor is provided, where the content of the first dopant is no less than 5×1015 atoms/cm3, the content of the second dopant is no less than 5×1015 atoms/cm3, and the content...

20060091403 - Led module and method of packaging the same: An LED module and method of packing the same are provided. The LED module includes a substrate with at least one cavity therein, at least one LED unit positioned on portions of the substrate in the cavity, a circuit positioned above the LED unit and electrically connected to the LED...

20060091405 - Multi-layer electrode and compound semiconductor light emitting device comprising the same: A multi-layer electrode and a compound semiconductor light emitting device comprising the same. A multi-layer electrode for the compound semiconductor light emitting device may be formed on a p-type compound semiconductor layer of the compound semiconductor light-emitting device and may include: a first electrode layer formed on the p-type compound...

20060091404 - Semiconductor light emitting devices with graded compositon light emitting layers: A III-nitride light emitting layer in a semiconductor light emitting device has a graded composition. The composition of the light emitting layer may be graded such that the change in the composition of a first element is at least 0.2% per angstrom of light emitting layer. Grading in the light...

20060091406 - Illuminating apparatus, method for fabricating the same and display apparatus using the same: An illuminating apparatus has a reduced number of mounting spots by soldering or the like to permit an increased yield rate and a reduced cost. The illuminating apparatus has light emitting diodes, lead frames, and a transparent sealer. N light emitting diodes, N sets of lead frames mounted with the...

20060091407 - Multi-wavelength light receiving element and method of fabricating same: Disclosed is a multi-wavelength light receiving element. The multi-wavelength light receiving element includes a first type substrate. A first intrinsic layer is positioned on the first type substrate. A heavily-doped second-type buried layer is positioned on the first intrinsic layer. A second intrinsic layer is positioned on the heavily-doped second-type...

20060091408 - Nitride based semiconductor device using nanorods and process for preparing the same: Disclosed are a nitride based semiconductor device, including a high-quality GaN layer formed on a silicone substrate, and a process for preparing the same. A nitride based semiconductor device in accordance with the present invention comprises a plurality of nanorods aligned and formed on the silicone substrate in the vertical...

20060091410 - Low thermal resistance led package: A LED chip is bonded on a large submount serving as a heat sink. The submount is punched out from a thin metal sheet together with two other sections of lead frames for the LED and held together with insulating material. The planar structure makes the package thin. A transparent...

20060091409 - Package-integrated thin film led: LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. For each die, the n and p layers are electrically bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth...

20060091411 - High brightness led package: Light sources are disclosed utilizing LED dies that have a light emitting surface. A patterned low refractive index layer that can support total internal reflection within the LED die is provided in optical contact with a first portion of the emitting surface. In optical contact with a second portion of...

20060091413 - Light guide plate, surface light source device and display: A guide plate 30 has a back face 34 provided with a great number of micro-reflectors 90 which has a guide portion and a conversion output portion including a valley. The conversion output portion reflects twice input light P at inner slopes, generating inner output light Q directed obliquely as...

20060091412 - Polarized led: A solid state light source includes an LED die that generates light of two polarization states. A medium is provided at or near an emitting surface of the LED die that preferentially reflects one polarization state back into the LED die and preferentially transmits the other polarization state out of...

20060091416 - High power led package with universal bonding pads and interconnect arrangement: LED packages are provided that can accommodate more than one type of LED. These packages include at least three bonding pads arranged such that two are appropriate for one type of LED, while another two are appropriate for another type of LED. Packages can include a thermally conductive layer on...

20060091414 - Led package with front surface heat extractor: Light sources are disclosed utilizing LED dies having at least one emitting surface. An optical element is disclosed for efficiently extracting light out of an LED die by controlling the angular distribution of the emitted light. The optical element has an input surface that is optically coupled to the emitting...

20060091415 - Led package with structure and materials for high heat dissipation: LED packages are provided that include a material that is both thermally conductive and has a coefficient of thermal expansion that is matched to that of an LED. The material can be a ceramic such as aluminum nitride. The package has a body that includes a bottom surface and a...

20060091417 - Nitride semiconductor device: A nitride semiconductor device includes a semiconductor layer, a first electrode for establishing an ohmic contact disposed on the semiconductor layer, and a second electrode on the first electrode, having a different shape from that of the first electrode. A joint region is formed with the upper layer of the...

20060091418 - Side emitting led device and method of fabrication: In one embodiment, a light emitting diode (LED) device comprises an LED die for generating output light and an encapsulant sealing the LED die, the encapsulant comprising a conical structure extending away from the LED die and positioned above the LED die, wherein a profile of the conical structure causes...

20060091420 - Diode having vertical structure and method of manufacturing the same: A light emitting diode includes a conductive layer, an n-GaN layer on the conductive layer, an active layer on the n-GaN layer, a p-GaN layer on the active layer, and a p-electrode on the p-GaN layer. The conductive layer is an n-electrode....

20060091419 - Light emitting diode: A light emitting diode (LED) utilizes an adhesive layer to adhere a light emitting layer to a substrate. The LED further comprises an electrode buffer layer to enhance the adhesion between the electrode and the light emitting diode, and thus to improve the yield rate of the LED....

20060091421 - Semiconductor laser device: A semiconductor laser device according to the present invention comprises: an n-band discontinuity reduction layer (n-BDR layer) disposed on an n-GaAs substrate and the n-BDR layer including an AlGaAs layer whose concentration of Si doped as an n-type impurity is in a range from 0.2×1018 cm−3 to 1.4×1018 cm−3; an...

20060091422 - Semiconductor memory and method of fabricating the same: A semiconductor memory includes first and second source regions that are formed in a semiconductor substrate and run in orthogonal directions. The first and second source regions are diffused regions and are electrically connected to each other at crossing portions thereof. The semiconductor device may further include drain regions formed...

20060091423 - Layer fill for homogenous technology processing: Spare transistors are formed in regions of a semiconductor device where functional transistors are not formed, providing uniformity in etch and polishing processes, and resulting in transistors with more uniform parameters on the semiconductor device. The spare transistors may not be electrically connected to other components on the device, or...

20060091425 - Semiconductor device: A semiconductor device in which surge breakdown of interlayer-insulating film does not occur even when effectively suppressing variations in etching and proximity effects. The semiconductor comprises dummy patterns 7b that are made from a gate layer and shaped to be disposed within the surface shape of the insulating material of...

20060091424 - Semiconductor device and method of producing a semiconductor device: Semiconductor Device And Method Of Producing A Semiconductor Device A semiconductor device comprises a memory cell (160) including a transistor body (150) having a top surface (111) and including a first doping area (10a) and a second doping area (10b) with a channel region (110) in between. The memory cell...

20060091426 - Semiconductor substrate, semiconductor device, method of manufacturing semiconductor substare and method of manufacturing semiconductor device: A semiconductor substrate includes a semiconductor base substrate that has an oxide film selectively formed on a part thereof, the oxide film having a non-uniform thickness; and a semiconductor layer that is formed on the oxide film by epitaxial growth so as to have a non-uniform thickness....

20060091427 - Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device: A semiconductor device comprising a substrate having a first crystal orientation and an insulating layer overlying the substrate is provided. A plurality of silicon layers are formed overlying the insulating layer. A first silicon layer comprises silicon having the first crystal orientation and a second silicon layer comprises silicon having...

20060091428 - Structure and method for forming the gate electrode in a multiple-gate transistor: In a method of forming semiconductor device, a semiconductor fin is formed on a semiconductor-on-insulator substrate. A gate dielectric is formed over at least a portion of the semiconductor fin. A first gate electrode material is formed over the gate dielectric and a second gate electrode material is formed over...

20060091429 - Light emitting diode and lens for the same: A light emitting diode includes a lens, a chip base attached to a bottom of the lens, and an LED chip attached in the chip base to be concentric with the lens. The lens includes a bottom, an outer sidewall extending from the bottom, a first outer top surface extending...

20060091430 - Metal-semiconductor field effect transistors (mesfets) having drains coupled to the substrate and methods of fabricating the same: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a MESFET having a source region, a drain region and a gate contact. The gate contact is disposed between the source region and the drain region. The drain region is...

20060091431 - Contact plug processing and a contact plug: A semiconductor device has anisotropically formed via holes through a PMD layer. The anisotropic geometry of the via holes results in the diameter of a via hole over a gate structure being equal to the diameter of a via hole not over the gate structure. The via holes are formed...

20060091432 - Damascene gate field effect transistor with an internal spacer structure: A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least...

20060091433 - Semiconductor integrated circuit device and manufacturing method thereof: A semiconductor integrated circuit device includes a projected semiconductor layer formed at a part of the upper surface of a semiconductor substrate; a gate insulation film formed on a first side surface of the semiconductor layer; a gate electrode formed on the gate insulation film; a first insulation film formed...

20060091436 - Methods of forming field effect transistors having metal silicide gate electrodes: Methods of forming field effect transistors according to embodiments of the invention include forming a conductive gate electrode (e.g., polysilicon gate electrode) on a semiconductor substrate and forming a first metal layer on the conductive gate electrode. This first metal layer may include a material selected from a group consisting...

20060091435 - Organic electronic circuit and method for making the same: In an organic electronic circuit (C), particularly a memory circuit with an organic ferroelectric or electret material (2) the active material comprises fluorine atoms and consists of various organic materials. The active material is located between first and second electrode sets constituting respectively bottom and top electrodes (1a;1b) of the...

20060091437 - Resistive memory device having array of probes and method of manufacturing the resistive memory device: Provided are a resistive memory device having a probe array and a method of manufacturing the same. The resistive memory device includes a memory part having a bottom electrode and a ferroelectric layer sequentially formed on a first substrate; a probe part having an array of resistive probes arranged on...

20060091438 - Semiconductor device and manufacturing method thereof: A ferroelectric capacitor including a bottom electrode (15), a ferroelectric film (16) and a top electrode (17) is covered with an interlayer insulating film (18). One end of the bottom electrode (15) is formed like comb teeth. To match with the remaining portion of that end, a plurality of contact...

20060091434 - Strain-engineered ferroelectric thin films: A strained thin film structure includes a substrate layer formed of a crystalline scandate material having a top surface, and a strained layer of crystalline ferroelectric epitaxially grown with respect to the crystalline substrate layer so as to be in a strained state and at a thickness below which dislocations...

20060091440 - Memory device having molecular adsorption layer: Provided is a memory device comprising a molecular adsorption layer. The memory device includes: a substrate; a source electrode and a drain electrode formed on the substrate and separated from each other; a carbon nanotube (CNT) layer electrically connected to the source electrode and the drain electrode; a memory cell...

20060091439 - System and method for protecting semiconductor devices: A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device....

20060091441 - Method to eliminate arsenic contamination in trench capacitors: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as...

20060091442 - Out of the box vertical transistor for edram on soi: The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is...

20060091443 - Composite capacitor: A composite capacitor includes a laminated substrate in which a plurality of dielectric layers and a plurality of conductive layers are laminated alternately. The laminated substrate includes a first common electrode that is composed of the corresponding conductive layer and is provided in laminated layers of the laminated substrate, a...

20060091444 - Double word line memory structure and manufacturing method thereof: A memory structure comprises two bit lines, a first gate dielectric, a second gate dielectric, at least one first gate, a second gate and a third gate, a first dielectric spacer and a second dielectric spacer, where the two bit lines are formed in the semiconductor substrate, the first gate...

20060091446 - Non-volatile semiconductor memory device and its manufacturing method: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon...

20060091447 - Semiconductor device and its manufacture method: A semiconductor device includes: a first insulating layer with a flat surface formed over a semiconductor substrate structure in which a plurality of semiconductor elements are formed; column-like conductive plugs formed to penetrate the first insulating layer in the thickness direction; elongated wall-like conductive plugs formed through the first insulating...

20060091445 - Semiconductor device and method for fabricating thereof: A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film...

20060091448 - Charge-trapping memory device and methods for operating and manufacturing the cell: To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the...

20060091449 - Stacked gate memory cell with erase to gate, array, and method of manufacturing: A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to...

20060091450 - Dual function finfet, finmemory and method of manufacture: A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin...

20060091451 - Semiconductor device: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor...

20060091458 - Nonvolatile memory device and method of manufacturing the same: Provided are a nonvolatile memory device that has enhanced endurance and can accurately read stored data, and a method of manufacturing the same. The nonvolatile memory device includes a trench formed in a semiconductor substrate, a gate electrode formed in the trench, a gate electrode insulating layer interposed between the...

20060091452 - Self-aligned trench dmos transistor structure and its manufacturing methods: A self-aligned trench DMOS transistor structure of the present invention comprises a self-aligned source structure and a self-aligned trench gate structure, in which the self-aligned source structure comprises a p-base diffusion region, a self-aligned n+ source diffusion ring, a self-aligned p+ contact diffusion region, and a self-aligned source contact window;...

20060091454 - Semiconductor device and method of manufacturing the same: After an isolation region is formed using a field-forming silicon nitride film, this silicon nitride film is patterned, thereby a gate trench is formed. Next, a gate electrode material is buried into the gate trench, and this is etched back. Thereafter, the silicon nitride is removed, thereby a contact hole...

20060091457 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a base region formed above a semiconductor substrate, a source region formed above the base region, a gate electrode filled inside a trench formed above the semiconductor substrate, an interlayer insulation film formed all over the semiconductor substrate, a first contact hole formed in the interlayer...

20060091453 - Trench mis device and method for manufacturing trench mis device: A trench MIS device includes a drain region, a base region disposed on the drain region, the base region having a channel face, a source region disposed on the base region, the source region having a source end face, the source end face being continuous with the channel face, a...

20060091455 - Trench mosfet and method of manufacturing same: A trench MOSFET of the present invention has a trench region on a semiconductor substrate. The semiconductor substrate contains: a substrate which is a p-type heavily doped drain region; an epitaxial layer which is a p-type lightly doped drain region; a n-type body region; and a p-type source diffusion region,...

20060091456 - Trench mosfet with deposited oxide: A trench type power semiconductor device which includes deposited rather than grown oxide in the trenches for the electrical isolation of electrodes disposed inside the trenches from the semiconductor body....

20060091459 - Semiconductor device having metal silicide and method of making the same: A MOS transistor device includes a polysilicon gate with opposing sidewalls over an active area of a semiconductor substrate. The polysilicon gate has a gate length “L”. Dielectric spacers are disposed at a lower portion of the opposing sidewalls of the polysilicon gate. A metal silicide layer is situated approximately...

20060091462 - Memory cell having an electrically floating body transistor and programming technique therefor: A semiconductor memory cell comprising an electrically floating body transistor including a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and a gate disposed over the body region and separated therefrom by a gate...

20060091460 - Semiconductor devices and methods of making: In one method of forming a semiconductor device, a first electrode is formed electrically coupled with a semiconductor material. After the first electrode is formed, an insulator is formed over the semiconductor material adjoining the first electrode and extending a selected distance from the first electrode. After the insulator is...

20060091461 - Transistor structure with dual trench for optimized stress effect and method therefor: A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semiconductor active layer and a stressor material is deposited on a bottom of the...

20060091463 - Finfet body contact structure: A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The...

20060091464 - Electrostatic protection circuit: An electrostatic protection circuit includes a thyristor that discharges an excess charge generated between a first power supply terminal and a second power supply terminal having a lower voltage than the first power supply terminal, a trigger device that supplies a current turning on the thyristor, and an electrostatic discharge...

20060091465 - Layout of semiconductor device with substrate-triggered esd protection: A semiconductor device with substrate-triggered ESD protection has a guard ring, a first MOS transistor array, a second MOS transistor array, a substrate-triggered portion, and an N-well. The first MOS transistor array, the second MOS transistor array, the substrate-triggered portion, and the N-well are formed in a region surrounded by...

20060091466 - Nonvolatile semiconductor memory device: A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in...

20060091469 - Dual-gate structure and method of fabricating integrated circuits having dual-gate structures: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K...

20060091467 - Resonant tunneling device using metal oxide semiconductor processing: An embodiment of the present invention is a technique to fabricate a semiconductor device having low off state leakage current. A gate structure of a first device is formed on a substrate layer having a hardmask. A channel is formed underneath the gate structure having a width to support the...

20060091468 - Top and sidewall bridged interconnect structure and method: An interconnect structure and its method for fabrication each employ an interconnect formed over and adjacent an active region of a semiconductor substrate. A gate electrode is also formed over the active region. Spacer layers are formed adjoining the interconnect and the gate electrode. A spacer layer adjoining the interconnect...

20060091470 - Nonvolatile semiconductor memory device with twin-well: A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a...

20060091473 - Semiconductor device, manufacturing method thereof, and cmos integrated circuit device: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the...

20060091472 - Sram array and analog fet with dual-strain layers: Disclosed is a semiconductor structure and associated method of performing the structure with good performance and stability trade-offs for digital circuits and SRAM cells and/or analog FETs on the same chip. Specifically, a dual-strain layer is formed over digital circuits and the other devices on a chip. The dual-strain layer...

20060091471 - Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress: A technique is provided that allows the formation of contact etch stop layers having different intrinsic stress for different transistors, while substantially avoiding any device degradation owing to the partial removal of the contact etch stop layer. Hereby, an additional thin etch stop layer is provided prior to the formation...

20060091474 - Semiconductor device and manufacturing method thereof: The manufacturing process of a semiconductor device in which a n channel MIS transistor and a p channel MIS transistor each having a gate electrode made of a metal material formed on a gate insulator made of a high dielectric constant material are used to form a CMOS circuit is...

20060091475 - Semiconductor device: A semiconductor device comprises a semiconductor substrate, a plurality of transistors provided in the semiconductor substrate, and an isolation region for isolating the plurality of transistors to one another, the isolation region being comprised of an isolating insulation film, wherein a crystal structure of at least a part of the...

20060091476 - Sub-lithographic structures, devices including such structures, and methods for producing the same: A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a...

20060091477 - Process for producing a contact pad on a region of an integrated circuit, in particular on the electrodes of a transistor: A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with...

20060091478 - Semiconductor gate structure and method for preparing the same: A semiconductor gate structure is described, which comprises a substrate, a gate oxide positioned on the substrate, a first conductive layer positioned on the gate oxide and a second conductive layer positioned on the first conductive layer. The second conductive layer comprises a bottom portion positioned on the first conductive...

20060091479 - Applying epitaxial silicon in disposable spacer flow: A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates;...

20060091480 - Lateral double diffused mos transistors: The specification describes an improved mechanical electrode structure for MOS transistor devices with elongated runners. It recognizes that shrinking the geometry increases the likelihood of mechanical failure of comb electrode geometries. The mechanical integrity of a comb electrode is improved by interconnecting the electrode fingers in a cross-connected grid. In...

20060091482 - Metal oxide semiconductor (mos) transistors having a recessed gate electrode and methods of fabricating the same: A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region....

20060091481 - Multi bridge channel field effect transistors with nano-wire channels and methods of manufacturing the same: A field effect transistor (FET) includes spaced apart source and drain regions disposed on a substrate and at least one pair of elongate channel regions disposed on the substrate and extending in parallel between the source and drain regions. A gate insulating region surrounds the at least one pair of...

20060091483 - Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, forming a barrier layer on the high-k gate dielectric layer, and forming a fully silicided gate electrode on the barrier layer....

20060091484 - Micro electromechanical systems thermal switch: A Micro Electro-Mechanical Systems (MEMS) thermal switch. The switch includes a FET having a source and drain in a substrate and a beam isolated from the substrate, wherein the beam is a monolithic beam. The beam is positioned over the source and the drain and spaced by a predefined gap....

20060091485 - Piezoelectric device and manufacturing method thereof: A surface acoustic wave device includes a SAW element having an IDT provided on a piezoelectric substrate and electroconductive pads connected to the IDT, and a bonding substrate having electroconductive pad through holes bonded by an adhesive layer so as to face the IDT. A protective space is provided by...

20060091487 - Manufacturing method of solid-state image sensing device: A sensor chip and a lens mount accommodating therein the sensor chip are mounted on a surface of a wiring substrate and a lens holder accommodating a lens therein is coupled with the lens mount. On a rear surface of the wiring substrate, a logic chip, a memory chip and...

20060091486 - Solid image-pickup device and method for manufacturing the solid image pickup device: It is an object of the invention to provide an improved solid image-pickup device which is compact in size and low in production cost. The solid image-pickup device is so formed that its semiconductor substrate has on its surface an image-pickup area having a plurality of light sensors arranged thereon....

20060091488 - Image sensor chip package and method of fabricating the same: The present invention relates to an image sensor chip package and a method for fabricating the same. In one embodiment of an image sensor chip package, chip pads on a first surface of an image sensor chip are attached to electrode pads of a glass substrate with conductive material. In...

20060091491 - Optical detector and method of producing an arrangement of multiple semiconductor layers: An optical detector with an arrangement of several semiconductor layers has at least one zone absorbing in a predetermined wavelength region, at least one zone which is at least partially light-permeable in the predetermined wavelength region, one semiconductor layer which is absorbing in the predetermined wavelength region, a semiconductor layer...

20060091490 - Self-aligned gated p-i-n diode for ultra-fast switching: A gated p-i-n diode and a method for forming the same. The gated p-i-n diode comprises: a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode on the gate dielectric; a source gate spacer and a drain gate spacer along respective edges of the gate dielectric and...

20060091489 - Trench photodetector: Trench type PIN photodetectors are formed by etching two sets of trenches simultaneously in a semiconductor substrate, the wide trenches having a width more than twice as great as the narrow trenches by a process margin; conformally filling both types of trenches with a sacrificial material doped with a first...

20060091492 - Depositing titanium silicon nitride films for forming phase change memories: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times,...

20060091493 - Locos schottky barrier contact structure and its manufacturing method: A LOCOS Schottky barrier contact structure of the present invention comprises a raised diffusion guard ring being surrounded by an outer LOCOS field oxide layer, a recessed semiconductor substrate being surrounded by the raised diffusion guard ring, a metal silicide layer being formed over the raised diffusion guard ring and...

20060091495 - Ceramic thin film on base metal electrode: A method including forming a first metal material layer on a dielectric material; transitioning a portion of the first metal material adjacent to the dielectric to a first oxidation state and a portion of the metal material peripheral to the dielectric material to a second different oxidation state; and forming...

20060091494 - High-permittivity insulation film, thin film capacity element, thin film multilayer capacitor, and production method of thin film capacity element: A dielectric thin film 8, comprising a first bismuth layer-structured compound layer 8a expressed by a composition formula of (Bi2O2)2+(Am−1 Bm O3m+1)2− or Bi2 Am−1 Bm O3m+3, wherein “m” is a positive number, “A” is at least one element selected from Na, K, Pb, Ba, Sr, Ca and Bi, and...

20060091496 - Metal-insulator-metal device: A metal-insulator-metal device includes a layer having a major dimensional surface. The layer has a first portion having a first boundary, a second metal portion having a second boundary facing the first boundary in a direction parallel to the surface and a non-linear dielectric between the first boundary and the...

20060091497 - Semiconductor device: A semiconductor device 100 includes a transistor, through which an electrical current flows via a first N-type buried region 106 and a second N-type buried region 108 having a conductivity type same as an N-type collector region 118 has. In semiconductor device 100, an N-type coupling region 107 that is...

20060091498 - Asymetric layout structures for transistors and methods of fabricating the same: High power transistors are provided. The transistors include a source region, a drain region and a gate contact. The gate contact is positioned between the source region and the drain region. First and second ohmic contacts are provided on the source and drain regions, respectively. The first and second ohmic...

20060091499 - Ald zno seed layer for deposition of zno nanostructures on a silicon substrate: Zinc-oxide nanostructures are grown without using a metal catalyst by forming a seed layer of polycrystalline zinc oxide on a surface of a substrate. The seed layer can be formed by an atomic layer deposition technique. Growth of at least one zinc-oxide nanostructure is induced on the seed layer. The...

20060091500 - Nitride based semiconductor device and process for preparing the same: A process for preparing a nitride based semiconductor device in accordance with the present invention comprises growing a high temperature AlN single crystal layer on a substrate; growing a first GaN layer on the high temperature AlN single crystal layer in a first V/III ratio, under a first pressure of...

20060091501 - Nitride semiconductor device and manufacturing method thereof: Provided are a nitride semiconductor device and a manufacturing method thereof The nitride semiconductor device includes an insulating layer and a metal layer formed on a nitride semiconductor layer. The insulating layer makes contact with the nitride semiconductor layer. A separation preventing layer is formed between the insulating layer and...

20060091502 - Multilayer structure comprising a substrate and a layer of silicon and germanium deposited heteroepitaxially thereon, and a process for producing it: A multilayer structure, comprises a substrate and a layer of silicon and germanium (SiGe layer) deposited heteroepitaxially thereon having the composition Si1-xGex and having a lattice constant which differs from the lattice constant of silicon, and a thin interfacial layer deposited on the SiGe layer and having the composition Si1-yGey,...

20060091503 - High voltage lateral diffused mosfet device: A semiconductor device comprises a substrate. A source active region and a drain active region are disposed in the substrate and spaced from one another in a first dimension. The source active region has a first and a second outline defining a width of the source active region in a...

20060091504 - Film circuit substrate having sn-in alloy layer: In one embodiment, a film circuit substrate comprises an insulating film made of polyimide resin; a conductive circuit pattern formed on the insulating film, the circuit pattern including an inner lead to be connected with a conductive bump of a semiconductor chip through a bump bonding process; and a tin-indium...

20060091505 - Low cost power mosfet with current monitoring: A semiconductor integrated circuit package having a common source current sensing circuit includes a main die having an integrated circuit, the main die including a source bonding pad and a gate bonding pad disposed on an upper surface, a leadframe having a leadframe pad disposed under the main die, and...

20060091506 - Lead frame having a lead with a non-uniform width: A lead frame may include a plurality of leads, each having a bonding portion electrically connected to a semiconductor chip and an attaching portion. A tape may be provided on the attaching portions of the leads. The attaching portion of each lead may have a width that is smaller than...

20060091507 - Ic package structures having separate circuit interconnection structures and assemblies constructed thereof: Disclosed are IC package structures comprised of standard IC packages modified with separate circuit interconnection structures and disposed to interconnect either directly to other IC packages or to intermediate pedestal connectors which serve to support and interconnect various circuit elements, thus effectively allowing critical signals to bypass the generally less...

20060091513 - Chip package having flat transmission surface of transparent molding compound and method for manufacturing the same: A chip package having flat transmission surface of transparent molding compound mainly comprises a substrate, a chip, a transparent cover and a transparent molding compound. The transparent molding compound is formed between the substrate and the transparent cover to seal the chip. The transparent molding compound is tightly attached to...

20060091511 - Chip-on-board package having flip chip assembly structure and manufacturing method thereof: A chip-on-board (COB) package has a flip chip assembly structure and is used for an integrated circuit (IC) card. The COB package has conductive patterns as contact terminals on an outer surface of a non-conductive film, and an IC chip on an inner surface of the film. The film has...

20060091514 - Fan out type wafer level package structure and method of the same: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover,...

20060091509 - Flip chip package including a non-planar heat spreader and method of making the same: A flip chip package generally includes a substrate, a flip chip die, and a heat spreader. The flip chip die is coupled to the substrate. The heat spreader is coupled to the flip chip die. The heat spreader can include one or more walls. Generally, the one or more walls...

20060091508 - Power distribution within a folded flex package method and apparatus: A device includes a folded flex substrate. A memory die is connected to a first side of the folded flex substrate. A logic die is connected to a second side of the folded flex substrate. A trace routing pattern of source voltage signals is identical to a trace routing pattern...

20060091510 - Probe card interposer: A probe card interposer includes a substrate with a plurality of conductive bumps disposed on first surface of the substrate. Each conductive bump comprises a dielectric core and a plurality of conductive leads. The suspended ends of the conductive wires extend toward the centers of the corresponding dielectric cores and...

20060091512 - Semiconductor device and manufacturing process thereof: The semiconductor device according to one of the embodiments of the present invention includes a metal block having first and second main surfaces and defining a recess on the first main surface. It also includes a semiconductor chip received within the recess of the metal block and mounted on the...

20060091515 - Sensor chip packaging structure: A sensor chip for defining an exposed molding region is disclosed. The sensor chip includes a semiconductor chip and a metal dam bar protruding from the active surface of the semiconductor chip. The active surface of the semiconductor chip includes a sensing region and at least one bonding pad is...

20060091516 - Flexible leaded stacked semiconductor package: A multi-chip semiconductor device comprises two semiconductor assemblies vertically aligned so that the second active chip surface (110a) faces the first active chip surface (101a) and forms a gap (120) between the assemblies. Encapsulation material (130) fills the gap and couples the first and second assemblies together to form the...

20060091519 - Multiple die stack apparatus employing t-shaped interposer elements: Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed....

20060091520 - Multiple die stack apparatus employing t-shaped interposer elements: Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed....

20060091518 - Semiconductor module having an internal semiconductor chip stack, and method for producing said semiconductor module: A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top...

20060091517 - Stacked semiconductor multi-chip package: Disclosed herein is a stacked semiconductor multi-chip package. The semiconductor multi-chip package comprises a substrate, a lower die mounted on an upper surface of the substrate to electrically connect to a circuit printed in a pattern on the substrate, an upper die electrically connected to the substrate via at least...

20060091521 - Stacking system and method: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected...

20060091522 - Plastic package and semiconductor component comprising such a plastic package, and method for its production: A plastic package and to a semiconductor component including such a plastic package, as well as to a method for its production is disclosed. In one embodiment, the plastic package includes plastic outer faces, which include lower outer contact faces on a lower side of the plastic package and upper...

20060091523 - Semiconductor device and a method for manufacturing of the same: A first solder resist section and a second solder resist section are formed over an upper surface of a wiring board. A semiconductor chip is bonded onto the first solder resist section via an adhesive interposed therebetween. Electrodes of the semiconductor chip are respectively electrically connected to connecting terminals exposed...

20060091524 - Semiconductor module, process for producing the same, and film interposer: A semiconductor module, comprising: a semiconductor element having a principal face on which an element electrode is formed; and a film member comprising an insulating resin layer having a front face and a rear face which is opposite to said front face, and a wiring pattern formed on the rear...

20060091525 - Wiring board with semiconductor component: An electronic device comprised of a wiring board with a semiconductor component. The device is unlikely to have any defects, such as cracks to a solder joint portion during a reflow process of a flip-chip connection. The semiconductor component is flip-chip bonded at a pad array at a component side...

20060091526 - Hybrid integrated circuit device, and method for fabricating the same, and electronic device: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate,...

20060091529 - High capacity thin module system and method: Flexible circuitry is populated with integrated circuitry disposed along one or both of its major sides. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. The circuit-populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on...

20060091528 - High heat dissipation flip chip package structure: A high heat dissipation flip chip package structure including a substrate, a chip, a supporting structure, and a heat spreader is provided. The substrate has a substrate surface. The chip has an active surface with several bumps formed thereon. The bumps are connected to the substrate surface. The supporting structure...

20060091527 - Semiconductor package with heat sink and method for fabricating same: A semiconductor package with a heat sink and a method for fabricating the same are proposed. The heat sink is provided with a rigid and thermally resistant detach member on a top surface thereof, and is attached via its bottom surface to a chip mounted on a chip carrier. The...

20060091531 - Cavity-down thermally enhanced package: A cavity-down thermally enhanced package mainly comprises a heat spreader, a thermally conductive metal ring, a circuit substrate and a chip. The circuit substrate is attached to a receiving surface of the heat spreader, and has an opening for exposing part of the receiving surface. The thermally conductive metal ring...

20060091530 - Multi-package module with heat spreader: A multi-package module (MPM) with a heat spreader is disclosed, which comprises a substrate, a chip, a plurality of chip scale packages (CSP), and a heat spreader. The CSPs are disposed on the peripheral region of the substrate, and the chip is disposed on the central region of the substrate...

20060091532 - Carbonaceous composite heat spreader and associated methods: A heat spreader including a plurality of carbonaceous particles present in an amount of at least about 50% by volume of the heat spreader. A non-carbonaceous material is also present in an amount of at least about 5% by volume of the heat spreader, the non-carbonaceous material including an element...

20060091534 - Chip part manufacturing method and chip parts: The present invention provides a chip part manufacturing method comprising a separating process capable of suppressing deformation of chip parts, and also provides chip parts. It comprises a step of forming a plurality of frame-like void portions (32) in one main surface of substrate (30) and insulating resin layer (20)...

20060091533 - Multi-row substrate strip and method for manufacturing the same: A multi-row substrate strip mainly comprises a plurality of first and second substrate units in parallel, a plurality of connecting bars, a degating metal layer and at least one plating layer. The connecting bars are used to connect the first substrate units and connect the second substrate units. The degating...

20060091536 - Bond pad structure with stress-buffering layer capping interconnection metal layer: A bond pad structure for an integrated circuit chip has a stress-buffering layer between a top interconnection level metal layer and a bond pad layer to prevent damages to the bond pad structure from wafer probing and packaging impacts. The stress-buffering layer is a conductive material having a property selected...

20060091535 - Fine pitch bonding pad layout and method of manufacturing same: Disclosed herein is a bonding pad formed on an IC chip for electrically coupling the IC chip to another device or component, and associated methods of manufacturing the bonding pad. In one embodiment, the bonding pad comprises a bonding portion having a bonding surface configured to receive an electrical connector....

20060091537 - Semiconductor device and method of fabricating the same: Slit-like gap regions are provided at sides of a bonding pad that surrounds a window for bonding. The bonding pad is divided into a region at the side of the window and another region at the side of an adjoining interconnection layer in which the gap regions are the boundaries...

20060091541 - Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion: A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (303, preferably silicon nitride) on the chip surface, followed by a...

20060091538 - Low profile and tight pad-pitch land-grid-array (lga) socket: The apparatus and method described herein are for coupling an integrated circuit to a circuit board through a low profile compression socket. A plurality of compressible columns disposed in a substrate, when compressed, make electrical connection to a first set of pads on an integrated circuit and to a plurality...

20060091540 - Semiconductor chip with post-passivation scheme formed over passivation layer: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and...

20060091539 - Semiconductor device, circuit board, electro-optic device, electronic device: A semiconductor device including a semiconductor element, an electrode pad formed on the semiconductor element, and a bump electrode conductively connected to the electrode pad which includes a resin bump formed on an active face of the semiconductor element and a conductive layer provided from the electrode pad to the...

20060091542 - Flip chip package including a heat spreader having an edge with a recessed edge portion and method of making the same: A flip chip package generally includes a substrate, a flip chip die, and a heat spreader. The flip chip die is coupled to the substrate. The heat spreader is coupled to the flip chip die. The flip chip package can further include an encapsulate. The encapsulate can protect the flip...

20060091543 - Land grid array module: Disclosed is a land grid array module comprising: a substrate; a plurality of active and passive components mounted on both sides of the substrate; and a molding compound for encapsulating the both sides of the substrate with the active and passive components mounted thereon. The land grid array module mounts...

20060091545 - Printed circuit board for high-speed electrical connectors: A printed circuit board exit arrangement is disclosed for use in high speed connector mounting applications. A ground plane has one or more open areas formed in it that surround pairs of signal vias formed in the board that are used to convey differential signals. The ground plane has a...

20060091544 - Wiring board and manufacturing method therefor: A wiring board is manufactured by a step of forming a meshy cylindrical body, where plural conductive rings are connected to each other at plural positions in the respective peripheral direction, a step of forming laminated meshy sheets, by squashing the meshy cylindrical body in the radial direction, a step...

20060091546 - Layer system: On account of their type of coating, layer systems of the prior art often exhibit poor adhesion to the substrate. If the components are subject to high mechanical stresses, the layer can then become detached. The layer system according to the invention has separately produced anchoring means which allow stronger...

20060091547 - Substrate provided with a thin film pattern, method of manufacturing a device, electro-optic device, and electronic instrument: A thin film pattern substrate, including an area provided to the substrate to form a recess and including a wider section and a linear section connected to the wider section, wherein the wider section having a width greater than the width of the linear section, and a thin film pattern...

20060091548 - Flexible wiring board for tape carrier package having improved flame resistance: A flexible wiring board for tape carrier package having improved flame resistance is disclosed. The flexible wiring board has an insulating film having a bending slit, a wiring pattern formed thereon and crossing the bending slit, an adhesive layer adhering the wiring pattern to the insulating film, a flex resin...

20060091550 - Method of analyzing operation of semiconductor integrated circuit device, analyzing apparatus used in the same, and optimization designing method using the same: In a method of analyzing a power noise based on the circuit information of a semiconductor integrated circuit device, the power noise is analyzed in consideration of the influence of the impedance of a substrate. Consequently, the impedance of the substrate which has not been conventionally considered is taken into...

20060091549 - Semiconductor device with suppressed copper migration: A semiconductor device having: a semiconductor substrate; a plurality of circuit regions formed on the semiconductor substrate, the circuit regions including circuits driven at multiple supply voltages; interlayer insulating film or films formed above the semiconductor substrate; copper wirings buried in the interlayer insulating film or films, a minimum wiring...

20060091551 - Differentially metal doped copper damascenes: A method of forming a copper filled semiconductor feature having improved bulk properties including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a...

20060091554 - Multilayered barrier metal thin-films: A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film...

20060091552 - Refractory metal substrate with improved thermal conductivity: A substrate for semiconductor and integrated circuit components including: a core plate containing a Group VIB metal from the periodic table of the elements and/or an anisotropic material, having a first major surface and a second major surface and a plurality of openings extending, at least partially, from the first...

20060091553 - Wiring board and method for producing same: The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of...

20060091555 - Method of and apparatus for mounting an electronic part to a substrate: An apparatus 1 for mounting an electronic part to a substrate according to the present invention includes: a mounting unit 12 for mounting an electronic part 11 to a substrate 10; a substrate supplying unit 17 for supplying the substrate 10 to a predetermined position; an electronic part supplying unit...

20060091556 - Semiconductor device and its manufacturing method: A semiconductor device with a new three-dimensional structure comprises a semiconductor substrate including a trench vertically formed to a surface of the semiconductor substrate, a plurality of isolations formed in side and bottom surfaces of the trench in a depth direction of the trench, a plurality of functional elements formed...

20060091558 - Circuitized substrate with trace embedded inside ground layer: A circuitized substrate with trace embedded inside ground layer mainly comprises a trace layer, a first dielectric layer, a ground layer, a second dielectric layer, and at least one embedded conductive trace. The embedded conductive trace is located between the first dielectric layer and the second dielectric layer. The embedded...

20060091557 - Semiconductor device and its manufacturing method: There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron...

20060091559 - Hardmask for improved reliability of silicon based dielectrics: The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising...

20060091560 - Multi-chip stack package: A multi-chip stack package mainly comprises a substrate, a first chip, a redistribution structure and at least one second chip. The first chip is disposed on the substrate by an active surface facing upwards. The redistribution structure comprises a plurality of first intermediate pads, a plurality of second intermediate pads...

20060091561 - Electronic component comprising external surface contacts and a method for producing the same: The invention relates to an electronic device and a method for producing it having external area contacts and having a rewiring structure and also having a semiconductor chip, which has contact areas, the external area contacts being electrically connected to the contact areas at least by means of the rewiring...

20060091562 - Flip chip bga process and package with stiffener ring: An assembly comprises a substrate, a ring structure bonded to a first side of the substrate; and a die flip-chip-bonded to a second side of the substrate opposite the first side....

20060091563 - Semiconductor device and method for fabricating the same: A semiconductor device has a substrate having electrode pads, a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween, a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having electrode pads on the upper surface thereof,...

20060091565 - Led with self aligned bond pad: A method is disclosed for attaching a bonding pad to the ohmic contact of a diode while reducing the complexity of the photolithography steps. The method includes the steps of forming a blanket passivation layer over the epitaxial layers and ohmic contacts of a diode, depositing a photoresist layer over...

20060091564 - System to control effective series resistance of decoupling capacitor: According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts and a decoupling capacitor. The decoupling capacitor may include a positive terminal contact pad coupled to a first one of the plurality...

20060091566 - Bond pad structure for integrated circuit chip: An integrated circuit chip is provided, which includes a bond pad structure, a low-k dielectric layer, and active circuits. The bond pad structure includes a conductive bond pad, an Mtop solid conductive plate, and an Mtop−1 solid conductive plate. The Mtop solid conductive plate is located under the bond pad....

20060091567 - Cavity-down package and method for fabricating the same: A method for fabricating a cavity-down package is provided. A chip carrier includes a chip cavity. A chip is disposed inside the cavity, and a plurality of bonding materials is formed at the corners of the chip. The bonding materials are cured to protect the corners of the chip. Next,...

20060091568 - Semiconductor device and method for manufacturing same: A process yield of a semiconductor device is enhanced. To that end, there is provided a semiconductor device comprising a substrate having a component mount face with semiconductor chips mounted thereon, the substrate being provided with a plurality of connection leads, and a cap made of resin, placed over the...