Active solid-state devices (e.g., transistors, solid-state diodes) inventions 04/06

20060086931 - Electro- and electroless plating of metal in the manufacture of pcram devices: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a...

20060086932 - Nitride based semiconductor device: The present invention provides a nitride based semiconductor device comprising an active layer having a quantum well layer and a quantum barrier layer, wherein the device includes an electron emitting layer formed of at least two repeats of a first nitride semiconductor layer and a second nitride semiconductor layer having...

20060086933 - Vertical organic transistor: A vertical organic transistor comprises a substrate, a first electrode positioned over the substrate, a first semiconductor layer formed over the first electrode, a second electrode formed on the first semiconductor layer and shaped into a prescribed pattern, a second semiconductor layer formed over the second electrode and the first...

20060086935 - Semiconductor device and manufacturing method thereof: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of...

20060086934 - Semiconductor device formed on insulating layer and method of manufacturing the same: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration...

20060086936 - Method of forming a transistor having a dual layer dielectric: Embodiments of methods, apparatuses, components, and/or systems for forming transistor having a dual layer dielectric are described....

20060086938 - Flat panel display and method of fabricating the same: A flat panel display, and method of fabricating the same, including a substrate having a display portion and a pad that is arranged on the substrate and is electrically coupled with the display portion. The pad includes a pad electrode arranged on the substrate, a passivation layer arranged on the...

20060086937 - Tft array substrate, liquid crystal display device, manufacturing methods of tft array substrate and liquid crystal display device, and electronic device: A TFT array substrate includes a thin film transistor section in which a gate electrode is formed on a substrate, and a semiconductor layer is formed on the gate electrode via a gate insulation layer. The semiconductor layer of this TFT array substrate has a shape formed by dropping a...

20060086939 - Solderable top metal for sic device: A silicon carbide device includes at least one power electrode on a surface thereof, a solderable contract formed on the power electrode, and at least one passivation layer that surrounds the solderable contact but is spaced from the solderable contract, thereby forming a gap....

20060086940 - Package structure of multi-chips light-emitting module: The present invention pertains to a package structure of multi-chips light-emitting module, wherein via the packaging technology of semiconductor, a plurality of light emitting diode chips are installed on the disposing portion of a lead frame, and the chips and the lead frame are interconnected with bond wires, and then...

20060086941 - Superluminescent diode including active layer formed of various sized quantum dots and method of manufacturing the same: The present invention provides a superluminescent diode, which has a wide wavelength bandwidth and a high optical power, and a method of manufacturing the same. The superluminescent diode includes an active layer having a chirped quantum dot (CQD) structure formed over the substrate, wherein the active layer emits lights of...

20060086942 - High-brightness gallium-nitride based light emitting diode structure: A GaN-based LED structure is provided so that the brightness and luminous efficiency of the GaN-based LED are enhanced effectively. The greatest difference between the GaN-based LEDs according to the invention and the prior arts lies in the addition of a masking buffer layer on top of the p-type contact...

20060086943 - Light emitting diode covered with a reflective layer and method for fabricating the same: A light emitting diode (LED) covered with a reflective layer by imprinting process is provided. The imprinting process includes coating a plastic layer on a mold to form an imprinting substrate; coating a reflective layer on the plastic layer and modifying the shape of the reflective layer to fit the...

20060086944 - Light emitting module: The light emitting module includes a substrate, a light emitting element and a driving circuit chip. The light emitting element is attached to the substrate and has a plurality of first contacts on a top surface thereof. The driving circuit chip is attached onto the substrate and has a plurality...

20060086945 - Package structure for optical-electrical semiconductor: A package structure for an optical-electrical semiconductor is described. The package structure has a thermal conductive structure for heat transfer and is integrally formed in one piece to improve the structural strength thereof, while the thermal conductive structure prevent over-heating of the LED device for greater longevity. The package structure...

20060086946 - Method and apparatus for mixing light emitted by a plurality of solid-state light emitters: In one embodiment, light emitted by a plurality of solid-state light emitters is mixed by mounting the plurality of solid-state light emitters on a transparent to translucent substrate so that they primarily emit light away from the substrate. The light emitters are then covered with a transparent to translucent encapsulant;...

20060086947 - Securing a transistor outline can within an optical component: The present invention relates to affixing components of optical packages. The optical packages can include an optical component, such as a TO-Can. The TO-Can can house an optical transmitter and/or an optical receiver. Another optical component of the optical package can be a barrel for aligning the TO-Can with an...

20060086948 - Semiconductor device and semiconductor device manufacturing method: A technique is provided which enables formation of nitride semiconductor layers with excellent flatness and excellent crystallinity on a gallium nitride substrate (GaN substrate), while improving the producibility of the semiconductor device using the GaN substrate. A gallium nitride substrate is prepared which has an upper surface having an off-angle...

20060086949 - Semiconductor structure and method of making same: A semiconductor structure includes a substrate having a surface and being made of a material that provides atypical surface properties to the surface, a bonding layer on the surface of the substrate, and a further layer molecularly bonded to the bonding layer. A method for fabricating such a semiconductor structure...

20060086950 - Method for making a passivated semiconductor substrate: The present invention is related to a method for making a passivated semiconductor substrate comprising the steps of providing a substrate surface comprising or consisting of mono-crystalline semiconductor material other than silicon and forming a silicon layer on the substrate surface, such that the silicon layer is substantially lattice matched...

20060086951 - Semiconductor memory device for storing data in memory cells as complementary information: A twin-cell type semiconductor memory device in which the area of a chip can be reduced. In the twin-cell type semiconductor memory device for storing data in at least one pair of memory cells as complementary information, memory cells are arranged at each of a plurality of word lines at...

20060086952 - Capacitor and method of manufacturing the same: A capacitor and method of manufacturing the same include an insulating interlayer, a lower electrode, a protection structure, a dielectric layer and an upper electrode. The insulating interlayer may include a conductive pattern formed on a substrate. The lower electrode may be electrically connected to the conductive pattern. The protection...

20060086954 - Multi-layer film stack for extinction of substrate reflections during patterning: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric...

20060086953 - Twin-ono-type sonos memory: A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second...

20060086955 - Solid-state image sensor and method for fabricating the same: A solid-state image sensor in which a plurality of unit pixel portions, each including a light receiving area which generates electric charges by light irradiation and a transistor which outputs an electric signal in accordance with the light receiving area, are arranged in a two-dimensional array, in which: each of...

20060086956 - Solid-state imaging device: A solid-state imaging device includes a photoelectric conversion section which is provided for each pixel and which converts light incident on a first surface of a substrate into signal charges, a circuit region which reads signal charges accumulated by the photoelectric conversion section, a multilayer film including an insulating film...

20060086957 - Cmos image sensor using reflection grating and method for manufacturing the same: A CMOS image sensor having a reflection grating adapted to reflect and refract light not parallel to an optical axis is disclosed. The CMOS image sensor includes at least one photodiode, a photo-shielding film, a first interlayer insulation film, a color filter, a second interlayer insulation film, and at least...

20060086959 - Semiconductor device: There is provided a semiconductor device including a semiconductor substrate which has an element region in which a diffusion layer for a source or a drain is formed, and a trench for a capacitor, a capacitor dielectric film which is formed on inner surfaces of the trench, a storage electrode...

20060086958 - Wire structure, semiconductor device, mram, and manufacturing method of semiconductor device: The present invention provides a wire structure where reduction in the amount of current that can be made to flow through the wire can be suppressed (a current comprising a large current density can be made to flow), even in the case where the wire is downsized. A wire structure...

20060086961 - Semiconductor device having a stacked capacitor: A capacitor formed in a deep-hole has a bottom electrode, a capacitor insulator film and a top electrode. The bottom electrode includes a sidewall conductive film formed on the sidewall of a top portion of the deep-hole, and an inner conductive film formed on the sidewall conductive film and the...

20060086960 - Semiconductor memory and method for manufacturing the same: A capacitor of a semiconductor memory of the present invention includes: a lower electrode which covers the surface of a storage node hole from the bottom to at least one of the sidewalls up to a level lower than the top surface of a second interlayer insulating film; a capacitive...

20060086964 - Capacitor device and method of manufacturing the same: A method of manufacturing a capacitor device of the present invention, includes the steps of, forming an insulating layer on a substrate, forming a recess portion in the insulating layer by an imprinting process, forming a lower electrode by filling a metal layer in the recess portion in the insulating...

20060086962 - Stacked capacitor and method for preparing the same: The present invention discloses a stacked capacitor having interdigital electrodes and method for preparing the same. The stacked capacitor comprises a first interdigital electrode, a second interdigital electrode and a dielectric material sandwiched between the first interdigital electrode and the second interdigital electrode. The first and the second interdigital electrodes...

20060086963 - Stacked capacitor and method for preparing the same: The present invention discloses a stacked capacitor having interdigital electrodes and method for preparing the same. The stacked capacitor comprises a first interdigital electrode, a second interdigital electrode and a dielectric material sandwiched between the first interdigital electrode and the second interdigital electrode. The first and the second interdigital electrodes...

20060086965 - Semiconductor device: An embodiment of the invention provides a semiconductor device having a capacitor including a first electrode, a second electrode and an insulator. The semiconductor device includes first layers and second layers laminated alternately. The first layers each includes lines of the first electrode and lines of the second electrode arranged...

20060086966 - Memory device comprising single transistor having functions of ram and rom and methods for operating and manufacturing the same: A memory device including a single transistor having functions of RAM and ROM and methods for operating and manufacturing the same are provided. The memory device includes a single transistor formed on a substrate. The transistor may be a memory transistor having a gate with a nonvolatile memory element, or...

20060086967 - Nonvolatile memory device and method for fabricating the same: A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a...

20060086968 - Method of fabricating nand-type flash eeprom without field oxide isolation: Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells....

20060086969 - Floating gate transistors: A floating gate MOS transistor comprises one or more control gates, an active channel, and at least one floating gate disposed between the control gate(s) and the active channel. First and second non-linear resistances couple the floating gate to first and second control voltage sources respectively, the non-linear resistances forming...

20060086970 - Non-volatile memory cell structure with charge trapping layers and method of fabricating the same: In a non-volatile memory device and a method for forming such a device, at least one edge of the charge trapping layer is recessed. In this manner, the threshold voltage of the device during a programming operation and the threshold voltage of the device during an erase operation are maintained...

20060086971 - Semiconductor device and method for fabricating the same: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the...

20060086972 - Semiconductor device and method of manufacturing same: A semiconductor device comprises: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a trench formed in the second semiconductor region; a thick gate insulating film selectively provided in a center area of a bottom...

20060086973 - Semiconductor integrated circuit and a semiconductor device: A semiconductor integrated circuit that has a quick response to changes in source/drain electrode voltage having an LDMOS transistor. The transistor has a second conduction type first well region formed in a first conduction type semiconductor substrate; a first conduction type second well region formed in the first well region;...

20060086974 - Integrated circuit with multi-length power transistor segments: A monolithic power integrated circuit fabricated on a semiconductor die includes a control circuit and a first output high voltage field-effect transistor (HVFET) having source and drain segments substantially equal to a first length. A second output HVFET has source and drain segments substantially equal to a second length. At...

20060086975 - Device junction structure: A semiconductor device includes a gate structure having a plurality of gate layers, which are layered upon a gate dielectric. A pair of thin spacers is formed on corresponding sidewalls of the gate structure. Each thin spacer is at most 25 nanometers (nm) wide. Length of the gate structure is...

20060086979 - Metal wiring, method of manufacturing the same, tft substrate having the same, method of manufacturing tft substrate and display device having the same: A TFT substrate includes a transparent substrate, a scan line, a data line, a switching device and a pixel electrode. The scan line is formed on the transparent substrate. The data line is formed on the transparent substrate such that the data line is electrically insulated from the scan line....

20060086976 - Method of forming a component having dielectric sub-layers: Embodiments of methods, apparatuses, devices, and/or systems for forming a component having dielectric sub-layers are described....

20060086977 - Nonplanar device with thinned lower body portion and method of fabrication: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top...

20060086981 - Power converter: The power converter for solving the above-described problem has a module section and a drive section for operating the module section. The drive section has a drive circuit. The drive circuit is provided so as to correspond to the first semiconductor element which is one of the semiconductor elements comprising...

20060086980 - Semiconductor device, sram and manufacturing method of semiconductor device: A semiconductor device according to the present invention is provided with an SOI substrate, an active region, a first insulating film (complete separation insulating film), a second insulating film (partial separation insulating film), and a contact portion. Here, the active region is formed within the surface of the SOI layer....

20060086978 - Thin film transistor, electro-optical device and electronic apparatus: A thin film transistor includes a semiconductor layer formed over a substrate, and an electrode member formed over the substrate by a liquid phase method. The electrode member includes a base layer composed of a metal material and an outer surface layer deposited on at least one surface of the...

20060086982 - Semiconductor device and manufacturing method thereof: In order to increase an aperture ratio, a part of or all of a gate electrode that overlaps with channel formation regions (213, 214) of a pixel TFT is caused to overlap with second wirings (source line or drain line) (154, 157). Additionally, a first interlayer insulating film (149) and...

20060086983 - Electrostatic protective element of semiconductor integrated circuit: An electrostatic protective element of the present invention comprises: a second-conductive-type and lightly-doped first diffusion layer to be a collector, which is formed to be in contact with a first conductive type semiconductor substrate; a first-conductive-type second diffusion layer to be a base, which is formed on the first diffusion...

20060086984 - Method of assessing potential for charging damage in integrated circuit designs and structures for preventing charging damage: Disclosed is a method and circuit for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The method/circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices...

20060086985 - Semiconductor device: A semiconductor device includes first integrated circuit comprising first to third MOSFET having same channel type, and first to third MOSFETs including gate electrode and gate sidewall insulating film on sidewall of gate electrode, and distance between gate electrodes of first and second MOSFETs, and distance between gate electrodes of...

20060086986 - Storage device with charge trapping structure and methods: A storage device includes a first semiconducting layer having a p-dopant and a second semiconducting layer having an n-dopant, disposed on the first semiconducting layer forming a junction between the first and the second semiconducting layers. The storage device also includes a charge trapping structure disposed on the second semiconducting...

20060086987 - Method for manufacturing a semiconductor device with reduced floating body effect: A semiconductor device includes a substrate, a first device situated on the substrate, the first device including a source and a drain each situated extending a first depth within the substrate, and a second device situated on the substrate, the second device including a source and a drain each situated...

20060086988 - Semiconductor integrated circuit and fabrication method thereof: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step...

20060086990 - Semiconductor device and fabrication method therefor: A semiconductor device has a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type which is formed to extend from the surface of the semiconductor substrate toward the inside thereof, a pair of second well regions of a second conductivity which are formed...

20060086989 - Semiconductor devices with reduced impact from alien particles: An improved semiconductor device is disclosed with a NMOS transistor formed on a P-Well in a deep N-well, a PMOS transistor formed on a N-Well in the deep N-well, a first voltage coupled to a source node of the PMOS, and a second voltage higher than the first voltage coupled...

20060086991 - Semiconductor component and method for producing the same: A method for producing a semiconductor component has the following step: the front side (101) of the semiconductor body (100) is irradiated with high-energy particles using the terminal electrode (40) as a mask, in order to produce recombination centres (80A, 80B) in the semiconductor body (100) for the recombination of...

20060086992 - High voltage transistor and methods of manufacturing the same: In a HV transistor having a high breakdown voltage and a method of manufacturing the same, a first insulation pattern is formed on a semiconductor substrate by oxidizing a portion of the substrate, and a second insulation pattern is formed such that at least a portion of the first insulation...

20060086993 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a Si substrate, a gate insulating film formed on the Si substrate, the gate insulating film being formed of an oxide film containing at least one selected from the group of Zr, Hf, Ti and a lanthanoid series metal, and having a single local minimal value...

20060086994 - Nanoelectromechanical components: A nanotube device is disclosed which includes a nanotube with a longitudinal and a lateral extension, a structure for supporting at least a first part of the nanotube, and a first device for exerting a force upon the nanotube in a first direction defined by its lateral extension. At least...

20060086995 - Temperature-compensated micro-electromechanical device, and method of temperature compensation in a micro-electromechanical device: A micro-electromechanical device includes a semiconductor body, in which at least one first microstructure and one second microstructure of reference are integrated. The first microstructure and the second microstructure are arranged in the body so as to undergo equal strains as a result of thermal expansions of the body. Furthermore,...

20060086996 - Solid state imaging device: A solid state imaging device, includes: a sensor cell array having a plurality of sensor cells arranged in a matrix on a substrate, each sensor cell including: a photoelectric transducer provided in the substrate and generating photo-generated electric charges according to an incident light; a transfer gate formed on the...

20060086997 - Schottky barrier diode: A buffer layer made of i-GaAs not doped with impurities, and an n+ GaAs layer doped with a high-concentration of n-type impurities are stacked in the order named on a semi-insulating GaAs substrate. An n− GaAs layer doped with a low-concentration of n-type impurities is partially located on the n+...

20060086998 - Semiconductor apparatus and method of manufacturing the same: The semiconductor apparatus is disclosed that includes a partial SOI substrate including an oxide film; a lateral first MOSFET section having a planar gate structure and formed in the portion of the partial SOI substrate where there is an oxide film; a vertical second MOSFET section having a trench gate...

20060086999 - Semiconductor device: In a semiconductor device in which a control circuit region and a power transistor region are formed, a first dummy region is formed between a ground side transistor composing a push-pull circuit and the control circuit region while a second dummy region is formed between the ground side transistor and...

20060087000 - Semiconductor device and manufacturing method thereof: A semiconductor device has a semiconductor layer of silicon which has a plurality of element formation regions, and a trench isolation region for isolating the plurality of element formation regions from each other. The trench isolation region is formed by filling a trench formed in an upper part of the...

20060087001 - Programmable semiconductor device: A programmable device (eFuse), includes: a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having a first end (12a), a second end (12b), a fuse link (11) between the ends, and an upper surface S. The semiconductor material...

20060087002 - Semiconductor device: On a silicon substrate 120 of a semiconductor device, a field oxide film 101 is provided. On the field oxide film 101, two fuses 104 are provided. Directly below the fuses 104 in the silicon substrate 120, an n-type well 102 is provided. Besides the n-type well 102, a p-type...

20060087003 - Design and layout techniques for low parasitic capacitance in analog circuit applications: A semiconductor device that reduces the parasitic capacitance between a conductive trace and a substrate, and a method of fabricating the same. The semiconductor device includes a substrate, an insulator layer disposed upon the substrate, a conductive trace disposed upon the insulator layer, and an element disposed between the substrate...

20060087004 - Semiconductor device including metal-insulator-metal capacitor arrangement: A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with...

20060087005 - Deposited semiconductor structure to minimize n-type dopant diffusion and method of making: In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer...

20060087006 - Physical quantity sensor and manufacturing method therefor: A physical quantity sensor includes a pair of physical quantity sensor chips that are inclined with respect to the bottom of an exterior mold package whose side surfaces are each inclined in a thickness direction by an angle ranging from 0° to 5° and are formed in proximity to the...

20060087008 - Wafer dividing apparatus: A wafer dividing apparatus for dividing along dividing lines a wafer whose strength is reduced, along the dividing lines, comprising a tape holding means for holding a protective tape affixed to one surface side of the wafer; and a wafer dividing means comprising a first suction-holding member and a second...

20060087007 - Wafer treating apparatus and method: A wafer treating apparatus includes a support for supporting a plate-like base, a heating mechanism for heating the base placed on the support, a first coating mechanism for coating a fixing composition on a surface of the base placed on the support, a loading mechanism for loading a wafer on...

20060087009 - Cavity-down multiple-chip package: A cavity-down multiple-chip package mainly comprises a heat spreader, a circuit substrate with an opening, a chip, and at least one electronic element; wherein an upper surface of the circuit substrate defines at least one element mounting area; the heat spreader is disposed on said upper surface of the circuit...

20060087010 - Ic substrate and manufacturing method thereof and semiconductor element package thereby: The present invention pertains to an IC substrate, a manufacturing method thereof and a semiconductor element packaged thereby, wherein a plurality of patterned through-trenches on a metallic board are filled with an insulating material or other materials of different electric conductivity in order to separate the metallic board into a...

20060087011 - Wired circuit board: A wired circuit board having terminals that can provide reliable placement of molten metals on the terminals, to connect between the terminals and the external terminals with a high degree of precision. An insulating base layer 3 is formed on a supporting board 2, and a conductive pattern 4 is...

20060087014 - Bolster plate assembly for processor module assembly: Systems, methodologies, methods of manufacture, and other embodiments associated with semiconductor/processor module assemblies are described. One exemplary system embodiment includes a bolster plate assembly for a semiconductor module assembly that includes a bolster plate and a leaf spring pre-loaded onto the bolster plate. The example system may also include the...

20060087013 - Stacked multiple integrated circuit die package assembly: An electronic package assembly is formed with a plurality of integrated circuit dies stacked in layers. At least one first die is placed on a substrate. Each subsequent layer of the stack contains at least one die. Each die on each layer has a size and shape such that, when...

20060087012 - System to control effective series resistance of power delivery circuit: According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts, and an element having a plurality of resistive portions, each of the plurality of resistive portions being coupled to a respective one...

20060087015 - Thermally enhanced molded package for semiconductors: Integrated circuit packaging with improved thermal transmission from the integrated circuit heat source to the exterior of the packaging. Improved packaging employs a compressive interposer which allows for greater manufacturability of the packaged integrated circuit parts. Additionally different shaped compressive interposers are described....

20060087016 - Ic (integrated circuit) card: An IC card according to the present invention reduces or prevents a deterioration or damage on an electronic device to which the IC card is mounted. A buffer section made of a thermoplastic resin formed by a plastic injection molding is provided at the outer peripheral face of a memory...

20060087017 - Image sensor package: An image sensor package includes a chip carrier, an image sensor chip, a transparent cover, and an O-ring. The chip carrier has a plurality of inner leads. The image sensor chip has an active surface including a sensing area and a plurality of bonding pads thereon. The bonding pads are...

20060087018 - Multi-chip image sensor module: A multi-chip image sensor module includes a flexible module board, an image sensor chip, a transparent cover, and at least an IC chip. The flexible module board has a first die-attached portion, a second die-attached portion, at least one bent portion, and at least one bonding portion where the bent...

20060087019 - Multi-layer integrated semiconductor structure having an electrical shielding portion: A multi-layer integrated semiconductor structure is provided, which includes at least a first semiconductor structure and a second semiconductor structure coupled together via an interface. The interface includes at least a first portion adapted to provide a communication interface between the first semiconductor structure and the second semiconductor structure and...

20060087021 - Multilayer semiconductor device: The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips comprises a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device further comprises...

20060087020 - Semiconductor device and method for producing the same: In a semiconductor device, circuit boards are connected electrically to each other by via-conductors that penetrate sheet members, semiconductor elements arranged between substrates are contained in element-containing portions formed on the sheet members, and a low-elastic material whose elastic modulus is lower than the elastic modulus of the thermosetting resin...

20060087022 - Image sensor assembly and method for fabricating the same: An assembly device of an image sensor chip is disclosed. A flexible circuit has a die-attached portion, a plurality of bendable portions, and a plurality of bonding portions where the bendable portions extend from the die-attached portion and are connected to the corresponding bonding portions. A plurality of inner leads...

20060087023 - Functional coating of an scfm preform: The invention relates to a power semiconductor module having at least one semiconductor chip (11) made of a semiconductor material and having a first and a second main electrode (12, 13), a first and a second main connection (91, 92) and a contact lamina (2) in electrical contact with the...

20060087024 - Method and system for an improved power distribution network for use with a semiconductor device: Systems and methods for a structure for a power distribution network intended to distribute power from a PCB to a semiconductor device on a package. These improved power distribution networks may reduce current crowding in the BGA balls of a package and may serve to more equitably distribute current through...

20060087025 - Method of manufacturing a substrate with concave portions, a substrate with concave portions, a microlens substrate, a transmission screen, and a rear projection: A method of manufacturing a substrate 6 provided with a plurality of concave portions 61 is disclosed. The substrate 6 is used for manufacturing a microlens substrate provided with a plurality of microlenses as convex lenses which are to be formed using the plurality of concave portions 61. The method...

20060087026 - Audio amplifier assembly: An audio amplifier assembly that includes a semiconductor package having a semiconductor power die tuned for class D amplifier applications and a conductive clip used for low inductance integration into the amplifier circuit....

20060087027 - Semiconductor device capsule: A semiconductor device capsule (30) comprising a semiconductor assembly (32) mounted between opposed poles (34,36). At least one of the poles (34,36) includes slots (38) around the locality of the or each chip or group of chips (46) within the semiconductor assembly (32) to define a contact body portion (37)...

20060087028 - Method and system for a pad structure for use with a semiconductor package: Systems and methods for substrate layers used in attaching devices to a semiconductor package are disclosed. A novel pad structure may be employed on a substrate layer which has pads, each pad having a common electrical potential. Multiple pad openings may be employed on a single pad, allowing the attachment...

20060087029 - Semiconductor device and method of producing the same: A semiconductor device includes a semiconductor chip having a surface provided with connecting electrodes, a stacked structure made up of alternately stacked dielectric and wiring layers and provided on the surface of the semiconductor chip, a passive element provided in the stacked structure and electrically connected to the wiring layers;...

20060087030 - Array capacitor with resistive structure: An apparatus comprises a first plurality of contacts disposed on a first side of the apparatus, adapted to engage with a first corresponding plurality of contacts on an external integrated circuit package. The apparatus further comprises a plurality of capacitive storage structures selectively coupled to the first plurality of contacts,...

20060087031 - Assembly and method: An assembly comprises a substrate, such as a printed circuit board, with an electrically insulating layer provided thereon. The electrically insulating layer defines at least one opening, said opening being formed in a shape of an indicium relating to an aspect of the assembly....

20060087032 - Compliant interconnects for semiconductors and micromachines: A compliant interconnect is described that is useful for coupling semiconductor dies to other components. In one embodiment, the interconnect includes a base to couple to a first component and an arch extending from and integral with the base to couple to a second component. The interconnect may be formed...

20060087034 - Bumping process and structure thereof: A bumping process includes the steps of: firstly, providing a wafer; forming a first photo-resist layer on a active surface of the wafer and forming at least a first opening on the first photo-resist layer; next, forming a first copper pillar in the first opening; next, forming a second photo-resist...

20060087033 - Molded high density electronic packaging structure for high performance applications: A thermally enhanced ball grid array package is disclosed. The package includes a base layer element and a flip chip die mounted on the base layer element. The die has a first surface electrically coupled to the base layer element, a second surface opposite to the first surface, and lateral...

20060087035 - Solder wall structure in flip-chip technologies: A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a first solder wall on a perimeter of the first...

20060087036 - Chip-size package structure and method of the same: The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking...

20060087038 - Packaged device and method of forming same: A method of packaging an integrated circuit die (12) includes the steps of loading an array of soft conductive balls into recesses formed in a platen and locating the platen in a first part of a mold cavity. A second part of the mold is pressed against the balls to...

20060087037 - Substrate structure with embedded chip of semiconductor package and method for fabricating the same: A substrate structure with embedded chips of a semiconductor package and a method for fabricating the same are proposed. First of all, a carrier structure having a first carrier plate and a second carrier plate being directly formed on the first carrier plate is provided. The second carrier plate is...

20060087039 - Ubm structure for improving reliability and performance: A novel under-bump metallization (UBM) structure for providing electrical communication is described. The UBM structure includes a plurality of metallic layers, which are deposited onto a bonding pad of a semiconductor device, such as a semiconductor chip. The UBM structure may be provided as an interface between the bonding pad...

20060087040 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: an insulating film formed above a semiconductor substrate; a pad formed on the insulating film; a passivation film formed on the insulating film and the pad, the passivation film being provided with a first opening positioned on the pad; a first bulge member formed on the...

20060087041 - Semiconductor device: A semiconductor device is disclosed that includes a substrate, a first wiring structure arranged on the substrate which first wiring structure includes a first insulating layer and a first wiring layer arranged within the first insulating layer, a second wiring structure arranged on the first wiring structure which second wiring...

20060087042 - Semiconductor device and manufacturing method of the same: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A refractory metal layer is formed on a pad electrode formed on a semiconductor substrate with a first insulation film therebetween....

20060087043 - Semiconductor device having semiconductor chip on base through solder layer and method for manufacturing the same: A semiconductor device includes: a base member; a solder layer; and a semiconductor chip disposed on the base member through the solder layer. The chip has an in-plane temperature distribution when the chip is operated. The chip has an allowable maximum temperature as a temperature limit of operation. The in-plane...

20060087044 - Electronic component, and system carrier and panel for producing an electronic component: An electronic component has a first semiconductor chip and a second semiconductor chip that is arranged on a plastic compound in which the first semiconductor chip is embedded. The semiconductor chips are connected to one another by rewiring layers and vias which extend between the rewiring layers, the vias being...

20060087045 - Substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same: A disclosed substrate having a built-in semiconductor chip includes the built-in semiconductor chip, a resin member having the built-in semiconductor chip contained therein and external connection terminals. The resin member contains a resin and 60 to 90% by weight of spherical filler....

20060081830 - Air gaps between conductive lines for reduced rc delay of integrated circuits: Methods of forming air gaps or porous dielectric materials between interconnects of integrated circuits and structures thereof. Air gaps or highly porous dielectric material having a dielectric constant of close to or equal to 1.0 are formed in a first region but not a second region of an interconnect layer....

20060081831 - Light emitting device using nitride semiconductor and fabrication method of the same: A nitride based 3-5 group compound semiconductor light emitting device comprising: a substrate; a buffer layer formed above the substrate; a first In-doped GaN layer formed above the buffer layer; an InxGa1−xN/InyGa1−yN super lattice structure layer formed above the first In-doped GaN layer; a first electrode contact layer formed above...

20060081832 - Light-emitting element with porous light-emitting layers: The invention relates to a light-emitting element with porous light-emitting layers. The light-emitting element comprises: a substrate, a first conductive cladding layer, a second conductive cladding layer and at least one porous light-emitting layer. The porous light-emitting layer is formed between the first conductive cladding layer and the second conductive...

20060081833 - Package structure of light-emitting device: A package structure of light-emitting device comprises a substrate. Two lines are formed on the substrate. An insulating layer is formed between two lines. A plurality of light-emitting sources are formed on the substrate for generating the light. Each light-emitting source has a positive electrode and a negative electrode. A...

20060081834 - Semiconductor luminescent device and manufacturing method thereof: A first principal plane faces a second principal plane of a p-type Ga N compound semiconductor that is in contact with an MQW luminescent layer. On the surface of the first principal plane, a first region made up of the p-type Ga N compound semiconductor including at least Ni is...

20060081835 - Scaffold-organized clusters and electronic devices made using such clusters: A method for forming arrays of metal, alloy, semiconductor or magnetic nanoparticles is described. An embodiment of the method comprises placing a scaffold on a substrate, the scaffold comprising, for example, polynucleotides and/or polypeptides, and coupling the nanoparticles to the scaffold. Methods of producing arrays in predetermined patterns and electronic...

20060081836 - Semiconductor device and method of manufacturing the same: In a field effect semiconductor device for high frequency power amplification, it is difficult to achieve size reduction and increased efficiency simultaneously while ensuring voltage withstanding. A further improvement in efficiency is attained by using a strained Si channel for LDMOS at an output stage for high frequency power amplification....

20060081837 - Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present...

20060081838 - Functional molecular element and functional molecular device: A functional molecular element whose functions can be controlled by an electric field based on a new principle. A Lewis base molecule (14) with positive permittivity anisotropy or a dipole moment in the major axis direction of the molecule is disposed, via a metal ion (3) that can act as...

20060081841 - Gelable composition: A composition including a polymer and a liquid, wherein the polymer exhibits lower solubility in the liquid at room temperature but exhibits greater solubility in the liquid at an elevated temperature, wherein the composition gels when the elevated temperature is lowered to a first lower temperature without agitation, wherein the...

20060081839 - Oligothiophene-arylene derivatives and organic thin film transistors using the same: An oligothiophene-arylene derivative wherein an arylene having n-type semiconductor characteristics is introduced into an oligothiophene having p-type semiconductor characteristics, thereby simultaneously exhibiting both p-type and n-type semiconductor characteristics. Further, an organic thin film transistor using the oligothiophene-arylene derivative....

20060081840 - Organic electronic device and method for producing the same: A main object of the present invention is to provide an organic electronic device which has a high charge injection property by lowering a charge injection barrier between an electrode and an organic layer, and a layer having a charge injection function of which can be formed by a wet...

20060081842 - Monitor pattern of semiconductor device and method of manufacturing semiconductor device: A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to...

20060081843 - Semiconductor article and method for manufacturing the same: Method for manufacturing a semiconductor article, in that a silicide layer is applied, an impurity which acts as a dopant in a semiconductor region is introduced into the silicide layer, the silicide layer being located at least partially beneath the monocrystalline semiconductor region adjacent to the silicide layer, so that...

20060081844 - Display device: The invention provides a technique to manufacture a display device with high image quality and reliability at low cost with high yield. According to the invention, a spacer is provided over a pixel electrode layer in a pixel region. Moreover, a surface of an insulating layer which functions as a...

20060081845 - Organic electro-luminescence display device and method of fabricating the same: The present invention relates to an organic electro-luminescence display device and a method of fabricating the same capable of improving an emission efficiency and of reducing a deterioration of picture quality. An organic electro-luminescence display device, including a display area and a non-display area, according to the present invention includes:...

20060081846 - Semiconductor device and method of manufacturing the same: The present invention improves the aperture ratio of a pixel of a reflection-type display device or a reflection type display device without increasing the number of masks and without using a blackmask. A pixel electrode (167) is arranged so as to partially overlap a source wiring (137) for shielding the...

20060081847 - Methods for fabricating a wafer structure having a strained silicon utility layer: Methods for fabricating a wafer structure having a strained silicon utility layer are described. In an embodiment, the method includes providing a prototype wafer having at least a support substrate and a strained silicon model layer upon the support substrate, and then providing a relaxed silicon-germanium layer on the strained...

20060081850 - Display device and driving method thereof: A display device that employs fewer IC chips and lends itself to cost-efficient manufacturing is presented. The device includes: a plurality of pixel rows including first and second pixels alternately arranged; a plurality of first and second gate lines disposed above and below the pixel rows and applying first and...

20060081853 - Display panel and method of manufacturing the same: A display panel and a method for manufacturing the display device having the display pixel, includes forming a first substrate with pixel areas and a second substrate facing the first substrate. The second substrate includes a color filter layer having a first region and a second region that is arranged...

20060081854 - Organic electro luminescence device and fabrication method thereof: An organic electro luminescence device and a fabrication method thereof are provided. An array element is formed on a first substrate and an electro luminescent diode is formed on a second substrate. The array element and the electro luminescent diode are electrically connected together by a spacer. A separator divides...

20060081849 - Organic thin film transistor array and manufacturing method thereof: An organic thin film transistor array panel is provided, which includes: a substrate; a data line formed on the substrate and including a source electrode; a drain electrode formed on the substrate and separated from the data line; an organic semiconductor disposed on the source electrode and the drain electrode;...

20060081852 - Semiconductor device and manufacturing method thereof: To obtain a semiconductor device containing TFTs of different, suitable properties as display pixel TFTs and high-voltage, driver-circuit TFTs, the semiconductor device of the present invention includes: first and second islands-shaped polycrystalline silicon (p-Si) layers provided above an insulating substrate and having relatively large grain sizes; a third islands-shaped p-Si...

20060081851 - Semiconductor memory device: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal...

20060081848 - Solid state imaging device and method for producing the same: On a light shielding film 7, an anti-oxidation layer 9 covering at least the light shielding film 7 is formed. The anti-oxidation layer 9 is formed under a condition which does not oxidize a surface of the light shielding film 7. The anti-oxidation layer 9 is formed of a high...

20060081855 - Thin film transistor and method of forming thin film transistor: The thin film transistor has a non-transparent structure besides and insulated with the gate. Hence, the light transmitted from the substrate is blocked and the light current induced in the thin film transistor is negligible. The method uses a mask with a slit pattern to form a non-uniform photoresist. Hence,...

20060081856 - Novel wide bandgap material and method of making: A wide bandgap semiconductor material comprised of Silicon carbide containing a predetermined portion of germanium....

20060081857 - Light emitting device having circuit protection unit: A light emitting device having a circuit protection unit is provided. The circuit protection unit has a low-resistance layer and a potential barrier layer, wherein a barrier potential exists at the interface between the low-resistance layer and the potential barrier layer. The circuit protection unit is electrically connected with the...

20060081858 - Light emitting device with omnidirectional reflectors: A light emitting device includes a semiconductor structure having lateral side faces, and including a light-generating layer, and two omnidirectional reflectors disposed respectively at two sides of the light-generating layer. Each of the omnidirectional reflectors exhibits a periodic variation indielectric constant in such a manner so as to introduce an...

20060081859 - Light emitting semiconductor bonding structure and method of manufacturing the same: Disclosed is a light emitting semiconductor bonding structure and its manufacturing method. The light emitting semiconductor bonding structure includes a structure formed by bonding a substrate onto a light emitting semiconductor. The substrate is a structure containing electric circuits. The ohmic contact N electrode layer and P electrode layer are...

20060081861 - Gallium-nitride based multi-quantum well light-emitting diode n-type contact layer structure: A structure for the n-type contact layer in the GaN-based MQW LEDs is provided. Instead of using Si-doped GaN as commonly found in conventional GaN-based MQW LEDs, the n-type contact layer provided by the present invention achieves high doping density (>1×1019 cm−3) and low resistivity through a superlattice structure combining...

20060081860 - Group iii nitride semiconductor light-emitting element and method of manufacturing the same: A Group III nitride semiconductor light-emitting element includes a crack-preventing layer 15 of n-type GaN provided between a n-type contact layer 4A and a n-type clad layer 5A, wherein the crack-preventing layer 15 has a dopant concentration lower than that of the n-type contact layer 4A....

20060081862 - Device and method for emitting output light using quantum dots and non-quantum fluorescent material: A device and method for emitting output light utilizes both quantum dots and non-quantum fluorescent material to convert at least some of the original light emitted from a light source of the device to longer wavelength light to change the color characteristics of the output light. The device can be...

20060081863 - Dipolar side-emitting led lens and led module incorporating the same: The present invention relates to a dipolar LED and a dipolar LED module incorporating the same, in which an upper hemisphere-shaped base houses an LED chip therein and adapted to radiate light from the LED chip to the outside, and a pair of reflecting surfaces placed at opposed top portions...

20060081864 - Encapsulating composition for led: An organopolysiloxane composition which cures to a resinous solid has high strength, transparency, and resistance to thermal- and photo-degradation, and is especially suited for encapsulating LEDs. The composition contains specific addition curable organopolysiloxanes having D, T, and Q units, and a proportion of silicon-bonded aromatic groups....

20060081865 - Light-emitting diode: A light-emitting diode capable of making its light emission more uniform without too high a concentration current and of improving the efficiency of outgoing light and its life. In the light-emitting diode, the n-side electrode has an n-side connecting portion and an n-side extending portion, which extends in the longitudinal...

20060081869 - Flip-chip electrode light-emitting element formed by multilayer coatings: A flip-chip electrode light-emitting element formed by multilayer coatings where a translucent conducting layer and a highly reflective metal layer acts as flip-chip electrode for enhancing the LED luminous efficiency. The flip-chip electrode light-emitting element includes a translucent substrate, a semiconductor die structure attached on the translucent substrate and made...

20060081870 - Method of forming a lamination film pattern and improved lamination film pattern: In a method of forming an electrically conductive lamination pattern, an insulating film is formed on a surface of a chromium-containing bottom layer, before an aluminum-containing top layer is formed over the insulating film, so that the insulating film separates the aluminum-containing top layer from the chromium-containing bottom layer. A...

20060081866 - Optical semiconductor apparatus: An optical semiconductor apparatus has an eyelet having a through hole, an insulating member provided in the through hole, a semiconductor optical element, and a submount on which the semiconductor optical element is mounted. The insulating member supports a plurality of lead terminals. The submount has a first portion supported...

20060081867 - Reflective electrode and compound semiconductor light emitting device including the same: Provided are a reflective electrode and a compound semiconductor light emitting device having the reflective electrode, such as LED or LD is provided. The reflective electrode formed on a p-type compound semiconductor layer of a compound semiconductor light emitting device, comprising a first electrode layer formed one of a Ag...

20060081868 - Semiconductor device: A semiconductor device with high reliability, low voltage, and high luminance is provided by preventing detachment of an electrode by way of obtaining good adhesion of the electrode, even in cases where a face-down mounting of a semiconductor laser is performed, and further, an insulating film and a protective film...

20060081871 - Multiple light-emitting diode arrangement: A radiation-emitting semiconductor component comprising a plurality of semiconductor bodies (10, 20, 30) which each have an active zone (11, 21, 31) and during operation emit light having in each case a different central wavelength (λ10, λ20, λ30) and an assigned spectral bandwidth (Δλ10, Δλ20, Δλ30), so that the mixing...

20060081872 - Compound semiconductor, method for producing the same, semiconductor light-emitting device and method for fabricating the same: An inventive method includes the steps of: growing a first p-type semiconductor layer of a compound semiconductor containing phosphorus on a substrate; and growing a second p-type semiconductor layer of a compound semiconductor containing arsenic on the first p-type semiconductor layer. While the first p-type semiconductor layer is grown, magnesium...

20060081873 - High temperature light-emitting diodes: A heterostructure semiconductor device capable of emitting electromagnetic radiation and having a junction with opposite conductivity type materials on either side thereof supported on a substrate with an active layer therebetween comprising zinc oxide and having a band gap energy that is less than that of either of the opposite...

20060081874 - Starved source diffusion for avalanche photodiode: Starved source diffusion methods for forming avalanche photodiodes (APDs) are provided for controlling the edge effect. The edge effect is controlled by reducing edge gain near the edges of an APD active region. This is accomplished by creating a sloped diffusion front near the edges of the active region. The...

20060081875 - Transistor with a strained region and method of manufacture: A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the...

20060081876 - Process for fabricating a heterostructure-channel insulated-gate field-effect transistor, and the corresponding transistor: The insulated-gate field-effect transistor includes a substrate surmounted by a layer of silicon-germanium alloy, the ratio of the germanium concentration to the silicon concentration of which increases towards the surface of the substrate. The transistor is formed on the active zone in the silicon-germanium alloy layer and lies between two...

20060081877 - Semiconductor epitaxial wafer and field effect rtansistor: A semiconductor epitaxial wafer has, on a sapphire substrate, an AlN buffer layer formed of undoped AlN, a GaN buffer layer formed of 2 μm-thick undoped GaN, and measurement electrodes formed thereon....

20060081879 - Semiconductor device and a manufacturing method thereof, and semiconductor module: The present invention provides a semiconductor device which comprises active components, passive components, wiring lines and electrodes and are satisfactory in terms of mechanical strength, miniaturization and thermal stability. In the semiconductor device, openings are formed just below active components. These openings are filled with conductor layers. Conductor layers are...

20060081878 - Transistor circuit: The transistor circuit 1 includes a plurality of transistor cells 10 each having a transistor 11, a base ballast resistor 12, a capacitor 13, and an inductor 14. The transistors 11 have the respective collectors commonly connected to a collector terminal 1c of the transistor circuit 1 and the respective...

20060081880 - Organic field effect transistor and method for producing the same: wherein R1 and R3 each denotes a group for forming an aromatic ring or a heteroaromatic ring which may have a substituent, together with a group to be bonded to R1 or R3; R2 and R4 each denotes a hydrogen atom, an alkyl group, an alkoxy group, an ester group...

20060081881 - Circuit wiring laying-out apparatus, method of laying-out a circuit, signal-bearing medium embodying a program of laying-out wiring, wiring layout, and method of using a wiring layout: A circuit wiring laying-out apparatus includes a wiring device that moves automatically a wiring in a first region to a second region, to make uniform a number of wirings in the circuit....

20060081882 - High performance field effect transistors comprising carbon nanotubes fabricated using solution based processing: The present invention is directed toward field effect transistors (FETs) and thin film transistors (TFTs) comprising carbon nanotubes (CNTs) and to methods of making such devices using solution-based processing techniques, wherein the CNTs within such devices have been fractionated so as to be concentrated in semiconducting CNTs. Additionally, the relatively...

20060081884 - Semiconductor constructions: The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for example, DRAM devices. The invention can be utilized for forming 4F2 DRAM devices....

20060081883 - Three-dimensional memory system-on-a-chip: The present invention provides a three-dimensional memory (3D-M) system-on-a-chip (SoC). It takes full advantage of the difference in the number of interconnect levels between the embedded processor (eP) and embedded memory (eM) in an SoC chip. The un-used interconnect space on top of the eM block is converted into 3D-M....

20060081885 - Field effect transistor with electroplated metal gate: Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate...

20060081886 - Method, system and apparatus for gating configurations and improved contacts in nanowire-based electronic devices: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and...

20060081887 - Solid state image sensor devices having non-planar transistors: CMOS image sensor devices are provided, wherein active pixel sensors are designed with non-planar transistors having vertical gate electrodes and channels, which minimize the effects of image lag and dark current....

20060081888 - Solid-state image sensor: A solid-state image sensor capable of suppressing mixture of charge between adjacent charge transfer paths (charge transfer regions), and suppressing reduction of a transfer efficiency of charge is provided. In the solid-state image sensor, the charge transfer region includes a first region with a first channel width, and a second...

20060081889 - Device and method for managing radiation: A device and method for managing terahertz and/or microwave radiation are provided. The device can comprise one or more field effect transistors (FETs) that each include at least one channel contact to a central region of the device channel of the FET. The frequency of the radiation managed by the...

20060081890 - Cmos image sensor and method of manufacturing the same: An image sensor includes a substrate with an epitaxial layer deposited thereon, a plurality of photodiodes buried in the epitaxial layer, and a plurality of field oxide films interposed between the photodiodes for insulating the photodiodes. Each of the field oxide films includes a trench formed on the epitaxial layer,...

20060081891 - Nonvolatile semiconductor memory capable of storing data of two bits or more per cell: A nonvolatile semiconductor memory includes a gate insulating layer, a control gate layer, a first silicide layer, charge accumulating layers, memory gate layers and second silicide layers. The gate insulating layer is formed on a first region of a semiconductor substrate. The control gate layer is formed on the gate...

20060081892 - Mos capacitor type semiconductor device and crystal oscillation device using the same: A compact semiconductor device forming a capacitive element for high frequencies that allows good capacitance change to be achieved is provided. AMOS capacitor type semiconductor device includes a gate electrode formed on a surface of a substrate through a gate insulating film, source/drain regions provided to have the gate electrode...

20060081893 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises an n-type MIS transistor comprising a first gate insulating film and a first gate electrode including an MSix film formed on the first gate insulating film, where M represents a metal element selected from tungsten and molybdenum and x is greater than 1, i.e., x>1; and...

20060081894 - Recessed drain extensions in transistor device: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms...

20060081896 - Semiconductor device and method for forming the same: The present invention disclosed herein is a semiconductor device and a method for forming the same. The semiconductor device includes a first semiconductor pattern defining an active region, second semiconductor patterns placed on the first semiconductor pattern apart from each other, an insulated gate electrode spaced apart from the second...

20060081895 - Semiconductor device having fin transistor and planar transistor and associated methods of manufacture: Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transistor is formed....

20060081897 - Gan-based semiconductor integrated circuit: A GaN-based semiconductor integrated circuit comprising a plurality of types of GaN-based semiconductor devices integrated on a single substrate, and one of the plurality of types of GaN-based semiconductor devices includes a Schottky diode. The Schottky diode includes a GaN-based semiconductor layer, a first anode and a second anode, wherein...

20060081899 - Detection arrangement for modular use in a combined transmission/emission tomography unit: A detection arrangement is for modular use for a combined transmission/emission tomography unit, for measuring transmission x-radiation and emission γ-radiation inside a detector. The detection arrangement includes at least three absorption layers of different thickness, arranged one above another in the radiation direction, for detecting absorption events in which case...

20060081898 - Enhanced color image sensor device and method of making the same: A semiconductor device including a substrate having a plurality of image sensing elements formed therein, a plurality of spaced apart color filters overlying the substrate and a light blocking material interposed between adjacent spaced apart color filters....

20060081900 - Pixel cell having a grated interface: A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with said silicon substrate, and a method of fabricating the pixel cell having a grated interface....

20060081902 - Ferroelectric memory and method of manufacturing the same: A method of manufacturing a ferroelectric memory includes: (a) stacking a lower electrode layer, a ferroelectric layer, and an upper electrode layer on a base in that order to form a ferroelectric laminate; (b) patterning the ferroelectric laminate to form a ferroelectric capacitor; (c) forming a first barrier film which...

20060081901 - Ferroelectric memory, multivalent data recording method and multivalent data reading method: A ferroelectric memory device includes a gate electrode formed on a semiconductor body via a ferroelectric film, first and second diffusion regions being formed in the semiconductor body at respective sides of a channel region, wherein the ferroelectric film comprises a first region located in the vicinity of the first...

20060081903 - Semiconductor device and method of fabricating the same: An n channel type power MOS field effect transistor has silica particles buried in a bottom portion of a trench and a gate electrode buried in another portion of the trench. The gate electrode is in contact with the silica particles. A gap of the silica particles is not filled...

20060081904 - On-chip capacitor: An on-chip capacitor having a plurality of capacitor layers Each capacitor layer comprising a pair of frames, such that a first frame of the pair is electrically connected to first frames on each other capacitor layer and a second frame of the pair is electrically connected to second frames on...

20060081905 - Dielectric multilayer of microelectronic device and method of fabricating the same: A dielectric multilayer suitable for improving a performance of a microelectronic device and a method of fabricating the dielectric multilayer are provided. The dielectric multilayer of the microelectronic device comprises a composite layer which is formed of oxides of two or more different elements and in which a laminar structure...

20060081907 - Nonvolatile semiconductor memory device having grooves isolating the floating electrodes of memory cells and method of manufacturing the nonvolatile semiconductor memory device: A plurality of nonvolatile memory elements formed on element regions respectively isolated by element isolation regions on a main surface of a first conductive type semiconductor substrate, the nonvolatile semiconductor memory elements comprising a gate insulating film formed on the main surface of the semiconductor substrate, a plurality of floating...

20060081906 - Semiconductor device and method of manufacturing the same: Disclosed herein is a semiconductor device and method of manufacturing the same. A step between a memory cell formed in a cell region and a transistor formed in a peripheral circuit region is minimized, and the height of a gate in the memory cell is minimized. Accordingly, subsequent processes are...

20060081908 - Flash gate stack notch to improve coupling ratio: A semiconductor flash memory device with increased gate coupling ratio and a method of preparing this flash memory device. The semiconductor flash memory device includes a notched floating polysilicon gate. The notches are at the interface between the floating polysilicon layer and the tunneling dielectric layer. The notches reduce the...

20060081911 - Method of forming a non-volatile electron storage memory and the resulting device: The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate...

20060081910 - Non-volatile electrically alterable memory cell for storing multiple data and an array thereof: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well....

20060081909 - Semiconductor device and manufacturing method therefor: A semiconductor device comprises a semiconductor substrate, diffusion layer regions formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, gate electrodes formed on the gate insulating film, a silicon nitride film covering the gate electrodes, an interlayer insulating film formed over the semiconductor substrate so...

20060081912 - Electronic memory component with protection against light attack: In order to further develop an electronic memory component (100 or 100′), comprising at least one memory cell matrix (10) which is embedded in and/or let into at least one doped receiving substrate (20), in such a way that a light incidence taking the form of a so-called light attack...

20060081914 - Semiconductor device and manufacturing method thereof: A plurality of first wiring structures of a first width are arranged periodically at first intervals. A second wiring structure is formed next to one of the first wiring structures. The lower part of the second wiring structure has a second width substantially equal to the sum of n times...

20060081913 - Semiconductor memory devices including electrode contact structures having reduced contact resistance and methods of fabricating the same: A semiconductor memory device includes a semiconductor substrate having an active region therein, an insulating layer on the substrate, and a lower electrode conductive pad extending through the insulating layer. The lower electrode conductive pad electrically contacts the active region at a lower surface of the lower electrode conductive pad....

20060081916 - Methods of forming gate structures for semiconductor devices and related structures: Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the...

20060081915 - Nonvolatile semiconductor memory device and method for fabricating the same: The nonvolatile semiconductor memory device comprises a channel region formed in a semiconductor substrate, a gate electrode formed over the channel region with a charge retaining insulating film interposed therebetween, a first pair of source/drain regions arranged in a first direction with the channel region formed therebetween, and a second...

20060081917 - Method for forming a hard mask for gate electrode patterning and corresponding device: A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch...

20060081921 - Integrated circuit device having non-linear active area pillars: An integrated circuit device having non-linear active area pillars. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the...

20060081919 - Semiconductor device: A semiconductor device comprising: a first-conductivity-type base layer; a second-conductivity-type emitter layer formed on a first main surface of said first-conductivity-type base layer; a collector electrode formed in contact with a surface of said second-conductivity-type emitter layer; a second-conductivity-type base layer formed on a second main surface of said first-conductivity-type...

20060081920 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: a semiconductor substrate of the first-type; a semiconductor region of the first-type formed on the substrate; a gate electrode a part of which is present within a trench selectively formed in part of the semiconductor region, and an extended top-end to have a wide width via...

20060081918 - Trench power moset and method for fabricating the same: A method for fabricating a trench power MOSFET, comprising an epitaxial layer and a mask layer formed over a substrate, a trench formed in the epitaxial layer and the mask layer, a gate oxide layer formed on the trench, then the mask layer removed, a body well region formed in...

20060081922 - Method of controlling emissions from a diesel cycle internal combustion engine with perovskite-type metal oxide compounds: Methods of controlling emissions from a diesel engine are provided. The method includes contacting the emissions with a perovskite-type catalyst consisting essentially of a metal oxide composition represented by the general formula Aa-xBxMOb, in which A is a mixture originally in the form of single phase mixed lanthanides collected from...

20060081923 - Semiconductor device and fabrication method suitable therefor: A semiconductor device according to the invention has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially...

20060081924 - Semiconductor device and manufacturing method of the same: A semiconductor device is disclosed that is capable of improving the drain breakdown voltage during operation. The semiconductor device includes a first drain region that is arranged to extend from the vicinity of an end portion of the gate electrode at the drain electrode side in a direction toward the...

20060081926 - Method of forming shallow doped junctions having a variable profile gradation of dopants: Disclosed is an electrical device having, and a process for forming, a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed....

20060081927 - Method of manufacturing an esd protection device with the same mask for both ldd and esd implantation: A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer...

20060081925 - Semiconductor device with asymmetric pocket implants: A semiconductor device (1) has a source (2) a gate (3) and a drain (4), a single deep-pocket ion implant (8) in a source-drain depletion region, and a single shallow-pocket ion implant (9) in the source-drain depletion region....

20060081928 - Isolation spacer for thin soi devices: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa....

20060081932 - Semiconductor channel on insulator structure: A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose...

20060081931 - Semiconductor device and method of manufacturing the same: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate...

20060081930 - Semiconductor device, manufacturing method thereof, and memory circuit: The present invention provides a semiconductor device capable of suppressing a body floating effect, and a manufacturing method thereof. A semiconductor device having an SOI structure includes a silicon substrate, a buried insulating layer formed on the silicon substrate, and a semiconductor layer formed on the buried insulating layer. The...

20060081929 - Silicon-on-insulator substrate, fabricating method thereof, and method for fabricating floating structure using the same: A silicon-on-insulator (SOI) substrate including laminated layers of a substrate, an oxide layer, and a silicon layer in order. The oxide layer has an electrifying hole fluidly connected with the substrate and the electrifying hole is filled with a part of the silicon layer. A method for fabricating the floating...

20060081933 - Electrostatic discharge protection device with complementary dual drain implant: Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher...

20060081934 - Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same: A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then...

20060081935 - Esd protection devices with scr structures for semiconductor integrated circuits: To control the uneven distribution of current density and reduce the area of an ESD protection circuit in an SCR-type ESD protection device. An N-type well 11, and P-type wells 12a and 12b disposed oppositely and adjacent to the N-type well 11, with the N-type well 11 interposed between them,...

20060081936 - Semiconductor device for low power operation: A semiconductor device for low power operation includes a channel region having a channel length greater than a standard minimum channel length. The voltage supply of the device is less than the threshold voltage of the device. A gate terminal of the device may have a raised height relative to...

20060081937 - Laterally diffused metal oxide semiconductor device and method of forming the same: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region...

20060081938 - Integrated circuit tolerant to the locking phenomenon: Integrated circuit comprising doped zones (3 to 8) formed in a substrate (1, 2), forming a parasite thyristor structure with two parasite bipolar transistors (T1, T2), the integrated circuit comprising two metallisations (16, 19) interconnecting each of the two corresponding doped zones (4, 5; 6, 7) of the integrated circuit,...

20060081940 - Semiconductor device: A semiconductor device capable of integrally controlling thresholds of gate electrodes of transistors present in a region of one-conductivity-type and transistors present in a region of an reverse-conductivity-type while suppressing noise propagation is provided. A digital circuit region 123 and an analog circuit region 121 are provided on a P—Si...

20060081939 - Semiconductor device having misfet using high dielectric constant gate insulation film and method for fabricating the same: A semiconductor device having a metal insulator semiconductor field effect transistor (MISFET) with increased electron mobility and enhanced hole mobility is disclosed. In this semiconductor device, a p-type well layer and an n-type well layer are formed in a surface portion of a silicon substrate. A nitrogen-nondoped n-channel interface layer...

20060081941 - Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus: The present invention provides a semiconductor storage device having: a first conductivity type region formed in a semiconductor layer; a second conductivity type region formed in the semiconductor layer in contact with the first conductivity type region; a memory functional element disposed on the semiconductor layer across the boundary of...

20060081942 - Semiconductor device and manufacturing method therefor: A semiconductor device, comprising: a conductive layer which includes a metal and is formed on a silicon substrate via an insulation layer, the insulation layer being formed by implanting an impurity ion and having a stress changing region with stress different from that of the other region....

20060081943 - Semiconductor device and method for the preparation thereof: A semiconductor device in which penetration of a metal silicide film in a source/drain layer as well as generation of the leakage current is suppressed. A semiconductor device includes a gate 6, formed only of a metal silicide, and a metal silicide layer 10, formed on a source/drain layer 9....

20060081945 - Method for making an array of multi-bit rom cells with each cell having bi-directional read: A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the...

20060081944 - Scrambling method to reduce wordline coupling noise: A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). Each row has a first part (1102) and a second part (1108). A first conductor (750)...

20060081946 - Method of manufacturing a thin film transistor device: In a case of a liquid crystal display apparatus, a gate insulating film of a TFT driven at a low voltage (3.3 V or 5 V) is constituted by one insulating film, and a thickness thereof is set to, for example, 30 nm. This TFT has a structure in which...

20060081947 - Field effect transistor and production method thereof: A field effect transistor having a gate, a source, and a drain formed from metallic materials is disclosed that is able to supply a high driving current. In the field effect transistor, a source region, a drain region and a gate electrode are formed from silicide or other metallic materials....

20060081948 - Transistors with multilayered dielectric films and methods of manufacturing such transistors: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a...

20060081949 - Semiconductor device and process for producing the same: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in...

20060081951 - Micro-electro-mechanical system (mems) package having side double-sealing member and method of manufacturing the same: A micro-electro-mechanical system (MEMS) package having a side double-sealing member and method of manufacturing the MEMS package is disclosed. The MEMS package is formed by forming a metal layer on a base substrate by patterning so that the metal layer surrounds an MEMS element provided on the base substrate, joining...

20060081950 - Molehole embedded 3-d crossbar architecture used in electrochemical molecular memory device: This invention provides a new design and fabrication for a three-dimensional crossbar architecture embedding a sub-micron or nanometer sized hole (called a molehole) in each cross-region. Each molehole is an electrochemical cell consisting of two or more sectional surfaces separated by a non-conductor (e.g., a dialectric layer and solid electrolyte)....

20060081952 - Inflected magnetoresistive structures, memory cells having inflected magnetoresistive structures, and fabrication methods: Disclosed herein is a magnetoresistive structure having a non-planar form. Embodiments of the present MR structure includes those having at least one inflection between a first portion of the MR structure that is somewhat vertical relative to a substrate and a second portion of the MR structure that is somewhat...

20060081954 - Magnetic particle flow detector: A ferromagnetic thin-film based magnetic field detection system having a substrate supporting a magnetic field sensor in a channel with a first electrical conductor supported on the substrate positioned at least in part along the channel gap and in direct contact with at least some surface of the magnetic field...

20060081953 - Spin transfer magnetic element with free layers having high perpendicular anisotropy and in-plane equilibrium magnetization: A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a...

20060081955 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same improve photosensitivity by imparting a color filter layer with the function of a microlens layer. The CMOS image sensor includes a semiconductor substrate; a plurality of photo-sensing elements formed in the semiconductor substrate; and a color filter layer comprised...

20060081956 - Solid-state image sensor: A solid-state image sensor capable of suppressing deterioration of a transfer efficiency of electrons is provided. The solid-state image sensor comprises a first conductive type first impurity region that can store electrons and holes; a second conductive type second impurity region that is formed so as to have a region...

20060081957 - Solid-state imaging device: The present invention provides a solid-state imaging device having an array of unit pixels, each unit pixel including a photoelectric conversion element and an amplifier transistor for amplifying a signal corresponding to charge obtained by photoelectric conversion through the photoelectric conversion element and outputting the resultant signal. The amplifier transistor...

20060081958 - Semiconductor device and method of providing regions of low substrate capacitance: A semiconductor device (2) includes a semiconductor substrate (12) having a surface (13) formed with a first recessed region (20). A first dielectric material (60) is deposited in the first recessed region and formed with a second recessed region (76), and a second dielectric material (100) is grown over the...

20060081959 - Poly-silicon stringer fuse: A polysilicon silicide stringer fuse is constructed having a narrow width by using an overlay tolerance of the photo stepper tool instead of the minimum critical dimension tolerance of the stepper tool. In an example embodiment, a fuse (200) for integration within a semiconductor comprises depositing an insulating layer (205)...

20060081960 - Integrated capacitor on packaging substrate: An integrated capacitor on a packaging substrate. The integrated capacitor comprises a conductor plane, a first dielectric layer and a signal transmission layer. The conductor plane has an extrusion layer of a first thickness. The first extrusion layer and the conductor plane are made of the same material. The first...

20060081961 - Variable resistance device and a semiconductor apparatus, including a variable resistance layer made of a material with a perovskite structure: The present invention offers a variable resistance device and a semiconductor apparatus that have component parts less subject to damage and thereby ensure stable quality at a high yield, even if the manufacturing processes include operations in a deoxidizing atmosphere or an oxidizing atmosphere. The variable resistance device of the...

20060081962 - Variable resistance device made of a material which has an electric resistance value changing in accordance with an applied electric field and maintains the electric resistance value after being changed in a nonvolatile manner, and a semiconductor apparat: The variable resistance device of the present invention comprises a variable resistance layer. The variable resistance layer is made of a material which has an electric resistance changing in accordance with an applied electric field and maintains the electric resistance after being changed in a nonvolatile manner. Provided for the...

20060081963 - Bipolar transistor with enhanced base transport: A bipolar transistor includes a base layer design and a method for fabricating such a bipolar transistor that employ a built-in accelerating field focused on a base region adjacent to a collector, where minority carrier transport is otherwise retarded. The accelerating field of the base layer includes on average, a...

20060081964 - Semiconductor device: A semiconductor device (1, 20-80) has an emitter terminal (2), a collector terminal (3) and also a semiconductor body (4) provided between emitter terminal (2) and collector terminal (3). An emitter zone (5, 70) is formed in the semiconductor body (4), said emitter zone at least partially adjoining the emitter...

20060081966 - Chip-scale packages: Improved chip-scale packages wherein semiconductor die side surfaces are free of the material defects associated with prior art chip-scale package formation. In one embodiment, chip-scale package includes a semiconductor die includes an active surface, an opposing passive surface, and a plurality of etched side surfaces extending from the active surface...

20060081965 - Plasma treatment of an etch stop layer: A method of manufacturing an etch stop layer 18, 20, 21 on a semiconductor wafer 2 and the etch stop layer 18, 20, 21 produced by the method. The method includes depositing a dielectric layer 18, 20, 21 and applying a plasma treatment to the semiconductor wafer 2. Also, an...

20060081967 - Multichip leadframe package: A multichip package has a leadframe including peripheral leads arranged about a centrally situated die paddle. A first (“upper”) die is attached to a first (“top”) side of the leadframe die paddle, which can be generally flat. The second (“bottom”) side of the leadframe is partially-cut away (such as by...

20060081969 - Package structure module of bump posited type lead frame: A package structure that uses a bump posited type lead frame is disclosed. The package structure uses a lead frame having holes thereon for accommodating conductive bumps of a chip or a positioning film having openings thereon for accommodating conductive bumps of a chip or both to avoid the flow...

20060081968 - Semiconductor package: The present invention discloses a semiconductor package comprising a substrate having a plurality of substrate units, a plurality of semiconductor chips respectively disposed on the substrate units, and a plurality of conductive guard lines each disposed between two adjacent substrate units. Each substrate unit is provided with a plurality of...

20060081970 - Memory card module with an inlay design: A memory card module with an inlay design includes a substrate having an upper surface on which an upper cavity is formed, and a lower surface on which at least a lower cavity corresponding to the upper cavity of the upper surface is formed, a through hole is penetrated from...

20060081972 - Fine pitch grid array type semiconductor device: A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality...

20060081971 - Signal transfer methods for integrated circuits: The present invention discloses novel methods to transfer data between a plurality of integrated circuit blocks on a semiconductor wafer. Each individual circuit blocks contains internal circuits to control data transfer to nearby circuit blocks. Long distance signal transfer is achieved by a series of short distance data transfers. Such...

20060081973 - Integrated circuit package having inductance loop formed from same-pin-to-same-bonding-pad structure: An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of...

20060081974 - Electronic part mounting apparatus and method: An electronic part mounting apparatus includes a chamber for cleaning a substrate and an electronic part by plasma, amounting mechanism for mounting the electronic part on the electronic part, and a conveying robot for conveying the substrate and the electronic part from the chamber to the mounting mechanism. After plasma...

20060081976 - Fabrication of semiconductor dies with micro-pins and structures produced therewith: A method for forming a semiconductor die, comprising forming a trench in a surface of the die; filing the trench with a sacrificial material; patterning the die to form a series of channels extending substantially perpendicularly to the trench; depositing a conductive material in the channels; removing at least a...

20060081975 - Substrate supporting frame: A substrate supporting frame, a substrate supporting frame assembly including the frame, a method of framing a substrate using the frame, a method of fabricating a donor substrate using the substrate supporting frame assembly, and a method of fabricating an Organic Light Emitting Display (OLED) using the donor substrate each...

20060081977 - Ceramic multilayer substrate: A ceramic multilayer substrate has a ceramic laminate including a plurality of ceramic layers laminated, having a first main surface, and including internal circuit elements disposed in the inside, a resin layer having a bonding surface in contact with the first main surface of the ceramic laminate and a mounting...

20060081978 - Heat dissipating package structure and method for fabricating the same: A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; a heat spreader having a first surface, an opposed second surface and a hollow structure, the second surface of the heat spreader being mounted on the chip, wherein the chip...

20060081979 - Thermal properties for microelectronic devices: A microelectronic device is made of a semiconductor substrate, a heat generating component in a layer thereof, and a body within the remaining semiconductor substrate. The body is made of materials which have a high thermal inertia and/or thermal conductivity. When high thermal conductivity materials are used, the body acts...

20060081980 - Integrated circuit package employing a heat-spreader member: An integrated circuit package is proposed in which a laminar substrate 41 is provided with an aperture 43. A heat-spreader member 1 is mounted to cover this aperture 43, and contains a cavity 3 opening towards the aperture 43 in the substrate 41. A stack of integrated circuit circuits 11,...

20060081981 - Method of forming a bond pad on an i/c chip and resulting structure: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a...

20060081982 - Chip scale package with micro antenna and method for manufacturing the same: A chip scale package with micro antenna includes a chip, a first dielectric layer and an antenna. The chip has an active surface, a first bonding pad and a second bonding pad on the active surface. The first dielectric layer is formed on the active surface of the chip. The...

20060081984 - Power grid layout techniques on integrated circuits: Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive...

20060081983 - Wafer level microelectronic packaging with double isolation: A microelectronic package may include front and rear covers overlying the front and rear surfaces of a microelectronic element such as an infrared sensor and spaces between the microelectronic element and the covers to provide thermal isolation. A sensing unit including a microelectronic package may include a reflector spaced from...

20060081985 - Iii-nitride power semiconductor device with a current sense electrode: A III-nitride power semiconductor device that includes a current sense electrode....

20060081986 - Modified via bottom structure for reliability enhancement: The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the...

20060081987 - Semiconductor device and method for fabricating the same: A semiconductor device has a first interlayer insulating film formed on a substrate, having a first interconnection buried therein, and having a depressed portion and an insulating barrier film formed on the first interlayer insulating film. A second interlayer insulating film is formed to fill in the depressed portion, cover...

20060081988 - Shapes-based migration of aluminum designs to copper damascene: An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes....

20060081989 - Structure of polymer-matrix conductive film and method for fabricating the same: A composite conductive film formed of a polymer-matrix and a plurality of conductive lines less than micro-sized and its fabricating method are provided. The conductive lines are arranged parallel and spaced apart from each other so as to provide anisotropic conductivity. The present conductive film can serve as an electrical...

20060081990 - Circuit structure: A circuit structure for a package substrate or a circuit board is provided. The circuit structure has a dielectric layer with an upper surface and a lower surface, at least a first line and at least a second line. The first line is disposed on the dielectric layer on which...

20060081991 - Computer automated design system, a computer automated design method, and a semiconductor integrated circuit: A computer automated design system includes a subject routing module configured to set a first grid area and a first diagonal grid area and route a first wire in the first grid area and a first diagonal wire extending diagonally to a longitudinal direction of the first wire and a...

20060081992 - Semiconductor device with a fluorinated silicate glass film as an interlayer metal dielectric film, and manufacturing method thereof: A plurality of metal wire layers consisting of a first metal wire layer and a second metal wire layer are formed on a semiconductor substrate. A fluorinated silicate glass film serving as an interlayer metal dielectric film is formed between the first and second metal wire layers. A silicon nitride...

20060081993 - High luminance coated glass: A coating composition and related coated substrates are disclosed. The coating composition of the present invention includes a first dielectric layer having a thickness ranging from 380 Å to 430 Å; a first metal layer over the first dielectric layer having a thickness ranging from 60 Å to 130 Å;...

20060081994 - Assembly: An assembly includes a substrate, a device coupled to the substrate; a ring formed on the substrate; and one or more bonding pads formed on the substrate, wherein the ring and bonding pads are formed of a same material....

20060081995 - Soldered material, semiconductor device, method of soldering, and method of manufacturing semiconductor device: A soldered material according to an aspect of the present invention comprises a first metallic material to be soldered, a second metallic material to be soldered which is composed of at least one element selected from the group consisting of nickel, palladium, platinum and aluminum, and a soldering layer soldering...

20060081997 - Liquid crystal display: A display device includes a substrate having plural signal lines connected to switching elements which are formed in an image display region, and plural terminals connected to respective ones of the signal lines. The terminals include a first group arranged at an image display region side and a second group...

20060081996 - Semiconductor device having aluminum electrode and metallic electrode: A semiconductor device includes: a semiconductor substrate; an aluminum electrode disposed on the surface of the substrate; a protection film disposed on the aluminum electrode and having an opening; and a metallic electrode disposed on a surface of the aluminum electrode through the opening of the protection film. The surface...

20060081998 - Methods of forming in package integrated capacitors and structures formed thereby: Methods of forming a microelectronic structure are described. Those methods comprise depositing a bottom electrode, depositing a dielectric layer on the bottom electrode, forming at least one via in the dielectric layer, wherein a bottom surface of the via does not contact a top surface of the bottom electrode, and...

20060081999 - Connection structure for connecting semiconductor element and wiring board, and semiconductor device: In a connection structure of the present invention, the wiring board including a solder resist covering part which covers the wiring pattern with solder resist, the solder resist covering part having a solder resist opening or solder resist openings which expose(s) the wiring board connection terminals therethrough, and the solder...

20060082001 - Printed wiring board and information processing device incorporating the board: A printed wiring board mounted with a BGA package including pads, through holes and leads. The leads are linearly formed with almost the same width as the diameter of each of the pads and through holes and thus have high bonding strength against their peeling against an external force. The...

20060082000 - Structure and method for contact pads having a recessed bondable metal plug over of copper-metallized integrated circuits: A metal structure for an integrated circuit, which has copper interconnecting metallization (311) protected by an overcoat layer (320). A portion of the metallization is exposed in a window (301) opened through the thickness of the overcoat layer. The metal structure comprises a patterned conductive barrier layer (330) positioned on...

20060082003 - Method of dicing a semiconductor device into plural chips: A semiconductor device includes a substrate, a seal layer which seals a semiconductor element formed on the substrate, wherein a side surface of the seal layer is positioned inside of a side surface of the substrate....

20060082002 - Sheet for circuit substrates and sheet of a circuit substrate for displays: A sheet for circuit substrates for displays which comprises a polymer material of an energy ray hardening type for embedding circuit chips, wherein a storage modulus of an unhardened layer comprising the polymer material of an energy ray hardening type is 103 Pa or greater and smaller than 107 Pa...

20060082004 - Methods of forming memory circuitry: The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact...

20060076547 - Three-dimensional viewing and editing of microcircuit design: An editing tool that provides a user interface for displaying and editing a representation of a microcircuit design. More particularly, the user interface displays a three dimensional representation of a second portion of the circuit design. A user can then select and edit a structure employing the three-dimensional representation of...

20060076548 - Prams having a plurality of active regions located vertically in sequence and methods of forming the same: There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one...

20060076549 - Semiconductor memory: The object of providing a non-volatile semiconductor memory that stands out by good scalability and a high retention time as well as ensures low switching voltages at low switching times and achieves a great number of switching cycles at good temperature stability is solved by the present invention with a...

20060076550 - Light emitting display and light emitting display panel: A display device according to an embodiment of the present invention includes a pixel driver, first, second, and third light emitting diodes, and first, second, and third switches. The pixel driver outputs a driving current corresponding to a data signal to an output terminal in response to the scan signal....

20060076552 - Light emitting device and method for fabricating the same: The light emitting device comprises a substrate 10 of a p-type semiconductor; an active layer 20 formed of a plurality of quantum dot layers 18 stacked, the quantum dot layers 18 having three-dimensional grown islands self-formed by S-K mode, respectively; and an n-type semiconductor layer 22 formed over the active...

20060076551 - Nanotube based multi-level memory structure: A multi-level memory structure comprises the junction of a series of metallic type nanotube structures attached to a semiconductive nanotube so that electrons are substantially captured in said junction. In the preferred embodiment, one or more arms of the metallic type nanotube structures include one or more boron nitride bands....

20060076557 - Aqueous dispersions of polythienothiophenes with fluorinated ion exchange polymers as dopants: Compositions are provided comprising aqueous dispersions of polythienothiophenes and colloid-forming polymeric acids. Films from invention compositions are useful as hole injection layers in organic electronic devices, including electroluminescent devices, such as, for example, organic light emitting diodes (OLED) displays, as hole extraction layers in organic optoelectronic devices, such as organic...

20060076553 - Compounds for organic semiconductor device having triazine group, organic semiconductor thin film and organic semiconductor device comprising the same, and methods of preparing them: m

20060076555 - Detection and repair system and method: A detection and repair system applied for organic light-emitting devices comprises a distance measuring unit, a processing controller, a detector and a high-energy radiation beam generator. The distance measuring unit automatically detects the location of the organic light-emitting device. The processing controller generates a first control signal for automatically adjusting...

20060076554 - Organic semiconductor material, organic semiconductor structure, and organic semiconductor device: To achieve the object, the present invention provides an organic semiconductor material comprising a quaterthiophene skeleton shown in a following chemical formula 1, wherein R1 in the chemical formula 1 is an alkyl group of C1 to C20 or a hydrogen, and R2 is an alkyl group of C1 to...

20060076556 - Semiconductor device and method for manufacturing the same: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes conductor or semiconductor fine particles, and organic semiconductor molecules bonded to the fine particles to form a conductive path, the conductivity of the conductive path being controlled by an electric field. In the semiconductor device,...

20060076558 - Semiconductor device and manufacturing method thereof: An object of the present invention is to prevent a junction leakage current generation across a pn junction formed under a silicide layer, even when a direct probing to an electrode formed of the silicide layer is performed. There is provided a semiconductor device including an element for evaluation, wherein...

20060076559 - Method of fabricating an epitaxially grown layer: A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown...

20060076561 - Active matrix type display device and method of manufacturing the same: A method of manufacturing an active matrix type display device, which is reliable and flexible, is provided. An active matrix type display device according to an aspect of the present invention includes: a first substrate, which is flexible; a thin glass layer provided on the first substrate via an adhesion...

20060076560 - Thin-film semiconductor device, electro-optical device, and electronic apparatus: A thin-film semiconductor device includes, on the same substrate, a thin-film transistor, in which an active layer, a gate insulating film, and a gate electrode are laminated, and a capacitive element, in which a first electrode formed using a semiconductor film formed on the same layer as the active layer,...

20060076563 - Method of forming a pattern, method of forming wiring, semiconductor device, tft device, electro-optic device, and electronic instrument: A method of forming a pattern of a functional layer on a surface of a substrate, where a pattern region, to which the pattern is provided, is edged with a boundary layer, and has a first region and a second region communicated with the first region and having a narrower...

20060076562 - Thin film transistor array panel and method for manufacturing the same: The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion...

20060076564 - Gallium-nitride based semiconductor device buffer layer structure: A buffer layer structure for the GaN-based semiconductor devices is provided. The buffer layer proposed by the present invention comprises internally at least two sub-layers: a first intermediate layer and a second intermediate layer. Initially, the first intermediate layer is developed on the substrate under a low temperature using silicon-nitride...

20060076566 - Light emitting device and optical device using the same: A light emitting device which can be easily manufactured and can control the positions of light emission precisely, and an optical device. A first and second light emitting elements are formed on one face of a supporting base. The first light emitting element has an active layer made of GaInN...

20060076565 - Semiconductor light emitting element and fabrication method thereof: In a semiconductor light emitting element, multiple bosses having a cylindrical shape and dispersed like islands, and recesses are formed on the upper surface of a window layer. A contact electrode is formed on the upper surface of the bosses. A transparent dielectric film is formed in the recesses. A...

20060076567 - Driving method of light emitting device: If a potential of a gate electrode of a driving transistor varies after a gray scale signal is inputted into each pixel, a current value of a current supplied to a light emitting element varies so that accurate gray scale display cannot be obtained. In particular, in the case of...

20060076569 - Semiconductor light emitting device: In one aspect of the present invention, a semiconductor light emitting device may include a light emitting element configured to emit a first wavelength light and a phosphor configured to absorb the first wavelength light and emit light of a second wavelength which is different from the first wavelength. The...

20060076568 - Side-emitting optical coupling device: An LED package includes a LED structure that outputs light in a pattern about an axis and an optical coupling device with a central axis. The coupling device is positioned relative to the LED structure and accepts light from the LED. The coupling device includes a first dielectric interface surface...

20060076572 - Light-emitting diode arrangement and motor vehicle headlamp: A light-emitting diode arrangement having at least one light-emitting diode chip (1), each light-emitting diode chip (1) being assigned at least one optical element (4). In addition, the light-emitting diode arrangement has at least one heat-conducting element (13) which is suitable to carry away the heat generated by the light-emitting...

20060076571 - Semiconductor light-emitting element assembly: A semiconductor light-emitting element assembly, comprising a composite substrate, a circuit layout carrier, a connecting structure, a recess, and a semiconductor light-emitting element, is disclosed. The connecting structure is used for bonding the composite substrate with the circuit layout carrier. The recess is formed by the circuit layout carrier and...

20060076570 - Smd(surface mount device)-type light emitting diode with high heat dissipation efficiency and high power: A SMD-type LED with high heat dissipation efficiency and high power includes a base with a post arranged and integrated on the center thereof and a slot on top of the post. At least one contact hole is arranged on bottom of the base for connecting with an external heat...

20060076573 - Structure of chip carrier for semiconductor optical device, optical module, and optical transmitter and receiver: A chip carrier includes a metal-coated portion formed on a front surface of a substrate and to be mounted a device, and a rear surface of the substrate being coated with a metal, in which a metal-coated portion is formed on a side surface of the substrate and the metal-coated...

20060076574 - Gallium-nitride based light-emitting diodes structure with high reverse withstanding voltage and anti-esd capability: An epitaxial structure for GaN-based LEDs to achieve better reverse withstanding voltage and anti-ESD capability is provided herein. The epitaxial structure has an additional anti-ESD thin layer as the topmost layer, which is made of undoped indium-gallium-nitrides (InGaN) or low-band-gap (Eg<3.4 eV), undoped aluminum-indium-gallium-nitrides (AlInGaN). The anti-ESD thin layer could...

20060076575 - Semiconductor device: There is provided a semiconductor device in which the thresholds of gate electrodes in transistors can be adjusted together for each of regions having their own functions different from one another. The semiconductor device is provided with: a P-type Si substrate 109; a P-type annular well 181 provided in the...

20060076576 - High electron mobility epitaxial substrate: A compound semiconductor epitaxial substrate for use in a strain channel high electron mobility field effect transistor, comprising an InGaAs layer as a strain channel layer 6 and AlGaAs layers containing n-type impurities as back side and front side electron supplying layers 3 and 9, wherein an emission peak wavelength...

20060076577 - High electron mobility transistors with sb-based channels: This invention pertains to an electronic device containing a semi-insulating substrate, a buffer layer of an antimony-based material disposed on said substrate, a channel layer of InAsySb1−y material disposed on said buffer layer, a barrier layer of an antimony-based disposed on said channel layer, and a cap layer of InAsySb1−y...

20060076578 - Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom: A donor wafer resulting from a method of recycling the wafer after detaching at least one useful layer. The donor wafer includes a substrate; a buffer structure on the substrate; a protective layer associated with the buffer structure; and a post detachment layer located above the buffer structure and presenting...

20060076580 - Image sensor with vertically integrated thin-film photodiode: An image sensor with a vertically integrated thin-film photodiode includes a bottom doped layer of a PIN photodiode imbedded in a dielectric layer, wherein a bottom surface of the bottom doped layer completely contacts its corresponding underlying pixel electrode. The bottom doped layers of the PIN photodiodes are formed by...

20060076579 - Semiconductor transistor having structural elements of differing materials: A transistor is formed using a semiconductor substrate and forming a control electrode overlying the semiconductor substrate. A first current electrode is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a first predetermined semiconductor material. A second current electrode is formed within the...

20060076581 - Solid-state image sensor: A solid-state image sensor capable of suppressing increase of a dark current and a power consumption, and suppressing reduction of a transfer efficiency of electrons is provided. The solid-state image sensor comprises a charge storage region including a first conductive type first impurity region that has a first depth from...

20060076582 - Solid-state imaging device, method for manufacturing the same and interline transfer ccd image sensor: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided...

20060076583 - Semiconductor device and manufacturing method thereof: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity...

20060076584 - Fabrication of electronic and photonic systems on flexible substrates by layer transfer method: A transfer layer includes a transparent substrate. A buffer layer is formed on the transparent substrate that comprises PbO, GaN, PbTiO3, La0.5Sr0.5CoO3 (LSCO), or LaxPb1-xCoO3 (LPCO) so that separation between the buffer layer and the transparent substrate occurs at substantially high temperatures....

20060076585 - Semiconductor resistor and method for manufacturing the same: An object of the present invention is to provide a semiconductor resistor that allows improvement in saturation voltage characteristics and a method for manufacturing the same. The semiconductor resistor of the present invention is formed on the substrate on which a GaAs FET is formed. The GaAs FET includes: a...

20060076586 - Virtual ground memory array and method therefor: A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer...

20060076587 - Solid-state image sensor: A p+-type region 5 on a surface of a photodiode unit is formed over a region from a surface of the photodiode unit through a surface of a signal charge read-out unit 9 until reaching the charge transfer unit. Also, the following structure is adapted: the structure in which a...

20060076588 - Image sensor and pixel having a non-convex photodiode: In a photodiode used in a pixel of an image sensor, the area of interface between an N-type region and a P-type region is increased, such as through the use of an interstitial P+-type region or an interstitial P-type region. By increasing the interface area, greater well capacity can be...

20060076589 - Pin photodiode structure and fabrication process for reducing dielectric delamination: A PIN photodiode, and a method of manufacturing a PIN photodiode that reduces dielectric delamination and increases device reliability. The process proceeds by forming an first type electrode layer on the substrate; forming an intrinsic layer of the first type electrode layer; forming a second type electrode layer on the...

20060076591 - Solid state image pickup element and method of manufacturing solid state image pickup element: Provided is a solid state image pickup element which can exponentially reduce the in-plane photoelectric conversion portion characteristic distribution that is created in forming color filters by a common photolithography technique and which, when color filters are formed by split exposure, can reduce image non-uniformity between exposure regions in a...

20060076590 - Structure for implementation of back-illuminated cmos or ccd imagers: A structure for implementation of back-illuminated CMOS or CCD imagers. An epitaxial silicon layer is connected with a passivation layer, acting as a junction anode. The epitaxial silicon layer converts light passing through the passivation layer and collected by the imaging structure to photoelectrons. A semiconductor well is also provided,...

20060076592 - Integratable polarization rotator: Embodiments of the invention provide a polarization rotator. The polarization rotator may be integrated with a waveguide on a substrate, and may include a ferromagnetic semiconductor layer on the substrate, a first doped layer on the ferromagnetic semiconductor layer, and a second doped layer on the first doped layer....

20060076593 - Method to sputter deposit metal on a ferroelectric polymer: Methods of depositing various metal layers adjacent to a ferroelectric polymer layer are disclosed. In one embodiment, a collimator may be used during a sputtering process to filter out charged particles from the material that may be deposited as a metal layer. In various embodiments, a metal layer may contain...

20060076595 - Dynamic random access memory cell and fabricating method thereof: A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep trench. Thereafter, a trench is formed...

20060076597 - Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers: Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and...

20060076596 - Semiconductor device: A capacity element with a simple configuration exhibits excellent production reliability. A semiconductor device 100 includes a capacity element consisting of a lower electrode 102, an SiCN film 107 and an upper electrode 113. In an insulating film 101 on a semiconductor substrate is formed a groove, in which the...

20060076598 - Semiconductor device and method of fabrication: A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main...

20060076594 - Semiconductor memory device: The present invention provides a semiconductor memory device which comprises an interlayer insulating film formed on a semiconductor substrate, a contact plug formed in the interlayer insulating film and having one end electrically connected to the semiconductor substrate, a ferroelectric capacitor formed on the interlayer insulating film and comprising a...

20060076599 - Semiconductor memory devices including offset active regions: A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width...

20060076600 - Semiconductor device and method for fabricating the same: In a method for fabricating a semiconductor device according to the present invention, a groove is formed in a second interlayer insulating film, and then a storage electrode is formed which covers bottom and side surfaces of the groove. A capacitor insulating film is formed on the storage electrode, and...

20060076602 - Dram cell pair and dram memory cell array: Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for...

20060076601 - Dynamic random access memory structure: A dynamic random access memory structure is provided, each active area of a memory unit cell is distributed individually in a substrate, and deep trench patterns are designed to have a checkerboard-like arrangement in the substrate. Also, there is a constant space between each deep trench pattern in a row....

20060076603 - Semiconductor device having polycide wiring layer, and manufacturing method of the same: A semiconductor device is provided with a semiconductor substrate comprising element isolation regions and an element region surrounded by the element isolation regions, a first polysilicon layer formed in the element region of the semiconductor substrate, an element-isolating insulation film formed in the element isolation region of the semiconductor substrate,...

20060076604 - Virtual ground memory array and method therefor: A virtual ground memory array (VGA) is formed by forming source/drain lines using a patterned photoresist layer over a sacrificial layer. The sacrificial layer is opened according to the pattern of the patterned photoresist layer. The openings are implanted to form the source/drain lines then filled with a conformal layer...

20060076605 - Improved flash forward tunneling voltage (ftv) flash memory device: A FLASH memory device comprising a substrate having a gate conductor formed thereover is provided. The gate conductor comprises a gate with a floating gate oxide layer formed thereon, the floating gate oxide layer including respective lateral tip portions, whereby the forward tunneling voltage of the FLASH memory is improved....

20060076608 - Cell structure of non-volatile memory device and method for fabricating the same: A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first...

20060076606 - Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device: A method of simultaneously fabricating at least two semiconductor devices, at least one of which is a nanocrystal memory and at least one of which is a non-nonocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semiconductor devices being fabricated. The nanocrystal...

20060076607 - Non-volatile memory and method of fabricating same: In one embodiment, a semiconductor device comprises an insulated floating gate disposed on a semiconductor substrate, an insulated program gate formed at least on a side surface of the floating gate, and an insulated erase gate disposed adjacent the floating gate....

20060076609 - Electronic device including an array and process for forming the same: An electronic device can include an NVM array, wherein portions of word lines are formed within trenches. Insulating features are formed over heavily doped regions within the substrate. In one embodiment, charge storage stacks and a control gate electrode layer can be formed and substantially fill the trench. The insulating...

20060076611 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed, which comprises trench type device isolation regions formed in a semiconductor substrate, semiconductor active regions electrically isolated by the isolation regions, a first electrode layer formed to self-align to the isolation regions, and a second electrode layer formed over the first electrode layer with an...

20060076610 - Semiconductor integrated circuit device with reduced leakage current: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low...

20060076612 - Semiconductor device and manufacturing method of the same: In a manufacturing method of a semiconductor device according to the invention, a silicon oxide film, a polysilicon film, and silicon nitride film are deposited. An opening for forming a LOCOS oxide film is provided in the polysilicon film and the silicon nitride film. Then, using the opening, a P-type...

20060076616 - High density memory array having increased channel widths: A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to...

20060076613 - Semiconductor device: A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second...

20060076614 - Semiconductor device: A semiconductor device well balanced between high voltage applicability and low ON resistance, includes an n+-type semiconductor substrate; an n-type drift region formed thereon; a p-type base region formed on the n-type drift region; a plurality of p-type column regions in the n-type drift region so as to contact with...

20060076615 - Vertical field-effect transistor in source-down structure: The invention relates to a vertical field-effect transistor in source-down structure, in which the active zones (10, 7, 11) are introduced from trenches (5, 8, 9) into a semiconductor body (1), a source electrode (18) being connected via the filling (6) of a body trench (5) to a highly doped...

20060076617 - Mos-gated transistor with reduced miller capacitance: In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom...

20060076619 - Dielectric plug in mosfets to suppress short-channel effects: The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices including a MOSFET having a dielectric plug. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the...

20060076618 - Semiconductor device having variable thickness insulating film and method of manufacturing same: Embodiments of a semiconductor device capable of increasing an aperture ratio of an organic electroluminescence display device by decreasing the surface area of a capacitor in the organic electroluminescence display device and a method of manufacturing the semiconductor device are disclosed. By forming a gate insulating film of a gate...

20060076620 - Semiconductor device: The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control...

20060076621 - Lateral semiconductor transistor: A lateral semiconductor transistor is disclosed. In one embodiment, the transistor includes a semiconductor body, in which a source region, a body region and a drain region, a drift region extending in the lateral direction between body region and drain region, and also a gate are formed. The gate is...

20060076623 - High mobility plane cmos soi: Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate...

20060076622 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device including an NMOS region and a PMOS region in the same substrate, wherein the semiconductor device includes a strained Si layer which is provided on the substrate in the NMOS region and in which the surface has a plane orientation different from that of the substrate, and...

20060076624 - Semiconductor substrate, method of manufacturing the same, semiconductor device, and method of manufacturing the same: A semiconductor substrate is disclosed which comprises a first single crystal silicon layer, an insulator formed to partially cover one main surface of the first single crystal silicon layer, a second single crystal silicon layer formed to cover a region of the first single crystal silicon layer which is not...

20060076625 - Field effect transistors having a strained silicon channel and methods of fabricating same: Field effect transistors (FETs) and methods of fabricating FETs that include a channel layer on sidewalls of a structure on a semiconductor substrate and having at least a portion of the channel layer strained in a direction that the sidewalls of the structure extend from the semiconductor substrate are provided....

20060076626 - Semiconductor integrated circuit device, contactless electronic device, and handheld terminal: In a semiconductor integrated circuit device in which a rectifier device constituting a rectifier comprises a MOS transistor whose gate is connected to one antenna terminal and whose source is connected to the other antenna terminal, the parasitic capacitance applied between the antenna terminals increased. The present invention provides a...

20060076627 - Ultra shallow junction formation by epitaxial interface limited diffusion: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is...

20060076628 - Integrated circuit with bulk and soi devices connected with an epitaxial region: An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk regions. The SOI and bulk regions may have the same or...

20060076629 - Semiconductor devices with isolation and sinker regions containing trenches filled with conductive material: A semiconductor structure includes a trench formed in an epitaxial layer that overlies a semiconductor substrate, the sides of the trench being lined with an oxide layer. The trench is filled with a conductive material, e.g., a metal or heavily-doped polysilicon, and the conductive is in contact with the substrate...

20060076630 - Integrated transistor devices: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14)...

20060076631 - Method and system for providing mems device package with secondary seal: A MEMS device package comprises a substrate with a MEMS device formed thereon, a backplane, and a primary seal, wherein the primary seal is positioned between the backplane and the substrate to encapsulate and seal the MEMS device package from ambient conditions. The MEMS device package further comprises a secondary...

20060076633 - Methods and apparatus for particle reduction in mems devices: A method for assembling a micro-electromechanical system (MEMS) device that includes a micro-machine is described. The method comprises forming the micro-machine on a die, the die having a top surface and a bottom surface, providing a plurality of die bonding pedestals on a surface of a housing, and mounting at...

20060076632 - System and method for display device with activated desiccant: A MEMS device package comprises a substrate with a MEMS device formed thereon, a backplane, a seal, and an inactive desiccant within the package. The desiccant is activated after assembly of the package by exposure to an environmental change or an activating substance. A method of packaging a MEMS device...

20060076634 - Method and system for packaging mems devices with incorporated getter: Methods and systems for packaging MEMS devices such as interferometric modulator arrays are disclosed. One embodiment of a MEMS device package structure includes a seal with a chemically reactant getter. Another embodiment of a MEMS device package comprises a primary seal with a getter, and a secondary seal proximate an...

20060076635 - Magnetoresistive memory device assemblies, and methods of forming magnetoresistive memory device assemblies: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the...

20060076636 - Solid-state imaging device: In a solid-state imaging device including an on-chip microlens and a light-receiving part to receive incident light condensed by the on-chip microlens, an optical waveguide extending from an undersurface part of the microlens to the light-receiving part and for guiding the incident light condensed by the microlens to the light-receiving...

20060076637 - Method and system for packaging a display: A package structure and method of packaging for an interferometric modulator. A transparent substrate having an interferometric modulator formed thereon is provided. A backplane is joined to the transparent substrate with a seal where the interferometric modulator is exposed to the surrounding environment through an opening in either the backplane...

20060076638 - Semiconductor device, mounting structure, electro-optical device, method of manufacturing electro-optical device, and electronic apparatus: A semiconductor device includes a protrusion group composed of a plurality of first protrusions arranged on a mounting surface with predetermined gaps; a plurality of second protrusions for burying spaces between the neighboring first protrusions; and conductive members provided on protruding surfaces of the plurality of first protrusions....

20060076639 - Schottky diodes and methods of making the same: In one aspect, a Schottky diode includes a semiconductor material, and a metal material forming a Schottky barrier junction with the semiconductor material, wherein a cavity having a lateral dimension of at least 200 nm is adjacent to the Schottky barrier junction. In another aspect, a Schottky diode includes a...

20060076640 - Semiconductor device: A semiconductor device, comprising a trench extending into the device from a surface. The trench has sidewalls extending along the length of the trench, a depth and a width defined at said surface between said sidewalls. The trench is at least partly filled with a material. At least one of...

20060076641 - Methods of fabricating phase changeable semiconductor memory devices including multi-plug conductive structures and related devices: In fabricating a phase changeable memory device, an insulating layer with an opening extending therethrough is formed on a substrate. A conductive structure is formed in the opening. The conductive structure includes a first conductive plug on opposing sidewalls of the opening and a surface therebetween and a second plug...

20060076642 - Semiconductor device and manufacturing method thereof: The present invention provides a semiconductor device comprising: a substrate; a first insulating film formed on a principal surface of the substrate; a second insulating film formed on the first insulating film; a plurality of fuses formed on the second insulating film; and a blocking layer disposed in the first...

20060076643 - Fin-type antifuse: A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting the center portion of the...

20060076644 - Nanowire filament: A method of manufacturing a nanowire filament includes forming and fusing actions. In a forming action, close proximity conductors are formed. In another forming action, a junction oxide is formed between the close proximity conductors. In a fusing action, a nanowire filament is fused between the close proximity conductors, through...

20060076645 - Method for producing vertical bipolar transistors and integrated circuit: A method for producing vertical bipolar transistors having different voltage breakdown and high-frequency performance characteristics on a single die comprises forming, for each of the vertical bipolar transistors, a buried collector region, and base and emitter regions above the buried collector region. The lateral extensions and locations of the base...

20060076646 - Apparatus and method for visible imaging using darlington phototransistors: The present invention is a modified darlington phototransistor wherein a phototransistor is coupled to a Bipolar Junction Transistor (BJT). This design provides a high sensitivity and a fast response and effectively increases the gain of the photocurrent. This circuit is particularly will suited for the readily available CMOS and Bipolar...

20060076647 - Semiconductor component with a bipolar lateral power transistor: A semiconductor component comprising at least one lateral bipolar power transistor which is composed of at least one group of single transistors with a common collector-, base- and emitter zone, which are parallel connected by three conductor track systems which bring together the emitter-, base- and collector currents of each...

20060076649 - Substrate for stressed systems and method of making same: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer....

20060076648 - System and method for protecting microelectromechanical systems array using structurally reinforced back-plate: Disclosed is an electronic device utilizing interferometric modulation and a package of the device. The packaged device includes a substrate, an interferometric modulation display array formed on the substrate, and a back-plate. The back-plate is placed over the display array with a gap between the back-plate and the display array....

20060076651 - Electronic device and method for fabricating the same: An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed in the interlayer insulating films in the chip region, and a plug formed in the interlayer insulating films in the chip region and...

20060076650 - Multilayered structure, multilayered structure array and method of manufacturing the same: The productivity of a multilayered structure etc. is improved by easily forming insulating films for insulating internal electrode layers from side electrodes. The multilayered structure includes: a first internal electrode layer including a first conducting material extending to a first side surface of the multilayered structure and having magnetism at...

20060076652 - Method of forming a field effect transistor comprising a stressed channel region: A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined tensile intrinsic stress of about 900 MPa or more. Due to this high intrinsic stress, the stressed layer exerts considerable elastic forces to the...

20060076653 - Passivation layer assembly on a substrate and display substrate having the same: A passivation layer assembly and a display substrate having the same are presented. The passivation layer assembly is positioned on a substrate having a thin film assembly and protects the thin film assembly. The thin film assembly includes a first passivation layer and a second passivation layer. The first passivation...

20060076655 - Integrated circuit package employing a flexible substrate: An integrated circuit package includes a flexible laminar substrate 1. The substrate 1 has a flexible layer 5 of heat conductive material on one of its faces. The layer 5 extends across an aperture 9 in the flexible substrate 1. A first integrated circuit 11 is mounted on the layer...

20060076654 - Lead frame and physical amount sensor: A lead frame for a physical sensor is made of sheet metal and includes a stage for mounting a physical sensor chip, a frame having a plurality of leads disposed peripherally around the stage, and a pair of connecting members which connect the frame and the stage and are oppositely...

20060076656 - Electro-optical device and electronic apparatus: An electro-optical device includes an electro-optical panel having a substrate; a plurality of input terminals that are arranged in a first direction on the substrate; and a semiconductor device provided with a plurality of input bumps electrically connected to the input terminals through conductive organic members. The input terminals connected...

20060076657 - Die attach paddle for mounting integrated circuit die: An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper...

20060076661 - Attachment of integrated circuit structures and other substrates to substrates with vias: Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The...

20060076659 - Chip package structure, package substrate and manufacturing method thereof: A package substrate for carrying a chip with a plurality of bumps thereon is provided. The package substrate includes a first substrate, and an interposer. The first substrate has a first circuit layer disposed on a surface thereof. The interposer includes a second substrate and a second circuit layer formed...

20060076660 - Power transistor: A power transistor includes a leadframe and a semiconductor chip arranged on the leadframe. The top side of the semiconductor chip has a drain contact-making layer, and the underside of the semiconductor chip has a source contact-making layer. The source contact-making layer bears directly on the leadframe. A gate contact-making...

20060076658 - Semiconductor package structure with microstrip antennan: A semiconductor package structure with a microstrip antenna comprises a packaging substrate, a chip and a microstrip radiation device. The packaging substrate has an upper surface having a packaging area on which the chip is disposed and a peripheral area on which the microstrip radiation device is disposed for transceiving...

20060076663 - Deterministic generation of an integrated circuit identification number: The generation of an identification number of a chip supporting at least one integrated circuit, including the step of causing a cutting of at least one conductive section by cutting of the chip among several first conductive sections parallel to one another and perpendicular to at least one edge of...

20060076662 - Memory card structure and manufacturing method thereof: A memory card structure comprising a substrate, a plurality of memory chips, some molding compound and an ultra-thin plastic shell is provided. To fabricate the memory card, a substrate having a first surface and a second surface is provided. The first surface has a plurality of outer contacts and the...

20060076664 - 3d interconnect with protruding contacts: This invention relates to a semiconductor having protruding contacts comprising, a first semiconductor substrate having at least one interconnect located substantially within the first substrate, and a second semiconductor substrate having at least one protruding contact point that substantially contacts at least one interconnect....

20060076665 - Package stack and manufacturing method thereof: A package stack may include a first package and a second package. The first package may have an IC chip with an active surface and a back surface. The active surface may be connected to a first major surface of a first circuit substrate. The second package may include a...

20060076666 - Micro-electro-mechanical system (mems) package having hydrophobic layer: A micro-electro-mechanical system (MEMS) package having a hydrophobic layer is disclosed. The MEMS package includes: a base substrate, with an MEMS element provided on a surface of the base substrate; a lid, spaced apart from the MEMS element provided on the base substrate and covering the MEMS element; a side...

20060076667 - Semiconductor component with plastic housing, and process for producing the same: A semiconductor component includes a plastic housing including: plastic outer surfaces; lower outer contact surfaces arranged on an underside of the housing; upper outer contact surfaces arranged on a top side of the housing that is opposite the underside; and outer interconnects electrically connecting the lower outer contact surfaces to...

20060076668 - Multi-layer printed circuit board: A multi-layer PCB includes a first signal layer, a ground layer, a second signal layer, a third signal layer, an electric power layer, and a fourth signal layer, including a first insulating layer arranged between the first signal layer and the ground layer; a second insulating layer arranged between the...

20060076669 - Deflectable probe and thermometer: A deflectable probe for use in a thermometer. The deflectable probe is constituted by a bendable probe body and a hollow tip member secured thereto. Furthermore, a deflectable member includes a main portion disposed in the bendable probe body. When the bendable probe body is subjected to a force, deformation...

20060076670 - Micro-electro-mechanical system (mems) package having metal sealing member: A micro-electro-mechanical system (MEMS) package having a metal sealing member is disclosed. The MEMS package is formed by forming a metal layer on a substrate by patterning so that the metal layer surrounds an MEMS element provided on the substrate; joining a lid to the metal layer; providing a side...

20060076671 - Semiconductor chip mounting wiring board, manufacturing method for same, and semiconductor module: A semiconductor module is produced by mounting the semiconductor chip 3 in advance on the first conductive bump 12 on the semiconductor chip mounting wiring board 2 and stacking a plurality of the wiring boards 2 and interlayer members 20 each having an opening 27 to receive the semiconductor chip...

20060076672 - Magnetic attachment method for led light engines: A light engine (16) includes at least one LED (12) for generating light of one of a plurality of wavelengths. The LED (12) is disposed on the magnetic core printed circuit board (14). A heatsink (26) is disposed in thermal communication with a base (24) and the LED (12) for...

20060076673 - Power amplifier module: A semiconductor device has a plurality of external connection lead terminals including an input lead terminal, an output lead terminal, and an RF grounding lead terminal, a heat dissipation plate connected to the RF grounding lead terminal, a semiconductor device and a printed circuit board each mounted on the heat...

20060076674 - Semiconductor device: A semiconductor device mountable on a wiring board with the bottom surface being opposed to the wiring board. The semiconductor device includes: a semiconductor chip; a mold resin encapsulating the semiconductor chip; a first heat spreader joined to the semiconductor chip on the bottom surface side with both ends thereof...

20060076675 - Semiconductor device having projection on surface thereof, and method of identifying semiconductor package: A technique of accurately recognizing a semiconductor device and of specifying a package type thereof will be provided. By forming, on the package surface, projections having a geometric pattern such as a circle pattern using an ejector pin 11 and by judging only presence or absence of the circular projections...

20060076676 - Multi-chip integrated circuit module for high-frequency operation: A multi-chip electronic module comprises a multiplicity of integrated circuit chips arranged in a vertical stack. Each chip includes at least one first electrical terminal, with at least a first subset of the first terminals being disposed at different heights relative to the stack. A multiplicity of second electrical terminals...

20060076677 - Resist sidewall spacer for c4 blm undercut control: A method and system for preventing undercutting of the solder bump in a C4 package by forming a barrier of resist that effectively widens the footprint of the solder bump. The BLM is then etched to the perimeter edge of the barrier rather than the solder bump, thereby precluding any...

20060076678 - Thick metal layer integrated process flow to improve power delivery and mechanical buffering: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may...

20060076679 - Non-circular via holes for bumping pads and related structures: An integrated circuit device may include a substrate, a conductive pad on a surface of the substrate, and a conductive line on the surface of the substrate. Moreover, the conductive line may be connected to the conductive pad, and the conductive line may be narrow relative to the conductive pad....

20060076680 - Submicron contact fill using a cvd tin barrier and high temperature pvd aluminum alloy deposition: A submicron contact opening fill using a chemical vapor deposition (CVD) TiN liner/barrier and a high temperature, e.g., greater than about 385° C., physical vapor deposition (PVD) aluminum alloy layer that substantially fills the submicron contact....

20060076682 - Advanced copper damascene structure: A method of forming round bottom corners for conductive lines in an integrated circuit is presented. Two approaches are taken to achieve a preferred rounding profile. For both approaches, a trench is formed and conductive materials are filled in the trench. The etch stop layer (ESL) approach involves forming an...

20060076683 - Printed wiring board, information processing apparatus, and method of manufacturing the printed wiring board: Disclosed is a printed wiring board comprising an insulating layer having a rectangular flat shape and provided with fibers in the layer, the direction of the fiber in the layer being almost parallel to any side of the rectangle, a reference potential layer disposed on one surface side of the...

20060076681 - Semiconductor package substrate for flip chip packaging: A substrate of semiconductor package for flip chip package is provided. The substrate comprises a plurality of bump pads; a solder mask layer covering a portion of the plurality of bump pads; and a plurality of dummy anchor plugs coupled beneath the bump pads....

20060076684 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the-creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second...

20060076685 - Selective capping of copper wiring: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided....

20060076686 - Method for manufacturing an electronic module, and an electronic module: This publication discloses an electronic module and a method for manufacturing an electronic module, in which a component (6) is attached to the surface of a conductive layer and electrical and electrical contacts are formed between the contact zones of the component (6) and the conductive layer. After this, an...

20060076687 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a...

20060076689 - Damascene processes for forming conductive structures: A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer...

20060076688 - Semiconductor device having improved contact hole structure and method for fabricating the same: A contact hole fabrication method for semiconductor device includes forming a dielectric layer on a semiconductor substrate, forming an antireflective layer on the dielectric layer, forming an amine source layer on the antireflective layer, forming a photoresist layer on the amine source layer, forming a first hole pattern having a...

20060076690 - Stacked die module: Semiconductor dies are stacked offset from one another so that terminals located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same direction. Electrical connections may connect terminals on one die with terminals on another die, and the...

20060076691 - chip bond layout for chip carrier for flip chip applications: A chip carrier for flip chip applications, according to the present invention, provides peripheral bumps and inner bumps. The inputs and outputs related to the inner bumps are routed out on an additional wiring layer by means of vias. The proposed bond layout provides a high I/O count for a...

20060076692 - Semiconductor package using flip-chip mounting technique: A semiconductor package using flip-chip mounting technique is disclosed. The semiconductor package includes: a semiconductor device provided with a plurality of first pads extending from the semiconductor device; a substrate provided with a plurality of second pads extending from the substrate at positions in registry with the location of the...

20060076693 - Self-releasing spring structures and methods: According to various exemplary embodiments, a spring device that includes a substrate, a self-releasing layer provided over the substrate and a stressed-metal layer provided over the self-releasing layer is disclosed, wherein an amount of stress inside the stressed-metal layer results in a peeling force that is higher than an adhesion...

20060076694 - Semiconductor device package with concavity-containing encapsulation body to prevent device delamination and increase thermal-transferring efficiency: A semiconductor device package has a concavity-containing encapsulation body to prevent device delamination and increase thermal-transferring efficiency. An encapsulation body of polymer-based material encapsulates a semiconductor device and bonding wires, and a concavity structure is patterned on the encapsulation body by imprinting, laser drilling, photolithography, dry etching, die sawing, or...

20060076695 - Semiconductor package with flash-absorbing mechanism and fabrication method thereof: A semiconductor package with flash-absorbing mechanism and a fabrication method thereof are proposed, wherein a flash-absorbing structure is formed on a gold-plated copper layer of a substrate, and adhesion between the flash-absorbing structure and a molding material is larger than that between the molding material and a mold, such that...

20060071204 - Resistive memory element: An electrically operated, resistive memory element includes a volume of resistive memory material, adapted to be switched between different detectable resistive states in response to selected enery pulses; means for delivering electrical signals to at least a portion of the volume of resistive memory material; and a volume of heating...

20060071205 - Nanocrystal switch: A switch comprises a set of electrodes with a nanocrystal channel disposed between the electrodes. The nanocrystal channel has bridges between conductive nanocrystals. A gate electrode is disposed above the nanocrystal channel and is insulated there from. Voltage applied to the gate can modulate electrical conductivity of the bridges between...

20060071206 - Palladium and platinum complexes: The invention relates to novel metallo-organic compounds which are phosphorescence emitters. Such compounds can be used as active components (functional materials) in a range of different applications which form part of the electronics industry in the broadest sense. The inventive compounds are described by the formulae (1), (1a), (2), (2a),...

20060071207 - Selective deposition of zno nanostructures on a silicon substrate using a nickel catalyst and either patterned polysilicon or silicon surface modification: Zinc-oxide nanostructures are formed by forming a pattern on a surface of a substrate. A catalyst metal, such as nickel, is formed on the surface of the substrate. Growth of at least one zinc oxide nanostructure is induced on the catalyst metal substantially over the pattern on the surface of...

20060071209 - Biopolymer resonant tunneling with a gate voltage source: The invention provides an apparatus and method for sequencing and identifying a biopolymer. The invention provides a first electrode, a second electrode, a first gate electrode, a second gate electrode, a gate voltage source and a potential means. The gate electrodes may be ramped by a voltage source to search...

20060071208 - Inspection methods and structures for visualizing and/or detecting specific chip structures: The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to “stain” a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process...

20060071210 - Semiconductor device and method of fabricating the same: It is an object of the present invention to manufacture a thin film transistor having a required property without complicating steps and devices. It is another object of the present invention to provide a technique for manufacturing a semiconductor device having high reliability and better electrical characteristics with a higher...

20060071211 - Bottom gate thin film transistor, flat panel display having the same and method of fabricating the same: A bottom gate thin film transistor (TFT), a flat panel display having the same, and a method of fabricating the same are disclosed. The TFT comprises a gate electrode disposed on a substrate, and a gate insulating layer disposed on the gate electrode. A semiconductor layer is disposed on the...

20060071212 - Thin film transistor array substrate, method for manufacturing the same, liquid crystal display having the substrate, and method for manufacturing the liquid crystal display: A liquid crystal display has, a plurality of pixel including a switching element, a plurality of gate lines extending transversally, a plurality of data lines extending longitudinally, a first storage electrode line extending transversally, a second storage electrode line extending longitudinally, a third storage electrode line connecting two of the...

20060071213 - Low temperature selective epitaxial growth of silicon germanium layers: The present invention relates generally to a method and means for growing strained or relaxed or graded silicon germanium (SiGe) layers on a semiconductor substrate using a selective epitaxial growth process. In particular, the present invention provides a method for epitaxially growing SiGe layers at temperatures lower than 600° C....

20060071214 - Process for manufacturing a semiconductor device, a semiconductor device and a high-frequency circuit: A process for manufacturing a semiconductor device, provides that a silicide layer is formed, an amorphous semiconductor layer is applied both to the silicide layer and to an open monocrystalline semiconductor region, adjacent to the silicide layer, and during a subsequent temperature treatment, the amorphous semiconductor layer is crystallized proceeding...

20060071215 - Semiconductor device and method of manufacturing the same: In a semiconductor device having a substrate which has a metal surface, an insulating film which is formed on the substrate having the metal surface, and a pixel unit which is formed on the insulating film; the pixel unit includes a TFT, and wiring lines connected with the TFT, and...

20060071216 - Thin film transistor having a short channel formed by using an exposure mask with slits: A mask containing apertures therein which is used for fabricating a channel of a thin film transistor (TFT), wherein the pixel charging time for a TFT in a high-resolution liquid crystal display (LCD) device is reduced by minimizing the length of the channel in the TFT when the active region...

20060071217 - Semiconductor device: A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first...

20060071219 - Monolithic array for solid state ultraviolet light emitters: The present invention is directed towards a source of ultraviolet energy, wherein the source is a UV-emitting LED's. In an embodiment of the invention, the UV-LED's are characterized by a base layer material including a substrate, a p-doped semiconductor material, a multiple quantum well, a n-doped semiconductor material, upon which...

20060071218 - Semiconductior multilayer structurehaving inhomogeneous quantum dots, light-emitting diode using same, semiconductor laser diode, semiconductor optical amplifier, and method for manufacturing them: A semiconductor multi-layered structure (1) having non-uniform quantum dots formed without requiring lattice strain is of a double hetero junction structure in which an active layer (3) has clad layers (5, 6, 16) laid on its opposite sides, wherein the clad layers are larger in forbidden band than the active...

20060071220 - Semiconductor package including light emitter and ic: The is to disclose a semiconductor package featuring inclusion of light emitter(s) providing light to indicate the states of the semiconductor package as a whole and/or the chip(s) therein. The light emitter is in an original state or flashing state or emitting state according to the states of the semiconductor...

20060071221 - Organic light emitting display and driving method thereof: An organic light emitting display and a driving method thereof, with an improved aperture ratio is disclosed. In one embodiment, the organic light emitting display comprises: a plurality of scan lines and a plurality of emission control lines, which are arranged in a horizontal direction; a plurality of data lines...

20060071222 - Led lamp for light source: Whereas incandescent light bulbs and other similar light sources known in the related art emit light in all directions, LED lamps can emit light in a single direction, and this is manifested in the problem of being unable to achieve light distribution characteristics satisfied by conventional headlamp designs. In accordance...

20060071223 - Light-emitting diode chip comprising a converter layer and method of making a light-emitting diode chip comprising a converter layer: Disclosed is a light-emitting diode chip comprising a semiconductor layer sequence suitable for emitting primary electromagnetic radiation and further comprising a converter layer that is applied to at least one main face of the semiconductor layer sequence and comprises at least one phosphor suitable for converting a portion of the...

20060071225 - Light emitting diodes exhibiting both high reflectivity and high light extraction: The invention is a light emitting diode that exhibits high reflectivity to incident light and high extraction efficiency for internally generated light. The light emitting diode includes a reflecting layer that reflects both the incident light and the internally generated light. A multi-layer semiconductor structure is deposited on the reflecting...

20060071226 - Light-emitting semiconductor device: A flip-chip type of Group III nitride based compound semiconductor light-emitting device comprises a transparent conductive film 10 made of ITO on a p-type contact layer. On the transparent conductive film, an insulation protection film 20, a reflection film 30 which is made of silver (Ag) and aluminum (Al) and...

20060071224 - Radiation-emitting semiconductor component: A radiation-emitting semiconductor component with a layer structure (12) which includes a photon-emitting active layer (16), an n-doped cladding layer (14) and a p-doped cladding layer (18), a contact connected to the n-doped cladding layer (14) and a mirror layer (20) connected to the p-doped cladding layer (18). The mirror...

20060071228 - Contact and omnidirectional reflective mirror for flip chipped light emitting devices: A light emitting device includes a substrate, a doped substrate layer, a layer of first conductivity type overlying the doped substrate layer, a light emitting layer overlying the layer of first conductivity type, and a layer of second conductivity type overlying the light emitting layer. A conductive transparent layer, e.g.,...

20060071229 - Integrated diode in a silicon chip scale package: An optical component with integrated back monitor photodiode. The optical component includes a substrate doped with a first type dopant, such as an n-type dopant. The substrate has a trench with sloped walls. An optical source is disposed in the trench. An implant of a second type dopant, such as...

20060071227 - System and method for active array temperature sensing and cooling: A system and method for active array temperature sensing and cooling. The system includes an active temperature sensing layer, a thermoelectric cooling layer and a heatsink layer. The temperature sensing layer is formed of temperature sensing elements that sense the temperature gradient across an unevenly heated region of the active...

20060071230 - Method of fabricating vertical structure leds: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate,...

20060071234 - Nitride semiconductor substrate and method of producing same: A nitride semiconductor substrate having a rugged surface being lapped by whetting granules to roughness between Rms5 nm and Rms200 nm, which has a function of reducing dislocations of a GaN, InGaN or AlGaN layer epitaxially grown on the lapped substrate by gathering dislocations in the epi-layer to boundaries of...

20060071231 - Optical film, backlight assembly having the same and display device having the same: An optical film includes a base layer, a resin layer and a plurality of hollow particles. The resin layer is disposed on a surface of the base layer. The hollow particles are disposed in the resin layer. The hollow particles each have an epidermis that defines an inner space of...

20060071233 - Organic light emitting device and method of manufacturing the same: An organic light emitting device (OLED) and a method for manufacturing the same are disclosed. In one embodiment, the OLED includes i) a pixel layer having a first electrode, a second electrode, and a light emitting portion interposed between the first electrode and the second electrode and having at least...

20060071232 - Semiconductor light emitting device having narrow radiation spectrum: Radiation occurs when current is injected into an active layer from electrodes. A pair of clad layers is disposed sandwiching the active layer, the clad layer having a band gap wider than a band gap of the active layer. An optical absorption layer is disposed outside at least one clad...

20060071235 - Lateral semiconductor diode and method for fabricating it: The invention relates to a lateral semiconductor diode, in which contact metal fillings (6, 7), which run in trenches (3, 4) in particular in a silicon carbide body (1, 2), are interdigitated at a distance from one another, and a rectifying Schottky or pn junction (18) is provided....

20060071237 - Circuit arrangement comprising a power component and a drive circuit integrated in two semiconductor bodies: A circuit arrangement comprises at least one power component and a drive circuit for the power component, which are integrated in a first and a second semiconductor chip. Only CMOS components of the drive circuit or CMOS components, capacitive components and resistance components of the drive circuit are integrated in...

20060071236 - Integrated circuit: The invention relates to an integrated circuit having a semiconductor component (10) comprising a first p-type region (12) and a first n-type region (11) adjoining the first p-type region (12), which together form a first pn junction having a breakdown voltage. According to the invention, a further n-type region adjoining...

20060071238 - Power module: A power module that includes a power circuit assembly in which power components are electrically and mechanically connected without wires....

20060071239 - Semiconductor device: A high capacity semiconductor device having a narrowed emitter layer. The semiconductor device includes a collector layer formed on a semiconductor substrate. An SiGe alloy layer is formed on the collector layer. A silicon film is formed on the SiGe layer. An emitter electrode is formed on the silicon film....

20060071240 - Integrated circuit with at least one bump: In an integrated circuit (1) having a substrate (3) and having a signal-processing circuit (4) which is produced at a surface (8) of the substrate (3), there is provided on the substrate surface (8) a protective layer (12) that has at least one aperture (13) through which a second contact...

20060071241 - Metal i/o ring structure providing on-chip decoupling capacitance: There are provided a metal I/O ring structure for a semiconductor chip and a decoupling capacitance structure using the same. In the Metal I/O ring structure, a plurality of first metal lines are formed on a first metal layer and connected with a power supply voltage, and a plurality of...

20060071242 - Vertical conduction power electronic device and corresponding realization method: A vertical conduction electronic power device includes respective gate, source and drain areas, realized in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be realized by a first metallization level. The gate, source and drain terminals or pads may be realized by...

20060071243 - Thin film transistor array substrate and manufacturing method thereof: A thin film transistor array substrate and manufacturing method thereof are provided. A shielding layer is formed between lead lines in a peripheral region of the substrate. The shielding layer and a gate layer may be formed simultaneously so that the light leakage between lead lines connected to a source/drain...

20060071244 - Switching or amplifier device, in particular transistor: t

20060071245 - Projection lens for light source arrangement: A light source arrangement for substantially enhaning the lighting intensity of the light beams emitted from the light source therefore includes a lens body and an illumination unit. The lens body has an illumination portion defining a light projecting surface and at least a diffraction portion defining a light diffraction...

20060071246 - Semiconductor device and sustaining circuit: At least two switching devices each including a substrate formed of a wide bandgap semiconductor, source and gate electrodes formed in a principal surface side of the substrate, and a drain electrode formed on the back surface of the substrate are stacked so that respective upper surface sides of the...

20060071247 - Reliable high-voltage junction field effect transistor and method of manufacture therefor: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a...

20060071248 - Spin polarization amplifying transistor: An embodiment of the invention is a transistor formed in part by a ferromagnetic semiconductor with a sufficiently high ferromagnetic transition temperature to coherently amplify spin polarization of a current. For example, an injected non-polarized control current creates ferromagnetic conditions within the transistor base, enabling a small spin-polarized signal current...

20060071249 - Low noise field effect transistor: An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower extremity of the source and drain regions so as to be spaced from the surface of the semiconductor body...

20060071250 - Iii-v power field effect transistors: A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured...

20060071253 - Photoelectric conversion device and imaging device: A photoelectric conversion device comprises: at least two electrodes; and an organic photoelectric conversion film intervening between said at least two electrodes, the organic photoelectric conversion film comprising a positive hole transporting material containing an arylidene compound having a specific structure....

20060071251 - Solid state image pickup apparatus and radiation image pickup apparatus: In a solid state image pickup apparatus with a photodetecting device and one or more thin film transistors connected to the photodetecting device formed in one pixel, a part of the photodetecting device is formed over at least a part of the thin film transistor, and the thin film transistor...

20060071252 - Solid-state imaging apparatus: Disclosed herein is a solid-state imaging apparatus including: a pixel section having a plurality of pixels disposed two-dimensionally in rows and columns, each pixel containing a photoelectric conversion section and an amplifying section for amplifying output of the photoelectric conversion section to output pixel signals; a first scanning section for...

20060071254 - High dynamic range image sensor: A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a dual purpose, acting as both a leaking transistor and either a transfer gate or a reset gate. Alternatively, the HDR transistor may...

20060071256 - Ferroelectric polymer memory device including polymer electrodes and method of fabricating same: A method of fabricating a ferroelectric memory module with conducting polymer electrodes, and a ferroelectric memory module fabricated according to the method. The ferroelectric polymer memory module includes a first set of layers including: an ILD layer defining trenches therein; a first electrode layer disposed in the trenches; a first...

20060071257 - Gate layer diode method and apparatus: Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a temperature compensated logic circuit and other on-chip temperature sensor applications....

20060071255 - Non-destructive read ferroelectric memory cell, array and integrated circuit device: A ferroelectric memory cell has a semiconductor substrate of a first conductivity type having a first region and a second region with each being of a second conductivity type, with a channel region therebetween. The first region and the second region are aligned in a first direction. A gate dielectric...

20060071258 - Semiconductor device: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a dielectric film provided on the bottom electrode, and a top electrode provided on the dielectric film, a mask film provided on the top electrode and used as a...

20060071259 - Charge-trapping memory cell and charge-trapping memory device: The memory cell is arranged in a ridge of semiconductor material forming a fin with sidewalls and a channel region between source and drain regions. Memory layer sequences provided for charge-trapping are applied to the sidewalls, and gate electrodes are arranged on both sides of the ridge. A plurality of...

20060071260 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate, an insulating film provided on the semiconductor substrate, the insulating film including an opening portion, a surface strap embedded in the opening portion, the surface strap comprising a semiconductor layer, a reaction preventing film provided on the surface strap, the reaction preventing film...

20060071261 - Integrated semiconductor storage with at least a storage cell and procedure: The invention relates to an integrated semiconductor memory with at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region and a region arranged between the first...

20060071262 - Metal-insulator-metal (mim) capacitor structure formed with dual damascene structure: A microelectronic product and a method for fabricating the same each provide a capacitor formed interposed between a first dielectric layer and a second dielectric layer formed over a substrate having a first contact region and a second contact region exposed therein. The capacitor is also connected to a first...

20060071263 - Dielectric thin film, dielectric thin film device, and method of production thereof: To provide a dielectric thin with a high dielectric constant, a low leakage current, and stable physical properties and electrical properties and to provide a thin film capacitor or other thin film dielectric device with a high capacitance and high reliability and a method of production of the same, a...

20060071264 - Non-volatile memory with asymmetrical doping profile: Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped...

20060071265 - Nonvolatile memory devices and methods of forming the same: A nonvolatile memory device includes first and second impurity diffusion regions formed in a semiconductor substrate, and a memory cell formed on a channel region of a semiconductor substrate between the first and second impurity diffusion regions. The memory cell includes a stacked gate structure formed on the channel region,...

20060071266 - Semiconductor memory and fabrication method for the same: A semiconductor memory includes memory cell transistors comprising a tunnel insulating film, a floating gate electrode, a first insulating film, a control gate electrode, and a first metal salicide film; low-voltage transistors comprising a first p-type source region and a first p-type drain region, a first gate insulating film, and...

20060071267 - Power semiconductor device: s

20060071268 - Shallow source mosfet: A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a...

20060071269 - High voltage mos transistor with up-retro well: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the...

20060071270 - Metal-oxide-semiconductor device having trenched diffusion region and method of forming same: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A...

20060071271 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second...

20060071272 - Programmable non-volatile resistance switching device: A memory element comprises a first number of electrodes and a second number of electrically conducting channels between sub-groups of two of said electrodes, the channels exhibiting an electrical resistance that is reversibly switchable between different states, wherein the first number is larger than two and the second number is...

20060071273 - Semiconductor device including an ldmos transistor: A semiconductor device 100 includes an LDMOS transistor which includes: a P-type silicon substrate 102; a gate electrode 120 formed on the P-type silicon substrate 102; a drain (a second N-type diffusion area 109) formed apart from the gate electrode 120 in the horizontal direction; a drain electrode 130 formed...

20060071274 - Method and structure for bonded silicon-on-insulator wafer: A bonded SOI wafer and a method for forming a bonded SOI wafer are provided. According to the disclosed method, a first semiconductor wafer is provided, having a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the...

20060071275 - Nonplanar transistors with metal gate electrodes: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of...

20060071276 - Field effect trench transistor: One embodiment of the invention relates to a field effect trench transistor with a multiplicity of transistor cells that are arranged like an array and whose gate electrodes are arranged in active trenches formed in a semiconductor body. Inactive trenches are arranged in the array of the transistor cells, there...

20060071277 - Apparatus and method for breakdown protection of a source follower circuit: A breakdown protection circuit for a source follower comprising a field effect transistor (FEI). The protection circuit comprises a plurality of PFET's and NFET's that are controlled to exhibit on and off states for advantageously configuring a gate, source, drain and body of the source follower FET, to avoid breakdown...

20060071278 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a well 58 formed in a semiconductor substrate 10 and having a channel region; a gate electrode 34n formed over the channel region with an insulating film 32 interposed therebetween; source/drain regions 60 formed in the well 58 on both sides of the gate electrode 34n,...

20060071279 - Semiconductor device, method of manufacturing semiconductor substrate, and method of manufacturing semiconductor device: A semiconductor device includes a semiconductor substrate that has an oxide film selectively formed on a part thereof; a semiconductor layer that is formed on the oxide film by epitaxial growth; a first gate electrode that is formed on the semiconductor layer; first source/drain layers that are formed on the...

20060071280 - Semiconductor diode, electronic component, voltage source inverter and control method: The invention relates to a semiconductor diode, an electronic component and to a voltage source converter. According to the invention, the semiconductor diode having at least one pn-transition can be switched between a first state and a second state. In comparison to the first state, the second state has a...

20060071281 - Integrated circuit and method for manufacturing: A semiconductor structure, fluid ejection device, and methods for manufacturing the same are provided, such that a contact to a substrate is formed from a conductive layer....

20060071282 - Semiconductor device and manufacturing method thereof: A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of a n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide film....

20060071283 - Thick oxide region in a semiconductor device and method of forming same: A method of forming an oxide region in a semiconductor device includes the steps of forming a plurality of trenches in a semiconductor layer of the device, the trenches being formed in close relative proximity to one another, and oxidizing the semiconductor layer such that an insulating layer is formed...

20060071284 - Easily crack checkable semiconductor device: A semiconductor device includes a first insulation film, a second insulation film, a thin film resistor interposed between the insulation films. A predetermined voltage is applied to the thin film resistor so that a current flows through the thin film resistor. When a crack occurs in the insulation films, the...

20060071285 - Inducing strain in the channels of metal gate transistors: In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient...

20060071286 - Polymeric piezoresistive sensors: A MEMS system, such as a biosensor, includes a micromechanical resonator and a piezoresistive sensing element which includes an organic semiconductor, such as an organic thin film transistor....

20060071287 - Magnetoresistance effect element, magnetic head and magnetic reproducing apparatus: In a spin valve type element, an interface insertion layer (32, 34) of a material exhibiting large spin-dependent interface scattering is inserted in a location of a magnetically pinned layer (16) or a magnetically free layer (20) closer to a nonmagnetic intermediate layer (18). A nonmagnetic back layer (36) may...

20060071288 - Small-gap light sensor: A sensor having a light detector with a small gap between the cathode and anode to enable a high pressure cavity resulting in a long lifetime of the detector due to insignificant sputtering from the cathode and subsequent minimal burying of the noble gas in the cavity. The detector may...

20060071289 - Lead frame and light receiving module comprising it: On a leadframe on which to fix a photodetector element, an element mount frame and a fitting frame are laid with a gap left in between. A shielding frame for electromagnetically shielding the photodetector element is tied, via a tying portion, not to the element mount frame but to the...

20060071290 - Photogate stack with nitride insulating cap over conductive layer: A photogate structure having increased quantum efficiency, especially for low wavelength light such as blue light. The photogate is formed of a thin conductive layer, such as a layer of doped polysilicon. A nitride insulating cap is formed over the conductive layer. The nitride layer reduces the reflections at the...

20060071291 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate, and a MOS transistor provided on the semiconductor substrate and having a channel type of a first conductivity, the MOS transistor comprising a semiconductor region of the first conductivity type including first and second channel regions, gate insulating films provided on the first...

20060071292 - Reduced guard ring in schottky barrier diode structure: Schottky barrier diodes use a dielectric separation region to bound an active region. The dielectric separation region permits the elimination of a guard ring in at least one dimension. Further, using a dielectric separation region in an active portion of the integrated circuit device may reduce or eliminate parasitic capacitance...

20060071293 - Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same: An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on...

20060071295 - High voltage fet switch with conductivity modulation: A high power FET switch comprises an N− drift layer, in which pairs of trenches are recessed to a predetermined depth; oxide side-walls extend to the trench bottoms, and each trench is filled with a conductive material. N+ and metal layers on opposite sides of the drift layer provide drain...

20060071294 - Semiconductor device channel termination: A semiconductor device has a channel termination region for using a trench (30) filled with field oxide (32) and a channel stopper ring (18) which extends from the first major surface (8) through p-well (6) along the outer edge (36) of the trench (30), under the trench and extends passed...

20060071296 - Rf passive circuit and rf amplifier with via-holes: An input matching parallel inductor 114 which utilizes a spiral inductor, and an input matching parallel capacitor 115 which utilizes an MIM capacitor, both being constituting elements of an input matching circuit portion 125, form an input matching parallel capacitor 115 inside an input matching circuit via-hole 121 being formed...

20060071297 - Device with integrated capacitance structure: Device with integrated capacitance structure The present invention relates to a device with integrated capacitance structure has at least one first and an adjacent second rewiring plane, each of which comprises at least one first partial structure and a second partial structure, which is different from the first partial structure,...

20060071298 - Polysilicon memory element: A memory element may be formed from a polysilicon PN junction. In one state, the junction exhibits the characteristics of a diode. After exposure to a reverse bias breakdown voltage, the junction may exhibit the characteristics of a resistor. Thus, two different states may be detected by determining the characteristics...

20060071299 - Independently accessed double-gate and tri-gate transistors in same process flow: An independent access, double-gate transistor and tri-gate transistor fabricated in the same process flow is described. An insulative plug is removed from above the semiconductor body of the I-gate device, but not the tri-gate device. This allows, for instance, metalization to form on three sides of the tri-gate device, and...

20060071300 - Dielectric material having carborane derivatives: Numerous embodiments of an apparatus and method of a dielectric material having a low dielectric constant and good mechanical strength are described. In one embodiment a dielectric material having multiple porous regions is disposed over a substrate. A caged structure is bridged within the plurality of pores. In one particular...

20060071301 - Silicon rich dielectric antireflective coating: A light absorption layer for use in fabricating semiconductor devices is provided with a high Si concentration. For example, a semiconductor device comprises a substrate and an Si-rich dielectric light absorption layer, such as an SiON or SiOX layer having an Si concentration of at least 68%. A second dielectric...

20060071302 - Fluid injection devices and fabrication methods thereof: Fluid injection devices and fabrication methods thereof. A first structural layer is disposed on a substrate. A fluid chamber is disposed between the substrate and the first structural layer. At least one bubble generator is disposed on the first structural layer and on the opposite side of the fluid chamber....

20060071303 - Film substrate of a semiconductor package and a manufacturing method: Embodiments of the present invention are directed to a film substrate of a semiconductor package. The film substrate of the semiconductor package comprises a thin film insulating substrate and a thin copper circuit pattern. An inter-pattern groove between the thin copper circuit patterns is formed by laser etching. Accordingly, the...

20060071304 - Structure and layout of a fet prime cell: A structure, apparatus and method for a FET prime cell surrounded by a conductor is provided. The surrounding conductor includes a substrate contact arranged proximate a source of the FET. The surrounding conductor may be a ring substrate contact arranged within the substrate of the FET in electrical communication with...

20060071306 - Active device bases, leadframes utilizing the same, and leadframe fabrication methods: Active device bases, leadframes utilizing the same, and leadframe fabrication methods. The base includes a plate, a predetermined attachment area for an active device on a surface of the plate, and a recess in the predetermined attachment area, which substantially does not penetrate the plate....

20060071305 - Electrical package structure including chip with polymer thereon: An electrical package structure incorporating a chip with polymer thereon is described, including at least a package, a polymer and a molding compound. The package includes a carrier, at least one chip and multiple wires, wherein the chip is disposed on the carrier and the wires electrically connect the chip...

20060071307 - Lead frame and semiconductor package therefor: A lead frame is produced using a thin metal plate to form a stage for mounting a semiconductor chip, a plurality of leads encompassing the stage, and a frame portion for fixing the stage and leads together. Surfaces of the internal ends of the leads are each expanded in a...

20060071308 - Apparatus of antenna with heat slug and its fabricating process: An apparatus of antenna with heat slug and its fabricating process are provided, in which the antenna with heat slug can be realized with a single sheet or double sheets of metal. A dual-band antenna module with a mask cover is taken as an example to realize the apparatus. Each...

20060071309 - Semiconductor device: The present invention provides inhibiting an electrical leakage caused by anion migration. A trenched portion 15 is provided as ion migration-preventing zone between a source electrode 4 and a gate electrode 5. The trenched portion 15 is formed so as to surround a periphery of the source electrode 4....

20060071310 - Semiconductor lead frame, semiconductor package having the same, and method of plating the same: Provided are a semiconductor lead frame, a semiconductor package having the semiconductor lead frame, and a method of plating the semiconductor lead frame. The method includes preparing a substrate formed of a Fe—Ni alloy (alloy 42), and a plating layer that contains grains less than 1 micrometer in size and...

20060071312 - Semiconducting device that includes wirebonds: Some embodiments relate to a semiconducting device that includes a substrate, a die and an interconnect device. The die and interconnect device are attached to an upper surface of the substrate. The semiconducting device further includes a first wire that is bonded to the substrate and to the interconnect device...

20060071311 - Surface-mounted microwave package and corresponding mounting with a multilayer circuit: The invention relates to a microwave package delimiting an interior volume, comprising: a Faraday cage formed by a conducting surface surrounding the interior volume, a connection point placed outside the Faraday cage, the connection point being intended to be linked electrically to an exterior circuit, an input-output passing through the...

20060071313 - Memory card and method of fabricating the same: A memory card. The memory card comprises a substrate, a plurality of electronic package devices, a molding compound and a plastic forming material. The substrate has at least a plurality of outer contacts and a plurality of inner contacts and the outer contacts are electively connected to the inner contacts....

20060071314 - Cavity-down stacked multi-chip package: A cavity-down stacked multi-chip package with a plurality of packages stacked together is provided. The uppermost package has a circuit board with an opening, a heat spreader, and a chip. The heat spreader is positioned on the circuit board and covers the opening. The chip is positioned in the opening...

20060071315 - Method of forming a stacked semiconductor package: A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface...

20060071318 - Methods for manufacturing semiconductor device, semiconductor device and metal mold: A method for manufacturing a semiconductor device including: fixing each of a plurality of semiconductor substrates onto a surface of a wiring substrate in which a perforation is formed in advance; covering the surface of the wiring substrate with a metal mold having a protrusion on an inner surface along...

20060071317 - Multi-chip package and method for manufacturing the same: A multi-chip package and method for manufacturing are disclosed. The multi-chip package may include a substrate, a lower semiconductor chip mounted on the substrate, a first electrical connection for electrically connecting the substrate and the lower semiconductor chip, an upper semiconductor chip attached to the lower semiconductor chip and having...

20060071316 - Three-dimensional stack manufacture for integrated circuit devices and method of manufacture: An integrated circuit package assembly formed by stacking flip-chip mounted substrates interleaved with precisely dimensioned spacers and then bonded by injection molding the stack. The sides of the stack are sawed off to expose vias in the substrates, and multilevel-interconnect substrates are precisely aligned on the sides of the stack....

20060071320 - Semiconductor device: Fine-pitch first and second bonding pads are formed on a chip along its perimeter. The first bonding pads are formed at the peripheral parts on the chip, while the second bonding pads are formed inside the peripheral parts. An ESD protection circuit is connected to the first bonding pad, and...

20060071319 - Semiconductor integrated circuit: In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply wire to the lower cell power-supply wire. The supplementary power-supply wire...

20060071322 - Automatic trace determination method and apparatus for automatically determining optimal trace positions on substrate using computation: An automatic trace determination apparatus for automatically determining optimal positions of traces from pads to corresponding vias on a substrate using computation comprises: tentative determination means for tentatively determining a tentative target line with which tentative positions of bending points of traces are aligned; and final determination means for determining...

20060071321 - Resin molded semiconductor device and mold: To provide an excellent image by reducing buckling of a CCD device having one-dimensional CCD elements mounted thereon due to changes in temperature. Blackening treated iron or iron-based alloy is used as a material of a heat sink 11 having a one-dimensional CCD element 14 mounted thereon. The thermal coefficient...

20060071323 - Method for processing a thin film substrate: The present invention comprises a processed thin film substrate (10) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing through the thin film substrate and electrically connected along faced-away surfaces, in order to form an electric circuit. A...

20060071324 - Microelectronic package having chamber sealed by material including one or more intermetallic compounds: Microelectronic packages having chambers and sealing materials, and methods of making the packages, and sealing the chambers, are disclosed. An exemplary package may include a first surface, a second surface, a solid sealing material including an intermetallic compound, such as, for example, of gallium or another relatively low melting material,...

20060071325 - Semiconductor device and electronic apparatus: A semiconductor device is provided with a heat dissipation metal plate which improves heat dissipation performance in heat generating members of a semiconductor element and the like. In particular, the heat dissipation metal plate is placed on a surface of an insulating film, the surface being located on an opposite...

20060071326 - Integrated micro channels and manifold/plenum using separate silicon or low-cost polycrystalline silicon: A method and apparatus for cooling an electronics chip with a cooling plate having integrated micro channels and manifold/plenum made in separate single-crystal silicon or low-cost polycrystalline silicon. Forming the microchannels in the cooling plate is more economical than forming the microchannels directly into the back of the chip being...

20060071327 - Construction to improve thermal performance and reduce die backside warpage: A semiconductor package construction aimed at improving thermal performance. A heatspreader is provided having a metal alloy preform attached to it already. Then, a few dots of conductive epoxy are dispensed around the die. The heatspreader with the preformed metal alloy is pressed on the adhesive and then the part...

20060071328 - Semiconductor substrate structure: A semiconductor substrate structure with a highly heat-conductive advantage increases packaging good rate and quality. Using semiconductor chip packaging, an electronic chip is easily made highly heat-conductive, and compared with the prior art, the present invention has superior good rate for substrate structure. The improved heat-conductive structure avoids the semiconductor...

20060071329 - Power led package: In a chip package (10, 10′, 110, 210), first and second electrical power buses (14, 14′, 16, 16′, 114, 116, 214, 216) are each formed of an electrical conductor having a chip bonding portion (20, 22, 120, 122, 220, 222) and a lead portion (26, 26′, 28, 28′, 126, 128,...

20060071330 - Semiconductor package: A semiconductor package which is multifunctional, thin, and high in mounting reliability includes an insulating film; a first electronic component formed on one of the main surfaces of the insulating film; a second electronic component formed outwardly on the other of the main surfaces opposite to the one of the...

20060071331 - Semiconductor device carrier unit and semiconductor socket provided therewith: In a pressing cap forming part of a semiconductor device carrier unit, a pressing portion of a pressure body has recesses, to each of which a bump is inserted....

20060071332 - Face-to-face bonded i/o circuit die and functional logic circuit die system: An integrated circuit system includes a first set of integrated circuit dice each member of the set having a different configuration of input/output circuits disposed thereon and a second set of integrated circuit dice each having different logical function circuits disposed thereon. Each member of the first and second sets...

20060071333 - Packaging substrate and semiconductor device: A packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate and comprises a wiring provided on a bonding surface to which the...

20060071334 - Carbon nanotube structure, a semiconductor device, a semiconductor package and a manufacturing method of a semiconductor device: A semiconductor device uses a carbon nanotube structure, which reduces an electric resistance and a thermal resistance by increasing a density of the carbon nanotubes. An insulation film covers a first electrically conductive material. A second electrically conductive material is provided on the insulation film. A plurality of carbon nanotubes...

20060071335 - Semiconductor device using multi-layer unleaded metal plating, and method of manufacturing the same: A semiconductor device comprises a semiconductor integrated circuit, an external connection terminal connecting the semiconductor integrated circuit to an external device, and a plurality of tin or tin-alloy plating layers formed on the external connection terminal as multiple unleaded metal plating layers. The multiple unleaded metal plating layers comprise a...

20060071336 - Copper interconnect: An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of...

20060071337 - Underfill material to reduce ball limiting metallurgy delamination and cracking potential in semiconductor devices: An electronic structure includes an electronic device coupled to a substrate by conductive bumps and ball limiting metallurgy (BLM). Underfill material having filler particles is disposed in a space between the electronic device and the substrate. A weight percentage of the filler particles is at least about 60%. A particle...

20060071338 - Homogeneous copper interconnects for beol: Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer. The impure copper seed layer covers a barrier layer, which covers an insulating layer that has an opening. Electroplated copper fills the opening...

20060071339 - Semiconductor device, wafer and method of designing and manufacturing the same: A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interconnect) is disposed in a same orientation such that...

20060071340 - Methods to deposit metal alloy barrier layers: Metal alloy barrier layers formed of a group VII metal alloyed with boron (B) and/or phosphorous (P) and an at least one element from glyoxylic acid, such as carbon (C), hydrogen (H), or carbon and hydrogen (CH) formed by electoless plating are described. These barrier layers may be used as...

20060071341 - Array capacitor apparatuses to filter input/output signal: An apparatus for filtering noise from an input/output (I/O) signal is disclosed. In various embodiments, the apparatus may be an array capacitor, and may be disposed between an electronic package and an underlying substrate such as a printed circuit board....

20060071343 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device is configured of a semiconductor chip which is sandwiched by first and second resin films having a wiring pattern. Plural semiconductor chips can be fabricated collectively by sandwiching the semiconductor chips by the first and second resin films, and productivity can be improved....

20060071342 - Semiconductor device manufacturing method of the same: The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention layer for preventing an insulation film and a protection layer peeling is formed in corner portions of the semiconductor device. The peeling...

20060071344 - Wiring connection structure and method for forming the same: Disclosed is a wiring connection structure comprising a wiring on which a preferable carbon nanotube can be formed, and a method for forming the same. On a lower layer Cu wiring, Mo is deposited to form a connection layer. On this connection layer, a carbon nanotube is grown using a...

20060071345 - Copper interposer for reducing warping of integrated circuit packages and method of making ic packages: A stacked die integrated circuit assembly comprising: 1) a substrate; 2) a first integrated circuit die mounted on the substrate; 3) a copper interposer mounted on the first integrated circuit die; and 4) a second integrated circuit die mounted on the copper interposer. The copper interposer significantly reduces the warping...

20060071346 - Semiconductor device and manufacturing method thereof: A semiconductor device, includes: a circuit board having an inner terminal on one surface, an outer terminal on the other surface, and wiring between the inner terminal and the outer terminal; a semiconductor chip flip-chip bonded to the inner terminal against the circuit board; and a sealing resin covering the...

20060071347 - Semiconductor device and fabrication method thereof: In a semiconductor device and a fabrication method thereof according to the present invention, a second insulating film is formed on a second surface of a semiconductor substrate whose first surface has been formed with a first insulating film and an electrode pad, and an opening is made in a...

20060071348 - Increasing the adhesion of an adhesive connection in housings: A housing having a non-detachable bond to a micromechanical component using a flexible bonding material in particular. The combination including the housing and the micromechanical component as well as the manufacturing method of this combination. At least part of the component and/or of the housing has depressions for receiving the...

20060071349 - Semiconductor device and semiconductor device unit: A semiconductor device, comprising: a flexible substrate; at least one semiconductor element; at least one electrode for external connection, the element and the electrode being formed on a front surface of the flexible substrate; and at least one wire formed on the front surface to electrically connect the element to...

20060071350 - Structure and method for fabricating a bond pad structure: A structure and method for an improved a bond pad structure. We provide a top wiring layer and a top dielectric (IMD) layer over a semiconductor structure. The buffer dielectric layer is formed over the top wiring layer and the top dielectric (IMD) layer. We form a buffer opening in...

20060071351 - Mold compound interlocking feature to improve semiconductor package strength: A semiconductor package comprising a chip, a die pad adjacent the chip, said die pad having a side facing away from the chip, a portion of said side separated from an adjacent package surface by a distance greater than zero. The package further comprises mold compound abutting the chip and...

20060071352 - Thin film transistors and methods of manufacture thereof: A polycrystalline silicon GOLDD TFT with a gate (10) overlying its channel (11) is fabricated by using the gate (10) as a mask during a first dopant implantation step. Spacers (13, 14) are then formed adjacent to the gate (10), which comprise portions of a thin metallic layer (19) which...