Active solid-state devices (e.g., transistors, solid-state diodes) inventions 03/06

20060065886 - Semiconductor apparatus for white light generation and amplification: The present invention is a semiconductor apparatus for white light generation and amplification, where, under different current bias, white light can be generated steadily and evenly by folding up multi-wavelength quantum wells and by side-injecting a current. And, the white light can be excited out electronically without mingling with a...

20060065887 - Carbon nanotube-based electronic devices made by electrolytic deposition and applications thereof: Carbon nanotube-based devices made by electrolytic deposition and applications thereof are provided. In a preferred embodiment, the present invention provides a device comprising at least one array of active carbon nanotube junctions deposited on at least one microelectronic substrate. In another preferred embodiment, the present invention provides a device comprising...

20060065889 - Compositions for making organic thin films used in organic electronic devices: An organic electronic layer is formed using a monomer dissolved in a solvent such as formic acid. The solution is oxidized with the aid of an oxidizing agent, chosen such that there are no ionic byproducts resulting therefrom. Additives such as polyacids, acids, salts and electrolytes may be added to...

20060065888 - Organic semiconductor diode: The present invention relates to organic semiconductor diodes, in particular, to the diodes with nonlinear current-voltage characteristics, which are used for power switching, rectifying variable signals, and frequency mixing. The organic semiconductor diode with the p-n junction comprises an anode, cathode, a hole transport layer in contact with the anode,...

20060065890 - Rhodium and iridium complexes: The present invention describes novel organometallic compounds which are phosphorescence emitters. Such compounds can be used as active components (=functional materials) in a series of different types of application which can be classed within the electronics industry in the broadest sense. The compounds according to the invention are described by...

20060065891 - Zener zap diode structure compatible with tungsten plug technology: A zener zap device is formed in a fabrication process using a tungsten plug process having standard sized contact openings. The zener zap device includes first and second regions of opposite conductivity types formed in a semiconductor layer. A dielectric layer overlaying the surface of the semiconductor layer includes first...

20060065892 - Thin film transistor array panel and manufacturing method therefor: A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be...

20060065893 - Method of forming gate by using layer-growing process and gate structure manufactured thereby: Provided are a method of forming a gate by using layer growth, and a gate structure formed thereby. A gate dielectric layer and a seed layer are sequentially formed on a substrate, and then a mask is used to selectively grow a gate layer on the seed layer. An exposed...

20060065895 - Image display device: An interlayer insulator with a low taper angle is formed as a laminated film in which a silicon nitride film is formed on a silicon oxide film formed on the glass substrate side (field insulator side). Thus, an upper electrode of a cathode formed on the interlayer insulator is prevented...

20060065894 - Thin film transistor array panel and manufacturing method thereof: A thin film transistor array panel is provided, which includes a substrate having a display area and driver, a polysilicon layer formed on the substrate and including channel, source, and drain regions, and lightly doped regions disposed between the channel region and the source and drain regions, and having an...

20060065896 - Cmos solid-state imaging device and method of manufacturing the same as well as drive method of cmos solid-state imaging device: Adjacent pixels 2A and 2B are separated by element isolation portion 82 formed of a diffusion layer 43 and an insulating layer 44 thereon, and the insulating layer 44 of the element isolation portion 82 is formed in a position equal to or shallower than the position 45j of a...

20060065897 - Pattern formed structure, method of forming pattern, device, electrooptical device and electronic equipment: A partition-wall structure having a concave portion corresponding to a pattern formed by a functional liquid, including: a first concave portion provided corresponding to a first pattern; a second concave portion provided corresponding to a second pattern that is coupled to the first pattern and whose width is smaller than...

20060065898 - Semiconductor device and method of manufacturing the same: In a semiconductor device in which a group III nitride compound semiconductor layer is formed without a low temperature grown buffer layer provided on an undercoat layer formed by a metal nitride layer, the metal nitride layer is formed of reddish brown titanium nitride. The reddish brown titanium nitride can...

20060065899 - Semiconductor device: A semiconductor device includes an SiC substrate, a normal direction of the substrate surface being off from a <0001> or <000-1> direction in an off direction, an SiC layer formed on the SiC substrate, a junction forming region formed in a substantially central portion of the SiC layer, a junction...

20060065900 - Liquid crystal display: A liquid crystal display having a backlight module, liquid crystal layer and a color filter layer is disclosed in the invention. An ultraviolet unit for emitting ultraviolet is disposed in the backlight module. The color filter layer is composed of a purity of pixels, and at least one of the...

20060065901 - Migration-proof light-emitting semiconductor device and method of fabrication: An LED has a light-generating semiconductor region formed on an electroconductive baseplate via a reflector layer of silver or silver-base alloy. The light-generating semiconductor region has an active layer between claddings of opposite conductivity types. An anti-migration sheath envelopes either or both of the reflector layer and light-generating semiconductor region...

20060065902 - Refractive index changing apparatus and method: Refractive index changing apparatus includes quantum dots each having discrete energy levels including ground level and excited level, the excited level being higher than the ground level even if energy due to ambient temperature is provided on the quantum dots, barrier structure unit formed of dielectric which surrounds the quantum...

20060065903 - Electro-optical device, image forming apparatus, and image reader: An electro-optical device includes a substrate, a plurality of self-emitting elements formed in the substrate, a sealing member attached to the substrate so as to seal the self-emitting elements in cooperation with the substrate, and a circuit that is disposed to overlap the sealing member and that drives or controls...

20060065904 - Display: A display includes pixels each of which contains a light emitting element and which are arranged in a matrix form, a light transmitting insulating layer which includes a back surface facing the light emitting element and a front surface as a light output surface, a beam-condensing element which is arranged...

20060065905 - Semiconductor component and production method: A semiconductor component having a light-emitting semiconductor layer or a light-emitting semiconductor element, two contact locations and a vertically or horizontally patterned carrier substrate, and a method for producing a semiconductor component are disclosed for the purpose of reducing or compensating for the thermal stresses in the component. The thermal...

20060065906 - Method for manufacturing and semiconductor light emitting device: A method for manufacturing a semiconductor light emitting device can include providing a housing having a cavity and a power feed line, a light emitting element connected to the power feed line on a bottom face of the cavity, and a wavelength conversion layer provided within the cavity and containing...

20060065907 - White light emitting device and manufacturing method thereof: A white light emitting device (LED) and a manufacturing method thereof wherein an LED coated with polymeric resin in which organic phosphors are solved and inorganic phosphors are dispersed creates a white LED, thereby producing an effect of excellent luminance and color coordinate without creating a compatibility problem with the...

20060065908 - Iii-nitride multi-channel heterojunction interdigitated rectifier: A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions....

20060065911 - Electronic device and heterojunction fet: In an electronic device of the present invention a gate Schottky electrode is formed on an active layer constructed of a GaN layer and an AlGaN layer, and a source ohmic electrode and a drain ohmic electrode are further formed on both sides of the gate Schottky electrode on the...

20060065910 - Method of forming vias in silicon carbide and resulting devices and circuits: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for...

20060065909 - Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed thereby: Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer,...

20060065912 - Non-planar iii-nitride power device having a lateral conduction path: A III-nitride power semiconductor device that includes a heterojunction body with a stepped profile....

20060065913 - Semiconductor device with double barrier film: A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has...

20060065914 - Structure and method for making strained channel field effect transistor using sacrificial spacer: A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides...

20060065915 - Sold-state imaging devices: A solid-state imaging device includes: a substrate; a photoelectric transducer that is provided within the substrate and generates light-generated charge in accordance with incident light; a floating diffusion that retains the light-generated charge generated from the photoelectric transducer; a transfer and retention unit that is provided between the photoelectric transducer...

20060065917 - Hybrid memory device and method for manufacturing the same: A hybrid memory device includes a plurality of regions including a memory cell array region upon which are formed a plurality of memory cells and a logic circuit region upon which is formed a logic circuit device, and is provided with a liner oxide layer formed on a region covering...

20060065916 - Varactors and methods of manufacture and use: In an embodiment of the present invention is provided a varactor, comprising: a bottom electrode supported by a substrate; a tunable dielectric in contact with said bottom electrode and in contact with a top electrode; and an interconnect in contact with said top electrode and capable of being in contact...

20060065918 - Semiconductor device and method of fabricating the same: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first...

20060065919 - Nonvolatile memory device and method for producing the same: To provide a nonvolatile memory device suppressing a reduction of a data retention characteristic even if charges injected and stored into a local area of a nitride film is redistributed to achieve a reduction of voltage, the nonvolatile memory device in which hot electrons are injected into the local area...

20060065920 - Semiconductor memory device and method for producing the same: Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a...

20060065921 - Non-volatile semiconductor memory device: Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks....

20060065922 - Semiconductor memory with vertical charge-trapping memory cells and fabrication: A semiconductor device is formed by forming a plurality of trenches in a semiconductor body. The trenches alternate between active trenches and isolation trenches with the isolation trenches being deeper than the active trenches. The semiconductor body is doped so that a top surface of the semiconductor body adjacent each...

20060065923 - High-voltage-resistant semiconductor component having vertically conductive semiconductor body areas and a trench structure: A high-voltage-resistant semiconductor component (1) has vertically conductive semiconductor areas (17) and a trench structure (5). These vertically conductive semiconductor areas are formed from semiconductor body areas (10) of a first conductivity type and are surrounded by a trench structure (5) on the upper face (6) of the semiconductor component....

20060065924 - Semiconductor device containing dielectrically isolated pn junction for enhanced breakdown characteristics: A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and...

20060065925 - Vertical mosfet: A vertical MOSFET includes a gate electrode formed inside a trench in a semiconductor layer, an interlayer insulating film formed above the semiconductor layer, a source electrode formed above the interlayer insulating film and electrically connected to a source region of the semiconductor layer through a conductive plug filled in...

20060065926 - Insulated gate semiconductor device and manufacturing method of the same: A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed...

20060065927 - Double gate device having a heterojunction source/drain and strained channel: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material...

20060065928 - Semiconductor device: The invention provides a semiconductor apparatus capable of achieving a device having a snap-back resisting pressure of about 5 to 10 V by a self-aligning process. The semiconductor apparatus includes two or more sub-gates placed next to a main gate at a predetermined interval, and low concentration layers placed continuously...

20060065929 - Nitride based semiconductor device and method for manufacturing the same: Provided is a nitride-based semiconductor device in which a SAW filter and a HFET are integrated on a single substrate, as well as a method for manufacturing the same. The nitride-based semiconductor device comprises a semi-insulating GaN layer formed on a substrate, a plurality of electrodes for a SAW filter...

20060065930 - Growing [110] silicon on [001]-oriented substrate with rare-earth oxide buffer film: An assembly and method of making the same wherein the assembly incorporates a rare-earth oxide film to form a [110] crystal lattice orientation semiconductor film. The assembly comprises a substrate, a rare-earth oxide film formed on the substrate, and a [110]-oriented semiconductor film formed on the rare-earth oxide film. The...

20060065932 - Circuit to improve esd performance made by fully silicided process: An electrostatic discharge (ESD) protection circuit is provided. The circuit is coupled between a first and a second node for dissipating an ESD current. The circuit comprises a first transistor formed on a substrate with its gate and a first diffusion region coupled to the first node for receiving the...

20060065933 - Esd protection circuit with floating diffusion regions: This invention discloses an electrostatic discharge (ESD) protection circuit that comprises a substrate of a predetermined type, at least one MOS transistor being coupled to a pad of an integrated circuit for dissipating an ESD current from the pad during an ESD event, a substrate contact region, and at least...

20060065931 - Esd protection for high voltage applications: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and...

20060065934 - Semiconductor device and method for manufacturing the same: A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface...

20060065935 - Patterned backside stress engineering for transistor performance optimization: Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance....

20060065936 - Multiple doping level bipolar junctions transistors and method for forming: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for...

20060065937 - Short channel effect of mos devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regions: A method of providing a halo implant region in a substrate of a MOS device having a gate electrode thereon and defining source/drain regions, a MOS device fabricated according to the above method, and a system comprising the MOS device. The method comprises: defining undercut recesses in the substrate at...

20060065938 - Method and system for forming a feature in a high-k layer: A method for plasma processing a high-k layer includes providing a substrate having a high-k layer formed thereon, on a substrate holder in a process chamber, and creating a plasma in the process chamber to thereby expose the high-k layer to the plasma. RF power is applied to the substrate...

20060065939 - Metal gate electrode semiconductor device: A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer...

20060065940 - Analog interferometric modulator device: Disclosed is new architecture of microelectromechanical system (MEMS) device. The device has a partially reflective optical layer, a deformable mechanical layer and a mirror layer, each of which forms an independent electrode. A support post separates the optical layer from the mechanical layer. The mirror layer is located and movable...

20060065941 - Encapsulation component for integrated micro electromechanical systems and fabrication process of the component: The microsystems are integrated in a first cavity bounded by at least a substrate and by a top wall formed by at least a part of a first cover. The component has a second cavity bounded by at least the whole of the top wall of the first cavity and...

20060065942 - Mechanism to prevent actuation charging in microelectromechanical actuators: According to one embodiment a microelectromechanical (MEMS) switch is disclosed. The MEMS switch includes a top movable electrode, and an actutaion electrode with an undoped polysilicon stopper region to contact the top movable electrode when an actuation current is applied. The undoped polysilicon stopper region prevents actuation charging that accumulates...

20060065943 - Thin film alternating current solid-state lighting: Group IV semiconductor nanocrystal doped with rare earths or other light emitting metal to form alternating current solid-state devices that can be designed to operate at a variety of voltages including line voltages. The semiconductor nanocrystals are preferably silicon, silicon carbide, germanium or germanium carbide, and the electric luminescent device...

20060065944 - Image pickup apparatus and radiation image pickup apparatus: To improve a sensor resetting method and thereby implement a high rate at which a moving image is read, the invention provides an image pickup apparatus and a radiation image pickup apparatus including: a plurality of pixels arranged on a substrate in row and column directions, each pixel having a...

20060065945 - Chemical sensor using chemically induced electron-hole production at a schottky barrier: Electron-hole production at a Schottky barrier has recently been observed experimentally as a result of chemical processes. This conversion of chemical energy to electronic energy may serve as a basic link between chemistry and electronics and offers the potential for generation of unique electronic signatures for chemical reactions and the...

20060065946 - Multi-doped semiconductor e-fuse: The present invention provides a multi-doped semiconductor e-fuse for use in an integrated circuit and a method of manufacture therefore. In one aspect, the semiconductor e-fuse 200 includes a semiconductor body 205 having a neck region 220 interposed a first portion 210 of the semiconductor body 205 and a second...

20060065948 - Inductor energy loss reduction techniques: An inductive device including an inductor coil located over a substrate, at least one electrically insulating layer interposing the inductor coil and the substrate, and a plurality of current interrupters each extending into the substrate, wherein a first aggregate outer boundary of the plurality of current interrupters substantially encompasses a...

20060065947 - Reverse-biased p/n wells isolating a cmos inductor from the substrate: A double well structure beneath an inductor to isolate it from the substrate. Contacts are provided for the deeper well and the substrate, to reverse bias the junction between the substrate and the deep well. In one embodiment, for a P-substrate, the deep well is an N-well, and the other...

20060065949 - Semiconductor device: A semiconductor device equipped with an integrated circuit including a metal thin-film-resistor object is disclosed. The semiconductor device includes a lower layer side insulator film formed on a semiconductor substrate, a metal wiring pattern formed on the lower layer side insulator film, an underground insulator film having a silicon oxide-film...

20060065950 - Semiconductor device: A high performance semiconductor device including a silicon oxide film that surrounds an SiGe alloy layer, which functions as a base layer, and an n-type diffusion layer, which functions as an emitter layer. Under a polycrystalline silicon film, the silicon oxide film extends over a boundary between an active region...

20060065952 - Inalassb/ingasb and inalpsb/ingasb heterojunction bipolar transistors: This invention pertains to heterojunction bipolar transistors containing a semiconductor substrate, a buffer layer of an antimony-based material deposited on the substrate, a sub-collector layer of an antimony-based material deposited on the buffer layer, a collector layer of an antimony-based material deposited on the sub-collector layer, a base layer of...

20060065951 - Structure and method for bipolar transistor having non-uniform collector-base junction: A bipolar transistor is provided which includes a collector region, an intrinsic base region overlying the collector region and an emitter region overlying the intrinsic base region. An extrinsic base overlies a portion of the intrinsic base region. An epitaxial spacer layer is disposed between the collector region and the...

20060065953 - Semiconductor die with protective layer and related method of processing a semiconductor wafer: A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface....

20060065954 - High-performance cmos soi devices on hybrid crystal-oriented substrates: Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. The first-type transistors are on first portions of the substrate that have a first type of crystalline orientation and second-type transistors are on second portions of the substrate that have a second...

20060065955 - Method for forming wiring pattern, wiring pattern, and electronic apparatus: A method for forming a wiring pattern in which a plurality of electrical wirings deposited onto a substrate is conductively connected with each other through a plurality of conductive posts, the method including relatively moving a discharge head having a plurality of nozzles and a substrate in a predetermined direction...

20060065956 - Cof flexible printed wiring board and method of producing the wiring board: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, and which exhibits no drop in bonding strength during panel bonding carried out after mounting of semiconductor chips, whereby reliability and productivity of a semiconductor chip mounting line is enhanced....

20060065957 - Light emitting diode device: A plurality of separate lead frames can be insert-molded in a reflector composed of a white resin having a high reflectivity to form a package for an LED device. A cavity is formed in the reflector. The cavity can have an inner circumferential surface that opens wider in an upward...

20060065959 - Chip package: The chip package comprising a package substrate, a circuit layer, a chip and at least one conductive wire is provided. The circuit layer is disposed on a first surface of the substrate, and extends from the first surface to a second surface of the substrate via the inner surface of...

20060065960 - Display device and manufacturing method thereof: A technique for obtaining light emitting devices manufactured with high yield is provided. The width of a seal pattern (605b) can be kept thin by manufacturing a light emitting device using a second substrate (600a) which has a concave portion (607a) and a concave portion (608a). It therefore becomes possible...

20060065958 - Three dimensional package and packaging method for integrated circuits: A 3D package has: a three-dimensional (3D) package substrate, a land grid array (LGA) or quad flat no-lead (QFN) package mounted on the 3D package substrate, the LGA or QFN package having an LGA or QFN die on a first side of an LGA or QFN package substrate, and a...

20060065961 - Integrated lid formed on mems device: An integrated lid for micro-electro-mechanical system (MEMS) devices is formed from a nitride layer deposited over a cavity containing movable parts for the device. Pillars are formed through openings within large area movable parts to support the lid over those parts. Slides are formed and moved under large etchant openings...

20060065962 - Control circuitry in stacked silicon: Apparatus, system and method for managing power of a main circuitry disposed on a main substrate using a control circuitry disposed on a control substrate, in a stacked relationship with the main substrate, are described herein....

20060065963 - Electronic device: An electronic device includes a first die that includes wires for bonding, a second die that includes an array of balls for bonding, and a substrate. The substrate includes bond sites for wires from the first die, and bond sites for the array of balls from the second die. The...

20060065965 - Multi-terminal device and printed wiring board: According to the invention, even when high-speed differential signal pins are arranged on the inner side of a BGA, they can be wired on a printed wiring board at a low cost. In a multi-terminal device (1) having one surface where a large number of connection terminals are arrayed planarly,...

20060065964 - Semiconductor device comprising light-emitting element and light-receiving element, and manufacturing method therefor: A semiconductor device includes a substrate for transmitting light, a wiring layer provided on the substrate, a semiconductor chip formed on the wiring layer, a columnar electrode, a sealant, and an external connection terminal electrically connected to the semiconductor chip via the wiring layer and protruding electrode. The device includes...

20060065966 - Semiconductor package with crossing conductor assembly and method of manufacture: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having...

20060065967 - Apparatus for singulating and bonding semiconductor chips, and method for the same: An apparatus for singulating and bonding semiconductor chips includes a singulating station and a mounting station. In the singulating station, a semiconductor chip is provided with a bonding wire by a bonding tool and lifted off a carrier film. Then, in the mounting station, the semiconductor chip is placed on...

20060065968 - Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board: An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device (10) having a semiconductor chip (12) with electrodes (16), a...

20060065970 - Radiating fin and method for manufacturing the same: A plurality of carbon fibers having a surface having a metal-plated layer (Cu-plated layer) are stood vertically on a flat plate-like provisional substrate by electrostatic flocking, and one end of the carbon fibers is provisionally adhered to the provisional substrate with an adhesive. The other end of the carbon fibers...

20060065969 - Reinforced bond pad for a semiconductor device: Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe region 212 from...

20060065971 - Electronic circuit packages: This invention relates to electronic circuit packages designed to hold high frequency circuits operating particularly, but not exclusively, in the microwave, millimetre wave, and sub-millimetre wave bands. The invention provides a package incorporating a cavity in a material for containment of the circuits, wherein the package further incorporates at least...

20060065972 - Die down ball grid array packages and method for making same: A cavity or die down ball grid array package includes an interposer substrate structure attached to the die. In an example, the interposer substrate reduces the interconnect length from a board to which the package mounts to power and ground pads on a top layer of the semiconductor or integrated...

20060065973 - Gap-change sensing through capacitive techniques: A gap-change sensing through capacitive techniques is disclosed. In one embodiment, an apparatus includes a first conductive surface and a second conductive surface substantially parallel to the first conductive surface, and a sensor to generate a measurement based on a change in a distance between the first conductive surface and...

20060065974 - Reactive gettering in phase change solders to inhibit oxidation at contact surfaces: A method for forming a high thermal conductivity heat sink to IC package interface is disclosed. The method uses reactive getter materials added to a two phase solder system having a phase change temperature that is about the normal operating temperature range of the IC, to bind absorbed and dissolved...

20060065975 - Input/output routing on an electronic device: An electronic device includes a material having a first dielectric constant (K) value, and a material having a second dielectric constant (K) value. The first dielectric constant (K) value is lower than the second dielectric constant (K) value. The electronic device also includes input/output connection conductors for transmitting signals to...

20060065976 - Method for manufacturing wafer level chip scale package structure: The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The...

20060065977 - Reliable printed wiring board assembly employing packages with solder joints and related assembly technique: An exemplary assembly comprises a printed wiring board having a first surface, and a package including a plurality of solder joints, such as solder balls, on one surface of the package. An anchor via is defined through the first surface of the printed wiring board, and conductive material situated in...

20060065978 - Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an...

20060065980 - Semiconductor device: Disclosed is a semiconductor device comprising an underlying film, a first electrode formed on the underlying film, a first dielectric film formed on the first electrode, a second electrode formed on the first dielectric film, and a first interconnect including a first conductive portion extending in a stack direction of...

20060065979 - Semiconductor device and manufacturing method thereof: A semiconductor device which is excellent in a contact property between an antireflection film on an Al contained metal film and a conductive plug is provided with good production stability. The semiconductor device includes a semiconductor substrate, an insulating interlayer 101, and a multi-layer structure. The insulating interlayer 101 is...

20060065981 - Semiconductor device and method for producing same: The present invention is concerned with a method for producing a semiconductor device wherein lower-layer wirings and upper-layer wirings are formed with an interlayer insulating film therebetween, and the lower-layer wirings are electrically connected to the upper-layer wirings via via-hole plugs. Over a semiconductor substrate, the interlayer insulating film is...

20060065982 - Semiconductor device: The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor...

20060065983 - Semiconductor package with wire bond arrangement to reduce cross talk for high speed circuits: A package for reducing signal cross talk between wire bonds of semiconductor packages. The package includes a semiconductor die having a plurality of bond pads formed thereon. The bond pads arranged in a first subset of bond pads and a second subset of bond pads. The package also includes a...

20060065984 - Package stress management: Numerous embodiments of an apparatus and method to stress and warpage of semiconductor packages are described. In one embodiment, a semiconductor die is disposed above a substrate. An encapsulating material is disposed above the substrate and semiconductor die, in which the encapsulating material has a combination of a low coefficient...

20060065985 - Substrate edge scribe: A substrate that is adapted for the fabrication of integrated circuits, having an improved scribe mark. The scribe mark is small enough to fit within an edge exclusion zone of the substrate, is disposed wholly within the edge exclusion zone of the substrate, is not disposed on a backside of...

20060054878 - Vertical elevated pore phase change memory: A vertical elevated pore structure for a phase change memory may include a pore with a lower electrode beneath the pore contacting the phase change material in the pore. The lower electrode may be made up of a higher resistivity lower electrode and a lower resistivity lower electrode underneath the...

20060054879 - Article comprising gated field emission structures with centralized nanowires and method for making the same: This invention provides novel methods of fabricating novel gated field emission structures that include aligned nanowire electron emitters (individually or in small groups) localized in central regions within gate apertures. It also provides novel devices using nanoscale emitters for microwave amplifiers, electron-beam lithography, field emission displays and x-ray sources. The...

20060054880 - High performance hyperspectral detectors using photon controlling cavities: According to various embodiments, a photodetector including a first contact layer, a second contact layer, an active region, and a photonic crystal resonant cavity is disclosed. The photonic crystal resonant cavity can operate as a resonant structure to enhance the response of the photodetector at one or more wavelengths. In...

20060054881 - Sers-active structures including nanowires: A SERS-active structure is disclosed that includes a substrate and at least one nanowire disposed on the substrate. The at least one nanowire includes a core including a first material and a coating including a SERS-active material. A SERS system is also disclosed that includes a SERS-active structure. Also disclosed...

20060054887 - Encapsulated organic luminescent display panel and method for manufacturing the same: Provided is a display panel comprised of a white color organic luminescent element and a color filter for full color implementation, wherein a substrate in which an organic luminescent element is formed and a color filter are assembled and fixed to face each other with an adhesive pattern therebetween, and...

20060054886 - Methods and devices utilizing soluble conjugated polymers: Methods, compositions and articles of manufacture involving soluble conjugated polymers are provided. The conjugated polymers have a sufficient density of polar substituents to render them soluble in a polar medium, for example water and/or methanol. The conjugated polymers may desirably comprise monomers which alter their conductivity properties. The different solubility...

20060054883 - Organic semiconductor device: The present invention provides an organic semiconductor device comprising an organic semiconductor layer having good charge carrier transport property, wherein a carrier injection to the organic semiconductor layer is easy. The above problem is solved by an organic semiconductor device comprising a first electrode and a second electrode facing to...

20060054884 - Organic semiconductor material, organic semiconductor structure, and organic semiconductor device: wherein A is a mesogen exhibiting liquid crystallinity; has a skeletal structure comprising a π-electron ring selected from a group consisting of L-unit of 6π-electron system ring, M-unit of 8π-electron system ring, N-unit of 10π-electron system ring, O-unit of 12π-electron system ring, P-unit of 14π-electron system ring, Q-unit of 16π-electron...

20060054885 - Organic thin film transistor and substrate including the same: An organic thin film transistor includes a gate electrode having a first thickness on a substrate; an organic insulating layer on the gate electrode and the substrate, a portion of the organic insulating layer on the substrate having a second thickness, and a portion of the organic insulating layer on...

20060054882 - Switching element: The present invention provides a switching element in which the compositional deviation of material is suppressed and that attains uniform bistability performance and is suitable for mass production. In a switching element comprising an organic bistable material, which exhibits two stable states in resistance under applied voltage, arranged between at...

20060054888 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device having excellent crystallinity and excellent electric characteristics includes a ZnO thin film having excellent surface smoothness. ZnO-based thin films (an n-type contact layer, an n-type clad layer, an active layer, a p-type clad layer, and a p-type contact layer primarily including ZnO are formed sequentially by an...

20060054890 - Multi-domain vertical alignment liquid crystal display: A multi-domain vertical alignment liquid crystal display (MVA LCD) has a plurality of pixel electrodes for defining a plurality of pixel units. The pixel units are disposed in matrix arrangement, and each of them has a first electrode, a second electrode, and a third electrode. When a voltage is applied...

20060054889 - Thin film transistor array panel: A thin film transistor array panel comprising: an insulating substrate; a plurality of gate lines formed on the insulating substrate and including a plurality of gate electrodes and end portions; a plurality of storage electrode lines formed on the insulating substrate; a gate insulating layer formed on the gate lines...

20060054891 - Method of creating defect free high ge content (>25%) sige-on-insulator (sgoi) substrates using wafer bonding techniques: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding...

20060054892 - Semiconductor device and method of producing the same: A semiconductor device includes a laminated substrate; a removal portion; a cavity; a first semiconductor element; and a second semiconductor element. In the laminated substrate, a bulk layer, an insulating layer, and a semiconductor layer are laminated in this order from a bottom. The laminated substrate includes a first area,...

20060054894 - Display device and driving method of the same: A problem in that a light emitting element slightly emits light is solved by an off current of a thin film transistor connected in series to the light emitting element, thereby a display device which can perform a clear display by increasing contrast, and a driving method thereof are provided....

20060054893 - Pixel driver circuit and pixel circuit having the pixel driver circuit: A pixel driver circuit for driving a light-emitting element and a pixel circuit having the pixel driver circuit are provided. The pixel driver circuit includes a data line, address lines, switch thin film transistors, feedback thin film transistors and drive thin film transistors. The pixel circuit may include an organic...

20060054895 - Multiple floating guard ring edge termination for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same: Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface...

20060054896 - Active matrix display devices and the manufacture thereof: An active plate (2) for an active matrix display device (16), the active plate (2) comprising a substrate (4), a pixel area (6) and an adjacent drive circuit area (8). Both areas include polycrystalline silicon material formed by a process in which a metal is used to enhance the crystallisation...

20060054897 - Gallium-nitride based light emitting diode light emitting layer structure: A number of light-emitting layer structures for the GaN-based LEDs that can increase the lighting efficiency of the GaN-based LEDs on one hand and facilitate the growth of epitaxial layer with better quality on the other hand are provided. The light-emitting layer structure provided is located between the n-type GaN...

20060054898 - Light-emitting gallium nitride-based iii-v group compound semiconductor device with high light extraction efficiency: A light-emitting gallium nitride-based III-V group compound semiconductor device with high light extraction efficiency that features on a substrate with concave and/or convex surface, a texturing surface layer, and a transparent conductive window layer. Therefore, the operating voltage is decreased and the efficiency of light extracting is improved....

20060054900 - Compound semiconductor device epitaxial growth substrate, semiconductor device, and manufacturing method thereof: A compound semiconductor device epitaxial growth substrate, wherein a semiconductor substrate, a substrate protective layer made of a material that is different from the material of the substrate, a middle layer for making separation of the semiconductor substrate and a compound semiconductor device layer possible, and a compound semiconductor device...

20060054901 - Optical semiconductor device, method for fabricating the same, lead frame and electronic equipment: An optical semiconductor element 2 is mounted on a lead frame 1, the optical semiconductor element 2 is encapsulated with a mold resin portion 14 of a first layer that has light permeability, and the mold resin portion 14 of the first layer is encapsulated with a mold resin portion...

20060054899 - Semiconductor optical modulator, an optical amplifier and an integrated semiconductor light-emitting device: An integrated semiconductor optical-emitting device includes a surface-emission laser diode and an EA-type semiconductor optical modulator integrated commonly on a GaAs substrate in a direction perpendicular to the GaAs substrate....

20060054902 - Band offset in alingap based light emitters to improve temperature performance: Systems and methods for improving the temperature performance of AlInGaP based light emitters. Nitrogen is added to the quantum wells in small quantities. Nitrogen is added in a range of about 0.5 percent to 2 percent. The addition of nitrogen increases the conduction band offset and increases the separation of...

20060054903 - Transparent solid-state structure for diagnostics of fluorescently labeled biomolecules: Fluorescence modification, meaning either fluorescence enhancement or fluorescence diminishment, is obtained in a transparent layer structure comprised of a substrate, a dielectric layer and a fluorophore-labeled biomolecule layer. A metal particle layer is positioned in the layer structure a distance of 200-500 nm from the fluorophore-labeled biomolecule layer. Separation distances...

20060054904 - Light emitting diode and fabrication method thereof: A light emitting diode. The light emitting diode comprises a lead frame, a plurality of light emitting chips in the lead frame, and a molding unit in an optical path of the light emitting chips, wherein the molding unit comprises a periodic microstructure....

20060054906 - Semiconductor laser apparatus: A sub-substrate, a blue-violet semiconductor laser device, an insulating layer, and a red semiconductor laser device are stacked in order on a support member through a plurality of fusion layers. The insulating layer is stacked on an n-side pad electrode of the blue-violet semiconductor laser device, and a conductive layer...

20060054905 - White, single or multi-color light emitting diodes by recycling guided modes: A white, single or multi-color light emitting diode (LED) includes a mirror for reflecting photons within the LED; a first active region, adjacent the mirror, including one or more current-injected layers for emitting photons when electrically biased in a forward direction; a second active region, adjacent the first active region,...

20060054907 - Light-emitting device of gallium nitride-based iii-v group compound semiconductor: A light-emitting device of gallium nitride-based III-V group compound semiconductor includes a substrate, a texturing surface area arranged over the substrate; a n-type gallium nitride-based III-V group compound semiconductor layer having an ohmic contact area with texturing surface disposed over the substrate; a light-emitting layer arranged over the n-type gallium...

20060054908 - Semiconductor light-emitting device: A semiconductor light-emitting device is made of a group III-nitride compound semiconductor expressed as AlxGayIn1-x-yN (where 0≦x≦1, 0≦y≦1, and 0≦x+y≦1). The semiconductor light-emitting device includes: a substrate made of SiC; a semiconductor layer which is placed above the substrate and has a light-emitting region; a multi-layered reflective layer which is...

20060054909 - Light emitting diode improved in luminous efficiency: The present invention relates to an LED, in which an n-doped semiconductor layer, an active layer, a p-doped semiconductor layer and a p-electrode are formed in their order on a sapphire substrate. A high reflectivity material layer containing Cu and Si is deposited on a remaining partial region of the...

20060054910 - Submount for light emitting diode and its manufacturing method: A submount for a light emitting diode and its manufacturing method, the submount including a reflector and having a compact size. The submount for the light emitting diode comprises a Si base substrate having input/output terminals formed on a front side thereof, and a Si reflector having a sloped through...

20060054913 - Light emitting device and method of producing same: A light emitting device having: a light emitting element; an electricity supply portion on which the light emitting element is mounted and which supplies electricity; and an inorganic sealing material for sealing the light emitting element. The inorganic sealing material has a tapered surface which becomes wider outward in a...

20060054911 - Light source assembly having high-performance heat dissipation means: A light source assembly includes a vapor chamber, which has an electrical circuit installed in the top surface, an insulation layer covered in between the top surface of the vapor chamber and the electrical circuit, and light emitting diodes installed in the top surface directly of the vapor chamber and...

20060054912 - Light-emitting unit and method for producing same as well as lead frame used for producing light-emitting unit: A surface mount type light-emitting unit composed of a light-emitting device, a first lead connected electrically with a first electrode of the light-emitting device, a second lead connected electrically with a second electrode of the light-emitting device, and a clear insulator for sealing the light-emitting device, a connecting section of...

20060054914 - Composite heat conductive structure for a led package: A composite heat conductive structure for a LED package includes an upper heat conductive base plate substantially made of ceramic material with a hole and a lower heat conductive member with a hollow portion of cylindrical shape on a top surface thereof. The lower heat conductive member is detachably secured...

20060054915 - Led package: A LED package includes a heat conductive base plate and a light emitting diode disposed thereon. A transparent encapsulating layer without luminescent powder seals the light emitting diode and a ventilation layer thereon is adapted to communicate with outside air. A luminescent plate is over the ventilation layer....

20060054916 - Optical semiconductor device and method of fabricating optical semiconductor device: In an optical semiconductor device including, at least, an n-type semiconductor layer having n-type conductivity, an active layer, a p-type semiconductor layer having p-type conductivity, current blocking layers doped with Fe are located on opposite sides of the p-type semiconductor layer. Fe and Be are simultaneously supplied as dopants when...

20060054918 - Antimonide-based optical devices: An optical device includes an antimonide-containing substrate, and an antimonide-containing n-doped layer provided on the substrate. The optical device further includes an antimonide-containing i-doped layer provided on the n-doped layer, an antimonide-containing p-doped layer provided on the i-doped layer, and an antimonide-containing p+-doped layer provided on the p-doped layer....

20060054921 - Light emitting diode: The light emitting diode comprises a p-type AlGaInP active layer 15, a p-type GaAs contact layer for transparent electrode 17, and an ITO transparent electrode 110. The carrier concentration of the p-type GaAs contact layer 17 has been set to 1.0×1019 cm−3....

20060054919 - Light-emitting element, method for manufacturing the same and lighting equipment using the same: The present invention is a light-emitting element provided with semiconductor layers of gallium nitride compounds 4 having a multilayer structure including an emitting layer 3 formed by subjecting gallium nitride compounds to epitaxial growth on a surface 2 of a substrate 1, wherein a back surface 7 of the semiconductor...

20060054917 - Nitride semiconductor light emitting device and method of manufacturing the same: A nitride semiconductor light emitting device and a method of manufacturing the same are disclosed. The nitride semiconductor light emitting device comprises an n-type nitride semiconductor layer formed on a substrate, an active layer formed on the n-type nitride semiconductor layer, a p-type nitride semiconductor layer formed on the active...

20060054920 - Semiconductor composite device, method for manufacturing the semiconductor composite device, led head that employs the semiconductor composite device, and image forming apparatus that employs the led head: A semiconductor composite apparatus includes a semiconductor thin film and a metal layer formed on a substrate. The semiconductor thin film is bonded to the metal layer formed on the substrate. A region is formed between the semiconductor thin film and the metal surface, and contains an oxide of a...

20060054922 - Optically controlled electrical switching device based on wide bandgap semiconductors: A power switching device includes an optically controlled component using a semiconducting carbon nanotube. An optical signal transmitted over an optical fiber controls the conductivity of the nanotube. The nanotube transmits a signal controlled by the optical signal to a wide-bandgap semiconductor power switch, which switches the power....

20060054925 - Compound semiconductor device and method for fabricating the same: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode...

20060054923 - Compound semiconductor epitaxial substrate and method for manufacturing same: A compound semiconductor epitaxial substrate having a pseudomorphic high electron mobility field effect transistor structure which comprises an InGaAs layer as a channel layer 9 and an InGaP layer containing n-type impurities as a front side electron supplying layer 12, wherein an electron mobility in the InGaAs layer at room...

20060054924 - Nitride-based semiconductor device: A nitride-based semiconductor device includes a first semiconductor layer consisting essentially of a nitride-based semiconductor, and a second semiconductor layer disposed on the first semiconductor layer and consisting essentially of a non-doped or first conductivity type nitride-based semiconductor. The first and second semiconductor layers forms a hetero-interface. A gate electrode...

20060054926 - High electron mobility transistor piezoelectric structures: Piezoelectric semiconductor structures and methods for fabricating the same are described. In an embodiment, the piezoelectric semiconductor structure includes a support substrate, a channel layer arranged on one side of the support substrate, and a barrier layer formed on the channel layer. The barrier layer is made of alternating binary...

20060054927 - Sensor using a gan transistor: The present invention uses a GaN transistor grown over a Si substrate, which is obtained by etching through lithography or a plasma etching; and is used as a pressure sensor with great sensitivity by utilizing the characteristic of piezoelectric effect of GaN with the ability of magnifying signals and providing...

20060054928 - Layered construction: The invention relates to a layered construction for a Gunn diode. The layered construction comprises a series of stacked layers consisting of a first highly doped nd GaAs layer (3), a graded AlGaAs layer (5), which is placed upon the first highly doped layer (3), whereby the aluminum concentration of...

20060054931 - Magneto-resistance transistor and method thereof: A magneto-resistance transistor including a magneto-resistant element which may function as an emitter and a passive element which may function as a collector. The base may be interposed between the passive element and the magneto-resistant element, thereby coupling the passive element with the magneto-resistant element. A magnetic field of a...

20060054929 - Semiconductor device: A semiconductor device includes, on a substrate (101), a buffer layer (102), and an channel layer (104), consisting essentially of semiconductor of a wultzite compound of group III-V, having a (0001) plane as a principal plane. The channel layer is subjected to compressive strain. A carrier supplying layer (103) is...

20060054932 - Semiconductor device, high-frequency amplifier and personal digital assistant: A semiconductor device includes a GaAs substrate, a sub-collector layer provided on the GaAs substrate, a collector layer provided on part of the sub-collector layer, a base layer (first semiconductor layer) provided on the collector layer, a second emitter layer (second semiconductor layer) provided on part of the base layer...

20060054930 - Spin transistor and method thereof: A spin transistor uses a single potential barrier structure to increase a current fluctuation rate. The spin transistor may include at least one of an emitter, a collector, a base and a base resistor. The emitter may be a magneto-resistant device, which may provide an adjustable resistance based on a...

20060054933 - Asymmetric memory cell: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the...

20060054935 - Standard cells, lsi with the standard cells and layout design method for the standard cells: In automatic placing and routing, a standard cell 101 is composed of a P-channel transistor region 102 and an N-channel transistor region 103. The P-channel transistor region 102 has a P-channel functional transistor forming region 104, and the N-channel transistor region 103 has an N-channel functional transistor forming region 105....

20060054934 - Using oxynitride spacer to reduce parasitic capacitance in cmos devices: A complementary metal oxide semiconductor (CMOS) device has a substrate 100, a gate structure 108 disposed atop the substrate, and spacers 250, deposited on opposite sides of the gate structure 108 to govern formation of deep source drain regions S, D in the substrate. Spacers 250 are formed of an...

20060054936 - Nanosensors: Electrical devices comprised of nanowires are described, along with methods of their manufacture and use. The nanowires can be nanotubes and nanowires. The surface of the nanowires may be selectively functionalized. Nanodetector devices are described....

20060054937 - Semiconductor devices having an interfacial dielectric layer and related methods: A semiconductor device includes a semiconductor substrate including silicon and an oxide layer on the substrate. The oxide layer includes silicon. An interfacial dielectric layer is disposed on the oxide layer opposite the substrate. The interfacial dielectric layer includes HfO2, ZrO2, a zirconium silicate alloy, and/or a hafnium silicate alloy...

20060054938 - Gate driver with programmable dead-time insertion: A dead-time generator for incorporation in an integrated circuit wherein the integrated circuit includes a high side and low side gate driver and wherein the high side and low side gate driver drive output switches such that a dead-time is provided between on times of the output switches, the dead-time...

20060054939 - Cmos image sensor: A complementary metal oxide semiconductor field effect transistor (CMOS-FET) image sensor. An active photosensing pixel is formed on a substrate. At least one side of the pixel has a width equal to or less than approximately 3 μm. At least one dielectric layer is disposed on the substrate covering the...

20060054940 - Short channel insulated-gate static induction transistor and method of manufacturing the same: The ultra high-speed vertical short channel insulated-gate static induction transistor with uniform operating characteristic which has the drain layer 3 consisting of an epitaxial single crystal layer on the main surface 2 of substrate 1, the channel layer 4 with thickness 1000 Å or less on the drain layer, the...

20060054941 - Multifunctional biosensor based on zno nanostructures: The present invention provides the multifunctional biological and biochemical sensor technology based on ZnO nanostructures. The ZnO nanotips serve as strong DNA or protein molecule binding sites to enhance the immobilization. Patterned ZnO nanotips are used to provide conductivity-based biosensors. Patterned ZnO nanotips are also used as the gate for...

20060054942 - Light emitting device: A light emitting device which has increased light emitting amount without changing its size is provided. The light emitting device is characterized in that a semiconductor layer 30 is formed on an uneven surface 1a of an uneven substrate 1. The light emitting device of the invention can be configured...

20060054943 - Flash eeprom with metal floating gate electrode: A memory device comprises a substrate including isolation regions and active regions, and a floating gate stack proximate the substrate. The floating gate stack comprises a first high-k dielectric layer proximate the substrate, a first metal layer proximate the first high-k dielectric layer, and a second high-k dielectric layer proximate...

20060054944 - Semiconductor device and process for manufacturing the same: The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film...

20060054945 - Isolation techniques for reducing dark current in cmos image sensors: A structure for isolating areas in a semiconductor device is provided. The structure includes a trench having first and second portions formed in a substrate. The first portion has a first width, and the second portion has a second width and is below the first portion. The first width is...

20060054946 - Cmos image sensor and method of manufacturing same: Disclosed are a complementary metal oxide semiconductor (CMOS) image sensor and a method of forming the same. The CMOS image sensor comprises a semiconductor substrate having a photodiode region and a transistor region. An optical path is formed between a micro lens on the photodiode region and a photodiode formed...

20060054949 - Ferroelectric memory and method of manufacturing same: A ferroelectric memory which ensures a high reliability without increasing the area of a capacitor, and a method of manufacturing the same. An interlayer film 4 is formed on a semiconductor substrate 1 which has been formed with a circuit including a transistor 2 for storage element selection, and a...

20060054947 - Magnetic random access memory and method of manufacturing the same: A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape as the lower electrode, and is formed by one...

20060054951 - Memory cell arrays: The invention includes a method of forming an array of memory cells. A series of capacitor constructions is formed, with the individual capacitor constructions having storage nodes. The capacitor constructions are defined to include a first set of capacitor constructions and a second set of capacitor constructions. A series of...

20060054950 - Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer and methods of manufacturing the same: Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer are provided. The non-volatile memory cells include a lower and upper electrodes overlapped with each other. A transition metal oxide layer pattern is provided between the lower and upper electrodes. The transition metal oxide layer...

20060054948 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes a semi-conductor substrate, a MOS transistor formed on the semiconductor substrate and including a pair of impurity regions as a source and a drain, and a gate electrode, a first conductive plug formed in contact with an upper surface of one of the pair of...

20060054955 - Dram cell having mos capacitor: A DRAM cell having a MOS capacitor and a method for manufacturing the same are disclosed. The DRAM cell includes: an active region of a semiconductor substrate; a MOS capacitor consisting of a plate node electrode which is a part of the active region, a storage node electrode having a...

20060054954 - Lateral mos device with minimization of parasitic elements: A lateral MOS device is formed in a body having a surface and is formed by a semiconductor layer of a first conductivity type; a drain region of a second conductivity type, formed in the semiconductor layer and facing the surface; a source region of the second conductivity type, formed...

20060054953 - Memory devices having a resistance pattern and methods of forming the same: Memory devices include a semiconductor substrate and a device isolation layer in the substrate and defining a cell region and a resistance region. A resistance pattern is disposed on the device isolation layer in the resistance region. An interlayer insulating layer is on the resistance pattern and a resistance contact...

20060054957 - Nonvolatile semiconductor memory and manufacturing method for the same: The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics...

20060054952 - One-time programmable memory device: A one-time programmable, dual-bit memory device comprises one MOS storage transistor having a semiconductor substrate, first and second active regions formed under the surface of the substrate being separated by a part of the substrate forming a channel region, a gate formed on the surface of the said substrate in...

20060054956 - Technique to control tunneling currents in dram capacitors, cells, and devices: Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as gates. A memory cell is provided that utilizes materials with work functions larger than n-type doped polysilicon (4.1 eV) or aluminum metal (4.1 eV) for...

20060054959 - Capacitor structure in trench structures of semiconductor devices and semiconductor devices comprising capacitor structures of this type and methods for fabricating the same: A capacitor structure includes: a number of conductive regions of metallic and/or semiconducting materials and/or conductive metal compounds thereof, the conductive regions being arranged as stacked layers in a trench structure of a semiconductor device; and a dielectric surrounding the conductive regions....

20060054958 - Fabricating a memory cell array: A DRAM memory cell array is fabricated such that, for each memory cell of the array, the gate electrode is initially produced such that it is insulated from all the other gate electrodes assigned to a certain word line, and is only connected to the other gate electrodes assigned to...

20060054960 - Semiconductor device and method for fabricating the same: A semiconductor device has a MIM capacitor including a first insulating film formed on a semiconductor substrate, a lower electrode composed of a first metal film formed on the first insulating film, a capacitor insulating film formed on the lower electrode, and an upper electrode composed of a second metal...

20060054961 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer...

20060054962 - Method to minimize formation of recess at surface planarized by chemical mechanical planarization: When chemical mechanical planarization (CMP) is used to planarize a surface coexposing patterned features and dielectric fill, where patterned features and the fill are formed of materials having very different CMP removal rates or characteristics, the planarized surface may have excessively rough, dishing or recessing may take place, or one...

20060054963 - Non-volatile and non-uniform trapped-charge memory cell structure and method of fabrication: A memory cell having a charge-trapping structure in the form of a layer of conductive clusters disposed between upper and lower insulator layers is disclosed. The memory cell can otherwise be constructed and operated similarly to a nitride read-only memory cell....

20060054964 - Semiconductor device and method for fabricating a region thereon: A semiconductor device comprises a transistor body of boron doped semiconductor substrate and a conterminous isolating area formed of insulating material, wherein an oxy-nitride layer is between the transistor body and the isolating area. This invention can be used in a transistor body for example in an NROM cell....

20060054965 - Byte-operational nonvolatile semiconductor memory device: Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed...

20060054966 - Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer...

20060054967 - Integrated half-bridge power circuit: A down converter includes an integrated circuit, which includes a control FET (CF) and a synchronous rectifier FIT (SF). The control FET is a lateral double-diffused (LDMOS) FET, and the conductivity-type of the LDMOS FET and the conductivity-type of the substrate are of the same type....

20060054969 - Semiconductor device having a junction extended by a selective epitaxial growth (seg) layer and method of fabricating the same: In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion....

20060054968 - Thin channel mosfet with source/drain stressors: Methods of manufacturing microelectronic device including, in one embodiment, forming a gate electrode over a substrate having an insulating layer interposing a bulk semiconductor portion and a thin semiconductor layer, and removing at least a portion of the thin semiconductor and insulating layers, thereby defining a pedestal comprising a portion...

20060054970 - Semiconductor device and method of manufacturing the same: In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat...

20060054971 - Memory cell without halo implant: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of...

20060054972 - Component and method for producing the same: A method and device are for anchoring fixed structural elements and, e.g., for anchoring electrodes for components, e.g., SOI wafer components, whose component structure is formed in a silicon layer on top of a substrate used as support. The fixed element may be mechanically connected to the substrate via at...

20060054973 - Method of making cavities in a semiconductor wafer: The invention provides a method of making a semiconductor structure that includes a surface layer of silicon, a buried insulating layer, and a substrate. The method includes implanting atoms through at least a portion of the insulating layer; and etching the insulating layer in at least a portion of the...

20060054974 - Compact scr device and method for integrated circuits: A semiconductor device and method for electrostatic discharge protection. The semiconductor device includes a first semiconductor controlled rectifier and a second semiconductor controlled rectifier. The first semiconductor controlled rectifier includes a first semiconductor region and a second semiconductor region, and the second semiconductor controlled rectifier includes the first semiconductor region...

20060054975 - Resistor structure and method for manufacturing the same: A resistor structure includes a substrate, a semiconductor layer positioned on the substrate, a salicide block positioned on portions of the surface of the semiconductor layer, and at least a salicide layer positioned on the portions of the surface of the semiconductor layer adjacent to the salicide block. The semiconductor...

20060054977 - Charge storage memory cell: A memory device is provided that includes a plurality of memory cells where each memory cell includes a source region, a drain region and a floating gate. A coupling bit-line is also provided that extends over at least one column of the plurality of memory cells. The coupling bit-line may...

20060054976 - Charge-trapping semiconductor memory device: Memory cells are formed by preferably cylindrical recesses at the main surface of a semiconductor substrate, containing a memory layer sequence at sidewalls and a gate electrode and being provided with upper and lower source/drain regions connected in columns to first and second bit lines. Word lines are arranged above...

20060054978 - Multiple dielectric finfet structure and method: Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics...

20060054980 - Dielectric multilayer structures of microelectronic devices and methods for fabricating the same: A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric...

20060054979 - Method for fabricating a drain/source path: A method for fabricating a drain/source path is provided, in which essentially firstly a nitride layer is applied, on which a TEOS layer is then patterned. The patterning is effected in a simplified manner by virtue of the fact that the nitride layer acts as an etching stop layer during...

20060054981 - Semiconductor device and method of manufacturing same: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and...

20060054982 - Nanowire optoelectric switching device and method: A nanowire switching device and method. The device has a nanowire structure comprising an elongated member having a cross-sectional area ranging from about 1 nanometers but less than about 500 nanometers, but can also be at other dimensions, which vary or are substantially constant or any combination of these. The...

20060054984 - Mos transistor with a deformable gate: A MOS transistor with a deformable gate formed in a semiconductor substrate, including source and drain areas separated by a channel area extending in a first direction from the source to the drain and in a second direction perpendicular to the first one, a conductive gate beam placed at least...

20060054983 - Post-release capacitance enhancement in micromachined devices and a method of performing the same: A MEMS device which utilizes a capacitive sensor or actuator is enhancement by initially fabricating the capacitive assembly which comprises the sensor or actuator as two sets of interdigitated fingers in a noninterdigitated configuration. One of the two sets of fingers is coupled to a movable stage. The stage is...

20060054985 - Artificial ferromagnetism in semiconducting arrays: Nanostructures are provided having electronic properties suitable for artificial ferromagnetism or anti-ferromagnetism in semiconducting arrays. An artificial ferromagnet device comprises an insulator substrate, and a semiconductor material over the insulator substrate. The semiconductor material has a bipartite architecture comprising interconnected, nonmagnetic nanodots organized into a plurality of cells in a...

20060054986 - Image sensor with multilevel binary optics element: An image sensor includes a substrate (41), an interlayer (42) on the substrate and a lens layer (40) on the interlayer. The substrate is a silicon layer. A plurality of photodiodes (411) are arranged in a matrix in an upper surface portion of the substrate. The interlayer includes an opaque...

20060054987 - Photoelectric conversion device, image pickup device, and method for applying electric field to the same: A photoelectric conversion device comprises an organic photoelectric conversion film intervening between at least two electrodes, the organic photoelectric conversion film comprising a positive hole transporting photoelectric conversion film and an electron transporting photoelectric conversion film, wherein each of the positive hole transporting photoelectric conversion film and the electron transporting...

20060054988 - Solid-state imaging device, method of producing the same, and camera: The prevent invention is to provide a solid-state imaging device having a electrode configuration applicable to a progressive scan, and able to reduce a obstruction of incident light at the periphery of a light receiving portion, a method of producing the same, a camera including the same. A first transfer...

20060054989 - Semiconductor devices having multilayer isolation structures and methods of forming semiconductor devices having multilayer isolation structures: A semiconductor device includes a first structure having a recess having a bottom and opposing side surfaces, and a second structure conformally disposed on the bottom and side surfaces of the recess. The second structure includes a multilayer having two layers having a thickness substantially smaller than a width of...

20060054990 - Insulating tube, semiconductor device employing the tube, and method of manufacturing the same: An insulating tube includes a underlying insulating film, a first sidewall insulating film disposed on the underlying insulating film, a second sidewall insulating film disposed on the underlying insulating film, opposite to the first sidewall insulating film so as to provide a cavity between the first and second sidewall insulating...

20060054991 - Forming phase change memory arrays: A phase change memory may be formed to have a dimension that is sub-lithographic in one embodiment by forming a surface feature over the phase change material, and coating the surface feature with a mask of sub-lithographic dimensions. The horizontal portions of the mask and the surface feature may then...

20060054992 - Semiconductor device having fuse area surrounded by protection means: A semiconductor device has a semiconductor substrate, first and second insulating layers, a fuse, a diffusion layer and a conductive pattern. The first insulating layer is selectively formed on a surface of the semiconductor substrate. The fuse is formed on the first insulating layer. The diffusion layer is formed on...

20060054993 - Semiconductor device having fuse with protection capacitor: A semiconductor device has a fuse, an internal circuit and a protection capacitor. The fuse has a first terminal connected to be applied to a fixed voltage and a second terminal. The internal circuit includes a transistor. The transistor has a threshold voltage and a gate. The protection capacitor is...

20060054994 - Interdigitaded capacitors: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner...

20060054995 - Metal-insulator-metal capacitor and method for manufacturing the same: A capacitor has a lower electrode formed on an insulation layer, a dielectric layer formed on the lower electrode, an upper electrode layer formed on the dielectric layer, and a first protection layer pattern formed on the upper electrode layer. The upper electrode layer is etched using the first protection...

20060054996 - Controlled breakdown phase change memory device: A phase change memory material may be deposited over an electrode in a pore through an insulator. The adherence of the memory material to the insulator may be improved by using a glue layer. At the same time, a breakdown layer may be formed in the pore between the memory...

20060054997 - Techniques for forming passive devices during semiconductor back-end processing: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive...

20060054998 - Bipolar transistor with high dynamic performances: A novel bipolar transistor with very high dynamic performances, usable in an integrated circuit. This bipolar transistor comprises a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy....

20060054999 - Semiconductor device: A semiconductor device includes a Zener diode connected between an outside terminal and ground, and a resistor connected to the Zener diode in series. The Zener diode and the resistor divide a noise voltage, so that the semiconductor device can have the high noise tolerance even if it uses the...

20060055000 - Epitaxial wafer and device: An epitaxial wafer and a device having improved characteristics are obtained. The epitaxial wafer includes a substrate, a buffer layer formed on the substrate, a light-receiving layer formed on the buffer layer, and a window layer. The light-receiving layer is constituted of an epitaxial film having its lattice constant larger...

20060055001 - Semiconductor device having multiple substrates: A semiconductor device includes a first substrate including first, second and third layers; and a second substrate including fourth, fifth and sixth layers. The first substrate provides an electric device. The second substrate provides a physical quantity sensor. The first layer of the first substrate and the fourth layer of...

20060055002 - Methods for enhancing die saw and packaging reliability: A wafer device is disclosed for improving reliability of circuits fabricated in an active area on a silicon substrate. A seal ring is fabricated around the active area, and a shallow trench isolation is also formed between the seal ring and a scribe line by etching into a portion of...

20060055003 - Bonded soi substrate, and method for manufacturing the same: This bonded SOI substrate includes: an SOI layer having a low density impurity layer in which dopants are present at low density and a high density impurity layer in which dopants are present at high density; a wafer for a support substrate which supports said SOI layer; and a buried...

20060055004 - Low k and ultra low k sicoh dielectric films and methods to form the same: Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric...

20060055005 - Semiconductor device: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and...

20060055006 - Field device incorporating circuit card assembly as environmental and emi/rfi shield: A field hardened industrial device is described with a housing of the device having electrically conductive walls surrounding a cavity with an open end. An electronics assembly is adapted to fit within the cavity. The device includes a circuit card assembly, which is a multi-layered printed wiring board with pass-through...

20060055007 - Seal ring structure for integrated circuit chips: A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge...

20060055009 - Chip scale package with open substrate: An integrated circuit package comprises a substrate including a core layer with a through opening and vias. A first conductive layer is on the core layer covering the through opening and a second conductive layer is on the core layer opposite the first conductive layer in the through opening and...

20060055008 - Electronic devices with edge connectors and methods of using the same: An electronic device includes a substrate having a primary surface, an array lying along the primary surface, wherein the array includes one or more radiation-emitting components, one or more radiation-responsive components, or any combination thereof, and a first edge connector. In a direction parallel to the primary surface, the first...

20060055010 - Semiconductor packages: The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the openings, a semiconductor die over the circuit traces, and a matrix contacting the circuit traces and also contacting the die. The invention also includes methods...

20060055011 - Robust power semiconductor package: A power semiconductor package, including a leadframe having at least one first terminal, a second terminal and a third terminal. The package also includes a semiconductor power die having a bottom surface defining a first current carrying electrode and a top surface on which a first metalized region defining a...

20060055013 - Electronic component, circuit board, electronic apparatus, and method for manufacturing electronic component: An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the...

20060055012 - Led package with zener diode protection circuit: A light emitting diode (LED) package is fabricated with protection circuit against static electricity. The protection circuit includes series connection of more than one Zener diodes which limit any voltage surge no higher than their breakdown voltage, and is connected in parallel with the LED chip. The breakdown voltage of...

20060055015 - Surface mount hermetic package for power semiconductor die: A hermetically sealed AlN housing for power semiconductor die has a rectangular bottom surrounded by a peripheral wall. Spaced conductive plating sections on the top of the bottom section are connected by conductive vias to conductive plated sections on the bottom to enable surface mounting of the device. A ceramic...

20060055014 - Wireless chip and manufacturing method of the same: The present invention provides a new type wireless chip that can be used without being fixed on a product. Specifically, a wireless chip can have a new function by a sealing step. One feature of a wireless chip according to the present invention is to have a structure in which...

20060055016 - Chip package assembly produced thereby: A chip package assembly is rather than a conventional package assembly and can improve the ability of packaging a photoelectric chip in order to save materials and costs. The chip package assembly includes a transparent substrate, a chip is electrically connected to a circuit layout of the transparent substrate, a...

20060055019 - Multi-chip package structure: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate....

20060055018 - Semiconductor device: A plurality of signal processing semiconductor elements are stacked on or above a circuit board. A rewiring silicon chip is mounted on or above the circuit board. The rewiring silicon chip has an inner conductor layer for connection between the plural signal processing semiconductor elements and between the circuit board...

20060055020 - Stackable ball grid array: A memory package having a plurality of vertically stacked ball grid arrays. Each of the vertically stacked ball grid arrays has a memory chip coupled thereto. Further, each of the plurality of ball grid arrays includes non-metal mateable alignment features. Each of the plurality of ball grid arrays is coupled...

20060055017 - Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip package are mounted: Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects...

20060055021 - Wiring board, method of manufacturing the same, and semiconductor device: According to this invention, a wiring board includes a conductive pattern formed from leads each of which is formed on an organic layer and has a thickness t larger than a width W....

20060055022 - Routing power and ground vias in a substrate: A method for routing vias in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with an internal bond surface having a plurality of internal bond pads and an external bond surface with a plurality of external bond pads. A plurality of power...

20060055023 - Chip carrier and chip package structure thereof: A chip carrier comprising a laminated layer and an oxidation protection layer is provided. The oxidation protection layer is a non-electrolytic metallic coating or an organic oxidation protection film on the surface of bonding finger pads or other contacts formed by deploying a simple, fast film-coating technique. Therefore, there is...

20060055024 - Adapted leaded integrated circuit module: An interposer is provided having an array of surface mount pads along the upper side and an array of BGA (ball grid array) contacts on the lower side. A module of one or more leaded packaged ICs (integrated circuits) is mounted to the array of surface mount pads. The one...

20060055025 - Method of forming a low capacitance semiconductor device and structure therefor: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator....

20060055026 - Apparatus for and method of packaging semiconductor devices: A carrier and package for plural semiconductor devices includes a member with device-conformal apertures therethrough. A first removable cover is attached to one side of the member to close one end of each aperture. After devices are inserted into the apertures with their first ends “up” and their second ends...

20060055027 - Semiconductor device: A semiconductor apparatus includes a semiconductor chip 61 including a power semiconductor device using a wide band gap semiconductor, base materials 62 and 63, first and second intermediate members 65 and 68a, a heat conducting member 66, a radiation fin 67, and an encapsulating material 68 for encapsulating the semiconductor...

20060055028 - Semiconductor device: According to an aspect of the present invention, a semiconductor device, including: a semiconductor chip having a first metal heat conductive medium in the inside thereof; a substrate having a second metal heat conductive medium thermally connected to the first metal heat conductive medium; and a temperature control device of...

20060055029 - Integrated heatspreader for use in wire bonded ball grid array semiconductor packages: The present invention is directed toward systems, packages, and methods for providing improved thermal performance in such packages and systems. Embodiments of the invention include a semiconductor integrated circuit (IC) package having a substrate with a heat spreader mounted on the substrate. An IC die is mounted to the heat...

20060055030 - Using external radiators with electroosmotic pumps for cooling integrated circuits: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically...

20060055031 - Assembled structure and clamping device thereof: An assembled structure. A first substrate having a base surface is connected to a second substrate by at least one metallic clamping device. The clamping device, vertically disposed on the second substrate, comprises two parts: a first half and a second half having a supporting surface. The first half comprises...

20060055033 - Methods of forming semiconductor packages: The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the openings, a semiconductor die over the circuit traces, and a matrix contacting the circuit traces and also contacting the die. The invention also includes methods...

20060055032 - Packaging with metal studs formed on solder pads: A semiconductor assembly has solder bumps with increased reliability. One embodiment of an assembly comprises a first substrate having at least one conductive pad on its surface; a second substrate having at least one conductive pad on its surface; at least one conductive stud; and at least one solder bump...

20060055034 - Projected contact structures for engaging bumped semiconductor devices and methods of making the same: A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder ball of a bumped integrated circuit (IC) device, such as a bumped die and a bumped packaged IC device. The projections are...

20060055035 - Bump structure: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a solder bump structure comprises a semiconductor substrate, the substrate has at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad. At least one...

20060055036 - Method of manufacturing semiconductor device, semiconductor device, and mounting structure of semiconductor device: A method of manufacturing a semiconductor device, including the following steps, forming a resin layer on a surface of a semiconductor chip, the surface is provided with a bump formed thereon, the resin layer having photosensitivity and adhesiveness, exposing an upper surface of the bump by removing a part of...

20060055037 - Microelectronic device chip including hybrid au bump, package of the same, lcd apparatus including microelectronic device chip and method of fabricating microelectronic device chip: A microelectronic device chip including a hybrid Au bump in which foreign materials are not generated in a probe tip in an electrical die sorting (EDS) test is provided. The microelectronic device chip includes a chip pad which is connected to a microelectronic device formed on a substrate and on...

20060055040 - Cavity ball grid array apparatus having improved inductance characteristics: A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically conductive adhesive layer. Bond...

20060055039 - Stackable layer containing ball grid array package: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the...

20060055038 - Tape ball grid array package with electromagnetic interference protection and method for fabricating the package: A tape ball grid array (TBGA) package and method for fabricating the package utilizes at least one electrical connection between a conductive stiffener and a patterned metal layer of a tape substrate, which is connected to a solder ball that is designated to be connected to AC ground, so that...

20060055041 - Bonding wire and bonded connection: A bonding wire (1) includes a matrix material (2) and a filler (3) embedded in this matrix material (2), the coefficient of thermal expansion of the filler (3) being lower than the coefficient of thermal expansion of the matrix material (2), and the filler (3) content by weight amounting to...

20060055042 - Method and device for the detection of at least one luminescent substance: Disclosed is a device for detecting at least one luminescent substance, comprising a radiation source for emitting excitation radiation to the at least one luminescent substance. The excitation radiation is provided with at least one excitation wavelength at which the luminescent substance is excited so as to emit luminescent radiation....

20060055043 - Connection structure for semiconductor devices: The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to an improved connection structure for semiconductor devices. A connection structure for a semiconductor device includes: a peanut-shaped opening comprising a narrow area and one or more wide areas, wherein the narrow area is between two...

20060055044 - Semiconductor device: A semiconductor device includes: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric...

20060055046 - Semiconductor device and method for manufacturing the same: The present invention provides a semiconductor device having a multilayer wiring structure including a lower Cu buried-wiring layer, a SiC film, a SiOC film of 400 nm in thickness functioning as an interlayer insulating film, and an upper Cu buried-wiring layer electrically connected to the lower buried-wiring layer through contact...

20060055045 - Semiconductor memory device and arrangement method thereof: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged...

20060055047 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device including forming a depression in a front surface of a semiconductor substrate, forming an electrode pad within the depression, forming structures including circuit devices and metal wires on the front surface of the semiconductor substrate, and exposing the electrode pad by removing a...

20060055048 - Method of wet etching vias and articles formed thereby: A method for forming smooth walled, prismatically-profiled through-wafer vias and articles formed through the method. An etch stop material is provided on a wafer, which may be a <110> silicon wafer. A mask material is provided on the etch stop material and patterned in such a way as to lead...

20060055049 - Routing vias in a substrate from bypass capacitor pads: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias...

20060055050 - Semiconductor device and manufacturing method thereof: A semiconductor device comprises a semiconductor substrate having an through hole, a first insulation resin layer formed on an inner surface of the through hole, a second insulation resin layer formed on at least one of front and rear surfaces of the semiconductor substrate, and a first conductor layer formed...

20060055051 - Method for producing chip stacks: A plurality of interconnect layers are produced on a top side of one or two semiconductor chips, and are mutually isolated from one another in each case by insulation layers that are patterned in such a way that an interconnect layer applied as bridge makes contact with the interconnects applied...

20060055053 - Semiconductor device and method for manufacturing the same, circuit board, electronic apparatus, and semiconductor device manufacturing apparatus: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps...

20060055052 - Semiconductor packages: The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the openings, a semiconductor die over the circuit traces, and a matrix contacting the circuit traces and also contacting the die. The invention also includes methods...

20060055055 - Semiconductor chip with flexible contacts at a face: The present invention relates to a semiconductor chip comprising a semiconductor element, at least a conducting line and a contact area being arranged on the semiconductor element, the conducting line being connected with the contact area, the contact area being disposed for contacting another electrical contact, characterised in that the...

20060055056 - Semiconductor equipment having a pair of heat radiation plates: Semiconductor equipment includes: a semiconductor device; a pair of upper and lower heat radiation plates; and a heat radiation block. The heat radiation block has a planar shape, which is smaller than a planer shape of the semiconductor device. The semiconductor device includes a heat generation portion facing the heat...

20060055054 - Solder-coated ball and method for manufacture thereof, and method for forming semiconductor interconnecting structure: A solder ball 50 according to the present invention includes a spherical core 2 and a solder layer 4, which includes Sn and Ag and which is provided so as to wrap the core 2 up. The amount of water contained in the solder layer 4 is 100 μl/g or...

20060055057 - Copper interconnect: An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of...

20060055058 - Copper interconnect: An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of...

20060055059 - Copper interconnect: An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of...

20060055060 - Copper interconnect: An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of...

20060055061 - Semiconductor device and a method of assembling a semiconductor device: A semiconductor device includes a substrate having first and second surfaces, the substrate having an opening; a first adhesive layer provided on the first surface; a second adhesive layer provided under the second surface; a third adhesive layer provided around the opening; a semiconductor chip arranging a plurality of chip...

20060055062 - Sensor device having stopper for limitting displacement: A sensor includes: a first chip; a second chip disposed on the first chip through an adhesive member; and a stopper. The second chip is connected to the first chip through a bonding wire. The stopper limits a displacement of the second chip when the adhesive member is deformed. The...

20060055063 - Leadframe designs for plastic overmold packages: The specification describes a plastic overmolded package for high power devices that has a very low lead count, typically fewer than eight, and in a preferred embodiment, only two. The leads occupy essentially the same linear space as the multiple leads in a conventional package and thus have a wide-blade...

20060055064 - Semiconductor device: An ion-through region 100, 102 is provided as a first opening in a passivation film 90 on a source electrode 70 and a drain electrode 80. The passivation film 90 is coated with a sealing resin to package the semiconductor device. At this point, the ion-through region 100, 102 is...

20060055065 - Hv-mos and mixed-signal circuit structure with low-k interconnection: A semiconductor chip comprises a fast device formed on a semiconductor substrate and a high-voltage metal-oxide-semiconductor transistor (HV-MOS) formed on the semiconductor substrate and an interconnect isolation feature having a low-k dielectric material disposed over the fast device and the HV-MOS in the semiconductor substrate....

20060049389 - Electric device comprising phase change material: The electric device (1, 100) has a body (2, 101) with a resistor (7, 250) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 250) has an electric resistance which depends on whether the phase change material is in the first...

20060049390 - Resistively switching nonvolatile memory cell based on alkali metal ion drift: A nonvolatile, resistively switching memory cell includes a layer arranged between a first electrode and a second electrode. The layer includes one or more chalcogenide compound(s) selected from the group consisting of CuInS, CuInSe, CdInS, CdInSe, ZnInS, MnInS, MnZnInS, ZnInSe, InS, InSSe and InSe, with alkali metal or alkaline-earth metal...

20060049391 - Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof: An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive...

20060049392 - Process for manufacturing an array of cells including selection bipolar junction transistors: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type...

20060049393 - Field emission-type electron source and method of producing the same: A field emission-type electron source has a plurality of electron source elements (10a) formed on the side of one surface (front surface) of an insulative substrate (11) composed of a glass substrate. Each of electron source elements (10a) includes a lower electrode (12), a buffer layer (14) composed of an...

20060049394 - Layered composite film incorporating a quantum dot shift register: Quantum dots are positioned within a layered composite film to produce one-dimensional and multi-dimensional shift registers within the film. Charge carriers are driven into the quantum dots by energy in connected control paths. The charge carriers are trapped in the quantum dots through quantum confinement, such that the charge carriers...

20060049395 - Field-effect transistor: An organic FET 1 comprises a substrate 2 on which a gate insulation film 41 and a functional layer 43 are formed in this order, and a source electrode 6 and a drain electrode 8 are further arranged thereon at a predetermined distance from each other, and furthermore, an organic...

20060049398 - Field-effect transistor comprising a layer of an organic semiconductor: Provided is a field-effect transistor (10) which comprises a metal or carbon source electrode (14) and a layer of a functional organic semiconductor (28). A column of an injection material (48) extends through the layer of the functional organic semiconductor (28), the column being in contact with both the source...

20060049399 - Germanium-on-insulator fabrication utilizing wafer bonding: Methods of forming a germanium on insulator structure and its associated structures are described. Those methods comprise forming an epitaxial germanium layer on a sacrificial silicon layer, removing a portion of the epitaxial germanium layer, activating the epitaxial germanium layer and an oxide layer disposed on a silicon substrate in...

20060049396 - Sealing of electronic device using absorbing layer for glue line: In one embodiment of the invention, a first absorbing layer is on a substrate and/or a second absorbing layer is on a heat-activated adhesive. If the IR source that supplies IR radiation is present on the substrate-side, then the absorption percentage of the substrate is less than the absorption percentage...

20060049397 - Use of an organic matrix material for producing an organic semiconductor material, organic semiconductor material and electronic component: The present invention relates to use of an organic matrix material for producing an organic semiconductor material, characterized in that the organic matrix material is comprised at least partly of a spirobifluorene compound, and the glass transition temperature of the organic matrix material is at least 120° C. and the...

20060049400 - Semiconductor device: A first wiring part in a first wiring layer is a starting terminal that is connected to a ground potential. The first wiring part and a second wiring part in a second wiring layer are connected by a first connecting part. The second wiring part and a third wiring part...

20060049401 - Nitride epitaxial layer structure and method of manufacturing the same: Disclosed is a nitride epitaxial layer structure and manufacturing method thereof. The structure includes a substrate, which is used as the basic supporting material, a first immediate layer formed by stacking an appropriate thickness of high temperature aluminum-gallium-indium-nitride (Al1-x-yGaxInyN) on the substrate, a second immediate layer formed by re-crystallizing an...

20060049405 - Passive matrix display device: In a semiconductor device with a reflective passive matrix liquid crystal display mounted thereto, the area for mounting a logic circuit is reduced, the product is reduced in size, and further the reliability is improved. A semiconductor device with a reflective passive matrix liquid crystal display mounted thereto is reduced...

20060049403 - Substrate for a display device, liquid crystal display device having the same and method of manufacturing the same: A substrate for a display device includes an insulating substrate, a data line, an insulating layer and a pixel electrode. The insulating substrate has a switching element. The data line is formed on the insulating substrate to be electrically connected to a first electrode of the switching element. The insulating...

20060049402 - Thin film transistor array substrate and fabricating method thereof: A thin film transistor array substrate and a fabricating method for simplifying a process and reducing a manufacturing cost. In the thin film transistor array substrate, a gate line is formed on a substrate and a gate insulating film is formed on the gate line. A data line is provided...

20060049404 - Transistor and display device having the same: A transistor includes a control electrode, a first current electrode and a second current electrode. The control electrode includes a body portion, and first and second hand portions protruded from first and second ends of the body portion, respectively. The first current electrode is electrically insulated from the control electrode...

20060049406 - Power semiconductor and method of fabrication: This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and methods for their fabrication. A power semiconductor, the semiconductor comprising: a power device, said power device having first and second electrical contact regions and...

20060049408 - Display device and method of manufacturing the same: A display device includes first and second substrates, and first and second alignment keys. The first and second substrates have first and second display regions and first and second peripheral regions, respectively. The first alignment key is disposed in the first peripheral region of the first substrate. The first alignment...

20060049407 - Thin film transistor array panel: Improved thin film transistor array panels are provided. In one embodiment, a panel includes a plurality of gate lines, data lines, and a plurality of switching elements connected to the gate lines and the data lines. An interlayer insulating layer is formed between the gate lines and the data lines....

20060049409 - Method for forming integrated circuit utilizing dual semiconductors: A monolithically integrated electronic circuit using two different semiconductor layers which are separated by a dielectric layer. Transistors formed in the upper semiconductor layer are connected to transistors formed in the lower semiconductor layer via conventional wiring. Preferably, one layer of transistors is of one polarity, N-type or P-type, while...

20060049411 - Method for fabricating group-iii nitride devices and devices fabricated using method: A method according to the present invention for fabricating high light extraction photonic devices comprising growing an epitaxial semiconductor structure on a substrate and depositing a first mirror layer on the epitaxial semiconductor structure such that the epitaxial semiconductor structure is sandwiched between the first mirror layer and the substrate....

20060049410 - Organic electroluminescence device: An organic luminescence device including an anode (1); an insulating or semiconductive inorganic thin film layer (3) having an energy gap of 2.7 eV or more; an organic compound layer (4) comprising one or more layers which include at least an organic emitting layer, at least one of the layers...

20060049412 - Cmos image sensor and method for fabricating the same: Disclosed are a complementary metal oxide semiconductor (CMOS) device and a method for fabricating the same. The CMOS image sensor includes: a photodetector; a microlens formed on the photodetector; an insulating passivation layer formed on the microlens to protect the microlens; and an oxide layer with a refraction index lower...

20060049413 - Array substrate with reduced pixel defect, method of manufacturing the same and liquid crystal display panel having the same: An array substrate includes a transparent substrate, a switching element, an insulating layer and a pixel electrode. The switching element includes a gate electrode formed on the transparent substrate and connected to a gate line, a channel layer formed on the gate electrode and extended in a first direction, a...

20060049414 - Novel oxynitride phosphors: Disclosed are oxynitride and oxide phosphor compositions having various formulations. Also disclosed are phosphor blends of the above phosphors and one or more additional phosphors and light emitting devices incorporating the same. The phosphors and their blends can be used in saturated color light sources (e.g. traffic signals), as well...

20060049415 - Monolithic multi-color, multi-quantum well semiconductor led: A monolithic, multi-color semiconductor light emitting diode (LED) is formed with a multi-bandgap, multi-quantum well (MQW) active light emitting region which emits light at spaced-apart wavelength bands or regions ranging from UV to red. The MQW active light emitting region comprises a MQW layer stack including n quantum barriers which...

20060049416 - Solid state white light emitter and display using same: A light emitting assembly comprising a solid state device coupleable with a power supply constructed and arranged to power the solid state device to emit from the solid state device a first, relatively shorter wavelength radiation, and a down-converting luminophoric medium arranged in receiving relationship to said first, relatively shorter...

20060049417 - Iii-nitride based on semiconductor device with low-resistance ohmic contacts: The present invention utilizes high-indium-content InxGa1-xN islands (0<x≦1) formed on a top of a p-type GaN based layer to reduce contact resistance between an electrode and the p-type GaN based layer. These InxGa1-xN islands serve as channels for electrical current to flow through and dramatically reduce the contact resistance between...

20060049418 - Epitaxial structure and fabrication method of nitride semiconductor device: A structure and a fabrication method for a nitride semiconductor device are provided so that the device has a lower defect density resulted from incompatible lattice constants between its constituent layers. The nitride semiconductor device contains a substrate, at least a first intermediate layer made of aluminum-gallium-indium-nitride (Al1-x-yGaxInyN) at least...

20060049419 - Light emitting diode device: A light emitting diode device can include a pair of opposed electrodes and a thin film multilayer structure interposed between the pair of electrodes. The device can include one or more light emitting layers each having an emission interface. In the device, there can be adjacent layers having an interfacial...

20060049420 - Light emitting diode (led) packaging: A light emitting diode (LED) packaging comprising a stacked substrate, a main body, and an LED die is provided. The stacked substrate includes a heat spreader and a first circuit board. The first circuit board is stacked on the heat spreader. Two channels penetrate the first circuit board and the...

20060049421 - Solid-state optical device: A solid-state optical device having: a solid-state element; a power supplying/retrieving portion that supplies or retrieves electric power to/from the solid-state element; and a glass sealing material that seals the solid-state element. The glass sealing material is made of a P2O5—ZnO-based low-melting glass that has 45 to 50 wt %...

20060049423 - Light-emitting device: A light-emitting device has a light-emitting portion having a light-emitting element; a heat dissipation base on which is mounted the light-emitting portion and which is exposed outwardly for dissipating heat produced by the light-emitting portion; a power feeding portion for feeding power to the light-emitting portion; and a sealing portion...

20060049422 - Surface mount led: An LED can include a silicon substrate that has a conductive pattern including an LED chip equipped portion, a connection portion, and external electrodes. A glass frame can be anodic-bonded onto the silicon substrate, and can include a through-hole forming a lamp house. An LED chip can be mounted onto...

20060049424 - Gallium-nitride based light-emitting diode structure with high reverse withstanding voltage and anti-esd capability: An epitaxial structure for GaN-based LEDs to achieve better reverse withstanding voltage and anti-ESD capability is provided. The epitaxial structure has an additional anti-ESD thin layer on top of the p-type contact layer within traditional GaN-based LEDs, which is made of undoped indium-gallium-nitrides (InGaN) or low-band-gap (Eg<3.4 eV), undoped aluminum-indium-gallium-nitrides...

20060049425 - Zinc-oxide-based light-emitting diode: A light-emitting zinc oxide based compound semiconductor device of a double-heterostructure. The double-heterostructure includes a light-emitting layer formed of a low-resistivity Mg1-x-y Cdx Zny O; 0≦x<1, 0<y≦1, and x+y=0.1 to 1 compound semiconductor doped with p-type and/or n-type impurity. A first clad layer is joined to one surface of the...

20060049427 - Field effect type semiconductor device: A field effect type semiconductor device is disclosed wherein a channel is easily depleted just under a gate electrode to implement an E-mode, but a channel is hard to be depleted just under a gate recess region so that the transconductance gm and the cutoff frequency fT can be set...

20060049426 - Nitride based hetero-junction field effect transistor: A nitride based hetero-junction field effect transistor comprises a high resistance nitride semiconductor layer formed on a substrate, an Al-doped GaN layer formed on the high resistance nitride semiconductor layer and having an Al content of 0.1˜1%, an undoped GaN layer formed on the Al-doped GaN layer, and an AlGaN...

20060049429 - Field effect transistor (fet) having wire channels and method of fabricating the same: In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, the plurality of wire channels being arranged in two columns...

20060049430 - Field-effect transistor, complementary field-effect transistor, and method of manufacturing field-effect transistor: For this purpose, on a single-crystal silicon substrate 101 having a {100} plane as a principal surface are formed a gate electrode 107 extending substantially in a <010> crystal axis direction of the single-crystal silicon or an axis direction equivalent to the <010> crystal axis direction, and in both sides...

20060049428 - Tft electronic devices and their manufacture: An electronic device (70) comprises a thin film transistor (TFT) (9,59), the TFT including a channel (16) defined in a layer of polycrystalline semiconductor material (10,48). The polycrystalline semiconductor material is produced by crystallising amorphous semiconductor material (2) using metal atoms (6) to promote the crystallisation process. The polycrystalline semiconductor...

20060049431 - Solid-state image sensor: A solid-state image sensor capable of improving detection sensitivity for an output signal is provided. This solid-state image sensor comprises a first gate electrode formed on a semiconductor substrate, a first impurity region formed on the semiconductor substrate at a first distance from the first gate electrode for receiving the...

20060049432 - Barrier regions for image sensors: Embodiments of the invention provide a barrier region for isolating devices of an image sensor. The barrier region comprises a charge accumulation region of a particular conductivity type in a substrate electrically connected to a voltage source terminal. The charge accumulation region is adjacent to at least one pixel cell...

20060049433 - Semiconductor light-emitting device and method for manufacturing the same: A method for fabricating a semiconductor light-emitting element according to the present invention includes the steps of (A) providing a striped masking layer on a first Group III-V compound semiconductor, (B) selectively growing a second Group III-V compound semiconductor over the entire surface of the first Group III-V compound semiconductor...

20060049434 - Semiconductor device and manufacturing method thereof: A semiconductor device and method of manufacturing the same includes an n−-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode...

20060049435 - Vertical jfet as used for selective component in a memory array: Systems and methods are disclosed that facilitate providing a selective functionality to a polymer memory cell in a memory array while increasing device density in the memory cell array. A vertical JFET is described to which voltages can be selectively applied to control internal current flow there through, which in...

20060049436 - Semiconductor component with a mos transistor: The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection...

20060049438 - Active pixel array with matching analog-to-digital converters for image processing: An imaging device includes a plurality of photo-diodes arranged in a plurality of columns on a single Complementary Metal Oxide Semiconductor (CMOS) substrate. A plurality of analog-to-digital converters (ADCs) corresponding to the plurality of columns of photo-diodes are arranged on the substrate, with each ADC having an input coupled to...

20060049437 - Cmos image sensors and methods for fabricating the same: Complementary metal-oxide semiconductor (CMOS) image sensors and methods of fabricating the same are disclosed. In one example, the method includes forming at least a first pad layer and a second pad layer on a p-type semiconductor substrate having an active area and a device dividing area defined thereon, removing the...

20060049439 - Image device and method of fabricating the same: An image device includes a substrate in which a light receiving element is formed, an interlayer dielectric structure which is formed on the substrate and has a cavity over the light receiving element, a transparent dielectric layer which fills the cavity and has a lens-shaped portion protruding beyond an upper...

20060049440 - Ferroelectric memory arrangement: A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating...

20060049443 - Flip feram cell and method to form same: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric...

20060049441 - Magnetoresistive random access memory with reduced switching field variation: An array of multi-state, multi-layer magnetic memory devices (10) wherein each memory device comprises a nonmagnetic spacer region (22) and a free magnetic region (24) positioned adjacent to a surface of the nonmagnetic spacer region, the free magnetic region including a plurality of magnetic layers (36,34,38), wherein the magnetic layer...

20060049442 - Methods for fabricating ferroelectric memory devices: A ferroelectric memory device includes a semiconductor substrate, ferroelectric capacitors, conductive patterns, and plate lines. The ferroelectric capacitors are arranged in rows and columns on the semiconductor substrate. The conductive patterns are arranged in even numbered and odd numbered rows. Each of the conductive patterns is on, and electrically connected...

20060049445 - Dram having at least three layered impurity regions between channel holes and method of fabricating same: Disclosed is a dynamic random access memory (DRAM) comprising a transistor having channel holes formed in the channel region thereof and cell gate structures formed in the channel holes. At least three layered impurity regions are formed in a semiconductor substrate between the channel holes and the at least three...

20060049444 - Semiconductor device and method of fabricating the same: According to the present invention, there is provided a semiconductor device comprising: a plurality of transistors each having a semiconductor substrate, a first-conductivity-type semiconductor layer formed on said semiconductor substrate via a first insulating film, and having a single-crystal structure, a second-conductivity-type source region and second-conductivity-type drain region formed in...

20060049446 - Method for manufacturing a semiconductor device: A semiconductor device includes a semiconductor substrate, a lower conductive layer formed over the semiconductor substrate, an intermediate insulating layer formed over the lower conductive layer and an upper conductive layer formed over the intermediate insulating layer. The upper conductive layer crosses the lower conductive layer. The semiconductor device also...

20060049447 - Antimony precursor, phase-change memory device using the antimony precursor, and method of manufacturing the phase-change memory device: An antimony precursor including antimony, nitrogen and silicon, a phase-change memory device using the same, and a method of making the phase-change memory device. The phase-change memory device may have a phase-change film of a Ge2—Sb2—Te5 material including nitrogen and silicon....

20060049448 - Method and apparatus for operating a string of charge trapping memory cells: A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge...

20060049450 - Non-volatile memory integrated circuit: A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines,...

20060049451 - Non-volatile memory integrated circuit: A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines,...

20060049449 - Non-volatile semiconductor memory and method for fabricating a non-volatile semiconductor memory: A non-volatile semiconductor memory includes memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor....

20060049452 - Novel ldmos ic technology with low threshold voltage: A lateral double diffused metal oxide semiconductor (LDMOS) device includes forming a plurality of wells on a semiconductor substrate. The plurality of wells include a first well of a first type, a second well of a second type opposite to the first type, and a third well of the first...

20060049454 - Accufet with schottky source contact: An accumulation mode FET (ACCUFET) having a source contact that makes Schottky contact with the base region thereof....

20060049456 - Insulated gate semiconductor device and method of manufacturing insulated gate semiconductor device: Disclosed is an insulated gate semiconductor device comprising: a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region; a semiconductor region which includes a channel forming region and is disposed to oppose the gate electrode region with the first insulating film...

20060049457 - Semiconductor device and method of fabricating the same: A gate electrode <13> is provided to fill up a trench <300> while covering its opening. Assuming that WG represents the diameter (sectional width) of a head portion of the gate electrode <13> located upward beyond a P-type base layer <4> and an N+-type emitter diffusion layer <51>, WT represents...

20060049455 - Semiconductor devices with local recess channel transistors and methods of manufacturing the same: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a...

20060049453 - Vertical insulated gate transistor and manufacturing method: A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into...

20060049458 - Power semiconductor device having an improved ruggedness: The power semiconductor of the invention consists of an n+ drain area; an n− epitaxial area; p− body and p+ body areas formed on top of the n− epitaxial area in a striped configuration; an n° epitaxial area formed on the n− epitaxial area and between the p− body and...

20060049459 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a drift layer of a first conductivity type formed on a first main surface of the semiconductor substrate, a surface of the drift layer having a first area and a second area which is positioned on an outer...

20060049460 - Cmos logic gate fabricated on hybrid crystal orientations and method of forming thereof: In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation...

20060049461 - Thin-film transistor with vertical channel region: A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate; forming a gate, having sidewalls and a thickness, overlying a...

20060049462 - High voltage transistor and method for fabricating the same: A high voltage transistor operating through a high voltage and a method for fabricating the same are provided. The high voltage transistor includes: an insulation layer on a substrate; an N+-type drain junction region on the insulation layer; an N−-type drain junction region on the N+-type drain junction region; a...

20060049463 - High voltage operating electrostatic discharge protection device: A high voltage operating electrostatic discharge protection device is provided. The high voltage operating electrostatic discharge protection device includes: a first gate structure and a second gate structure disposed on a substrate of a first conductive type with a predetermined distance; a well of the first conductive type formed in...

20060049464 - Semiconductor devices with graded dopant regions: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation...

20060049465 - Power semiconductor device for preventing punchthrough and manufacturing method thereof: This invention presents a power semiconductor for preventing punchthrough in the channel area. For this purpose, the invention presents a power semiconductor possessing a high concentration substrate area of conduction type 1; a primary epitaxial area of conduction type 1, formed in low concentration on top of the drain area;...

20060049466 - Semiconductor device having fuse and protection circuit: A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer...

20060049467 - Body-tied-to-source mosfets with asymmetrical source and drain regions and methods of fabricating the same: A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern. A drain region of a second conductivity type is disposed on the insulating layer and having a sidewall in...

20060049469 - Integrated semiconductor circuit comprising a transistor and a strip conductor: An integrated semiconductor circuit includes a transistor and a strip conductor (11). The transistor includes a first (1) and a second source/drain region (2) and a gate electrode. The strip conductor (11) is electrically insulated from a semiconductor body at least by a gate dielectric and forms the gate electrode...

20060049468 - Interconnection architecture and method of assessing interconnection architecture: A multi-celled chip. The chip includes a plurality of hexagonal cells arranged in an array. A plurality of interconnects including Y's connect the cells in clusters of three cells each, so that each of the cells is interconnected....

20060049470 - Double layer polysilicon gate electrode: A method for forming a microelectronic product and the microelectronic product resulting from the method both employ a bilayer gate electrode. The bilayer gate electrode employs: (1) a first layer formed of a random oriented polycrystalline silicon material; and (2) a second layer laminated to the first layer and formed...

20060049471 - Encapsulated microstructure and method of producing one such microstructure: A microstructure including in a first layer insulated from a substrate by an insulator layer at least one sensitive element connected to at least one contact pad by an electrical connection and protected by a package cap. The sensitive element, the electrical connection, and the contact pad form an assembly...

20060049472 - Magnetic elements with spin engineered insertion layers and mram devices using the magnetic elements: A method and system for providing a magnetic element is disclosed. The method and system include providing a pinned layer, a free layer, and a spacer layer between the pinned and free layers. The spacer layer is nonmagnetic. The magnetic element is configured to allow the free layer to be...

20060049473 - Spin polarization of charge carriers: Methods and devices for producing spin polarized charge carriers are provided. The devices utilize semiconductors exhibiting spin orbit coupling, at least one barrier and at least one aperture. The at least one aperture is positioned such that charge carriers having a first polarization after reflecting off of the barrier can...

20060049474 - High performance spin-valve transistor: The invention generally relates to the field of spintronics, a branch of electronics using the magnetic spin properties of electrons. More particularly, the invention relates to the field of spin-valve transistors which can be used in numerous fields of electronics. The invention aims to propose an original arrangement for producing...

20060049475 - High power led array: The present invention relates to a high-power LED array. The high-power LED array has a printed circuit board (PCB), anodes, cathodes, high-power LED dies, packing materials, and lenses. The PCB has cavities arranged in an array. One anode and one cathode are located in each cavity. The anode and the...

20060049476 - Solid-state image sensor and imaging system: At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise....

20060049477 - Optoelectronic component: The invention relates to an optoelectronic component containing an optoelectronic chip (1) and containing a chip carrier (2) that has a central region (3) on which the chip is fixed and that comprises terminals (41, 42, 43, 44) extending outwardly from the central region of the chip carrier (2) to...

20060049478 - Photoelectric converter, photoelectric conversion device and iron silicide film: A solar battery 10 comprises a metal electrode layer 12, a pin junction 100, and a transparent electrode layer 16 which are successively laminated on a substrate 11 such as a silicon substrate. The pin junction 100 comprises an n-layer 13, an i-layer 14, and a p-layer 15 which are...

20060049479 - Capacitor placement for integrated circuit packages: A side-mounted capacitor for a semiconductor die package is described. In one embodiment, a substrate has a die side to which an IC (integrated circuit) may be attached, and an edge adjacent the die side. A bypass capacitor is attached to the package substrate edge....

20060049480 - Method of and apparatus for measuring stress of semiconductor material: The present invention provides a method of and a device for measuring the stress in a semiconductor material. An excitation light is irradiated on a semiconductor material formed with a silicon germanium layer and a strained silicon layer in a multilayer structure on a single crystal silicon substrate from the...

20060049481 - Planar inductive component and an integrated circuit comprising a planar inductive component: The invention relates to a planar inductive component arranged over a substrate (103). The substrate in a first plane, a patterned ground shield (102), for shielding the winding (101) from the substrate (103). The winding (101) is at least substantially symmetrical plane. The patterned ground shield (102) comprises a plurality...

20060049483 - Post passivation interconnection process and structures: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer....

20060049482 - System and method for providing a low frequency filter pole: Systems are provided for producing a low frequency filter pole. A first bond pad is coupled to a power source. A second bond pad is inductively connected to the first bond pad by a first bond wire. A capacitor is connected to the second bond pad. A third bond pad...

20060049484 - Semiconductor device: The semiconductor device comprises a resistance element 26 formed of polysilicon film formed on a silicon substrate 10, which includes a resistor part 26a having a resistance value set at a prescribed value, contact parts 26b formed on both sides of the resistor part 26a and connected to a line...

20060049485 - High on-state breakdown heterojunction bipolar transistor: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state...

20060049486 - Method of self-assembling electronic circuitry and circuits formed thereby: A method of assembling a circuit includes providing a template, enabling a semiconductor material to self assemble on the template, and enabling self-assembly of a connection between the semiconductor material and the template to form the circuit and a circuit created by self-assembly....

20060049487 - Semiconductor device and method of manufacturing the same: A semiconductor device manufacturing method is disclosed. A semiconductor substrate having a separation region and a semiconductor region which covers the separation region entirely is prepared. One or a plurality of circuit elements are formed in the semiconductor region. The semiconductor substrate is split at the separation region....

20060049488 - Semiconductor device and method for fabricating the same: A semiconductor device according to the present invention includes a semiconductor substrate, which comprises a first surface on which an electrode pad is formed, and a second surface arranged at an opposite side of the first surface; an external terminal formed on the first surface of the semiconductor substrate and...

20060049490 - Displaying apparatus: A displaying apparatus includes a printed circuit board (PCB), an integrated circuit (IC) provided on the PCB, a shield case enclosing the PCB, an electromagnetic wave conducting part interposed between and in contact with the IC and the shield case to conduct electromagnetic waves generated from the IC into the...

20060049489 - Surface acoustic wave device and manufacturing method of the same: A surface acoustic wave device has a SAW device element 10 and a package 20 housing the SAW device element. The package includes a resin substrate 20 having metal patterns 21 and 22 formed on both surfaces thereof, and a resin cap 32. The SAW device element is mounted on...

20060049491 - Connection structure for coaxial connector and multilayer substrate: In the structure for connecting a board and a coaxial connector, which electrically connects a high-frequency board 20 mounted in an electroconductive casing 1 and a coaxial connector 10, a transfer board 30 is disposed between the high-frequency board 20 and the coaxial connector 10, and the high-frequency board 20...

20060049493 - Lead frame and method of manufacturing the same: Provided is a lead frame having an improved wire bonding property of inner leads and an improved soldering property of outer leads and preventing defects with high producing yield, and a method of manufacturing the lead frame. The lead frame includes a plurality of inner leads formed with predetermined intervals...

20060049492 - Reduced foot print lead-less package with tolerance for thermal and mechanical stresses and method thereof: System and method for a reduced foot print package with tolerance for thermal and mechanical stresses for integrated circuits. A preferred embodiment comprises a package for an integrated circuit die comprising a plurality of input/output contacts and a die support to hold the integrated circuit die. The die support comprises...

20060049494 - Semiconductor device: A semiconductor device comprises; a semiconductor chip including a first and second groups of pads; and a wiring substrate including a first and second groups of leads, wherein the first group pads are arranged in line with a first line extending along one side of the semiconductor chip; the second...

20060049498 - Methods of making microelectronic assemblies including compliant interfaces: An assembly includes a structure, a plurality of terminals and a plurality of compliant pads disposed between said terminals and said structure. The terminals are aligned with at least some of said pads, with the pads providing a standoff between the structure and the terminals. The compliant pads are preferably...

20060049497 - Physical quantity sensor: A physical quantity sensor includes a package, a circuit chip disposed and held in the package, a sensor chip stacked and fixed on the circuit chip, and a wiring member having flexibility, through which the circuit chip and the package are electrically and mechanically bonded together. In the physical quantity...

20060049499 - Semiconductor device and its manufacturing method: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in...

20060049495 - Semiconductor package and laminated semiconductor package: A semiconductor package has a semiconductor device chip and a flexible substrate having a thermoplastic insulating resin layer. An electrode provided on the flexible substrate is connected to a predetermined electrode of the semiconductor device chip and sealed by the thermoplastic insulating resin layer. The flexible substrate is bent and...

20060049496 - System and method for providing scalability in an integrated circuit: The invention provides a system and method for providing scalability in an integrated circuit (IC) having a package coupled to a die through package balls. The die includes a plurality of input/output (I/O) slots and a hardmac configured to implement a logic function. A patch board is included between the...

20060049504 - Module assembly and method for stacked bga packages: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected...

20060049502 - Module thermal management system and method: A circuit module shunts thermal energy into a chassis component or a part of the box of the computing application in which the module is employed. In one preferred mode, a flex circuit is populated along each of its first and second major sides with two ranks of ICs which...

20060049501 - Package having dummy package substrate and method of fabricating the same: A package may include a stack of unit chip packages, and each unit chip package may include a printed circuit board. The printed circuit board may support a semiconductor chip and a connection terminal for connecting to an adjacent unit chip package within the stack. A dummy package substrate may...

20060049503 - Substrate-based housing component with a semiconductor chip: The invention, which relates to an electronic component with a semiconductor chip, which is connected to a carrier substrate and surrounded by a housing, is based on presenting a substrate-based, housed electronic component, which enables the continuous release of the internal vapor pressure arising when the electronic component is heated,...

20060049500 - Thin module system and method: Modules with larger areas for device mounting but minimized profiles are provided. In preferred embodiments, modules that employ one or more flex circuits have sculpted supportive substrates to selectively accommodate larger or taller profile devices. In several preferred embodiments, higher profile circuits such as AMBs, for example, are disposed in...

20060049506 - Capacitance type semiconductor sensor: In a capacitance type semiconductor dynamic quantity sensor, a sensor chip and a circuit are connected to each other through adhesive film having an elasticity of 200 MPa or less to reduce the temperature characteristic. Four bonding wires for connecting the sensor chip and the circuit chip are arranged so...

20060049505 - High density interconnect power and ground strap and method therefor: One aspect of the present invention relates to reducing the impedance of the paths connecting the power or ground of a device and a BGA package. In a particular example implementation, impedance of the signal bond wires is controlled by placing a ground strap (130) at a predetermined distance from...

20060049507 - Semiconductor device and wire bonding chip size package therefor: A semiconductor device incorporated in a wire bonding chip size package (WBCSP) is designed such that a plurality of pads are formed on the surface of a semiconductor substrate and are connected to external terminals via conductive posts, wherein first and second rewiring patterns are respectively connected to the pads....

20060049508 - Semiconductor device, lead frame, and methods for manufacturing the same: In a semiconductor device in which a semiconductor chip is mounted on a die pad, an electrode on the surface of the chip and a lead arranged around the die pad are connected with a wire, and the semiconductor chip, the wire and a wire connecting portion of the lead...

20060049509 - Printed wiring board: A printed wiring board comprises the insulating layer 11 (12); at least one resistance element 31, (312) comprising a metal as a main component has 0.5 to 5 μm of a roughened surface in an arithmetic means height in the one surface, in −Z direction, and 5% to 50% of...

20060049511 - Integrated semiconductor circuit and method for producing an integrated semiconductor circuit: An integrated semiconductor circuit comprises a substrate with a circuit, a plurality of wiring planes that are isolated from one another and from the substrate by insulator layers, and a signal path for the circuit in the substrate and/or the wiring planes. A first contact terminal, which is formed from...

20060049510 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device according to claim 1, wherein A method of manufacturing a semiconductor chip the carrier substrate A semiconductor device includes; a carrier substrate in which a semiconductor chip is mounted; a first land that is mounted on the carrier substrate and placed on a region which is differ...

20060049512 - Thin module system and method with skew reduction: A flex circuit populated with integrated circuits on one or both sides and in one or more fields along the flex circuitry is wrapped about an edge of a supporting substrate. One side of the flex circuitry has a connective facility implemented in a preferred embodiment with edge connector contacts...

20060049513 - Thin module system and method with thermal management: A flex circuit populated with integrated circuits on one or both sides and in one or more fields along the flex circuitry is wrapped about an edge of a supporting substrate. In preferred embodiments, the substrate is thermally conductive material. One side of the flex circuitry has a connective facility...

20060049514 - Semiconductor device with reduced contact resistance: A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device....

20060049515 - Memory module having memory chips protected from excessive heat: The invention relates to a memory module having a printed circuit board; having one or more memory chips which are arranged in a first region of the printed circuit board and are contact-connected by the printed circuit board; having a buffer chip for driving the memory chips and for communicating...

20060049516 - Nickel/gold pad structure of semiconductor package and fabrication method thereof: A nickel/gold (Ni/Au) pad structure of a semiconductor package and a fabrication method thereof are provided. The fabrication method includes preparing a core layer; forming a conductive trace layer on the core layer; patterning the conductive trace layer to form at least one pad of the conductive trace layer; applying...

20060049517 - Flip chip semiconductor device and manufacturing method thereof: A flip chip semiconductor device having an improved structure and a method of manufacturing the flip chip semiconductor device, in which a semiconductor chip can be more securely joined to a lead frame while preventing contact defects between the two. The flip chip semiconductor device includes: a semiconductor chip having...

20060049519 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device, comprises: a carrier substrate in which a semiconductor chip is mounted; and a land formed in the carrier substrate and arranged in a region different from the mounting face of the semiconductor chip, wherein a coarse face, the surface roughness of which is 20 through 100 μm,...

20060049518 - Semiconductor device and method for manufacturing the same: A semiconductor device, comprising: a semiconductor substrate in which an integrated circuit is formed, the semiconductor substrate having an electrode electrically connected to the integrated circuit; a resin layer formed on a face in which the electrode of the semiconductor substrate is formed, as to avoid the electrode; a wiring...

20060049521 - Semiconductor device having tin-based solder layer and method for manufacturing the same: A semiconductor device includes: a semiconductor substrate; a base member; a tin-based solder layer; a first metal layer; and a first alloy layer. The semiconductor substrate is bonded to the base member through the first metal layer, the first alloy layer and the tin-based solder layer in this order. The...

20060049520 - Semiconductor device mounting structure for reducing thermal stress and warpage: A semiconductor device is composed of a circuit board, a semiconductor chip connected with the circuit board by a plurality of bumps. The semiconductor chip includes a center portion and a peripheral portion surrounding the center portion. The peripheral portion has a thickness smaller than that of the center portion....

20060049522 - Grooved substrates for uniform underfilling solder ball assembled electronic devices: A semiconductor assembly (300) comprising a semiconductor device (301), which has a plurality of metallic contact pads (302) and an outline by sides (303). A metallic bump (304) made of reflowable metal is attached to each of these contact pads. An electrically insulating substrate (305) has a surface with a...

20060049523 - Wire-bonding method for connecting wire-bond pads and chip and the structure formed thereby: A wire-bonding method for connecting a wire-bond pad and a chip is characterized in that a metal ball is disposed on the wire-bond pad such that a bonding wire can be electrically connected to the wire-bond pad and raised to a certain height by the metal ball. In this arrangement,...

20060049524 - Post passivation interconnection process and structures: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer....

20060049525 - Post passivation interconnection process and structures: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer....

20060049526 - Processing methods of forming an electrically conductive plug to a node location: Methods of forming electrical connections with an integrated circuitry substrate node location are described. According to one aspect of the invention, a substrate node location is laterally surrounded with insulating material and left outwardly exposed. Conductive material is deposited over the exposed node location. Subsequently, a photomaskless etch of the...

20060049527 - Electronic device and method of manufacturing the same: An electronic device including a substrate provided with a first wiring formed thereon; and a pedestal provided above the substrate and provided with a second wiring formed thereon, wherein the second wiring is connected to the first wiring on the substrate....

20060049528 - Semiconductor chip stack structure and method for forming the same: Semiconductor chip stack structure and method are provided. A first chip has a first metal bump formed on a first electrode pad. The first chip is attached to and electrically connected to a substrate. The electrical connection is made by a bump reverse bonding method in which one end of...

20060049529 - Flip chip metal bonding to plastic leadframe: A plastic substrate can be provided and thereafter a plurality of metal-to-metal connections can be ultrasonically bonded to the plastic substrate. One or more dies and a plurality of conductive components thereof can then be respectively connected to the metal-to-metal connections in order to provide a plastic leadframe package structure...

20060049530 - Method of embedding semiconductor chip in support plate and embedded structure thereof: A method of embedding a semiconductor chip in a support plate and an embedded structure thereof are proposed. A first dielectric layer having a reinforced filling material is provided, and a semiconductor chip is mounted on the first dielectric layer. A support plate having an opening and a second dielectric...

20060049531 - Semiconductor package having a partial slot cover for encapsulation process: A system and method for encapsulating an integrated circuit package is provided. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the...

20060049532 - Chip module: A chip module having a chip which is mounted by means of chip adhesive on a mount and is electrically connected via bonding wires to contact pads, and an encapsulation compound which surrounds the chip and the bonding wires and is bounded by a subarea of the mount. The encapsulation...

20060043355 - Prams having phase-change layer pattern with electrode contact area and methods of forming the same: According to some embodiments of the present invention, there are provided PRAMS having a phase-change layer pattern interposed between a molding layer and a forming layer pattern, and methods of forming the same that include a node conductive layer pattern, a molding layer, a forming layer pattern and a protecting...

20060043354 - Reactive sputtering process for optimizing the thermal stability of thin chalcogenide layers: A chalcogenide layer includes a composition of compounds having the formula MmX1-m, where M denotes one or more elements selected from the group consisting of group IVb elements of the periodic system, group Vb elements of the periodic system and transition metals, X denotes one or more elements selected from...

20060043357 - Quantum computer apparatus: Quantum computer includes optical resonator including system group containing systems each having energy states highest-energy state |3>, and other two energy states |1> and |2>, fourth or more states |p>, transition angular frequency (ωij) between |i> and |j>, homogeneous broadening (Δωhomo,ij) in transition angular frequency between |i> and |j>, optical...

20060043356 - Semiconductor optical device having quantum well structure and its manufacturing method: Oxygen is doped in a quantum well active layer. First, an n-type In0.02Ga0.98N barrier layer 550 of 10 nm is formed by supplying TMG at 10 sccm, TMI at 30 sccm, O2 at 20 sccm, and NH3 at 10 slm, on the n-type GaN optical guide layer 405. Next, a...

20060043359 - Field-effect transistor: An organic FET 1 comprises a substrate 2 on which a gate insulation film 41 and a reformed layer 43 are formed in this order, and a source electrode 6 and a drain electrode 8 are further arranged thereon at a predetermined distance from each other, and furthermore, an organic...

20060043362 - Organic electroluminescent element and method of manufacturing the same: An organic electroluminescent element comprising a transparent substrate and at least one organic layer containing a light-emitting layer between a pair of electrodes, wherein the transparent substrate is placed as the light output face of the element, a prism structure consisting of a prism pattern containing a medium having a...

20060043360 - Organic light emitting display with circuit measuring pad and method of fabricating the same: An organic light emitting display and method of fabricating the same are disclosed. The light emitting display includes: a substrate having a display region and a circuit measuring pad region; source and drain electrodes arranged above the display region and a first conductive layer arranged above the circuit measuring pad...

20060043358 - Polymer thin and polymer thin film device using same: The present invention relates to a polymer film comprising a polymer having liquid crystallinity, having a number-average molecular weight in terms of polystyrene of 103 to 108 and having an electron mobility or hole mobility of 10−5 cm2/Vs or more, and having a film thickness in the range from 1...

20060043363 - Vertical organic fet and method for manufacturing same: The present invention provides a vertical organic FET with increased carrier mobility and suppressed molecular orientation of an active layer composed of an organic semiconductor. The present invention relates to a vertical organic FET having a structure in which at least a source electrode layer, a drain electrode layer, a...

20060043361 - White light-emitting organic-inorganic hybrid electroluminescence device comprising semiconductor nanocrystals: A white light-emitting organic-inorganic hybrid electroluminescence device which has nanocrystals as illuminants. According to the device, a semiconductor nanocrystal layer composed of at least one kind of nanocrystals, a hole transport layer and/or an electron transport layer simultaneously emit light to produce white light, or a semiconductor nanocrystal layer composed...

20060043364 - Methods for applying front side and edge protection material to electronic devices at the wafer level, devices made by the methods, and systems including the devices: Methods for applying a dielectric protective layer to a wafer in wafer-level chip scale package manufacture. A flowable dielectric protective material with fluxing capability is applied over the active surface of an unbumped semiconductor wafer to cover active device areas, bond pads, test socket contact locations, and optional pre-scribed wafer...

20060043366 - Driving circuit active matrix type organic light emitting diode device and method thereof: Disclosed are a driving circuit and driving method for an organic light emitting diode (OLED) device. The driving circuit for the OLED device comprises RGB pixels each including: a gate line arranged in a first direction and a data line and a power supply line arranged in a second direction...

20060043365 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; forming a gate insulating layer; forming a semiconductor layer; forming a lower data line; forming an upper data line including a source electrode and a drain electrode, the upper...

20060043367 - Semiconductor device and method of fabricating a low temperature poly-silicon layer: A method of fabricating a low temperature poly-silicon (LTPS). A plurality of semiconductor heat sinks are formed over a substrate. A buffer layer and an amorphous silicon layer are formed over the substrate and the semiconductor heat sinks. Following that, a laser crystallization process is performed to transform the amorphous...

20060043368 - Flash cell structures and methods of formation: Methods of fabrication and flash memory structures eliminate process steps while increasing capacitive coupling between floating gates and control gates of the memory cells. A thick floating gate is deposited early in the process, and a height and width of the floating gate is controlled with deposition and etching or...

20060043369 - Cmos device having different amounts of nitrogen in the nmos gate dielectric layers and pmos gate dielectric layers: The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer...

20060043370 - Thin film transistor array and pixel structure: A pixel structure having a storage capacitor therein is provided. The pixel structure comprises a substrate, a first capacitor electrode, a capacitor dielectric layer, a second capacitor electrode, a passivation layer and a pixel electrode. The first capacitor electrode is disposed over the substrate. The capacitor dielectric layer is disposed...

20060043371 - Active matrix organic electroluminescent display device: An active matrix electroluminescent display device uses a stepped voltage waveform to the input of the pixel, the stepped voltage waveform being voltage-shifted by a previously stored pixel drive voltage before application to the gate of a drive transistor. The level of the voltage shift determines the duty cycle with...

20060043378 - Front substrate of plasma display panel and fabrication method thereof: A front substrate for a plasma display panel (PDP) and an associated fabrication method are provided. An upper dielectric layer of the front substrate includes a colorant, which causes the dielectric layer to also act as a color filter. The resulting front substrate enhances at least one of color temperature,...

20060043375 - Image display and method of driving image display: An image display includes a light emitting unit that emits light via energization; a driver that includes at least a first terminal and a second terminal, and that controls light emission by the light emitting unit according to a potential difference which is applied between the first terminal and the...

20060043372 - Light emitting devices and arrays with reduced electrode resistance: For light emitting devices used in conventional information displays, the dimensions of each light emitting device are small and the effect of series resistance of electrodes is not too severe in affecting the performance of the displays. When the dimensions or areas of the devices increase for large area display...

20060043373 - Method for manufacturing a pixel array of top emitting oled: A process for manufacturing a pixel array of top-emitting OLED pixel is provided. The process comprises: providing a substrate having at least two poly-silicon islands defined thereon, and defining an implantation region on the substrate; forming a gate insulator layer and a gate metal layer sequentially, and then defining a...

20060043377 - Semiconductor device: A semiconductor device can include a channel including an oxide comprising a combination of isovalent cations selected from within the D block and the P block of the Periodic Table....

20060043376 - Semiconductor device having display device: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high...

20060043374 - Touch panel: In a touch panel, upper and lower electrode connecting portions are provided in the vicinity of a sealing agent formed above extending electrodes, and the upper and lower electrode connecting portions are connected so as to overlap each other. Accordingly, a gap between a height of the overlap of the...

20060043379 - Sic metal semiconductor field-effect transistors and methods for producing same: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication...

20060043380 - Light-emitting device of field-effect transistor type: A theme is to provide a field-effect light-emitting device that can obtain a long-term reliability and broaden a selectivity of emission wavelength. The invention of this application is a field-effect transistor type light-emitting device having an electron injection electrode, i.e. a source electrode, a hole injection electrode, i.e. a drain...

20060043382 - Metal base wiring board for retaining light emitting elements, light emitting source, lightning apparatus, and display apparatus: A metal base wiring board including: an insulation substrate composed of an upper insulation layer and a lower insulation layer; and a metal base attached to a rear surface of the insulation substrate. In front surfaces of the upper and lower insulation layers, wiring patterns are embedded and connected to...

20060043387 - Nitride-based compound semiconductor light emitting device, structural unit thereof, and fabricating method thereof: A nitride-based compound semiconductor light emitting device includes a first conductive substrate, a first ohmic electrode formed on the first conductive substrate, a bonding metal layer formed on the first ohmic electrode, a second ohmic electrode formed on the bonding metal layer, and a nitride-based compound semiconductor layer formed on...

20060043381 - Radiation emitting semiconductor device and method of manufacturing such a device: Radiation-emitting semiconductor device and method of manufacturing such a device. The invention relates to a radiation-emitting semiconductor device (10) comprising a silicon-containing semiconductor body (1) and a substrate (2), which semiconductor body (1) comprises a lateral semiconductor diode positioned on an insulating layer (7) which separates the diode from the...

20060043383 - Red light-emitting device and method for preparing the same: The present red light-emitting device includes a substrate with a first window layer, a silicon dioxide layer positioned on the first window layer, a plurality of silicon nanocrystals distributed in the silicon dioxide layer, a second window layer, a transparent conductive layer and a first ohmic contact electrode positioned in...

20060043386 - Semiconductor light-emitting device: A semiconductor light-emitting device including a light-emitting portion permitting light at a specific wavelength and having two surfaces opposite each other. The device also includes a first type of semiconductor substrate and a second type semiconductor substrate which are integrally joined to corresponding surfaces of the light-emitting portion and are...

20060043384 - Vertical nitride semiconductor light emitting diode: The present invention relates to a vertical nitride semiconductor light emitting diode. The present invention provides a vertical nitride semiconductor light emitting diode comprising a first conductive nitride semiconductor layer including an upper surface having a first electrode formed thereon; an active layer formed on a lower surface of the...

20060043385 - White light emitting diode of a blue and yellow light emitting (structure) layer stacked structure and method of manufacturing the same: A white LED of a blue and yellow light emitting (structure) layer stacked structure includes a sapphire substrate, or gallium nitride substrate, or silicon carbide substrate, or silicon substrate; a buffer layer formed on the substrate; an N type gallium nitride epitaxial layer formed on the buffer layer; an N...

20060043388 - Reflective electrode and compound semiconductor light emitting device including the same: Provided are a reflective electrode and a compound semiconductor light emitting device, such as an LED or an LD, including the same. The reflective electrode, which is formed on a p-type compound semiconductor layer, includes: a first electrode layer forming an ohmic contact with the p-type compound semiconductor layer; a...

20060043389 - Digital signal transfer device: A digital signal transfer device generates from a modulating section (100) a modulated signal responsive to a digital input signal and transfers this to a demodulating section (200) through a pulse transformer (6). The demodulating section (200) generates from the modulated signal an output signal in which the digital input...

20060043391 - Light emitting devices for liquid crystal displays: Light-emitting devices, and related components, processes, systems and methods are disclosed....

20060043390 - Light-receiving panel or light-emitting panel, and manufacturing method thereof: A light receiving panel provided with a plurality of particulate semiconductor elements (solar cells) or a light emitting panel provided with a plurality of particulate semiconductor elements (light emitting diodes) is disclosed. In the solar cell panel, a printed wiring sheet is constructed by forming printed wiring and retaining holes...

20060043392 - Semiconductor light emitting device and manufacturing method for semiconductor light emitting device: A semiconductor light emitting device includes a first conductivity-type first semiconductor layer; an emission layer; a second conductivity-type second semiconductor layer; and a second conductivity-type transparent substrate transparent to light beams from the emission layer and directly bonded to the second semiconductor layer. The transparent substrate has a parallel surface...

20060043393 - Image pickup apparatus and image pickup system: A well 302 is formed on a wafer 301, and semiconductor layers 101a, 101b are formed in the well to constitute photodiodes. A well contact 306 is formed between the semiconductor layers 101a, 101b. Element isolation regions 303b, 303a are provided between the well contact and the semiconductor layers, and...

20060043394 - Gallium-nitride based light emitting diode structure: A gallium-nitride(GaN) based light emitting diode (LED) structure utilizing materials having compatible lattice constant is provided. When aluminum-indium-nitride (AlxIn1-xN, 0<x<1) is used to make the p-type cladding layer within the GaN-based LED structure, the cladding layer has a lattice constant compatible with that of GaN. The active layer's multi-quantum well...

20060043396 - Sapphire substrate, epitaxial substrate and semiconductor device: An epitaxial substrate for manufacturing field effect transistor (FET) that has heterojunction structure consisting of at least a channel layer made of gallium nitride or gallium indium nitride and a barrier layer made of aluminum gallium nitride formed successively on the principal plane of the sapphire substrate, wherein the principal...

20060043395 - Semiconductor light-emitting element and method of producing the same: There is provided a semiconductor light-emitting element and a method of producing the same including high density and high quality quantum dots emitting light at a wavelength of 1.3 μm. A semiconductor light-emitting element has a first GaAs layer, a second InAs thin film layer having the plurality of InAs...

20060043397 - Infra-red light-emitting device and method for preparing the same: The present infra-red light-emitting device includes a substrate with a first window layer, a silicon dioxide layer positioned on the first window layer, silicon nanocrystals distributed in the silicon dioxide layer, a second window layer, a transparent conductive layer and a first ohmic contact electrode positioned in sequence on the...

20060043398 - Light emitting diode with diffraction lattice: A method of fabricating light emitting diodes (LED) with a colour purifying diffraction lattice (CPDL) is suggested, the essence of the invention is in the use of the coherent scattering of the light by the CPDL for colour purifying of the light emitted by the LED and enhancement its extraction...

20060043400 - Polarized light emitting device: Light-emitting devices, and related components, processes, systems and methods are disclosed....

20060043399 - Semiconductor light emitting device: A semiconductor light emitting device comprises: a substrate; a light emitting layer; and an ohmic electrode. The substrate has first and second major surfaces and being transparent to light in a first wavelength band. The light emitting layer is provided above the first major surface of the substrate, and the...

20060043404 - Cap for semiconductor device: In a cap for a semiconductor device in which a light transmissive window is fixed to a cap body provided with a light transmissive opening using low-melting glass as a fixing material so that the light transmissive window covers the light transmissive opening, the low-melting glass is leadless vanadate-series low-melting...

20060043401 - High power light emitting diode package: The invention relates to a high power LED package, in which a package body is integrally formed with resin to have a recess for receiving an LED chip. A first sheet metal member is electrically connected with the LED chip, supports the LED chip at its upper partial portion in...

20060043402 - Light emitting device and light emitting element: A light emitting device having: a predetermined optical form that is provided on a surface of an LED element mounted on a base, the predetermined optical form being made to allow an increase in efficiency of taken out light from an inside of the LED element; and a sealing material...

20060043406 - Liquid crystal display device, illumination device backlight unit: A liquid crystal display device with a liquid crystal display panel and a backlight, the backlight is formed by stacking a lower electrode, a light emitting layer and an upper layer on one surface of a substrate, one of the lower electrode and the upper electrode have planer pattern, another...

20060043405 - Nitride-based compound semiconductor light emitting device: A nitride-based compound semiconductor light emitting device has a first ohmic electrode, a first bonding metal layer, a second bonding metal layer and a second ohmic electrode provided in this order on a conductive substrate, and also has a nitride-based compound semiconductor layer provided on the second ohmic electrode. A...

20060043403 - Organic light emitting device and method of fabricating the same: An organic light emitting device, and method of fabricating the same, in which a data line, a power line, or a data line and a power line of a unit pixel region are formed in a trench formed in an insulating layer. A first pixel electrode overlaps the trench....

20060043407 - Semiconductor light emitting apparatus: A semiconductor light emitting apparatus comprises: a first lead having a recess; a second lead; embedding resin that embeds therein a portion of the first lead and a portion of the second lead; a semiconductor light emitting device; a wire connecting the semiconductor light emitting device to the second lead;...

20060043410 - Light-emitting device and production method thereof: A light-emitting device is provided that is excellent in light emission efficiency and stability. The light-emitting device has a first part of a first dielectric constant, a second part of a second dielectric constant and a third part of a third dielectric constant, and has a triple junction where they...

20060043409 - Nitride semiconductor laser device and manufacturing method thereof: A nitride semiconductor laser device of the present invention has an electrical connection point which is provided outside of a pair of trenches in the surface of an upper electrode layer so as to make an electrical connection to the outside. The thickness between the surface of the upper electrode...

20060043408 - Semiconductor optical device: In a semiconductor optical device, a first conductive type semiconductor region includes first and second semiconductor portions. The first and second semiconductor portions are made of nitride mixed semiconductor crystal. This first semiconductor portion has a first region and a second region. The second semiconductor portion is provided on the...

20060043411 - Memory cell with trenched gated thyristor: One aspect of this disclosure relates to a memory cell. Various memory cell embodiments include an isolated semiconductor region separated from a bulk semiconductor region, an access transistor and a vertically-oriented thyristor formed in a trench extending between the isolated and bulk semiconductor regions. The access transistor includes a first...

20060043412 - Method and arrangement in connection with a half-controlled network bridge: A method and an arrangement for controlling phase-specific thyristors of a half-controlled network bridge, the method comprising identifying a thyristor to be controlled on the basis of the magnitude of phase voltage, controlling the thyristor by switching on a voltage in its gate current circuit to achieve a gate current....

20060043413 - Pressed-contact type semiconductor device: A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N−-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer...

20060043414 - Rectification chip terminal structure: A rectification chip terminal structure for soldering a rectification chip encased in a glass passivated pallet (GPP) on a terminal filled with a packaging material to form a secured mounting for the rectification chip is to be inserted in a coupling bore of a circuit board. The structure includes a...

20060043415 - Field-effect transistor: An electric-field control electrode (5) is formed between a gate electrode (2) and a drain electrode (3). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed below the electric-field control electrode (5). The SiN film (21) is formed so that a surface of an...

20060043416 - Recessed semiconductor device: A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second...

20060043417 - Semiconductor device: A semiconductor layer of n− type is formed on a semiconductor substrate of p− type. A first buried impurity region of n+ type is formed at an interface between the semiconductor substrate and the semiconductor layer. A second buried impurity region of p+ type is formed at an interface between...

20060043418 - Semiconductor device and method of manufacturing the same: A bipolar type semiconductor device capable of attaining high current gain and high cut-off frequency and performing a satisfactory transistor operation also in a high current region while maintaining a high breakdown voltage performance, as well as a method of manufacturing the semiconductor device, are provided. In a collector comprising...

20060043419 - Semiconductor substrate and semiconductor device manufactured by epitaxial growth on the semiconductor substrate: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1-100> direction lying in a...

20060043420 - Bitline structure and method for production thereof: The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made...

20060043423 - Lattice platforms for performing quantum computations: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the...

20060043421 - Multi-gate device with high k dielectric for channel top surface: A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the...

20060043422 - Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof: A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature extending from the source to the...

20060043424 - Enhanced pmos via transverse stress: In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel...

20060043425 - Semiconductor integrated circuit device which restricts an increase in the area of a chip, an increase in the number of lead terminals of a package, and can reduce parasitic inductance: A semiconductor integrated circuit device according to the present invention has a configuration where a GND line is shared by a first circuit block and a second circuit block from among a number of circuit blocks provided on a semiconductor substrate, where the first circuit block and the second circuit...

20060043426 - Method and apparatus for calculating wiring capacitance, and computer product: A diagonal-capacitance calculating unit calculates diagonal capacitance based on the adjacent wirings in diagonally upward and downward direction from a target wiring. A basic-capacitance correcting unit corrects basic capacitance, which is wiring capacitance based on adjacent wirings in above, below, on a left of, and on a right of the...

20060043427 - Automatic-arrangement-wiring apparatus for and program for performing layout of integrated circuit: An automatic-arrangement-wiring apparatus is provided with a calculating unit for calculating the lowest transfer rate and a corresponding repeater-to-repeater distance for each of wiring layers having different time constants, an arrangement unit or carrying out automatic arrangement, an estimating unit for estimating the wire length of each of wiring routes...

20060043428 - Semiconductor devices and optical semiconductor relay devices using same: Power MISFET 20 includes SIO substrate 4 composed of first silicon substrate 1, BOX layer 2 formed on the front surface of first silicon substrate 1 and silicon substrate 3 formed on BOX layer 2. Second silicon substrate 3 is provided with lightly doped-impurity offset layer 5, P layer 6,...

20060043429 - Contact structure and contact liner process: A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a conductive spacer liner that effectively prevents the contact structure...

20060043431 - Memory array with overlapping buried digit line and active area and method for forming same: A memory cell, array and device include an active area formed in the substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the...

20060043430 - Transistor having an asymmetric source/drain and halo implantation region and a method of forming the same: By providing an asymmetric design of a halo region and extension regions of a field effect transistor, the transistor performance may significantly be enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the...

20060043432 - Thin-layer chemical transistor and making method: In a thin-layer chemical transistor having a metal/solid electrolyte/semiconductor structure, the materials of which the solid electrolyte and semiconductor layers are made comprise organic solvent-soluble compounds. The transistor can be fabricated solely by solvent processes, typically printing techniques including ink jet printing....

20060043433 - Light-emitting diode: A light-emitting diode 10A has a light-emitting element 11a fixed to a leadframe 30 with a conductive adhesive material 20, the light-emitting element 11a having a semiconductor layer 9 including a light-emitting layer 16 laid on a first surface 12a of a translucent substrate 12, a second surface 12b thereof...

20060043435 - Nano-scaled gate structure with self-interconnect capabilities: Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device...

20060043434 - Semiconductor devices and methods of manufacture thereof: A semiconductor device, for example a MOSFET or IGBT, includes a region (30, 36, 50) in the drain drift region (14) juxtaposed with its channel-accommodating region (15) and spaced from the drain contact region (14a) by means of an intermediate portion of the drift region. The region comprises alternating stripes...

20060043436 - Contacts for cmos imagers and method of formation: Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a leakage sensitive area of a CMOS imager. The polysilicon contact comprises a polysilicon region in direct contact...

20060043439 - Image pickup device and camera: An object is to provide a solid state image pickup device and a camera which do not worsen a sensor performance in terms of an optical property, a saturated charge amount and the like. A solid state image sensor including a pixel region having a plurality of pixels includes at...

20060043440 - Imaging device and imaging system: An object of the present invention is to prevent a sensitivity difference between pixels. There are disposed plural unit cells each including plural photodiodes 101A and 101B, plural transfer MOSFETs 102A and 102B arranged corresponding to the plural photodiodes, respectively, and a common MOSFET 104 which amplifies and outputs signals...

20060043438 - Integrated photoserver for cmos imagers: An exemplary system and method for providing an integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS host wafer (460) bonded with a monocrystalline, optically active donor wafer (300); a photosensing element (390) integrated in said optically active donor...

20060043437 - Transparent metal shielded isolation for image sensors: An isolation region formed in a substrate and lined with a transparent metal layer. The isolation region provides isolation between adjacent active areas of an integrated circuit structure, for example the inventive region may provide isolation between pixels of a pixel array. Utilizing a transparent material maintains high quantum efficiency...

20060043441 - Device for subtracting or adding charge in a charge-coupled device: The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a “wire transfer” device structure to perform the addition or subtraction of charge during the charge packets traversal across...

20060043442 - Photoelectric conversion device, method for manufacturing the same and image pickup system: An object of the present invention is to provide a photoelectric conversion device, wherein improvement of charge transfer properties when charge is output from a charge storage region and suppression of dark current generation during charge storage are compatible with each other. This object is achieved by forming a depletion...

20060043446 - Ferroelectric memory and its manufacturing method: To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes...

20060043445 - Semiconductor device and method for manufacturing the same: A lower electrode film is formed above a semiconductor substrate first, and then a ferroelectric film is formed on the lower electrode film. After that, an upper electrode film is formed on the ferroelectric film. When forming the upper electrode, an IrOx film containing crystallized small crystals when formed is...

20060043443 - Spin transistor using spin-filter effect and nonvolatile memory using spin transistor: A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due...

20060043444 - Thin film device and a method of formation thereof: An aspect of the present invention is a thin film device. The thin film device includes at least one patterned thin film layer, a thermally conductive material coupled to at least one of the patterned thin-film layer and an electrically and thermally isolating material in contact with the thermally conductive...

20060043447 - Thin film transistor having an etching protection film and manufacturing method thereof: A thin film transistor of the present invention includes a semiconductor thin film (8); a gate insulating film (7) formed on one surface of the semiconductor thin film (8); a gate electrode (6) formed to be opposite to the semiconductor thin film (8) through the gate insulating film (7); a...

20060043448 - Dielectric relaxation memory: A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as...

20060043449 - Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate...

20060043450 - Vertical transistors: Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the lower active area. Vertical transistor pillars can be formed from epitaxial silicon or etched from bulk silicon. Memory cells...

20060043451 - Method for obtaining extreme selectivity of metal nitrides and metal oxides: Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H2F2. The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride....

20060043452 - Ferroelectric memory and its manufacturing method: A ferroelectric memory includes a base member, a dielectric layer formed above the base member, a contact hole that penetrates the dielectric layer, a plug formed inside the contact hole, a barrier layer formed above the plug, and including a first portion with a portion formed in the contact hole...

20060043453 - Semiconductor devices: The invention includes semiconductor devices. In one implementation, semiconductor device includes a first conductive material. A first layer of a dielectric material is over the first conductive material. A second layer of the dielectric material is on the first layer. A second conductive material is over the second layer of...

20060043454 - Mos varactor using isolation well: The present invention provides a varactor that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes...

20060043455 - Multiple-depth sti trenches in integrated circuit fabrication: Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a...

20060043457 - Nonvolatile semiconductor memory device having a recessed gate and a charge trapping layer and methods of forming the same, and methods of operating the same: A nonvolatile semiconductor memory device includes a substrate having a trench therein, a gate electrode in the trench, and a plurality of source/drain regions in the substrate adjacent the gate electrode. A pair of channel regions extends along sidewalls of the trench between respective pairs of adjacent source/drain regions. A...

20060043456 - Protection of tunnel dielectric using epitaxial silicon: Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containing layers on opposing sides of the tunnel...

20060043460 - Exposure system, semiconductor device, and method for fabricating the semiconductor device: In order to link a defect inspection process before forming contact holes with an exposure process for forming the contact holes, a position (physical coordinates) of a defect on a wafer is stored, the defect having been detected in the defect inspection process before forming the contact holes, an exposure...

20060043458 - Gate coupling in floating-gate memory cells: Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic capacitance. The stepped structure results in a reduced surface area of a first floating gate in close proximity to an adjacent floating gate with substantially no reduction in coupling area,...

20060043459 - Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same: A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the...

20060043461 - Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure: A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps: defining on a same semiconductor substrate...

20060043464 - Direct tunneling semiconductor memory device and fabrication process thereof: A direct-tunneling semiconductor memory device includes a device isolation structure formed on a semiconductor substrate, including a device isolation trench and a device isolation insulation film filling the device isolation trench, a dielectric film covering both sidewall surfaces and a top surface of a floating gate electrode formed on the...

20060043463 - Floating gate having enhanced charge retention: A semiconductor device includes a source and a drain formed in a substrate, a tunneling dielectric formed on the substrate between the source and the drain, and a floating gate disposed over the tunneling dielectric having a band-gap energy less than the energy band-gap of silicon....

20060043465 - Semiconductor device and method of manufacturing the same: An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion below the floating gate electrode. The first insulating film...

20060043462 - Stepped gate configuration for non-volatile memory: A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor...

20060043466 - Stepped gate configuration for non-volatile memory: A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor...

20060043467 - Stepped gate configuration for non-volatile memory: A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor...

20060043468 - Stepped gate configuration for non-volatile memory: A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor...

20060043469 - Sonos memory cell and method of forming the same: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and a method of forming the same are disclosed. The SONOS memory cell includes a substrate in which a recessed region having at least one side wall is arranged and a trap storage pattern with which the recessed region is filled with a first insulating...

20060043470 - Method for producing a buried n-doped semiconductor zone in a semiconductor body and semiconductor component: A method for producing a buried n-doped semiconductor zone in a semiconductor body. In one embodiment, the method includes producing an oxygen concentration at least in the region to be doped in the semiconductor body. The semiconductor body is irradiated via one side with nondoping particles for producing defects in...

20060043471 - Vertical transistor structures having vertical-surrounding-gates with self-aligned features: The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in...

20060043472 - High density access transistor having increased channel width and methods of fabricating such devices: A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to...

20060043473 - Memory cell, array, device and system with overlapping buried digit line and active area and method for forming same: A memory cell, array and device include an active area formed in the substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the...

20060043474 - Top drain mosgated device and process of manufacture therefor: A trench type top drain MOSgated device has a drain electrode on the die top and a source electrode on the die bottom surface. The device is turned on by a control voltage connected between a drain and a gate region. The device cell has a body short trench and...

20060043475 - Semiconductor device: A semiconductor device includes a P diffusion region formed in the surface of an N− epitaxial layer apart from other P diffusion regions; an N+ diffusion region formed in the surface of the P diffusion region so as to be surrounded by the P diffusion region; a second collector electrode...

20060043476 - Junction varactor with high q factor: A junction varactor includes a gate finger lying across an ion well of a semiconductor substrate; a gate dielectric situated between the gate finger and the ion well; a first ion diffusion region with first conductivity type located in the ion well at one side of the gate finger, the...

20060043477 - Interposers for chip-scale packages and intermediates thereof: A carrier substrate, or interposer, for use in a chip-scale package includes a material, such as a semiconductive material, that has a coefficient of thermal expansion that is the same or similar to that of the semiconductor device to be secured thereto. The interposer may also include a rerouting element...

20060043478 - Semiconductor device having super junction structure and method for manufacturing the same: A semiconductor device includes: a center region; a periphery region; and a semiconductor layer including pairs of a first region having a first impurity amount and a second region having a second impurity amount. The first and the second regions are alternately aligned in a plane. The periphery region includes...

20060043479 - Metal oxide semiconductor device including a shielding structure for low gate-drain capacitance: A semiconductor MOSFET device (70, 100), and method of fabricating the device, including a shielding structure (86, 210) for decreasing the gate-drain capacitance (CGD) without simultaneously increasing the gate resistance or the total device ON-state resistance (RDSON). The shielding structure (86, 210) is formed between a drain region (76, 106)...

20060043480 - Semiconductor device and fabrication method of the same: A semiconductor device comprises a semiconductor layer which includes a terminate end part and a cell formation part that is surrounded by this end part, and a plurality of guard rings each of which is formed at the end part to surround the cell formation part. These guard rings are...

20060043481 - Semiconductor device and method of manufacturing the same: A first semiconductor pillar layer of a first conductivity type is formed on a main surface of a semiconductor substrate of the first conductivity type. A second semiconductor pillar layer of a second conductivity type is formed adjacent to the first semiconductor pillar layer. A third semiconductor pillar layer of...

20060043482 - Programming and erasing structure for an nvm cell: A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is formed by first forming a cavity in the substrate in the drain location. SiGe is epitaxially grown in the...

20060043483 - Bonding of substrates: In one embodiment, a method comprises placing a first and a second substrate into a reaction chamber, the first substrate being made of an indium antimonide material and having a first surface and the second substrate being made of a silicon or a silicon dioxide material and having a second...

20060043485 - Method for fabricating semiconductor device and semiconductor device: A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first...

20060043484 - Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk mosfets and for shallow junctions: A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide...

20060043486 - Electro-optical device and manufacturing method thereof: A semiconductor device that uses a high reliability TFT structure is provided. The gate electrode of an n-channel type TFT is formed by a first gate electrode and a second gate electrode that covers the first gate electrode. LDD regions have portions that overlap the second gate electrode through a...

20060043487 - Bi-directional esd protection circuit: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node...

20060043489 - Diode and applications thereof: A diode with low substrate current leakage and suitable for BiCMOS process technology. A buried layer is formed on a semiconductor substrate. A connection region and well contact the buried layer. Isolation regions are adjacent to two sides of the buried layer, each deeper than the buried layer. The isolation...

20060043490 - Electrostatic discharge (esd) detection and protection: A system and method are provided for protecting a transistor from electrostatic discharge (ESD) current associated with an ESD event. In one embodiment, a system comprises a detection circuit operative to detect an ESD event and a switch that is operative to hold the transistor in a deactivated state in...

20060043491 - Electrostatic discharge protection device and method for its manufacture: Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode...

20060043488 - Method and system for a programmable electrostatic discharge (esd) protection circuit: An electrostatic discharge (ESD) protection device is disclosed. The ESD protection device comprises a source diffusion in a substrate and a deeper body diffusion in the substrate. The ESD protection device further includes a gate function provided at a space between the source diffusion and the body diffusion surface terminations;...

20060043492 - Ruthenium gate for a lanthanide oxide dielectric layer: A ruthenium gate for a lanthanide oxide dielectric layer and a method of fabricating such a combination gate and dielectric layer produce a reliable structure for use in a variety of electronic devices. The lanthanide oxide dielectric layer is formed by depositing lanthanum by atomic layer deposition onto a substrate...

20060043493 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a first gate insulating film formed on a first nMOS transistor region in a semiconductor substrate; a second gate insulating film formed on a first pMOS transistor region in the substrate; a third gate insulating film formed on a second nMOS transistor region in the substrate;...

20060043494 - Semiconductor device and method of manufacturing semiconductor device: A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between...

20060043495 - Semiconductor device: In an n-channel type power MISFET, a source electrode in contact with an n+-semiconductor region (source region) and a p+-semiconductor region (back gate contact region) is constituted with an Al film and an underlying barrier film comprised of MoSi2, use of the material having higher barrier height relation to n-Si...

20060043497 - Semiconductor device: Threshold voltage of a field effect transistor is successfully adjusted with a smaller dose of an impurity, as compared with a conventional adjustment of the threshold voltage only by doping an impurity into the channel region. A semiconductor device 100 has a silicon substrate 101 and a P-type MOSFET 103...

20060043496 - Semiconductor device and method for fabricating the same: A semiconductor device includes: an active region formed in a substrate and surrounded with an isolation formed in the substrate; a gate electrode formed above the active region and made of a semiconductor material; and an interconnect formed on the isolation and in the same layer as the gate electrode...

20060043498 - Method and apparatus for performance enhancement in an asymmetrical semiconductor device: A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second current region (75, 33, 66) has a content of...

20060043499 - Bi-directional double nmos switch: A semiconductor switch comprises two NMOS transistors coupled in an anti-series arrangement, and a gate control circuit coupled to both gates of the NMOS transistors. Both drains of the NMOS transistors are interconnected, and the gate control circuit is coupled to the drains interconnection. The required chip area is halved...

20060043501 - Nitride semiconductor device: In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN)...

20060043502 - Structure and method to fabricate finfet devices: There is provided a method for fabricating a FinFET in which a self-limiting reaction is employed to produce a unique and useful structure that may be detectable with simple failure analysis techniques. The structure is an improved vertical fin with a gently sloping base portion that is sufficient to reduce...

20060043500 - Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof: A transistor comprises an active region having a periphery with opposing sides and a source and a drain positioned within the active region. A gate overlies a channel area of the active region, the channel region separating the source and drain. The transistor further includes at least one stress modifying...

20060043503 - Semiconductor constructions: The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segments of dielectric material, with the thin and thicker segments of...

20060043504 - Atomic layer deposited titanium aluminum oxide films: A dielectric layer containing an atomic layer deposited insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric layer produce a reliable dielectric layer for use in a variety of electronic devices. Embodiments include conducting a number of annealing processes between a number of...

20060043505 - Semiconductor constructions, and methods of forming gatelines and transistor devices: The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segments of dielectric material, with the thin and thicker segments of...

20060043506 - Boron phosphide-based compound semiconductor device, production method thereof and light-emitting diode: A boron phosphide-based compound semiconductor device with excellent device properties, comprising a boron phosphide-based compound semiconductor layer having a wide bandgap is provided. The boron phosphide-based compound semiconductor layer consists of an amorphous layer and a polycrystal layer provided to join with the amorphous layer, and the room-temperature bandgap of...

20060043507 - Bulk acoustic wave resonator with means for suppression of pass-band ripple in bulk acoustic wave filters: A bulk acoustic wave resonator comprising a substrate (5), a Bragg reflector (4), a top (1) and a bottom (3) electrode and a piezoelectric layer (2) with means for suppression of the pass-band ripples in a bulk acoustic wave filter. The means for absorbing or scattering the spurious modes are...

20060043508 - Apparatus for measuring a mechanical quantity: A mechanical quantity measuring apparatus is provided which can make highly precise measurements and is not easily affected by noise even when it is supplied an electricity through electromagnetic induction or microwaves. At least a strain sensor and an amplifier, an analog/digital converter, a rectification/detection/modulation-demodulation circuit, and a communication control...

20060043509 - Packaged microelectronic imaging devices and methods of packaging microelectronic imaging devices: Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, a microelectronic imaging device includes a microelectronic die having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit. The imaging...

20060043510 - Display device and method for manufacturing the same: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle...

20060043511 - Solid state image pickup device and its manufacture method: A solid state image pickup device is provided which includes: charge accumulation regions disposed in a semiconductor substrate in a matrix shape; a plurality of vertical transfer channels formed in the semiconductor substrate each in a close proximity to each column of the charge accumulation regions; vertical transfer electrodes formed...

20060043513 - Method of making camera module in wafer level: A plurality of photo-sensing device packages are provided. The packages are formed on unit substrate portions of a substrate to each include at least one photo-sensing semiconductor die. The substrate is formed of a material substantially transparent to light within a predetermined range of wavelengths, with each unit substrate portion...

20060043512 - Microelectronic imagers with optical devices having integral reference features and methods for manufacturing such microelectronic imagers: Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed herein. In one embodiment, the imager assembly can include a workpiece with a substrate having a front side, a back side, and a plurality of imaging dies on and/or in the...

20060043514 - Semiconductor device with simplified constitution: An image-capturing semiconductor device is provided with a simplified constitution and by means of fewer steps than conventional techniques. In a semiconductor device which is packaged at substantially identical outer dimensions to the outer dimensions of a first semiconductor chip, first pads serving as electrode pads are formed along a...

20060043515 - Light block for pixel arrays: Imager devices are formed with light block material between microlenses to enhance the characteristics of image acquisition. The light block material may be deposited over the lenses, and then partially removed to expose central portions of the lenses. The invention is applicable to, among other things, imager devices having pixel...

20060043516 - Transistor integrated circuit apparatus: A transistor integrated circuit apparatus generating less noise, having superb RF characteristics, and preventing thermal runaway of transistors is provided. Owing to capacitors C11 through C1n having one end commonly connected to an RF signal input terminal RFin and the other end connected to a base electrode of a corresponding...

20060043518 - Semiconductor photoreceptor device and manufacturing method therefor: A semiconductor light detecting device includes an n-contact layer selectively disposed on an Fe—InP substrate. An optical waveguide layer is disposed on the n-contact layer and includes an n-cladding layer, a light absorption layer, and a p-cladding layer, laminated on one another, over the n-contact layer, in that order. An...

20060043517 - Stacked photoelectric converter: In a stacked-layer type photoelectric conversion device, a plurality of photoelectric conversion units are stacked on a substrate, each of which includes a one conductivity-type layer, a photoelectric conversion layer of substantially intrinsic semiconductor and an opposite conductivity-type layer in this order from a light-incident side. At least one of...

20060043519 - Solid-state imaging device, camera module and electronic equipment module: To provide a back-illuminated type solid-state imaging device capable of color separation of pixels without using a color filter, and a camera module and an electronic equipment module which incorporate the solid-state imaging device. A solid-state imaging device including: a photoelectric conversion element PD formed in a semiconductor substrate 22;...

20060043520 - Active photosensitive structure with buried depletion layer: An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a resistance characteristic that changes depending on the level of accumulated charge in the accumulation region. During an integration period, incident light causes electrons to be accumulated...

20060043521 - Liner for shallow trench isolation: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the...

20060043522 - Dual depth trench isolation: A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench...

20060043523 - Electronic device and the production method: An electronic device having an element body, wherein dielectric layers and internal electrode layers are alternately stacked, wherein a hetero phase is formed in the dielectric layers and/or the internal electrode layers; and the hetero phase includes a Mg element and a Mn element. Preferably, the hetero phase is formed...

20060043524 - Versatile system for triple-gated transistors with engineered corners: The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop...

20060043525 - Isolation techniques for reducing dark current in cmos image sensors: A structure for isolating areas in a semiconductor device is provided. The structure includes a trench having first and second portions formed in a substrate. The first portion has a first width, and the second portion has a second width and is below the first portion. The first width is...

20060043526 - Lateral programmable polysilicon structure incorporating polysilicon blocking diode: A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of...

20060043527 - Capacitor: The present invention relates to a capacitor having a configuration in which capacitors are coupled in series to each other. The capacitor formed on a substrate according to an exemplary embodiment of the present invention includes: a polysilicon layer doped with an impurity; a first insulation layer formed on the...

20060043529 - Bipolar transistor with extrinsic stress layer: A method of increasing mobility of charge carriers in a bipolar device comprises the steps of: creating compressive strain in the device to increase mobility of holes in an intrinsic base of the device; and creating tensile strain in the device to increase mobility of electrons in the intrinsic base...

20060043528 - Lateral pnp transistor and the method of manufacturing the same: The present invention relates to a lateral PNP transistor and the method of manufacturing the same. The medium doping N-type base area and the light doping P− collector area were first introduced in the structure before the formation of P+ doping emitter area and the collector area. The emitter-base-collector doping...

20060043530 - Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for soi bicmos with reduced buried oxide thickness for low-substrate bias operation: The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at...

20060043531 - Reduction of source and drain parasitic capacitance in cmos devices: A method for fabricating a semiconductor-based device includes providing a doped semiconductor substrate, introducing a second dopant into the substrate to define a pn junction, and introducing a neutralizing species into the substrate in the neighborhood of the pn junction to reduce a capacitance associated with the pn junction. A...

20060043534 - Microfeature dies with porous regions, and associated methods and systems: Microfeature dies with porous regions, and associated methods and systems are disclosed. A method in accordance with one embodiment of the invention includes forming a porous region between a die and a remainder portion of a microfeature workpiece, and separating the die from the remainder portion by removing at least...

20060043532 - Protective structure of semiconductor wafer, method for protecting semiconductor wafer, multilayer protective sheet used therein, and method for processing semiconductor wafer: A semiconductor wafer protection structure including a semiconductor wafer and a protective sheet overlaid on a circuit surface of the semiconductor wafer, wherein the protective sheet has a larger diameter than the outer diameter of the semiconductor wafer. Semiconductor wafer protection structures and methods, and laminated protective sheet for use...

20060043533 - Wafer backside removal to complete through-holes and provide wafer singulation during the formation of a semiconductor device: A method used to form a semiconductor device comprises processing a semiconductor wafer to include one or more vias or through-holes only partially etched into the wafer, and scribe marks only partially etched into the wafer which define a plurality of semiconductor devices. Wafer material is removed from the back...

20060043535 - Pass through via technology for use during the manufacture of a semiconductor device: A method for forming vias which pass through a semiconductor wafer substrate assembly such as a semiconductor die or wafer allows two different types of connections to be formed during a single formation process. One connection passes through the wafer without being electrically coupled to the wafer, while the other...

20060043536 - Implanted photoresist to reduce etch erosion during the formation of a semiconductor device: A method for forming a semiconductor device comprises forming a layer to be etched, and forming a patterned photoresist layer over the layer to be etched. The patterned photoresist layer is treated prior to etching, for example by implantation with argon or nitrogen. This treatment reduces the volume of the...

20060043537 - Routing differential signal lines in a substrate: A method for routing signals in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with at least one differential signal line pair aligned along a common plane that is substantially transverse to a top surface of the multilayer substrate, jogging a first...

20060043538 - Bump structure of an opto-electronic chip: An opto-electronic chip includes a plurality of multi-level bumps thereon, each consisting of multiple plated layers. The opto-electronic chip has a plurality of bonding pads and an photoelectric effecting region on its active surface. Each multi-level bump comprises at least an electroless-plated nickel (Ni) layer and an electroless-plated gold (Au)...

20060043539 - Electronic component comprising a multilayer wiring frame and method for producing the same: The invention relates to an electronic component having a multilayered rewiring plate, which carries a circuit chip, in particular a magnetic memory chip, and connects contact areas of the chip to external contacts of the electronic component via rewiring lines. The rewiring plate has at least one patterned, magnetic shielding...

20060043540 - Silicon package for piezoelectric device: A hermetic package for electronic components which is made of metallic silicon is disclosed. The package creates a cavity for receiving the electronic component, preferably a piezoelectric device, which provides a evacuated environment in the range of 1×10−5 to 1×10−11 torr. In a first embodiment, the single crystal metallic silicon...

20060043541 - Method and apparatus for implementing a co-axial wire in a semiconductor chip: A coaxial shield for a semiconductor chip includes: a top vertical shield wire formed in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield; a first side shield wire formed in an intermediate metal layer of...

20060043542 - Floating lead finger on a lead frame, method of making, and lead frame strip and lead frame assembly including same: A semiconductor device assembly includes a semiconductor device and a lead frame having lead fingers for connection to the semiconductor device. The lead frame may include floating NC lead fingers with inner portions of the floating NC lead fingers electrically isolated from the semiconductor device and the associated outer portion...

20060043544 - Semiconductor device, semiconductor module, and manufacturing method of semiconductor device: An imaging device as a semiconductor device includes a semiconductor substrate on which an imaging element is mounted, a light-transmitting lid section (covering section) arranged to face a light receiving section provided on one surface of the imaging element, and an adhesive layer arranged in an area excluding the light...

20060043545 - Smt three phase inverter package and lead frame: A surface mounted package for semiconductor die has a lead frame with a first and elongated die pad which receives three MOSgated die spaced along its length; second, third and fourth die pads laterally spaced from the first die pad and in a row parallel to the first die pad...

20060043543 - Solder composition, connecting process with soldering, and connection structure with soldering: There is provided a solder composition which contains: (1) a metal material comprising solder particles, and (2) a thermosetting flux material comprising a thermosetting resin and a solid resin which changes to be in its liquid-like state when heated with a proviso that the thermosetting resin is excluded from the...

20060043546 - Optoelectronic component and housing: Disclosed is a housing for an optoelectronic component comprising a reflector and a heat dissipating element, wherein the housing comprises a mounting portion with at least one mounting area for mounting a semiconductor chip or a component provided with at least one semiconductor chip, plus at least one reflector wall...

20060043553 - Chip package having a heat spreader and method for packaging the same: A chip package mainly includes a substrate, a stiffener, a chip, a thermal interface material (TIM) and a heat spreader. The stiffener is disposed on the substrate and has a receiving portion. The chip is disposed on the substrate. The thermal interface material (TIM) is formed on a surface of...

20060043547 - Circuit board and method for producing a circuit board: A circuit board comprises a dielectric layer, a net of first power supply lines for providing a first reference voltage plane and a net of second power supply lines for providing a second reference voltage plane. The nets of first and second power supply lines are arranged such that first...

20060043551 - Electronic control device: A circuit board mounting electronic components including a heat generating element is accommodated in a casing. A heat dissipation member is disposed between the heat generating element and an inner surface of the casing. The heat dissipation member is thermally bonded to the heat generating element and to the casing....

20060043550 - Hermetic semiconductor package: A hermetically sealed semiconductor package that includes a power semiconductor die having electrodes thereof electrically connected to the external surface mountable terminals of the package without the use of wirebonds....

20060043554 - Method of making a semiconductor device adapted to remove noise from a signal: What is invented is a semiconductor device (10) comprising a pellet (12) having a ground electrode (18), an outside signal terminal (15) connected to the pellet (12), so as to receive signal which is likely to include noise. Therein, said outside signal terminal (15) is surrounded with a ground terminal...

20060043549 - Micro-electronic package structure and method for fabricating the same: A micro-electronic package structure and a method for fabricating the same are proposed. A carrier is prepared and provided with a cavity for receiving at least one semiconductor chip having a plurality of electrical connection contacts. A dielectric layer is formed on the carrier, with the electrical connection contacts being...

20060043552 - Semiconductor device and process for manufacturing the same: The present invention relates to a semiconductor device in which electrodes formed on a semiconductor chip and electrodes formed on a wiring board are electrically connected via projecting elastic electrodes, and further relates to a mounting method of reducing a pressure applied to electrodes formed on a substrate or underlying...

20060043548 - Semiconductor device having stiffener: A semiconductor device includes a substrate, a semiconductor element mounted on the substrate and a stiffener attached via an adhesive to a surface of the substrate opposite to a surface thereof on which the semiconductor element is mounted. The adhesive has a coefficient of thermal expansion smaller than that of...

20060043555 - Sensor package: An image sensor package includes a bottom substrate, a transparent substrate, a plurality of spacers and adhesive. The bottom substrate includes a plurality of chips, which each includes an active surface and an image sensor disposed on the active surface. The transparent substrate includes a plurality of transparent substrate units...

20060043557 - Apparatus for improved power distribution in wirebond semiconductor packages: A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and electrically coupled to a metal apparatus adjacent the substrate and the die using a plurality of bond wires. The metal apparatus supplies power to the conducting...

20060043562 - Circuit device and manufacture method for circuit device: There is provided a circuit device including a plurality of circuit blocks, wherein: on one surface of an insulating sheet having flexibility, a first and a second wiring patterns are formed, the second wiring pattern including a plurality of divisionally disposed patterns and electrically connected to the first wiring pattern;...

20060043560 - Multichip module package and fabrication method: A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor...

20060043561 - Semiconductor apparatus having stacked semiconductor components: The present invention provides an apparatus having stacked semiconductor components. Two semiconductor components (21, 26) are arranged such that their contact regions (28, 22) are opposite one another. A contact-connection device (29) forms a short electrical connection between the two contact regions (28, 22). The contact regions (28, 22) are...

20060043559 - Stacked die packaging and fabrication method: A semiconductor package includes a substrate. A crenellated spacer is attached to the substrate. At least one top die is attached to the crenellated spacer. The at least one top die is wire bonded to the substrate, and an encapsulant is formed over the crenellated spacer and the at least...

20060043558 - Stacked integrated circuit cascade signaling system and method: Integrated circuits (ICs) are stacked into modules that conserve PCB or other board surface area. The modules provide for lower capacitance memory signaling systems and methods for connecting stacked CSPs in a serial cascade arrangement. In one preferred embodiment, on-die terminations are used selectively to terminate a cascaded...

20060043563 - Stacked microelectronic layer and module with three-axis channel t-connects: A method for interconnecting stacked layers containing integrated circuit die and a device built from the method is disclosed. The stacked layers are bonded together to form a module whereby individual I/O pads of the integrated circuit die are rerouted to at least one edge of the module. The rerouted...

20060043556 - Stacked packaging methods and structures: A packaging method and structures are disclosed. A first die is mounted on a package substrate. A chip scale package is mounted on the first die. The chip scale package comprises a chip scale package substrate and a second die mounted on a first surface of the chip scale package...

20060043564 - Air pocket resistant semiconductor package: A die is attached to a substrate and is enclosed in a heat spreader, the heat spreader having a first encapsulant guide and a heat spreader air vent in the heat spreader extending therethrough. An encapsulant encapsulates the die, the substrate, at least a portion of the heat spreader, the...

20060043566 - Electronic component package: An electronic component package includes an electronic component substrate disposed on a dice pad, a plurality of leads disposed around the dice pad, wires connecting the leads and signal pads of the electronic component substrate, and a molding resin for sealing the dice pad, the electronic component substrate, and the...

20060043565 - Laser removal of plating tails for high speed packages: A method wherein a substrate with plating tails is formed or otherwise provided, such as by performing a conventional electroplating process. Subsequently, a laser is used to remove some or all of the plating tails or a portion of some or all of the plating tails. If portions or remnants...

20060043567 - Substrate having a functionally gradient coefficient of thermal expansion: A substrate and a method of making a substrate having a functionally gradient coefficient of thermal expansion are described herein. A system having a silicon die, an organic package substrate, and a substrate having a functionally gradient coefficient of thermal expansion, connecting the silicon die and the organic substrate is...

20060043569 - Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies: Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the active surface devices of a semiconductor substrate using through wafer interconnects (TWIs). The TWIs may be formed prior to forming the RDLs, after forming the RDLs, or substantially...

20060043568 - Semiconductor device having multilayer printed wiring board and manufacturing method of the same: A semiconductor device includes a support body, a first substrate provided on a surface at one side of the support body, a second substrate provided on a surface at the other side of the support body, and a semiconductor chip provided on the first substrate exposed to an opening part...

20060043570 - Substrate, semiconductor device, substrate fabricating method, and semiconductor device fabricating method: A semiconductor element having a first external connection terminal is connected to a substrate. The substrate includes a base material and a wiring portion, positioned at the first surface side of the base material. This configuration facilitates the realization of the connection between the first external connection terminal and the...

20060043571 - Multilayer silicon over insulator device: An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least another device. Where the multilayer SOI device has a first...

20060043573 - Semiconductor and method for producing a semiconductor: A semiconductor device comprises at least one first semiconductor component being located in a first plane and comprising an active area which has a first contact region and at least one second semiconductor component being located in a second plane and comprising a second active area which has a second...

20060043572 - Wiring board: A wiring board comprising: a plate core having a first main surface and a second main surface; conductor layers including a conductor line; dielectric layers laminated alternately with said conductor layers on at least one of said first and second main surfaces; via conductors as defined herein; a signal through-hole...

20060043574 - Aluminum/ceramic bonding substrate: There is provided an aluminum/ceramic bonding substrate having a high reliability to high-temperature heat cycles. An aluminum member of an aluminum alloy having a Vickers hardness of 35 to 45 is bonded to a ceramic substrate having a flexural strength of 500 to 600 MPa in three-point bending. The ceramic...

20060043575 - Chip module: A chip module including a chip having an integrated circuit and a stiffening element which is connected to the chip. The stiffening element includes a first part which extends parallel to the connection plane of the chip, and at least one second part which extends at an angle to the...

20060043578 - Semiconductor device having heat sink: A semiconductor device, which may include a heat sink using a thermal induced adhesive is provided. The adhesive strength of the thermal induced adhesive at room temperature may be reduced when heated. The thermal induced adhesive may attach the heat sink to the semiconductor device, and may result in a...

20060043577 - Structure and process of semiconductor package with an exposed heatsink: A structure and a process of semiconductor package with an exposed heatsink not only reduces the mold-clamping force acted on the chip but also improves the heat-dissipation by the heatsink directly adhered on the chip. Furthermore, the reliability of the semiconductor package is also improved. The structure of semiconductor package...

20060043576 - Structures and methods for heat dissipation of semiconductor integrated circuits: Structures and methods for semiconductor integrated circuits with respect to heat dissipation are provided. The structure comprises a die having a first surface and a second surface. The first surface has an opening in it, and the second surface has a contact pad formed on it. The first surface is...

20060043580 - Bandpass filter within a multilayerd low temperature co-fired ceramic substrate: A compact bandpass filter within a multilayered low temperature co-fired ceramic (LTCC) substrate is provided. Each resonator comprises an inductor and a capacitor connected in parallel. A top ceramic substrate comprises a top conductive plate to form a first RF ground plane. A bottom ceramic substrate comprises a bottom conductive...

20060043579 - Transistor performance enhancement using engineered strains: A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die....

20060043581 - Ic package with power and singal lines on opposing sides: A package for integrated circuits is described. The package has a package substrate with a land side and an opposite die side, a first set of low level signal connectors on the die side to connect to an IC to be carried by the package, and a second set of...

20060043582 - Method for heat dissipation on semiconductor device: A device and method wherein a thermo electric generator device is disposed between stacks of a multiple level device, or is provided on or under a die of a package and is conductively connected to the package. The thermo electric generator device is configured to generate a voltage by converting...

20060043583 - Semiconductor device: A semiconductor device is disclosed that includes a semiconductor element, a circuit board electrically connected to the semiconductor element, a heat dissipation member fixed to the first surface of the circuit board and thermally coupled to the semiconductor element, and an interposer provided to the second surface of the circuit...

20060043584 - Device and method for applying semiconductor chips to carriers: The invention relates to a device and a method for applying semiconductor chips (5) to a plurality of carriers (4), especially smart card modules or flexboards. According to the invention, an adhesive application device (1) is used to apply an adhesive to pre-defined positions on the carrier (4), a fitting...

20060043585 - Semiconductor device, substrate, equipment board, method for producing semiconductor device, and semiconductor chip for communication: A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting...

20060043587 - Apparatus and method for reducing signal cross talk between wire bonds of semiconductor packages: A semiconductor package for reducing signal cross talk between wire bonds of semiconductor packages by using a tier of input-output power bond pads between two tiers of signal bond pads. The package includes a substrate having a first surface and a second surface and a die attach area on the...

20060043586 - Board level solder joint support for bga packages under heatsink compression: A system comprising a ball grid array (“BGA”) substrate adapted to electrically couple to an application board using a plurality of solder balls, and a film adapted to abut the application board and the BGA substrate, the film comprising a plurality of perforations, the solder balls adapted to couple to...

20060043589 - Electronic device and method for fabricating the same: An electronic device includes: a lower interconnect formed to fill a recess of a first insulating film; a barrier film formed at least on the lower interconnect; and a second insulating film formed on the first insulating film and the barrier film. The first and second insulating films are bonded...

20060043588 - Semiconductor device including a low-k metallization layer stack for enhanced resistance against electromigration: A technique is disclosed which enables the formation of a metallization layer being substantially comprised of a low-k dielectric material, wherein a compressive stress layer provides enhanced electromigration behavior of the metallization layer. In particular embodiments, a compressive silicon dioxide layer may be formed on or in the vicinity of...

20060043590 - Maintaining uniform cmp hard mask thickness: A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is...

20060043593 - Connecting apparatus, semiconductor chip inspecting apparatus, and method for manufacturing semiconductor device: In the connecting apparatus for inspecting the semiconductor chip, in which contact terminals are electrically connected to each of the plurality of electrode pads formed on the semiconductor chips, a part of metal projections in the shape of quadrangular pyramid which constitute the contact terminals is composed of insulator in...

20060043591 - Low temperature process to produce low-k dielectrics with low stress by plasma-enhanced chemical vapor deposition (pecvd): Low K dielectric films exhibiting low mechanical stress may be formed utilizing various techniques in accordance with the present invention. In one embodiment, carbon-containing silicon oxide films are formed by plasma-assisted chemical vapor deposition at low temperatures (300° C. or less). In accordance with another embodiment, as-deposited carbon containing silicon...

20060043595 - Memory device and method of production and method of use of same and semiconductor device and method of production of same: A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor portion) formed by a first minimum processing dimension is formed on...

20060043596 - Semiconductor structure implementing sacrificial material and methods for making and implementing the same: A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels through depositing a sacrificial layer. A dual damascene process is performed to etch trenches and vias, and filling and planarizing the trenches...

20060043592 - Substlate, electro-optical device, electronic apparatus, method of forming substlate, method of forming electro-optical device, and method of forming electronic apparatus: A contact structure, including: a first conductive layer; a insulating layer formed on the first conductive layer; a second conductive layer formed on the insulating layer; and a columnar structure, buried in a direction of film thickness in the insulating layer, electrically connecting the first conductive layer and the second...

20060043594 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within...

20060043597 - Solder composition, connecting process with soldering, and connection structure with soldering: There is provided a solder composition which contains: (1) a metal material comprising solder particles, and (2) a thermosetting flux material comprising a thermosetting resin and a solid resin which transforms to its liquid-like state when heated with a proviso that the thermosetting resin is excluded from the solid resin....

20060043600 - Carrier structure for stacked-type semiconductor device, method of producing the same, and method of fabricating stacked-type semiconductor device: A carrier structure for fabricating a stacked-type semiconductor device includes: a lower carrier that has laminated thin plates and has first openings for mounting first semiconductor packages thereon; and an upper carrier having second openings for mounting second semiconductor packages on the first semiconductor packages. The lower carrier composed of...

20060043598 - Methods of manufacture of a via structure comprising a plurality of conductive elements, semiconductor die, multichip module, and system including same: Methods of forming at least one multiconductor via are disclosed. Specifically, a substrate may be provided and at least one through-hole may be formed therethrough. At least one seed layer may be formed, patterned, and a metal may be deposited thereon to form a plurality of conductive elements. Alternatively, the...

20060043599 - Through-wafer interconnects for photoimager and memory wafers: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and...

20060043601 - Hermetically encapsulated component and waferscale method for the production thereof: A component having a sandwich-like structure is described, in which the chip that carriers the component structures is glued together with a frame structure and a diffusion-proof cover, in such a manner that the component structures are disposed in the interior of the structure and preferably in a cavity. The...

20060043602 - Flip chip ball grid array package with constraint plate: A flip chip ball grid array package is provided. In one embodiment, a flip chip ball grid array package comprises a substrate having an upper surface and a lower surface opposite the upper surface and a microelectronic element comprising a set of solder balls being secured to the upper surface...

20060043604 - High-reliable semiconductor device using hermetic sealing of electrodes: The present invention relates to a high-reliable semiconductor device in which electrodes formed on substrates are prevented from deteriorating by sealing the electrodes with a frame member rather than a sealing material. The frame member in the present invention surrounds electrodes formed on the substrates. The inside of the frame...

20060043603 - Low temperature pb-free processing for semiconductor devices: Techniques for utilizing a bonding agent that allows a solder reflow process to occur at a lower reflow temperature. One area of use includes semiconductor device manufacturing processes. The bonding agent is placed between a solder ball and a contact surface. The bonding agent has a melting temperature that is...

20060043605 - Semiconductor device: To prevent peeling-off of a film in a solder connection pad of a semiconductor device, which peeling-off may occur due to thermal load and so on in the manufacture process, a pad structure is adopted in which a Cr film good in adhesiveness to either of a Ti film or...

20060043606 - Semiconductor device having laminated structure: A technique for reducing the size of a semiconductor device is provided. A semiconductor device comprises a base, a semiconductor chip, a chip component, an insulating base, a wiring pattern, a via plug, an external lead-out electrode, a recess, and a resin. The insulating base has a multi-layer structure formed...

20060043607 - Adhesive film for semiconductor, metal sheet with such adhesive film, wiring substrate with adhesive film, semiconductor device, and method for manufactring semiconductor device: An adhesive film for semiconductor use of the present invention is used in a method in which, after the adhesive film for semiconductor use is laminated to one side of a metal sheet, the metal sheet is processed to give a wiring circuit, a semiconductor die is mounted and molded,...

20060043609 - Integrated circuit with substantially perpendicular wire bonds: An integrated circuit comprises an integrated circuit package and a plurality of circuit elements disposed within the integrated circuit package. A plurality of wire bonds provide connections for at least one of the circuit elements. At least one wire bond in a first subset of wire bonds and at least...

20060043608 - Low stress conductive polymer bump: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion...

20060043610 - Power controller with bond wire fuse: A power controller includes bond wires that also act as fuses to protect the power controller from damage caused by a short circuit fault. The bond wires connect switching elements within the power controller with at least one output pin having at least one output rating. The bond wires themselves...

20060043611 - Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component mounted to a substrate. The substrate carries a plurality of bond pads at a location substantially coplanar with a terminal surface of...

20060043612 - Wire sweep resistant semiconductor package and manufacturing method thereof: A method for manufacturing a wire sweep resistant semiconductor package provides a die attached to an interposer. The die is electrically connected to the interposer with conductive wires. A sealant is applied to the conductive wires and optionally the die to prevent wire sweep, the sealant being applied free of...

20060043613 - Surface-mounting semiconductor device and method of making the same: A semiconductor device X1 comprises: a first conductor 110 including a first terminal surface113a; a second conductor 120 placed by the first conductor 110 and including a second terminal surface 123a facing a same direction as does the first terminal surface 113a; a third conductor 130 connected with the first...

20060043614 - Underfill and mold compounds including siloxane-based aromatic diamines: An apparatus including a first substrate comprising a first set of contact points; a second substrate including a second set of contact points coupled to the first substrate through interconnections between a portion of the first set of contact points a portion of the second set of contact points; and...

20060043615 - Methods and systems of enhancing stepper alignment signals and metrology alignment target signals: Methods and systems of enhancing stepper alignment signals and metrology alignment target signals. In one embodiment, a plurality of alternating rows comprising a first material of a first height and a second material of a second height are constructed. The first material and the second material are selected to enhance...

20060043616 - Finfet with low gate capacitance and low extrinsic resistance: A FinFET device and a method of lowering a gate capacitance and extrinsic resistance in a field effect transistor, wherein the method comprises forming an isolation layer comprising a BOX layer over a substrate, configuring source/drain regions above the isolation layer, forming a fin structure over the isolation layer, configuring...

20060043617 - Dram layout with vertical fets and method of formation: DRAM cell arrays having a cell area of less than about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed...

20060043618 - Semiconductor device: A semiconductor device has a semiconductor chip including first and second surfaces opposed to each other in a thickness direction of the semiconductor chip, wherein the first and second surfaces include first and second electrode surfaces respectively, and first and second electrically conductive members covering the first and second electrode...