Active solid-state devices (e.g., transistors, solid-state diodes) inventions 02/06

20060038166 - Nitride semiconductor light emitting device: A first region and a second region that has a defect density of which the value is higher than that of the first region are respectively formed so as to be aligned in stripe form in the direction parallel to the direction in which a dug out region extends, where...

20060038167 - Integrated carbon nanotube sensors: A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor,...

20060038168 - Terahertz interconnect system and applications: An assembly includes a first electrical circuitry for providing a first electrical signal containing data and a transmitting arrangement, connected with the first electrical circuitry, for receiving the first electrical signal and for converting the first electrical signal into an electromagnetic signal containing at least a portion of the data....

20060038170 - Electronic device having an electrode with enhanced injection properties: The present invention relates to methods and apparatus for producing an electronic device, such as an organic light-emitting diode (OLED), having an electrode with enhanced injection properties. An example method according to the invention comprises the steps of providing an electrode, depositing a first layer of molecular charge transfer material...

20060038169 - Polymer memory device with variable period of retention time: Systems and methodologies are provided for of enabling a polymer memory cell to exhibit variable retention times for stored data therein. Such setting of retention time can depend upon a programming mode and/or type of material employed in the polymer memory cell. Short retention times can be obtained by programming...

20060038172 - Apparatus and methods for wafer-level testing of the chip-scale semiconductor device packages: A test chuck is configured for assembly with, and to test, semiconductor devices of a large-scale substrate. The test chuck includes a substrate with terminals that are arranged correspondingly to the arrangement of bond pads or other contacts of the semiconductor devices, which have yet to be singulated from the...

20060038171 - Semiconductor integrated circuit design tool, computer implemented method for designing semiconductor integrated circuit, and method for manufacturing semiconductor integrated circuit: A semiconductor integrated circuit design tool includes a reference data defining module configured to define design data of one of transistors implementing the semiconductor integrated circuit as reference data, a simulator configured to simulate on each effective channel length of the transistors, based on the design data and a reference...

20060038173 - Buffer layer for promoting electron mobility and thin film transistor having the same: A buffer layer for promoting electron mobility. The buffer layer comprises amorphous silicon layer (a-Si) and an oxide-containing layer. The a-Si has high enough density that the particles in the substrate are prevented by the a-Si buffer layer from diffusing into the active layer. As well, the buffer, having thermal...

20060038174 - Display device provided with semiconductor element and manufacturing method thereof, and electronic device installed with display device provided with semiconductor element: According to one feature of the invention, a region of an insulating film surface at least overlapped with a part of a gate electrode or wiring is coated with an organic agent; a fluid in which conductive fine particles are dispersed in an organic solvent is discharged by a droplet...

20060038177 - Cog-typed organic electroluminescent cell: The present invention relates to a COG-typed organic electroluminescent device including dummy data lines formed at different location from data lines. The COG-typed organic electroluminescent cell having a plurality of pixels formed in the luminescent areas which are cross areas of indium tin oxide films (ITO films) and metal line...

20060038175 - Pixel structure: A pixel structure is provided. The pixel structure comprises a scan line, a data line, a pixel electrode and a thin film transistor. The data line branches out into a plurality of subsidiary lines in the area above the scan line. If there is a short circuit between the scan...

20060038176 - Semiconductor device and manufacturing method thereof: According to the present invention, wirings, electrodes or the like formed from two films (an ITO film and an aluminum film) which are incompatible with each other are connected, and low power consumption is realized even if a display screen size is increased in an active matrix display device. A...

20060038178 - Thin film transistor array panel and a manufacturing method thereof: A method of manufacturing a thin film transistor array panel and a thin film transistor array panel are provided. The method includes: forming a gate line and a storage electrode line on a substrate; forming a gate insulating layer on the gate line and the storage electrode line; forming a...

20060038179 - Method and apparatus for solution processed doping of carbon nanotube: A method is provided for doping a carbon nanotube. The method comprises exposing the nanotube to a one-electron oxidant in a solution phase. A method is also provided for forming a carbon nanotube FET device....

20060038181 - Manufacturing process of thin film transistor liquid crystal display: A process for manufacturing a thin film transistor liquid crystal display (TFT-LCD) is disclosed. The process can reduce the number of the mask used in the photolithography process to three masks, form a capacitor during the manufacturing process simultaneously, and enhance the transmission rate of the TFT-LCD. Because the pixel...

20060038180 - Pixel structure: A pixel structure is provided. The pixel structure comprises a scan line, a data line, a pixel electrode and a thin film transistor. The data line branches out into a plurality of subsidiary lines in the area above the scan line. If there is a short circuit between the scan...

20060038182 - Stretchable semiconductor elements and stretchable electrical circuits: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials....

20060038185 - Light emitting device and light emitting device module: A light emitting device including a substrate transparent at the emission wavelength and an active layer structure formed on such substrate, in which the thickness of the substrate is 75 μm or less, and/or a layer for suppressing spectral-intensity-modulation due to the substrate-mode is provided between the substrate and the...

20060038184 - Light-emitting device, manufacturing method of particle and manufacturing method of light-emitting device: A light-emitting device includes, in order of mention: a positive hole supply layer; a particle layer comprising particles of semiconductor crystals and a conductive medium, the conductive medium which fills spaces between the particles and confines positive holes and electrons in the particles by dint of an energy gap larger...

20060038186 - Light-emitting diode and its manufacturing method: It is an object of the present invention to provides the light emitting diode having a light emitting part of an AlGaInP type, and having a current diffusion layer which includes In on a light emitting side of the light emitting part, so that the generation of hillocks is effectively...

20060038183 - Microelectronic imagers with curved image sensors and methods for manufacturing microelectronic imagers: Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device comprises an imager die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry...

20060038187 - Led and method of manufacturing the same: An LED can include a pair of electrode members, and an LED chip joined to a chip mount portion disposed at the extremity of one of the pair of electrode members. The LED chip can be electrically connected to the pair of electrode members. A transparent resin portion can include...

20060038188 - Light emitting diode systems: Light emitting diode systems are disclosed....

20060038189 - Hermetically sealed packages and their method of manufacture: A device includes a temperature-sensitive material disposed between a first substrate and a second substrate. A metal-containing seal is disposed perimetrically between the first and second substrates. In addition, a method of forming a device includes providing a temperature-sensitive material between a first substrate and a second substrate. The method...

20060038190 - Fabrication method of light emitting diode incorporating substrate surface treatment by laser and light emitting diode fabricated thereby: The present invention relates to a fabrication method of LEDs incorporating a step of surface-treating a substrate by a laser and an LED fabricated by such a fabrication method. The present invention can use a laser in order to implement finer surface treatment to an LED substrate over the prior...

20060038191 - Semiconductor light emitting device: A semiconductor light emitting device includes: a cavity including a mesa formed over a substrate, the mesa having an active layer and being isolated by a recess formed around the mesa; and a resin layer with which the recess is filled. On the upper surface of the cavity, which is...

20060038192 - Fiber optic phototherapy devices including led light sources: Fiber optic phototherapy devices include fiber optic light emitters having fiber optic end portions at one or both ends that may be separated into a plurality of groups of end portions that receive light from one or more light emitting diodes (LEDs). The fiber optic end portions of different segments...

20060038193 - Gallium-nitride based light emitting diode structure with enhanced light illuminance: Disclosed is a multi-quantum-well light emitting diode, which makes enormous adjustments and improvements over the conventional light emitting diode, and further utilizes a transparent contact layer of better transmittance efficiency, so as to significantly raise the illuminance of this light emitting diode and its light emission efficiency. The multi-quantum-well light...

20060038195 - Light-emitting diode and the manufacturing method of the same: The specification discloses a light-emitting diode and the corresponding manufacturing method. A GaN thick film with a slant surface is formed on the surface of a substrate. An epitaxial slant surface is naturally formed using the properties of the GaN epitaxy. An LED structure is grown on the GaN thick...

20060038194 - Light-emitting element device, light-receiving element device, optical device, fluoride crystals, production method of fluoride crystals, and crucible: In the present invention, a short-wavelength light-emitting element such as an ultraviolet light-emitting element or blue light-emitting element is arranged in a container which has a window with a window board formed of calcium fluoride crystals. According to the present invention, it is possible to obtain a reliable light-emitting element...

20060038198 - Device and method for producing output light having a wavelength spectrum in the visible range and the infrared range using a fluorescent material: A device and method for producing output light having a wavelength spectrum in the visible wavelength range and the infrared wavelength range uses a fluorescent material to convert at least some of the original light emitted from a light source of the device to longer wavelength light to produce the...

20060038197 - Reflection-type optoelectronic semiconductor device: A reflection-type optoelectronic semiconductor device has an LED chip disposed on a first conducting wire portion, a second conducting wire portion connected to the LED chip via a connection wire, a packaging body for sealing the LED chip and part of the first conducting wire portion and the second conducting...

20060038196 - Sideway-emission light emitting diode: A sideway-emission light emitting diode includes a light emitting diode package comprised of a light emitting diode dice that gives off light and a lens that is positioned in front of a front end face of the package for receiving the light and redirecting the received light toward a circumference...

20060038199 - Cmosfet with hybrid strained channels: Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from...

20060038200 - Transistors having reinforcement layer patterns and methods of forming the same: According to some embodiments of the invention, there is provided line photo masks that includes transistors having reinforcement layer patterns and methods of forming the same. The transistors and the methods provide a way of compensating a partially removed amount of a strained silicon layer during semiconductor fabrication processes. To...

20060038201 - Layout symmetry constraint checking method and layout symmetry constraint checking apparatus: A layout symmetry constraint checking method and apparatus for efficiently checking a layout symmetry constraint is provided. The layout symmetry constraint is checked by performing a first checking step of checking, for example, a match between shapes of a symmetrical element pair for input layout data, a second checking step...

20060038202 - Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages: A semiconductor package comprising a die adjacent a lead frame die pad, said lead frame die pad adapted to dissipate heat from the die. The package further comprises a thermally-conductive material abutting the die and a heatsink abutting the thermally-conductive material, said heatsink facing a direction opposite from the lead...

20060038203 - Methods to eliminate amplifier glowing artifact in digital images captured by an image sensor: A charge coupled device includes a substrate; a plurality of image pixels arranged in a two dimensional array in the substrate for capturing an electronic representation of an image and for transferring charge in a first direction; a transfer mechanism for transferring charge in a second direction from the plurality...

20060038204 - Solid-state imaging device and method for manufacturing the same: A transfer film, on which an adhesive is applied, is glued to plural spacers formed on a glass substrate. The glass substrate is laid on a working table, and one end of the transfer film is fixed to a winding roller. A peeling guide is set at a position over...

20060038205 - Dram layout with vertical fets and method of formation: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a...

20060038206 - Semiconductor device and manufacturing method thereof: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet...

20060038208 - Apparatus and method of image processing to avoid image saturation: An imaging device includes a plurality of photo-diodes that operate as optical pixels arranged in a plurality of columns on a single CMOS substrate. The outputs of the multiple pixel sensors, or photo-diodes, are examined to determine if a one pixel, or a region of pixels are in saturation. If...

20060038207 - Wide dynamic range sensor having a pinned diode with multiple pinned voltages: A pixel cell has controlled photosensor anti-blooming leakage by having dual pinned voltage regions, one of which is used to set the anti-blooming characteristics of the photosensor. Additional exemplary embodiments also employ an anti-blooming transistor in conjunction with the dual pinned photosensor. Other exemplary embodiments provide a pixel with two...

20060038209 - Photoelectric conversion device and manufacturing method thereof: A photoelectric conversion device is provided which is capable of improving the light condensation efficiency without substantially decreasing the sensitivity. The photoelectric conversion device has a first pattern provided above an element isolation region formed between adjacent two photoelectric conversion elements, a second pattern provided above the element isolation region...

20060038214 - Low voltage drive ferroelectric capacitor: A method of forming a low-voltage drive thin film ferroelectric capacitor includes the steps of depositing a ferroelectric and platinum thin film dielectric layer over a bottom electrode, annealing the dielectric layer, wherein a nanocomposite layer is formed including nanoparticles of platinum and forming a top electrode over the dielectric...

20060038213 - Magnetic memory adopting synthetic antiferromagnet as free magnetic layer: A magnetic memory is composed of: a magnetoresistance element including a free magnetic layer; a first interconnection extending in a first direction obliquely to an easy axis of the free magnetic layer; a second interconnection extending in a second direction substantially orthogonal to the first direction; and a write circuit...

20060038211 - Magnetic memory with static magnetic offset field: A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer...

20060038210 - Multi-sensing level mram structures: The present disclosure provides an improved magnetic memory cell. The magnetic memory cell includes a switching element and two magnetic tunnel junction (MTJ) devices. A conductor connects the first and second MTJ devices in a parallel configuration, and serially connecting the parallel configuration to an electrode of the switching element....

20060038215 - Semiconductor device and method for manufacturing the same: A semiconductor device comprising a semiconductor substrate, and a plurality of capacitors formed on the semiconductor substrate. The capacitors comprise a plurality of lower electrodes formed on the semiconductor substrate, a ferroelectric film formed continuously covering the plurality of lower electrodes, and an upper electrode formed on the surface of...

20060038212 - Structure for amorphous carbon based non-volatile memory: A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a second layer of amorphous carbon. The device also includes at least one first conductive layer common to the at least one first and the...

20060038216 - Formation of capacitor having a fin structure: Device designs and methods are described for incorporating capacitors commonly used in planar CMOS technology into a FinFET based technology. A capacitor includes at least one single-crystal Fin structure having a top surface and a first side surface opposite a second side surface. Adjacent the top surface of the at...

20060038217 - Dielectric memory device and method for fabricating the same: A method for fabricating a dielectric memory device is carried out in the following manner. A first lower electrode is formed above a substrate, and then a first insulating film is formed on the first lower electrode. Through the first insulating film, a hole is formed which reaches an upper...

20060038218 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating...

20060038221 - Antiferromagnetic/paramagnetic resistive device, non-volatile memory and method for fabricating the same: A resistive multilayer device employs a first layer comprising a first material that is electrically conducting, a second layer disposed on the first layer, wherein the second layer comprises a second material having a state that is switchable between an antiferromagnetic state and a paramagnetic state by passing current through...

20060038222 - Chemoreceptive semiconductor structure: A field effect transistor has a floating gate with an extended portion. A selectively chemoreceptive finger or layer is electrostatically coupled to the extended portion of the floating gate, and induces a voltage on the gate in response to selected chemicals or other conditions affecting the finger. The voltage on...

20060038219 - Memory device: A memory device is provided. The memory device comprises a substrate, first isolation structures, stacked device structures, and second isolation structures. The substrate comprises a memory cell area and a periphery area having trenches therein. Each stacked device structure is disposed between two neighboring trenches over the substrate. The stacked...

20060038220 - Semiconductor memory device comprising memory cells with floating gate electrode and method of production: Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially...

20060038223 - Trench mosfet having drain-drift region comprising stack of implanted regions: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. A trench is formed in the epitaxial layer. A drain-drift region is formed by implanting N-type dopant through the bottom of the trench at different energies, creating a stack of N-type regions...

20060038226 - Field effect transistor and application device thereof: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4....

20060038225 - Integrated circuit employable with a power converter: An integrated circuit employable with a power converter. In one embodiment, the integrated circuit includes a transistor employable as a switch of a power train of the power converter including a gate located over a channel region recessed into a semiconductor substrate. The transistor also includes a source/drain including a...

20060038224 - Metal-oxide-semiconductor device having an enhanced shielding structure: An MOS device includes a semiconductor layer formed on a substrate, the substrate defining a horizontal plane and a vertical direction normal to the horizontal plane. First and second source/drain regions are formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain...

20060038228 - High strain glass/glass-ceramic containing semiconductor-on-insulator structures: The present invention relates to semiconductor-on-insulator structures having strained semiconductor layers. According to one embodiment of the invention, a semiconductor-on-insulator structure has a first layer including a semiconductor material, attached to a second layer including a glass or glass-ceramic, with the strain point of the glass or glass-ceramic equal to...

20060038227 - Strained semiconductor-on-insulator structures and methods for making strained semiconductor-on-insulator structures: The present invention relates to semiconductor-on-insulator structures having strained semiconductor layers. According to one embodiment of the invention, a semiconductor-on-insulator structure has a first layer including a semiconductor material, attached to a second layer including a glass or glass-ceramic, with the CTEs of the semiconductor and glass or glass-ceramic selected...

20060038229 - Semiconductor device: Disclosed is a semiconductor device comprising a semiconductor substrate having isolation regions, and a MIS transistor comprising a gate electrode formed above the semiconductor substrate with a gate insulating film interposed therebetween, and a pair of contact layers formed on the semiconductor substrate sandwiching the gate electrode, the contact layers...

20060038230 - Transistor and method of manufacturing the same: A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second...

20060038231 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick...

20060038232 - High-voltage transistor having shielding gate: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode...

20060038233 - Semiconductor device and method of manufacturing the same: A semiconductor device has a substrate, a first gate electrode, and a second gate electrode. The substrate has an active region surrounded by an isolation region. The first gate electrode is formed on the active region through a gate insulating film. The second gate electrode is formed on the gate...

20060038234 - Memory cell structure: An SRAM device includes an SRAM cell in a deep NWELL region in a substrate. PWELL regions in the SRAM cell occupy less than about 65% of the cell area of the SRAM cell. A ratio of a longer side of a cell area of the SRAM cell to a...

20060038235 - Semiconductor device: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within...

20060038236 - Semiconductor device: A P-type MOSFET 120 includes a semiconductor substrate (N-well 102b); a gate insulating film formed on the semiconductor substrate, composed of a high-dielectric-constant film 108 which contains a silicate compound containing a first element selected from the group consisting of Hf, Zr and any of lanthanoids, together with N; a...

20060038237 - Integrated circuit incorporating higher voltage devices and low voltage devices therein: An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a switch formed on the semiconductor substrate and a driver switch of a driver configured to provide a drive signal to the switch...

20060038238 - Integrated circuit incorporating higher voltage devices and low voltage devices therein: An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a transistor having a gate located over a channel region recessed into a semiconductor substrate, and a source/drain including a lightly doped region...

20060038239 - Semiconductor device and method of manufacturing the same: Disclosed is a semiconductor device comprising a semiconductor substrate having isolation regions a p-type MIS transistor comprising a pair of source/drain regions formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a gate electrode formed on the gate insulating film and having a first...

20060038240 - Semiconductor device and manufacturing method of the same: An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV...

20060038241 - Semiconductor device and method of manufacturing the same: A semiconductor device comprising a semiconductor substrate having a recess whose depth is not more than 6 nm, a source region and a drain region which are formed in a surface region of the semiconductor substrate so as to sandwich the recess, each of the source region and the drain...

20060038242 - Semiconductive metal oxide thin film ferroelectric memory transistor: The present invention discloses a novel transistor structure employing semiconductive metal oxide as the transistor conductive channel. By replacing the silicon conductive channel with a semiconductive metal oxide channel, the transistors can achieve simpler fabrication process and could realize 3D structure to increase circuit density. The disclosed semiconductive metal oxide...

20060038243 - Transistor and method of manufacturing the same: A transistor of the present invention includes a semiconductor substrate that has a first surface of the {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a side face of the {111} crystal plane connecting the first...

20060038244 - Gated field effect devices: This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a...

20060038247 - Magnetic memory device having uniform switching characteristics and capable of switching with low current and associated methods: A magnetic memory device includes a magnetic tunneling junction (MTJ) structure having a cylindrical shape. Elements of the MTJ structure are co-axial. The MTJ structure includes a conductive layer, an insulating layer co-axially formed around the conductive layer and a material layer formed around the insulating layer, the material layer...

20060038246 - Magnetoresistance effect device and method of production thereof: A method of production of a magnetoresistance effect device is able to prevent or minimize a drop in the MR ratio and maintain the high performance of the magnetoresistance effect device even if forming an oxide layer as a surface-most layer constituting a protective layer by the oxidation process inevitably...

20060038245 - Semiconductor device and method of producing the same: A semiconductor device of a wafer level chip size package type is formed by cutting a semiconductor wafer with a plurality of semiconductor elements formed thereon in pieces. The semiconductor device includes a semiconductor substrate as the semiconductor wafer having a magnetic layer formed on at least one of a...

20060038248 - Method for manufacturing cmos image sensor using spacer etching barrier film: A method for fabricating a CMOS image sensor including a low voltage buried photodiode and a transfer transistor, includes the steps of: forming a field oxide for defining active area and field area on certain area of an epitaxial layer formed on a substrate, and forming a gate of transfer...

20060038249 - Semiconductor light-receiving device and uv sensor apparatus: A semiconductor light-receiving device and a UV sensor apparatus that have high photoelectric conversion efficiency even for short-wavelength radiation are provided. The semiconductor light-receiving device includes a cathode layer and anode layers formed at a surface of the cathode layer. A part of the cathode layer that is located between...

20060038250 - Semiconductor device, method of manufacturing the same, cover for semiconductor device, and electronic equipment: A method of manufacturing a semiconductor device includes (a) fixing a cover onto a semiconductor substrate so as to place a surface of the cover that includes a portion defining a first opening, face to face on a surface of the semiconductor substrate that includes an electrode and (b) applying...

20060038251 - Multispectral detector matrix: m

20060038252 - Reduced crosstalk sensor and method of formation: Isolation methods and devices for isolating regions of a semiconductor device are disclosed. The isolation methods and structures include forming an isolating trench among pixels or other active areas of a semiconductor device. The trench extends through the substrate to the base layer, wherein a liner may be deposited on...

20060038253 - Pressed-contact type semiconductor device: A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N−-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer...

20060038254 - Trench isolation structure and method of formation: In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a bottom portion and first and second trench sidewalls. At least...

20060038255 - Mos electric fuse, its programming method, and semiconductor device using the same: A programming method of a MOS electric fuse includes steps of preparing, as a fuse element, a MOS transistor which comprises second conductivity type first and second impurity regions formed to face with each other on an upper surface of a first conductivity type well on a semiconductor substrate, a...

20060038256 - Semiconductor fuse arrangements: The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to...

20060038257 - Semiconductor device which includes an inductor therein and a manufacturing method thereof: A semiconductor device includes a semiconductor substrate having a principal surface in which a semiconductor integrated circuit is included and a spiral inductor disposed over the principal surface of the semiconductor substrate so as to be coupled to the semiconductor integrated circuit. A region occupied by the spiral inductor is...

20060038258 - High-frequency bipolar transistor and method for the production thereof: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which...

20060038259 - Silicon pillars for vertical transistors: In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas...

20060038260 - Semiconductor wafer and method of manufacturing semiconductor device: A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus improving the manufacturing efficiency....

20060038261 - Shallow trench isolation and fabricating method thereof: A shallow trench isolation (STI) structure and fabricating method thereof is provided. A substrate is provided. A patterned mask layer is formed over the substrate. Using the patterned mask layer as an etching mask, the substrate is patterned to form a trench. A nitridation process is performed to form a...

20060038262 - Semiconductor processing methods: In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material...

20060038263 - Semiconductor chip arrangement: A patterned connection plane between two semiconductor chips which are connected using face-to-face technology is patterned into first pads, second pads, and conductor strips which are alternatively connected to one of these pads. The conductor strips are connected to a read-out circuit in one of the semiconductor chips via connections....

20060038264 - Printed circuit board: To provide a printed circuit board in which two wiring patterns having a width of 0.15 mm, which are to be passed through the area of the printed circuit board for mounting a 1608-size chip component, are formed by printing, thereby increasing the circuit packaging density, reducing the production cost...

20060038265 - Multi-path bar bond connector for an integrated circuit assembly: A solderable bar bond connector establishes a primary interconnect between a substrate and a high current terminal of an IC chip mounted on the substrate, and one or more secondary interconnects between the substrate and low current terminals of the IC chip. The bar bond connector includes a plate portion...

20060038266 - Qfn package and method therefor: A semiconductor device (20) includes an integrated circuit (22) having a plurality of bonding pads (24) located on a peripheral portion of its top surface and a groove (26) formed in its bottom surface (28). The groove (26) extends from one end to an opposite end of the IC (22)....

20060038267 - Display device with characteristic data stored therein: A method of manufacturing a display device is presented. The method includes mounting the memory on the printed circuit board (PCB) and writing the characteristic data in the memory. The characteristic data, which is data that is specific to a display device having a particular specification, allows an operator to...

20060038268 - Semiconductor module: Disclosed is a semiconductor module comprising a semiconductor element (1) and two terminal electrodes (3a, 3b, 3c) between which the semiconductor element (1) is disposed and with which the semiconductor element (1) is contacted in an electrically conducting manner. The semiconductor element (1) is surrounded by an at least partly...

20060038269 - Method and apparatus for lubricating microelectromechanical devices in packages: The present invention provides a lubricant container inside a microelectromechanical device package. The lubricant container contains selected lubricant that evaporates from the container and contact to a surface of the microelectromechanical device for lubricating the surface....

20060038270 - Semiconductor device, semiconductor package, electronic device, and method for establishing information processing environment: An electronic device is provided on which semiconductor packages can be mounted efficiently. The electronic device includes a board that can receive a plurality of first semiconductor packages each carrying a processor device and a plurality of second semiconductor packages each carrying a memory device. Mount regions where the packages...

20060038274 - 3d circuit module, multilayer 3d circuit module formed thereof, mobile terminal device using the circuit modules and method for manufacturing the circuit modules: A 3D circuit module which is highly reliable, easily layered and able to mount electronic components in high density is obtained by providing a support member having a frame in the periphery thereof and a recess; a coating layer for coating the frame and filling in the recess, the coating...

20060038273 - Electronic packages with dice landed on wire bonds: A stacked dice electronic package without spacers between the dice and where an overlying die is landed on wire bonds of the underlying die is disclosed....

20060038275 - Method and apparatus for manufacturing stacked-type semiconductor device: A method of manufacturing a stacked-type semiconductor device, comprises: arranging a plurality of stacked chips obtained by stacking semiconductor chips on a plurality of stages on a support substrate; connecting a semiconductor chip of each stage in each stacked chip and the support substrate by wire while performing heating in...

20060038276 - Methods and systems for attaching die in stacked-die packages: A method for producing a multiple-die device by attaching a die to a substrate using a first die-attach material having a first processing temperature and attaching a subsequent die using a second die-attach material having a second processing temperature such that the process of attaching the second die does not...

20060038272 - Stacked wafer scale package: A device comprising a first die enclosed in a wafer scale package, said first die adapted to mate with a printed circuit board (“PCB”) via solder bumps. The device further comprises a second die enclosed in a wafer scale package and electrically connected to a surface of the first die...

20060038271 - Substrate isolation design: A substrate isolation design includes a P substrate, a P well positioned on the P substrate, at least a device positioned in the P well, and at least a P substrate guard ring surrounding the device. A P+ guard ring, an N well guard ring, or a deep N well...

20060038277 - Semiconductor device and electronic apparatus using the same: A semiconductor device contains a semiconductor chip, and includes first and second circuits, a control signal line and a terminal. The first circuit is arranged in a center of the semiconductor chip and is configured to operate in a first voltage. The second circuit is arranged in an input/output circuit...

20060038278 - Submember mounted on a chip of electrical device for electrical connection: A submember for electrical device is disclosed. Said submember is mounted on a chip of electrical device. An embodiment for the submember comprised of an insulator and a plurality of conductive elements, wherein the conductive elements embedded in the insulator and a portion of conductive element exposed to the insulator...

20060038279 - System-on-a-chip with multi-layered metallized through-hole interconnection: The present invention is directed to a high-performance system on a chip which uses multi-layer wiring/insulation through-hole interconnections to provide short wiring and controlled low-impedance wiring including ground planes and power supply distribution planes between chips....

20060038280 - Substrate for producing semiconductor packages: where αj is respective thermal expansion coefficients of, Ej is respective elastic moduli of, and vj is respective volume ratios of first through mth components constituting the lower part (e.g., insulation layer, conductor patterns, and PSR layers of the lower part), a equivalent thermal expansion ratio (αupper/αlower) of αupper to...

20060038282 - Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages: A semiconductor package comprising a die adjacent a lead frame die pad, said lead frame die pad adapted to dissipate heat from the die. The package further comprises a thermally-conductive material abutting the die and a heatsink abutting the thermally-conductive material, said heatsink facing a direction opposite from the lead...

20060038283 - Integrated circuit with increased heat transfer: A technique for improving the thermal power dissipation of an integrated circuit includes reducing the thermal resistivity of the integrated circuit by increasing heat transfer in vertical and/or lateral directions. These results are achieved by increasing the surface area of the backside and/or the surface area of the lateral sides...

20060038281 - Multiple power density chip structure: A multiple power density packaging structure with two or more semiconductor chips on a common wiring substrate having a common thermal spreader with a planar surface in thermal contact with the non-active surfaces of the chips. The semiconductor chips have different cooling requirements and some of the chips are thinned...

20060038285 - Electronic apparatus: A small-size and light-weight electronic apparatus with a cooling structure capable of exhibiting good cooling performance is provided. A cover member with a plurality of grooves for forming a channel is joined by brazing to a housing on a lid body side to which an LCD panel is attached, and...

20060038284 - Fluid cooled encapsulated microelectronic package: An encapsulated microelectronic package includes a fluid conducting cooling tube directly coupled to one or more semiconductor chips, with the encapsulant being molded over the semiconductor chips and portions of the cooling tube in proximity to the semiconductor chips. The encapsulant immobilizes the cooling tube with respect to the semiconductor...

20060038286 - Package, method for producing a package and a device for producing a package: The invention relates to a package or package raw material comprising an electrically conductive layer arranged on a base material and a chip connected to the electrically conductive layer, the electrically conductive layer being configured as an antenna element for transferring data and/or energy, wherein the electrically conductive layer comprises...

20060038287 - Lsi package equipped with interface module, interface module and connection holding mechanism: I an LSI package, an interface module includes with an interposer having a signal processing LSI mounted thereon and has electric connection terminals for connection to a mounting board and a transmission line for transmitting a high-speed signal to an external wiring. An electric connection terminal is formed in each...

20060038288 - Substrate with many via contact means disposed therein: A substrate having many via contact means disposed therein. Each of the via contact means is composed of a via hole, as a through-hole, formed in the substrate, a metal film disposed on the inner peripheral surface of the via hole, and a solder filled into the cavity defined by...

20060038289 - Integrated inductors and compliant interconnects for semiconductor packaging: Some embodiments of the present invention include integrated inductors and compliant interconnects for semiconductor packaging....

20060038290 - Process for making electrode pairs: The present invention is a process for making a matching pair of surfaces, which involves creating a network of channels on one surface of two substrate. The substrates are then coated with one or more layers of materials, the coating extending over the regions between the channels and also partially...

20060038291 - Electrode structure of a semiconductor device and method of manufacturing the same: In the manufacture of a semiconductor device, a photosensitive layer is deposited to cover an exposed portion of an electrode with the photosensitive layer. The photosensitive layer is then subjected to a photolithography process to partially remove the photosensitive layer covering the electrode. The electrode may be a ball electrode...

20060038292 - Semiconductor device having wires that vary in wiring pitch: A semiconductor device includes a first wiring layer having a first wiring pitch and a second wiring layer having a second wiring pitch that differs from the first wiring pitch. The device further includes a third wiring layer which connects the first wiring layer and the second wiring layer and...

20060038293 - Inter-metal dielectric fill: An inter-metal dielectric (IMD) fill process includes depositing an insulating nanolaminate barrier layer. The nanolaminate is preferably an oxide liner formed by using an alternating layer deposition process. The layer is highly conformal and is an excellent diffusion barrier. Gaps between metal lines are filled using high density plasma chemical...

20060038296 - Integrated low-k hard mask: Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers....

20060038294 - Metallization performance in electronic devices: Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 μm in height and advantageously within 100 μm of another...

20060038295 - Selectively encased surface metal structures in a semiconductor device: The present invention provides, in one embodiment, An integrated circuit device (100). The integrated circuit device (100) comprises a circuit feature (105) located over a semiconductor substrate (110) and an insulating layer (115) located over the circuit feature (105). A protective overcoat (120) is located over the insulating layer (115)...

20060038297 - Semiconductor device: Propagation of a crack in a semiconductor device is to be suppressed, thus to protect an element forming region. An interface reinforcing film is provided so as to cover a sidewall of a concave portion that penetrates a SiCN film and a SiOC film formed on a silicon substrate. The...

20060038298 - Tape circuit substrate, semiconductor chip package including the same, and liquid crystal display device including the semiconductor chip package: A liquid crystal display device includes a liquid crystal panel including a pad electrode, a tape circuit substrate and an anisotropic conductive film. The pad electrode receives one of a driving signal and a power supply voltage signal. The tape circuit substrate includes a base film made of an insulating...

20060038299 - Carbon nanotube device, process for producing the same and carbon nanotube transcriptional body: To provide a carbon nanotube device capable of efficiently exerting various electrical or physical characteristics of a carbon nanotube, the present invention provides: a carbon nanotube device, in which a carbon nanotube structure layer having a network structure in which plural carbon nanotubes mutually cross-link, is formed in an arbitrary...

20060038300 - Semiconductor chip manufacturing method, semiconductor chip, semiconductor device manufacturing method, and semiconductor device: The invention provides a semiconductor chip manufacturing method, including a step of forming a front-surface-side concave portion in a semiconductor substrate having a front surface and a rear surface, a functional device being formed on the front surface, the front-surface-side concave portion being formed in the front surface and having...

20060038301 - Micro structure with interlock configuration: A micro structure has: a semiconductor substrate; an insulating film having a via hole and formed on the semiconductor substrate; an interlock structure formed on a side wall of the via hole and having a retracted portion and a protruded portion above the retracted portion; a conductive member having at...

20060038303 - Etched interposer for integrated circuit devices: In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer 106 includes columnar interconnects which may be fabricated by etching a conductive member such as copper...

20060038302 - Thermal fatigue resistant tin-lead-silver solder: A solder comprising a ternary alloy of tin, lead, and silver, providing approximately the eutectic melting temperature and about 0.7 to 1.5 weight percent silver. In one embodiment, the ternary solder alloy comprises the composition of about 61.0 weight percent tin, about 37.5 weight percent lead, and about 1.5 percent...

20060038304 - Conductive adhesive agent and process for manufacturing article using the conductive adhesive agent: The present invention provides a conductive adhesive agent capable of being diluted with a solvent to give good coating workability and allowing formation of a conductive joint excellent in both thermal conductivity and electrical conductivity by inhibiting a gas generated when a binder resin is heat-cured after attachment of a...

20060033094 - Resistance variable memory with temperature tolerant materials: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device....

20060033095 - Non-planar pmos structure with a strained channel region and an integrated strained cmos flow: A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on...

20060033096 - Method and circuit for reading quantum state: A single electron-transistor is used to read out charge states of two coupled qubits formed by two Cooper pair boxes. Detection is made about a gate voltage shift of the peak of the current that flows in the single electron transistor in accordance with the charge states. Since the current...

20060033097 - Systems and methods for performing quantum computations: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the...

20060033099 - Organic light emitting diode display and manufacturing method thereof: An organic light emitting diode display includes an insulating layer, a stress buffer disposed on the insulating layer, a first electrode disposed on the stress buffer, an organic light emitting member disposed on the first electrode, and a second electrode disposed on the organic light emitting member....

20060033098 - Organic semiconductor devices having low contact resistance: Organic semiconductor-based devices such as thin film transistors, organic light emitting devices and solar cells have potential in low cost electronic and optoelectronic applications. The performance of these organic semiconductor-based devices is often limited by the large resistance between the organic semiconductors and counter electrodes. This invention provides device structures...

20060033100 - Anisotropically conductive connector and production process thereof, and probe member: An anisotropically conductive connector, by which positioning, and holding and fixing to a wafer to be inspected can be conducted with ease even when the wafer has a large area, contains a frame plate having a plurality of anisotropically conductive film-arranging holes formed corresponding to regions of electrodes to be...

20060033103 - Display device, method of production of the same, and projection type display device: A display device able to raise a light resistance of pixel transistors without depending upon a light shielding structure and a method of production of same, wherein an average crystal grain size of a polycrystalline silicon film 111 forming an active layer of the pixel transistors is controlled to be...

20060033101 - Pixel structure and fabricating method thereof: A pixel structure and a fabricating method thereof are described. The method comprises forming a conductive layer, a data line and a source/drain at the same time. The conductive layer has a coupling portion and a connecting portion. The coupling portion is used as a top electrode of a pixel...

20060033102 - Thin film transistor array panel used for a liquid crystal display and a manufacturing method thereof: A gate insulating layer, an amorphous silicon layer, an n+ amorphous silicon layer and a metal layer are deposited in sequence after a gate line, a gate electrode and a gate pad are formed on a substrate, using a first mask. The metal layer is etched to form a data...

20060033104 - Thin film transistor, method of manufacturing thin film transistor, and display device: There is disclosed a thin film transistor having a source region, a channel region, and a drain region in a semiconductor thin film whose crystals have grown in a transverse direction, the thin film transistor having a gate insulating film and a gate electrode in an upper part of the...

20060033106 - Thin film transistor and method of fabricating the same: A bottom gate thin film transistor and method of fabricating the same are disclosed, in which a channel region is crystallized by a super grain silicon (SGS) crystallization method, including: forming a gate electrode and a gate insulating layer on an insulating substrate; forming an amorphous silicon layer on the...

20060033107 - Thin film transistor and method of fabricating the same: The present invention discloses a thin film transistor and a method of fabricating the same. The thin film transistor includes an insulating substrate; and a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulator, and a source/drain electrode which are formed on the substrate, wherein the gate...

20060033105 - Thin film transistor, liquid crystal display apparatus, manufacturing method of thin film transistor, and manafacturing method of liquid crystal display apparatus: A manufacturing method of a thin film transistor of the present invention includes the steps of (i) forming an electrode formation area in which a source electrode and a drain electrode are formed by applying a droplet of an electrode raw material, (ii) applying the droplet of the electrode raw...

20060033108 - Transparent double-injection field-effect transistor: A double-injection field-effect transistor has an anode, a cathode, a substantially transparent channel, a substantially transparent gate insulator, and at least one substantially transparent gate electrode. The transistor may also have a substantially transparent anode and/or cathode. The transistor may also be formed on a substantially transparent substrate. Electrode contacts...

20060033109 - Liquid crystal display device and fabrication method thereof: A method for fabricating an LCD device includes forming an active layer having a source region, a drain region and a channel region on the first substrate; forming first and second conductive layers on the first substrate; forming a gate electrode, a gate line and a pixel electrode by patterning...

20060033110 - Three dimensional integrated circuit and method of design: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to...

20060033111 - Methods of treating a silicon carbide substrate for improved epitaxial deposition and resulting structures and devices: A silicon carbide structure is disclosed that is suitable for use as a substrate in the manufacture of electronic devices such as light emitting diodes. The structure includes a silicon carbide wafer having a first and second surface and having a predetermined conductivity type and an initial carrier concentration; a...

20060033112 - Substrate for light emitting diodes: A substrate has a pair of metal bases, and a first heat insulation layer disposed between the metal bases. A second heat insulation layer is securely mounted on the metal bases, and a pair of circuit patterns are securely mounted on the second heat insulation layer for mounting an LED....

20060033113 - Nitride semiconductor light emitting diode and method of manufacturing the same: The present invention provides a flip chip-type nitride semiconductor light emitting diode. The nitride semiconductor light emitting diode comprises a light transmittance substrate, an n-type nitride semiconductor layer, an active layer, a p-type nitride semiconductor layer and a mesh-type DBR reflecting layer. The mesh-type DBR reflecting layer has a plurality...

20060033114 - Light emitting and imaging sensing device and apparatus: There is provided a light emitting and image sensing device for a scene. The light emitting and image sensing device is formed in a semiconductor substrate and comprises a photoemitter means for illuminating the scene with light, and a photosensor means for sensing an image of the scene. The photosensor...

20060033115 - Transparent, thermally stable light-emitting component comprising organic layers: The invention relates to a thermally stable, high efficient, transparent light-emitting component, which comprises organic layers, is run at low operating voltages and is simple to produce. The aim of the invention is to disclose a completely transparent (>70% transmission) organic light-emitting diode, which can be operated at a reduced...

20060033116 - Gallium nitride based semiconductor light emitting diode and process for preparing the same: The present invention provides a gallium nitride based semiconductor light emitting diode having high transparency, and at the same time, capable of improving contact resistance between a p-type GaN layer and electrode and a process for preparing the same. These objects can be accomplished by forming, on an upper part...

20060033117 - Light-emitting diode and mehtod for its production: A Light-emitting diode which comprises a pair of metal plate leads connected to a light-emitting element. The pair of metal plate leads comprise, at the edges of the metal plates, surface mounting-type connecting parts that connect facing the pads of a circuit substrate. Furthermore, the light-emitting diode comprises a support...

20060033118 - System, apparatus and method of selective laser repair for metal bumps of semiconductor device stack: Exemplary embodiments of the selective laser repair apparatus and method may allow the repair of metal bumps in a semiconductor device stack by applying a laser beam to a damaged and/or defective bump. Metal bumps may be repaired and individual chips and/or packages forming a device stack need not be...

20060033120 - Gallium nitride based light emitting device and the fabricating method for the same: A GaN-based light-emitting device and the fabricating method for the same are described. The light-emitting device is a light-emitting body with a light extraction layer thereon. The light-emitting body has some GaN-based layers and is capable of emitting a light when energy is applied. The light extraction layer is a...

20060033119 - Iii-v group nitride system semiconductor self-standing substrate, method of making the same and iii-v group nitride system semiconductor wafer: A III-V group nitride system semiconductor self-standing substrate has: a first III-V group nitride system semiconductor crystal layer that has a region with dislocation lines gathered densely, the dislocation lines being gathered substantially perpendicular to a surface of the substrate, and a region with dislocation lines gathered thinly; and a...

20060033121 - Chemical sensor using chemically induced electron-hole production at a schottky barrier: Electron-hole production at a Schottky barrier has recently been observed experimentally as a result of chemical processes. This conversion of chemical energy to electronic energy may serve as a basic link between chemistry and electronics and offers the potential for generation of unique electronic signatures for chemical reactions and the...

20060033122 - Half-bridge package: A semiconductor package which includes two power semiconductor die arranged in a half-bridge configuration....

20060033123 - Interconnect line selectively isolated from an underlying contact plug: The present invention relates to selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line...

20060033124 - Method for fabrication of semiconductor device: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step...

20060033125 - Transistor with nitrogen-hardened gate oxide: An improved surface P-channel transistor includes providing a semiconductor substrate, forming a gate oxide layer over the semiconductor substrate, subjecting the gate oxide layer to a remote plasma nitrogen hardening treatment followed by an oxidative anneal, and forming a polysilicon layer over the resulting gate oxide layer. Significantly, the present...

20060033126 - Photon amplification for image sensors: A pixel cell having a substrate, photo-conversion device, and at least one dielectric layer over the photo-conversion device. The at least one dielectric layer includes one or more rare earth elements for amplifying the number of photons capable of being converted to charge by the photo-conversion device....

20060033127 - Pinned photodiode integrated with trench isolation and fabrication method: A photo sensor with pinned photodiode structure integrated with a trench isolation structure. The photo sensor includes a substrate of a first conductivity type, at least one trench in the substrate, at least one doped region of the first conductivity type, and at least one doped region of a second...

20060033128 - Logic switch and circuits utilizing the switch: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic...

20060033130 - Liquid crystal display device: An object of the invention is to repair a drain signal line easily. Each region enclosed by two gate signal lines adjacent to each other and two drain signal lines adjacent to each other that are formed on the liquid-crystal-side surface of one of transparent substrates that are opposed to...

20060033129 - Low dark current image sensors with epitaxial sic and/or carbonated channels for array transistors: A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or carbonated silicon is provided over the substrate of the pixel cell to reduce the dark current leakage....

20060033131 - Complementary metal oxide semiconductor image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same is disclosed, to enhance the image-sensing efficiency by forming a concave lens area for improving the light-condensing efficiency in a planarization layer formed before a micro-lens array, in which the CMOS image sensor includes a plurality of photosensitive devices...

20060033132 - Low dark current image sensors with epitaxial sic and/or carbonated channels for array transistors: A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or carbonated silicon is provided over the substrate of the pixel cell to reduce the dark current leakage....

20060033135 - Ferroelectric element and method for manufacturing the same: In a ferroelectric element, the ferroelectric film is prevented from deteriorating and the interconnect film from lowering in reliability. A ferroelectric element comprises a first electrode, a ferroelectric film formed on the first electrode, a second electrode formed on the ferroelectric film, a first hydrogen blocking film formed directly on...

20060033134 - Ferroelectric random access memories (frams) having lower electrodes respectively self-aligned to node conductive layer patterns and methods of forming the same: A ferroelectric random access memory (FRAM) includes a semiconductor substrate and an interlayer insulating layer on the substrate. A diffusion preventive layer is on the interlayer insulating layer. The diffusion preventive layer and the interlayer insulating layer have two node contact holes formed therein. Node conductive layer patterns are aligned...

20060033133 - Mram cell having shared configuration: A magnetic memory includes two first magnetic layers each oriented over a substrate, a second magnetic layer interposing the two first magnetic layers, and two dielectric layers each contacting the second magnetic layer and interposing the second magnetic layer and one of the two first magnetic layers. Each of the...

20060033138 - Method for manufacturing semiconductor device, and semiconductor device: A manufacturing method for a semiconductor device that has a first region for memory elements and a second region for elements other than memory elements on a substrate, includes forming a first interlayer dielectric film on the substrate. A first opening section, which is made to reach the substrate, is...

20060033137 - Methods of forming capacitors for semiconductor memory devices and resulting semiconductor memory devices: Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first...

20060033136 - Mram over sloped pillar: An apparatus including a pillar located over a substrate and having at least one sloped surface oriented at an acute angle relative to the substrate. The apparatus also includes an MRAM stack substantially conforming to the sloped surface, the MRAM stack thereby also oriented at the acute angle relative to...

20060033139 - Semiconductor device and method of manufacturing the same: The present invention provides a semiconductor device comprising a capacitive element with a very uniform capacitive value as well as a method of manufacturing the semiconductor device. In a capacitive element formation region 20 of a semiconductor device 1, an N-type well 22 as a conductive layer is formed in...

20060033140 - Memory circuitry: The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors. Individual of the capacitors include a storage node electrode, a capacitor dielectric region, and a cell electrode. The cell electrode is commonly shared among at least some of the...

20060033141 - Method of manufacturing a semiconductor device having trenches for isolation and capacitor: At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor is increased, which enables improvement of the capacitance of...

20060033142 - Non-volatile memory device and method for manufacturing the same: An increase of charge storing capacity, prevention of an over-erase, and a reduction of ΔVth may be achieved when a 2-bit/cell non-volatile memory device includes a gate of a predetermined width above a semiconductor substrate, an insulating layer between the gate and the semiconductor substrate and at lateral sides of...

20060033147 - Flash memory structure and fabrication method thereof: A flash memory structure comprises a semiconductor substrate, a source region, a drain region, a first insulating dielectric layer, a floating gate, a second insulating dielectric layer, and a control gate. The semiconductor substrate has a first top surface and a second top surface that is lower than the first...

20060033145 - Integrated memory device and process: A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of...

20060033144 - Non-planar flash memory array with shielded floating gates on silicon mesas: A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions....

20060033143 - Non-volatile memory cell and manufacturing method thereof: A non-volatile memory cell includes a substrate, a first isolation structure positioned in a first region on the substrate, a second isolation structure surrounding a second region on the substrate, a control gate positioned on the first isolation structure in the first region, a first insulating layer positioned on the...

20060033146 - P-channel electrically alterable non-volatile memory cell: A nonvolatile memory cell is provided. The memory cell comprises a storage transistor and an injector in a semiconductor substrate of a p-type conductivity. The injector comprises a first region of the p-type conductivity and a second region of an n-type conductivity. The storage transistor comprises a source, a drain,...

20060033148 - Semiconductor device and method of fabricating the same: A semiconductor device such as a flash memory includes a semiconductor substrate, two gate insulating films formed on the substrate so as to have a first film thickness and a second film thickness smaller than the first film thickness respectively, and a polycrystalline silicon film formed on the gate insulating...

20060033149 - Semiconductor device and method of manufacturing the same: An EEPROM cell includes first and second assist gates on opposite sides of a charge retaining insulating layer. Current in the EEPROM memory cell flows between inversion layers, which are created in response to a bias applied to the assist gates. The insulating layer can include silicon nitride, which is...

20060033151 - Flash memory having memory section and peripheral circuit section and manufacturing the same: A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region,...

20060033150 - Nonvolatile memory device and method for fabricating the same: A nonvolatile memory device and a method for fabricating the same decreases power consumption and prevents contamination of an insulating layer. The nonvolatile memory devices includes a semiconductor substrate; a tunneling oxide layer formed on a predetermined portion of the semiconductor substrate; a floating gate formed on the tunneling oxide...

20060033152 - Non-volatile memory device and method of fabricating the same: A non-volatile memory device having improved electrical characteristics and a method of fabricating the non-volatile memory device are provided. The non-volatile memory device includes a gate electrode, which is formed on a semiconductor substrate on which source and drain regions are formed, a trapping structure, which is interposed between the...

20060033153 - Semiconductor device with improved breakdown voltage and high current capacity: The superjunction semiconductor device includes a drain drift section, which includes a first alternating conductivity type layer formed of first n-type regions and first p-type regions arranged alternately. The device also includes a peripheral section around the drain drift section, which includes a second alternating conductivity type layer formed of...

20060033154 - Mosgated power semiconductor device with source field electrode: A power semiconductor device which includes a source field electrode, and at least one insulated gate electrode adjacent a respective side of the source field electrode, the source field electrode and the gate electrode being disposed in a common trench, and a method for fabricating the device....

20060033157 - Field effect transistor and application device thereof: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4....

20060033156 - High voltage and low on-resistance ldmos transistor having radiation structure and isolation effect: A high voltage LDMOS transistor according to the present invention includes at least one P-field block in the extended drain region of the N-well. The P-field blocks form junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete...

20060033155 - Method of making and structure for ldmos transistor: A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped...

20060033158 - Method for fabricating a recessed channel field effect transistor (fet) device: A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a...

20060033159 - Semiconductor integrated circuit device: A MOS transistor for composing a multi-Vth device is provided by selectively arranging a nitride film to overlap with the gate elect