Active solid-state devices (e.g., transistors, solid-state diodes) inventions 01/06

20060017049 - Large area electron emission system for application in mask-based lithography, maskless lithography ii and microscopy: The present invention relates to a various systems for generating and directing electron flow, and related methods, manufacturing techniques and related componentry, such as can be used in lithography, microscopy and other applications. In one embodiment, the present invention involves a system that includes an electron source having a plurality...

20060017050 - Light-emitting device: To provide a light-emitting device which can emit light with high luminance and high efficiency, and is excellent in durability. The light-emitting device includes an organic compound layer containing a phenanthroline compound represented by the general formula [I] and a carbonate....

20060017051 - Apparatus having photoelectric converting element, and device manufacturing method: Disclosed is an apparatus that includes an output unit having a photoelectric converting element, for producing a signal corresponding to light incident on the photoelectric converting element, a restricting unit for restricting a light receiving region of the photoelectric converting element to one of a first region and a second...

20060017052 - Method of fabricating semiconductor device and semiconductor fabricated by the same method: A semiconductor device and method of fabricating the same are provided. The method includes: depositing a silicon layer containing amorphous silicon on a substrate; partially crystallizing the amorphous silicon by applying an annealing process to the silicon layer under an atmosphere of H2O at a predetermined temperature; forming a polycrystalline...

20060017053 - Semiconductor device and a method of manufacturing the same, integrated circuit, electro-optical device, and electronic apparatus: Aspects of the invention provide a method, in a semiconductor device, such as a thin film transistor, a technology capable of preventing or reducing the electric field concentration at the edge section of the semiconductor film to enhance the reliability. The method of manufacturing a semiconductor device according to the...

20060017054 - Liquid crystal display device and fabricating method thereof: A horizontal electric field applying type thin film transistor substrate of a LCD device having an increased aperture ratio as well as a simplified manufacturing process. The device includes a gate line having a double layered structure including a transparent first conductive layer and an opaque second conductive layer, a...

20060017056 - Field plate trench transistor: A field plate trench transistor (20-60) has a semiconductor body (3) which contains a plurality of trenches (9) which are isolated from one another by mesa regions. The trenches (9) contain gate electrodes (11) for controlling a vertical flow of current through the semiconductor body (3). At least one portion...

20060017055 - Method for manufacturing a display device with low temperature diamond coatings: A display device with multiple low temperature diamond coatings, including a substrate as a base; an anode layer residing on the diamond substrate for emitting holes; a hole drift layer that includes a doped diamond coating residing on the anode layer; an emissive layer for emitting light and residing on...

20060017057 - Device structure to improve oled reliability: An organic light emitting diode (“OLED”) device is formed with a thick light emitting polymer layer, hole transporting layer and an interlayer between the thick LEP layer and the hole transporting layer....

20060017058 - Construction of led circuit board: A LED circuit board construction having the circuit board provided with a pit carrier on a baseboard; multiple conduction circuits of different polarities being provided on the peripheral of the carrier; one end of the conduction circuit facing the carrier related to a chip conductor maintaining a fixed spacing from...

20060017059 - Packaged oled light source: A packaged organic light emitting diode (OLED) light source, comprising one or more OLED devices fabricated on a substrate and sealed with a cover, wherein at least one of the substrate and cover comprises a polymer layer and the OLED device is packaged in a sealed storage container having a...

20060017060 - Vertical conducting nitride diode using an electrically conductive substrate with a metal connection: A semiconductor device using an electrically conductive substrate that has a metal connection includes an n-type/p-type electrically conductive substrate and one buffer layer formed on the n-type/p-type electrically conductive substrate. An electrically conductive semiconductor layer is formed on the buffer layer, and the metal connection is formed between the electrically...

20060017061 - Nitride semiconductor light emitting device: A nitride semiconductor light emitting device comprising an n-side nitride semiconductor layer and a p-side nitride semiconductor layer formed on a substrate, with a light transmitting electrode 10 formed on the p-side nitride semiconductor layer, and the p-side pad electrode 14 formed for the connection with an outside circuit, and...

20060017062 - Semiconductor optical device: In a semiconductor optical device, a first conductive type semiconductor region is provided on a surface of GaAs. The first conductive type semiconductor region has a first region and a second region. An active layer is provided on the first region of the first conductive type semiconductor region. The active...

20060017063 - Metamorphic buffer on small lattice constant substrates: A semiconductor device is supported by a substrate with a smaller lattice constant. A metamorphic buffer provides a transition from the smaller lattice constant of the substrate to the larger lattice constant of the semiconductor device. In one application, the semiconductor device has a lattice constant of between approximately 6.1...

20060017064 - Nitride-based transistors having laterally grown active region and methods of fabricating same: High electron mobility transistors and/or methods of fabricating high electron mobility transistors that include a first Group III-nitride layer having vertically grown regions, laterally grown regions and a coalescence region are provided. A Group III-nitride channel layer is provided on the first Group III-nitride layer and a Group III-nitride barrier...

20060017065 - Bipolar transistor and fabrication method of the same: A bipolar transistor having a base electrode of an air bridge structure is simplified in structure and enhanced in the degree of freedom of a contact position of a base wiring line with the base electrode. The bipolar transistor has a semiconductor mesa portion having a base layer formed on...

20060017066 - Methods of base formation in a bicmos process: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow...

20060017067 - Semiconductor device and power supply unit utilizing the same: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals...

20060017068 - Integrated circuit with on-chip memory and method for fabricating the same: An integrated circuit includes an on-chip memory having bit lines, which is formed in a metal layer; and an embedded passage wiring that is arranged in the metal layer or above so as to avoid a cross-talk noise with the bit lines. The embedded passage wiring is electrically connected to...

20060017069 - Electronic component with an adhesive layer and method for the production thereof: The present invention relates to an electronic module having a layer of adhesive between metallic surfaces of components of the module. The metallic surfaces are arranged facing one another. The adhesive of the layer of adhesive includes agglomerates of nanoparticles, which form paths, surrounded by an adhesive base composition, in...

20060017070 - Semiconductor device: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region...

20060017071 - Semiconductor integrated circuit: There is provided a high-performance semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a switch block for switching connections among a plurality of signal lines by means of a plurality...

20060017072 - Cmos active pixel sensor with improved dark current and sensitivity: An active pixel sensor which provides reduced dark current, improved sensitivity, and improved modulation transfer function. An N well, surrounded by a P well is formed in a P type epitaxial substrate. A P+ region is formed extending from within the P well into the substrate leaving a gap between...

20060017073 - Semiconductor device and method of fabricating the same: A first buffer layer is formed on a substrate at a lower temperature than a single-crystal-growth-temperature, one or more of a layer composed of a nitride containing neither Ga nor In, a layer which has two or more thin films having different moduli of elasticity cyclically laminated therein, and a...

20060017074 - Raised-lines overlay semiconductor targets and method of making the same: The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present...

20060017075 - Image sensor production method and image sensor: A production method for an image sensor which is provided with a plurality of sensor portions arranged on a semiconductor substrate and each having a first photodiode constituted by a first region of a first conductivity type and a second region of a second conductivity type different from the first...

20060017076 - Electric device with phase change material and metod of manufacturing the same: The electric device (100) has a body (102) having a resistor (107) comprising a phase change material being changeable between a first phase and a second phase. The resistor (107) has a first electrical resistance when the phase change material is in the first phase, and a second electrical resistance,...

20060017077 - Semiconductor device having switch circuit to supply voltage: A memory cell array has memory cells arranged in a matrix form. The memory cell includes a floating gate and a control gate. Word lines are each coupled to the control gates of the memory cells which are arranged on a corresponding one of the rows in the memory cell...

20060017078 - Accufet with schottky source contact: An accumulation mode FET (ACCUFET) which includes an insulated gate, an adjacently disposed insulated source field electrode, and a source contact that makes Schottky contact with the base region of the ACCUFET....

20060017079 - N-type transistor with antimony-doped ultra shallow source and drain: We disclose a process for forming ultra shallow n+p junctions. The junction is formed by, for example, implanting 3E14 ions/cm2 of antimony ions at 5 keV into silicon. The silicon is pre-amorphized by a previous ion-implantation. The pre-amorphizing implant species may be germanium or arsenic. Germanium may be implanted at...

20060017080 - Field-effect transistor: The field-effect transistor includes: a ferromagnetic layer, having a film thickness of 50 nm or less, which is made of a Ba—Mn oxide showing ferromagnetism at 0° C. or higher; a dielectric layer made of a dielectric material or a ferroelectric material, and the ferromagnetic layer and the dielectric layer...

20060017082 - Magnetic random access memory having magnetoresistive element: A magnetic random access memory includes a magnetoresistive element which has a recording layer, a fixed layer, and an intermediate nonmagnetic layer, the recording layer comprising a first ferromagnetic layer formed on the intermediate nonmagnetic layer, a first nonmagnetic layer formed on the first ferromagnetic layer, a second ferromagnetic layer...

20060017081 - Magnetic tunnel junction element structures and methods for fabricating the same: Magnetic tunnel junction (“MTJ”) element structures and methods for fabricating MTJ element structures are provided. An MTJ element structure may comprise a crystalline pinned layer, an amorphous fixed layer, and a coupling layer disposed between the crystalline pinned layer and the amorphous fixed layer. The amorphous fixed layer is antiferromagnetically...

20060017083 - Multi-state magnetoresistance random access cell with improved memory storage density: A multi-state magnetoresistive random access memory device having a pinned ferromagnetic region with a magnetic moment vector fixed in a preferred direction in the absence of an applied magnetic field, a non-ferromagnetic spacer layer positioned on the pinned ferromagnetic region, and a free ferromagnetic region with an anisotropy designed to...

20060017084 - Integrated semiconductor metal-insulator-semiconductor capacitor: An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and...

20060017085 - Nand flash memory with densely packed memory gates and fabrication process: NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source...

20060017086 - Semiconductor device and method for manufacturing the same: There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film....

20060017087 - Semiconductor device and method of manufacturing the same utilizing permittivity of an insulating layer to provide a desired cross conductive layer capacitance property: A supplemental capacitor is formed using the large capacitance between the wirings (M11 and M12) and that between the through-holes (B11 and B12) because of downsizing of the process technique. The inter-wiring capacitor and inter-through-hole capacitor can be arranged at any optional position within the semiconductor device. The supplemental capacitor...

20060017088 - Dram layout with vertical fets and method of formation: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a...

20060017089 - Method and apparatus for providing capacitor feedthrough: A capacitor feedthrough assembly with a cavity, comprising a capacitor stack, including one or more substantially flat anode layers and one or more substantially flat cathode layers in a case with a cover, the case having a first opening sized for passage of the capacitor stack and a second opening...

20060017090 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a cylinder-shaped capacitor. The capacitor includes a second insulating layer formed with a recessed portion formed on a semiconductor substrate, a cylinder shaped lower electrode formed in the recessed portion, a capacitance layer formed on the lower electrode, and an upper electrode formed on the capacitance...

20060017091 - Method and apparatus for nonvolatile memory: Method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for nonvolatile memory device. The device has a strain source, an injection filter, a tunneling gate, a ballistic gate, a charge storage region, a source, and a drain with a channel defined between the source and drain. The...

20060017092 - Method for simultaneously fabricating ono-type memory cell, and gate dielectrics for associated high voltage write transistors and gate dielectrics for low voltage logic transistors by using issg: Conventional fabrication of top oxide in an ONO-type memory cell stack usually produces Bird's Beak. Certain materials in the stack such as silicon nitrides are relatively difficult to oxidize. As a result oxidation does not proceed uniformly along the multi-layered height of the ONO-type stack. The present disclosure shows how...

20060017095 - Carburized silicon gate insulators for integrated circuits: Silicon carbide films are grown by carburization of silicon to form insulative films. In one embodiment, the film is used to provide a gate insulator for a field effect transistor. The film is grown in a microwave-plasma-enhanced chemical vapor deposition (MPECVD) system. A silicon substrate is first etched in dilute...

20060017094 - Non-volatile memory devices with improved insulation layers and methods of manufacturing such devices: Non-volatile memory devices are provided which include a plurality of gate structures on a substrate. In these devices, a first insulation interlayer is on both the substrate and on the plurality of gate structures, and includes an opening therein. A common source line is in the opening in the first...

20060017093 - Semiconductor devices with overlapping gate electrodes and methods of fabricating the same: A semiconductor device, such as a flash memory device, includes an isolation region provided in a trench in a substrate and having a recess therein. The device also includes a tunnel oxide layer pattern on the substrate adjacent the isolation region, and a first gate electrode provided on the tunnel...

20060017096 - Semiconductor device: A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor...

20060017097 - Method of manufacturing a trench-gate semiconductor device: A method of making a trench MOSFET includes forming a nitride liner 50 on the sidewalls 28 of a trench and a plug of doped polysilicon 26 at the bottom of a trench. The plug of polysilicon 26 may then be oxidised to form a thick oxide plug 30 at...

20060017099 - Mos transistor having a recessed gate electrode and fabrication method thereof: A metal oxide semiconductor (MOS) transistor having a recessed gate electrode and a fabrication method thereof are provided. The MOS transistor includes a semiconductor substrate and an isolation layer formed in a predetermined region of the semiconductor substrate to define an active region. A channel trench region is disposed within...

20060017098 - Semiconductor device with a high-k gate dielectric and a metal gate electrode: A semiconductor device is described that comprises a gate dielectric and a metal gate electrode that comprises an aluminide....

20060017100 - Dynamic deep depletion field effect transistor: A vertical conduction trench FET has a plurality of trenches containing conductive polysilicon gates. The mesas between the trenches have a source diffusion region connected to a common source electrode. The trenches are spaced so that the depletion regions induced by the trench gate will overlap to pinch off conduction...

20060017101 - Semiconductor integrated circuit and manufacturing method of the same: There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring...

20060017102 - Ldmos device and method of fabrication: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface...

20060017103 - Method for making reduced size dmos transistor and resulting dmos transistor: A method is provided for making a laterally extended drain DMOS transistor. According to the method, a gate having two substantially parallel lateral faces is produced on a substrate, and a drain spacer and a source spacer made of an insulating material are produced on the lateral faces of the...

20060017104 - Semiconductor device having a channel pattern and method of manufacturing the same: A semiconductor device may include a tubular channel pattern vertically extending from a semiconductor substrate. A gate insulation layer may be provided on faces exposed through the channel pattern. A gate electrode may be provided on the gate insulation layer. The gate electrode may fill the channel pattern. A conductive...

20060017105 - Semiconductor device and method of fabricating the same: A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide...

20060017106 - Tft, electronic device having the tft, and flat display device having the tft: The invention provides an improved thin film transistor (TFT) that can be formed at room temperature and has an improved contact resistance between an active layer and source and drain electrodes, and further provides a flat display device using such a TFT. The TFT includes an active layer including at...

20060017107 - Metal gate engineering for surface p-channel devices: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in...

20060017108 - Nano and mems power sources and methods thereof: A power source and methods thereof includes a structure comprising one or more p type layers, one or more n type layers, and one or more intrinsic layers and at least one source of radiation is disposed on at least a portion of the structure. Each of the p type...

20060017109 - High voltage esd-protection structure: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the...

20060017110 - Semiconductor device with low resistance contacts: An N channel transistor and a P channel transistor have their source/drains contacts with different suicides to provide for low resistance contacts. The silicides are chosen to provide good matching of the work functions. The P-type source/drain contacts of the P channel transistors have a silicide that is close to...

20060017111 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, an interlayer insulating film formed so that the gate electrode is buried therein, a contact hole formed in the interlayer insulating film so as to...

20060017113 - High transconductance and drive current high voltage mos transistors: A composite MOS transistor (100) includes a first MOS sub-transistor (105) having a first gate dielectric thickness (106), and a second MOS sub-transistor (155) in series connection with the first MOS sub-transistor having a second gate dielectric thickness (107). The second gate dielectric thickness (107) is substantially thicker than the...

20060017112 - Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof: A process and apparatus for a semiconductor device is provided. A device comprises a first transistor having a first charge carrier type. The first transistor comprises a high-k gate dielectric and a first doped electrode. The first charge carrier type comprises one of p-type and n-type and the first doped...

20060017114 - Method for fabricating integrated circuits having both high voltage and low voltage devices: A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of...

20060017115 - One-transistor random access memory technology compatible with metal gate process: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM...

20060017116 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device includes forming a gate insulating layer, a gate and a protective layer on a semiconductor substrate, forming a spacer on lateral sides of the protective layer and the gate, forming one or more junction regions in the semiconductor substrate at sides of the...

20060017117 - Semiconductor device and method for fabricating the same: A semiconductor device includes a resistor element covered by a silicon oxide film. In the semiconductor device, with respective gate electrodes of MIS transistors and impurity doped layers, i.e., non-silicide regions exposed, thermal treatment for activating an impurity and silicidization are performed. Thus, auto-doping of an impurity is suppressed, so...

20060017118 - Semiconductor device having spacer pattern and method of forming the same: The present invention provides a semiconductor device having a spacer pattern and methods of forming the same that includes a lower interconnection pattern on a semiconductor substrate. A lower interconnection spacer covers sidewalls of the lower interconnection pattern. Spacer patterns cover the lower interconnection spacer of the lower interconnection pattern...

20060017119 - Multi-gate transistor and method of fabricating multi-gate transistor: A multi-gate transistor and a method of fabricating the multi-gate transistor may involve forming an active pattern with a multi-channel region, in which a channel region is provided on at least two surfaces of the active pattern. An interconnect may be connected to an interconnect region of the active pattern...

20060017120 - Semiconductor-ferroelectric storage device and its manufacturing method: The MFIS transistors heretofore have a problem that after data writing, the data disappear in terms of memory transistor operation in about one day at most. This is mainly because the buffer layer and the ferroelectric have a high leakage current and, hence, charge is accumulated around the interface between...

20060017121 - Nonvolatile semiconductor memory device and method for fabricating the same: A nonvolatile semiconductor memory device includes: a gate dielectric made of a multilayer dielectric that is formed on a substrate and discretely accumulates charges; a gate electrode formed on the gate dielectric; a pair of diffusion regions formed in the surface of the substrate with the gate electrode interposed therebetween...

20060017122 - Novel metal-gate electrode for cmos transistor applications: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying...

20060017124 - Bistable magnetic device using soft magnetic intermediary material: Roughly described, a magnetic structure includes an electrically conductive path for carrying current flow, a soft magnetic material with high permeability value in magnetic communication with the current flow so that it can be magnetized in either of two directions, and a magnetic device such as a magnetic random access...

20060017123 - Field imager: A detection apparatus for detecting the presence of a sample, the detection apparatus comprising a chamber, ports for introducing a sample within the chamber, an actuation unit for establishing a controllable electromagnetic field in the chamber; and a sensing unit for sensing changes in the electromagnetic field due to the...

20060017125 - Vibration type mems switch and fabricating method thereof: A vibration type MEMS switch and a method of fabricating the vibration type MEMS switch. The vibration type MEMS switch includes a vibrating body supplied with an alternating current voltage of a predetermined frequency to vibrate in a predetermined direction; and a stationary contact point spaced apart from the vibrating...

20060017126 - Thermally written magnetic memory device: A thermally written magnetic memory device is disclosed. The thermally written magnetic memory device includes a plurality of thermally written magnetic tunnel junction devices. Each thermally written magnetic tunnel junction device includes a super-paramagnetically stable data layer. The data layer includes a high coercivity at a read temperature such that...

20060017127 - Optical package for a semiconductor sensor: An optical package for integrated circuit chips including optical microsensors and its manufacturing method, an encapsulation resin thickness smaller than the thickness provided straight above connecting wires being provided at least straight above the microsensors between the upper surface of the chip and a substrate supporting it....

20060017128 - Solid-state imaging apparatus and manufacturing method thereof: A structure member is used wherein a circuit board is connected to a solid-state image pickup element and placed between a portion of the structure member to which the solid-state image pickup element is attached, and another portion to which a light-transmitting member is attached, and the circuit board is...

20060017129 - Avalanche photodiode: An avalanche photodiode has improved low-noise characteristics, high-speed response characteristics, and sensitivity. The avalanche photodiode includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, a semiconductor multiplication layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a semiconductor...

20060017130 - Fast recovery diode with a single large area p/n junction: A fast recovery diode has a single large area P/N junction surrounded by a termination region. The anode contact in contact with the central active area extends over the inner periphery of an oxide termination ring and an EQR metal ring extends over the outer periphery of the oxide termination...

20060017131 - Process for manufacturing an soi wafer by annealing and oxidation of buried channels: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures....

20060017132 - Method for producing a dielectric and semiconductor structure: The present invention relates to a method for producing a dielectric on a semiconductor body having the following steps that are to be performed successively: provision of a semiconductor body, application of a dielectric layer on at least parts of a first surface of the semiconductor body in such a...

20060017133 - Electronic part-containing elements, electronic devices and production methods: An electronic part-containing element used by being incorporated in an electronic device, in which the electronic part-containing element comprises an insulating support member which does not take part in the constitution of the electronic device but is removed in the process of producing the electronic device, and a circuit module...

20060017134 - Input protection circuit preventing electrostatic discharge damage of semiconductor integrated circuit: An input protection circuit comprises a semiconductor chip, an internal circuit disposed on the semiconductor chip, a first input/output terminal which is disposed on the semiconductor chip and connected to the internal circuit, a second input/output terminal which is disposed on the semiconductor chip, connected to the internal circuit and...

20060017136 - Capacitor of analog semiconductor device having multi-layer dielectric film and method of manufacturing the same: In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film...

20060017135 - Layout method of decoupling capacitors: A layout method of decoupling capacitors while ensuring the decoupling capacitance necessary for each grid area. The method includes calculating the total power consumption of logic cells, arranging the decoupling capacitance throughout the subject area in correspondence with the total power consumption, dividing the subject area into a plurality of...

20060017137 - Semiconductor device and its manufacturing method: A semiconductor device and its manufacturing method are achieved which are capable of mixing a plurality of different crystal orientations in SOI substrate surfaces and controlling increase of leakage current into substrates and increase in power consumption in each area. An SOI substrate is fabricated by bonding two semiconductor wafers...

20060017138 - Strain enhanced ultra shallow junction formation: Provided is a method of manufacturing a microelectronic device. In one example where the device includes a semiconductor substrate with a gate feature and a shallow junction, the method includes introducing dopants to the substrate to form a source region and a drain region. A strained layer may be formed...

20060017139 - Thin film semiconductor device and method of manufacturing the same, electro-optical device, and electronic apparatus: A thin film semiconductor device includes a substrate and a semiconductor film formed on the substrate. The thin film semiconductor device further includes a protective circuit element having a PIN diode having the semiconductor film, and a floating electrode disposed opposite to an I layer of the PIN diode with...

20060017140 - Flashless lead frame with horizontal singulation: A lead frame is configured for use with a singulation apparatus that eliminates flash. A die pad is attached to sides of the frame by tie bars and peripheral portions. The peripheral portions have cutout sections defining openings that are bridged by lead frame segments. The apparatus applies a downward...

20060017141 - Power semiconductor package: A semiconductor package including a relatively thick lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die coupled thereto, bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum, and a resin body encapsulating...

20060017142 - Bonding configurations for lead-frame-based and substrate-based semiconductor packages and method of fabrication thereof: In a bonding configuration for a semiconductor device package, the bonding angles of the bonding wires are maintained within acceptable limits, without causing an increase in the chip die size, and without necessitating the use of the corner rule. In this manner, the occurrence of shorting between adjacent bonding wires...

20060017144 - Semiconductor device: The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above...

20060017143 - Semiconductor device and its manufacturing method: There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing...

20060017145 - Semiconductor package with heat sink: A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to...

20060017146 - Ic with stably mounted chip: An IC with stably mounted chip includes a chip, a leadframe, a bridge, and an encapsulating compound. The bridge is a flat arch made of a sheet material and includes a horizontal fixing section and a supporting section downward extended from each end of the fixing section. The chip is...

20060017147 - Method and apparatus for using capacitively coupled communication within stacks of laminated chips: One embodiment of the present invention provides a technique for assembling semiconductor chips. First, multiple semiconductor chips are permanently laminated together into a plurality of laminated chip assemblies, wherein the semiconductor chips within the laminated chip assembly communicate with each other through electrically conductive connections. Next, laminated chip assemblies are...

20060017148 - Semiconductor package and method for its manufacture: A method of manufacturing a semiconductor package having a double encapsulant structure. The method comprises preparing a group substrate. The group substrate includes a plurality of semiconductor chips arranged on the top surface, which chips typically are stacked. The semiconductor chips are electrically connected with the group substrate by bonding...

20060017149 - Substrate-based bga package, in particular fbga package: A ball grid array package includes a substrate. A number of solder balls overlie the solder ball surface of the substrate. The solder balls are arranged within a ballout area. A chip is attached to the chip surface of the substrate by an adhesive layer. Contact pads of the chip...

20060017150 - Multi-chip module and single-chip module for chips and proximity connectors: A single-chip module is described. The module includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the first semiconductor die. A cable coupled...

20060017151 - Bga package board and method for manufacturing the same: Disclosed herein is a Ball Grid Array (BGA) package board. The BGA package board includes a first external layer on which a pattern comprising a circuit pattern and a wire bonding pad pattern is formed, a second external layer on which a pattern comprising a circuit pattern and a solder...

20060017152 - Heterogeneous organic laminate stack ups for high frequency applications: Organic laminate stack ups are disclosed for a variety of applications, including high frequency RF applications. One or more inner core layers may be disposed between outer layers along with bondply or prepreg layers as needed. Discrete devices, including surface mount components and flip chips, may be embedded within the...

20060017153 - Interconnections of semiconductor device and method of forming the same: An interconnection structure includes a substrate containing a first lower interconnection and a pair of second interconnections separated from each other by a predetermined distance, and a metallic compound fuse pattern connecting the second lower interconnections, being positioned over the second lower interconnections. The fuse pattern is formed by using...

20060017154 - Semiconductor device and method for manufacturing same: A method to provide an improved production yield of electronic devices. A thin film device 41 is manufactured by the following method. Semiconductor elements 11 are formed on the substrate 10. Then, a protective film is adhered onto the upper portions of the semiconductor elements 11 using an adhesive agent....

20060017155 - Flip chip package capable of measuring bond line thickness of thermal interface material: A flip chip package includes a substrate, a flip chip, a thermal interface material and a heat sink. The flip chip is mounted on the substrate. The thermal interface material is applied on the back surface of the flip chip. The back surface of the flip chip includes a region...

20060017156 - Method for mounting a chip on a base and arrangement produced by this method: An electronic component includes a base and a chip attached to the base by a plurality of adhesive pads that are spaced apart from one another and are arranged in an intermediate space between the chip and the base. The chip is electrically connected to interconnects of the base. The...

20060017157 - High frequency semiconductor apparatus, transmitting apparatus and receiving apparatus: A high frequency semiconductor apparatus is provided which prevents characteristics of a high frequency semiconductor element from being deteriorated so that the high frequency semiconductor element can be made to operate stably. The high frequency semiconductor apparatus is so configured that heat generated by a high frequency semiconductor element is...

20060017158 - Power supply wiring structure: Provided is a power supply wiring structure which comprises a first and a second power supply wirings, which are disposed on different planes to cross each other two-dimensionally. The first and second power supply wirings are interlayer-connected by a first via at a crossing area where those power supply wirings...

20060017159 - Semiconductor device and method of manufacturing a semiconductor device: According to an aspect of the present invention, there is provided a semiconductor device including a lead frame, a semiconductor chip, a back surface opposed to a main surface of the semiconductor chip disposed on the lead frame, a first electrode formed on the main surface of the semiconductor chip,...

20060017161 - Semiconductor package having protective layer for re-routing lines and method of manufacturing the same: An apparatus and method for manufacturing a semiconductor package are disclosed. The apparatus may include at least a semiconductor chip having input/output (I/O) pads arranged on a surface thereof, a first dielectric layer formed on the surface of the semiconductor chip which may expose the I/O pads, a seed metal...

20060017160 - Structure and formation method of conductive bumps: A method and structure for a conductive bump are provided herein. A conductive surface is provided on a wafer. A conductive barrier layer and a conductive wetting layer on a part of the conductive surface have a bottom and a side wall and further reach up a top surface. The...

20060017163 - Device having contact pad with a conductive layer and a conductive passivation layer: A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material which resists formation of resistive oxides. In particular, a tank is divided into three compartments, each holding a different solution: a lower compartment and two upper compartments divided...

20060017162 - Semiconductor device and manufacturing method of the same: A semiconductor device is disclosed, which comprises a semiconductor substrate, a semiconductor element formed on the semiconductor substrate, and multi-level wiring structure including first wirings at a plurality of levels, in which the first wirings at at least one of the levels are provided at different heights in a cross-sectional...

20060017164 - Semiconductor device: A semiconductor device, wherein an increase of a capacity between wiring layers is suppressed, reliability of wiring and property of withstand voltage of a diffusion prevention insulation film can be improved and the wiring resistance can be maintained low, is provided by comprising an interlayer insulation film formed on a...

20060017165 - Semiconductor device and manufacturing method thereof: A method of manufacturing a semiconductor device comprises the steps as follow. After forming an insulating layer with opening therein over a substrate, a polysilicon layer that partially fills the opening is formed over the substrate and then a refractory metal silicide layer that completely fills the opening is formed...

20060017166 - Robust fluorine containing silica glass (fsg) film with less free fluorine: A semiconductor device and method of manufacture thereof having a less free fluorine (F) fluorine containing Silica Glass (FSG) dielectric film formed thereon. The FSG dielectric film includes about 25% or less free F, has a porosity of about 5% or less and has a dielectric constant of about 3.8...

20060017167 - Semiconductor device: A semiconductor device having a structure which can be manufactured with a higher yield includes a local interconnection layer 14 (a first interconnection layer) on a semiconductor substrate 10 and a global interconnection layer 18 (a second interconnection layer) on the local interconnection layer 14. The local interconnection layer 14...

20060017168 - Semiconductor devices to reduce stress on a metal interconnect: Semiconductor devices to reduce stress on a metal interconnect are disclosed. A disclosed semiconductor device comprises: a semiconductor substrate; an uppermost metal interconnect formed on the semiconductor substrate; an oxide layer formed on the substrate and the uppermost metal interconnect; an aluminum layer formed on the oxide layer; and a...

20060017169 - Electroplated interconnection structures on integrated circuit chips: A process is described for the fabrication of submicton interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features...

20060017170 - Cosb3-based thermoelectric device fabrication method: A method of fabricating a CoSb3-based thermoelectric device is disclosed. The method includes providing a high-temperature electrode, providing a buffer layer on the high-temperature electrode, forming composite n-type and p-type layers, attaching the buffer layer to the composite n-type and p-type layers, providing a low-temperature electrode on the composite n-type...

20060017171 - Formation method and structure of conductive bumps: A formation method and structure of conductive bump are provided. A conductive bump is formed on a wafer through an under bump metallurgy layer. A nickel-based wetting layer in the under bump metallurgy layer is applied on the conductive bump to prevent stannum in the conductive bump from diffusing downwards....

20060017172 - Die and die-package interface metallization and bump design and arrangement: A die metallization and bump design/arrangement, and a die-package interface metallization and bump design/arrangement are described herein....

20060017173 - Flip-chip semiconductor package with lead frame and method for fabricating the same: A flip-chip semiconductor package with a lead frame and a method for fabricating the same are provided. The lead frame has a plurality of leads, each lead having an upper surface, a lower surface, and an inner end directed toward the center of the lead frame. A recessed portion is...

20060017174 - Semiconductor device: The invention relates to a semiconductor device with a semiconductor chip, on which a terminal contact formed in one piece, a patterned metallization layer, contacting the terminal contact, and a connecting layer are successively arranged, the patterned metallization layer and the patterned connecting layer forming an electrically conducting contact layer....

20060017176 - Bump ball device and placing method thereof: The present invention provides a bump ball device and a placing method thereof. The bump ball device having a die on which I/O terminal of a plurality of circuit elements are arranged, includes: a plurality of bonding pads which are electrically connected to the I/O terminals of the circuit elements;...

20060017175 - Collars, support structures, and forms for protuding conductive structures: Collars, support structures, or forms for protruding conductive structures include apertures or receptacles through which the conductive structure may extend. The aperture or receptacle may be configured to contact a surface of the conductive structure, and even to define a shape of at least a portion of the conductive structure....

20060017177 - Microelectronic component assemblies with recessed wire bonds and methods of making same: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, a substrate, and at least one bond wire. The substrate has a reduced-thickness base adjacent terminals of the microelectronic component and a...

20060017178 - Wiring structure for a pad section in a semiconductor device: The wiring structure of a pad section in a semiconductor device includes a row of pads and a plurality of first bias wirings provided at either side of the row of pads on a same plane. The first bias wirings carry electrical signals to the pads. A plurality of second...

20060017179 - Insulated structure of a chip array component and fabrication method of the same: An insulated structure of a chip array component and fabrication method of the same, the element is fabricated by enclosing its main body with a dense layer of high surface insulation resistance material, and then exposing the portions of the main body where terminal electrodes are to be formed by...

20060017180 - Alignment of mtj stack to conductive lines in the absence of topography: A scheme for aligning opaque material layers of a semiconductor device. Alignment marks are formed in a via level of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may have about the same length as vias formed in the via layer. The alignment marks...

20060017181 - Semiconductor memory device and semiconductor device group: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to...

20060011902 - Phase change memory device and method for forming the same: A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical...

20060011903 - Nitride based semiconductor light-emitting device: The present invention provides a semiconductor device having a semiconductor multi-layer structure which includes at least an active layer having at least a quantum well, and the active layer further including at least a luminescent layer of InxAlyGa1-x-yN (0<x<1, 0≦y≦0.2), wherein a threshold mode gain of each of the at...

20060011904 - Layered composite film incorporating quantum dots as programmable dopants: Quantum dots are positioned within a layered composite film to produce a plurality of real-time programmable dopants within the film. Charge carriers are driven into the quantum dots by energy in connected control paths. The charge carriers are trapped in the quantum dots through quantum confinement, such that the charge...

20060011905 - Semiconductor device comprising a superlattice dielectric interface layer: A semiconductor device may include a semiconductor substrate and at least one active device adjacent the semiconductor substrate. The at least one active device may include an electrode layer, a high-K dielectric layer underlying the electrode layer and in contact therewith, and a superlattice underlying the high-K dielectric layer opposite...

20060011906 - Ion implantation for suppression of defects in annealed sige layers: A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed. The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form...

20060011907 - Compounds containing 3,4-methylenedioxythiophene units: m

20060011908 - Light emitting element: The present invention relates to a thin film light emitting element which has low drive voltage. In particular, the present invention relates to a thin film light emitting element which has low drive voltage and in which color purity and luminous efficiency are not deteriorated. A structure of a light...

20060011909 - Organic thin film transistor with polymeric interface: Provided is an organic thin film transistor comprising a polymeric layer interposed between a gate dielectric and an organic semiconductor layer. Various homopolymers, copolymers, and functional copolymers are taught for use in the polymeric layer. An integrated circuit comprising a multiplicity of thin film transistors and methods of making a...

20060011910 - Pcram device with switching glass layer: A memory device, such as a PCRAM, including a chalcogenide glass backbone material with germanium telluride glass and methods of forming such a memory device....

20060011911 - Detection of molecular probes fixed to an active zone of a sensor: The present invention relates to a method for detecting at least one parameter representative of molecular probes fixed to zones of a sensor....

20060011913 - Display device mounted with read function and electric appliance: According to the present invention, a material having a light-shielding property is used for a bank layer surrounding the edge of a light-emitting element. Accordingly, light which is not reflected by an object to be read out can be prevented from entering an image pick-up element, and information on the...

20060011912 - Method of forming a metal pattern and a method of fabricating tft array panel by using the same: With a metal pattern formation process and a method of manufacturing a thin film transistor array panel using the metal pattern formation process, an organometallic layer is formed by coating an organometallic complex containing metal. The organometallic layer is exposed to light through a photo mask, and developed to form...

20060011914 - Novel conductive elements for thin film transistors used in a flat panel display: A novel design for an electrode for a thin film transistor. The novel design allows for formation of a normal conductive channel between a source electrode and a drain electrode even after a heat treatment process, and a flat panel display including the thin film transistor. The thin film transistor...

20060011915 - Nitride semiconductor device: A nitride semiconductor device according to one embodiment of the present invention comprises: a non-doped first aluminum gallium nitride (AlxGa1-xN (0≦x≦1)) layer which is formed as a channel layer; a non-doped or n type second aluminum gallium nitride (AlyGa1-yN (0≦x≦1,x<y)) layer which is formed on the first aluminum gallium nitride...

20060011916 - Substrate for epitaxial growth, process for producing the same, and multi-layered film structure: A substrate for epitaxial growth includes a silicon-containing substrate, a silicon-germanium film, and a network-shaped structure. The silicon-germanium film is formed lamellarly on the silicon-containing substrate. The network-shaped structure is disposed adjacent to an interface between the silicon-containing substrate and the silicon-germanium film, and is composed of a 90-degree-dislocation dislocation...

20060011918 - Flat panel display device and method of manufacturing the same: A flat panel display includes a pixel electrode having an opening portion formed on an insulating substrate, a semiconductor layer formed over a surface of the insulating substrate, spaced apart from the pixel electrode, having source and drain regions formed to both end portions thereof, a first insulating layer formed...

20060011917 - Thin film transistor, flat panel display device therewith, and method of manufacturing the thin film transistor: A thin film transistor that does not deform or exfoliate due to thermal or mechanical stress, a flat panel display having the same, and a method manufacturing the same, the thin film transistor including a substrate, a patterned buffer layer disposed on the substrate, a patterned active layer disposed on...

20060011919 - Vertical gate device for an image sensor and method of forming the same: A CMOS pixel cell having a charge transfer transistor adjacent the photo-conversion device. The transistor has a channel region surrounded by a gate and an upper source/drain region over the channel region....

20060011921 - Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films: A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor...

20060011920 - Thin film transistor array panel and manufacturing method thereof: Gate lines and a gate shorting bar connected to the gate lines, which include lower and upper films, are formed on a substrate. A gate insulating layer, semiconductors, and ohmic contacts are formed in sequence. Data lines and a data shorting bar connected to the data lines, which include lower...

20060011922 - Light-emitting device comprising an eu(ii)-activated phosphor: The invention concerns a light emitting device comprising a light emitting structure capable of emitting primary light of a wavelength less then 480 nm and a luminescent screen comprising a phosphor of general formula (Sr1-a-bCabBacMgdZne)SixNyOz:Eua, wherein 0.002≦a≦0.2, 0.0≦b≦0.25, 0.0≦c≦0.25, 0.0≦d≦0.25, 0.0≦e≦0.25, 1.5≦x≦2.5, 1.5≦y≦2.5 and 1.5≦z≦2.5. The invention also concerns a...

20060011923 - Electromagnetic radiation generating semiconductor chip and method for making same: An electromagnetic radiation generating semiconductor chip is disclosed. A semiconductor layer sequence suitable for generating electromagnetic radiation is grown on a first main face of a radioparent, electrically conductive growth substrate, for example, a SiC growth substrate. Provided on a second main face of said growth substrate that faces away...

20060011924 - Monolithic vertical junction field effect transistor and schottky barrier diode fabricated from silicon carbide and method for fabricating the same: A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The...

20060011925 - Radiation-emitting semiconductor element and method for producing the same: The invention also describes a production method for a semiconductor component pursuant to the invention. An interlayer (9) is first applied to a substrate (8), and a plurality of GaN layers (1) that constitute the semiconductor body of the component are then applied to this. The substrate (8) and the...

20060011926 - Light-emitting diode device with resecurable connection: An LED device includes a scrambler portion, a substrate portion having a light-emitting diode (“LED”) and a substrate layer attached to the LED, an electrical connection between the LED and the substrate layer, and a resecurable connection between the scrambler portion and the substrate layer....

20060011927 - Organic light emitting devices and electroluminescent display panel applying the same: Organic light emitting devices include an anode, a cathode and a plurality of organic light emitting units. The adjacent organic light emitting units are separated by a charge transfer layer formed of various fullerenes in combination. The charge transfer layer may be a relatively homogenous layer that is a mixture...

20060011928 - Surface-mountable light-emitting diode and/or photodiode and method for the production thereof: A surface-mountable miniature luminescent diode with a chip package which has a leadframe (16) and a semiconductor chip (22) which is arranged on the leadframe (16) and is in electrical contact with it and which contains an active, radiation-emitting region. The leadframe (16) is formed by a flexible multi-layered sheet...

20060011929 - Rotating display device: A device for displaying an image is provided. The device includes a hub that is configured to rotate about a first axis and a motor configured to rotate the hub about the first axis. A plurality of light detecting devices attached to the hub and at least one lens configured...

20060011930 - Semiconductor photodetecting device and method of manufacturing the same: An object of the present invention is to provide a semiconductor photodetecting device that enables a solid-state image sensor to meet requirement of higher quality imaging and more reduction in cost, and the semiconductor photodetecting device includes a semiconductor substrate, and an epitaxial layer that is formed on the semiconductor...

20060011931 - Ic package with an integrated power source: A radioactive power source resident in an IC package is provided. The power source is a stand-alone device, fabricated separately from the IC or other device that is eventually attached to the package. The power source may be attached to the packaging substrate or to another portion of the package...

20060011932 - Complementary metal oxide semiconductor image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same is disclosed, to enhance the efficiency in condensing the light by forming a multi-layered micro lens with various materials having different refractive indexes, in which the CMOS image sensor includes a plurality of photosensitive devices on a semiconductor substrate;...

20060011933 - Optoelectronic device manufacturing: Provides optoelectronic devices and methods for manufacturing an optoelectronic devices. Optoelectronic devices including a capping layer for improving out-coupling and optical fine-tuning of emission characteristics. The present invention is particularly advantageous for top-emitting devices and for organic light emitting devices. An example optoelectronic device includes an optoelectronic member for emitting...

20060011935 - Light extraction from a semiconductor light emitting device via chip shaping: A method for designing semiconductor light emitting devices is disclosed wherein the side surfaces (surfaces not parallel to the epitaxial layers) are formed at preferred angles relative to vertical (normal to the plane of the light-emitting active layer) to improve light extraction efficiency and increase total light output efficiency. Device...

20060011934 - Semiconductor light-emitting element and manufacturing method thereof: An improvement in electrode reliability is realized by preventing over-etching on a peripheral lower portion of an electrode while maintaining the flow of steps of roughening a surface after forming the electrode on a semiconductor substrate. After a P-side electrode 4 is formed on a main surface 3a of a...

20060011936 - Fluorescent substance containing nitrogen, method for manufacturing the same, and light-emitting device: Disclosed is a method for manufacturing a nitrogen-containing fluorescent substance comprising accommodating an oxide fluorescent substance containing two or more elements in a receptacle made of a material containing carbon, and sintering the oxide fluorescent substance in a mixed gas atmosphere containing nitrogen gas....

20060011937 - Strain-controlled iii-nitride light emitting device: In a III-nitride light emitting device, a ternary or quaternary light emitting layer is configured to control the degree of phase separation. In some embodiments, the difference between the InN composition at any point in the light emitting layer and the average InN composition in the light emitting layer is...

20060011938 - Super lattice tunnel junctions: Super lattice structures in conjunction with a tunnel junction to provide an improved contact for multiple components. The tunnel junctions can include a first semiconductor material having a resistance parameter for conducting a current and a second semiconductor material having a resistance parameter that is more restrictive to conduction of...

20060011939 - Two-dimensional silicon controlled rectifier: A two-dimensional silicon controlled rectifier (2DSCR) having the anode and cathode forming a checkerboard pattern. Such a pattern maximizes the anode to cathode contact length (the active area) within a given SCR area, i.e., effectively increasing the SCR width. Increasing the physical SCR area, increases the current handling capabilities of...

20060011940 - Thyristor-type memory device: A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to...

20060011941 - Substrate for growing electro-optical single crystal thin film and method of manufacturing the same: A substrate 1 for growing an electro-optical single crystal thin film in which two or more layers of buffer layers 3, 4, and 5 for buffering lattice mismatch between Si and BTO are formed on an Si (001) substrate 2 is provided as a substrate for growing an electro-optical single...

20060011942 - 2-terminal semiconductor device using abrupt metal-insulator transition semiconductor material: Provided is a 2-terminal semiconductor device that uses an abrupt MIT semiconductor material layer. The 2-terminal semiconductor device includes a first electrode layer, an abrupt MIT semiconductor organic or inorganic material layer having an energy gap less than 2eV and holes in a hole level disposed on the first electrode...

20060011943 - Bipolar transistor having base over buried insulating and polycrystalline regions, and method of fabrication: A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface layer; a base contact (130 and 131) extending through a substantial portion (141) of...

20060011944 - Semiconductor device: A semiconductor device provided with an emitter layer having a narrowed base contact portion. The semiconductor device includes a collector layer arranged on a semiconductor substrate. A conductive layer is arranged on the collector layer. A silicon film is arranged on the conductive layer. An emitter electrode is arranged on...

20060011945 - Photocatalyst and process for purifying gas effluent by photocatalytic oxidation: The photocatalyst based on a composite WO3—SiC/TiO2 semiconductor and subjected to radiation whose wavelength is at least partly less than 400 nm gives photocatalytic oxidation of volatile organic compounds and leads to their total mineralisation into CO2 and H2O. The process for the photocatalytic purification of industrial, agricultural or domestic...

20060011946 - Nitride semiconductor laser element: A nitride semiconductor laser element capable of controlling the lateral confinement of light with a good reproducibility, the nitride semiconductor element comprising an n-type cladding layer (3), an MQW light emitting layer (4) formed on the cladding layer (3), a p-type cladding layer (5) and a p-type contact layer (6)...

20060011947 - Semiconductor structures and memory device constructions: The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as...

20060011948 - Structure and method of fabricating a transistor having a trench gate: An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the...

20060011949 - Metal-gate cmos device and fabrication method of making same: A metal-gate complementary metal-oxide-semiconductor (CMOS) device is disclosed. The CMOS device includes a PMOS transistor formed on a first area of a substrate and a NMOS transistor formed on a second area of the substrate and being coupled to the PMOS transistor. The PMOS transistor includes a first gate stack...

20060011950 - Semiconductor device and method of manufacturing the same: Disclosed is a semiconductor device comprises a semiconductor substrate having on its surface a trench, a polycrystalline semiconductor film formed inside the trench, a diffusion layer deposited on a surface region of the semiconductor substrate, and a metal semi-conductor nitride layer interposed between the diffusion layer and the polycrystalline semiconductor...

20060011951 - Process for fabricating non-volatile memory by tilt-angle ion implantation: A potassium/sodium ion sensing device applying an extended-gate field effect transistor, which using an extended-gate ion sensitive field effect transistor (EGFET) as base to fabricate a potassium/sodium ion sensing device, using the extended gate of the extended-gate ion sensitive field effect transistor as a signal intercept electrode, and immobilizing the...

20060011954 - Semiconductor photodetecting device and method of manufacturing the same: A semiconductor photodetecting device is provided for enabling a solid-state image sensor to meet the requirements of higher quality imaging and more reduction in cost. The photodetecting device of the present invention includes: a semiconductor substrate; and an epitaxial layer formed on the semiconductor substrate by epitaxial growth. The epitaxial...

20060011953 - Solid state imaging device and method of manufacturing the same: A solid-state imaging device including a photoelectric conversion portion and a charge transfer portion equipped with charge transfer electrodes to transfer the charge generated in the photoelectric conversion portion, wherein the charge transfer portion is provided with a charge transfer electrodes having a first electrode including a first layer electric...

20060011952 - Solid-state image sensor and method for fabricating the same: A solid-state image sensor comprises a semiconductor substrate of a first conductivity type having a color pixel region and a black pixel region; a first well of the first conductivity type formed in the color pixel region; a second well of the first conductivity type formed in the black pixel...

20060011957 - Information detecting device for photo film: A photo film scanner for photo film having an image frame has plural light sources, which apply illuminating light to the photo film, and include a multi-chip LED packages having plural chips for emitting the illuminating light at wavelengths different from one another. Plural photo receptors receive light from the...

20060011955 - Pixel cell having a grated interface: A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with said silicon substrate, and a method of fabricating the pixel cell having a grated interface....

20060011956 - Solid-state image sensor: The solid-state image sensor includes a pixel part 10, an analog circuit part 12, a digital circuit part 14 and an input/output circuit part 16. The digital circuit part 14 includes a first well 42c of a second conduction type formed in a second region of a semiconductor substrate 20...

20060011958 - Magnetic random access memory with bit line and/or digit line magnetic layers: A magnetic random access memory (MRAM) device may include a substrate, a first magnetic layer on the substrate, and a digit line on the first magnetic layer. A magnetic tunnel junction structure may be provided adjacent the digit line, and a bit line may be provided on the magnetic tunnel...

20060011959 - Semiconductor devices having a planarized insulating layer and methods of forming the same: A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping...

20060011960 - Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and...

20060011961 - Thin film capacitor: A thin film capacitor includes a pair of electrodes and a dielectric layer having piezoelectricity sandwiched therebetween. The phase characteristic of an impedance resulting from application of a voltage to the pair of electrodes peaks periodically according to a frequency of a signal to be inputted or outputted. The frequency...

20060011962 - Accumulation device with charge balance structure and method of forming the same: An accumulation-mode field effect transistor includes a plurality of gates and a semiconductor region having a channel region adjacent to but insulated from each of the plurality of gates. The semiconductor region further includes a conduction region wherein the channel regions and the conduction region are of a first conductivity...

20060011963 - Method and apparatus for interconnecting electrodes with partial titanium coating: The present subject matter includes a capacitor stack having a plurality of anode layers, and a plurality of cathodic metal substrates partially coated in a titanium coating. Cathode portions lacking titanium enable weld interconnections which are substantially free of titanium, improving capacitor properties. In some embodiments, anodes are interspersed among...

20060011964 - Semiconductor device and method for fabricating the same: In a semiconductor device of the present invention, capacitors are formed on a part of an interlayer dielectric (26) located in a memory cell area, and another interlayer dielectric (39) is formed on a part of still another interlayer dielectric (30) located in a peripheral circuit area AreaB. Furthermore, a...

20060011965 - Non-volatile flash memory device having at least two different channel concentrations and method of fabricating the same: In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding...

20060011970 - Field-effect transistors having doped aluminum oxide dielectrics: Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum...

20060011968 - Semiconductor devices and methods of forming the same: Methods of forming a semiconductor device include forming a structure including an oxide layer, a polysilicon layer and a mask layer on a substrate. The structure is etched to form an opening therein and the substrate beneath the opening to form a trench. An insulating structure is formed in the...

20060011967 - Split gate memory structure and manufacturing method thereof: A split gate memory structure including two cells formed on a semiconductor substrate comprises a first conductive line, two dielectric spacers, two conductive spacers, two doping regions, a first dielectric layer and a second conductive line, where the two dielectric spacers, two conductive spacers and two doping regions are symmetrical...

20060011966 - Structure of a non-volatile memory cell and method of forming the same: A flash memory cell is provided. The flash memory cell includes a substrate having a source and a drain formed therein, a bit line contact formed above the drain, a control gate formed above the substrate, a spacer floating gate formed above the substrate and adjacent to the control gate,...

20060011969 - Use of dilute steam ambient for improvement of flash devices: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures...

20060011971 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device has a substrate, a floating gate, a buried gate, a control gate, and source/drain regions. The substrate has a trench formed in a first direction. The floating gate is formed on a surface of the substrate outside the trench through a first gate insulating film....

20060011972 - Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell: A nonvolatile memory cell, memory cell arrangement, and method for production