Active solid-state devices (e.g., transistors, solid-state diodes) inventions 01/06

20060017049 - Large area electron emission system for application in mask-based lithography, maskless lithography ii and microscopy: The present invention relates to a various systems for generating and directing electron flow, and related methods, manufacturing techniques and related componentry, such as can be used in lithography, microscopy and other applications. In one embodiment, the present invention involves a system that includes an electron source having a plurality...

20060017050 - Light-emitting device: To provide a light-emitting device which can emit light with high luminance and high efficiency, and is excellent in durability. The light-emitting device includes an organic compound layer containing a phenanthroline compound represented by the general formula [I] and a carbonate....

20060017051 - Apparatus having photoelectric converting element, and device manufacturing method: Disclosed is an apparatus that includes an output unit having a photoelectric converting element, for producing a signal corresponding to light incident on the photoelectric converting element, a restricting unit for restricting a light receiving region of the photoelectric converting element to one of a first region and a second...

20060017052 - Method of fabricating semiconductor device and semiconductor fabricated by the same method: A semiconductor device and method of fabricating the same are provided. The method includes: depositing a silicon layer containing amorphous silicon on a substrate; partially crystallizing the amorphous silicon by applying an annealing process to the silicon layer under an atmosphere of H2O at a predetermined temperature; forming a polycrystalline...

20060017053 - Semiconductor device and a method of manufacturing the same, integrated circuit, electro-optical device, and electronic apparatus: Aspects of the invention provide a method, in a semiconductor device, such as a thin film transistor, a technology capable of preventing or reducing the electric field concentration at the edge section of the semiconductor film to enhance the reliability. The method of manufacturing a semiconductor device according to the...

20060017054 - Liquid crystal display device and fabricating method thereof: A horizontal electric field applying type thin film transistor substrate of a LCD device having an increased aperture ratio as well as a simplified manufacturing process. The device includes a gate line having a double layered structure including a transparent first conductive layer and an opaque second conductive layer, a...

20060017056 - Field plate trench transistor: A field plate trench transistor (20-60) has a semiconductor body (3) which contains a plurality of trenches (9) which are isolated from one another by mesa regions. The trenches (9) contain gate electrodes (11) for controlling a vertical flow of current through the semiconductor body (3). At least one portion...

20060017055 - Method for manufacturing a display device with low temperature diamond coatings: A display device with multiple low temperature diamond coatings, including a substrate as a base; an anode layer residing on the diamond substrate for emitting holes; a hole drift layer that includes a doped diamond coating residing on the anode layer; an emissive layer for emitting light and residing on...

20060017057 - Device structure to improve oled reliability: An organic light emitting diode (“OLED”) device is formed with a thick light emitting polymer layer, hole transporting layer and an interlayer between the thick LEP layer and the hole transporting layer....

20060017058 - Construction of led circuit board: A LED circuit board construction having the circuit board provided with a pit carrier on a baseboard; multiple conduction circuits of different polarities being provided on the peripheral of the carrier; one end of the conduction circuit facing the carrier related to a chip conductor maintaining a fixed spacing from...

20060017059 - Packaged oled light source: A packaged organic light emitting diode (OLED) light source, comprising one or more OLED devices fabricated on a substrate and sealed with a cover, wherein at least one of the substrate and cover comprises a polymer layer and the OLED device is packaged in a sealed storage container having a...

20060017060 - Vertical conducting nitride diode using an electrically conductive substrate with a metal connection: A semiconductor device using an electrically conductive substrate that has a metal connection includes an n-type/p-type electrically conductive substrate and one buffer layer formed on the n-type/p-type electrically conductive substrate. An electrically conductive semiconductor layer is formed on the buffer layer, and the metal connection is formed between the electrically...

20060017061 - Nitride semiconductor light emitting device: A nitride semiconductor light emitting device comprising an n-side nitride semiconductor layer and a p-side nitride semiconductor layer formed on a substrate, with a light transmitting electrode 10 formed on the p-side nitride semiconductor layer, and the p-side pad electrode 14 formed for the connection with an outside circuit, and...

20060017062 - Semiconductor optical device: In a semiconductor optical device, a first conductive type semiconductor region is provided on a surface of GaAs. The first conductive type semiconductor region has a first region and a second region. An active layer is provided on the first region of the first conductive type semiconductor region. The active...

20060017063 - Metamorphic buffer on small lattice constant substrates: A semiconductor device is supported by a substrate with a smaller lattice constant. A metamorphic buffer provides a transition from the smaller lattice constant of the substrate to the larger lattice constant of the semiconductor device. In one application, the semiconductor device has a lattice constant of between approximately 6.1...

20060017064 - Nitride-based transistors having laterally grown active region and methods of fabricating same: High electron mobility transistors and/or methods of fabricating high electron mobility transistors that include a first Group III-nitride layer having vertically grown regions, laterally grown regions and a coalescence region are provided. A Group III-nitride channel layer is provided on the first Group III-nitride layer and a Group III-nitride barrier...

20060017065 - Bipolar transistor and fabrication method of the same: A bipolar transistor having a base electrode of an air bridge structure is simplified in structure and enhanced in the degree of freedom of a contact position of a base wiring line with the base electrode. The bipolar transistor has a semiconductor mesa portion having a base layer formed on...

20060017066 - Methods of base formation in a bicmos process: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow...

20060017067 - Semiconductor device and power supply unit utilizing the same: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals...

20060017068 - Integrated circuit with on-chip memory and method for fabricating the same: An integrated circuit includes an on-chip memory having bit lines, which is formed in a metal layer; and an embedded passage wiring that is arranged in the metal layer or above so as to avoid a cross-talk noise with the bit lines. The embedded passage wiring is electrically connected to...

20060017069 - Electronic component with an adhesive layer and method for the production thereof: The present invention relates to an electronic module having a layer of adhesive between metallic surfaces of components of the module. The metallic surfaces are arranged facing one another. The adhesive of the layer of adhesive includes agglomerates of nanoparticles, which form paths, surrounded by an adhesive base composition, in...

20060017070 - Semiconductor device: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region...

20060017071 - Semiconductor integrated circuit: There is provided a high-performance semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a switch block for switching connections among a plurality of signal lines by means of a plurality...

20060017072 - Cmos active pixel sensor with improved dark current and sensitivity: An active pixel sensor which provides reduced dark current, improved sensitivity, and improved modulation transfer function. An N well, surrounded by a P well is formed in a P type epitaxial substrate. A P+ region is formed extending from within the P well into the substrate leaving a gap between...

20060017073 - Semiconductor device and method of fabricating the same: A first buffer layer is formed on a substrate at a lower temperature than a single-crystal-growth-temperature, one or more of a layer composed of a nitride containing neither Ga nor In, a layer which has two or more thin films having different moduli of elasticity cyclically laminated therein, and a...

20060017074 - Raised-lines overlay semiconductor targets and method of making the same: The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present...

20060017075 - Image sensor production method and image sensor: A production method for an image sensor which is provided with a plurality of sensor portions arranged on a semiconductor substrate and each having a first photodiode constituted by a first region of a first conductivity type and a second region of a second conductivity type different from the first...

20060017076 - Electric device with phase change material and metod of manufacturing the same: The electric device (100) has a body (102) having a resistor (107) comprising a phase change material being changeable between a first phase and a second phase. The resistor (107) has a first electrical resistance when the phase change material is in the first phase, and a second electrical resistance,...

20060017077 - Semiconductor device having switch circuit to supply voltage: A memory cell array has memory cells arranged in a matrix form. The memory cell includes a floating gate and a control gate. Word lines are each coupled to the control gates of the memory cells which are arranged on a corresponding one of the rows in the memory cell...

20060017078 - Accufet with schottky source contact: An accumulation mode FET (ACCUFET) which includes an insulated gate, an adjacently disposed insulated source field electrode, and a source contact that makes Schottky contact with the base region of the ACCUFET....

20060017079 - N-type transistor with antimony-doped ultra shallow source and drain: We disclose a process for forming ultra shallow n+p junctions. The junction is formed by, for example, implanting 3E14 ions/cm2 of antimony ions at 5 keV into silicon. The silicon is pre-amorphized by a previous ion-implantation. The pre-amorphizing implant species may be germanium or arsenic. Germanium may be implanted at...

20060017080 - Field-effect transistor: The field-effect transistor includes: a ferromagnetic layer, having a film thickness of 50 nm or less, which is made of a Ba—Mn oxide showing ferromagnetism at 0° C. or higher; a dielectric layer made of a dielectric material or a ferroelectric material, and the ferromagnetic layer and the dielectric layer...

20060017082 - Magnetic random access memory having magnetoresistive element: A magnetic random access memory includes a magnetoresistive element which has a recording layer, a fixed layer, and an intermediate nonmagnetic layer, the recording layer comprising a first ferromagnetic layer formed on the intermediate nonmagnetic layer, a first nonmagnetic layer formed on the first ferromagnetic layer, a second ferromagnetic layer...

20060017081 - Magnetic tunnel junction element structures and methods for fabricating the same: Magnetic tunnel junction (“MTJ”) element structures and methods for fabricating MTJ element structures are provided. An MTJ element structure may comprise a crystalline pinned layer, an amorphous fixed layer, and a coupling layer disposed between the crystalline pinned layer and the amorphous fixed layer. The amorphous fixed layer is antiferromagnetically...

20060017083 - Multi-state magnetoresistance random access cell with improved memory storage density: A multi-state magnetoresistive random access memory device having a pinned ferromagnetic region with a magnetic moment vector fixed in a preferred direction in the absence of an applied magnetic field, a non-ferromagnetic spacer layer positioned on the pinned ferromagnetic region, and a free ferromagnetic region with an anisotropy designed to...

20060017084 - Integrated semiconductor metal-insulator-semiconductor capacitor: An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and...

20060017085 - Nand flash memory with densely packed memory gates and fabrication process: NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source...

20060017086 - Semiconductor device and method for manufacturing the same: There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film....

20060017087 - Semiconductor device and method of manufacturing the same utilizing permittivity of an insulating layer to provide a desired cross conductive layer capacitance property: A supplemental capacitor is formed using the large capacitance between the wirings (M11 and M12) and that between the through-holes (B11 and B12) because of downsizing of the process technique. The inter-wiring capacitor and inter-through-hole capacitor can be arranged at any optional position within the semiconductor device. The supplemental capacitor...

20060017088 - Dram layout with vertical fets and method of formation: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a...

20060017089 - Method and apparatus for providing capacitor feedthrough: A capacitor feedthrough assembly with a cavity, comprising a capacitor stack, including one or more substantially flat anode layers and one or more substantially flat cathode layers in a case with a cover, the case having a first opening sized for passage of the capacitor stack and a second opening...

20060017090 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a cylinder-shaped capacitor. The capacitor includes a second insulating layer formed with a recessed portion formed on a semiconductor substrate, a cylinder shaped lower electrode formed in the recessed portion, a capacitance layer formed on the lower electrode, and an upper electrode formed on the capacitance...

20060017091 - Method and apparatus for nonvolatile memory: Method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for nonvolatile memory device. The device has a strain source, an injection filter, a tunneling gate, a ballistic gate, a charge storage region, a source, and a drain with a channel defined between the source and drain. The...

20060017092 - Method for simultaneously fabricating ono-type memory cell, and gate dielectrics for associated high voltage write transistors and gate dielectrics for low voltage logic transistors by using issg: Conventional fabrication of top oxide in an ONO-type memory cell stack usually produces Bird's Beak. Certain materials in the stack such as silicon nitrides are relatively difficult to oxidize. As a result oxidation does not proceed uniformly along the multi-layered height of the ONO-type stack. The present disclosure shows how...

20060017095 - Carburized silicon gate insulators for integrated circuits: Silicon carbide films are grown by carburization of silicon to form insulative films. In one embodiment, the film is used to provide a gate insulator for a field effect transistor. The film is grown in a microwave-plasma-enhanced chemical vapor deposition (MPECVD) system. A silicon substrate is first etched in dilute...

20060017094 - Non-volatile memory devices with improved insulation layers and methods of manufacturing such devices: Non-volatile memory devices are provided which include a plurality of gate structures on a substrate. In these devices, a first insulation interlayer is on both the substrate and on the plurality of gate structures, and includes an opening therein. A common source line is in the opening in the first...

20060017093 - Semiconductor devices with overlapping gate electrodes and methods of fabricating the same: A semiconductor device, such as a flash memory device, includes an isolation region provided in a trench in a substrate and having a recess therein. The device also includes a tunnel oxide layer pattern on the substrate adjacent the isolation region, and a first gate electrode provided on the tunnel...

20060017096 - Semiconductor device: A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor...

20060017097 - Method of manufacturing a trench-gate semiconductor device: A method of making a trench MOSFET includes forming a nitride liner 50 on the sidewalls 28 of a trench and a plug of doped polysilicon 26 at the bottom of a trench. The plug of polysilicon 26 may then be oxidised to form a thick oxide plug 30 at...

20060017099 - Mos transistor having a recessed gate electrode and fabrication method thereof: A metal oxide semiconductor (MOS) transistor having a recessed gate electrode and a fabrication method thereof are provided. The MOS transistor includes a semiconductor substrate and an isolation layer formed in a predetermined region of the semiconductor substrate to define an active region. A channel trench region is disposed within...

20060017098 - Semiconductor device with a high-k gate dielectric and a metal gate electrode: A semiconductor device is described that comprises a gate dielectric and a metal gate electrode that comprises an aluminide....

20060017100 - Dynamic deep depletion field effect transistor: A vertical conduction trench FET has a plurality of trenches containing conductive polysilicon gates. The mesas between the trenches have a source diffusion region connected to a common source electrode. The trenches are spaced so that the depletion regions induced by the trench gate will overlap to pinch off conduction...

20060017101 - Semiconductor integrated circuit and manufacturing method of the same: There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring...

20060017102 - Ldmos device and method of fabrication: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface...

20060017103 - Method for making reduced size dmos transistor and resulting dmos transistor: A method is provided for making a laterally extended drain DMOS transistor. According to the method, a gate having two substantially parallel lateral faces is produced on a substrate, and a drain spacer and a source spacer made of an insulating material are produced on the lateral faces of the...

20060017104 - Semiconductor device having a channel pattern and method of manufacturing the same: A semiconductor device may include a tubular channel pattern vertically extending from a semiconductor substrate. A gate insulation layer may be provided on faces exposed through the channel pattern. A gate electrode may be provided on the gate insulation layer. The gate electrode may fill the channel pattern. A conductive...

20060017105 - Semiconductor device and method of fabricating the same: A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide...

20060017106 - Tft, electronic device having the tft, and flat display device having the tft: The invention provides an improved thin film transistor (TFT) that can be formed at room temperature and has an improved contact resistance between an active layer and source and drain electrodes, and further provides a flat display device using such a TFT. The TFT includes an active layer including at...

20060017107 - Metal gate engineering for surface p-channel devices: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in...

20060017108 - Nano and mems power sources and methods thereof: A power source and methods thereof includes a structure comprising one or more p type layers, one or more n type layers, and one or more intrinsic layers and at least one source of radiation is disposed on at least a portion of the structure. Each of the p type...

20060017109 - High voltage esd-protection structure: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the...

20060017110 - Semiconductor device with low resistance contacts: An N channel transistor and a P channel transistor have their source/drains contacts with different suicides to provide for low resistance contacts. The silicides are chosen to provide good matching of the work functions. The P-type source/drain contacts of the P channel transistors have a silicide that is close to...

20060017111 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, an interlayer insulating film formed so that the gate electrode is buried therein, a contact hole formed in the interlayer insulating film so as to...

20060017113 - High transconductance and drive current high voltage mos transistors: A composite MOS transistor (100) includes a first MOS sub-transistor (105) having a first gate dielectric thickness (106), and a second MOS sub-transistor (155) in series connection with the first MOS sub-transistor having a second gate dielectric thickness (107). The second gate dielectric thickness (107) is substantially thicker than the...

20060017112 - Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof: A process and apparatus for a semiconductor device is provided. A device comprises a first transistor having a first charge carrier type. The first transistor comprises a high-k gate dielectric and a first doped electrode. The first charge carrier type comprises one of p-type and n-type and the first doped...

20060017114 - Method for fabricating integrated circuits having both high voltage and low voltage devices: A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of...

20060017115 - One-transistor random access memory technology compatible with metal gate process: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM...

20060017116 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device includes forming a gate insulating layer, a gate and a protective layer on a semiconductor substrate, forming a spacer on lateral sides of the protective layer and the gate, forming one or more junction regions in the semiconductor substrate at sides of the...

20060017117 - Semiconductor device and method for fabricating the same: A semiconductor device includes a resistor element covered by a silicon oxide film. In the semiconductor device, with respective gate electrodes of MIS transistors and impurity doped layers, i.e., non-silicide regions exposed, thermal treatment for activating an impurity and silicidization are performed. Thus, auto-doping of an impurity is suppressed, so...

20060017118 - Semiconductor device having spacer pattern and method of forming the same: The present invention provides a semiconductor device having a spacer pattern and methods of forming the same that includes a lower interconnection pattern on a semiconductor substrate. A lower interconnection spacer covers sidewalls of the lower interconnection pattern. Spacer patterns cover the lower interconnection spacer of the lower interconnection pattern...

20060017119 - Multi-gate transistor and method of fabricating multi-gate transistor: A multi-gate transistor and a method of fabricating the multi-gate transistor may involve forming an active pattern with a multi-channel region, in which a channel region is provided on at least two surfaces of the active pattern. An interconnect may be connected to an interconnect region of the active pattern...

20060017120 - Semiconductor-ferroelectric storage device and its manufacturing method: The MFIS transistors heretofore have a problem that after data writing, the data disappear in terms of memory transistor operation in about one day at most. This is mainly because the buffer layer and the ferroelectric have a high leakage current and, hence, charge is accumulated around the interface between...

20060017121 - Nonvolatile semiconductor memory device and method for fabricating the same: A nonvolatile semiconductor memory device includes: a gate dielectric made of a multilayer dielectric that is formed on a substrate and discretely accumulates charges; a gate electrode formed on the gate dielectric; a pair of diffusion regions formed in the surface of the substrate with the gate electrode interposed therebetween...

20060017122 - Novel metal-gate electrode for cmos transistor applications: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying...

20060017124 - Bistable magnetic device using soft magnetic intermediary material: Roughly described, a magnetic structure includes an electrically conductive path for carrying current flow, a soft magnetic material with high permeability value in magnetic communication with the current flow so that it can be magnetized in either of two directions, and a magnetic device such as a magnetic random access...

20060017123 - Field imager: A detection apparatus for detecting the presence of a sample, the detection apparatus comprising a chamber, ports for introducing a sample within the chamber, an actuation unit for establishing a controllable electromagnetic field in the chamber; and a sensing unit for sensing changes in the electromagnetic field due to the...

20060017125 - Vibration type mems switch and fabricating method thereof: A vibration type MEMS switch and a method of fabricating the vibration type MEMS switch. The vibration type MEMS switch includes a vibrating body supplied with an alternating current voltage of a predetermined frequency to vibrate in a predetermined direction; and a stationary contact point spaced apart from the vibrating...

20060017126 - Thermally written magnetic memory device: A thermally written magnetic memory device is disclosed. The thermally written magnetic memory device includes a plurality of thermally written magnetic tunnel junction devices. Each thermally written magnetic tunnel junction device includes a super-paramagnetically stable data layer. The data layer includes a high coercivity at a read temperature such that...

20060017127 - Optical package for a semiconductor sensor: An optical package for integrated circuit chips including optical microsensors and its manufacturing method, an encapsulation resin thickness smaller than the thickness provided straight above connecting wires being provided at least straight above the microsensors between the upper surface of the chip and a substrate supporting it....

20060017128 - Solid-state imaging apparatus and manufacturing method thereof: A structure member is used wherein a circuit board is connected to a solid-state image pickup element and placed between a portion of the structure member to which the solid-state image pickup element is attached, and another portion to which a light-transmitting member is attached, and the circuit board is...

20060017129 - Avalanche photodiode: An avalanche photodiode has improved low-noise characteristics, high-speed response characteristics, and sensitivity. The avalanche photodiode includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, a semiconductor multiplication layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a semiconductor...

20060017130 - Fast recovery diode with a single large area p/n junction: A fast recovery diode has a single large area P/N junction surrounded by a termination region. The anode contact in contact with the central active area extends over the inner periphery of an oxide termination ring and an EQR metal ring extends over the outer periphery of the oxide termination...

20060017131 - Process for manufacturing an soi wafer by annealing and oxidation of buried channels: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures....

20060017132 - Method for producing a dielectric and semiconductor structure: The present invention relates to a method for producing a dielectric on a semiconductor body having the following steps that are to be performed successively: provision of a semiconductor body, application of a dielectric layer on at least parts of a first surface of the semiconductor body in such a...

20060017133 - Electronic part-containing elements, electronic devices and production methods: An electronic part-containing element used by being incorporated in an electronic device, in which the electronic part-containing element comprises an insulating support member which does not take part in the constitution of the electronic device but is removed in the process of producing the electronic device, and a circuit module...

20060017134 - Input protection circuit preventing electrostatic discharge damage of semiconductor integrated circuit: An input protection circuit comprises a semiconductor chip, an internal circuit disposed on the semiconductor chip, a first input/output terminal which is disposed on the semiconductor chip and connected to the internal circuit, a second input/output terminal which is disposed on the semiconductor chip, connected to the internal circuit and...

20060017136 - Capacitor of analog semiconductor device having multi-layer dielectric film and method of manufacturing the same: In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film...

20060017135 - Layout method of decoupling capacitors: A layout method of decoupling capacitors while ensuring the decoupling capacitance necessary for each grid area. The method includes calculating the total power consumption of logic cells, arranging the decoupling capacitance throughout the subject area in correspondence with the total power consumption, dividing the subject area into a plurality of...

20060017137 - Semiconductor device and its manufacturing method: A semiconductor device and its manufacturing method are achieved which are capable of mixing a plurality of different crystal orientations in SOI substrate surfaces and controlling increase of leakage current into substrates and increase in power consumption in each area. An SOI substrate is fabricated by bonding two semiconductor wafers...

20060017138 - Strain enhanced ultra shallow junction formation: Provided is a method of manufacturing a microelectronic device. In one example where the device includes a semiconductor substrate with a gate feature and a shallow junction, the method includes introducing dopants to the substrate to form a source region and a drain region. A strained layer may be formed...

20060017139 - Thin film semiconductor device and method of manufacturing the same, electro-optical device, and electronic apparatus: A thin film semiconductor device includes a substrate and a semiconductor film formed on the substrate. The thin film semiconductor device further includes a protective circuit element having a PIN diode having the semiconductor film, and a floating electrode disposed opposite to an I layer of the PIN diode with...

20060017140 - Flashless lead frame with horizontal singulation: A lead frame is configured for use with a singulation apparatus that eliminates flash. A die pad is attached to sides of the frame by tie bars and peripheral portions. The peripheral portions have cutout sections defining openings that are bridged by lead frame segments. The apparatus applies a downward...

20060017141 - Power semiconductor package: A semiconductor package including a relatively thick lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die coupled thereto, bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum, and a resin body encapsulating...

20060017142 - Bonding configurations for lead-frame-based and substrate-based semiconductor packages and method of fabrication thereof: In a bonding configuration for a semiconductor device package, the bonding angles of the bonding wires are maintained within acceptable limits, without causing an increase in the chip die size, and without necessitating the use of the corner rule. In this manner, the occurrence of shorting between adjacent bonding wires...

20060017144 - Semiconductor device: The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above...

20060017143 - Semiconductor device and its manufacturing method: There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing...

20060017145 - Semiconductor package with heat sink: A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to...

20060017146 - Ic with stably mounted chip: An IC with stably mounted chip includes a chip, a leadframe, a bridge, and an encapsulating compound. The bridge is a flat arch made of a sheet material and includes a horizontal fixing section and a supporting section downward extended from each end of the fixing section. The chip is...

20060017147 - Method and apparatus for using capacitively coupled communication within stacks of laminated chips: One embodiment of the present invention provides a technique for assembling semiconductor chips. First, multiple semiconductor chips are permanently laminated together into a plurality of laminated chip assemblies, wherein the semiconductor chips within the laminated chip assembly communicate with each other through electrically conductive connections. Next, laminated chip assemblies are...

20060017148 - Semiconductor package and method for its manufacture: A method of manufacturing a semiconductor package having a double encapsulant structure. The method comprises preparing a group substrate. The group substrate includes a plurality of semiconductor chips arranged on the top surface, which chips typically are stacked. The semiconductor chips are electrically connected with the group substrate by bonding...

20060017149 - Substrate-based bga package, in particular fbga package: A ball grid array package includes a substrate. A number of solder balls overlie the solder ball surface of the substrate. The solder balls are arranged within a ballout area. A chip is attached to the chip surface of the substrate by an adhesive layer. Contact pads of the chip...

20060017150 - Multi-chip module and single-chip module for chips and proximity connectors: A single-chip module is described. The module includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the first semiconductor die. A cable coupled...

20060017151 - Bga package board and method for manufacturing the same: Disclosed herein is a Ball Grid Array (BGA) package board. The BGA package board includes a first external layer on which a pattern comprising a circuit pattern and a wire bonding pad pattern is formed, a second external layer on which a pattern comprising a circuit pattern and a solder...

20060017152 - Heterogeneous organic laminate stack ups for high frequency applications: Organic laminate stack ups are disclosed for a variety of applications, including high frequency RF applications. One or more inner core layers may be disposed between outer layers along with bondply or prepreg layers as needed. Discrete devices, including surface mount components and flip chips, may be embedded within the...

20060017153 - Interconnections of semiconductor device and method of forming the same: An interconnection structure includes a substrate containing a first lower interconnection and a pair of second interconnections separated from each other by a predetermined distance, and a metallic compound fuse pattern connecting the second lower interconnections, being positioned over the second lower interconnections. The fuse pattern is formed by using...

20060017154 - Semiconductor device and method for manufacturing same: A method to provide an improved production yield of electronic devices. A thin film device 41 is manufactured by the following method. Semiconductor elements 11 are formed on the substrate 10. Then, a protective film is adhered onto the upper portions of the semiconductor elements 11 using an adhesive agent....

20060017155 - Flip chip package capable of measuring bond line thickness of thermal interface material: A flip chip package includes a substrate, a flip chip, a thermal interface material and a heat sink. The flip chip is mounted on the substrate. The thermal interface material is applied on the back surface of the flip chip. The back surface of the flip chip includes a region...

20060017156 - Method for mounting a chip on a base and arrangement produced by this method: An electronic component includes a base and a chip attached to the base by a plurality of adhesive pads that are spaced apart from one another and are arranged in an intermediate space between the chip and the base. The chip is electrically connected to interconnects of the base. The...

20060017157 - High frequency semiconductor apparatus, transmitting apparatus and receiving apparatus: A high frequency semiconductor apparatus is provided which prevents characteristics of a high frequency semiconductor element from being deteriorated so that the high frequency semiconductor element can be made to operate stably. The high frequency semiconductor apparatus is so configured that heat generated by a high frequency semiconductor element is...

20060017158 - Power supply wiring structure: Provided is a power supply wiring structure which comprises a first and a second power supply wirings, which are disposed on different planes to cross each other two-dimensionally. The first and second power supply wirings are interlayer-connected by a first via at a crossing area where those power supply wirings...

20060017159 - Semiconductor device and method of manufacturing a semiconductor device: According to an aspect of the present invention, there is provided a semiconductor device including a lead frame, a semiconductor chip, a back surface opposed to a main surface of the semiconductor chip disposed on the lead frame, a first electrode formed on the main surface of the semiconductor chip,...

20060017161 - Semiconductor package having protective layer for re-routing lines and method of manufacturing the same: An apparatus and method for manufacturing a semiconductor package are disclosed. The apparatus may include at least a semiconductor chip having input/output (I/O) pads arranged on a surface thereof, a first dielectric layer formed on the surface of the semiconductor chip which may expose the I/O pads, a seed metal...

20060017160 - Structure and formation method of conductive bumps: A method and structure for a conductive bump are provided herein. A conductive surface is provided on a wafer. A conductive barrier layer and a conductive wetting layer on a part of the conductive surface have a bottom and a side wall and further reach up a top surface. The...

20060017163 - Device having contact pad with a conductive layer and a conductive passivation layer: A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material which resists formation of resistive oxides. In particular, a tank is divided into three compartments, each holding a different solution: a lower compartment and two upper compartments divided...

20060017162 - Semiconductor device and manufacturing method of the same: A semiconductor device is disclosed, which comprises a semiconductor substrate, a semiconductor element formed on the semiconductor substrate, and multi-level wiring structure including first wirings at a plurality of levels, in which the first wirings at at least one of the levels are provided at different heights in a cross-sectional...

20060017164 - Semiconductor device: A semiconductor device, wherein an increase of a capacity between wiring layers is suppressed, reliability of wiring and property of withstand voltage of a diffusion prevention insulation film can be improved and the wiring resistance can be maintained low, is provided by comprising an interlayer insulation film formed on a...

20060017165 - Semiconductor device and manufacturing method thereof: A method of manufacturing a semiconductor device comprises the steps as follow. After forming an insulating layer with opening therein over a substrate, a polysilicon layer that partially fills the opening is formed over the substrate and then a refractory metal silicide layer that completely fills the opening is formed...

20060017166 - Robust fluorine containing silica glass (fsg) film with less free fluorine: A semiconductor device and method of manufacture thereof having a less free fluorine (F) fluorine containing Silica Glass (FSG) dielectric film formed thereon. The FSG dielectric film includes about 25% or less free F, has a porosity of about 5% or less and has a dielectric constant of about 3.8...

20060017167 - Semiconductor device: A semiconductor device having a structure which can be manufactured with a higher yield includes a local interconnection layer 14 (a first interconnection layer) on a semiconductor substrate 10 and a global interconnection layer 18 (a second interconnection layer) on the local interconnection layer 14. The local interconnection layer 14...

20060017168 - Semiconductor devices to reduce stress on a metal interconnect: Semiconductor devices to reduce stress on a metal interconnect are disclosed. A disclosed semiconductor device comprises: a semiconductor substrate; an uppermost metal interconnect formed on the semiconductor substrate; an oxide layer formed on the substrate and the uppermost metal interconnect; an aluminum layer formed on the oxide layer; and a...

20060017169 - Electroplated interconnection structures on integrated circuit chips: A process is described for the fabrication of submicton interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features...

20060017170 - Cosb3-based thermoelectric device fabrication method: A method of fabricating a CoSb3-based thermoelectric device is disclosed. The method includes providing a high-temperature electrode, providing a buffer layer on the high-temperature electrode, forming composite n-type and p-type layers, attaching the buffer layer to the composite n-type and p-type layers, providing a low-temperature electrode on the composite n-type...

20060017171 - Formation method and structure of conductive bumps: A formation method and structure of conductive bump are provided. A conductive bump is formed on a wafer through an under bump metallurgy layer. A nickel-based wetting layer in the under bump metallurgy layer is applied on the conductive bump to prevent stannum in the conductive bump from diffusing downwards....

20060017172 - Die and die-package interface metallization and bump design and arrangement: A die metallization and bump design/arrangement, and a die-package interface metallization and bump design/arrangement are described herein....

20060017173 - Flip-chip semiconductor package with lead frame and method for fabricating the same: A flip-chip semiconductor package with a lead frame and a method for fabricating the same are provided. The lead frame has a plurality of leads, each lead having an upper surface, a lower surface, and an inner end directed toward the center of the lead frame. A recessed portion is...

20060017174 - Semiconductor device: The invention relates to a semiconductor device with a semiconductor chip, on which a terminal contact formed in one piece, a patterned metallization layer, contacting the terminal contact, and a connecting layer are successively arranged, the patterned metallization layer and the patterned connecting layer forming an electrically conducting contact layer....

20060017176 - Bump ball device and placing method thereof: The present invention provides a bump ball device and a placing method thereof. The bump ball device having a die on which I/O terminal of a plurality of circuit elements are arranged, includes: a plurality of bonding pads which are electrically connected to the I/O terminals of the circuit elements;...

20060017175 - Collars, support structures, and forms for protuding conductive structures: Collars, support structures, or forms for protruding conductive structures include apertures or receptacles through which the conductive structure may extend. The aperture or receptacle may be configured to contact a surface of the conductive structure, and even to define a shape of at least a portion of the conductive structure....

20060017177 - Microelectronic component assemblies with recessed wire bonds and methods of making same: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, a substrate, and at least one bond wire. The substrate has a reduced-thickness base adjacent terminals of the microelectronic component and a...

20060017178 - Wiring structure for a pad section in a semiconductor device: The wiring structure of a pad section in a semiconductor device includes a row of pads and a plurality of first bias wirings provided at either side of the row of pads on a same plane. The first bias wirings carry electrical signals to the pads. A plurality of second...

20060017179 - Insulated structure of a chip array component and fabrication method of the same: An insulated structure of a chip array component and fabrication method of the same, the element is fabricated by enclosing its main body with a dense layer of high surface insulation resistance material, and then exposing the portions of the main body where terminal electrodes are to be formed by...

20060017180 - Alignment of mtj stack to conductive lines in the absence of topography: A scheme for aligning opaque material layers of a semiconductor device. Alignment marks are formed in a via level of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may have about the same length as vias formed in the via layer. The alignment marks...

20060017181 - Semiconductor memory device and semiconductor device group: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to...

20060011902 - Phase change memory device and method for forming the same: A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical...

20060011903 - Nitride based semiconductor light-emitting device: The present invention provides a semiconductor device having a semiconductor multi-layer structure which includes at least an active layer having at least a quantum well, and the active layer further including at least a luminescent layer of InxAlyGa1-x-yN (0<x<1, 0≦y≦0.2), wherein a threshold mode gain of each of the at...

20060011904 - Layered composite film incorporating quantum dots as programmable dopants: Quantum dots are positioned within a layered composite film to produce a plurality of real-time programmable dopants within the film. Charge carriers are driven into the quantum dots by energy in connected control paths. The charge carriers are trapped in the quantum dots through quantum confinement, such that the charge...

20060011905 - Semiconductor device comprising a superlattice dielectric interface layer: A semiconductor device may include a semiconductor substrate and at least one active device adjacent the semiconductor substrate. The at least one active device may include an electrode layer, a high-K dielectric layer underlying the electrode layer and in contact therewith, and a superlattice underlying the high-K dielectric layer opposite...

20060011906 - Ion implantation for suppression of defects in annealed sige layers: A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed. The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form...

20060011907 - Compounds containing 3,4-methylenedioxythiophene units: m

20060011908 - Light emitting element: The present invention relates to a thin film light emitting element which has low drive voltage. In particular, the present invention relates to a thin film light emitting element which has low drive voltage and in which color purity and luminous efficiency are not deteriorated. A structure of a light...

20060011909 - Organic thin film transistor with polymeric interface: Provided is an organic thin film transistor comprising a polymeric layer interposed between a gate dielectric and an organic semiconductor layer. Various homopolymers, copolymers, and functional copolymers are taught for use in the polymeric layer. An integrated circuit comprising a multiplicity of thin film transistors and methods of making a...

20060011910 - Pcram device with switching glass layer: A memory device, such as a PCRAM, including a chalcogenide glass backbone material with germanium telluride glass and methods of forming such a memory device....

20060011911 - Detection of molecular probes fixed to an active zone of a sensor: The present invention relates to a method for detecting at least one parameter representative of molecular probes fixed to zones of a sensor....

20060011913 - Display device mounted with read function and electric appliance: According to the present invention, a material having a light-shielding property is used for a bank layer surrounding the edge of a light-emitting element. Accordingly, light which is not reflected by an object to be read out can be prevented from entering an image pick-up element, and information on the...

20060011912 - Method of forming a metal pattern and a method of fabricating tft array panel by using the same: With a metal pattern formation process and a method of manufacturing a thin film transistor array panel using the metal pattern formation process, an organometallic layer is formed by coating an organometallic complex containing metal. The organometallic layer is exposed to light through a photo mask, and developed to form...

20060011914 - Novel conductive elements for thin film transistors used in a flat panel display: A novel design for an electrode for a thin film transistor. The novel design allows for formation of a normal conductive channel between a source electrode and a drain electrode even after a heat treatment process, and a flat panel display including the thin film transistor. The thin film transistor...

20060011915 - Nitride semiconductor device: A nitride semiconductor device according to one embodiment of the present invention comprises: a non-doped first aluminum gallium nitride (AlxGa1-xN (0≦x≦1)) layer which is formed as a channel layer; a non-doped or n type second aluminum gallium nitride (AlyGa1-yN (0≦x≦1,x<y)) layer which is formed on the first aluminum gallium nitride...

20060011916 - Substrate for epitaxial growth, process for producing the same, and multi-layered film structure: A substrate for epitaxial growth includes a silicon-containing substrate, a silicon-germanium film, and a network-shaped structure. The silicon-germanium film is formed lamellarly on the silicon-containing substrate. The network-shaped structure is disposed adjacent to an interface between the silicon-containing substrate and the silicon-germanium film, and is composed of a 90-degree-dislocation dislocation...

20060011918 - Flat panel display device and method of manufacturing the same: A flat panel display includes a pixel electrode having an opening portion formed on an insulating substrate, a semiconductor layer formed over a surface of the insulating substrate, spaced apart from the pixel electrode, having source and drain regions formed to both end portions thereof, a first insulating layer formed...

20060011917 - Thin film transistor, flat panel display device therewith, and method of manufacturing the thin film transistor: A thin film transistor that does not deform or exfoliate due to thermal or mechanical stress, a flat panel display having the same, and a method manufacturing the same, the thin film transistor including a substrate, a patterned buffer layer disposed on the substrate, a patterned active layer disposed on...

20060011919 - Vertical gate device for an image sensor and method of forming the same: A CMOS pixel cell having a charge transfer transistor adjacent the photo-conversion device. The transistor has a channel region surrounded by a gate and an upper source/drain region over the channel region....

20060011921 - Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films: A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor...

20060011920 - Thin film transistor array panel and manufacturing method thereof: Gate lines and a gate shorting bar connected to the gate lines, which include lower and upper films, are formed on a substrate. A gate insulating layer, semiconductors, and ohmic contacts are formed in sequence. Data lines and a data shorting bar connected to the data lines, which include lower...

20060011922 - Light-emitting device comprising an eu(ii)-activated phosphor: The invention concerns a light emitting device comprising a light emitting structure capable of emitting primary light of a wavelength less then 480 nm and a luminescent screen comprising a phosphor of general formula (Sr1-a-bCabBacMgdZne)SixNyOz:Eua, wherein 0.002≦a≦0.2, 0.0≦b≦0.25, 0.0≦c≦0.25, 0.0≦d≦0.25, 0.0≦e≦0.25, 1.5≦x≦2.5, 1.5≦y≦2.5 and 1.5≦z≦2.5. The invention also concerns a...

20060011923 - Electromagnetic radiation generating semiconductor chip and method for making same: An electromagnetic radiation generating semiconductor chip is disclosed. A semiconductor layer sequence suitable for generating electromagnetic radiation is grown on a first main face of a radioparent, electrically conductive growth substrate, for example, a SiC growth substrate. Provided on a second main face of said growth substrate that faces away...

20060011924 - Monolithic vertical junction field effect transistor and schottky barrier diode fabricated from silicon carbide and method for fabricating the same: A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The...

20060011925 - Radiation-emitting semiconductor element and method for producing the same: The invention also describes a production method for a semiconductor component pursuant to the invention. An interlayer (9) is first applied to a substrate (8), and a plurality of GaN layers (1) that constitute the semiconductor body of the component are then applied to this. The substrate (8) and the...

20060011926 - Light-emitting diode device with resecurable connection: An LED device includes a scrambler portion, a substrate portion having a light-emitting diode (“LED”) and a substrate layer attached to the LED, an electrical connection between the LED and the substrate layer, and a resecurable connection between the scrambler portion and the substrate layer....

20060011927 - Organic light emitting devices and electroluminescent display panel applying the same: Organic light emitting devices include an anode, a cathode and a plurality of organic light emitting units. The adjacent organic light emitting units are separated by a charge transfer layer formed of various fullerenes in combination. The charge transfer layer may be a relatively homogenous layer that is a mixture...

20060011928 - Surface-mountable light-emitting diode and/or photodiode and method for the production thereof: A surface-mountable miniature luminescent diode with a chip package which has a leadframe (16) and a semiconductor chip (22) which is arranged on the leadframe (16) and is in electrical contact with it and which contains an active, radiation-emitting region. The leadframe (16) is formed by a flexible multi-layered sheet...

20060011929 - Rotating display device: A device for displaying an image is provided. The device includes a hub that is configured to rotate about a first axis and a motor configured to rotate the hub about the first axis. A plurality of light detecting devices attached to the hub and at least one lens configured...

20060011930 - Semiconductor photodetecting device and method of manufacturing the same: An object of the present invention is to provide a semiconductor photodetecting device that enables a solid-state image sensor to meet requirement of higher quality imaging and more reduction in cost, and the semiconductor photodetecting device includes a semiconductor substrate, and an epitaxial layer that is formed on the semiconductor...

20060011931 - Ic package with an integrated power source: A radioactive power source resident in an IC package is provided. The power source is a stand-alone device, fabricated separately from the IC or other device that is eventually attached to the package. The power source may be attached to the packaging substrate or to another portion of the package...

20060011932 - Complementary metal oxide semiconductor image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same is disclosed, to enhance the efficiency in condensing the light by forming a multi-layered micro lens with various materials having different refractive indexes, in which the CMOS image sensor includes a plurality of photosensitive devices on a semiconductor substrate;...

20060011933 - Optoelectronic device manufacturing: Provides optoelectronic devices and methods for manufacturing an optoelectronic devices. Optoelectronic devices including a capping layer for improving out-coupling and optical fine-tuning of emission characteristics. The present invention is particularly advantageous for top-emitting devices and for organic light emitting devices. An example optoelectronic device includes an optoelectronic member for emitting...

20060011935 - Light extraction from a semiconductor light emitting device via chip shaping: A method for designing semiconductor light emitting devices is disclosed wherein the side surfaces (surfaces not parallel to the epitaxial layers) are formed at preferred angles relative to vertical (normal to the plane of the light-emitting active layer) to improve light extraction efficiency and increase total light output efficiency. Device...

20060011934 - Semiconductor light-emitting element and manufacturing method thereof: An improvement in electrode reliability is realized by preventing over-etching on a peripheral lower portion of an electrode while maintaining the flow of steps of roughening a surface after forming the electrode on a semiconductor substrate. After a P-side electrode 4 is formed on a main surface 3a of a...

20060011936 - Fluorescent substance containing nitrogen, method for manufacturing the same, and light-emitting device: Disclosed is a method for manufacturing a nitrogen-containing fluorescent substance comprising accommodating an oxide fluorescent substance containing two or more elements in a receptacle made of a material containing carbon, and sintering the oxide fluorescent substance in a mixed gas atmosphere containing nitrogen gas....

20060011937 - Strain-controlled iii-nitride light emitting device: In a III-nitride light emitting device, a ternary or quaternary light emitting layer is configured to control the degree of phase separation. In some embodiments, the difference between the InN composition at any point in the light emitting layer and the average InN composition in the light emitting layer is...

20060011938 - Super lattice tunnel junctions: Super lattice structures in conjunction with a tunnel junction to provide an improved contact for multiple components. The tunnel junctions can include a first semiconductor material having a resistance parameter for conducting a current and a second semiconductor material having a resistance parameter that is more restrictive to conduction of...

20060011939 - Two-dimensional silicon controlled rectifier: A two-dimensional silicon controlled rectifier (2DSCR) having the anode and cathode forming a checkerboard pattern. Such a pattern maximizes the anode to cathode contact length (the active area) within a given SCR area, i.e., effectively increasing the SCR width. Increasing the physical SCR area, increases the current handling capabilities of...

20060011940 - Thyristor-type memory device: A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to...

20060011941 - Substrate for growing electro-optical single crystal thin film and method of manufacturing the same: A substrate 1 for growing an electro-optical single crystal thin film in which two or more layers of buffer layers 3, 4, and 5 for buffering lattice mismatch between Si and BTO are formed on an Si (001) substrate 2 is provided as a substrate for growing an electro-optical single...

20060011942 - 2-terminal semiconductor device using abrupt metal-insulator transition semiconductor material: Provided is a 2-terminal semiconductor device that uses an abrupt MIT semiconductor material layer. The 2-terminal semiconductor device includes a first electrode layer, an abrupt MIT semiconductor organic or inorganic material layer having an energy gap less than 2eV and holes in a hole level disposed on the first electrode...

20060011943 - Bipolar transistor having base over buried insulating and polycrystalline regions, and method of fabrication: A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface layer; a base contact (130 and 131) extending through a substantial portion (141) of...

20060011944 - Semiconductor device: A semiconductor device provided with an emitter layer having a narrowed base contact portion. The semiconductor device includes a collector layer arranged on a semiconductor substrate. A conductive layer is arranged on the collector layer. A silicon film is arranged on the conductive layer. An emitter electrode is arranged on...

20060011945 - Photocatalyst and process for purifying gas effluent by photocatalytic oxidation: The photocatalyst based on a composite WO3—SiC/TiO2 semiconductor and subjected to radiation whose wavelength is at least partly less than 400 nm gives photocatalytic oxidation of volatile organic compounds and leads to their total mineralisation into CO2 and H2O. The process for the photocatalytic purification of industrial, agricultural or domestic...

20060011946 - Nitride semiconductor laser element: A nitride semiconductor laser element capable of controlling the lateral confinement of light with a good reproducibility, the nitride semiconductor element comprising an n-type cladding layer (3), an MQW light emitting layer (4) formed on the cladding layer (3), a p-type cladding layer (5) and a p-type contact layer (6)...

20060011947 - Semiconductor structures and memory device constructions: The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as...

20060011948 - Structure and method of fabricating a transistor having a trench gate: An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the...

20060011949 - Metal-gate cmos device and fabrication method of making same: A metal-gate complementary metal-oxide-semiconductor (CMOS) device is disclosed. The CMOS device includes a PMOS transistor formed on a first area of a substrate and a NMOS transistor formed on a second area of the substrate and being coupled to the PMOS transistor. The PMOS transistor includes a first gate stack...

20060011950 - Semiconductor device and method of manufacturing the same: Disclosed is a semiconductor device comprises a semiconductor substrate having on its surface a trench, a polycrystalline semiconductor film formed inside the trench, a diffusion layer deposited on a surface region of the semiconductor substrate, and a metal semi-conductor nitride layer interposed between the diffusion layer and the polycrystalline semiconductor...

20060011951 - Process for fabricating non-volatile memory by tilt-angle ion implantation: A potassium/sodium ion sensing device applying an extended-gate field effect transistor, which using an extended-gate ion sensitive field effect transistor (EGFET) as base to fabricate a potassium/sodium ion sensing device, using the extended gate of the extended-gate ion sensitive field effect transistor as a signal intercept electrode, and immobilizing the...

20060011954 - Semiconductor photodetecting device and method of manufacturing the same: A semiconductor photodetecting device is provided for enabling a solid-state image sensor to meet the requirements of higher quality imaging and more reduction in cost. The photodetecting device of the present invention includes: a semiconductor substrate; and an epitaxial layer formed on the semiconductor substrate by epitaxial growth. The epitaxial...

20060011953 - Solid state imaging device and method of manufacturing the same: A solid-state imaging device including a photoelectric conversion portion and a charge transfer portion equipped with charge transfer electrodes to transfer the charge generated in the photoelectric conversion portion, wherein the charge transfer portion is provided with a charge transfer electrodes having a first electrode including a first layer electric...

20060011952 - Solid-state image sensor and method for fabricating the same: A solid-state image sensor comprises a semiconductor substrate of a first conductivity type having a color pixel region and a black pixel region; a first well of the first conductivity type formed in the color pixel region; a second well of the first conductivity type formed in the black pixel...

20060011957 - Information detecting device for photo film: A photo film scanner for photo film having an image frame has plural light sources, which apply illuminating light to the photo film, and include a multi-chip LED packages having plural chips for emitting the illuminating light at wavelengths different from one another. Plural photo receptors receive light from the...

20060011955 - Pixel cell having a grated interface: A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with said silicon substrate, and a method of fabricating the pixel cell having a grated interface....

20060011956 - Solid-state image sensor: The solid-state image sensor includes a pixel part 10, an analog circuit part 12, a digital circuit part 14 and an input/output circuit part 16. The digital circuit part 14 includes a first well 42c of a second conduction type formed in a second region of a semiconductor substrate 20...

20060011958 - Magnetic random access memory with bit line and/or digit line magnetic layers: A magnetic random access memory (MRAM) device may include a substrate, a first magnetic layer on the substrate, and a digit line on the first magnetic layer. A magnetic tunnel junction structure may be provided adjacent the digit line, and a bit line may be provided on the magnetic tunnel...

20060011959 - Semiconductor devices having a planarized insulating layer and methods of forming the same: A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping...

20060011960 - Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and...

20060011961 - Thin film capacitor: A thin film capacitor includes a pair of electrodes and a dielectric layer having piezoelectricity sandwiched therebetween. The phase characteristic of an impedance resulting from application of a voltage to the pair of electrodes peaks periodically according to a frequency of a signal to be inputted or outputted. The frequency...

20060011962 - Accumulation device with charge balance structure and method of forming the same: An accumulation-mode field effect transistor includes a plurality of gates and a semiconductor region having a channel region adjacent to but insulated from each of the plurality of gates. The semiconductor region further includes a conduction region wherein the channel regions and the conduction region are of a first conductivity...

20060011963 - Method and apparatus for interconnecting electrodes with partial titanium coating: The present subject matter includes a capacitor stack having a plurality of anode layers, and a plurality of cathodic metal substrates partially coated in a titanium coating. Cathode portions lacking titanium enable weld interconnections which are substantially free of titanium, improving capacitor properties. In some embodiments, anodes are interspersed among...

20060011964 - Semiconductor device and method for fabricating the same: In a semiconductor device of the present invention, capacitors are formed on a part of an interlayer dielectric (26) located in a memory cell area, and another interlayer dielectric (39) is formed on a part of still another interlayer dielectric (30) located in a peripheral circuit area AreaB. Furthermore, a...

20060011965 - Non-volatile flash memory device having at least two different channel concentrations and method of fabricating the same: In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding...

20060011970 - Field-effect transistors having doped aluminum oxide dielectrics: Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum...

20060011968 - Semiconductor devices and methods of forming the same: Methods of forming a semiconductor device include forming a structure including an oxide layer, a polysilicon layer and a mask layer on a substrate. The structure is etched to form an opening therein and the substrate beneath the opening to form a trench. An insulating structure is formed in the...

20060011967 - Split gate memory structure and manufacturing method thereof: A split gate memory structure including two cells formed on a semiconductor substrate comprises a first conductive line, two dielectric spacers, two conductive spacers, two doping regions, a first dielectric layer and a second conductive line, where the two dielectric spacers, two conductive spacers and two doping regions are symmetrical...

20060011966 - Structure of a non-volatile memory cell and method of forming the same: A flash memory cell is provided. The flash memory cell includes a substrate having a source and a drain formed therein, a bit line contact formed above the drain, a control gate formed above the substrate, a spacer floating gate formed above the substrate and adjacent to the control gate,...

20060011969 - Use of dilute steam ambient for improvement of flash devices: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures...

20060011971 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device has a substrate, a floating gate, a buried gate, a control gate, and source/drain regions. The substrate has a trench formed in a first direction. The floating gate is formed on a surface of the substrate outside the trench through a first gate insulating film....

20060011972 - Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell: A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially...

20060011973 - Semiconductor device: A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a...

20060011974 - Drain-extended mos transistors with diode clamp and methods for making the same: High side extended-drain MOS driver transistors (T2) are presented in which an extended drain (108, 156) is separated from a first buried layer (120) by a second buried layer (130), wherein an internal or external diode (148) is coupled between the first buried layer (120) and the extended drain (108,...

20060011975 - Semiconductor device and manufacturing method for the same: A manufacturing method for a semiconductor device, comprising the steps of: (a) forming a body portion of a DMOS by implanting impurity ions of a second conductive type into a predetermined region of a well of a first conductive type that has been formed in a main surface of a...

20060011976 - Termination for trench mis device having implanted drain-drift region: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in...

20060011980 - Electronic device, thin film transistor structure and flat panel display having the same: The present invention provides an electronic device having more than two conductive layers that cross but not in contact with each other. At least one of the conductive layers comprises a width change part, a width of which changes in a length direction of at least one of the conductive...

20060011981 - High frequency mos transistor, method of forming the same, and method of manufacturing a semiconductor device including the same: In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower...

20060011982 - Micro-mechanically strained semiconductor film: One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor film is formed on a substrate surface, and a recess is created beneath the film. A portion of the film is influenced into the void and strained....

20060011978 - Semiconductor constructions and integrated circuits: The invention includes a TFT-based logic circuit construction. Such construction includes a pair of first transistor devices, and a pair of second transistor devices over the first transistor devices. The first transistor devices have first active regions extending into a first semiconductive material, and the second transistor devices have second...

20060011977 - Semiconductor device and method of fabricating the same: According to the present invention, there is provided a semiconductor device comprising: a semiconductor layer formed on a semiconductor substrate via an insulating film and having a projecting shape; a gate electrode formed, via a gate insulating film, on a pair of side surfaces of four side surfaces of said...

20060011979 - Substrate for semiconductor device, method of manufacturing substrate for semiconductor device, substrate for electro-optical device, electro-optical device, and electronic apparatus: A substrate for a semiconductor device includes a substrate, a thin film transistor that is provided on the substrate, a wiring line that is provided above the thin film transistor, an interlayer insulating film that electrically isolates the wiring line from at least a semiconductor layer of the thin film...

20060011983 - Methods of fabricating strained-channel fet having a dopant supply region: A buried channel FET including a substrate, a relaxed SiGe layer, a channel layer, a SiGe cap layer, and an ion implanted dopant supply. The ion implanted dopant supply can be in either the SiGe cap layer or the relaxed SiGe layer. In one embodiment the FET is a MOSFET....

20060011984 - Control of strain in device layers by selective relaxation: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance....

20060011985 - Asymmetric hetero-doped high-voltage mosfet (ah2mos): An asymmetric heterodoped metal oxide (AH2MOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions are formed. The tub region has dopants of a...

20060011988 - Integrated circuit with multiple spacer insulating region widths: An integrated circuit with both P-channel transistors (823) and N-channel transistors (821) with different spacer insulating region widths. In one example, the outer sidewall spacer (321) of the N-channel transistors is removed while the P-channel regions (115) are masked such that the spacer insulating region widths of the N-channel transistors...

20060011987 - Method for fabricating a p-type shallow junction using diatomic arsenic: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises exposing a portion (125) of an n-type substrate (105) to an arsenic dimer (130). The method also includes forming a p-type lightly doped drain (LDD) region (145) within the portion of the...

20060011986 - Semiconductor device and method for manufacturing the same: A semiconductor device comprises an island shaped channel layer formed on a substrate, the channel later being composed of a semiconductor material, a gate insulation film formed on the channel layer, a gate electrode formed on the gate insulation film, an insulation film formed on both side faces opposite to...

20060011989 - Semiconductor device including metal insulator semiconductor field effect transistor and method of manufacturing the same: A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of...

20060011990 - Method for fabricating strained semiconductor structures and strained semiconductor structures formed thereby: Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source/drain regions. Disposed in at least...

20060011991 - Non-volatile semiconductor memory device and method of manufacturing the same: A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion...

20060011992 - Capacitor layout orientation: The disclosed embodiments relate to a plurality of capacitive memory elements disposed on a substrate. The substrate may comprise a processor, a memory device or other integrated circuit device. The capacitive memory elements may have a generally oblong shape and may be capacitive elements. The capacitive memory elements may be...

20060011993 - Junction interconnection structures: An integrated circuit device includes a semiconductor substrate having an interlayer insulating layer thereon and a first junction block embedded in the interlayer insulating layer. The first junction block includes a first plurality of conductive junction traces located side-by-side within the interlayer insulating layer and a corresponding first plurality of...

20060011994 - Damascene replacement metal gate process with controlled gate profile and length using si1-xgex as sacrificial material: A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered...

20060011995 - Method of forming an oxide film: A method of forming an oxide film and a method of manufacturing an electronic device utilizing the oxide film is disclosed. A silicon oxide film is formed on a substrate by sputtering. Therefore, the film formation is carried out at a low temperature. The sputtering atmosphere . comprises an oxidizing...

20060011996 - Semiconductor structure including silicide regions and method of making same: A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the...

20060011998 - Electromechanical electron transfer devices: An electron transfer device is implemented in a structure which is readily capable of achieving charge transfer cycle frequencies in the range of several hundred MHz or more and which can be formed by conventional semiconductor integrated circuit manufacturing processes. The device includes a substrate having a horizontal extent and...

20060011997 - Electrostatic discharge protection of a capacitive type fingerprint sensing: A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes an amplifier having an ungrounded input mode and an ungrounded output node. Output-to-input negative feedback that is sensitive to the fingerprint pattern is provided...

20060011999 - Magnetic field sensor comprising a hall element: A symmetrical vertical Hall element comprises a well of a first conductivity type that is embedded in a substrate of a second conductivity type and which is contacted by four contacts serving as current and voltage contacts. From the electrical point of view, such a Hall element with four contacts...

20060012000 - Thin-film transistors based on tunneling structures and applications: A hot electron transistor includes an emitter electrode, a base electrode, a collector electrode, and a first tunneling structure disposed and serving as a transport of electrons between the emitter and base electrodes. The first tunneling structure includes at least a first amorphous insulating layer and a different, second insulating...

20060012001 - Cmos image sensor and method for fabricating the same: A complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same are disclosed. The image sensor includes a sub-layer having a photodiode and a plurality of transistors formed thereon, a pad insulating layer formed on the sub-layer, a micro-lens formed on the pad insulating layer, the micro-lens...

20060012002 - Device for mounting a semiconductor package on a support plate via a base: A semiconductor package is mounted to a support plate through a base. The base is inserted between a rear face of the semiconductor package and a front face of the support plate. An electrical connection mechanism is provided to connect the semiconductor package to the support plate pass. This mechanism...

20060012003 - Seal ring for mixed circuitry semiconductor devices: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic...

20060012004 - Sti liner for soi structure: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer...

20060012006 - Capacitors integrated with inductive components: Techniques for producing integrated capacitors are disclosed. According to one of the techniques, one or more layers are introduced in conjunction with a ground layer supporting a substrate on which various components are realized. Depending on the use of an integrated capacitor, micro capacitors can be formed between one introduced...

20060012005 - Method for producing a component comprising a conductor structure that is suitable for use at high frequencies: The invention provides a process for producing a substrate having a conductor arrangement that is suitable for radio-frequency applications, with improved radio-frequency properties. For this purpose, the process includes the steps of: depositing a structured glass layer having at least one opening over a contact-connection region by evaporation coating on...

20060012007 - Open pattern inductor: The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or...

20060012008 - Resistance variable memory device and method of fabrication: Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least one chalcogenide glass layer. The invention also relates to methods of forming such a...

20060012009 - Semiconductor device: A semiconductor device includes a variable capacitance diode. The variable capacitance diode includes a semiconductor substrate having a circuit area; a plurality of diffusion areas formed on the semiconductor substrate in the circuit area; a gate oxide layer formed in a gate area between the diffusion areas; a control electrode...

20060012010 - Epitaxial growing method and substrate for epitaxial growth: An epitaxial growth method includes: supporting a substrate for growth (for example, an InP substrate) with a substrate supporter, growing a compound semiconductor layer comprising 3 or 4 elements (for example, a III-V group compound semiconductor such as an InGaAs layer, AlGaAs layer, AlInAs layer and AlInGaAs layer) on the...

20060012011 - Mehtod for processing nitride semiconductor crystal surface and nitride semiconductor crystal obtained by such method: A method of processing a surface of a nitride semiconductor crystal, wherein a surface of a nitride semiconductor crystal is brought into contact with a liquid containing at least Na, Li or Ca as a processing solution. In the method, the processing solution can be a liquid containing at least...

20060012012 - Semiconductor device with crack prevention ring and method of manufacture thereof: A method of forming a crack prevention ring at the exterior edge of an integrated circuit to prevent delamination and cracking during the separation of the integrated circuits into individual die. The crack prevention ring extends vertically into a semiconductor workpiece to at least a metallization layer of the integrated...

20060012013 - Columnar structured material and method of manufacturing the same: A method of forming, on a substrate, minute-sized columnar portions of a columnar structured material at minute intervals, and a columnar structured material formed by the manufacturing method. A columnar structured material is formed through an etching process in which a pattern of minute dots formed on the substrate is...

20060012014 - Reliability of low-k dielectric devices with energy dissipative layer: The present invention provides a plastically and/or viscoelastically deformable layer that can be used in conjunction with a low-k dielectric (k of less than 4.0) to provide an electronic semiconductor structure having improved reliability. The deformable layer can be incorporated into various points within an electronic structure to dissipate energy...

20060012015 - Two-pole smt miniature housing for semiconductor components and method for the manufacture thereof: In a two-pole SMT miniature housing in leadframe technique for semiconductor components, a semiconductor chip is mounted on one leadframe part and is contacted to a further leadframe part. The further leadframe part is conducted out of the housing in which the chip is encapsulated as a solder terminal. No...

20060012016 - High-frequency power semiconductor module with a hollow housing and method for the production thereof: The invention relates to a radiofrequency power semiconductor module having a cavity housing constructed from three modules, a 1st module, which has an upwardly and downwardly open housing frame with horizontally arranged flat conductors, a 2nd module, which has the chip island as a heat sink with at least one...

20060012017 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a frame provided on a substrate to form a semiconductor-chip accommodating part on the substrate. A semiconductor chip is provided in the semiconductor-chip accommodating part. An organic insulating layer is provided to cover the semiconductor chip and the frame. A wiring layer is provided on the...

20060012018 - Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package: A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package...

20060012019 - Semiconductor package: A semiconductor package includes a semiconductor chip, a circuit board at which a wire pattern is formed, and a metal structure including a portion inserted through an opening of the circuit board and upon which the semiconductor chip rests. With the semiconductor chip in direct contact with the metal structure,...

20060012020 - Wafer-level assembly method for semiconductor devices: A wafer-level assembly method for bonding chips to other wafers or to arrays of circuits. The method allows an array of chips, held on a temporary carrier, to be separated by expanding said carrier so that said chips can be aligned and bonded to a substrate with dimensions that would...

20060012021 - Film bulk acoustic resonator package and method of fabricating same: A microfabricated device has a first substrate, a second substrate, a film bulk acoustic resonator (FBAR) device, and a circuit. The second substrate is bonded to the first substrate to define a chamber. The FBAR device is located on a surface of the first substrate and inside the chamber. The...

20060012022 - Integrated circuit die with pedestal: An integrated circuit die is provided having a body portion having a singulation side and a pedestal portion extending from the body portion and having a singulation side coplanar with the singulation side of the body portion....

20060012023 - Method of manufacturing a data carrier: A method of manufacturing a data carrier from a support strip includes an overmoulding step, in which at least one support element of the support strip is overmoulded so as to obtain a data carrier body, and a microcircuit-connecting step, in which a microcircuit is electrically connected to the wiring...

20060012024 - Semiconductor chip assembly with metal containment wall and solder terminal: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a metal containment wall and a solder terminal, and a connection joint that electrically connects the routing line and the pad. The metal containment wall includes a cavity, and...

20060012025 - Semiconductor device and manufacturing method therefor: A semiconductor device is produced using a lead frame whose size is smaller than a prescribed center area of a semiconductor chip surrounded by its bonding pads, which are connected with electrodes supported by electrode supports and interconnected with outer frames and an intermediate frame of the lead frame via...

20060012026 - Semiconductor package and method for its manufacture: A semiconductor package includes a metal plate in which one or more openings are formed, the metal plate mounting a semiconductor chip and a printed wire pattern substrate, e.g. a PCB, mounting one or more decoupling capacitors. The semiconductor chip is in direct contact with the metal plate to improve...

20060012028 - Device mounting board: A device mounting board on which a device is mounted is provided with a substrate and an insulating film provided on one surface of the substrate. The substrate and the insulating film include glass fiber impregnated with epoxy resin. The epoxy resin impregnation ratio of the glass fiber included in...

20060012030 - Multi-conducting through hole structure: A multi-conducting through hole structure is provided. The multi-conducting through hole structure has a substrate, at least two signal lines and at least a reference line. The substrate has a through hole passing therethrough. The signal lines are disposed on a portion of an inner surface of the through hole...

20060012029 - Semiconductor device: A minute wiring structure portion including first wiring layers and first insulating layers, in which each of first wiring layers and each of first insulating layers are alternately laminated, is formed on a semiconductor substrate. A first huge wiring structure portion is formed on the minute wiring structure portion, and...

20060012027 - Thermally isolated via structure: This document discusses, among other things, a flexible circuit or other laminate comprising a first conductive layer and a second conductive layer disposed over the first conductive layer. An insulator is disposed between the first and second conductive layers. A conductive via extends through the insulator and electrically connects the...

20060012032 - Electronic device with semiconductor chip including a radiofrequency power module: An electronic device, including a radiofrequency power module, includes a cavity housing including a housing frame with plastic walls and with a metal frame including a top side and a rear side, a metallic housing bottom including at least one chip island, and at least one semiconductor chip. Each semiconductor...

20060012031 - Heat dissipation device for integrated circuits: An integrated circuit (27, 67) is packaged by mounting it onto a substrate (11, 55) with a heat conductive plate (1, 41) interposed between the integrated circuit (27, 67) and the substrate (11, 55). The plate (1, 41) has portions (5, 7, 9) extending laterally out from under the integrated...

20060012034 - Engine control circuit device: An engine control circuit device which has higher heat resistance and can be installed in a place exposed to severe thermal environments. In an engine control circuit device comprising a circuit board on which a plurality of packaged electronic parts are mounted, and a connector mounted on the circuit board...

20060012033 - Semiconductor device and a method of manufacturing the same: A semiconductor device has a semiconductor chip having first and second surfaces; a sealing resin formed over the first surface; and a cooling structure having a first conductive layer formed on the first surface, an n-type semiconductor formed on the first conductive layer and having one end thereof being exposed...

20060012036 - Circuit device with at least partial packaging and method for forming: A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may...

20060012035 - Method of packaging integrated circuits, and integrated circuit packages produced by the method: A method of packaging integrated circuits is proposed in which two integrated circuits 13, 17 are provided in register on opposite sides of a single substrate 1. Electrical contacts on the each of the integrated circuits 13, 17 are electrically connected to electrical conductors of the substrate 1. One of...

20060012037 - Methods for bonding and devices according to such methods: A method of bonding two elements such as wafers used in microelectronics applications is disclosed. One inventive aspect relates to a method for bonding comprising producing on a first main surface of a first element a first solder ball, producing on a first main surface of a second element a...

20060012039 - Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric...

20060012038 - Semiconductor device, semiconductor device module and method of manufacturing the semiconductor device: A reliable semiconductor device including support bumps so as to adequately seal the region between the chips is to be provided. The semiconductor device includes a semiconductor chip; a bump formed on an upper face of the semiconductor chip; and a plurality of support bumps formed along a circumference of...

20060012041 - Connection between two circuitry components: A semiconductor chip or wafer includes a passivation layer, a pad and a bump. The pad is exposed by an opening in the passivation layer. The bump is connected to the pad, wherein the area of the connection between the pad and the bump is larger than 30,000 μm2....

20060012040 - Semiconductor package: A semiconductor package includes a substrate, a first chip, a nonconductive adhesive, a second chip and a plurality of supporting balls. The first chip has an upper surface and a lower surface opposite to the upper surface, and the lower surface is mounted on the substrate. The nonconductive adhesive is...

20060012042 - Use of direct gold surface finish on a copper wire-bond substrate, methods of making same, and methods of testing same: A wire-bonding substrate is described. The wire-bonding substrate includes a copper metallization and a gold surface finish disposed above and on the copper metallization. The gold surface finish completes a structure that includes at least one of a bond finger for wire bonding of a first side of the substrate,...

20060012043 - Plasma display device: A plasma display device including a plasma display panel that displays images, an integrated circuit chip that controls potentials to be applied to a discharge electrode, a protection film that covers the integrated circuit chip, a thermally conductive material disposed on a portion of a surface of the protection film,...

20060012044 - Plating method: Methods for depositing a metal or metal alloy on a substrate and articles made with the methods are described. The metal or metal alloy is deposited on the substrate electrolytically. The current is periodically interrupted during deposition to improve throwing power and reduce nodule formation on the metal or metal...

20060012045 - Design of beol patterns to reduce the stresses on structures below chip bondpads: A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the...

20060012047 - Method of manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device comprising forming a hydrophobic interlayer insulating film having a relative dielectric constant of 3.5 or less above a semiconductor substrate, forming a recess in the interlayer insulating film, depositing a conductive material above the interlayer insulating film having the recess to...

20060012046 - Semiconductor device having copper wiring and its manufacture method: A first interlayer insulating film made of insulting material is formed over an underlying substrate. A via hole is formed through the first interlayer insulating film. A conductive plug made of copper or alloy mainly consisting of copper is filled in the via hole. A second interlayer insulating film made...

20060012048 - Wiring substrate for mounting semiconductors, method of manufacturing the same, and semiconductor package: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the...

20060012049 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within...

20060012050 - Semiconductor device, designing method thereof, and recording medium storing semicondcutor designing program: A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of...

20060012051 - Production process and production apparatus of three-dimensionally structured material: Disclosed herein is a process for producing a three-dimensionally structured material, which comprises the steps of preparing a liquid composition comprising a block polymer and a liquid medium, and imparting a stimulus to the liquid composition to modify the block polymer, thereby forming the three-dimensionally structured material....

20060012052 - Dual damascene wiring and method: A structure and method of fabricating a dual damascene interconnect structure, the structure including a dual damascene wire in a dielectric layer, the dual damascene wires extending a distance into the dielectric layer less than the thickness of the dielectric layer and dual damascene via bars integral with and extending...

20060012053 - Flip-chip packaged smd-type led with antistatic function and having no wire bonding: A flip-chip packaged SMD-type (surface-mount device) light emitting diode is provided. The light emitting diode chip is packaged in flip chip packages and is connected with an electrostatic protection device such as a transient voltage suppressor (TVS) or a Zener diode. The electrostatic protection device is attached with a substrate...

20060012054 - High wireability microvia substrate: The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the...

20060012055 - Semiconductor package including rivet for bonding of lead posts: A semiconductor device (30,30′) includes a semiconductor die (32, 32′) having bonding pads (34, 34′) and ball bumps (38, 38′). Each of the ball bumps (38, 38′) has a base portion (40, 40′) and a protruding portion (42, 42′). The semiconductor die (32, 32′) is mounted on a lead frame...

20060012056 - Semiconductor chip resin encapsulation method: A semiconductor chip resin encapsulation method, including a resin filling and curing step of encapsulating a plurality of semiconductor chips, which have been bonded onto a substrate, in a molten resin, and curing the molten resin. The semiconductor chip resin encapsulation method further includes a grinding step of grinding an...

20060006373 - Method for manufacturing pattern formed structure: In order to achieve the object, the present invention provides a method for manufacturing a pattern formed structure, comprising: a patterning substrate preparing process of preparing a patterning substrate having a base material and a photocatalyst-containing property variable layer which is formed on the base material, comprises at least a...

20060006374 - Phase-change memory device and method of manufacturing the same: Disclosed are a phase-change memory device and its manufacturing method, which can reduce a contact area between a bottom electrode and a phase-change layer, thereby reducing the quantity of current necessary for phase change. The phase-change memory device comprises: a first oxide layer formed on a dielectric interlayer and a...

20060006375 - Light mixing led: A light mixing LED includes a first active layer containing In laminated adjacent to an n-type nitride-based semiconductor stack layer, a second active layer containing In laminated adjacent to a p-type nitride-based semiconductor stack layer, and a tunnelable barrier layer formed between the first active layer and the second active...

20060006376 - Strongly textured atomic ridge nanowindows: The present invention provides a MOSFET device comprising: a substrate including a plurality of atomic ridges, each of the atomic ridges including a semiconductor layer comprising Si and an dielectric layer comprising a Si compound; a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at...

20060006377 - Suspended carbon nanotube field effect transistor: The invention provides a carbon nanotube field effect transistor including a nanotube having a length suspended between source and drain electrodes. A gate dielectric material coaxially coats the suspended nanotube length and at least a portion of the source and drain electrodes. A gate metal layer coaxially coats the gate...

20060006380 - Composition for forming organic insulating film and method for forming pattern of organic insulating film using the same: A photo-patternable composition for forming an organic insulating film which includes (i) a functional group-containing monomer, (ii) an initiator generating an acid or a radical upon light irradiation, and (iii) an organic or inorganic polymer. Further disclosed is a method for forming a pattern of an organic insulating film using...

20060006378 - Electrical circuit, thin film transistor, method for manufacturing electric circuit and method for manufactturing thin film transistor: An electrical circuit containing a substrate having thereon a receptive layer, wherein the receptive layer has a conductive polymer impregnated in the receptive layer, and a method for forming the electrical circuit....

20060006379 - Organic semiconductor copolymers containing oligothiophene and n-type heteroaromatic units: An exemplary organic semiconductor copolymer includes a polymeric repeat structure having a polythiophene structure and an electron accepting unit. The electron accepting unit has at least one electron-accepting heteroaromatic structure with at least one electron-withdrawing imine nitrogen in the heteroaromatic structure or a thiophene-arylene comprising a C2-30 heteroaromatic structure. Methods...

20060006381 - Organic thin film transistor with polymeric interface: Provided is an organic thin film transistor comprising a polymeric layer interposed between a gate dielectric and an organic semiconductor layer. Various homopolymers, copolymers, and functional copolymers are taught for use in the polymeric layer. An integrated circuit comprising a multiplicity of thin film transistors and methods of making a...

20060006382 - Composite material: Composite material (10) comprises a substrate (1) and a chemically, mechanically, physically, catalytically and/or optically functional titanium oxide layer (2), applied on at least one side thereof. A titanium oxide layer (2) is deposited on the substrate (1) as a base layer (3), made from TiOx with an oxygen content...

20060006383 - Single and double-gate pseudo-fet devices for semiconductor materials evaluation: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior...

20060006384 - Special contact points for accessing internal circuitry of an intergrated circuit: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads...

20060006385 - Liquid crystal display device and method of manufacturing liquid crystal display device with color filter layer on thin film transistor: A method of fabricating a liquid crystal display device is provided. The method of fabricating a liquid crystal display device includes forming a thin film transistor including a source electrode and a drain electrode on a substrate, forming a first passivation layer on the substrate, forming a black matrix on...

20060006386 - Lateral semiconductor component with a drift zone having at least one field electrode: A semiconductor component is described. In one embodiment, the semiconductor component includes a semiconductor body with a first side and a second side. A drift zone is provided, which is arranged in the semiconductor body below the first side and extends in a first lateral direction of the semiconductor body...

20060006388 - Method of manufacturing semiconductor device: A grain size of a crystal grain in a crystalline semiconductor film obtained by a thermal crystallization method using a metallic element is reduced. Thus, the number of crystal grains in active regions of a device is made uniform. The thermal crystallization method using a metallic element is performed for...

20060006387 - Semiconductor device and ltps-tft within and method of making the same: A thin film transistor (TFT) formed on a substrate includes a polycrystalline film, a gate insulator, a hydrogen-supplying film and a gate electrode. The polycrystalline film is formed on the substrate. Two sides of the polycrystalline film serve as the source and the drain of the semiconductor device, and the...

20060006389 - Technique for forming a substrate having crystalline semiconductor regions of different characteristics: Different types of crystalline semiconductor regions are provided on a single substrate by forming a dielectric region within a first crystalline semiconductor region. Thereafter, a second crystalline region is positioned above the dielectric region by wafer bond techniques. In preferred embodiments, isolation structures may be formed in the first crystalline...

20060006392 - Display device: A display device has C-MOS p-Si TFTs which enable high integration by reducing spaces for P-MOS TFTs and N-MOS TFTs in a driving circuit or the like thereof. A self-aligned C-MOS process is adopted, which uses a half tone mask as an exposure mask for manufacturing the C-MOS p-Si TFTs...

20060006391 - Image display devices: To obtain a system-in-display with high performance and multifunction at low cost, high performance and reliability of a low temperature polysilicon thin film transistor is devised by terminating traps at a interface between a gate oxide film and a polycrystalline silicon film constituting a channel with fluorine. To maximize its...

20060006390 - Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same: A method for forming a polysilicon structure is provided. An amorphous silicon structure with a first amorphous silicon region and a second amorphous silicon region is formed in a first region and a second region of a substrate, respectively. The first amorphous silicon region is thinner than the second amorphous...

20060006395 - Method for manufacturing aluminum nitride single crystal: There is provided a method for manufacturing an aluminum nitride single crystal, the method including the steps of: preparing a raw material composition containing: aluminum oxide and/or an aluminum oxide precursor which is converted into aluminum oxide by heating, and aluminum nitride and/or an aluminum nitride precursor which is converted...

20060006394 - Silicon carbide schottky diodes and fabrication method: A semiconductor device and method of formation wherein a disjointed termination layer 102 is formed around a Schottky metal region 110. A SiC substrate 104 is provided, on top of which a SiC blocking layer 108 is disposed. The disjointed termination layer 102 is formed above the SiC blocking layer...

20060006393 - Silicon-rich nickel-silicide ohmic contacts for sic semiconductor devices: A method of producing an ohmic contact and a resulting ohmic contact structure are disclosed. The method includes the steps of forming a deposited film of nickel and silicon on a silicon carbide surface at a temperature below which either element will react with silicon carbide and in respective proportions...

20060006397 - Device and method for emitting output light using group iia/iib selenide sulfur-based phosphor material: A device and method for emitting output light utilizes Group IIA/IIB element Selenide Sulfur-based phosphor material to convert at least some of the original light emitted from a light source of the device to longer wavelength light to change the optical spectrum of the output light. Thus, the device and...

20060006396 - Phosphor mixture of organge/red znse0.5s0.5:cu,cl and green basrga4s7:eu for white phosphor-converted led: A device and method for emitting output light utilizes orange/red light emitting ZnSe0.5S0.5:Cu,Cl phosphor material and green light emitting BaSrGa4S7:Eu phosphor material to convert some of the original light emitted from a light source of the device to a longer wavelength light to change the optical spectrum of the output...

20060006399 - Gallium nitride based ill-v group compound semiconductor device and method of producing the same: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed....

20060006400 - Method of making diode having reflective layer: A method of forming a light emitting diode includes forming a transparent substrate and a GaN buffer layer on the transparent substrate. An n-GaN layer is formed on the buffer layer. An active layer is formed on the n-GaN layer. A p-GaN layer is formed on the active layer. A...

20060006398 - Nitride-based compound semiconductor light emitting device and fabricating method thereof: The nitride-based compound semiconductor light emitting device includes a first ohmic electrode, a bonding metal layer, a second ohmic electrode, a nitride-based compound semiconductor layer, and a transparent electrode stacked in this order on a support substrate, and further includes an ohmic electrode formed on a back side of the...

20060006401 - Flip chip light emitting diode: A flip chip light emitting diode structure includes a substrate, a LED chip, and a low refractive index layer. The substrate is formed of a substantially transparent material, which includes a top surface and a lower surface. The LED chip has a first surface and a second surface. The first...

20060006402 - Light emitting diode having an omnidirectional reflector including a transparent conductive layer: The present invention is related to a light emitting diode of an omnidirectional reflector providing with a transparent conductive layer. In the present invention, a cohesion layer is formed between a transparent layer and a metal reflection layer to improve the cohesive force therebetween and increase the reflectivity of the...

20060006404 - Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices: A packaged light emitting device includes a carrier substrate having a top surface and a bottom surface, first and second conductive vias extending from the top surface of the substrate to the bottom surface of the substrate, and a bond pad on the top surface of the substrate in electrical...

20060006403 - Optical module: There is provided an optical module in which electrical wirings in a module package are simplified without increasing a manufacturing cost. A light emitting element is mounted on a substrate having electrical wirings therein. In the substrate, electrodes connected to the electrical wirings are formed at a side where the...

20060006405 - Surface mountable light emitting diode assemblies packaged for high temperature operation: Light emitting diode (LED) assemblies packaged for high temperature operation and surface mounting. In particular, the LED assemblies according to the present invention are constructed to include a thermally conducting base and an optically efficient cavity that provides protection for the LED assembly and maximizes light extraction. The LED assemblies...

20060006406 - Light emitting diode package and light source comprising the same: An LED package comprises a substrate, one or three terminals formed on a first side of the substrate, three terminals formed on a second side opposite to the first side, and two or three LEDs disposed on the substrate, one of the LEDS being electrically connected to one of the...

20060006408 - Light emitting element and method of making same: A light emitting element is provided with a semiconductor layer having a light emitting layer and an uneven surface, and a transparent material formed on the uneven surface. The transparent material has a refractive index lower than a sapphire substrate. Alternatively, a light emitting element is provided with a semiconductor...

20060006407 - Nitride semiconductor device and method of manufacturing the same: The present invention provides a nitride semiconductor device. The nitride semiconductor device comprises an n-type nitride semiconductor layer formed on a nitride crystal growth substrate. An active layer is formed on the n-type nitride semiconductor layer. A first p-type nitride semiconductor layer is formed on the active layer. A micro-structured...

20060006409 - Power semiconductor device: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity...

20060006410 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and...

20060006411 - Method for producing a package for an electronic circuit and a substrate for a package: The invention relates a substrate for a package for an electronic circuit and methods for packaging an electronic circuit with a substrate. The substrate comprises at least one conduction region and an activation region arranged within the substrate. The activation region is generally in contact with the conduction region and...

20060006412 - Semiconductor substrate, method of manufacturing the same and semiconductor device: A semiconductor substrate comprising a silicon substrate with an oxide film on its surface, on which a silicon layer, a warp-relieved SiGe layer and a warped cap layer are formed in this order, a semiconductor device comprising a transistor, a diode, a capacitor and/or a bipolar transistor formed solely or...

20060006414 - Algan/gan high electron mobility transistor devices: The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where...

20060006413 - Iii-nitride device passivation and method: An embodiment of a III-nitride semiconductor device and method for making the same may include a low resistive passivation layer that permits the formation of device contacts without damage to the III-nitride material during high temperature processing. The passivation layer may be used to passivate the entire device. The passivation...

20060006415 - Wide bandgap hemts with source connected field plates: A HEMT comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the plurality of active layers. A spacer layer is formed on at least a portion of a surface of said plurality of active layers and...

20060006416 - Bipolar transistor with nonselective epitaxial base and raised extrinsic base: A method for forming a transistor that includes forming an intrinsic base on a substrate using nonselective epitaxy and forming a raised extrinsic base on the intrinsic base. The nonselective epitaxy used to form the intrinsic base avoids the costly, complex, and defect prone process of selective epitaxy while the...

20060006417 - Electronic device, thin film transistor structure and flat panel display having the same: The invention provides an electronic device configured to prevent or reduce electrostatic discharge from causing a pixel to malfunction. An electronic device manufactured according to the principles of the invention may include multiple conductive layers that cross but do not contact each other, wherein at least one of the conductive...

20060006418 - Semiconductor device having an improved voltage control oscillator circuit: A semiconductor device having an improved voltage control oscillator circuit is provided. The voltage control oscillator circuit includes, in combination, a variable-capacitance element and at least one bipolar transistor on a single semiconductor substrate. The variable-capacitance element includes reversely serially connected PN junctions, and junctions are formed by a single...

20060006419 - Method of testing a memory module and hub of the memory module: A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of...

20060006421 - Memory device, programmable resistance memory cell and memory array: A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and...

20060006420 - Semiconductor device and a cmos integrated circuit device: A semiconductor device includes a stress-accumulating insulation film formed on a semiconductor substrate so as to cover a gate electrode and sidewall insulation films, the stress-accumulating insulation film accumulating a stress therein, wherein the stress-accumulating insulation film including a channel part covering the gate electrode and the sidewall insulation films...

20060006424 - Light emitting apparatus and method for manufacturing the same: The purpose of the invention is to improve reliability of a light emitting apparatus comprising TFTs and organic light emitting elements. The light emitting apparatus according to the invention having thin film transistors and light emitting elements, comprises; a second inorganic insulation layer on a gate electrode, a first organic...

20060006422 - Semiconductor package substrate having bonding pads with plated layer thereon and process of manufacturing the same: A semiconductor package substrate is provided having a plurality of bonding pads on at least one surface thereof and covered by a conductive film. A photoresist layer formed over the conductive film has a plurality of first openings for exposing portions of the conductive film corresponding to the bonding pads....

20060006423 - Semiconductor wafer and manufacturing method thereof: A semiconductor wafer and its manufacturing method are provided where the current driving capability of a MOS transistor can be sufficiently enhanced. An SOI layer wafer in which an SOI layer (32) is formed has a <100> crystal direction notch (32a) and a <110> crystal direction notch (32b). The SOI...

20060006425 - Thin film transistor substrate and its manufacture: A semiconductor layer with a threshold voltage for n-channel is formed and patterned to TFT island areas. A gate insulating film is deposited. The first gate electrode layer is fomed and pattered to form an opening. Phosphorous ions are implanted into a p-channel TFT in the opening to set threshold...

20060006426 - Signal processing device and method: The present invention provides a signal processing device which, even when a defective pixel exists in the VOPB area B, can detect column noise accurately, and can carry out column noise correction. The signal processing device includes a solid-state image pickup element having a pixel part including an effective pixel...

20060006427 - Material architecture for the fabrication of low temperature transistor: A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example...

20060006428 - Image sensor and method of fabricating the same: Image sensors and methods of fabricating the same are provided. The image sensor includes a blocking pattern disposed on photodiodes. The blocking pattern is formed of insulation material having a metal diffusion coefficient which is lower than a silicon oxide diffusion coefficient. Therefore, dark defects of the image sensor are...

20060006429 - Semiconductor device, method for manufacturing the same, and display device: On a poly-silicon layer formed on a glass substrate, a gate electrode is formed via a gate insulation film. After forming an impurity-doped region in the poly-silicon layer using the gate electrode as a mask, an insulation layer is formed on the gate electrode and an insulation film is then...

20060006430 - Submount substrate for mounting light emitting device and method of fabricating the same: A submount substrate for mounting a light emitting device and a method of fabricating the same, wherein since a submount substrate for mouthing a light emitting device in which a Zener diode device is integrated can be fabricated by means of a silicon bulk micromachining process without using a diffusion...

20060006433 - Electrical passivation of silicon-containing surfaces using organic layers: Electrical structures and devices may be formed and include an organic passivating layer that is chemically bonded to a silicon-containing semiconductor material to improve the electrical properties of electrical devices. In different embodiments, the organic passivating layer may remain within finished devices to reduce dangling bonds, improve carrier lifetimes, decrease...

20060006431 - Metal oxide semiconductor (mos) varactor: A metal oxide semiconductor (MOS) varactor includes a first terminal and a second terminal, and the MOS varactor comprises a substrate; a deep well, formed on the substrate; and a first MOS device, formed on the deep well; wherein a gate of the first MOS device is coupled to the...

20060006434 - Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which...

20060006432 - Semiconductor devices, dc/dc converter and power supply: A semiconductor device in which the self-turn-on phenomenon is prevented that can significantly improve power conversion efficiency. The semiconductor device is a system-in-package for power supply applications in which a high-side switch, a low-side switch, and two drivers are included in a single package. The device includes an auxiliary switch...

20060006435 - Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses: Contacts for a nitride based transistor and methods of fabricating such contacts provide a recess through a regrowth process. The contacts are formed in the recess. The regrowth process includes fabricating a first cap layer comprising a Group III-nitride semiconductor material. A mask is fabricated and patterned on the first...

20060006436 - Deuterated structures for image sensors and methods for forming the same: A pixel cell with a photo-conversion device and at least one structure includes a deuterated material adjacent the photo-conversion device....

20060006437 - Image sensor and method of fabricating the same: Image sensors and methods of fabricating the same are provided. The image sensor includes a blocking pattern disposed on photodiodes. The blocking pattern is formed of insulation material having a metal diffusion coefficient which is lower than a silicon oxide diffusion coefficient. Therefore, dark defects of the image sensor are...

20060006438 - Solid state imaging device and production method therefor: Since a main light beam a launches on pixels in a screen peripheral part at an angle of incidence θ, a microlens (260), color filter (250), wires (220, 230 and 240), photodiode (110) and so on are disposed along the direction of incidence in accordance with the angle of incidence...

20060006439 - Magnetic random access memory with multiple memory layers and improved memory cell selectivity: A magnetic random access memory (MRAM) has multiple stacked memory layers, with each memory layer being a plurality of alternating rows of memory cells and electrically conductive access lines. The access lines in each layer are aligned with the access lines in the layers above and below. Similarly the memory...

20060006440 - Devices with different electrical gate dielectric thicknesses but with substantially similar physical configurations: An integrated circuit is disclosed having one or more devices having substantially similar physical gate electric thicknesses but different electrical gate electric thicknesses for accommodating various operation needs. One or more devices are manufactured with a same mask set using multiple doping processes to generate substantially similar physical gate dielectric...

20060006443 - Electrically programmable memory element with reduced area of contact: A programmable resistance memory element having a conductive layer as an electrode. The conductive layer and memory material may have a small area of contact. In one embodiment, the conductive layer may be cup-shaped. In one embodiment, the memory element may include a chalcogenide material....

20060006442 - Process for making a silicon-on-insulator ledge and structures achieved thereby: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region...

20060006441 - Semiconductor device including a trench-type metal-insulator-metal (mim) capacitor and method of fabricating the same: In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a bottom electrode and a first interconnection layer on a semiconductor substrate, an upper surface of the bottom electrode and an upper surface of the first interconnection layer being level, an interlayer insulating layer having...

20060006444 - Selective epitaxy vertical integrated circuit components and methods: Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of the component body. These components are grown directly in electrical communication lines. Moreover,...

20060006445 - Container capacitor structure and method of formation thereof: Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode (“bottom electrodes”) of the structure. The etch provides a recess between proximal pairs of container capacitor structures, which is available for forming additional capacitance. A capacitor...

20060006446 - Method for fabricating a dram memory cell arrangement having fin field effect transistors and dram memory cell: The invention relates to the fabrication of DRAM memory cell arrangements having fin field effect transistors and curved channel field effect transistors. The FinFETs and CFETs are formed in a manner oriented to semiconductor fins arranged in cell rows. Within the cell rows, the semiconductor fins are spaced apart from...

20060006447 - Semiconductor devices having a metal-insulator-metal capacitor and methods of forming the same: A semiconductor device having an MIM capacitor and a method of forming the same are provided. A lower electrode includes a plate electrode and a sidewall electrode. The plate electrode is formed by a patterning process preferably including a plasma anisotropic etching. The sidewall electrode is formed like a spacer...

20060006448 - Localized masking for semiconductor structure development: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface...

20060006450 - Capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen: The invention comprises capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen. In one embodiment, a capacitor includes first and second conductive electrodes having a high k capacitor dielectric region positioned therebetween. The high k capacitor dielectric region includes a layer of...

20060006449 - Semiconductor integrated circuit devices having a hybrid dielectric layer and methods of fabricating the same: In semiconductor integrated circuit devices having a hybrid dielectric layer and methods of fabricating the same, the hybrid dielectric layer includes a lower dielectric layer, an intermediate dielectric layer and an upper dielectric layer which are sequentially stacked. The lower dielectric layer contains hafnium (Hf) or zirconium (Zr). The upper...

20060006452 - Eeprom device and manufacturing method thereof: Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a...

20060006454 - Electrically alterable memory cell: A nonvolatile memory cell is provided. The cell has a charge filter, a tunneling gate, a ballistic gate, a charge storage layer, a source, and a drain with a channel defined between the source and drain. The charge filter permits transporting of charge carriers of one polarity type from the...

20060006455 - Memory cell with polysilicon local interconnects: Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity,...

20060006453 - Nonvolatile semiconductor memory device and method of fabricating the same: In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in...

20060006451 - Use of selective epitaxial silicon growth in formation of floating gates: Methods and apparatus utilizing epitaxial silicon growth on a base structure of a floating gate of a floating-gate memory cell to increase the available coupling area of the floating gate while reducing the spacing between adjacent memory cells. The epitaxial silicon growth facilitates a reduction in spacing between adjacent cells...

20060006456 - Memory cells and select gates of nand memory arrays: A select gate of a NAND memory array has a first dielectric layer formed on a semiconductor substrate. A first conductive layer is formed on the first dielectric layer. Conductive spacers are formed on sidewalls of the first conductive layer and are located between an upper surface of the first...

20060006457 - Semiconductor nonvolatile memory cell array: A semiconductor nonvolatile memory cell array includes a plurality of semiconductor nonvolatile memory cells. Each memory cell has a control electrode (30); a pair of impurity diffusion regions (21, 22) to provide first and second main electrodes; a pair of variable resistance sections (24, 26); and a pair of charge...

20060006458 - Semiconductor device and method for manufacturing the same: A semiconductor device comprises a semiconductor substrate. A plurality of first semiconductor regions are formed in a single crystal semiconductor layer of a first conduction type disposed on a surface of the semiconductor substrate as defined by a plurality of trenches provided in the single crystal semiconductor layer. A plurality...

20060006459 - Semiconductor system functioning as thyristor in on-state, and as bipolar transistor in transient state or with overcurrent: A semiconductor system includes a self arc-extinguishing device, and an IGBT that works as a thyristor when a current between a first terminal and a second terminal connected to a second well electrode is small, and as a bipolar transistor when that current is large, and automatically switches between them...

20060006460 - Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is...

20060006461 - Drain extended mos transistors and methods for making the same: Drain extended MOS transistors (52) and fabrication methods (100) therefor are presented, in which a voltage drop region (80) is provided in a well (82) of a second conductivity type between a channel (78) of a first conductivity type and a drain (74) to inhibit channel hot carrier or direct...

20060006462 - Method and apparatus for a semiconductor device having low and high voltage transistors: Method and apparatus for a semiconductor device including high voltage MOS transistors is described. A substrate is provided with a low voltage and a high voltage region separated one from the other. Isolation regions containing an insulator are formed including at least one formed within one of said wells within...

20060006464 - Method and system for providing a thin film with a controlled crystal orientation using pulsed laser induced melting and nucleation-initiated crystallization: Method and system for generating a metal thin film with a uniform crystalline orientation and a controlled crystalline microstructure are provided. For example, a metal layer is irradicated with a pulsed laser to completely melt the film throughout its entire thickness. The metal layer can then resolidify to form grains...

20060006463 - Nanowire device with (111) vertical sidewalls and method of fabrication: A nano-scale device and method of fabrication provide a nanowire having (111) vertical sidewalls. The nano-scale device includes a semiconductor-on-insulator substrate polished in a [110] direction, the nanowire, and an electrical contact at opposite ends of the nanowire. The method includes wet etching a semiconductor layer of the semiconductor-on-insulator substrate...

20060006466 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a support substrate, an insulation film provided on the support substrate, a rectangular silicon island provided on the insulation film, the rectangular silicon island having first side surfaces mutually opposed in a first direction and second side surfaces mutually opposed in a second direction perpendicular to...

20060006465 - Thin film transistor and method of fabricating the same: A thin film transistor and method of fabricating the same are provided. The thin film transistor is characterized in that low angle grain boundaries formed in a channel layer in a semiconductor layer pattern is tilted −15 to 15° with respect to a current flowing direction. The method includes: forming...

20060006467 - Transistor structure and circuit suitable for input/output protection of liquid crystal display device: A TFT structure and a circuit configuration, which are suitable, for example, for input/output protection of a liquid crystal display device, are provided. According to an embodiment of the invention, there is provided a TFT that includes a source region, a channel region and a drain region, which are formed...

20060006468 - Semiconductor device: A semiconductor device such as a DRAM memory device is disclosed. A substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconductor layer (16) has source (18) and drain (20)...

20060006469 - Method of fabricating cmos thin film transistor (tft) and cmos tft fabricated using the same: A method of fabricating a CMOS thin film transistor (TFT) and a CMOS TFT fabricated using the method involve provision of a substrate having a first region and a second region. A first semiconductor layer and a second semiconductor layer are formed on the first and second regions, respectively. A...

20060006470 - Mos field-effect transistor: A high-reliable depletion-type MOS field-effect transistor as a process monitor is provided. A diode formed in polycrystalline silicon and a diode formed in a semiconductor substrate form a bidirectional diode. The bi-directional diode connects a gate electrode with the semiconductor substrate in the depletion-type MOS field-effect transistor through metal wirings....

20060006472 - Phase change memory with extra-small resistors: A phase change memory cell comprises of multiple resistors. In one design, the resistor layer is a layer with a plurality of resistors embedded in an insulator layer which is sandwiched between the electrodes. In the other design, a combination of a heater layer with a plurality of heaters and...

20060006471 - Resistor with improved switchable resistance and non-volatile memory device: Provides a resistor with improved switchable resistance and non-volatile memory device. An example resistor includes a first electrode, a second electrode facing the first electrode and a resistance structure between the first electrode and the second electrode. The resistance structure includes an insulating dielectric material in which a confined switchable...

20060006473 - Integrated circuit hierarchical design system, integrated circuit hierarchical design program and integrated circuit hierarchical design method: An integrated circuit hierarchical design system for optimizing a circuit locating between flip-flops included in a lower layer through a higher layer among layers forming an integrated circuit, which shifts a layer section as a boundary between the higher layer and the lower layer that locates on the circuit to...

20060006474 - Semiconductor device: In an active region a pair of source/drain regions of an nMOS transistor is provided. Between the paired source/drain regions the semiconductor substrate has a region provided with a gate electrode layer with a gate oxide film interposed. The gate electrode layer extends on both the active region and an...

20060006475 - Fabrication of an eeprom cell with emitter-polysilicon source/drain regions: An EEPROM memory cell uses an emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage of the wells. The wells are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage...

20060006476 - Methods for the formation of fully silicided metal gates: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. Methods of forming the advanced gate structure are also provided....

20060006477 - Semiconductor device and fabrication method thereof: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in...

20060006478 - Semiconductor device and manufacturing method thereof: In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a...

20060006479 - Method and apparatus for increasing stability of mos memory cells: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number...

20060006480 - Semiconductor integrated circuit device: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting...

20060006481 - Method and structure for reducing resistance of a semiconductor device feature: A method used to form a semiconductor device comprises forming a polysilicon layer, forming a conductive barrier layer on the polysilicon layer, then forming a conductive nitride layer on the conductive barrier layer. Next, a conductive amorphous layer is formed on the conductive barrier layer, and an elemental metal layer...

20060006482 - Tfa image sensor with stability-optimized photodiode: The invention relates to a TFA image sensor with stability-optimized photodiode for converting electromagnetic radiation into an intensity-dependent photocurrent with an intermetal dielectric, on which, in the region of the pixel matrix, a lower barrier layer is situated and a conductive layer is situated on the barrier layer, and vias...

20060006484 - Functional material for micro-mechanical systems: A MEMS device includes a first material structure. A second material structure includes TiN. The second material structure is moveable relative to the first material structure....

20060006483 - Silicon microphone: A solid-state transducer is disclosed. The transducer comprises a semi-conductor substrate forming a support structure and having an opening. A thin-film structure forming a diaphragm responsive to fluid-transmitted acoustic pressure is disposed over the opening. The transducer further includes a plurality of semi-conductor supports and tangential arms extending from the...

20060006485 - Photonic crystal-based lens elements for use in an image sensor: The invention, in various exemplary embodiments, incorporates a photonic crystal lens element into an image sensor. The photonic crystal lens element comprises a substrate and a plurality of pillars forming a photonic crystal structure over the substrate. The pillars are spaced apart from each other. Each pillar has a height...

20060006487 - Chip package substrate having soft circuit board and method for fabricating the same: A chip package substrate having a soft circuit board jas a multi-layer soft and hard composite PCB, a plurality of conducting components and a plurality of conducting holes. The conducting holes are formed in the multi-layer soft and hard composite PCB. The conducting components are electroplated on the inner edges...

20060006486 - Image sensor package and method of manufacturing the same: An image sensor package assembling method includes providing a substrate on which a plurality of image sensors are mounted; providing a housing strip having a plurality of housings arranged corresponding to an arrangement of the image sensors on the substrate, each of the housings having an aperture corresponding to an...

20060006488 - Solid-state imaging device, camera and method of producing the solid-state imaging device: To provide a back-illuminated solid-state imaging device able to suppress a crystal defect caused by a metal contamination in a process and to suppress a dark current to improve quantum efficiency, a camera including the same and a method of producing the same, having the steps of forming a structure...

20060006489 - Image sensor having self-aligned and overlapped photodiode and method of making same: An image sensing device includes a gate dielectric layer formed on a substrate and a transfer gate formed on the gate dielectric layer. A masking layer is formed on the transfer gate, the masking layer having a width smaller than a width of the transfer gate, such that a portion...

20060006490 - Method of fabricating a semiconductor device: A semiconductor device capable of moderating concentration of surge current and thereby improving surge voltage resistance is proposed, the device comprising a P-well 12 formed by diffusing an impurity into a P+-type semiconductor substrate 10; an outer peripheral P+-type diffusion layer 14 formed by diffusing an impurity along the outer...

20060006491 - Circuit for adjusting the operating point of multiple gate field effect transistors: An amplifier circuit includes a first multiple gate field-effect transistor having a source terminal, a drain terminal, at least one signal gate terminal for receiving an input signal and at least one control gate terminal for receiving a control signal, and a second multiple gate field-effect transistor having a source...

20060006492 - Method for manufacturing non-volatile semiconductor memory device, and non-volatile semiconductor memory device: An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films....

20060006493 - Semiconductor chip and method for manufacturing the same and semiconductor device: The semiconductor chip 1 has a semiconductor substrate 10. In the present embodiment, the semiconductor substrate 10, which is an SOI substrate, is constituted by comprising a support substrate 12, an insulating layer 14 formed on the support substrate 12 with a layered structure, and a silicon layer 16 formed...

20060006494 - Electrically programmable polysilicon fuse with multiple level resistance and programming: A method to form a programmable resistor device in an integrated circuit device is achieved. The method comprises depositing a semiconductor layer overlying a substrate. The semiconductor layer is patterned to form a plurality of lines. The lines are electrically parallel between a first terminal and a second terminal. Any...

20060006495 - Ultrathin chemically grown oxide film as a dopant diffusion barrier in semiconductor devices: The invention is a chemically grown oxide layer which prevents dopant diffusion between semiconductor layers. The chemically grown oxide layer may be so thin that it does not form a barrier to electrical conduction, and thus may be formed within active devices such as diodes or bipolar transistors. Such a...

20060006497 - Capacitors having doped aluminum oxide dielectrics: Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum...

20060006496 - Interdigitaded capacitors: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner...

20060006498 - Bipolar transistor with geometry optimized for device performance, and method of making same: The present invention is generally directed to bipolar transistors with geometry optimized for device performance and various methods of making same. In one illustrative embodiment, the device includes a substrate, an intrinsic base region formed in the substrate, a continuous emitter region formed within the intrinsic base region, the emitter...

20060006499 - Controlling diffusion in doped semiconductor regions: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first...

20060006500 - Iii-nitride materials including low dislocation densities and methods associated with the same: Semiconductor structures including one, or more, III-nitride material regions (e.g., gallium nitride material region) and methods associated with such structures are provided. The III-nitride material region(s) advantageously have a low dislocation density and, in particular, a low screw dislocation density. In some embodiments, the presence of screw dislocations in the...

20060006501 - Semiconductor device: A semiconductor device 1 has a semiconductor chip 10. The semiconductor chip 10 is constituted as having a semiconductor substrate 12 and an interlayer insulating film 14 on the semiconductor substrate 12. The semiconductor substrate 12 has a plurality of through electrodes 22 (first through electrodes) and a plurality of...

20060006502 - Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semiconductor device: A hard mask comprising boron-doped amorphous carbon, and a method for forming the hard mask, provides improved resistance to etches of a variety of materials compared with previous amorphous carbon hard mask layers....

20060006503 - Insulative coatings for apertures of semiconductor device components and semiconductor device components including insulative coatings: An insulative coating for an aperture of a semiconductor device component includes a plurality of adjacent, mutually adhered regions. The adjacent, mutually adhered regions may be formed by programmed material consolidation processes, such as stereolithography. Such an insulative coating may electrically isolate conductive features, such as conductive vias, from the...

20060006505 - Lead frame for improving molding reliability and semiconductor package with the lead frame: A lead frame for improving molding reliability and a semiconductor package with the lead frame are proposed. At least one embossed structure, such as a metal bump or recessed portion, is formed on a bonding layer of a wire-bonding area of the lead frame. At least one semiconductor chip is...

20060006504 - Multilayer leadframe module with embedded passive component and method of fabricating the same: A multilayer leadframe module with embedded passive components and method of fabricating the same. The leadframe, comprising opposite first and second surfaces, includes an active device base exposed on the first and second surfaces, a trace line, exposed on the first surface, beyond the active device base, a contact pad,...

20060006506 - Semiconductor device and method of manufacturing same: A semiconductor device comprises: a semiconductor chip; a first frame; a solder layer which bonds the solder bonding metal layer of the semiconductor chip and the first frame; and a second frame bonded to the rear face of the semiconductor chip. The semiconductor chip includes: a semiconductor substrate; a first...

20060006507 - Silicon building block architecture with flex tape: An apparatus is constituted with an integrated circuit and a flex tape coupled to the integrated circuit. The flex tape is employed to facilitate ingress/egress of signals to/from the integrated circuit. In one embodiment, the flex tape includes a plurality of signal-traces. In another embodiment, the apparatus also includes a...

20060006508 - Semiconductor device in which semiconductor chip is mounted on lead frame: A semiconductor device including a lead frame having a plurality of inner leads having end portions and a plurality of outer leads integrated with the inner leads, the inner leads having first surfaces and second surfaces which are opposite to the first surfaces, first plating provided at the end portions...

20060006510 - Plastic encapsulated semiconductor device with reliable down bonds: Plastic encapsulated semiconductor devices having elevated topographical features on the chip mount pad to control the extent of delamination at the plastic to substrate interface, thereby allowing reliable down bond sites to be formed on the top surface of the chip mount pad which may serve as a ground plane....

20060006509 - Semiconductor device: This is a semiconductor apparatus capable of realizing a sharing of parts without introducing enlargement of the apparatus and deterioration in reliability of the wire bonding in case of responding to various electronic circuits. It is a semiconductor laser apparatus configured to include a housing (1) in which device mounting...

20060006512 - Hydrogen diffusion hybrid port and method of making: A hydrogen diffusion port for use in a packaged electronic device. In one embodiment, the hydrogen window is characterized by a substantial absence of plating from the external surfaces of the cover the base. The hydrogen diffusion port is selected from the group of materials consisting of palladium and its...

20060006513 - Interposers and other carriers including a slot with laterally recessed area at an end thereof and semiconductor device assemblies and packages including such carriers: An interposer includes a substantially planar substrate with a slot therethrough. The slot includes a laterally recessed area in only a portion of a periphery thereof at a location that exposes at least a portion of an active surface of the semiconductor die located between a bond pad and an...

20060006511 - Ultrathin module for semiconductor device and method of fabricating the same: An ultrathin module is provided for special types of semiconductor devices such as image sensor devices and micro-electro-mechanical system (MEMS) devices. In the module, a chip cover is directly attached to a semiconductor chip so as to protect a light-sensing area or mechanical elements of the chip. The chip cover...

20060006515 - Conical housing: A conical diode device is disclosed, comprising a pair of electrodes and a conical housing. The conical housing ensures that the hermetic seal between the electrodes and the housing remains strong despite thermal imbalances between the two electrodes when the device is in operation. In one embodiment, the conical housing...

20060006514 - Interconnecting integrated circuits using mems: A semiconductor device comprises a plurality of integrated circuits and at least one MEMS device interconnecting the integrated circuits for signal transmission between the circuits....

20060006519 - Castellation wafer level packaging of integrated circuit chips: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When...

20060006517 - Multi-chip package having heat dissipating path: A multi-chip package having a heat dissipating path. The multi-chip package includes a stack of integrated circuit (IC) chips, a heat sink part interposed between the IC chips so that one end portion of the heat sink part can be exposed from a side of the stack of integrated circuit...

20060006518 - Semiconductor component having stacked, encapsulated dice and method of fabrication: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching...

20060006516 - Stacked semiconductor device and semiconductor memory module: A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless manner, and each of the plurality of stacked semiconductor devices comprises...

20060006520 - Semiconductor component and system having back side and circuit side contacts: A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor die having a pattern of die contacts, and conductive members formed by filled openings in the die contacts and the die. In addition, the pin contacts are formed...

20060006521 - Semiconductor device assemblies and packages with edge contacts and sacrificial substrates and other intermediate structures used or formed in fabricating the assemblies or packages: A sacrificial for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device,...

20060006522 - Forming dual metal complementary metal oxide semiconductor integrated circuits: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of...

20060006523 - Molded package for micromechanical devices and method of fabrication: According to the present invention, a plastic land-grid array package, a plastic ball-grid package, and a plastic leaded package for micromechanical components are fabricated by a molding process characterized by placing a sheet-like protector on the surface of the components during the molding phase, selectively encapsulating the bonding pads and...

20060006524 - Light emitting diode having an adhesive layer formed with heat paths: The present invention is related to a light emitting diode having an adhesive layer provided with heat paths. In the present invention, an adhesive layer is formed to bond the substrate and the LED stack. There are a plurality of metal protrusions or semiconductor protrusions passing through the adhesive layer...

20060006525 - System and method for dissipating heat from a semiconductor module: The system includes a circuit board, a semiconductor module, a heat dissipator, and at least one thermal via. The circuit board has substantially flat opposing first and second sides. The semiconductor module includes multiple semiconductor devices. The semiconductor module is oriented substantially parallel to the circuit board near the first...

20060006526 - Thermal interposer for cooled electrical packages: The specification describes electrical assemblies comprising actively cooled components wherein a thermal interposer is used to limit heat transfer between the ambient and the cooled components. The thermal interposer is effective for transmitting signals for both power/ground and RF. Structurally, the thermal interposer comprises thin conductors in various configurations that...

20060006527 - Audio sound quality enhancement apparatus and method: An audio enhancement apparatus includes a thermally insulating container and a substrate mounted at least partially within the thermally insulating container. A heat source is provided within the thermally insulating container and proximate to the substrate. At least one audio semiconductor is mounted to the substrate, where the audio semiconductor...

20060006528 - Semiconductor chip having pollished and ground bottom surface portions: A semiconductor chip having a thickness of 130 micrometers or less includes a mechanically ground bottom surface corresponding to a central circuit area, and a polished bottom surface corresponding to a peripheral scribe area. The mechanically ground bottom surface prevents heavy metals attached onto the bottom surface of the wafer...

20060006530 - Semiconductor device and manufacturing method therefor: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or...

20060006529 - Semiconductor package and method for manufacturing the same: A semiconductor package positioned on a first substrate includes a second substrate having a first surface and a second surface, a chip positioned on the first surface of the second substrate, a plurality of first bonding balls positioned on the second surface of the second substrate and arranged in a...

20060006531 - Bonding pad and chip structure: A chip structure and a bonding pad are provided. The chip structure comprises a chip and at least a bonding pad. The chip has an active surface. The bonding pad is disposed on the active surface of the chip. The bonding pad comprises a polygonal body and a plurality of...

20060006532 - Flip-chip without bumps and polymer for board assembly: A semiconductor chip having a planar active surface including an integrated circuit protected by an inorganic overcoat; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent...

20060006534 - Microelectronic devices and methods for packaging microelectronic devices: Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of microelectronic dies to a support member, covering the dies and at least a portion of the support member with a dielectric layer, forming a plurality...

20060006533 - Motherboard structure for preventing short circuit: A motherboard for preventing short circuit includes an IC device and a PCB. The IC device has a plurality of tin balls, and the PCB has matching pads with the tin balls of the IC device. The tin balls and the pads knit together to mount the IC device to...

20060006535 - Selective plating of package terminals: In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the...

20060006536 - Bga package and manufacturing method: In the ball grid array (BGA) package and its manufacturing method, an open region of a bonding pad is etched to a depth reaching below the solder mask to give an etched portion which is planar at the bottom center and slanted at the periphery. With this structure of the...

20060006537 - Conductive line structure: A conductive line Structure. In one embodiment of the invention, a conductive line includes at least two outer conductive portions, an inner conductive portion between the outer conductive portions, separated from the outer conductive portions by at least two trenches along the conductive line, and at least one connecting portion...

20060006538 - Extreme low-k interconnect structure and method: Embodiments of the invention include an extreme low-K circuit structure formed on a substrate having a plurality of electrically conductive structures. A lattice structure of bracing material configured to support the electrically conductive structures is formed on the substrate and also can define regions of extreme low-K dielectric space between...

20060006540 - Organic light emitting display having improved via hole: An organic light emitting display including a semiconductor layer formed on a substrate, a first insulating layer formed on the substrate and including a contact hole, an electrode formed on the first insulating layer and coupled to the semiconductor layer through the contact hole, a second insulating layer formed on...

20060006539 - Semiconductor device and semiconductor module employing thereof: A semiconductor device 100 is provided with a silicon substrate 101 and a structure 120 filled in a through hole that has a rectangular cross section and extends through the silicon substrate 101. The structure 120 comprises a pipe-shaped through electrode 103, stripe-shaped through electrodes 107, silicons 105, a first...

20060006541 - Organic silica-based film, method of forming the same, composition for forming insulating film for semiconductor device, interconnect structure, and semiconductor device: A method of forming an organic silica-based film, including: applying a composition for forming an insulating film for a semiconductor device, which is cured by using heat and ultraviolet radiation, to a substrate to form a coating; heating the coating; and applying heat and ultraviolet radiation to the coating to...

20060006542 - Semiconductor device and method for manufacturing the same: Enhanced step coverage and reduced resistivity of a TaSiN layer may be achieved when a semiconductor device is manufactured by: forming an interlayer insulating layer on a semiconductor substrate, the interlayer insulating layer having a contact hole that partially exposes the substrate; depositing a TaN thin film on the interlayer...

20060006543 - Semiconductor device: A reliable semiconductor device having a multilayer wiring structure formed of copper as a main component material, which constrains occurrence of voids caused by stress migration. In the multilayer wiring structure, a first insulation layer having a high barrier property and a compression stress, and making contact with the upper...

20060006544 - Method of forming a micro solder ball for use in c4 bonding process: A method of forming micro solder balls for use in a C4 process is described. The solder balls are formed by laying down a peel-away photoresist layer, forming holes in the photoresist layer to expose electrical contacts, depositing a solder layer over the photoresist, forming solder areas in the holes...

20060006548 - H2 plasma treatment: Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive layer to a H2 plasma treatment, and depositing a capping...

20060006546 - Method for improved process latitude by elongated via integration: Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a...

20060006547 - Semiconductor device and a method of manufacturing the semiconductor device: A semiconductor device includes first level wires; a low-dielectric constant film on the first level wires; first flat vias embedded in the low-dielectric constant film connected to the first level wires, each via having a first length in a longitudinal direction of the first level wires and a second length...

20060006545 - [semiconductor structure and fabrication therefor]: A semiconductor structure and a method of fabrication there-for are provided. The semiconductor structure comprises a substrate, a dielectric layer disposed over the substrate, a hydrophilic material layer disposed over the dielectric layer, and a hardmask layer disposed over the hydrophilic material layer. It is noted that, the edge of...

20060006549 - Stacked structure of integrated circuits: A stacked structure of integrated circuits includes a substrate, a lower integrated circuit, a space layer, an upper integrated circuit, and a compound resin. The substrate has an upper surface on which a plurality of signal input terminals are formed at one side of the upper surface, and a lower...

20060006550 - Substrate based unmolded package: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and...

20060006551 - Method for fabricating semiconductor component with adjustment circuitry for electrical characteristics or input/output configuration: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors...

20060006552 - Bond pad structure for copper metallization having increased reliability and method for fabricating same: According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the...

20060006553 - Electronic device package: An electronic device package is described that includes a non-metal die attached adhesive. The die attach is positioned in discrete positions on a surface to which the die will be fixed. The die is placed on the discrete die attach. The die attach, in an embodiment, is an epoxy resin...

20060006554 - Vertical structure semiconductor devices with improved light output: The invention provides a reliable technique to fabricate a new vertical structure compound semiconductor devices with highly improved light output. An exemplary embodiment of a method of fabricating light emitting semiconductor devices comprising the steps of forming a light emitting layer, and forming an undulated surface over light emitting layer...

20060006555 - Process for resurf diffusion for high voltage mosfet: A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusion step so that the...

20060001016 - Initializing phase change memories: A thin film phase change memory may be provided with a layer which changes between amorphous and crystalline states. The threshold voltage of that layer may be increased in a variety of fashions. As a result of the threshold increase, it is possible to transition cells, initially fabricated in the...

20060001017 - Phase-change random access memory device and method for manufacturing the same: Disclosed are a phase-change random access memory device and a method for manufacturing the same by performing a photolithography process using electronic beam. The phase-change random access memory device includes a first insulation layer having first contact holes and a second contact hole, conductive plugs for filling the first contact...

20060001018 - Iii-v and ii-vi compounds as template materials for growing germanium containing film on silicon: An assembly comprising a semiconductor substrate having a first lattice constant, an intermediate layer having a second lattice constant formed on the semiconductor substrate, and a virtual substrate layer having a third lattice constant formed on the intermediate layer. The intermediate layer comprises one of a combination of III-V elements...

20060001019 - Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same: A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between the conductive plug and the oxidation resistant layer....

20060001020 - Method of forming a self-assembled molecular layer: A method includes chemically bonding a polymeric material to a self-assembled molecular film that is chemically bonded to a surface of a substrate. The self-assembled molecular film includes one or more defect sites and a plurality of active device molecules, each of the plurality of active device molecules including a...

20060001021 - Multiple semiconductor inks apparatus and method: A semiconductor device can be comprised of a substrate having a plurality of different printable semiconductor inks formed thereon. In a preferred approach at least some of these printable semiconductor inks comprise organic semiconductor material inks. These semiconductor inks can vary from one another with respect to various properties including...

20060001022 - Methods for making nearly planar dielectric films in integrated circuits: In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the insulative layers sandwiched between layers of metal wiring—in integrated circuits. Accordingly, the inventor devised several methods...

20060001024 - Display device, method of production of the same, and projection type display device: A display device able to raise a light resistance of pixel transistors without depending upon a light shielding structure and a method of production of same, wherein an average crystal grain size of a polycrystalline silicon film 111 forming an active layer of the pixel transistors is controlled to be...

20060001023 - Method of manufacturing active matrix substrate with height control member: An active matrix substrate comprises a substrate, a plurality of adhesion parts provided on the substrate so as to have substantially the same height, and a plurality of active elements provided on the plurality of adhesion parts, respectively, each of the plurality of adhesion parts including a height control member...

20060001025 - Semiconductor device and method for fabricating the same: A semiconductor device in which a semiconductor layer of a thin film transistor and a first electrode of a capacitor are formed of amorphous silicon and the whole or a part of source/drain regions of the semiconductor layer and the first electrode of the capacitor are crystallized by a metal...

20060001026 - Semiconductor device and method of manufacturing the same: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating...

20060001027 - Liquid crystal display device and method of fabricating the same: A liquid crystal display device and a method of fabricating the same are disclosed in the present invention. The liquid crystal display device includes a gate line and a data line crossing each other on a-substrate, a pixel electrode at an area defined by the gate line and the data...

20060001029 - Diamond sensor: A diamond element is mounted on an insulating base material having a thickness of not more than 3 mm provided with one pair of metal interconnects. In the diamond element, an insulating diamond layer to act as a detection layer is deposited on a substrate, and one pair of interdigitated...

20060001028 - Method for the treatment of a surface of a metal-carbide substrate for use in semiconductor manufacturing processes as well as such a metal-carbide substrate: The invention relates to a method for the treatment of a surface of a metal-carbide substrate, said metal-carbide substrate being used in semiconductor manufacturing processes. The invention also relates to a metal-carbide substrate for use in semiconductor manufacturing processes treated with to the method according to the invention. According to...

20060001031 - Light emitting element and method of making same: A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (AlXInYGa(1−X−Y))2O3 where 0≦x≦1, 0≦y≦1 and 0≦x+y≦1. The pn-junction has first conductivity type substrate, and GaN system compound semiconductor thin film of second conductivity type opposite...

20060001030 - Light-emitting diode: An LED comprising a circuit board, a connecting electrode unit provided on the circuit board, a reflective cup provided within the circuit board, an LED element disposed in the reflective cup and connected to the connecting electrode unit, and a resin with which the reflective cup is filled, a fluorescent...

20060001032 - Light-emitting semiconductor device and method of fabrication: An LED comprises a semiconductor region including an active layer for generating light. An anode is arranged centrally on one of the opposite major surfaces of the semiconductor region from which is emitted the light. A reflective metal layer is bonded to the other major surface of the light-generating semiconductor...

20060001033 - Image display: An image display according to one aspect of the present invention includes a light emitting unit that is located in each unit pixel area in each, emits light corresponding to an injected electric current, and includes a plurality of light emitting layers which are horizontally divided into. The plurality of...

20060001034 - Rgb light emitting diode package with improved color mixing properties: Disclosed is an RGB light emitting diode package with improved color mixing properties. The RGB light emitting diode package includes red, green, and blue light emitting diode chips provided on a reflector, on which elements are to be installed or mounted. A photomixing material and a filler resin scatters rays...

20060001035 - Light emitting element and method of making same: A light emitting element has: a semiconductor layer having a light-emitting layer; a first electrode; a second electrode; an insulation layer that is formed on a mounting face side of the semiconductor layer; and a first terminal and a second terminal that are formed on a surface of the insulation...

20060001036 - Led-based edge lit illumination system: An edge lit illumination system is directed to providing backlighting utilizing a luminescent impregnated lightguide. The apparatus includes an LED radiation source providing a first radiation and a lightguide optically coupled to the LED radiation source including a luminescent material embedded or coated on an output surface of the lightguide...

20060001038 - Manufacture of a layer of optical interconnection on an electronic circuit:

20060001037 - Phosphor based illumination system having a plurality of light guides and a display using same: An illumination system including a light source, light guides coupled to the light source, each including an input surface and an output surface, emissive material positioned to receive light from at least one light guide, and a first interference reflector positioned between the emissive material and the output surfaces of...

20060001040 - High integrity protective coatings: A composite article with at least one high integrity protective coating, the high integrity protective coating having at least one planarizing layer and at least one organic-inorganic composition barrier coating layer. A method for depositing a high integrity protective coating....

20060001039 - Method of forming buried channels and microfluidic devices having the same: A method of manufacturing an integrated device that includes filling at least one channel region of a substrate with a sacrificial material to form a filled channel, forming an encapsulating layer over the filled channel, forming an aperture in the encapsulating layer, and selectively removing the sacrificial material in the...

20060001042 - Epitaxial wafer for semiconductor light-emitting devices, and semiconductor light-emitting device: An epitaxial wafer for semiconductor light-emitting devices has an n-type substrate, on which are sequentially formed an n-type cladding layer, an active layer, a p-type cladding layer having Mg as a p-type dopant, and a p-type cap layer. The p-type cap layer has at least two Mg-doped and Zn-doped layers...

20060001041 - Organic light emitting device: An organic light emitting device includes a substrate, an array of organic light emitting diodes mounted on the substrate, a cover disposed over the organic light emitting diodes and having a light transmittable region confronting the array of the organic light emitting diodes and an encompassing region around the light...

20060001043 - Cmos image sensor and fabricating method thereof: A CMOS image sensor and fabricating method thereof are disclosed, by which a dark current can be reduced. The present invention includes a first conductive type semiconductor substrate divided into an active area and a field area, an STI layer formed in the field area to divide the first conductive...

20060001044 - Method for manufacturing compound semiconductor wafer and compound semiconductor device: A method for producing a compound semiconductor wafer used for production of HBT by vapor growth of a sub-collector layer, a collector layer, a base layer and an emitter layer in this turn on a compound semiconductor substrate using MOCVD method wherein the base layer is grown as a p-type...

20060001045 - Integrated circuit structures for increasing resistance to single event upset: A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder...

20060001047 - Integrated circuit well bias circuitry: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The...

20060001046 - Led with substrate modifications for enhanced light extraction and method of making same: The surface morphology of an LED light emitting surface is changed by applying a reactive ion etch (RIE) process to the light emitting surface. Etched features, such as truncated pyramids, may be formed on the emitting surface, prior to the RIE process, by cutting into the surface using a saw...

20060001048 - Power delivery using an integrated heat spreader: An integrated heat spreader (IHS) having a groove and a cavity formed therein is disclosed. In one embodiment, the groove has an insulating layer formed therein, and a power conduit is mounted in the groove, the power conduit is electrically isolated from the IHS by the insulating layer, and the...

20060001049 - Service programmable logic arrays with low tunnel barrier interpoly insulators: Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and columns that are interconnected to produce a number of...

20060001052 - Dual-sided capacitor and method of formation: A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be...

20060001050 - High voltage fet gate structure: A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second...

20060001051 - Thin film semiconductor circuit, manufacturing method thereof, and image display apparatus utilizing the same thin film semiconductor circuit: Agglomeration of a polycrystalline silicon film is eliminated at the time of obtaining a high quality polycrystalline silicon film by forming a silicon layer on an insulating film substrate and conducting long-term melting and re-crystallization. For this purpose, a layer or a plurality of layers of an underlayer UCL are...

20060001053 - Method and apparatus transporting charges in semiconductor device and semiconductor memory device: A conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, voltage-divider function, and mass-filtering function to charge-carriers flows. The conductor-insulator system provides Image-Force barrier lowering effect to collect charge-carriers. The charge-injection system includes the conductor-filter system and the conductor-insulator...

20060001054 - Semiconductor processing method and field effect transistor: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with...

20060001055 - Led and fabrication method of same: An LED can include a silicon substrate and a pair of electrodes formed inside a horn that is formed on the silicon substrate by anisotropic etching. The LED can include an LED chip mounted inside the horn, the LED chip being electrically connected to the pair of electrodes. A resin...

20060001056 - Led with substrate modifications for enhanced light extraction and method of making same: The surface morphology of an LED light emitting surface is changed by applying processes, such as a reactive ion etch (RIE) process to the light emitting surface. In one embodiment, the changed surface morphology takes the form of a moth-eye surface. The surface morphology created by the RIE process may...

20060001057 - Schottky device and method of forming: A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the first conductivity type. A third region of the...

20060001058 - Fin field effect transistor memory cell: A fin field effect transistor memory cell having a first and a second source/drain region, a gate region, a semiconductor fin having a channel region between the first and the second source/drain region, a charge storage layer configured as a trapping layer arranged at least partly on the gate region,...

20060001062 - Method for fabricating cmos image sensor: A method for fabricating a CMOS image sensor is disclosed, to minimize the leakage current and to improve the yield, which includes the steps of preparing a semiconductor substrate including a peripheral circuit and a pixel array, wherein the pixel array is comprised of a photodiode and a readout circuit;...

20060001060 - Pixel cell with a controlled output signal knee characteristic response: A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have the gate profile of a transfer gate or a reset gate. The HDR transistor may be located on a side of the photodiode...

20060001061 - Solid-state image-sensing device and camera provided therewith: By feeding an appropriate voltage as a signal φTX to a transfer gate TG, a MOS transistor T1 , is operated in a threshold region. A potential linearly or natural logarithmically converted by a buried photodiode PD is transferred to an N-type floating diffusion layer FD so as to be...

20060001059 - Transparent conductor based pinned photodiode: A pinned photodiode with improved short wavelength light response. In exemplary embodiments of the invention, a gate oxide is formed over a doped, buried region in a semiconductor substrate. A conductor is formed on top of the gate oxide. The gate conductor is transparent, and in one embodiment is a...

20060001063 - Capacitor of semiconductor device and method of manufacturing the same: A MIM capacitor includes a lower electrode disposed on a semiconductor substrate. A dielectric layer is disposed on the lower electrode to completely cover an exposed surface of the lower electrode. An upper electrode is disposed on the dielectric layer. A method for forming a MIM capacitor includes forming a...

20060001064 - Methods for the lithographic deposition of ferroelectric materials: The invention is directed toward a photoresist-free method for depositing films comprising ferroelectric materials from metal complexes. More specifically, the method involves applying an amorphous film of a metal or metal oxide complex to a substrate. The metal complexes have the general formula MaM′bLcL′d, wherein M and M′ are independently...

20060001065 - Alignment key structures in semiconductor devices including protected electrode structures and methods of fabricating the same: An integrated circuit device includes a storage cell including an upper electrode and a lower electrode on a substrate, and a conductive hard mask pattern directly on the upper electrode of the storage cell opposite the lower electrode. The upper electrode is formed of a metal softer than the conductive...

20060001066 - Semiconductor constructions: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is...

20060001067 - Fabrication method for a semiconductor structure having integrated capacitors and corresponding semicomductor structure: The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The fabrication method has the following steps of: providing a semiconductor substrate (1; 1′, 60, 1″) having a front side (VS) and a rear side (RS); providing trenches (5) in the...

20060001069 - Composition for forming dielectric layer, mim capacitor and process for its production: To provide a composition for forming a dielectric layer excellent in dielectric constant and withstand voltage properties, a MIM capacitor and a process for its production. A composition for forming a dielectric layer, which comprises fine particles of perovskite type dielectric crystal, glass frit, and a hydrolysable silicon compound or...

20060001068 - Multi-layer capacitor using dielectric layers having differing compositions: The present disclosure describes an embodiment of an apparatus comprising a first dielectric layer having a first variation of capacitance with temperature, a second dielectric layer having a second variation of capacitance with temperature, the second variation of capacitance with temperature being different than the first variation of capacitance with...

20060001070 - Capacitor of a memory device and fabrication method thereof: A capacitor of a memory device, and a method of fabricating the same, includes a lower electrode electrically coupled to a doping region of a transistor structure, the lower electrode having a metal electrode and a metal oxide electrode, a ferroelectric layer covering and extending laterally along the lower electrode,...

20060001071 - Forming high-k dielectric layers on smooth substrates: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition....

20060001072 - Methods of forming a gated device: This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a...

20060001074 - Three dimensional flash cell: A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures....

20060001073 - Use of voids between elements in semiconductor structures for isolation: A flash EEPROM or other type of memory cell array having adjacent charge storage elements is formed with a gas filled void between them in order to reduce the level of capacitive coupling between storage elements, thus reducing cross-coupling between charge storage elements and resulting errors occurring in the data...

20060001075 - Charge trapping memory device with two separated non-conductive charge trapping inserts and method for making the same: A charge trapping memory device with two separated non-conductive charge trapping inserts is disclosed. The charge trapping memory device has a silicon substrate with two junctions. A gate oxide (GOX) is formed on top of the silicon substrate and between the two junctions. A polysilicon gate is defined over the...

20060001079 - Electronic systems having doped aluminum oxide dielectrics: Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum...

20060001078 - Method for fabricating nand type dual bit nitride read only memory: A NAND type dual bit nitride read only memory and a method for fabricating thereof are provided. Firstly, a plurality of isolation layers, which are spaced and parallel to each other are formed in the substrate. Next, a plurality of word lines and a plurality of oxide-nitride-oxide (ONO) stack structures...

20060001076 - Semiconductor device and method of manufacturing the same: Disclosed is a semiconductor device having a plurality of memory cells arranged in a first direction and a second direction perpendicular to the first direction, each memory cell comprising a first insulating film formed on a semiconductor substrate, a floating gate formed on the first insulating film, a second insulating...

20060001077 - Split gate type flash memory device and method of manufacturing the same: In a split gate type flash memory device, and a method of manufacturing the same, the device includes a memory cell array having a memory cell uniquely determined by a contact of a corresponding bit line and a corresponding word line, a floating gate formed on a semiconductor substrate to...

20060001080 - Write once read only memory employing floating gates: Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate transistor has a first source/drain region, a second source/drain region,...

20060001082 - Floating-gate field-effect transistors having doped aluminum oxide dielectrics: Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum...

20060001081 - Nonvolatile semiconductor memory device and manufacturing method thereof: A leakage current flowing between data lines of a nonvolatile semiconductor memory is reduced. In a memory array of a nonvolatile semiconductor memory device having an AND type flash memory, a concave portion is formed in a junction isolation area between adjacent word limes and between adjacent assist gate wirings...

20060001083 - Scalable flash/nv structures and devices with extended endurance: Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K...

20060001084 - Power semiconductor devices: A vertical insulated gate field effect power transistor (3) has a plurality of parallel transistor cells (TC3) with a peripheral gate structure (G31, G2) at the boundary between each two transistor cells (TC3). The gate structure (G31, G32) comprises first (G31) and second (G32) gates isolated from each other so...

20060001085 - Lateral semiconductor device using trench structure and method of manufacturing the same: A lateral trench MOS transistor is provided in which trenches extending to the source and drain regions are disposed parallel to the gate length direction, agate oxide is disposed on the trenches, a well is disposed under the trench region and the source and drain regions by using oblique ion...

20060001086 - Drain-extended mos transistors and methods for making the same: Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon...

20060001087 - Native high-voltage n-channel ldmosfet in standard logic cmos: A native high-voltage n-channel LDMOSFET includes a p− doped substrate, a first n+ doped region disposed in the p− doped substrate, a source terminal coupled to the first n+ doped region, an n− well disposed in the substrate, a second n+ doped region disposed in the n− well, a drain...

20060001094 - Semiconductor on insulator structure: An apparatus and a method for forming the apparatus include a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to that of the semiconductor layer. The semiconductor layer can also be formed...

20060001093 - Silicon-on insulator (soi) substrate having dual surface crystallographic orientations and method of forming same: A method is provided of forming a silicon-on-insulator (SOI) substrate having at least two exposed surface crystal orientations. The method begins by providing an SOI substrate having a first silicon layer with a surface having a first crystal orientation located on a first buried oxide layer. The buried oxide layer...

20060001090 - Soi substrate and method for manufacturing the same: The SOI substrate 1 has a supporting substrate 10, an insulating layer 20 formed on the supporting substrate 10 and a silicon layer 30 formed on the insulating layer 20. A through electrode 40 is provided in a device formation region A1 of the SOI substrate 1. The through electrode...

20060001088 - Strained si mosfet on tensile-strained sige-on-insulator (sgoi): A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate comprising a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer...

20060001092 - Thin film transistor (tft) and flat panel display including tft: A Thin Film Transistor (TFT) includes: an active layer including a channel region, a source region, and a drain region; a gate electrode insulated from the active layer and adapted to supply a signal to the channel region; and a source electrode and a drain electrode, insulated from the gate...

20060001091 - Thin film transistor (tft) and flat panel display including the tft and their methods of manufacture: A Thin Film Transistor (TFT) reduces interconnection resistance of source/drain electrodes, prevents contamination from an active layer, reduces contact resistance between a pixel electrode and the source/drain electrodes, smoothly supplies hydrogen to the active layer and has high mobility, on-current characteristics, and threshold voltage characteristics The TFT includes an active...

20060001089 - Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present...

20060001095 - Ultra thin body fully-depleted soi mosfets: A method of creating ultra tin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen...

20060001096 - Photodetector using mosfet with quantum channel and manufacturing method thereof: The present invention relates to a photodetector using MOSFET with quantum channels and a method for making thereof. A photodetector using MOSFET with quantum channels according to the present invention comprises a quantum channel formed on an activated SOI wafer, a gate oxide film covering said quantum channel; a gate...

20060001098 - Electrostatic discharge protection device: An electrostatic discharge (ESD) protection device for protecting an internal circuit includes a first ESD current unit and a second ESD current unit. The first ESD current unit is electrically connected between the internal circuit and a high source voltage for transmitting a discharging current to the high source voltage....

20060001100 - Method for simulating electrostatic discharge protective circuit: A method for simulating an electrostatic discharge protective circuit replaces an electrostatic discharge protective element having an insulated-gate field-effect transistor having a source and a drain with an equivalent circuit including the insulated-gate field-effect transistor, a bipolar transistor, a current source, a diode, and a substrate resistance. Then, the method...

20060001099 - Reverse-connect protection circuit with a low voltage drop: Current supply circuit for supplying a circuit with an internal supply voltage on the basis of an external supply voltage with an bipolar transistor for realizing reverse-connect protection for the circuit to be supplied, a supply current flowing through the bipolar transistor's collector-emitter path, a regulating circuit connected to the...

20060001101 - Semiconductor device: A semiconductor device has a supply pad to which a supply voltage is fed, a supply conductor that is electrically connected to the supply pad, an input/output pad via which a signal is fed in from outside or fed out to outside, an electrostatic protection device that is electrically connected...

20060001097 - Semiconductor device and manufacturing method of the same: A protection transistor which protects an internal transistor in an internal circuit from breakage due to static electricity occurring between power supply pads is provided. A conductivity type of a first p-well constructing a channel of the protection transistor corresponds to a conductivity type of a second p-well constructing a...

20060001102 - Drain-extended mos transistors and methods for making the same: Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon...

20060001103 - Interconnect structure in integrated circuits: A device includes an interconnect structure having a number of circuit paths to transfer signals. The circuit paths transfer the signals at different speed to reduce the coupling capacitance effect between adjacent circuit paths....

20060001105 - Semiconductor device having optimized shallow junction geometries and method for fabrication thereof: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that...

20060001104 - Semiconductor device having sti with nitride liner: A semiconductor device has: a silicon substrate; trench formed downward from the surface of the silicon substrate, the trench defining active regions on the surface of the silicon substrate; a first liner layer of a silicon nitride film covering an inner wall of the trench; a second liner layer of...

20060001106 - Using different gate dielectrics with nmos and pmos transistors of a complementary metal oxide semiconductor integrated circuit: Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a replacement process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples....

20060001107 - Transistor including an active region and methods for fabricating the same: A transistor including an active region and methods thereof. The active region may include corners with at least one of a rectangular, curved or rounded shape. The methods may include isotropically etching at least a portion of the active region such that the portion includes a desired shape....

20060001108 - Semiconductor device and method for manufacturing the same: After formation of a gate insulating film for a high voltage transistor on the entire surface, when removing the gate insulating film existing within a low voltage region, etching is not finished upon expose of an active region, but overetching is performed until the surface of an element isolation insulating...

20060001109 - High mobility tri-gate devices and methods of fabrication: A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a...

20060001110 - Lateral trench mosfet: In a lateral trench MOSFET in which a channel width is increased while an element area is not increased to attain reduction in an ON resistance, a source layer (004) and a drain layer (005) are formed in the vicinity of both ends of a trench (008) through multi-directional ion...

20060001111 - Semiconductor device: In a full depletion MISFET, there is a limit to control on a threshold voltage Vth by an impurity concentration in principle when a monocrystalline SOI layer becomes thin on the order of a few tens of nm. It was thus difficult to simultaneously realize predetermined Vth of both n...

20060001112 - Semiconductor device and method for manufacturing the same: The present invention discloses method for manufacturing semiconductor device employing an EXTIGATE structure. In accordance with the method, a predetermined thickness of the device isolation film is etched to form a recess. The recess is then filled with a second nitride film. A stacked structure of a barrier metal film,...

20060001113 - Magnetic sensor of very high sensitivity: A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two...

20060001114 - Apparatus and method of wafer level package: An apparatus of wafer level package for the micro elements and methods of fabricating the same is disclosed. The apparatus is utilized to provide a lid substrate for bonding the lid substrate to a substrate having several micro elements and therefore form a cavity capable of being operated for the...

20060001115 - Gate structure of semiconductor memory device: A gate structure of a semiconductor memory device capable of preventing a poly void generation by forming a hard mask and maintaining a hysteresis area within a certain value. The gate structure of the semiconductor memory device includes: a gate insulation layer formed on a semiconductor substrate; a gate electrode...

20060001117 - Semiconductor device, optoelectronic board, and production methods therefor: The semiconductor device of the present invention comprises an optical transmission region, and a light receiving part for converting light propagating through the optical transmission region to an electrical signal, wherein the optical transmission region comprises a two-dimensional optical waveguide layer, and wherein at least a portion of the light...

20060001116 - Semiconductor module with a semiconductor sensor chip and a plastic package as well as method for its production: The invention relates to a semiconductor module with a semiconductor sensor chip and an associated method. The sensor chip has a sensor region, and nonsensitive regions of the sensor chip are embedded in a nontransparent plastic package molding compound. The sensor region of the sensor chip is operably coupled to...

20060001118 - Low capacitance avalanche photodiode: An avalanche photodiode having a reduced capacitance is provided. The avalanche photodiode includes a wide band gap layer in its depletion region. The width of the wide band gap layer increases the extent of the depletion region, thereby reducing the capacitance while minimizing the impact on the dark current....

20060001119 - Iii-v semiconductor nanocrystal complexes and methods of making same: A semiconductor nanocrystal complex that is stable and has high luminescent quantum yield. The semiconductor nanocrystal complex has a semiconductor nanocrystal core of a III-V semiconductor nanocrystal material. A method of making a semiconductor nanocrystal complex is also provided. The method includes synthesizing a semiconductor nanocrystal core of a III-V...

20060001120 - Integrated mis photosensitive device using continuous films: An integrated photosensitive device with a metal-insulator-semiconductor (MIS) photodiode constructed with one or more substantially continuous layers of semiconductor material and with a substantially continuous layer of dielectric material....

20060001121 - Phototransistor of cmos image sensor and method for fabricating the same: A phototransistor of a CMOS image sensor suitable for decreasing the size of layout, and a method for fabricating the phototransistor are disclosed, in which the phototransistor includes a first conductive type semiconductor substrate; an STI layer on the first conductive type semiconductor substrate, to define an active area and...

20060001122 - Semiconductor device and method for manufacturing the same: An object of the present invention is to provide a semiconductor device that is able to realize a low on-resistance maintaining a high drain-to-source breakdown voltage, and a method for manufacturing thereof, the present invention including: a supporting substrate 1; a semiconductor layer 3 having a P− type active region...

20060001123 - Module integrating mems and passive components: An apparatus may include a first substrate, one or more microelectromechanical systems (MEMS) coupled to the first substrate, a second substrate coupled with the first substrate, and one or more passive components coupled to the second substrate. A method may include aligning a first substrate having one or more MEMS...

20060001124 - Low-loss substrate for high quality components: Methods and apparatus providing high quality factor (Q) components on low loss substrates. A substrate is fabricated having a plurality of substrate support elements. A bridging layer is formed on the substrate that is supported by the support elements. A component is formed on the bridging layer. CMOS-compatible processing of...

20060001125 - Semiconductor device and method of producing the same: A semiconductor device includes a first transistor having a first gate oxide layer with a first thickness; a second transistor having a second gate oxide layer with a second thickness different from the first thickness; and at least one of a capacitor and a variable capacitance diode. One of the...

20060001126 - Transistor structures and transistors with a germanium-containing channel: A transistor structure includes a first undoped, silicon-containing channel layer, a buried germanium channel, and a second undoped, silicon-containing channel layer. The first and second channel layers may contain SiGe or, alternatively, Si only. Another transistor structure includes a first channel layer, a buried germanium channel, and a second, undoped...

20060001127 - Plasma enhanced deposited, fully oxidized psg film: A method of forming a plasma enhanced deposited oxide film on a substrate includes introducing into a chamber containing the substrate silane gas and a dopant gas such as phosphine. The chamber is pressurized and energy is applied to create a plasma. The energy may be a dual frequency energy....

20060001128 - Glass substrate and capacitance-type pressure sensor using the same: A glass substrate has a pair of main surfaces opposite to each other. Two island-shaped portions made of silicon are buried in the glass substrate. The tow island-shaped portions are exposed from the two main surfaces of the glass substrate, respectively. An electrode is formed on one main surface of...

20060001129 - Component interconnect with substrate shielding: An example of a circuit structure may include a first dielectric layer having first and second surfaces, and a channel extending at least partially between the first and second surfaces and along a length of the first dielectric layer. First and second conductive layers may be disposed on respective portions...

20060001131 - Memory device power distribution in memory assemblies: A synchronous flash memory assembly with a memory package having a plurality of interconnect pins, a lead-over-chip leadframe having a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship, and a synchronous flash memory chip coupled to the plurality of leads. The synchronous flash memory...

20060001133 - Optical sub-assembly for a transceiver: An electro-optical device (1) has a lead frame (3) having a through-hole (10) acting as a locating feature for a mould pin for moulding a body (4) incorporating a lens (5). The hole (10) is also used as a reference for a placement machine placing a component (2) within 1.5...

20060001132 - Palladium-spot leadframes for high adhesion semiconductor devices and method of fabrication: A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an adherent film of palladium on said nickel layer; and an adherent layer of palladium on said palladium film, selectively covering areas of said...

20060001130 - Taped lead frames and methods of making and using the same in semiconductor packaging: The invention provides a taped lead frame for use in manufacturing electronic packages. The taped lead frame is composed of a tape and a lead frame formed from a plurality of individual metal features attached to the tape and arranged in a footprint pattern. The method of making the invention...

20060001135 - Electronic package and semiconductor device using the same: A package for an electronic component according to one embodiment of the invention has a chip mounting area mounting a semiconductor chip in a hollow part of a metal plate and a plurality of connection electrodes to be connected to a substrate. The plurality of connection electrodes are formed in...

20060001134 - Package structure: A package structure includes a lead frame having a plurality of leads, each of which includes a first recession, at least a first device, and a plurality of solder joints respectively positioned in the first recessions for connecting the first device to the lead frame....

20060001136 - Quad flat non-leaded package: The present invention relates to a quad flat non-leaded package comprising: a lead frame, a semiconductor chip, a plurality of connecting wires and a molding compound. The lead frame has a plurality of leads, a die pad, a plurality of supporting bars and an external ring. The external ring is...

20060001138 - Ic-tag-bearing wiring board and method of fabricating the same: To improve electronic part packaging efficiency without sacrificing the transmission distance of a radio IC tag, a recess is formed in the front side surface of a printed wiring board. An IC chip is placed in the recess so that the IC chip does not protrude from the front side...

20060001137 - Integrated circuit package including embedded thin-film battery: An integrated circuit package is provided with a thin-film battery electrically connected to and encapsulated with an integrated circuit die. The battery can be fabricated on a dedicated substrate, on the die pad, or on the integrated circuit die itself....

20060001139 - Support structure for use in thinning semiconductor substrates and for supporting thinned semiconductor substrates: A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support...

20060001142 - Castellation wafer level packaging of integrated circuit chips: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When...

20060001143 - Castellation wafer level packaging of integrated circuit chips: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When...

20060001141 - Multi-component integrated circuit contacts: An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure....

20060001140 - Semiconductor chip package with thermoelectric cooler: The semiconductor chip package may include a substrate having circuit patterns and substrate pads connected with the circuit patterns. At least one semiconductor chip is mounted on the substrate, and a thermoelectric cooler having a P-type material plate and an N-type material plate is mounted on the semiconductor chip. Portions...

20060001146 - Low inductance semiconductor device having half-bridge configuration: A semiconductor device has connecting leads, whose base points (1f, 2f, 3f) have centroids (1m, 2m, 3m), wherein the connecting line between the centroids (1m, 3m) of the base points (1f, 3f) of the first (1) and third (3) connecting lead, and the connecting line between the centroids (2m, 3m)...

20060001144 - Scribe street structure for backend interconnect semiconductor wafer integration: A method of making a semiconductor device includes forming a wafer having a substrate and an interconnect structure over the substrate. The wafer also includes a plurality of die areas and a street located between a first die area of the plurality and a second die area of the plurality....

20060001147 - Semiconductor package and method for manufacturing the same: A semiconductor package includes: a first substrate including: a semiconductor base material having a first side and a second side; a functional element that is provided at the first side of the semiconductor base material; a first wiring; a pad that is electrically connected to the functional element via the...

20060001145 - Wafer level mounting frame with passive components integration for ball grid array packaging: A mounting frame substrate having a cavity formed therein and a semiconductor chip in the cavity of the substrate. The semiconductor chip includes bond pads along the periphery thereof and forming a redistribution trace connected to a bond pad of the chip....

20060001150 - Alignment devices for securing semiconductor devices to carrier substrates, and assemblies including the alignment devices: A semiconductor device including a plurality of stub contacts extending from a single edge thereof. A complementary alignment device includes at least one receptacle for receiving the semiconductor device. The alignment device is securable to a carrier substrate. A contact element may be configured to bias the semiconductor device in...

20060001148 - Finger structure: An improved finger structure applied to a packaging stack structure. The packaging stack structure is composed of several layers of chips, each chip is formed several leading wires and several finger sets are connected to the leading wire. Several finger units are formed on a finger set. The shape of...

20060001149 - Packaged substrate having variable width conductors and a variably spaced reference plane: A package substrate for a microelectronic die is described. The package substrate has first terminals in a small area and second terminals in a larger area with conductors connecting the first and second terminals. The conductors are fairly narrow near the first terminals so that they can fit next to...

20060001151 - Atomic layer deposited dielectric layers: An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing a hafnium metal layer on a substrate surface by atomic layer deposition and depositing a hafnium oxide layer on...

20060001152 - Direct connection multi-chip semiconductor element structure: A direct connection multi-chip semiconductor element structure is proposed. A plurality of semiconductor chips are mounted and supported on a metal heat sink, such that heat generated by the chips during operation can be dissipated via the heat sink. A circuit structure is extended from the chips to provide direct...

20060001153 - Silicon die substrate manufacturing process and silicon die substrate with integrated cooling mechanism: In one embodiment a method is provided. The method comprises inserting a first end of a P-type semiconductor pin in a first through hole via in a substrate; inserting a first end of an N-type semiconductor pin in a second through hole via in the substrate; and electrically connecting the...

20060001154 - Chip-to-chip trench circuit structure: A circuit structure may be formed in a substrate having a face and an open trench, where one or more chips are to be mounted. At least one bridge may extend across an intermediate portion of the trench, and optionally, may divide the trench into sections. A conductive adhesive layer...

20060001155 - Semiconductor device packages including leads with substantially planar exposed portions extending from bottom edges of the packages, and assemblies including the packages: A semiconductor device package including leads with substantially planar exposed portions extending from a bottom edge of the package. The exposed portions of the leads may comprise stub contacts extending perpendicularly from the bottom edge. The exposed portions of the leads may be substantially rigid or nondeformable. A complementary alignment...

20060001156 - Semiconductor device: In a semiconductor device comprising a semiconductor chip, electrodes formed on the major surface of the semiconductor chip, and a wiring board for mounting the semiconductor chip, for example, wirings for electrically connecting the wirings of the wiring board to the electrodes are provided. As the wirings, those relaxing stress...

20060001157 - Methods and apparatus for integrated circuit ball bonding using stacked ball bumps: An integrated circuit comprises at least one circuit element having at least one bond site and a passivation layer. The bond site is accessible through an aperture in the passivation layer. At least two ball bumps are disposed at the bond site. A first ball bump is bonded to the...

20060001158 - Package stress management: Numerous embodiments of an apparatus and method to stress and warpage of semiconductor packages are described. In one embodiment, a semiconductor die is disposed above a substrate. An encapsulating material is disposed above the substrate and semiconductor die, in which the encapsulating material has a combination of a low coefficient...

20060001159 - Electronic assembly having multi-material interconnects: According to one aspect of the invention, an electronic assembly is provided. The electronic assembly includes a first substrate having an integrated circuit formed therein and a second substrate. The first and second substrates are interconnected by a plurality of bi-material interconnects that are electrically connected to the integrated circuit...

20060001160 - Surface treatment of metal interconnect lines: Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first...

20060001161 - Electrical contact for high dielectric constant capacitors and method for fabricating the same: An electrical contact includes a non-conductive spacer surrounding conductive plug material along the full height of the contact. The spacer inhibits oxide and other diffusion through the contact. In the illustrated embodiment, the contact includes metals or metal oxides which are resistant to oxidation, and additional conductive barrier layers. The...

20060001162 - Nitride and polysilicon interface with titanium layer: A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The...

20060001166 - Circuit device and manufacturing method thereof: A circuit device including a multilayer wiring structure having an improved heat radiation performance, and a manufacturing method thereof is provided. A circuit device of the invention includes a first wiring layer and a second wiring layer laminated while interposing a first insulating layer. The first wiring layer is connected...

20060001163 - Groundless flex circuit cable interconnect: Embodiments of the present invention include an apparatus, method, and/or system for using a groundless flex circuit cable to interconnect semiconductor packages....

20060001164 - Phase-change random access memory device and method for manufacturing the same: Disclosed are a phase-change random access memory device and a method for manufacturing the same. The phase-change random access memory includes a first insulation layer having first contact holes, conductive plugs for filling the first contact holes, a second insulation layer having a second contact hole, and a bit line....

20060001165 - Semiconductor device: A semiconductor device with a damascene wiring structure which can prevent short-circuits between a seal ring and a wiring line or electrode pad. The upper layer barrier layer made from a conductive barrier material film is formed on the interlayer insulating film groove sidewall of the semiconductor device, an upper...

20060001167 - Semiconductor device: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that...

20060001169 - Semiconductor device: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that...

20060001168 - Technique for forming a dielectric interlayer above a structure including closely spaced lines: By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces between closely spaced lines on the order of 200 nm or less. Moreover, the bulk silicon dioxide material is...

20060001170 - Conductive compound cap layer: An interconnect structure and method thereof comprising: a interconnect and a compound cap layer. The interconnect has a compound cap layer thereover. The interconnect is preferably comprised of copper. The compound cap layer is preferably comprised of a copper-metal (Cu-Me) compound or a metal; and is more preferably comprised of...

20060001171 - Electrode contact structure and method for fabricating the same: An electrode contact structure having a high reliability is provided. The structure comprises an Au electrode formed on a GaAs substrate, a contact hole open in an insulating film on the Au electrode, and an Al wiring being in contact with the Au electrode through the contact hole. The difference...

20060001172 - Hermetic seal cover and manufacturing method thereof: A hermetic seal cover capable of inhibiting defects such as voids from generating in sealing a package, and a method of manufacturing the seal cover are provided. The hermetic seal cover comprises: a seal cover main body; a Ni plating layer applied onto a surface of the seal cover main...

20060001175 - Masking structure having multiple layers including an amorphous carbon layer: A masking structure having multiple layers is formed. The masking structure includes an amorphous carbon layer and a cap layer formed over the amorphous carbon layer. The amorphous carbon layer includes transparent amorphous carbon. The cap layer includes non-oxide materials. The masking structure may be used as a mask in...

20060001174 - Semiconductor device and method for manufacturing the same: A semiconductor device 100 is provided with a multiplex through plug 111 that fills an opening extending through the silicon substrate 101. The multiplex through plugs 111 comprises a column-shaped and solid first through electrode 103, a first insulating film 105 that covers the cylindrical face of the first through...

20060001173 - Through electrode and method for forming the same: A method for forming a through electrode is disclosed. The through electrode integrally comprises a columnar electrode filling a through hole, a lower end electrode pad formed on a lower end side of a columnar electrode and having an area wider than the cross section of the through hole, and...

20060001177 - Semiconductor chip stack: A the semiconductor chip stack in which an intermediate space between semiconductor chips is filled at least along one edge of the upper face of a top chip by a spacer composed of a polymer which can be structured photographically, of photoresist, of an encapsulation compound or an adhesive, and...

20060001176 - Stacked semiconductor device: A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through...

20060001178 - Interconnect shunt used for current distribution and reliability redundancy: In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated...

20060001179 - Interposer, method of fabricating the same, and semiconductor device using the same: An interposer to be interposed between a semiconductor chip to be mounted thereon and a packaging board has an interposer portion made of a semiconductor and an interposer portion provided around the foregoing interposer portion integrally therewith. On both surfaces of the interposer portions, wiring patterns are formed via insulating...

20060001180 - In-line wire bonding on a package, and method of assembling same: A wire-bonding substrate includes in-line wire bonds that are substantially of the same pitch on the die bond pads as on the substrate bond pads. A wire-bonding substrate also includes staggered bond pads on at least one of the die and the substrate. A substrate bond pad includes a first...

20060001181 - Terminal structure of multi-layer substrate and method for forming the same: Disclosed is a terminal structure of a multi-layer substrate and a method for forming the same. In the terminal structure, a plurality of terminals are formed on at least two adjacent substrate layers, each of the terminals being spaced from adjacent ones to a predetermined interval. Openings are formed in...