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  A test structure and method for detecting charge effects during semiconductor processingUSPTO Application #: 20080023699Title: A test structure and method for detecting charge effects during semiconductor processing Abstract: A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure. (end of abstract) Agent: Baker & Mckenzie LLP Patent Department - Dallas, TX, US Inventors: Ming-Hsiu Lee, Chao-I Wu, Ming-Chang Kuo USPTO Applicaton #: 20080023699 - Class: 257 48 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080023699. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND [0001]1. Field of the Invention [0002]This invention relates generally to testing and diagnostics of line processes used for the manufacture of integrated circuit devices, and more particularly to the measurement and monitoring of the charging status in a gate dielectric layer or floating gate layer of a test structure during semiconductor processing steps. [0003]2. Background of the Invention [0004]The manufacture of large-scale integrated circuits involves hundreds of discrete processing steps. These steps are typically divided into two sub-processes. The first of these sub-processes is often referred to as the front-end of line (FEOL) sub-process during which the semiconductor devices are formed within a silicon wafer. The second of the sub-processes is often termed the back-end of line (BEOL) sub-process during which various metal interconnecting layers and contacts are formed on top of the semiconductor devices formed during the FEOL sub-process. [0005]Many of the processing steps comprising the FEOL and BEOL sub-processes involve depositing layers of material, patterning the layers by photolithographic techniques, and then etching away unwanted portions of the deposited material. The deposited materials primarily consist of insulators and metal alloys. In some instances the pattern layer serves as temporary protective mass, while on others they are functional components of the integrated circuit chips being formed. [0006]Radio frequency (RF) plasmas are often used in many of the processing steps, especially in the processing steps comprising the BEOL sub-process. For example, RF plasmas are used in Reactive Ion Etching (RIE), which is used to etch the layers of material as described above. RIE provides the etching anisotropy required to achieve the requisite high degree of pattern definition and precision and the requisite precision dimensional control. In RIE, gaseous chemical etching is assisted by unidirectional ion bombardment provided by an RF plasma. Photo-resist layers, used in the photolithographic patterning described above, are also frequently removed using plasma ashing. [0007]Unfortunately, the numerous exposures to the RF plasmas, and other forms of ionic radiation, results in radiation damage and the accumulation of charge on exposed conductive components, which leads to damaging current flows and trapped charges affecting the semiconductor devices and integrated circuit chips being formed. The surfaces of the patterned semiconductor wafer present multiple areas of conductors and insulators to the RF plasmas. The multiple areas of conductors and insulators produce local non-uniformities in the plasma currents, which can result in charge build up on the electrically floating conductor surfaces. This charge build up can produce the damaging current flows and can affect the threshold voltages for semiconductor structures formed on the silicon wafer. [0008]The semiconductor devices often comprise some form of field effect transistor comprising a gate, drain, and source regions. The gate often comprises a polysilicon electrode separated from the substrate by a gate dielectric. Charge can penetrated through the gate dielectric to the gate electrode. The mechanism of current flow through the gate oxide is primarily the result of Fowler-Nordheim (FN) tunneling. FN tunneling occurs at fields in excess of 10 MV/cm. Charge build up on the gate electrode resulting in a gate electrode potential of only 10 volts is therefore sufficient to induce FN tunneling through an oxide layer of 100 A. Such potentials are easily achieved in conventional plasma reactors used to generate RF plasmas and semiconductor processing. Excessive FN tunneling currents eventually lead to positively charged interface traps in the oxide layer forming the gate, which can lead to subsequent dielectric breakdown. [0009]As the semiconductor wafer is exposed to successive processing steps, the damage or potential damage is increased. As a result, efforts are made to assess the damage produced in the various semiconductor processing steps. For example, one common way to test for the level of damage is to produce test wafers or test chips comprising structures designed to measure, or allow measurement of, the damage produced by various processing steps. [0010]Test structures are typically formed within a specifically designated test site on a semiconductor wafer being processed. Alternatively, entire wafers can be devoted to providing a plurality of test structures for process monitoring. Thus, the test structures are run through the process which results in charge build up that can be then measured. A common method for measuring the charging status is to use Capacitance-Voltage (CV) techniques or floating gate testers. Such techniques, however, are often unsatisfactory for the semiconductor industry because of their low sensitivity, high test chip cost, or long delay time associated with the production of data related to the testing. [0011]For example, the CV method can only be used for processes with uniform charging effect. In other words, for processes that result in charge accumulating at the edge of the gate structure, CV methods will suffer from insufficient capacitance change produced by the trapped charges. The insufficient capacitance change will render conventional CV methods insufficient for monitoring the charging status. SUMMARY [0012]A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-Induced Drain Leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure. [0013]In one aspect, charge-trapping layers comprising dielectrics with different charging states near the diffusion region will result in different GIDL currents. [0014]In another aspect, the charge-trapping layer can be an oxide-nitrite-oxide or oxide-Si-oxide structure. [0015]These and other features, aspects, and embodiments of the invention are described below in the section entitled "Detailed Description." BRIEF DESCRIPTION OF THE DRAWINGS [0016]Features, aspects, and embodiments of the inventions are described in conjunction with the attached drawings, in which: [0017]FIGS. 1A-1C are diagrams illustrating various views of a test structure configured in accordance with one embodiment; [0018]FIG. 2 is a diagram illustrating a metalized version of the test structure of FIG. 1 with test leads; [0019]FIG. 3 is a diagram illustrating bias voltages that can be applied to the test structure of FIG. 1 in order to generate GIDL currents for measurement of charge status in accordance with one embodiment; [0020]FIG. 4 is a diagram illustrating current measurements obtained using the bias voltages of FIG. 3 before and after a process step being evaluated; [0021]FIG. 5 is a diagram illustrating a plurality of different gate electrode shapes that can be used for the test structure of FIG. 1; Continue reading... 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