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A cmos imager photodiode with enhanced capacitanceRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Light Responsive Or Combined With Light Responsive Device, Imaging Array, Photoresistors Accessed By Fets, Or Photodetectors Separate From Fet ChipA cmos imager photodiode with enhanced capacitance description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070187734, A cmos imager photodiode with enhanced capacitance. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to semiconductor optical image sensors, and particularly, to a novel CMOS (complementary metal oxide semiconductor) image sensor photodiode structure having a deep trench with a diode all along its sidewall to increase the capacitance of the structure without increasing the area of the cell. This trench structure can be designed in such a way that the trench will be fully depleted during the reset phase of operation and can hold a larger charge due to its larger capacitance than a conventional photodiode. DESCRIPTION OF THE PRIOR ART [0002] CMOS image sensors are now replacing conventional CCD sensors for applications requiring image pick-up such as digital cameras, cellular phones, PDA (personal digital assistant), personal computers, and the like. Advantageously, CMOS image sensors are fabricated by applying present CMOS fabricating process for semiconductor devices such as photodiodes or the like, at low costs. Furthermore, CMOS image sensors can be operated by a single power supply so that the power consumption for that can be restrained lower than that of CCD sensors, and further, CMOS logic circuits and like logic processing devices are easily integrated in the sensor chip and therefore the CMOS image sensors can be miniaturized. [0003] As the pixel size in CMOS imagers continue to scale down, to reduce costs, several problems arise: First, the smaller area reduces the total amount of electrons that can be stored in a given cell due to the reduced cell capacitance. Second, the smaller area increases the crosstalk between cells because electron diffusion is primarily responsible for the transport of the electrons from deep into the substrate to the surface photodiode. Third, the signal to noise ratio degrades because of a smaller number of electrons that are being measured and the noise sources (which primarily come from the periphery of the photodiode and its support circuits) that have not scaled. Current trench-type CMOS imager photosensor devices are described in U.S. Pat. Nos. 6,232,626; 6,500,692; 2004/0195600 and additionally, U.S. Pat. Nos. 6,611,037; 6,767,759; 6,730,980 and 6,838,742. [0004] FIG. 1 depicts a typical photosensor cell 10 having a trench-type configuration such as shown in prior art U.S. Pat. No. 6,232,626. As shown in FIG. 1, photosensor cell 10 is formed on a semiconductor substrate that includes an epitaxial layer or well surface layer 15 of a first conductivity type, e.g., p-doped. The photosensor cell 10 includes an overlying conductive layer 18 that is transparent to radiant energy and may comprise polysilicon. An insulating layer 22 formed of a suitable material, e.g., SiO.sub.2, is formed between the conductive layer 18 and underlying doped diffusion region 20. Element 25 comprises a transfer gate and includes diffusion regions 20 and 30 doped with material of a second conductivity type, e.g., n-doped. According to the prior art, the doped diffusion regions 20 and 30 are performed by ion implantation. The diffusion region 30 that is a floating diffusion region of the second conductivity-type serves as the source for a further reset transistor (not shown). The combined n-doped diffusion region 20 and p-type substrate 15 comprises a photodiode sensor for converting the photon energy into accumulating image charge for the photosensor cell pixel 10. [0005] The charge transfer transistor gate 25 is shown surrounded by thin spacer structures 23a,b. An STI region 40 is formed proximate the pixel imager cell for isolating the cell 10 from an adjacent pixel cell. In operation, light coming from the pixel is focused onto the photodiode where electrons collect at the n-type region 20. When the transfer gate 25 is operated, i.e., turned on by applying a voltage to the transfer gate comprising, for example, an n-type doped polysilicon layer or conducting layer 70, the photo-generated charge 24 is transferred from the charge accumulating n-type doped region 20 via a transfer device surface channel 16 to the floating diffusion region 30, e.g., doped n+ type, as shown by arrow A. [0006] While touted as providing increased surface area as compared to a flat photosensor element occupying a comparable area on a substrate, thus exhibiting a higher charge capacity and improved dynamic range, there are drawbacks, particularly, in the fact that this prior art photosensor cell of FIG. 1 teaches forming the charge collection region adjacent to physical boundaries such as trench walls, STI oxide structures, and the surface of the substrate. [0007] Thus, a characteristic of these trench type CMOS imager photosensor devices is the existence of large dark current, i.e., leakage current, which discharges the pixel capacitance when there is no light over the pixel. The dark current measured at the pixel output depends on the photodiode, the transistors, and the interconnectivity in the pixel. None of the above-indicated prior art references teach isolating the charge collection region thus, and do not address dark current performance. [0008] It would be highly desirable to provide a CMOS imager having the photodetector diode formed on the sidewall of a deep trench, resulting in collector isolation, and, a simplified process therefore. [0009] It would be highly desirable to provide a CMOS imager having a photodetector diode formed on the sidewall of a deep trench, the photodiode thus exhibiting increased electron capacity by increasing the photodiode capacitance without adding to the cell size, or to the cell leakage. SUMMARY OF THE INVENTION [0010] It thus an object of the invention to provide a CMOS image sensor having a photodetector diode formed on the sidewall of a deep trench, resulting in collector isolation, and, a simplified process therefore. [0011] It is a further object of the invention to provide a CMOS imager having a photodetector diode formed on the sidewall of a deep trench, the photodiode having increased electron capacity by increasing the photodiode capacitance without adding to the cell size, or to the cell leakage. [0012] According to one aspect of the invention, there is provided a pixel sensor cell comprising a non-lateral (e.g., vertical) collection region which is isolated from a physical boundary (e.g., substrate surfaces such as top surface or sidewalls/bottom of trench). In an embodiment of the invention, a trench is formed in a substrate of a first conductivity type (p type); a first doped layer of a second conductivity type (n type) is formed surrounding the trench walls to form a collection region; a second doped layer of the first conductivity type (p type) is formed between the first doped layer and the trench walls, and a third doped layer of the first conductivity type is formed on a surface of the substrate coupled to the second doped layer, wherein the second and third doped layers form a "pinning layer" for the sensor cell and isolate the collection region (e.g. first doped layer) from the trench walls and substrate surface. [0013] Advantageously, the isolating of the deep trench photodiode collection region (e.g. first doped layer) from the trench walls and substrate surface of the pixel sensor cell enables improved dark current performance with the same or smaller pinning voltage. [0014] A number of embodiments are described that include a pixel sensor cell structure having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region, the non-lateral charge collection region being entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and said substrate surface. [0015] In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region including a layer of second conductivity type material that contacts the first layer of the second conductivity type material of the non-laterally disposed charge collection region of the first photosensitive element. This layer of second conductivity type material underlies the second doped layer of the first conductivity type material formed at the substrate surface. [0016] In accordance with this further embodiment, the additional photosensitive element is formed adjacent a transfer gate device enabled for transferring charge carriers from both the laterally disposed charge collection region of the additional photosensitive element and charge carriers from the non-laterally disposed charge collection region of the photosensitive element across a gate channel to a formed diffusion region. The second conductivity type material of the first layer of the non-laterally disposed charge collection region of the photosensitive element is of a concentration such that the photosensitive element is fully depleted of accumulated charge carriers prior to depletion of charge carriers accumulated at the laterally disposed charge collection region of the additional photosensitive element. [0017] According to another aspect of the invention, there is provided a method for fabricating a pixel sensor cell including a photosensitive element having a non-laterally disposed charge collection region. The method comprises: [0018] forming a trench recess in a substrate of a first conductivity type material, the trench having sidewall and bottom portions; [0019] filling the trench recess with a material having second conductivity type material; [0020] outdiffuse second conductivity type material out of the filled trench material to the substrate region surrounding the trench sidewalls and bottom to form the non-laterally disposed charge collection region; [0021] removing the filled trench material to provide the trench recess; Continue reading about A cmos imager photodiode with enhanced capacitance... Full patent description for A cmos imager photodiode with enhanced capacitance Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this A cmos imager photodiode with enhanced capacitance patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like A cmos imager photodiode with enhanced capacitance or other areas of interest. ### Previous Patent Application: Solid-state image sensor using junction gate type field-effect transistor as pixel Next Patent Application: Method of manufacturing semiconductor device, and semiconductor device Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the A cmos imager photodiode with enhanced capacitance patent info. IP-related news and info Results in 0.13283 seconds Other interesting Feshpatents.com categories: Computers: Graphics , I/O , Processors , Dyn. Storage , Static Storage , Printers 174 |
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