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Static information storage and retrieval

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
12/18/2014 > 51 patent applications in 32 patent subcategories.

20140369103 - Content addressable memory cells and ternary content addressable memory cells: An embodiment of the invention provides a binary CAM cell. The binary CAM cell includes a storage circuit, a first discharging circuit, and a second discharging circuit. The storage circuit is configured to provide a first stored bit and a second stored bit, which are complimentary bits of each other.... Agent:

20140369104 - Memory device: According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the... Agent: Kabushiki Kaisha Toshiba

20140369105 - Generating output signal during read operation: A circuit includes a fuse cell, a sense circuit and an output control circuit. The fuse cell includes an electrical fuse. The sense circuit is electrically coupled to the fuse cell and configured for generating a sense signal indicative of a programmed condition of the electrical fuse, at an output... Agent:

20140369106 - Semiconductor device with fuse array and operating method thereof: A semiconductor device includes a fuse array for storing normal fuse data and pattern data through a programming operation, a boot-up control unit suitable for generating an enable signal for enabling an output of the pattern data, and a pattern detection unit suitable for detecting a pattern of the pattern... Agent: Sk Hynix Inc.

20140369107 - Structures for resistance random access memory and methods of forming the same: Memory cells and methods of forming the same and devices including the same. The memory cells have first and second electrodes. An amorphous semiconductor material capable of electronic switching and having a first band gap is between the first and second electrodes. A material is in contact with the semiconductor... Agent:

20140369108 - System and a method for designing a hybrid memory cell with memristor and complementary metal-oxide semiconductor: The embodiments herein relates to a hybrid non-volatile memory cell system and architecture for designing integrated circuits. The system comprises CMOS access transistor connected to a memristor which stores a data based on a resistance. The system has a word line for accessing the hybrid memory and two bit lines... Agent:

20140369109 - Semiconductor memory device and memory system including the same: A semiconductor memory device includes a plurality of word lines each of which are connected to a plurality of memory cells, a row control unit suitable for sequentially activating and precharging a word line corresponding to a target address and a predetermined (N) number of adjacent word lines during a... Agent: Sk Hynix Inc.

20140369111 - Semiconductor memory device and method for driving the same: In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m—1 or the... Agent:

20140369110 - Semiconductor memory device and semiconductor package: A semiconductor memory device includes: a memory unit including a first memory sub region including a first memory cell and a second memory sub region including a second memory cell; a temperature information obtaining unit that obtains temperature information; a temperature estimation unit that estimates a first temperature of the... Agent: Samsung Electronics Co., Ltd.

20140369112 - Semiconductor memory: A semiconductor memory is disclosed that includes a first data line, a second data line, a first coupling line and a second coupling line. The first coupling line is configured to capacitively couple the first coupling line with the first data line. The second coupling line is configured to capacitively... Agent:

20140369113 - Phase-change memory cells: A phase-change memory cell for storing information in a plurality of programmable cell states. The memory cell includes: a phase-change material located between a first electrode and a second electrode for applying a read voltage to the phase-change material to read a programmed cell state; and an electrically-conductive component extending... Agent:

20140369114 - Phase-change memory cells: Improved phase-change memory cells are provided for storing information in a plurality of programmable cell states. A phase-change material is located between first and second electrodes for applying a read voltage to the phase-change material to read the programmed cell state. An electrically-conductive component extends from one electrode to the... Agent:

20140369115 - Semiconductor device, method for fabricating the same, and memory system including the semiconductor device: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the... Agent: Samsung Electronics Co., Ltd.

20140369117 - Multiple step programming in a memory device: Method of operating a memory include programming a memory cell and reading the memory cell to determine a programmed threshold voltage of the memory cell. If the programmed threshold voltage is within a threshold voltage distribution of a plurality of threshold voltage distributions, the memory cell is reprogrammed, and if... Agent: Micron Technology, Inc.

20140369116 - Shielded vertically stacked data line architecture for memory: Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device.... Agent:

20140369118 - Configuring storage cells: Apparatuses, systems, methods, and computer program products are disclosed for configuring storage cells. A method includes determining a usage history for a set of storage cells of a solid-state storage medium. A method includes adjusting a voltage threshold for a set of storage cells by an amount based at least... Agent:

20140369119 - Compact memory device including a sram memory plane and a non volatile memory plane, and operating methods: A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable... Agent:

20140369120 - Memory device including a sram memory plane and a non volatile memory plane, and operating methods: A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a... Agent:

20140369124 - Memory systems including nonvolatile memory devices and dynamic access methods thereof: A method of operating a memory device includes: determining an erase mode based on a number of erase cycles performed on a memory block and an erase voltage utilized to perform each erase cycle; and setting an erase voltage level for executing an erase operation on the memory block based... Agent:

20140369122 - Pseudo block operation mode in 3d nand: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each... Agent: Sandisk Technologies Inc.

20140369123 - Pseudo block operation mode in 3d nand: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each... Agent: Sandisk Technologies Inc.

20140369121 - Semiconductor device: Disclosed is a semiconductor device, including: an active region defined in a shape extended in at least four different directions in a semiconductor substrate; and gates of first to fourth transistors formed on extended portions of the active region, respectively, in which the first to fourth transistors share one junction... Agent: Sk Hynix Inc.

20140369125 - Semiconductor device, data programming device, and method for improving the recovery of bit lines of unselected memory cells for programming operation: A device comprises a non-volatile memory array, a first selection circuit selecting whether to make a first connection path between a first bit line and a first circuit node, and selecting whether to make a second connection path between the first bit line and a second circuit node, a power... Agent:

20140369129 - Method and apparatus for program and erase of select gate transistors: Techniques are provided for programming select gate transistors in connection with the programming of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select... Agent:

20140369127 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a first string; a second string; and a controller. The first string is coupled with a first bit line and includes first memory cells. The second string is coupled with a second bit line and includes second memory cells. The controller... Agent: Kabushiki Kaisha Toshiba

20140369128 - Semiconductor memory device and operation method thereof: A semiconductor memory device includes a memory cell suitable for having a predetermined cell state based on a data stored therein, a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation, an information storage unit suitable... Agent: Sk Hynix Inc.

20140369126 - Simplified nonvolatile memory cell string and nand flash memory array using the same: The present invention provides a nonvolatile memory cell string and a NAND flash memory array using the same. According to the present invention, a wall type semiconductor separated into twin fins can increase the degree of integration and basically prevent the interferences between adjacent cells. And gate electrodes formed to... Agent:

20140369130 - Local self-boost using a plurality of cut-off cells on a single side of a string of memory cells: Methods for local self-boost of a selected memory cell channel, memory devices, and systems are disclosed. One such method generates a cut-off channel under each of a plurality of memory cells on one of either a source side or a drain side of a selected memory cell.... Agent: Micron Technology, Inc.

20140369131 - Method of operating semiconductor device: A semiconductor device is operated by, inter alia: programming selected memory cells by applying a first program voltage which is increased by a first step voltage to a selected word line and by applying a first pass voltage having a constant level to unselected word lines, and when a voltage... Agent:

20140369132 - Differential current sense amplifier and method for non-volatile memory: The selected bit line in a non-volatile memory carries a cell conduction current to be measured and also a leakage current or noise due to weak coupling with neighboring array structures. In a first phase, a sense amplifier senses the bit line current by discharging a capacitor with the combined... Agent: Sandisk 3d LLC

20140369133 - Semiconductor memory device, memory system including the same, and operating method thereof: Disclosed are a semiconductor memory device, a memory system including the same, and an operation method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; and a plurality of page buffers configured to supply currents to bit lines when a sensing operation is... Agent: Sk Hynix Inc.

20140369134 - Semiconductor memory device and method of operating the same: A semiconductor memory device and a method of operating the same perform a program loop, including a program operation and a program verification operation based on a sub-verification voltage smaller than a target verification voltage and the target verification voltage, to the memory cells until a threshold voltage of the... Agent: Sk Hynix Inc.

20140369135 - Ultra-low power programming method for n-channel semiconductor non-volatile memory: An Ultra-low power programming method for N-channel semiconductor Non-Volatile Memory (NVM) is disclosed. In contrast to the grounded voltage at the source electrode of an N-channel semiconductor NVM for the conventional Channel Hot Electron Injection (CHEI) programming, the source electrode in the programming method of the invention is necessarily floating... Agent:

20140369136 - Systems and methods for providing high voltage to memory devices: Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or... Agent: Cypress Semiconductor Corporation

20140369141 - Screening for reference cells in a memory: Selecting an array from among a plurality of arrays in a memory as a reference array. An exemplary method includes evaluating memory cells within the reference array to select a first reference cell associated with a first operation of the memory, and repeating the evaluating and the selecting to select... Agent:

20140369138 - Non-volatile memory, system, and method: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the... Agent:

20140369139 - Apparatus and a method for erasing data stored in a memory device: The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write... Agent:

20140369140 - Internal voltage generating circuit capable of controlling swing width of detection signal in semiconductor memory apparatus: An internal voltage generating circuit capable of controlling a swing width of a detection signal in a semiconductor memory apparatus is provided. The internal voltage generating circuit of a semiconductor memory apparatus includes an internal voltage level detecting unit configured to compare an internal voltage with a target voltage and... Agent:

20140369142 - Data transfer device, buffering circuit, and buffering method: A data transfer device 2 has a first bank 31 which has a first bank first memory 311 and a first bank second memory 312, a second bank 32 which has a second bank first memory 321 and a second bank second memory 322, and a control circuit. Write and... Agent:

20140369137 - Embedded memory device and memory controller including the same: An embedded memory device includes a mask ROM including a plurality of mask ROM cells and an address decoder configured to decode an address of the plurality of mask ROM cells; and an e-fuse memory configured to replace a part of data stored in the mask ROM with replacement data,... Agent: Samsung Electronics Co., Ltd.

20140369143 - Apparatuses and methods for mapping memory addresses to redundant memory: Apparatuses and methods related to redundant memory and mapping memory addresses to redundant memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of redundant memory sections. A programmable element block includes a plurality of programmable element sets. A programmable element set is configured to... Agent: Micron Technology, Inc.

20140369144 - Chip tester and test method of semiconductor device: A chip tester includes a test unit suitable for performing a test on guarantee blocks and for detecting at least one second defective block from the guarantee blocks, a storage unit suitable for storing repair information, a determination unit suitable for comparing the number of available redundancy blocks, which are... Agent: Sk Hynix Inc.

20140369145 - Semiconductor device and test method thereof: A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on... Agent:

20140369146 - Systems, circuits, and methods for charge sharing: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to... Agent:

20140369147 - Power converter for a memory module: An apparatus including a memory module and power converter and method of operating the same. In one embodiment, the apparatus includes a memory module, located on a circuit board, configured to operate from a first voltage and a second voltage being a multiple of the first voltage. The apparatus also... Agent: Enpirion, Inc.

20140369148 - Memory module and memory system: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal,... Agent:

20140369150 - Column decoders: Column decoders are provided. The column decoder includes a power supplier and a column selection signal generator. The power supplier generates a supply voltage signal from a power voltage in response to a control signal enabled from a start point of time of a write mode or a read mode... Agent:

20140369151 - High voltage switching circuitry for a cross-point array: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit... Agent:

20140369152 - N-well switching circuit: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage... Agent:

20140369149 - Word line drivers and semiconductor memory devices including the same: Word line drivers including a selection signal generator and a word line drive unit are provided. The selection signal generator generates a selection signal which is enabled according to a high-order address signal and a low-order address signal in an active mode. Further, the selection signal generator generates a complementary... Agent: Sk Hynix Inc.

20140369153 - Data strobe control device: A data strobe control device is disclosed, which relates to a technology for controlling a data write path of a semiconductor memory device. The data strobe control device includes: a plus-mode controller configured to output a first control signal for controlling a first mode and a plus on-the-fly signal upon... Agent: Sk Hynix Inc.

  
12/11/2014 > 29 patent applications in 20 patent subcategories.

20140362629 - Single package dual channel memory with co-support: A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can... Agent: Invensas Corporation

20140362630 - Method for improving bandwidth in stacked memory devices: Apparatus and methods of increasing the data rate and bandwidth of system memory including stacked memory device dice. The system memory includes a memory device having a plurality of memory device dice in a stacked configuration, a memory controller coupled to the stacked memory device dice, and a partitioned data... Agent:

20140362631 - Storage circuit: A storage circuit includes a volatile storage portion in which storage of a data signal is controlled by a clock signal and an inverted clock signal, and a nonvolatile storage portion in which a data signal supplied to the volatile storage portion can be held even after supply of power... Agent:

20140362632 - Data holding device and logic operation circuit using the same: A data holding device includes a loop structure unit configured to hold data using a plurality of logic gates connected in a loop shape, a nonvolatile storage unit including a plurality of ferroelectric elements, the nonvolatile storage unit configured to store the data held in the loop structure unit in... Agent:

20140362633 - Memory devices and memory operational methods: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different... Agent:

20140362634 - Oxide based memory: Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second... Agent:

20140362635 - Capacitor backup for sram: Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set... Agent:

20140362636 - Capacitor backup for sram: Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set... Agent: International Business Machines Corporation

20140362637 - Memory device, memory system, and operation method thereof: A memory device comprises: a memory cell array comprising first and second word lines located adjacent to each other, a first memory cell connected to the first word line, and a second memory cell connected to the second word line and located adjacent to the first memory cell; and a... Agent: Samsung Electronics Co., Ltd.

20140362638 - Structure and method for adjusting threshold voltage of the array of transistors: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge... Agent: International Business Machines Corporation

20140362639 - Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic... Agent:

20140362640 - Method for block-erasing a page-erasable eeprom-type memory: A method for erasing a page-erasable EEPROM-type memory includes: the memory receiving a command associated with a set of addresses of pages of the memory to be erased, each page comprising several memory cell groups each forming a word, for each address of the set of addresses, selecting a word... Agent: Stmicroelectronics (rousset) Sas

20140362642 - 3d non-volatile memory with control gate length based on memory hole diameter: A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at... Agent:

20140362645 - 3d non-volatile memory with control gate length based on memory hole diameter: A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at... Agent: Sandisk Technologies Inc.

20140362644 - Dual-mode memory devices and methods for operating same: A memory structure comprises a semiconductor strip having a multi-gate channel region, the p-type terminal region adjacent a first side of the channel region and an n-type terminal region adjacent the second side of the channel region. A plurality of word lines is arranged to cross the semiconductor strip at... Agent: Macronix International Co., Ltd.

20140362643 - Nonvolatile semiconductor memory device and method of operating the same: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of electrically rewritable memory transistors arranged therein; and a control unit configured to govern control that repeats a voltage application operation and a step-up operation, the voltage application operation applying an applied voltage... Agent: Kabushiki Kaisha Toshiba

20140362641 - Program and read operations for 3d non-volatile memory based on memory hole diameter: Techniques are provided for programming and reading memory cells in a 3D stacked non-volatile memory device by compensating for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, programming of memory cells at... Agent:

20140362646 - Reading soft bits simultaneously: Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a... Agent:

20140362647 - Determining system lifetime characteristics: The present disclosure includes methods and systems for determining system lifetime characteristics. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using... Agent:

20140362648 - Non-volatile memory system and method of programming the same: A non-volatile memory system includes a first non-volatile memory device, a second non-volatile memory device that performs a write operation more slowly than the first non-volatile memory device, where the first and second non-volatile memory devices are different types of non-volatile memory devices, and a controller that controls the first... Agent: The-aio Inc.

20140362650 - Apparatuses and methods for efficient write in a cross-point array: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing... Agent:

20140362649 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cell groups, a data line unit, a buffer unit and a bias voltage unit. The data line unit is coupled to the memory cell groups for transmitting to-be-read data and to-be-written data. The buffer unit includes a plurality of tri-state buffers... Agent:

20140362651 - Memory device and method operable to provide multi-port functionality thereof: A memory device operable to provide multi-port functionality, which may comprise a single-port memory having a first operating frequency that is at least twice of a second operation frequency of a multi-port memory, a read synchronization module that synchronizes a set of read signals from the second operation frequency to... Agent: Industrial Technology Research Institute

20140362652 - Semiconductor memory device and method for accessing the same: A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line... Agent: Institute Of Microelectronics, Chinese Academy Of Sciences

20140362653 - Memory control device and a delay controller: A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL... Agent:

20140362654 - Redundancy evaluation circuit for semiconductor device: A redundancy evaluation circuit has (m+1) fuse boxes and a comparator, wherein the m fuse box output a fuse status address signal and the other one fuse box outputs a comparator enable signal. Each fuse box has a common stage circuit and k redundant cells. The k redundant cells shares... Agent:

20140362655 - Semiconductor integrated circuit and information processing apparatus: According to an embodiment, a semiconductor integrated circuit includes a regulator, a level shifter and a switch circuit. The regulator converts an input voltage that is a difference in potential between a first terminal and a third terminal into an output voltage that is a difference in potential between a... Agent: Kabushiki Kaisha Toshiba

20140362656 - Memory with low current consumption and method for reducing current consumption of a memory: A method for reducing current consumption of a memory is disclosed, wherein the memory includes a controller and a plurality of banks, and each bank of the plurality of banks includes a plurality of segments. The method includes the controller enabling an activating command corresponding to a first row address... Agent:

20140362657 - Flexible identification technique: A shared-signaling multi-device memory system is capable of changing between addressing modes without the multi-device memory being required to undergo a power cycle. First and second registers of a memory device are set to both contain first address-identification information in response a first address-assignment command that is received a power... Agent:

  
12/04/2014 > 47 patent applications in 26 patent subcategories.

20140355326 - Non-volatile memory device: According to one embodiment, a non-volatile memory device includes: a plurality of first interconnects, and each of the first interconnects extending in a first direction; a plurality of second interconnects, and each of the second interconnects extending in a second direction intersecting with the first direction; a memory cell connected... Agent: Kabushiki Kaisha Toshiba

20140355325 - Packaging of high performance system topology for nand memory systems: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in... Agent: Sandisk Technologies Inc.

20140355327 - Memory module and memory system having the same: A memory system includes a controller, a first memory module, and a second memory module. The first memory module includes a first number of memory packages and a second number of memory packages. The second memory module includes a third number of memory packages and a fourth number of memory... Agent: Samsung Electronics Co., Ltd.

20140355328 - Ferroelectric memory cell for an integrated circuit: An integrated circuit includes a ferroelectric memory cell. In one embodiment, the ferroelectric memory cell includes a first oxide storage layer, a second oxide storage layer, and an amorphous layer disposed between the first and second oxide storage layers. Each of the first and second oxide storage layers includes a... Agent:

20140355330 - Integrated circuit:

20140355329 - Method and apparatus for common source line charge transfer: A method and apparatus for charge transfer comprising a resistive random access memory (ReRAM) cell, coupled to a common source voltage line (CSL) for controlling state of the ReRAM cell, and a charge transfer circuit, coupled to the memory cell through the CSL and a charge consumption circuit, for transferring... Agent: Sony Corporation

20140355331 - Multi-level memory cell with continuously tunable switching: The present disclosure provides a data storage device that includes multi-level memory cells. The data storage device may include circuitry configured to write data to the multi-level memory cell. The write circuitry may include compliance circuitry configured to implement continuously tunable switching. The write circuitry may be configured to select... Agent: Hewlett-packard Development Company, L.p.

20140355333 - Semiconductor memory device and driving method thereof: A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of... Agent:

20140355332 - Volatile memory device and refresh method thereof: Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the... Agent: Samsung Electronics Co., Ltd.

20140355334 - Handshaking sense amplifier: Handshaking sense amplifier. In accordance with a first embodiment, an electronic circuit includes a sense amplifier configured to differentially sense contents of a memory cell. The circuit also includes a self-timing circuit configured to detect a completion of evaluation by the sense amplifier; and to initiate a subsequent memory operation... Agent:

20140355335 - Static random access memory system and operation method thereof: A static random access memory system includes a static random access memory, a multiplexer, an input buffer, an output buffer, and a shifter. The input buffer writes write data stored in the input buffer to addresses of the static random access memory corresponding to a write address signal according to... Agent: Etron Technology, Inc.

20140355337 - Method of pinning domain walls in a nanowire magnetic memory device: There is provided a method of pinning domain walls in a magnetic memory device (10) comprising using an antiferromagnetic material to create domain wall pinning sites. Junctions (22) where arrays of ferromagnetic nanowires (16) and antiferromagnetic nanowires (20) cross exhibit a permanent exchange bias interaction between the ferromagnetic material and... Agent: University Of York

20140355336 - Semiconductor memory device: According to one embodiment, the semiconductor memory device includes a first memory cell, first, second, third and fourth interconnect lines and first, second and third write circuits. The first memory cell includes a first magnetic tunnel junction (MTJ) element. The first interconnect line is connected to one end of the... Agent:

20140355338 - Non-volatile phase-change resistive memory: A method for implementing a system containing at least one memory device including a plurality of non-volatile memory cells each including a phase-change material configured to change state reversibly between at least an amorphous state and a crystalline state having different electrical resistances. The method includes steps of manufacturing the... Agent: Commissariat A L'energie Atomique Et Aux Ene Alt

20140355339 - Driving method of semiconductor device: In a memory cell including first to third transistors, the potential of a bit line is set to VDD or GND when data is written through the first transistor. In a standby period, the potential of the bit line is set to GND. In reading operation, the bit line is... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140355342 - Dynamically configurable mlc state assignment: Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a... Agent: Micron Technology, Inc.

20140355341 - Read threshold estimation in analog memory cells using simultaneous multi-voltage sense: A method includes dividing a group of analog memory cells into multiple subsets. The memory cells in the group are sensed simultaneously by performing a single sense operation, while applying to the subsets of the memory cells respective different sets of read thresholds, so as to produce respective readout results.... Agent:

20140355340 - Updating read voltages: A data storage device includes a memory and a controller. Read voltages are updated based on adjusting a first read voltage without adjusting a second read voltage to generate multiple sets of read voltages, and the multiple sets of read voltages are used to generate multiple representations of data. A... Agent: Sandisk Technologies Inc.

20140355343 - Semiconductor memory having both volatile and non-volatile functionality and method of operating: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile... Agent:

20140355344 - Adaptive operation of three dimensional memory: When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable... Agent:

20140355345 - Adaptive operation of three dimensional memory: When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable... Agent: Sandisk Technologies Inc.

20140355348 - Flash memory system and word line interleaving method thereof: Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation... Agent:

20140355347 - Mitigating reliability degradation of analog memory cells during long static and erased state retention: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The... Agent: Apple Inc.

20140355346 - Nonvolatile memory device: A nonvolatile memory device includes first to N-th memory blocks, wherein N is an integer and N≧3. Each memory block, of the first to N-th memory blocks comprises first to (M−1)-th strings, wherein each string, of the first to (M−1)-th strings, includes drain-side memory cells, source-side memory cells, and a... Agent: Sk Hynix Inc.

20140355349 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block... Agent: Kabushiki Kaisha Toshiba

20140355350 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction... Agent: Kabushiki Kaisha Toshiba

20140355351 - Controller: A controller for a memory device having a bit line, a source line, and a plurality of strings of memory cell transistors connected between the bit line and the source line, is configured to update first and second values for each string when read and write operations are carried out... Agent: Kabushiki Kaisha Toshiba

20140355352 - Memory array with power-efficient read architecture: Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third... Agent:

20140355353 - Current sensing amplifier and sensing method thereof: A sensing method of a current sensing amplifier is provided used for determining a storing state of a cell of a non-volatile memory device during a read cycle. After a sensing node and a reference node are adjusted to a constant voltage, the sensing node and the reference node are... Agent:

20140355354 - Integrated circuit and operation method thereof: An integrated circuit includes a mirroring/amplifying unit suitable for mirroring and amplifying a sensing current that flows on a signal transmission line coupled to an internal circuit, and outputting an amplified current; a reference current generating unit suitable for generating a reference current; and a state determination unit suitable for... Agent: Sk Hynix Inc.

20140355355 - Methods, devices, and systems for adjusting sensing voltages in devices: The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage... Agent:

20140355356 - Data transfer circuit and memory including the same: A data transfer circuit includes a plurality of first lines, a second line suitable for receiving data from a first line selected among the first lines, a third line suitable for transferring data to the first line selected among the first lines, a plurality of driving units, each suitable for... Agent: Sk Hynix Inc.

20140355357 - Method for writing in an eeprom-type memory including a memory cell refresh: The present disclosure relates to a method for writing in an EEPROM memory, the method comprising steps of: storing the bits of a word to be written in first memory units, erasing a word to be modified, formed by first memory cells connected to a word line and first bit... Agent: Stmicroelectronics (rousset) Sas

20140355361 - Circuit in dynamic random access memory devices: A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide... Agent: Nanya Technology Corporation

20140355358 - Circuits and methods for efficient execution of a read or a write operation: A system for efficient execution of a read or a write is described. The system includes a memory array including a way. The system further includes a read and compare circuit. The read and compare circuit compares data stored within lower address memory cells of the way with information received... Agent: Oracle International Corporation

20140355359 - Continuous tuning of preamble release timing in a double data-rate memory device interface: Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated... Agent:

20140355360 - High speed and low offset sense amplifier: A sense amplifier includes a sensing circuit and an equalizing circuit. The sensing circuit is configured to supply one or more output signals according to one or more input signals. The equalizing circuit is configured to bring the sensing circuit to a metastable state from which the sensing circuit switches... Agent:

20140355362 - Pipelined one cycle throughput for single-port 6t ram: Pipelined one cycle throughput for single-port 6T RAM. In accordance with a first embodiment, an electronic circuit is configured to perform consecutive read accesses using one sense amplifier. The electronic circuit includes circuitry configured to precharge the sense amplifier, circuitry configured to precharge a sense node coupled to the sense... Agent:

20140355364 - Memory and memory system: A memory may include first to Nth cell arrays configured to include a plurality of memory cells and one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays, wherein the one or more first to Nth data input/output pads are configured to... Agent: Sk Hynix Inc.

20140355363 - Memory chip and semiconductor package including the same: A memory chip includes a data processing block suitable for serial-parallel converting data inputted and for parallel-serial converting data to be outputted, a write data transmitting unit suitable for transmitting the data serial-parallel converted by the data processing block to a write data interlayer channel, a write data receiving unit... Agent: Sk Hynix Inc.

20140355365 - Pulse generator: Various circuits and methods of operating circuits are disclosed. A circuit may include a pulse generator and a latch having an output configured to trigger the pulse generator, wherein the latch is configured to be set by an input signal and reset by feedback from the pulse generator. A method... Agent:

20140355366 - Multiple data rate memory with read timing information: A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured... Agent:

20140355367 - Multiple data rate memory with read timing information: A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured... Agent: Freescale Semiconductor, Inc.

20140355369 - Memory operation upon failure of one of two paired memory devices: A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory... Agent:

20140355368 - Semiconductor device: An embodiment of the present invention provides a semiconductor, including a non-volatile storage unit suitable for storing one or more first addresses; an address storage unit suitable for storing the first addresses sequentially received from the non-volatile storage unit as second addresses while deleting previously stored second addresses identical to... Agent: Sk Hynix Inc.

20140355370 - Semiconductor system and semiconductor package: A semiconductor system includes a plurality of memory chips. Each of the memory chips includes an oscillator suitable for generating a periodic wave in a self refresh mode, and a delay unit suitable for delaying the periodic wave to generate a refresh pulse and for setting a delay value based... Agent: Sk Hynix Inc.

20140355371 - Address detection circuit, memory system including the same: An address detection circuit includes an address storage unit suitable for receiving an address when an active command is activated, and storing recently inputted N number of addresses; and an address determination unit suitable for determining whether an address currently inputted to the address storage unit is already inputted at... Agent: Sk Hynix Inc.

  
11/27/2014 > 46 patent applications in 28 patent subcategories.

20140347907 - Electronic component including a matrix of tcam cells: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of... Agent: Stmicroelectronics S.a.

20140347906 - Tcam memory cell and component incorporating a matrix of such cells: A ternary content-addressable cell is configured to compare an input binary data item present on an input terminal with two reference binary data items, and to output a match signal on a match line. The cell includes: a first storage circuit (storing a potential representing the first reference binary data... Agent: Stmicroelectronics Sa

20140347908 - Semiconductor memory and method of making the same: A semiconductor cell comprises a plurality of metal layers. A first layer comprises a VDD conductor, a bit-line, and a complimentary bit-line. Each of the VDD conductor, the bit-line, and the complementary bit-line extend in a first direction. A second layer comprises a first VSS conductor and a first word-line.... Agent:

20140347909 - Semiconductor device and semiconductor memory device: A semiconductor device includes a fuse array having a plurality of fuse sets suitable for outputting a plurality of fuse status signals having different levels according to whether fuses of the plurality of fuse sets are cut or not, a code counter suitable for counting selection codes in a preset... Agent: Sk Hynic Inc.

20140347914 - Multi-function resistance change memory cells and apparatuses including the same: Various embodiments comprise apparatuses including drive circuitry to provide signal pulses of a selected time duration and/or amplitude to a number of memory cells. The memory cells may include an array of resistance change memory cells to be electrically coupled to the drive circuitry. The resistance change memory cells may... Agent:

20140347911 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell block that includes a memory cell array, the memory cell array including: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; and a memory cell that is provided at each... Agent: Kabushiki Kaisha Toshiba

20140347910 - Reading memory elements within a crossbar array: A method for reading the state of a memory element within a crossbar memory array includes storing a first electric current sensed from a half-selected target memory element within the crossbar memory array; and outputting a final electric current based on the stored first electric current and a second electric... Agent: Hewlett-packard Development Company, L.p.

20140347913 - Resistive switching memory device and method for operating the same: A resistive switching memory device and a method for operating the same are disclosed. The device includes a plurality of resistive switching memory units arranged in a matrix, each of which includes a switching element and a resistive switching device, and the switching element being connected to a word line... Agent:

20140347912 - Sense amplifier local feedback to control bit line voltage: Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include... Agent: Sandisk 3d LLC

20140347915 - Cmos image sensor with noise cancellation: A memory comprises a two dimensional array of memory cells. Each memory cell comprises a first transistor, a second transistor and a capacitor. A multi-bit datum is stored as one of a plurality of voltage signal levels driven over a vertical input signal line and further across a source and... Agent:

20140347916 - Eight transistor (8t) write assist static random access memory (sram) cell: Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS... Agent: Nvidia Corporation

20140347917 - Static random access memory structures: A static random access memory structure is provided. The static random access memory structure includes a storage region having a first storage node and a second storage node which is complementary to the first storage node. The static random access memory structure also includes a reading region having a first... Agent: Semiconductor Manufacturing International (shanghai) Corporation

20140347918 - Mram write pulses to dissipate intermediate state domains: A write method for a STT-RAM MTJ is disclosed that substantially reduces the bit error rate caused by intermediate domain states generated during write pulses. The method includes a plurality of “n” write periods or pulses and “n−1” domain dissipation periods where a domain dissipation period separates successive write periods.... Agent: Headway Technologies, Inc.

20140347919 - Semiconductor storage device: A semiconductor storage device includes: a memory cell array in which a plurality of pairs of bit lines and source lines, a plurality of word lines, and a plurality of resistance change memory cells are arranged; a write driver, a sense amplifier, a global bit line and a global source... Agent: Fujitsu Limited

20140347920 - Dual mode clock and data scheme for memory programming: A Phase-Change Memory (PCM) includes a factory programming interface to receive data changing on both a positive transition and a negative transition of a dual edge clock. A transition detector generated internal clock provides a delayed edge to latch the program data. This dual-edge clock scheme provides a doubling in... Agent:

20140347921 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes memory cell strings including selection transistors and memory cells coupled between the selection transistors, a peripheral circuit configured to apply an operating voltage to the memory cell strings during a read operation or a verify operation, and a control circuit configured to control the peripheral... Agent: Sk Hynix Inc.

20140347922 - Semiconductor memory device and method of operating the same: A method of operating a semiconductor memory device includes checking an erase-program cycling number, setting a target erase level to be maintained when the erase-program cycling number is less than a predetermined critical number, and setting the target erase level to be increased when the erase-program cycling number is greater... Agent: Sk Hynix Inc.

20140347924 - Data storage in analog memory cells across word lines using a non-integer number of bits per cell: A method for data storage includes accepting data for storage in an array of analog memory cells, which are arranged in rows associated with respective word lines. At least a first page of the data is stored in a first row of the array, and at least a second page... Agent:

20140347925 - Internal data load for non-volatile storage: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor... Agent:

20140347923 - Threshold voltage calibration using reference pattern detection: A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A... Agent: Seagate Technology LLC

20140347926 - Vertical memory with body connection: An embodiment of an apparatus includes a substrate, a body semiconductor, a vertical memory access line stack over the body semiconductor, and a body connection to the body semiconductor.... Agent:

20140347929 - Apparatuses and methods for transposing select gates: Apparatuses and methods for transposing select gates, such as in a computing system and/or memory device, are provided. One example apparatus can include a group of memory cells and select gates electrically coupled to the group of memory cells. The select gates are arranged such that a pair of select... Agent:

20140347928 - Low disturbance, power-consumption, and latency in nand read and program-verify operations: A HiNAND array with a hierarchical-BL scheme configured to divide a large global bit line (GBL) capacitance into J number of small local bit line (LBL) capacitances for reducing bit line precharge voltage and discharge time to achieve faster Read and Program-Verify speed, lower power consumption, lower latency, and lower... Agent:

20140347930 - Non-volative electronic memory device with nand structure being monolithically integrated on semiconductor: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory... Agent:

20140347927 - Nonvolatile memory device having split ground selection line structures: A nonvolatile memory device comprises a plurality of vertical NAND flash memory cells arranged in a three dimensional (3D) structure, a first memory block disposed in the 3D structure and having memory cells selected by a first ground selection line and a second ground selection line, wherein the first and... Agent:

20140347932 - Memory with three transistor memory cell device: Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access to the sense circuitry and page buffers by either... Agent: Micron Technology, Inc.

20140347931 - Writing into an eeprom on an i2c bus: An EEPROM circuit includes a data reception register and a column decoder. A buffer memory having a size corresponding to the size of a data page is included between the data reception register and the column decoder.... Agent: Stmicroelectronics (rousset) Sas

20140347934 - Memory devices having select gates with p type bodies, memory strings having separate source lines and methods: Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as... Agent:

20140347935 - Method of providing an operating voltage in a memory device and a memory controller for the memory device: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage... Agent:

20140347933 - Nor-based bcam/tcam cell and array with nand scalability: This invention discloses a 2T-string NOR-based CAM logic cell comprising two physical NAND cells connected in series with two horizontal WLs and one vertical BL and one vertical SL. Additionally, a sector of NOR-based CAM logic cell array is configured with N vertical cell strings each including M 2T-string NOR-based... Agent: Aplus Flash Technology, Inc.

20140347936 - Recovery of interfacial defects in memory cells: A group of non-volatile, solid state memory cells are transferred from an active list that includes memory cells accessible to a host to a temporary list that includes memory cells temporarily inaccessible to the host. The memory cells included in the temporary list are maintained at a temperature that is... Agent: Seagate Technology LLC

20140347937 - Semiconductor device and method of operating the same: A semiconductor device includes a memory block coupled to word lines and configured to a memory cell including a floating gate, an inter-poly dielectric and a control gate and a peripheral circuit configured to perform an erase loop operation, a program loop operation an electron injection operation of the memory... Agent: Sk Hynix Inc.

20140347938 - Semiconductor apparatus: A semiconductor apparatus includes an input buffer configured to buffer data inputted through a data input/output pad; a data input control unit configured to transfer an output of the input buffer to a data input/output line in response to a write clock; a test loop control unit configured to output... Agent: Sk Hynix Inc.

20140347940 - Semiconductor devices and semiconductor systems including the same: Semiconductor devices are provided. The semiconductor device includes a control signal generator and a first data input unit. The control signal generator generates an inverted control signal including a first bit and a second bit using a decoded signal in response to a test enable signal. The first data input... Agent: Sk Hynix Inc.

20140347939 - Semiconductor devices including pipe latch units and system including the same: The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data... Agent: Sk Hynix Inc.

20140347941 - Low latency synchronization scheme for mesochronous ddr system: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the... Agent: Qualcomm Incorporated

20140347942 - Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read... Agent:

20140347943 - Semiconductor package including stacked chips and method of fabricating the same: A semiconductor package includes first and second slave chips stacked vertically; and a master chip connected to the first and second slave chips, each of the slave chips including, a plurality of memory blocks, and a redundancy block, and the master chip including, a fuse block configured to repair a... Agent: Samsung Electronics Co., Ltd.

20140347944 - Methods and apparatuses for stacked device testing: Various embodiments include apparatus, systems, and methods having multiple dies arranged in a stack in which the dies or a logic chip in communication with the dies stores a flag for indicating whether a threshold number of cells of the dies have failed during test operations.... Agent: Micron Technology, Inc.

20140347945 - Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first... Agent: Micron Technology, Inc.

20140347947 - Apparatus and methods to provide power management for memory devices: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation... Agent:

20140347946 - Voltage regulator:

20140347948 - Apparatuses and methods for unit identification in a master/slave memory stack: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory... Agent:

20140347949 - Block selection circuit and semiconductor device having the same: A block selection circuit and a semiconductor device having the same may include a row decoder which includes a high voltage generating circuit configured to output a block selection voltage in response to upper addresses, switching circuits configured to receive the block selection voltage and aprecharge high voltage, and forward... Agent: Sk Hynix Inc.

20140347950 - Memory systems and methods for dividing physical memory locations into temporal memory locations: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies.... Agent:

20140347951 - Semiconductor memory device having sub word line driver and driving method thereof: A semiconductor memory device may include a memory cell array, a plurality of first sub word line drivers, and a plurality of second sub word line drivers. The memory cell array may comprise a plurality of sub cell arrays, a plurality of first word lines and a plurality of second... Agent:

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