|Static information storage and retrieval patents - Monitor Patents|
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Static information storage and retrievalBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 11/28/2013 > 57 patent applications in 34 patent subcategories.
20130314967 - Memory having buried digit lines and methods of making the same: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top... Agent: Micron Technology, Inc.
20130314968 - Offsetting clock package pins in a clamshell topology to improve signal integrity: The disclosed embodiments relate to the design of a memory system which includes a set of one or more memory modules, wherein each memory module in the set has a clamshell configuration, wherein pairs of opposing memory packages containing memory chips are located on opposite sides of the memory module.... Agent:
20130314969 - Nonvolatile semiconductor memory device: Each of m word lines is connected to n memory cells in a corresponding one of rows of m×n memory cells. Each of n bit lines is connected to m memory cells in a corresponding one of columns of m×n memory cells, and each of n source lines is connected... Agent: Panasonic Corporation
20130314970 - Pillar-shaped nonvolatile memory and method of fabrication: A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided.... Agent: Sandisk 3d LLC
20130314971 - Methods involving memory with high dielectric constant antifuses adapted for use at low voltage: Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which... Agent: Sandisk 3d LLC
20130314974 - Bipolar resistive-switching memory with a single diode per memory cell: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage... Agent: Intermolecular, Inc.
20130314973 - Memory cells, methods of programming memory cells, and methods of forming memory cells: Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A... Agent: Micron Technology, Inc.
20130314975 - Method for programming nonvolatile memory element, method for initializing nonvolatile memory element, and nonvolatile memory device: A method for programming a nonvolatile memory element includes: decreasing a resistance value of a variable resistance element in an initial state, by applying an initialization voltage pulse to a series circuit in which a load resistor having a first resistance value is connected in series with the variable resistance... Agent: Panasonic Corporation
20130314972 - Resistor thin film mtp memory: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one... Agent: Stmicroelectronics Pte Ltd.
20130314976 - Method for driving memory element: To provide a memory element which keeps a stored logic state even without supply of power. To increase an effect of reducing power consumption by facilitating stop of supply of power to the memory element for a short time. Data (potential) held in a node in a logic circuit can... Agent: Semiconductor Energy Laboratory Co., Ltd.
20130314977 - Memory circuit properly workable under low working voltage: A memory circuit properly workable under low working voltage includes a plurality of write word lines, a plurality of write bit lines, a plurality of read/write word lines, a plurality of read/write bit lines, a plurality of read/write inverted word lines, a plurality of virtual voltage source circuits, a plurality... Agent:
20130314978 - Low energy magnetic domain wall logic device: A logic gate device is disclosed. The logic gate device structure can include a magnetic tunnel junction on a soft ferromagnetic wire to provide a readout. One input contact can be at one end of the soft ferromagnetic wire and a second input contact can be at the other end... Agent: Massachusetts Institute Of Technology
20130314981 - Magnetic shift register memory device: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from... Agent: International Business Machines Corporation
20130314982 - Method for magnetic screening of arrays of magnetic memories: A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for... Agent: Avalanche Technology Inc.
20130314980 - Row-decoder circuit and method with dual power systems: A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied... Agent: Qualcomm Incorporated
20130314979 - Semiconductor memory device: A semiconductor memory device includes a memory cell unit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to provide a read value in response to an activated word line, a reference value generating unit including a plurality... Agent: Sk Hynix Inc.
20130314983 - Drift-insensitive or invariant material for phase change memory: A method of storing a bit at a memory device is disclosed. A memory cell the memory device is formed of a germanium-deficient chalcogenide glass configured to alternate between an amorphous phase and a crystalline phase upon application of a selected voltage, wherein a drift coefficient of the germanium-deficient chalcogenide... Agent: International Business Machines Corporation
20130314984 - Processors and systems using phase-change memory with and without bitline-sharing: Methods and systems for phase change memory having high RESET currents. In some sample embodiments, PCM elements share access devices in parallel between bit lines, permitting higher RESET currents to be shared between several access devices without overdriving. Lower individual current densities permit smaller access devices and smaller memories having... Agent: Being Advanced Memory Corporation
20130314985 - Spin logic based on persistent spin helices: A spin logic device which includes an electron confinement layer confining an electron gas in a two-dimensional area (2DEG) subtended by a direction x and a direction y, the latter perpendicular to the former. The spin logic device is configured for the 2DEG to support a persistent spin helix (PSH)... Agent: International Business Machines Corporation
20130314986 - Thyristors: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second... Agent: Micron Technology, Inc.
20130314987 - Ramping pass voltage to enhance channel boost in memory device: In a non-volatile storage system, first and second substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. The first and second substrate channel regions are created on either side of an isolation word line. During a program pulse time period in which a... Agent: Sandisk Technologies Inc.
20130314989 - Memory system: A memory system includes nonvolatile memory cells each configured to store more than one bit of data, dummy memory cells adjacent to the nonvolatile memory cells, and a control section that applies a read voltage to the nonvolatile memory cells while a first voltage is applied to a gate of... Agent: Kabushiki Kaisha Toshiba
20130314990 - Semiconductor memory device: According to one embodiment, the control circuit applies a pass potential to a first word line and a preliminary read-out potential to a second word line. The control circuit reads the data from the first memory cell transistor at a first condition when the second memory cell transistor has been... Agent: Kabushiki Kaisha Toshiba
20130314988 - Systems and methods of updating read voltages: A method includes, in a data storage device that includes a non-volatile memory, reading first data values from memory elements of the non-volatile memory using a set of reference voltages that includes a first reference voltage, and determining a first error count associated with the first reference voltage. The method... Agent: Sandisk Technologies Inc.
20130314991 - Semiconductor device: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On... Agent: Kabushiki Kaisha Toshiba
20130314993 - Programming rate identification and control in a solid state memory: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement... Agent: Micron Technology, Inc.
20130314992 - Semiconductor memory and method of controlling the same: According to one embodiment, a memory includes main and redundancy regions including cells, first units in the main region, second units in the redundancy region, a column control circuit configured to selects the first units using a first pointer corresponding to an address signal, and selects the second unit using... Agent:
20130314994 - Nonvolatile semiconductor memory device: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the... Agent: Kabushiki Kaisha Toshiba
20130314995 - Controlling dummy word line bias during erase in non-volatile memory: A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering... Agent:
20130314997 - Memory access method and flash memory using the same: A memory access method is applied in a memory controller for accessing a memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes: enabling the string select signal and disabling the string select signal before a read phase.... Agent: Macronix International Co., Ltd.
20130314996 - Nonvolatile semiconductor storage device: According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a cell well in a row direction and a column direction in a matrix; word lines which select the memory cell in the row direction; bit lines which select the... Agent: Kabushiki Kaisha Toshiba
20130314998 - Enhanced glitch filter: A glitch circuit includes an SR flip-flop where a received input clock is operatively coupled to set and reset inputs of the flip-flop, respectively. A configurable delay circuit receives an input signal, and an output of the delay circuit provides a delayed signal. The configurable delay circuit includes a plurality... Agent:
20130314999 - Flash memory device and reading method thereof: A flash memory device and reading method of the flash memory device. The reading method includes determining a read voltage set of memory cells corresponding to a first word line from at least one of flag cell data of the first word line and flag cell data of a second... Agent: Samsung Electronics Co., Ltd
20130315002 - Methods and devices for determining sensing voltages: The present disclosure includes methods and devices for determining sensing voltages. One such method includes comparing data associated with a number of template distributions to data associated with a first threshold voltage distribution and a second threshold voltage distribution associated with a number of memory cells programmed to particular adjacent... Agent: Micron Technology, Inc.
20130315001 - Semiconductor memory column decoder device and method: Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row... Agent: Micron Technology, Inc.
20130315000 - Techniques for providing a direct injection semiconductor memory device: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source... Agent: Micron Technology, Inc.
20130315003 - Memory device and method for verifying the same: A memory includes a cell string including a plurality of memory cells connected in series, a bit line connected to the cell string, a voltage transfer unit configured to electrically connect the bit line and a sensing node in response to a control signal, and a page buffer configured to... Agent:
20130315011 - Semiconductor device and driving method thereof: A semiconductor device in which a nonvolatile memory can normally operate and power saving can be performed with a P-state function, and a driving method of the semiconductor device are provided. The semiconductor device includes: a first circuit configured to control a state including a driving voltage and a clock... Agent: Semiconductor Energy Laboratory Co., Ltd.
20130315012 - Semiconductor memory device, and method of controlling the same: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low... Agent: Fujitsu Semiconductor Limited
20130315004 - Semiconductor device, a method for manufacturing the same, and a system having the same: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and... Agent:
20130315005 - Input buffer: An input buffer which includes an amplification circuit configured to amplify a difference between a first input signal and a second input signal; and an inverter configured to invert an output signal of the amplification circuit. The amplification circuit provides the inverter with a bias voltage generated on the basis... Agent: Samsung Electronics Co., Ltd
20130315006 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device includes a plurality of latches for storing data, a set/reset circuit for transferring data, stored in a selected latch of the latches, to a common node, a transmission circuit for transferring the data of the common node to a first sense node, a bit line transmission... Agent: Sk Hynix Inc.
20130315008 - Period signal generation circuit: A period signal generation circuit includes a first discharger configured to discharge first current having a constant value from a control node in response to a temperature signal; and a second discharger configured to discharge second current varying according to an internal temperature thereof from the control node in response... Agent: Sk Hynix Inc.
20130315009 - Period signal generation circuit: A period signal generation circuit includes a first discharger configured to discharge first current from a control node which is driven in response to a first reference voltage, and a second discharger configured to discharge second current from the control node. The total current of the first and second currents... Agent: Sk Hynix Inc.
20130315010 - Period signal generation circuits: A period signal generation circuit includes a period signal generator configured to alternately charge and discharge a control node according to a level of the control node to generate a period signal, a discharge controller configured to discharge a first current having a constant value from the control node in... Agent: Sk Hynix Inc.
20130315007 - Test circuit and method of semiconductor memory apparatus: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one... Agent: Sk Hynix Inc.
20130315013 - Memory device: A memory device includes a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array... Agent:
20130315014 - Method and apparatus for memory access delay training: Various method and apparatus embodiments for training a delay for enabling a data strobe signal in a memory subsystem are disclosed. In one embodiment, a system includes a memory controller configured to receive a data strobe signal. The memory controller includes a training circuit. The training circuit includes a first... Agent:
20130315015 - Semiconductor apparatus, method for delaying signal thereof, stacked semiconductor memory apparatus, and method for generating signal thereof: The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal;... Agent: Sk Hynix Inc.
20130315016 - Column repair circuit: A column repair circuit of a semiconductor memory apparatus includes a plurality of mats and performs a column repair operation to replace failed cells among a plurality of memory cells provided in the mats. The column repair circuit includes two or more fuse units configured to perform the column repair... Agent: Sk Hynix Inc.
20130315017 - Sense amplifier control circuit and semiconductor memory device including the same: A sense amplifier control circuit according to the present invention is disposed in a bit line sense amplifier (BLSA) array region including a plurality of BLSAs and is configured to supply a precharge voltage to the plurality of BLSAs in response to a control signal.... Agent: Sk Hynix Inc.
20130315018 - Sense amplifier ciruit and semiconductor device: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate... Agent: Elpida Memory, Inc.
20130315019 - Refresh circuits: A refresh circuit includes a period signal generation circuit configured to drive a control node according to a level of the control node, discharge first and second currents from the control node in response to the first temperature signal, and generate a period signal, a division signal generator configured to... Agent: Sk Hynix Inc.
20130315020 - Semiconductor memory device, and method of controlling the same: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low... Agent: Fujitsu Semiconductor Limited
20130315021 - Semiconductor device and method for driving semiconductor device: A semiconductor device capable of simply performing power gating and a driving method thereof are provided. Power gating is started passively (automatically in the case of satisfying predetermined conditions). Specifically, the semiconductor device includes a transistor for selecting whether a power source voltage is supplied or not to a functional... Agent: Semiconductor Energy Laboratory Co., Ltd.
20130315022 - Multi-bank random access memory structure with global and local signal buffering for improved performance: Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or... Agent: International Business Machines Corporation
20130315023 - Column select signal generation circuit: A column select signal generation circuit includes: a first current controller configured to control the level of a pre-column select signal in response to a bank active signal, a driver configured to generate an amplified column select signal in response to the pre-column select signal, and a second current controller... Agent: Sk Hynix Inc.11/21/2013 > 48 patent applications in 28 patent subcategories.
20130308363 - Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines: A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of... Agent: Sandisk 3d LLC
20130308365 - Circuit and method for reducing write disturb in a non-volatile memory device: An active precharge circuit for a non-volatile memory array which minimizes write disturb to non-selected memory cells during programming is disclosed. In a programming cycle, all bitlines are pre-charged to a program inhibit voltage level and held at the program inhibit voltage level with current or voltage sources coupled to... Agent: Sidense Corp.
20130308366 - Circuit and system of using junction diode as program selector for one-time programmable devices: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can... Agent:
20130308364 - Power up detection system for a memory device: A power up detection method for a memory device and a memory device are disclosed. In a first phase, a test word is read from a read-only memory (ROM) row of a memory array of the memory device, and the test word is compared to predetermined ROM row data. If... Agent: Sidense Corp.
20130308370 - Memory device and system with improved erase operation: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory... Agent:
20130308371 - Method for reading data from nonvolatile storage element, and nonvolatile storage device: Provided is a method for reading data from a variable resistance nonvolatile storage element, where the operation for reading data is less susceptible to a fluctuation phenomenon of resistance values in reading the data. The method includes: detecting a current value Iread that flows through the nonvolatile storage element that... Agent:
20130308368 - Semiconductor memory device: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections... Agent:
20130308367 - Structure and method for forming conductive path in resistive random-access memory device: An array and forming method for resistive-RAM (RRAM) devices provides for the simultaneous selection of multiple bit cells and the simultaneous forming of the RRAM resistive elements within the selected bit cells. The bit cells each include a resistive element and a transistor and are arranged vertically along vertical bit... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20130308369 - Switching device having a non-linear element: Method for a memory including a first, second, third and fourth cells include applying a read, program, or erase voltage, the first and second cells coupled to a first top interconnect, the third and fourth cells coupled to a second top interconnect, the first and third cells coupled to a... Agent:
20130308372 - Storage device and writing method of the same: A storage device in which held voltage is prevented from decreasing due to feedthrough in writing data to the storage device at high voltage is provided. The storage device includes a write circuit, a bit line, a word line, a transistor, and a capacitor. A gate of the transistor is... Agent: Semiconductor Energy Laboratory Co., Ltd.
20130308374 - Circuit and method for controlling mram cell bias voltages: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature,... Agent: Everspin Technologies, Inc.
20130308373 - Nonvolatile latch circuit: One embodiment of a nonvolatile latch circuit comprises a latch circuitry configurated to temporarily hold data and comprising a first output terminal, the latch circuitry is coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal, and a... Agent:
20130308375 - Semiconductor integrated circuit for low and high voltage operations: A semiconductor integrated circuit comprising a first circuit area for a low voltage operation and a second circuit area for a high voltage operation. The circuit areas comprise two vertically stacked backend patterned metal layers that are separated by an inter-metallic dielectric (IMD). The two metal layers and the IMD... Agent: Magsil Corporation
20130308376 - Apparatuses including current compliance circuits and methods: Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits that are configured to dynamically adjust a current passing through a variable resistance material during a memory operation. Some configurations utilize components within an array of memory cells to form... Agent:
20130308378 - Electric element: A temperature dependent electric element includes a phase change portion including at least one conductive phase change material having a predetermined phase transition temperature, a detector portion configured to detect a change in conductivity of the phase change material caused by a temperature change to a detect phase transition of... Agent:
20130308377 - Sensing circuits and phase change memory devices including the same: A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents... Agent: Samsung Electronics Co., Ltd.
20130308379 - Semiconductor device with electrically floating body: A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region, and a gate is disposed over a first portion of the body region. The device includes a source region adjoining a second portion of the... Agent: Micron Technology, Inc.
20130308381 - Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling: A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a... Agent: Sandisk Il Ltd.
20130308380 - Non-volatile semiconductor memory device and reading method thereof: Provided are a semiconductor memory device has improved read disturbance characteristics as well as improved retention characteristics at a high temperature, and a reading method thereof. The non-volatile semiconductor memory device includes at least one bit line; and a cell string configured to be coupled with the bit line respectively,... Agent:
20130308382 - Non-volatile memory device: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor.... Agent: Samsung Electronics Co., Ltd.
20130308383 - Hybrid volatile and non-volatile memory device: A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed... Agent: Rambus, Inc.
20130308384 - Non-volatile semiconductor memory device capable of improving failure-relief efficiency: According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a... Agent:
20130308385 - Apparatuses and methods for coupling load current to a common source: Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source.... Agent:
20130308386 - Nonvolatile semiconductor memory device: A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage;... Agent: Kabushiki Kaisha Toshiba
20130308388 - Apparatus and method for reduced peak power consumption during common operation of multi-nand flash memory devices: System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least... Agent: Micron Technology, Inc.
20130308387 - Memory read apparatus and methods: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one... Agent:
20130308389 - Word line kicking when sensing non-volatile storage: Methods and devices for sensing non-volatile storage are disclosed. Technology disclosed herein reduces the time for sensing operations of non-volatile storage such as read and program verify. In one embodiment, a kicking voltage is applied to a selected word line during a sensing operation. The kicking voltage may be applied... Agent: Sandisk Technologies Inc.
20130308390 - Method and apparatus for programming data in non-volatile memory device: A method and an apparatus for programming data, and a method and an apparatus for setting a data programming mode used for the same are provided. The method for programming data in a non-volatile memory device includes determining a programming mode to be used for data programming among at least... Agent: Samsung Electronics Co., Ltd.
20130308391 - Method of programming non-volatile memory device and non-volatile memory device using the same: A program method of a nonvolatile memory device according to example embodiments includes a operation (a) of detecting a level of a program voltage; and a operation (b) of providing a unselected word line voltage and a bit line precharge voltage having a variable level respectively according to the detected... Agent: Samsung Electronics Co., Ltd.
20130308392 - Memory device and method for driving memory device: A memory device in which one memory cell can operate in both a single-level cell mode and a multi-level cell mode includes a signal transmission path for a multi-level cell mode in which a multi-bit digital signal representing any of three or more states input to the memory circuit is... Agent: Semiconductor Energy Laboratory Co., Ltd.
20130308395 - Data output circuit and semiconductor memory device: A semiconductor memory device including internally generated control signals that help to ensure that buffered and amplified data from a memory cell is properly presented to a global line independent of the enable period of the internally generated enable signal EN. in the semiconductor memory device in accordance with an... Agent: Sk Hynix Inc.
20130308393 - Non-volatile memory device and method for driving the same: A non-volatile memory device includes a memory cell block programmed with data, a page buffer block configured to perform a program verification operation for verifying the data on a verification target memory cell as many times as a predetermined number, and temporarily store a plurality of verification result data obtained... Agent:
20130308394 - Refresh method and semiconductor memory device using the same: A semiconductor memory device includes an all bank select signal generation block configured to receive level signals including information on at least one bank which has been refreshed, and generate all bank select signals, in response to an all bank refresh command; and a bank block including a plurality of... Agent: Sk Hynix Inc.
20130308396 - Driver for semiconductor memory and method thereof: A driver for a semiconductor memory includes: a selection controller configured to output a target charge current select signal and a bucket charge current select signal in response to an inputted memory cell address and a target charge current value and a bucket charge current value, which are to be... Agent: Sk Hynix Inc.
20130308397 - Read self timing circuitry for self-timed memory: A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference wordline driver. Self-timing is effectuated by detecting completion of reference true bitline discharge in the timer cells resulting... Agent: Stmicroelectronics Pvt. Ltd.
20130308398 - Memory device having control circuitry configured for clock-based write self-time tracking: A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of... Agent: Lsi Corporation
20130308400 - Write control device: A write control device includes a switching unit configured to selectively supply a write current in response to a driving control signal, a driving unit configured to supply a driving current to a memory cell corresponding to the write current applied through the switching unit, and an over-driving control unit... Agent: Sk Hynix Inc.
20130308399 - Write self timing circuitry for self-timed memory: A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by... Agent: Stmicroelectronics Pvt. Ltd.
20130308401 - Semiconductor memory device: A semiconductor memory device includes an internal signal generation block configured to generate a control signal which is enabled from a generation time of an internal active signal enabled if it is determined that a combination of external commands in synchronization with a rising edge of an external clock inputted... Agent: Sk Hynix Inc.
20130308402 - Test flow to detect a latent leaky bit of a non-volatile memory: A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally,... Agent: Freescale Semiconductor, Inc.
20130308403 - Semiconductor device having sense amplifier circuit: Disclosed herein is a device that includes: a first control element that controls an amount of current flowing between a second line and a first node according to a potential of a first line; a second control element that controls an amount of current flowing between the first line and... Agent: Elpida Memory, Inc.
20130308404 - Circuit for sensing multi-level cell: A circuit for sensing a multi-level cell (MLC) comprises a first switch associated with a first read bit, a second switch associated with a second read bit, a first switch control unit to control the first switch in response to a first data bit from a counter, and a second... Agent: Elite Semiconductor Memory Technology Inc.
20130308406 - Semiconductor device, method for operating the same, and memory system including the same: A semiconductor device includes a clock supply circuit configured to generate an internal clock by using an external clock, an internal circuit configured to operate in synchronization with the internal clock and enter a power-down mode in response to a power-down signal, and a controller configured to control an entry... Agent: Sk Hynix Inc.
20130308405 - Semiconductor memory device controlling refresh cycle, memory system, and method of operating the semiconductor memory device: A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh... Agent:
20130308407 - Controlling a voltage level of an access signal to reduce access disturbs in semiconductor memories: A semiconductor memory storage device having a plurality of storage cells for storing data, each storage cell comprising an access control device and access control circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding... Agent: Arm Limited
20130308408 - Input buffer: An input buffer includes a first buffer circuit to amplify a difference between a first input signal and a second input signal; a second buffer circuit formed of a replica circuit of the first buffer circuit to generate a common mode output signal in response to the first input signal;... Agent: Samsung Electronics Co., Ltd.
20130308409 - Integrated circuit device, power management module and method for providing power management: An integrated circuit device comprising at least one memory module comprising a plurality of memory sub-modules, and at least one power management module arranged to provide power management for the at least one memory module. The at least one power management module is arranged to determine when content of at... Agent: Freescale Semiconductor Inc. A Corporation
20130308410 - High voltage switching circuitry for a cross-point array: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit... Agent: Unity Semiconductor Corporation11/14/2013 > 45 patent applications in 28 patent subcategories.
20130301332 - Semiconductor device: To provide a semiconductor device with high reliability in operation, in which data in a volatile memory can be saved to a non-volatile memory. For example, the semiconductor device includes an SRAM provided with first and second data storage portions and a non-volatile memory provided with third and fourth data... Agent: Semiconductor Energy Laboratory Co., Ltd.
20130301331 - Semiconductor device and driving method of semiconductor device: To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data... Agent: Semiconductor Energy Laboratory Co., Ltd.
20130301330 - Semiconductor device having hierarchical bit line structure: A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power... Agent: Elpida Memory, Inc.
20130301333 - Photonic quantum memory: A photonic quantum memory is provided. The photonic quantum memory includes entanglement basis conversion module configured to receive a first polarization-entangled photon pair and to produce a second entangled photon pair. The second polarization-entangled photon pair can he a time-bin entangled or a propagation direction-entangled photon pair. The photonic quantum... Agent: The Mitre Corporation
20130301335 - Architecture, system and method for testing resistive type memory: Example embodiments include a method for massive parallel stress testing of resistive type memories. The method can include, for example, disabling one or more internal analog voltage generators, configuring memory circuitry to use a common plane voltage (VCP) pad or external pin, connecting bit lines of the memory device to... Agent:
20130301340 - Erasing method of resistive random access memory: An erase method of a resistive random access memory which includes a plurality of cell strings, each having a plurality of memory cells and a string selection transistor, includes applying a first voltage to bit lines connected with string selection transistors of the plurality of cell strings, applying a turn-on... Agent: Samsung Electronics Co., Ltd.
20130301341 - Hereto resistive switching material layer in rram device and method: A non-volatile memory device includes a first electrode, a resistive switching material stack overlying the first electrode. The resistive switching material stack comprising a first resistive switching material and a second resistive switching material. The second resistive switching material overlies the first electrode and the first resistive switching material overlying... Agent: Crossbar, Inc.
20130301338 - Hybrid resistive memory devices and methods of operating and manufacturing the same: Hybrid resistive memory devices and methods of operating and manufacturing the same, include at least two resistive memory units. At least one of the at least two resistive memory units is a resistive memory unit configured to operate in a long-term plasticity state.... Agent: Samsung Electronics Co., Ltd.
20130301342 - Memory element, stacking, memory matrix and method for operation: Disclosed is a memory element, a stack, and to a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The... Agent: Forschungszentrum Juelich Gmbh
20130301334 - Methods, articles and devices for pulse adjustments to program a memory cell: Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.... Agent: Micron Technology, Inc.
20130301336 - Permutational memory cells: Various embodiments comprise apparatuses having at least two resistance change memory (RCM) cells. In one embodiment, an apparatus includes at least two electrical contacts coupled to each of the RCM cells. A memory cell material is disposed between pairs of each of the electrical contacts coupled to each of the... Agent: Micron Technology, Inc.
20130301337 - Resistive devices and methods of operation thereof: In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The... Agent: Adesto Technologies Corporation
20130301339 - Semiconductor memory device: A control circuit controls a voltage applied to a memory cell array. A first electrode contacts to a first surface of a variable resistance element, while a second electrode contacts to a second surface of the variable resistance element. The first electrode is configured by a metal, and the second... Agent: Kabushiki Kaisha Toshiba
20130301344 - Multiple-port memory device comprising single-port memory device with supporting control circuitry: An apparatus comprises a clock generator, first and second memory drivers and a multiple-port memory device having at least first and second ports configured to receive input signals from and supply output signals to respective ones of the first and second memory drivers, the multiple-port memory device further comprising a... Agent:
20130301343 - Threshold voltage measurement device: A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage... Agent:
20130301345 - Magnetic random access memory and memory system: According to one embodiment, a magnetic random access memory includes a write circuit to write s-bit (s is a natural number equal to 2 or greater) write data to magnetoresistive elements, and a read circuit to read s-bit read data from the magnetoresistive elements. The control circuit is configured to... Agent: Kabushiki Kaisha Toshiba
20130301346 - Self referencing sense amplifier for spin torque mram: Circuitry and a method provide self-referenced sensing of a resistive memory cell by using its characteristic of resistance variation with applied voltage in one state versus a relatively constant resistance regardless of the applied voltage in its opposite state. Based on an initial bias state with equalized resistances, a current... Agent: Everspin Technologies, Inc.
20130301347 - Shared bit line smt mram array with shunting transistors between bit lines: An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair... Agent:
20130301348 - Row decoder circuit for a phase change non-volatile memory device: A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage... Agent: Stmicroelectronics S.r.l.
20130301349 - Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of... Agent:
20130301350 - Vertical structure nonvolatile memory device: A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one... Agent:
20130301351 - Channel boosting using secondary neighbor channel coupling in non-volatile memory: In a non-volatile storage system, a programming portion of a program-verify iteration has multiple programming pulses, and storage elements along a word line are selected for programming according to a pattern. Unselected storage elements are grouped to benefit from channel-to-channel capacitive coupling from both primary and secondary neighbor storage elements.... Agent:
20130301352 - Method of programming a nonvolatile memory device and nonvolatile memory device performing the method: A method of programming a nonvolatile memory device including multi-level cells that store multi-bit data, includes performing a pre-programming operation that programs at least some of the multi-level cells to a plurality of intermediate states which are different from an erased state, and performing a main programming operation that programs... Agent: Samsung Electronics Co., Ltd.
20130301353 - Methods of driving a memory: Methods of driving a memory include erasing a plurality of memory cells of a memory device, testing whether the memory cells have been erased, and programming the memory cells without erasing the memory cells again if more than a predetermined percentage of the memory cells, but less than all of... Agent: Samsung Electronics Co., Ltd.
20130301354 - Semiconductor memory device: A semiconductor memory device includes memory cells and a voltage generating circuit for generating a voltage for memory cells. The first voltage generating circuit includes a first diode connected between first and second nodes, a first transistor connected between the output terminal and a third node and having a gate... Agent: Kabushiki Kaisha Toshiba
20130301355 - Eeprom memory unit and eeprom memory device: An EEPROM memory unit is disclosed. The EEPROM memory unit includes a first memory cell, a second memory cell, and a word line controller. The first memory cell includes a source that is connected to a first bit line of the EEPROM memory unit and a drain that is connected... Agent: Grace Semiconductor Manufacturing Corporation
20130301357 - Reducing noise in semiconductor devices: The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the... Agent:
20130301356 - Semiconductor device with one-time programmable memory cell including anti-fuse with maetal/polycide gate: A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating... Agent:
20130301358 - Bit line bl isolation scheme during erase operation for non-volatile storage: A system for erasing non-volatile storage system that reduces the voltage across the transistor that interfaces between the sense amplifier and the bit line so that the transistor can be made smaller. Additionally, the use of the lower voltage allows for various components to be positioned closer to each other.... Agent: Sandisk Technologies, Inc.
20130301359 - Non-volatile semiconductor storage device: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase... Agent:
20130301360 - Data storage in analog memory cells using modified pass voltages: A method for data storage includes storing data in a target analog memory cell, which is one of a group of analog memory cells that are connected in series with one another, by writing a storage value into the target memory cell. The storage value written into the target memory... Agent:
20130301362 - Pulse-based memory read-out: A pulse-based memory read-out device, including: a pulse generator at a first end of a bit line and a detector at a second end of the bit line. The pulse generator is configured to send an electrical pulse along the bit line from the first end of the bit line.... Agent: Nxp B.v.
20130301361 - Row driver architecture: Devices and circuits for row driver in a memory device. The proposed row driver circuit architectures may reduce size of the row driver circuitry and enhance the row driver circuit's reliability. Specifically, the proposed embodiments of the row driver may reduce the required sizing of the boosting capacitor or alternatively... Agent: Elpida Memory, Inc.
20130301363 - Semiconductor memory device and method of driving semiconductor memory device: Upon programming a semiconductor memory device including a first and a second n-wells, a first and a second p-channel memory transistors respectively formed in the first and the second n-wells, and a bit line connected to a drain of the first p-channel transistor and a drain of the second p-channel... Agent: Fujitsu Semiconductor Limited
20130301366 - Semiconductor memory device and method of operating the same: A semiconductor memory device of the present invention includes a memory cell array with cell strings having word lines stacked on a substrate and a vertical channel layer formed through the word lines, a peripheral circuit configured to select one of the word lines and perform a program operation on... Agent: Sk Hynix Inc.
20130301364 - Sense amplifier ciruit and semiconductor device: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate... Agent:
20130301365 - Dedicated reference voltage generation circuit for memory: A memory includes a data pin, an address pin, and a reference voltage generation circuit. The reference voltage generation circuit includes a first reference voltage generation circuit and a second reference voltage generation circuit. The first reference voltage generation circuit is electronically connected to the data pin, and supplies a... Agent:
20130301367 - Semiconductor device: An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an... Agent:
20130301368 - Supporting calibration for sub-rate operation in clocked memory systems: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate... Agent: Rambus Inc.
20130301369 - Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs: A method of self-testing and self-repairing a random access memory (RAM) is includes collecting failure data of the RAM with redundant rows and columns, wherein the failure data of all failed cells of the RAM are stored in two failure bit map (FBM) data structures. The method further includes performing... Agent:
20130301370 - Semiconductor device having hierarchically structured bit lines and system including the same: A device includes first memory blocks each including a first local bit line, first memory cells connected to the first local bit line and a first hierarchy switch connected between a first global bit line and the first local bit line, a dummy global bit line connected to the second... Agent:
20130301371 - Dynamic random access memory with multiple thermal sensors disposed therein and control method thereof: A dynamic random access memory (DRAM) with multiple thermal sensors disposed therein and a control method for the DRAM. A DRAM in accordance with an exemplary embodiment of the invention provides multi-zone temperature detection. The DRAM comprises a plurality of banks, a plurality of thermal sensors and a control unit.... Agent: Nanya Technology Corporation
20130301372 - Memory device, memory system, and power management method: A power management method includes receiving a first command with first address indicating a first high power operation that is immediately executed in a first memory die, after receipt of the first command, receiving a second command with a second address indicating a second high power operation, such that an... Agent: Samsung Electronics Co., Ltd.
20130301373 - Memory chip power management: A power supply voltage for a memory chip is compared with a plurality of threshold voltages that correspond to voltages below which classes of memory operations can no longer be guaranteed. When the power supply voltage drops below a threshold voltage, appropriate action is taken, which may include generating an... Agent:
20130301374 - Word line driver having a control switch: A word line driver including a control switch configured to receive a control signal, where the control switch is between a first node configured to receive an operating voltage signal and a second node configured to determine an output of the word line driver. The word line driver further includes... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.11/07/2013 > 56 patent applications in 31 patent subcategories.
20130294131 - Magnetic memory devices and systems: A method of storing one or more bits of information comprising: forming a magnetic bubble; and storing a said bit of information encoded in a typology of a domain wall of said magnetic bubble. Preferably a bit is encoded using a symmetric topological state of the domain wall and a... Agent:
20130294132 - Memory arrays: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into... Agent:
20130294133 - Semiconductor device: A semiconductor device includes: an I/O circuit configured to input/output a data signal; a plurality of internal circuits configured to transmit and receive the data signal to/from the I/O circuit; and a path provider configured to select one of a direct path to a target internal circuit or an indirect... Agent:
20130294135 - Semiconductor device having hierarchically structured bit lines and system including the same: A system includes a first circuit, a second circuit including a logic circuit, and a bus interconnecting the first and second circuits to each other so that the second circuit accesses the first circuit to perform a data transfer therebetween, wherein the first circuit includes a first sense amplifier array... Agent:
20130294134 - Stacked layer type semiconductor device and semiconductor system including the same: A stacked layer type semiconductor device includes N memories each including at least one main via and (N−1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N... Agent:
20130294136 - Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass... Agent:
20130294137 - Semiconductor device having bit line hierarchically structured: Disclosed herein is a semiconductor device that includes a plurality of memory cells; a local bit line coupled to the memory cells; a global bit line; and a first switch circuit coupled between the global bit line and the local bit line, the first switch circuit electrically connecting the local... Agent: Elpida Memory, Inc.
20130294138 - Shift register memory device, shift register, and data storage method: A shift register memory device includes a shift register, program/read element, and rotating force application unit. The shift register includes plural rotors arranged along a direction with uniaxial anisotropy. Each rotor has a characteristic direction rotatable around a rotational axis extending in the direction. The program/read element can program data... Agent:
20130294139 - Circuits configured to remain in a non-program state during a power-down event: In a particular embodiment, an apparatus includes a one-time programmable (OTP) memory circuit configured to be responsive to a programming voltage. The OTP memory circuit includes an OTP memory array including OTP memory cells, a first power switch configured to decouple the OTP memory array from the programming voltage, and... Agent: Qualcomm Incorporated
20130294140 - Anti-fuse circuit in which anti-fuse cell data is monitored, and semiconductor device including the same: An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse... Agent: Samsung Electronics Co., Ltd.
20130294143 - Built-in self test for one-time-programmable memory: An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The... Agent:
20130294141 - Memory device including antifuse memory cell array and memory system including the memory device: A memory device includes a memory cell array, a column decoder, and a row decoder. The row decoder includes a first word line driver and a second word line driver. The first word line driver is configured to electrically coupled to a first set of antifuse memory cells coupled to... Agent: Samsung Electronics Co., Ltd.
20130294142 - Method for controlling the breakdown of an antifuse memory cell: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.... Agent:
20130294144 - Method for bit-error rate testing of resistance-based ram cells using a reflected signal: A testing method is described for performing a fast bit-error rate (BER) measurement on resistance-based RAM cells, such MTJ cells, at the wafer or chip level. Embodiments use one or more specially designed test memory cells fabricated with direct electrical connections between the two electrodes of the cell and external... Agent:
20130294147 - Resistance change memory: A memory includes memory cells each includes a resistance change element and a diode, and each memory cell between one of row lines and one of column lines, a first decoder which selects one of the row lines as a selected row line, a second decoder which selects one of... Agent:
20130294146 - Resistive memory device and method of fabricating the same: A resistive memory device according to an embodiment includes a plurality of word lines extended and formed in a first direction; a global word line signal line extended substantially in the first direction, formed substantially in a layer substantially identical with the word lines, and interposed substantially between a designated... Agent: Sk Hynix Inc.
20130294148 - Resistive memory sensing methods and devices: The present disclosure includes resistive memory sensing methods and devices. One such method includes performing a voltage based multiple pass sensing operation on a group of cells coupled to a selected conductive line of an array of resistive memory cells. The voltage based multiple pass sensing operation can include providing... Agent:
20130294145 - Switching device structures and methods: Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a second electrode. The switching device can further include a third electrode coupled to the vertical stack and configured to receive a voltage applied thereto to... Agent: Micron Technology, Inc.
20130294149 - Reducing power in sram using supply voltage control: An embodiment of the invention provides a method for decreasing power in a static random access memory (SRAM). A first voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are column addressed during a read cycle. A second voltage is applied between... Agent: Texas Instruments Incorporated
20130294151 - Magnetic memory devices and methods of operating the same: A magnetic memory device includes: a free layer for storing information; and a reference layer disposed on a first surface of the free layer. The reference layer includes at least two magnetic domains and a magnetic domain wall between the at least two magnetic domains. The reference layer extends past... Agent:
20130294150 - Method and apparatus for testing a resistive memory element: Methods and apparatus for testing a resistive memory element are provided. In an example, an initial test resistor in a resistance network coupled to a first input of a sense amplifier is selected, where the resistive memory element is coupled. to a second input of the sense amplifier and an... Agent: Qualcomm Incorporated
20130294152 - Apparatuses and methods including memory access in cross point memory: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a... Agent:
20130294153 - Apparatuses and methods including supply current in memory: Some embodiments include apparatuses and methods having first conductive lines, second conductive lines, a memory array including memory cells, each of the memory cells coupled between one of the first conductive lines and one of the second conductive lines. At least one of such apparatuses and methods can include a... Agent: Micron Technology, Inc.
20130294154 - Semiconductor memory device: A semiconductor memory device is disclosed, which relates to a technology for a serial cell structure of a phase change memory (PCM). The semiconductor memory device includes a plurality of unit cells stacked with a plurality of layers, and a single bit line formed to have a vertical structure and... Agent: Sk Hynix Inc.
20130294156 - Memory kink checking: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line.... Agent:
20130294155 - Plural operation of memory device: An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data... Agent:
20130294159 - Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array: Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping... Agent:
20130294158 - Multi-level cell memory devices and methods of storing data in and reading data from the memory devices: A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order... Agent:
20130294157 - Reading data from multi-level cell memory: A method at a data storage device includes determining a first hard bit of a first logical page, the first hard bit corresponding to a particular cell of the MLC memory. A second hard bit of a second logical page is sensed. The second hard bit corresponds to the particular... Agent: Sandisk Technologies Inc.
20130294160 - Semiconductor memory device using only single-channel transistor to apply voltage to selected word line: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A... Agent:
20130294161 - Low-voltage fast-write nvsram cell: This invention discloses several embodiments of a low-voltage fast-write NVSRAM cells, made of either of a 2-poly floating-gate type flash cell or a 1-poly charge-trapping SONOS or MONOS flash cell with improvement by adding a Bridge circuit. This Bridge circuit is preferably inserted between each LV 6T SRAM cell and... Agent: Aplus Flash Technology, Inc.
20130294162 - Column redundancy circuitry for non-volatile memory: In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to... Agent:
20130294163 - Flash-based memory system with robust backup and restart features and removable modules: A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure.... Agent:
20130294164 - Nonvolatile semiconductor memory having a word line bent towards a select gate line side: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select... Agent:
20130294167 - Erase inhibit for 3d non-volatile memory: An erase process for a 3D stacked memory device performs a two-sided erase of NAND strings until one of more of the NAND strings passes an erase-verify test, then a one-sided erase of the remaining NAND strings is performed. The two-sided erase charges up the body of a NAND string... Agent:
20130294166 - Non-volatile memory device and method for driving the same: A non-volatile memory device and a method for driving the same are disclosed. During a precharge operation, the bit line is precharged on the basis of a voltage applied to a common source line. The bit line is precharged or not precharged based on whether or not a selected memory... Agent: Sk Hynix Inc.
20130294168 - Non-volatile semiconductor memory device: According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality of physical blocks. Each of the plurality of physical blocks includes a plurality of string units. Each string unit has a plurality of NAND strings... Agent:
20130294165 - Semiconductor memory device, memory system including the same and control method thereof: A semiconductor memory device includes first cell strings connected to first bit lines and second cell strings connected to second bit lines corresponding to the first bit lines, respectively. Data is stored in memory cells of the first cell strings, and the second cell strings are configured as a data... Agent: Sk Hynix Inc.
20130294169 - Simultaneous multi-level binary search in non-volatile storage: Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a... Agent:
20130294171 - Semiconductor integrated circuit and semiconductor physical quantity sensor device: In aspects of the invention, an auxiliary memory circuit includes a shift register wherein a plurality of flip-flops are cascade-connected and a plurality of inversion circuits that invert and output outputs of each D flip-flop. A main memory circuit includes a switch, which acts in accordance with a signal from... Agent:
20130294170 - Switch and semiconductor device including the switch: A device includes a first transistor coupled between first and second nodes, and including a control gate supplied with a first control signal, a second transistor coupled between the first node and a third node, and including a control gate supplied with the first control signal, a third transistor coupled... Agent: Elpida Memory, Inc.
20130294172 - Non-volatile memory (nvm) and method for manufacturing thereof: A nonvolatile memory and a method of manufacturing a nonvolatile memory are disclosed. A nonvolatile memory according to an exemplary embodiment may include a deep well formed on a substrate, a first well formed within the deep well, a second well formed separately from the first well within the deep... Agent:
20130294173 - Method and apparatus for the erase suspend operation: Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program... Agent:
20130294180 - Charge storage organic memory system: A memory system is disclosed. The system comprises a memory layer between a first layer and a second layer, wherein the first layer and the second layer are configured to apply an electrical bias to the memory layer. In some embodiments the memory layer comprises nanodots made of a material... Agent: Ramot At Tel-avlv University Ltd.
20130294179 - Circuits and methods for calibrating offset in an amplifier: In one embodiment, the present disclosure includes a circuit comprising an amplifier having an input and an output, an offset detection circuit to detect an offset of the amplifier at the output of the amplifier, and an offset generation circuit having an input coupled to the offset detection circuit and... Agent: Marvell World Trade Ltd.
20130294174 - Memory device for performing multi-core access to bank groups: A memory device has a burst length “b”, performs “k” core accesses per command, and receives a command, where “b” is an integer of at least 2 and “k” is an integer of at least 2 and at most “b”. The memory device includes a memory cell array comprising a... Agent: Samsung Electronics Co., Ltd.
20130294176 - Control device: A control device that comprises a first data strobe input terminal to be connected in common to data strobe terminals that are included respectively in first memory devices, and a plurality of first sub-units each coupled to the first data strobe input terminal and each holding a data strobe delay... Agent: Elpida Memory, Inc.
20130294175 - Nonvolatile semiconductor device and method for testing the same: A nonvolatile semiconductor device and a method for testing the same are provided. The nonvolatile semiconductor device includes a current generating unit configured to generate a set write current depending on a step pulse that is generated based on a reference current and output the set write current to a... Agent: Sk Hynix Inc.
20130294177 - Memory devices and control methods thereof: A memory device is provided. The memory device includes a first signal line, a memory cell array, first and second voltage adjustment circuits. The memory cell array is divided into first and second areas and includes first memory cells in the first area and second memory cells in the second... Agent: Media Tek Inc.
20130294178 - Method for reducing standby current of semiconductor memory device: A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first... Agent: Elite Semiconductor Memory Technology Inc.
20130294181 - Memory cell having flexible read/write assist and method of using: A semiconductor device includes at least one memory cell die. The at least one memory cell die includes a data storage unit. The at least one memory cell die includes at least one read assist enabling unit electrically connected to the data storage unit. The at least one read assist... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20130294182 - Non-volatile semiconductor device and method for controlling the same: A non-volatile semiconductor device and a method for controlling the same are disclosed, which can increase a read efficiency of the non-volatile semiconductor device using the Low Power Double Data Rate (LPDDR) 2 specifications. The non-volatile semiconductor device includes a decoder configured to output a plurality of active control signals... Agent: Sk Hynix Inc.
20130294183 - Electrical fuse rupture circuit: A semiconductor memory device including circuitry for detecting and repairing memory cell failures in a test mode. The memory cell repair process is conducted in a manner that effectively eliminates unnecessary fuse rupture operations and verify operations in a test mode, thus reducing product test time.... Agent: Sk Hynix Inc.
20130294184 - Self-repair logic for stacked memory architecture: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the... Agent:
20130294185 - Sense amplifier circuit and semiconductor device using the same: A sense amplifier circuit includes an enable signal generation unit configured to generate an enable signal when a change in a voltage level of input signals is sensed; a sink unit configured to provide a sense voltage in response to the enable signal; and a sense unit configured to generate... Agent: Sk Hynix Inc.
20130294186 - Phase-locked loop and integrated circuit chip including the same, and test system including the integrated circuit chip: A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a... Agent: Sk Hynix Inc.Previous industry: Electric power conversion systems
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