|Static information storage and retrieval patents - Monitor Patents|
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Static information storage and retrievalBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 07/10/2014 > 30 patent applications in 18 patent subcategories.
20140192579 - Two phase search content addressable memory with power-gated main-search: Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal voltage levels at all times while the main-search CAM cells are powered to a lower voltage level. Only... Agent: International Business Machines Corporation
20140192580 - Low power content addressable memory system: A content addressable memory (CAM) system includes one or more CAM cells, each including a bit cell to store a bit and a complementary bit, and a compare circuit to compare a reference input to the stored bit and to the stored complementary bit. The compare circuit may be implemented... Agent:
20140192583 - Configurable memory circuit system and method: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g.... Agent:
20140192582 - Memory structure with reduced number of reflected signals: A memory structure with reduced-reflection signals at least includes a processing unit; a lumped circuit unit, connected to the processing unit; a plurality of memories, connected to the lumped circuit unit; and a reflected signal absorption unit, disposed at one end of the lumped circuit unit. Thereby, with the cooperation... Agent: Eorex Corporation
20140192581 - Programmable and flexible reference cell selection method for memory devices: Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide... Agent: Spansion LLC
20140192584 - Semiconductor device: A semiconductor device includes a first memory block including first vertical strings, a second memory block including second vertical strings coupled in series with the first vertical strings, wherein the second memory block is stacked on the first memory block, first bit lines located between the first memory block and... Agent: Sk Hynix Inc.
20140192588 - Nonvolatile memory device and read method thereof: A nonvolatile memory device is provided which includes a main area including main cells connected to word lines and main bit lines; a reference area including reference cells connected to the word lines and reference bit lines and programmed using the same write condition as that of the main area;... Agent:
20140192589 - Reduced diffusion in metal electrode for two-terminal memory: Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal... Agent: Crossbar, Inc.
20140192585 - Resistive random access memory cell having three or more resistive states: Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive... Agent: Kabushiki Kaisha Toshiba
20140192586 - Resistive random access memory cells having variable switching characteristics: Provided are resistive random access memory (ReRAM) cells forming arrays and methods of operating such cells and arrays. The ReRAM cells of the same array may have the same structure, such as have the same bottom electrodes, top electrodes, and resistive switching layers. Yet, these cells may be operated in... Agent: Kabushiki Kaisha Toshiba
20140192587 - Thermodynamic bit formed of two memristors: A thermodynamic bit apparatus, method and system. A thermodynamic bit is a device that returns a true or false state with a probability that depends on its internal state, which can be controlled via the application of positive feedback. A thermodynamic bit can include two or more memristors connected in... Agent: Knowmtech, LLC
20140192591 - High capacity low cost multi-state magnetic memory: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.... Agent: Avalanche Technology, Inc.
20140192590 - Multi-port magnetic random access memory (mram): A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor... Agent: Avalanche Technology, Inc.
20140192592 - Sb-te-ti phase-change memory material and ti-sb2te3 phase-change memory material: The present invention relates to an Sb—Te—Ti phase-change thin-film material applicable to a phase-change memory and preparation thereof. The Sb—Te—Ti phase-change memory material of the present invention is formed by doping an Sb—Te phase-change material with Ti, Ti forms bonds with both Sb and Te, and the Sb—Te—Ti phase-change memory... Agent: Shanghai Institute Of Microsystem And Information Technology Chinese Academy
20140192593 - Flash multi-level threshold distribution scheme: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while... Agent: Mosaid Technologies Incorporated
20140192594 - P-channel 3d memory array: A p-channel flash memory device including a 3D NAND array has excellent performance characteristics. Techniques for operating 3D, p-channel NAND arrays include selective programming, selective (bit) erase, and block erase. Selective programming bias arrangements induce band-to-band tunneling current hot electron injection to increase threshold voltages in selected cells. Selective erase... Agent: Macronix International Co., Ltd.
20140192595 - Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which... Agent: Sandisk 3d LLC
20140192597 - Circuit for controlling eeprom cell: An EEPROM cell control circuit is provided which includes a signal input circuit configured to receive control signals for controlling an EEPROM cell from an external device; a bit line control circuit configured to provide a positive voltage and a negative voltage to two bit lines connected with the EEPROM... Agent:
20140192596 - Nonvolatile memory with split substrate select gates and heirarchical bitline configuration: Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each... Agent: Mosaid Technologies Incorporated
20140192598 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes first hookup transistors connected to word lines, a first dummy hookup transistor connected to first dummy word line, and a second dummy hookup transistor connected to second dummy word line. A group of hookup transistors formed by the first hookup transistors,... Agent:
20140192599 - Test partitioning for a non-volatile memory: Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region. A test application may be stored in the general purpose region, and the test application can be executed to... Agent: Apple Inc.
20140192600 - Eeprom cell and eeprom device: An EEPROM cell is provided which includes a control gate; a tunneling plate; a floating plate configured to form a capacitor area with the control plate and the tunneling plate; an inverter configured to sense a voltage level of the floating plate; a first transfer gate connected with the tunneling... Agent: Electronics And Telecommunications Research Institute
20140192601 - Multi-port memory device with serial input/output interface: A multi-port memory device includes a plurality of serial I/O data pads for providing a serial input/output (I/O) data communication; a plurality of ports for performing the serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data... Agent:
20140192602 - Defective memory column replacement with load isolation: Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to... Agent: International Business Machines Corporation
20140192603 - Differential sense amplifier for solid-state memories: Described embodiments provide a memory having at least one sense amplifier with inputs coupled to at least one pair of bit lines. One of the pair of bit lines is precharged to a power supply voltage and a second one of the pair is precharged to ground. A first switch... Agent: Lsi Corporation
20140192604 - Memory cell operation: Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge... Agent: Micron Technology, Inc.
20140192605 - Memory refresh management: Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory controller logic to determine a memory refresh frequency for a memory system and transmit refresh commands to a refresh control logic in at least one memory bank coupled... Agent:
20140192606 - Stacked memory device, memory system including the same and method for operating the same: A stacked memory device includes a plurality of interconnected memory chips and a controller to control the plurality of memory chips to perform refresh operations during non-overlapping time periods. Each memory chip includes a plurality of ranks, and each rank includes at least one memory bank. In one arrangement, the... Agent: Samsung Electronics Co., Ltd.
20140192607 - Adaptive voltage input to a charge pump: A memory subsystem includes an adaptive output voltage to provide a voltage based on a power profile of a memory device of the memory subsystem. A charge pump increases the voltage to a level needed to write data to the memory device. The voltage provided is based on the power... Agent:
20140192608 - Controlling method of connector, connector, and memory storage device: A controlling method of a connector, the connector, and a memory storage device are provided. The controlling method includes following steps. A first clock signal generated by a first oscillator in the connector is obtained. A second clock signal generated by a second oscillator in the connector is obtained. A... Agent: Phison Electronics Corp.07/03/2014 > 56 patent applications in 30 patent subcategories.
20140185348 - Hybrid ternary content addressable memory: A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second... Agent: Qualcomm Incorporated
20140185349 - Static nand cell for ternary content addressable memory (tcam): A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor.... Agent: Qualcomm Incorporated
20140185351 - Non-volatile storage system with dual block programming: A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to... Agent: Sandisk 3d LLC
20140185350 - Semiconductor device including plural chips stacked to each other: A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with... Agent: Elpida Memory, Inc.
20140185352 - Configurable-width memory channels for stacked memory structures: The disclosed embodiments provide a chip package that facilitates configurable-width memory channels. In this chip package, a semiconductor die is electrically connected to two or more memory chips. More specifically, contacts on each individual memory chip are each directly connected to a distinct set of contacts on the semiconductor die... Agent: Oracle International Corporation
20140185353 - Memory: A memory in accordance with an embodiment of the present invention may include a first page buffer, a second page buffer arranged adjacent to the first page buffer in a first direction, a global pad arranged between the first page buffer and the second page buffer, and a first bit... Agent: Sk Hynix Inc.
20140185354 - Stub minimization using duplicate sets of signal terminals: A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be... Agent: Invensas Corporation
20140185355 - Systems and devices including multi-transistor cells and methods of using, making, and operating the same: A device may include a first transistor, a second transistor, and a data element. The first transistor may have a column gate and a channel, and the second transistor may include a row gate that crosses over the column gate, under the column gate, or both. The second transistor may... Agent: Micron Technology, Inc.
20140185356 - Semiconductor integrated circuit and method of driving the same: A semiconductor integrated circuit includes a fuse circuit comprising a fuse configured to generate a fuse state signal corresponding to a rupture state of the fuse in response to an enable signal, a fuse state decision unit configured to determine whether or not the fuse state signal is normal based... Agent: Sk Hynix Inc.
20140185357 - Barrier design for steering elements: Steering elements suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the steering element can include a first electrode, a... Agent: Intermolecular, Inc.
20140185359 - Memory device: According to one embodiment, a memory device includes n (n being an integer of 2 or more) resistance change films being series connected to each other. Each of the resistance change films is a superlattice film in which a plurality of pairs of a first crystal layer made of a... Agent:
20140185361 - Non-volatile random access memory device and data read method thereof: A nonvolatile random access memory device includes a plurality of memory cells configured to store data therein, a plurality of reference cells separate from the memory cells, the reference cells each configured to output a corresponding reference cell signal, and a read/write circuit. The read/write circuit is configured to generate... Agent:
20140185358 - Resistive random access memory with non-linear current-voltage relationship: Providing for fabrication, construction, and/or assembly of a resistive random access memory (RRAM) cell is described herein. The RRAM cell can exhibit a non-linear current-voltage relationship. When arranged in a memory array architecture, these cells can significantly mitigate sneak path issues associated with conventional RRAM arrays.... Agent: Crossbar, Inc
20140185362 - System and method for performing memory operations on rram cells: A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to... Agent: Rambus Inc.
20140185360 - Write method for writing to variable resistance nonvolatile memory element and variable resistance nonvolatile memory device: A write method for writing to a variable resistance nonvolatile memory element, comprising applying a set of strong recovery-voltage pulses at least once to the variable resistance nonvolatile memory element when it is determined that the resistance state of the variable resistance nonvolatile memory element fails to change to a... Agent:
20140185363 - Bit cell internal voltage control: Among other things, techniques for facilitating a write operation to a bit cell are provided. A pulse generator initializes lowering of an internal voltage level associated with a bit cell that is to be written to by a write operation. In this way, the bit cell is placed into a... Agent: Taiwan Semiconductor Manufacturing Company Limited
20140185365 - Dual-port sram connection structure: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140185368 - Method and apparatus for storing data: A memory system (1) comprising a control logic (2) adapted to receive a number n of write requests (WRs) from input ports and to receive a read request (RR) from an output port within a clock cycle of a clock signal (CLK) applied to said memory system (1), wherein n... Agent: Huawei Technologies Co., Ltd.
20140185364 - Methods and apparatus for designing and constructing multi-port memory circuits: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true... Agent: Memoir Systems, Inc.
20140185366 - Pre-charge tracking of global read lines in high speed sram: In embodiments of the invention, a memory circuit includes a static random access memory (SRAM), rows of M sense amplifiers, a global read precharge tracking control circuit controlling a precharge of global read lines, a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier... Agent: Lsi Corporation
20140185369 - Sense amplifier scheme for low voltage sram and register files: In at least one embodiment, a sense amplifier circuit includes a bit line, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the bit line and includes an NMOS transistor coupled between a power node and the bit line. The... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140185367 - Sram bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter: Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would... Agent:
20140185371 - Antiferromagnetic storage device: An atomic-scale structure according to one embodiment has a net magnetic moment of zero or about zero, two or more stable magnetic states, and an array of atoms that has magnetic moments that alternate between adjacent magnetic atoms along one or more directions. Such structures may be used to store... Agent: International Business Machines Corporation
20140185372 - Memory sensing circuit: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance... Agent: Avalanche Technology, Inc.
20140185370 - Nonvolatile memory apparatus having magnetoresistive memory elements and method for driving the same: A semiconductor memory apparatus includes a source line, a first bit line disposed over the source line, a second bit line disposed under the source line, a first memory cell between the source line and the first bit line, and a second memory cell between the source line and the... Agent: Sk Hynix Inc.
20140185373 - Supply voltage generating circuit and semiconductor device having the same: A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The... Agent:
20140185375 - Memory system to determine inference of a memory cell by adjacent memory cells, and operating method thereof: Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time... Agent: Samsung Electronics Co., Ltd.
20140185376 - Method and system for asynchronous die operations in a non-volatile memory: A mass storage memory system and method of operation is disclosed. The memory includes an interface adapted to receive data from a host, a plurality of flash memory die and a controller, where the controller is configured to receive a first command and read or write data synchronously across the... Agent:
20140185378 - Multi-bit flash memory device and memory cell array: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2″ pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.... Agent:
20140185377 - Multi-level cell memory device and method of operating multi-level cell memory device: A read method of a multi-level cell memory device includes receiving a first read command, and reading first and second hard decision data by performing first and second hard decision read operations using a first hard decision read voltage and a second hard decision read voltage, respectively, the second hard... Agent:
20140185379 - Hybrid solid-state memory system having volatile and non-volatile memory: A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is... Agent: Mosaid Technologies Incorporated
20140185380 - Semiconductor memory device having faulty cells: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out... Agent: Solid State Storage Solutions, Inc.
20140185381 - Semiconductor apparatus and method of operating the same: A method of operating a semiconductor device includes: performing a program operation of selected memory cells of a memory block; setting a level of a program verification voltage according to the number of times program/erase operation is performed on the selected memory cells; and performing a program verification operation by... Agent: Sk Hynix Inc.
20140185382 - Erase for non-volatile storage: Techniques are disclosed herein for erasing non-volatile storage elements. A sequence of increasing erase voltages may be applied to a substrate. The select line may be floated and many of the word lines may be held at a low voltage (e.g., close to 0V). However, the voltage applied to an... Agent: Sandisk Technologies Inc.
20140185384 - Nonvolatile memory devices including simultaneous impedance calibration: An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence accompanies an impedance calibration operation; and if the input command sequence accompanies the impedance calibration operation, simultaneously performing an operation corresponding to the input command sequence and the... Agent: Samsung Electronics Co., Ltd.
20140185383 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a first NAND string and a second NAND string are connected to a bit line. One of the first and second NAND strings is selected by first to fourth select memory cells. At the write time, data is written in a... Agent:
20140185385 - Memories and methods of programming memories: Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of... Agent: Micron Technology, Inc.
20140185374 - Nonvolatile memory and method with improved i/o interface: Each I/O channel between a controller and one or more memory dice of a memory device has a driver on one end and a receiver at the other end. The receiver is optionally terminated with a pseudo open-drain (“POD”) termination instead of the conventional center-tapped (“CTT”) termination to save energy.... Agent: Sandisk Technologies Inc.
20140185386 - Reliability metrics management for soft decoding: Embodiments provide a method for reading a target memory sector of a memory. The method comprises, based on read data corresponding to a plurality of memory sectors of the memory, estimating first one or more reference voltages and, using the first one or more reference voltages, performing a first read... Agent: Marvell World Trade Ltd.
20140185387 - Semiconductor memory device and method of operating the same: A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification... Agent: Sk Hynix Inc.
20140185388 - Dynamic drive strength optimization: A system for optimizing drive strength may be utilized for identifying the maximum data transfer rate for different devices and different device configurations. The drive strength may be optimized for input/output (I/O) devices by measuring voltage drops on I/O power supply using different test patterns. The maximum drive strength is... Agent:
20140185393 - Design for test (dft) read speed through transition detector in built-in self-test (bist) sort: A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of... Agent: Spansion, LLC.
20140185392 - Memory sense amplifier voltage modulation: Memory sense amplifier voltage modulation. An embodiment of a an apparatus includes a memory including a sense amplifier; a first node for an high voltage rail for the sense amplifier and a second node for a low voltage rail for the sense amplifier; one or more elements to provide a... Agent:
20140185390 - Buffer for ordering out-of-order data, and corresponding integrated circuit and method for managing a buffer: A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify... Agent: Stmicroelectronics S.r.l.
20140185389 - Memory systems including an input/output buffer circuit: Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel... Agent: Samsung Electronics Co., Ltd.
20140185391 - Semiconductor apparatus: A semiconductor apparatus includes a phase detecting unit that continuously detects a first delay amount during a read operation, based on a phase difference between an external clock signal and an internal clock signal; a generating unit that generates a second control signal by delaying a first control signal by... Agent: Fujitsu Limited
20140185394 - Memory with bit cell header transistor: A memory includes a plurality of bit cells. Each bit cell includes a bit line and a storage cell coupled to the bit line. A header PMOS transistor is coupled to the storage cell in each bit cell. The header PMOS transistor is at least partially turned off during a... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140185395 - Methods of copying a page in a memory device and methods of managing pages in a memory system: A method of copying a page in a memory device having a plurality of memory blocks and a plurality of sets of bit lines is disclosed, wherein each of the plurality of memory blocks includes a plurality of pages, and each set of bit lines corresponds to a respective memory... Agent:
20140185396 - Semiconductor memory, memory system, and operation method thereof: A memory system includes a semiconductor memory including a storage unit configured to store parameter information in response to a test mode signal and to output the stored parameter information in response to a parameter request signal, and a memory controller configured to provide the parameter request signal to the... Agent: Sk Hynix Inc.
20140185397 - Hybrid latch and fuse scheme for memory repair: A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also... Agent: International Business Machines Corporation
20140185398 - Hybrid latch and fuse scheme for memory repair: A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also... Agent: International Business Machines Corporation
20140185399 - Test mediation device and system and method for testing memory device: A system for testing a memory device includes a memory device configured to include a plurality of memory cells, receive a test information having a first frequency, access memory cells corresponding to an address included in the test information, and activate a fail signal if fail occurs in the memory... Agent: Sk Hynix Inc.
20140185400 - Apparatus and method for sense amplifying: A sense amplifier includes four sub-circuits: pre-charge, sense enable, sense output, and buffer. The pre-charge sub-circuit provides a voltage between zero volts and the positive power supply (denoted VDD) to the sense enable sub-circuit. The sense enable sub-circuit is configured to adjust the received voltage based on the sensed value... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20140185402 - Dram security erase: A memory includes a DRAM array having memory cells, wordlines and bitlines coupled to the memory cells, and sense amplifiers. The memory can be configured to perform a method in which a wordline of the DRAM array is set to an active state. While the wordline is active, signals develop... Agent: Tessera, Inc.
20140185401 - Sensing circuit, memory device and data detecting method: A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140185403 - Refresh method for switching between different refresh types based on at least one parameter of volatile memory and related memory controller: A refresh method of a volatile memory includes at least the following steps: detecting at least one parameter of the volatile memory; selecting a target refresh type from a plurality of candidate refresh types according to the at least one parameter; and performing a refresh operation upon the volatile memory... Agent: Mediatek Inc.06/26/2014 > 69 patent applications in 41 patent subcategories.
20140177309 - Magnetic memory devices and systems: A method of storing one or more bits of information comprising: forming a magnetic bubble; and storing a said bit of information encoded in a typology of a domain wall of said magnetic bubble. Preferably a bit is encoded using a symmetric topological state of the domain wall and a... Agent: Ecole Polytechnique Federale De Lausanne (epfl)
20140177310 - Pseudo-nor cell for ternary content addressable memory: A method within a ternary content addressable memory (TCAM) includes receiving a match line output from a previous TCAM stage at a gate of a pull-up transistor of a current TCAM stage and at a gate of a pull-down transistor of the current TCAM stage. The method sets a match... Agent: Qualcomm Incorporated
20140177311 - Memory device structure with decoders in a device level separate from the array level: A memory device structure and method of fabricating the memory device structure is described. The memory device structure has a memory array disposed in a array level and peripheral circuitry, including decoders and other peripheral circuitry, disposed in a device level. The array of memory cells has a perimeter that... Agent: Macronix International Co., Ltd.
20140177312 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality... Agent: Renesas Electronics Corporation
20140177313 - Semiconductor device and method of operation: A semiconductor device and method of operation having reduced read time of fuse array information during boot-up operation. When fuse array information is read, only repaired fuse-set information is read such that a read time of the semiconductor memory device is reduced, resulting in an increased read margin.... Agent: Sk Hynix Inc.
20140177314 - Semiconductor memory devices and semiconductor system having parameters, and methods of testing the same: A semiconductor memory device may be effectively evaluated by a test that compares the phase of an internally generated control signal with the phase of an internally generated clock signal. Specifically, if the phase of the internal data strobe signal IDQS is synchronized with the phase of the internal clock... Agent: Sk Hynix Inc.
20140177318 - Hybrid memory: A two-switch hybrid memory cell device includes a storage node connected between one terminal of a first switch and a gate of a second switch. The device also includes a resistive switching device connected to the storage node. The resistive switching device is to act as a capacitance by being... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140177315 - Multi-level memory array having resistive elements for multi-bit data storage: A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in... Agent: Kabushiki Kaisha Toshiba
20140177317 - Non-volatile memory system with power reduction mechanism and method of operation thereof: A method of operation of a non-volatile memory system including: providing a resistive storage element having a transformation layer; activating a write driver, coupled to the resistive storage element, for applying a bias voltage to the transformation layer; monitoring a resistance of the resistive storage element by a sense amplifier;... Agent:
20140177316 - Non-volatile memory system with reset verification mechanism and method of operation thereof: A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through... Agent:
20140177319 - Nonvolatile memory apparatus: A nonvolatile memory apparatus includes a sensing voltage generation unit, a memory cell, a current copy unit and a data sensing unit. The sensing voltage generation unit provides a sensing voltage with a constant level, to a sensing node. The memory cell receives the sensing voltage from the sensing node.... Agent:
20140177321 - Nonvolatile memory device and related operating method: A method is for driving a nonvolatile memory device, where the nonvolatile memory device includes a memory cell array composed of resistance memory cells. The method includes electrically connecting a clamping circuit, a line resistor and a selected one of the resistance memory cells in series between a sensing node... Agent: Samsung Electronics Co., Ltd.
20140177320 - Resistive memory device and write method thereof: A method writes data in a resistive memory device in which paths for performing write operations to record first-state data and second-state data are controlled to cause current to flow in opposing directions in a resistive memory cell whose switching type has been determined. The method includes performing a write... Agent:
20140177322 - Semiconductor memory apparatus, verify read method and system: Disclosed are a semiconductor memory apparatus, and verify read method and system. The semiconductor memory apparatus includes a memory cell array including a plurality of resistive memory cells; and a control block controlling a resistance state of the memory cell to be discriminated based on a digital code value of... Agent: Research & Business Foundation Sungkyunkwan University
20140177323 - Bit-flipping in memories: Data stored in SRAM cells are periodically flipped e.g., before long idle periods. Operating the memories in both a ‘flipped’ mode and a ‘non-flipped’ mode helps cause the Bias Temperature Instability (BTI) degradation to be symmetric, thereby not degrading the Static Noise Margin (SNM) degradation of the cells. The data... Agent:
20140177324 - Single-port read multiple-port write storage device using single-port memory cells: A storage device provides single-port read multiple-port write functionality and includes first and second memory arrays and a controller. The first memory array includes first and second single-port memory cells. The second single-port memory cell stores data in response to a memory access conflict associated with the first single-port memory... Agent: Lsi Corporation
20140177326 - Electric field enhanced spin transfer torque memory (sttm) device: Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to... Agent:
20140177325 - Integrated mram module: Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module... Agent: Qualcomm Incorporated
20140177328 - Multi-bit magnetic memory cell: A device (20) for storing data includes at least first and second ferromagnetic films (F1, F2) and a sensing circuit (28). The ferromagnetic films both have perpendicular magnetic anisotropy that is configured responsively to the stored data, and are connected so that an electrical current traverses the first and second... Agent: Ramot At Tel Aviv University Ltd.
20140177327 - Voltage-controlled magnetic anisotropy (vcma) switch and magneto-electric memory (meram): Voltage controlled magnetic tunnel junctions and memory devices are described which provide efficient high speed switching of non-volatile magnetic devices at high cell densities. Implementations are described which provide a wide range of voltage control alternatives with in-plane and perpendicular magnetization, bidirectionally switched magnetization, and control of domain wall dynamics.... Agent: The Regents Of The University Of California
20140177329 - Bottom electrode geometry for phase change memory: A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current... Agent: Micron Technology, Inc.
20140177330 - Vertical bjt for high density memory: Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20140177331 - Semiconductor device and method for forming the same: In order to fabricate a semiconductor device, a semiconductor substrate in a peripheral region is etched to form a plurality of holes. A gap-filling material is buried in the holes of the semiconductor substrate in the peripheral region, and first and second device isolation films are formed in the semiconductor... Agent: Sk Hynix Inc.
20140177334 - Circuit for sensing mlc flash memory: A circuit for sensing a multi-level cell (MLC) flash memory is disclosed. The circuit comprises a plurality of first decoding units, a second decoding unit and a data latch. Each of the first decoding units provides a timing information and includes a controlled transistor to allow a current to pass... Agent: Elite Semiconductor Memory Technology Inc.
20140177335 - Nonconsecutive sensing of multilevel memory cells: The present disclosure includes apparatuses and methods for nonconsecutive sensing of multilevel memory cells. A number of methods include sensing a unit of information from a multilevel memory cell (MLC) using a sensing signal. The unit of information can correspond to a page of information. The MLC can store a... Agent: Micron Technology, Inc.
20140177336 - Non-volatile memory device and method of fabricating the same: This technology provides a non-volatile memory device and a method of manufacturing the same, which may prevent an over-erase phenomenon and also increase the degree of integration, In an aspect, the non-volatile memory device includes a select gate formed over a substrate, a plurality of floating gates laterally formed with... Agent: Sk Hynix Inc.
20140177337 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not... Agent: Kabushiki Kaisha Toshiba
20140177338 - Non-volatile memory cell: A non-volatile memory cell comprises a coupling device, a first and a second select transistor, and a first and a second floating gate transistor is disclosed. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to the first floating gate transistor and... Agent: Ememory Technology Inc.
20140177339 - Nonvolatile semiconductor memory device and memory system having the same: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein... Agent: Elpida Memory, Inc.
20140177340 - Determining memory page status: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (I/O) circuitry, and outputting the status through the I/O circuitry.... Agent: Micron Technology, Inc.
20140177332 - Operating circuit controlling device, semiconductor memory device and method of operating the same: A semiconductor memory device is kept in a busy state by controlling a ready/busy pad when a detection signal is output since an external voltage is less than a reference voltage, prevents generation of an operating voltage by a pump circuit by preventing generation of a pump clock, and resets... Agent: Sk Hynix Inc.
20140177333 - Row decoding circuit and memory: A row decoding circuit and a memory are provided. The row decoding circuit is adapted for providing a word line operation voltage and a control-gate line operation voltage to a dual-bit split gate flash memory array, and includes a dummy row decoding unit, at least one row decoding unit and... Agent: Grace Semiconductor Manufacturing Corporation
20140177341 - Semiconductor device: In this flash memory, after first and second nodes are precharged to a power supply voltage, a sense amplifier is activated, and signals appearing at the first and second nodes are held in a register. With output signals of the register, a transistor is rendered conductive, so that a constant... Agent:
20140177342 - Memory cell sensing using a boost voltage: The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging and/or floating a data line associated with a selected memory cell, boosting the pre-charged and/or floating data line, and determining a state of the selected memory cell based... Agent: Micron Technology, Inc.
20140177352 - Shared tracking circuit: A system comprises a plurality of first memory macros and a first tracking circuit to be shared by the plurality of first memory macros. The first tracking circuit includes at least one of a first tracking circuit associated with a row of memory cells of a first memory macro of... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140177343 - Memory device with high-speed reading function and method thereof: A method includes steps of: providing a first memory cell array including a plurality of first word lines, wherein a plurality of first data are stored in the first memory cell array; providing a second memory cell array including a plurality of second word lines, wherein the second memory cell... Agent: Winbond Electronics Corp.
20140177344 - Method and apparatus for clock power saving in multiport latch arrays: An integrated circuit element is disclosed having a memory device; a P-type semiconductor region including a first semiconductor device from a first memory port circuit coupled to the memory device and configured to enable access to the memory device when the first semiconductor device is activated; an N-type semiconductor region... Agent: Qualcomm Incorporated
20140177345 - Semiconductor device: To provide a semiconductor device that has a novel structure and achieves a higher degree of convenience, the semiconductor device is configured to include a memory cell that stores binary data or multilevel data, and a reading circuit that reads the data stored in the memory cell and transfers the... Agent: Semiconductor Energy Laboratory Co., Ltd.
20140177346 - Apparatus to suppress concurrent read and write word line access of the same memory element in a memory array: A memory array includes a number of word lines, with each word line coupled to a word line driver for memory write operations and a word line driver for memory read operations. A decode stage includes write logic for each word line and read logic for each word line. A... Agent: Apple Inc.
20140177347 - Inter-row data transfer in memory devices: A method and apparatus for inter-row data transfer in memory devices is described. Data transfer from one physical location in a memory device to another is achieved without engaging the external input/output pins on the memory device. In an example method, a memory device is responsive to a row transfer... Agent: Advanced Micro Devices, Inc.
20140177348 - Non-volatile register and non-volatile shift register: Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices are disclosed. The innovative NVR and NVSR devices of the invention can rapidly load the stored non-volatile data in non-volatile memory elements into their correspondent static memory elements for fast and constant referencing in digital circuitry. According to the invention, the... Agent: Flashsilicon Incorporation
20140177349 - Shared integrated sleep mode regulator for sram memory: Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed... Agent: Advanced Micro Devices Inc.
20140177350 - Single-ended sense amplifier circuit: A single-ended sense amplifier and a method for reading a memory cell are disclosed. The method includes the following steps. A bit line is charged according to a control signal. Thereafter, whether the dropoff time of the bit line voltage is greater or less than a predetermined time is deteremined.... Agent: Ememory Technology Inc.
20140177351 - Semiconductor device: A semiconductor device includes a first transistor connected to an internal voltage terminal and a first node at which a first resistance unit is connected. The first resistance unit includes a resistor connected between the first node and a node from which a monitoring voltage is provided for controlling the... Agent: Kabushiki Kaisha Toshiba
20140177353 - Nonvolatile memory apparatus: A nonvolatile memory apparatus includes a read/write control unit and a voltage generation unit and the memory cell. The read/write control circuit is configured to supply a bias voltage in response to a read control signal, a write control signal and data. The voltage generation unit is configured to compare... Agent: Sk Hynix Inc.
20140177355 - Nonvolatile memory apparatus: A nonvolatile memory apparatus includes a read driver. The read driver unit is configured to apply read current to a memory cell in a normal read operation for outputting data stored in the memory cell, and apply refresh current larger than the read current to the memory cell in a... Agent: Sk Hynix Inc.
20140177354 - Zero keeper circuit with full design-for-test coverage: A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down... Agent: Apple Inc.
20140177357 - Data write circuit of semiconductor apparatus: A data write circuit of a semiconductor apparatus includes a data path configured to receive a pattern signal and generate a first delayed pattern signal; a data strobe signal path configured to receive the pattern signal and generate a second delayed pattern signal; a data latch block configured to latch... Agent:
20140177356 - Programmable resistance-modulated write assist for a memory device: Providing for improved write processes of a semiconductor memory are disclosed herein. By way of example, a programmable write assist can be provided that includes partially discharging a supply voltage applied to a memory cell. Partially discharging the supply voltage can improve write speeds to the memory cell, as well... Agent: Applied Micro Circuits Corporation
20140177358 - Address counting circuit and semiconductor apparatus using the same: A semiconductor apparatus includes a first memory die; a second memory die; and a processor configured to provide an external command, an external start address and an external end address which are associated with a read operation, to the first memory die, and provide an external command, an external start... Agent:
20140177360 - Device and method for controlling self-refresh: A device and method for controlling self-refresh is disclosed, which reduces current when a semiconductor device stays in a self-refresh operation. The device for controlling self-refresh includes: a bulk voltage controller configured to combine an idle signal indicating an active termination state of a bank and a self-refresh signal so... Agent: Sk Hynix Inc.
20140177359 - Method and apparatus for aligning a clock signal and a data strobe signal in a memory system: A method of aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory, and a corresponding memory system are provided. The method comprising the steps of: putting the memory into a write levelling mode; incrementing an alignment delay applied to the... Agent: Arm Limited
20140177361 - Semiconductor device including a clock generating circuit for generating an internal signal having a coarse delay line, a fine delay line and a selector circuit: A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise... Agent:
20140177362 - Memory interface supporting both ecc and per-byte data masking: A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked... Agent: Advanced Micro Devices, Inc.
20140177363 - Method and system for automated device testing: Embodiments described herein provide enhanced testing of devices. For example, in an embodiment, an interposer for testing devices is provided. The interposer includes a substrate, a first plurality of connection elements located on a surface of the substrate, and a memory device electrically coupled to the first plurality of connection... Agent: Broadcom Corporation
20140177364 - One-time programmable memory and test method thereof: A one-time programmable memory device may include a normal cell array including a plurality of one-time programmable memory cells, which are programmable and accessible in the normal operation, a test cell array including one-time programmable memory cells, which are programmed at a given pattern in a test operation for determining... Agent: Sk Hynix Inc.
20140177365 - Semiconductor apparatus, test method using the same and muti chips system: A semiconductor apparatus includes a test unit including: a data determination unit configured to receive a plurality of data, determine whether the plurality of data are identical or not, and output the determination result as a compression signal; and an output control unit configured to output the compression signal as... Agent: Sk Hynix Inc.
20140177366 - Data input/output circuit and semiconductor memory device including the same: A data input/output circuit includes a precharge voltage supply unit configured to supply a precharge voltage driven by a first internal voltage in a standby state, and supply the precharge voltage driven by a second internal voltage when an active operation is performed; and a precharge unit configured to receive... Agent: Sk Hynix Inc.
20140177367 - Semiconductor device including plural chips stacked to each other: A device includes a plurality of Dynamic Random Access Memory (DRAM) chips in a stacked configuration connected by through silicon vias (TSVs), and each of the plurality of DRAM chips being configured to provide a local bank active signal to indicate when any one of a plurality of banks on... Agent:
20140177368 - Nonvolatile memory apparatus: A nonvolatile memory apparatus includes a memory cell configured to receive a first current and a second current through a bit line which is connected to a sensing node; a sensing node level control unit configured to be driven in response to a control signal, compare a reference voltage and... Agent: Sk Hynix Inc.
20140177369 - Optical data store and method for storage of data in an optical data store: An optical data store is specified, having a data storage layer with a non-toxic and biodegradable polymer as light-sensitive storage medium which has photo-inducible anisotropy, for the induction of which a threshold value of the optical intensity has to be exceeded. The light-sensitive material is preferably bacteriorhodopsin which, by way... Agent: Actilor Gmbh
20140177370 - Method, apparatus and system for responding to a row hammer event: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command... Agent: Intel Corporation
20140177372 - Semiconductor device that performs refresh operation: A method for refreshing memory cells in a DRAM includes receiving a refresh command, receiving a refresh mode specifying signal in synchronization with the refresh command, refreshing a first quantity of memory cells when the refresh mode specifying signal has a first value, and refreshing a second quantity of memory... Agent:
20140177371 - Suspend sdram refresh cycles during normal ddr operation: An apparatus comprising a test circuit and a protocol circuit. The test circuit may be configured to generate a plurality of control signals in response to one or more read data signals. The protocol circuit may be configured to generate a plurality of interface signals in response to the plurality... Agent: Lsi Corporation
20140177373 - System involving electrically reprogrammable fuses: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the... Agent: International Business Machines Corporation
20140177374 - Driver of semiconductor memory device and driving method thereof: A driver of a semiconductor memory device and driving method thereof is disclosed, which relates to a technology for reducing consumption of a leakage current not required for a driver circuit of a semiconductor memory device. The driver of the semiconductor memory device includes a drive controller configured to selectively... Agent: Sk Hynix Inc.
20140177375 - Memory device with internal combination logic: Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a... Agent: Spansion LLC
20140177376 - Memory and memory system including the same: A memory includes a first cell array including a plurality of first memory cells connected to a plurality of word lines, a bit line selection unit configured to select one or more bit lines among a plurality of bit lines based on repair information, a second cell array including a... Agent: Sk Hynix Inc.
20140177377 - Data signal receiver and method of calibrating a data signal receiver: A method of calibrating a data signal receiver configured to receive a multi-bit data signal and an associated data strobe signal, wherein transitions of the data strobe signal indicate sample points for the multi-bit data signal. The method comprises the steps of: receiving, on each bit of the multi-bit data... Agent: Arm Limited06/19/2014 > 63 patent applications in 31 patent subcategories.
20140169057 - Semiconductor device and information processing system having the same: A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a... Agent: Elpida Memory, Inc.
20140169058 - Semiconductor device and data processing system: Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers... Agent:
20140169059 - Fuse repair device: A fuse repair device may include a first fuse circuit configured to store a first portion out of a failed address, a second fuse circuit configured to store a multipurpose information or a second portion of the failed address, an enable control circuit configured to provide a first enable signal... Agent: Sk Hynix Inc.
20140169061 - Method of implementing a ferroelectric tunnel junction, device comprising a ferroelectric tunnel junction and use of such a device: The invention relates to a method of implementing a ferroelectric tunnel junction, said junction comprising to films each forming an electrode-type conductive element, and separated by a film forming a ferroelectric element acting as the tunnel barrier, said ferroelectric element being able to possess a remanent polarization. According to the... Agent: Centre National De La Recherche Scientifique (c.n.r.s)
20140169060 - Pulse generator and ferroelectric memory circuit: A pulse generator circuit with ferroelectric memory element is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively. Optionally, a third thin film transistor may be provided to operate as... Agent: Palo Alto Research Center Incorporated
20140169070 - Heterojunction oxide non-volatile memory devices: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation... Agent: 4ds, Inc
20140169065 - High voltage generating circuit for resistive memory apparatus: A high voltage generating circuit for a resistive memory apparatus is provided. The high voltage generating circuit includes a capacitor spaced from a semiconductor substrate and electrically insulated from the semiconductor substrate. A switching device, which is electrically connected to the capacitor, is electrically insulated from the semiconductor substrate.... Agent: Sk Hynix Inc.
20140169063 - Method and apparatus for reading variable resistance memory elements: In some embodiments, detecting resistance in a resistive memory cell may be done using a pulse edge. For example, a pulse may be applied through a resistive memory data cell and another through a reference delay circuit to determine which path has the larger delay in order to determine the... Agent:
20140169062 - Methods of manufacturing embedded bipolar switching resistive memory: Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type... Agent: Intermolecular, Inc.
20140169068 - Nonvolatile memory device having variable resistive elements and method of driving the same: A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first... Agent:
20140169064 - Regulator, voltage generator and semiconductor memory device: A regulator includes a variable resistance unit coupled between an input node to which a pumping voltage is inputted and a control node and configured to adjust resistance of the variable resistance unit in response to a control signal varied depending on a target voltage, a voltage output unit configured... Agent: Sk Hynix Inc.
20140169067 - Resistance memory device and memory apparatus and data processing system: A resistance memory device and a memory apparatus and data processing apparatus having the same are provided. The resistance memory device includes a pair of electrode layers and a variable resistance layer interposed between the pair of electrode layers. The variable resistance layer includes at least one variable resistance material... Agent: Sk Hynix Inc.
20140169069 - Resistive memory device, system including the same and method of reading data in the same: A resistive memory device includes a memory cell array, a memory interface and a read sensing circuit. The memory cell array includes a plurality of resistive memory cells coupled to a plurality of wordlines and a plurality of bitlines. The memory interface is configured to communicate with a memory controller.... Agent:
20140169066 - Resistive memory sensing: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of... Agent: Micro Technology, Inc.
20140169072 - Semiconductor device: An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a... Agent: Semiconductor Energy Laboratory Co., Ltd.
20140169073 - Semiconductor integrated circuit with thick gate oxide word line driving circuit: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance... Agent: Renesas Electronics Corporation
20140169071 - Semiconductor memory device: A semiconductor memory device including a plurality of memory blocks each including a first command generating circuit which generates a first command; a control circuit which controls the memory core based on the first command or based on a second command inputted via the input/output port; and an arbitration circuit... Agent: Fujitsu Semiconductor Limited
20140169075 - Memory array voltage source controller for retention and write assist: A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch... Agent: Apple Inc.
20140169074 - Memory elements with stacked pull-up devices: Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may... Agent: Altera Corporation
20140169076 - Power management sram write bit line drive circuit: A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted... Agent: International Business Machines Corporation
20140169077 - Operation aware auto-feedback sram: A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first... Agent:
20140169078 - Piezoelectronic memory: A memory element includes a first piezotronic transistor coupled to a second piezotronic transistor; the first and second piezotronic transistors each comprising a piezoelectric (PE) material and a piezoresistive (PR) material, wherein an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by... Agent: International Business Machines Corporation
20140169086 - Common source semiconductor memory device: A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents... Agent:
20140169081 - Flexible memory and its fabrication process: This invention describes the structure and the fabrication method of a flexible memory. The flexible memory includes eight layers. The three function layers are a flexible layer of hall unit, a flexible layer of horizontal lines, and a flexible layer of vertical lines. The main fabrication process of the flexible... Agent: Nanjing University
20140169083 - Magnetoresistive layer structure with voltage-induced switching and logic cell application: Embodiments of the invention include a voltage-switching MTJ cell structure that includes two sub-MTJs in series. Each free layer can be switched independently from the other. Each sub-MTJ has a high and a low resistance state and the MTJ cell structure can have three or four discrete resistance states. By... Agent: Avalanche Technology Inc.
20140169084 - Memory device: A memory device is described. The memory device comprises an antiferromagnet. The device may comprise an insulator and an electrode arranged in a tunnel junction configuration. Alternatively, the device may comprise first and second contacts to the antiferromagnet for measuring ohmic resistance of the antiferromagnet. The antiferromagnet is not coupled... Agent: Hitachi, Ltd.
20140169087 - Memory element and memory apparatus: A memory element has a layered structure, including a memory layer that has magnetization perpendicular to a film face in which a magnetization direction is changed depending on information, and includes a Co—Fe—B magnetic layer, the magnetization direction being changed by applying a current in a lamination direction of the... Agent: Sony Corporation
20140169079 - Method and apparatus for sensing the state of a magnetic tunnel junction (mtj): A method of measuring the resistance of a magnetic tunnel junction (MTJ) is performed by selecting the MTJ to be measured, the MTJ having a resistance associated therewith and coupled to an access transistor. Further, measuring a voltage at an end of the MTJ that is coupled to the access... Agent: Avalanche Technology, Inc.
20140169088 - Spin hall effect magnetic apparatus, method and applications: An ST-MRAM structure, a method for fabricating the ST-MRAM structure and a method for operating an ST-MRAM device that results from the ST-MRAM structure each utilize a spin Hall effect base layer that contacts a magnetic free layer and effects a magnetic moment switching within the magnetic free layer as... Agent: Cornell University
20140169080 - Thermal spin torqure transfer magnetoresistive random access memory: A thermal spin torque transfer magnetoresistive random access memory (MRAM) apparatus includes a magnetic tunnel junction and a tunnel junction programming circuit. The magnetic tunnel junction includes a reference layer having a fixed magnetic polarity, a tunnel barrier layer, and a free layer on an opposite side of the tunnel... Agent: International Business Machines Corporation
20140169082 - Thermal spin torqure transfer magnetoresistive random access memory: A thermal spin torque transfer magnetoresistive random access memory (MRAM) apparatus includes a magnetic tunnel junction and a tunnel junction programming circuit. The magnetic tunnel junction includes a reference layer having a fixed magnetic polarity, a tunnel barrier layer, and a free layer on an opposite side of the tunnel... Agent: International Business Machines Corporation
20140169085 - Voltage-controlled magnetic memory element with canted magnetization: A memory cell including information that is stored in the state of a magnetic bit (i.e. in a free layer, FL), where the FL magnetization has two stable states that may be canted (form an angle) with respect to the horizontal and vertical directions of the device is presented. The... Agent: The Regents Of The University Of California
20140169089 - Path isolation in a memory device: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line... Agent:
20140169090 - Memory card for storing and transmitting data: A memory card includes a control chip, a buffer, a NAND gate, and an inverter. The memory card has a first surface and a second surface opposite to the first surface. A first group of conductive pins is located on the first surface, and connected to the buffer through a... Agent:
20140169091 - Memory controller, storage device, and memory control method: According to one embodiment, a memory controller controlling a NAND memory having D bits/cell, includes: a code encoder which generates a code word having correction capability of t symbols; a write control unit which controls writing of the code word to the NAND memory; and a code decoder which decodes... Agent: Kabushiki Kaisha Toshiba
20140169092 - Semiconductor memory device: A semiconductor memory device includes a first data bus having a first width, and a second data bus which is separate from the first data bus and which has a second width which is different from the first width. The semiconductor memory device further includes a data transfer unit configured... Agent: Samsung Electronics Co., Ltd.
20140169093 - Erase and soft program for vertical nand flash: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the... Agent:
20140169094 - Data transmission circuit, memory including the same, and data transmission method: A data transmission circuit includes an input line selection unit configured to transfer data of a selected input line among a plurality of input lines to an output line, a data sensing unit connected to the plurality of input lines and configured to sense the data of the selected input... Agent: Sk Hynix Inc.
20140169095 - Select transistor tuning: In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the... Agent: Sandisk Technologies Inc.
20140169096 - Semiconductor memory device and operating method thereof: A semiconductor memory device includes: a memory array including a plurality of memory cells; and a peripheral circuit configured to change a voltage level of a bit line connected to a program target cell according to a threshold voltage of the program target cell among the memory cells during a... Agent: Sk Hynix Inc.
20140169097 - Semiconductor memory device, system having the same and program method thereof: The present invention relates to a semiconductor memory device and a program method thereof. The program method according to an embodiment of the present invention includes: precharging a plurality of cell strings by providing a positive voltage to the plurality of cell strings through a common source line; and performing... Agent: Sk Hynix Inc.
20140169098 - Apparatuses and methods involving accessing memory cells: Apparatuses and methods involving accessing memory cells are described. In one such method, chunks of memory cells in a memory array are enabled to be accessed and then one or more of the chunks are disabled from being accessed. In one such apparatus, an array includes chunks of memory cells... Agent: Micron Technology, Inc.
20140169099 - Memory array: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby... Agent: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
20140169101 - Method compensation operating voltage, flash memory device, and data storage device: Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of... Agent:
20140169100 - Semiconductor device: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line;... Agent: Semiconductor Energy Laboratoy Co., Ltd.
20140169102 - Log-likelihood ratio and lumped log-likelihood ratio generation for data storage systems: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) for upper and lower pages of memory cells in MLC solid-state media. Disclosed are systems and methods for generating lumped-LLR for upper pages, wherein at least some voltage threshold reads are linked together in order... Agent: Western Digital Technologies, Inc.
20140169103 - Methods of forming and programming memory devices with isolation structures: Methods of programming and forming memory devices. Methods of programming include biasing a control gate of a selected memory cell of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a... Agent: Micron Technology, Inc.
20140169104 - Nonvolatile flash memory structures including fullerene molecules and methods for manufacturing the same: Embodiments of tunneling barriers and methods for same can embed molecules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling... Agent: Cornell University
20140169105 - Non-volatile memory device and method of fabricating the same: Disclosed are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device includes a semiconductor substrate including a plurality of active regions and a pair of first pillars protruding from each active region. A pair of drain selection lines surround each pillar of the pair... Agent:
20140169106 - Negative bitline write assist circuit and method for operating the same: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit... Agent:
20140169107 - Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same: A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix... Agent: Micron Technology, Inc.
20140169108 - Mitigating external influences on long signal lines: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit... Agent: Nvidia Corporation
20140169110 - Clock synchronization in a memory system: Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is... Agent:
20140169111 - Device including a plurality of memory banks and a pipeline control circuit configured to execute a command on the plurality of memory banks: A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by... Agent: Elpida Memory, Inc.
20140169109 - Low power register file: Described is an apparatus which comprises: a memory cell with a data port; and a logic gate, coupled to the data port of the memory cell, to generate a data word-line signal according to data on the data port and an asynchronous word-line signal, wherein the logic gate is operable... Agent:
20140169112 - Semiconductor memory system and operating method thereof: A semiconductor memory system configured to exchange signals through channels may include a memory control device configured to have a plurality of channels, a plurality of memory devices configured to be connected to each of the plurality of channels, wherein the plurality of channels share at least one of the... Agent: Sk Hynix Inc.
20140169113 - Enhancing memory yield through memory subsystem repair: A memory system and a memory repair method for the memory system are disclosed. The method includes the steps of: organizing at least one repair block to serve as a shared repair resource for the plurality of memory blocks in the tiled memory; identifying a defective memory unit among the... Agent:
20140169114 - Volatile memory devices, memory systems including the same and related methods: A volatile memory device includes a memory cell array including a plurality of pages and a refresh control circuit. The refresh control circuit may adjust a refresh interval according to a refresh information signal and refreshes the plurality of pages according to the adjusted refresh interval while refreshing weak pages... Agent: Samsung Electronics Co., Ltd.
20140169115 - Auxiliary power device and user system including the same: A user system is provided which includes a storage device and an auxiliary power device configured to supply a power to the storage device, wherein the auxiliary power device includes a first one direction device configured to supply a supply voltage from an external power supply to the storage device,... Agent: Samsung Electronics Co., Ltd.
20140169116 - Circuitry and methods minimizing output switching noise through split-level signaling and bus division enabled by a third power supply: Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx... Agent: Micron Technology, Inc.
20140169118 - Address input circuit of semiconductor apparatus: An address input circuit of a semiconductor device includes: an address latch unit configured to generate latch addresses, by latching addresses sequentially provided by an external, according to a command decoding signal, wherein latch timings of each of the addresses are adjusted differently from one another; and a command decoder... Agent: Sk Hynix Inc.
20140169117 - Decoder circuit with reduced current leakage: A decoder circuit with reduced leakage configured to decode an address and drive one of a number of word lines may be implemented with two-high logic gates in a pre-decode stage, a decode stage, and a word line driver stage. Such decoder circuits may include, in the word line driver... Agent: Oracle International Corporation
20140169119 - Memory system having delay-locked-loop circuit: A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay... Agent:Previous industry: Electric power conversion systems
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