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Static information storage and retrieval

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
06/11/2015 > patent applications in patent subcategories.
06/04/2015 > patent applications in patent subcategories.
05/28/2015 > 27 patent applications in 17 patent subcategories.

20150146469 - Magnetic memory devices and systems: A method of storing one or more bits of information comprising: forming a magnetic bubble; and storing a said bit of information encoded in a typology of a domain wall of said magnetic bubble. Preferably a bit is encoded using a symmetric topological state of the domain wall and a... Agent:

20150146470 - Write assist circuit for write disturbed memory cell: A circuit comprises a first memory cell, a second memory cell, and a disturb control circuit. The first memory cell has a first port and a second port. The first port is associated with a first write assist circuit. The second port is associated with a second write assist circuit.... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150146471 - Anti-fuse array of semiconductor device and method for operating the same: An anti-fuse array includes: a plurality of first transistors having a matrix structure over a semiconductor substrate; a plurality of second transistors respectively disposed adjacent to first ends of the plurality of first transistors along a first direction of the matrix structure; and a plurality of third transistors respectively disposed... Agent: Sk Hynix Inc.

20150146474 - Memory device and method of controlling memory device: According to one embodiment, a memory device includes a plurality of global column lines arranged in parallel and extending in a first direction; a plurality of row lines extending in a second direction which is perpendicular to the first direction; a plurality of column lines in a two-dimensional arrangement, which... Agent: Kabushiki Kaisha Toshiba

20150146472 - Memory systems and memory programming methods: Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory... Agent: Micron Technology, Inc.

20150146473 - Resistive memory apparatus and write-in method thereof: A resistive memory apparatus and a write-in method thereof are provided. The memory controller provides unselected bit-lines and unselected word-lines both not coupled to a selected resistive memory cell respectively with a first bit-line voltage and a first word-line voltage in one of a setting duration and a resetting duration,... Agent: Winbond Electronics Corp.

20150146475 - Memory sense amplifier with multiple modes of operation: Memory circuitry comprising an array of 6T bit cells 6 in which columns of bit cells are coupled together via bit line pairs 8 connected to respective sense amplifier circuitry 10 is provided. The sense amplifier circuitry includes an inverter pair 12, 14 and control circuitry which is configured to... Agent: The Regents Of The University Of Michigan

20150146476 - Passive sram write assist: Passive write assist passively improves SRAM performance (e.g., write margin speed) while reducing manufacturing costs (e.g., die area, packaging) and operating costs (e.g., power consumption, cooling) associated with active write assist schemes. Passive write assist may be implemented in peripheral circuitry or embedded in an SRAM array or even in... Agent: Broadcom Corporation

20150146477 - Semiconductor device: In order to solve a problem that a calibration period for generating a signal obtained by delaying a core clock in a programmable manner is overhead in initialization, a clock generation circuit generates a plurality of delayed clocks having different phases by delaying a core clock which is an operation... Agent:

20150146478 - Sram bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter: Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would... Agent:

20150146480 - Novel 3d structure for advanced sram design to avoid half-selected issue: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150146479 - Sram write-assisted operation with vdd-to-vcs level shifting: An electronic circuit and a method for driving data writes to an SRAM bit cell in an electronic circuit. The electronic circuit translates a first write signal in a lower voltage domain to a second write signal in a higher voltage domain. Based, at least in part, on the second... Agent: International Business Machines Corporation

20150146483 - Differential current sensing scheme for magnetic random access memory: A circuit includes a cell segment, first and second reference cells, and a current sense amplifier. The first and second reference cells are configured to store opposite logic values, respectively. The current sense amplifier is configured with a first node and a second node for currents therethrough to be compared... Agent:

20150146482 - Method and apparatus for reading a magnetic tunnel junction using a sequence of short pulses: A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the... Agent:

20150146481 - Method and apparatus for sensing tunnel magneto-resistance: In one embodiment, an apparatus comprises: an MRAM (magnetic random access memory) cell array comprising a plurality of MRAM cells including a calibration cell and a plurality of data cells; a reference MRAM cell controlled by a control signal; and a sensing-amplifier/latch; wherein: said plurality of data cells are used... Agent: Realtek Semiconductor Corp.

20150146484 - Memory system including multi-level memory cells and programming method using different program start voltages: A method of programming multi-level memory cells includes defining a first program start voltage and a second program start voltage higher than the first program start voltage, programming first memory cells among the MLC to the first program state using a program operation that begins programming of the first memory... Agent:

20150146485 - Method of programming non-volatile memory device and non-volatile memory device using the same: A program method of a nonvolatile memory device according to example embodiments includes a operation (a) of detecting a level of a program voltage; and a operation (b) of providing a unselected word line voltage and a bit line precharge voltage having a variable level respectively according to the detected... Agent:

20150146486 - Data storage device and flash memory control method: A data storage device using a FLASH memory with replay-protected blocks. The storage space of the FLASH memory is divided into blocks and each block is further divided into pages. A controller is provided in the data storage device to couple to the FLASH memory. The controller manages at least... Agent: Silicon Motion, Inc.

20150146487 - Non-volatile memory device and method for erasing the same: Provided are a non-volatile memory device and a method for erasing the non-volatile memory device having vertical channel layers formed with different widths varying by height and a plurality of memory cells stacked along the vertical channel layers, the method including increasing potentials of the vertical channel layers, and when... Agent: Sk Hynix Inc.

20150146488 - Semiconductor device and program fail cells: A semiconductor device includes a memory block including even memory cells configured to form an even page and odd memory cells configured to form an odd page. The semiconductor device may also include an operation circuit configured to perform a program operation on the even memory cells and the odd... Agent: Sk Hynix Inc.

20150146489 - Method of operating nonvolatile memory device: In a method of operating a nonvolatile memory device having a substrate and first through n-th word lines stacked in a direction perpendicular to the substrate, first through k-th word line voltages are applied to first through k-th word lines, respectively, which are formed adjacent to the substrate, among the... Agent:

20150146490 - Non-volatile memory with reduced sub-threshold leakage during program and erase operations: A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is... Agent: Stmicroelectronics S.r.l.

20150146491 - In-memory computational device: A computing device comprising includes a memory array having a plurality of sections with memory cells arranged in rows and column, at least one cell in each column of the memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical... Agent:

20150146492 - Semiconductor devices: The semiconductor device includes an input clock generator and a data input unit. The input clock generator generates an input clock signal including a first pulse and a second pulse, wherein the first pulse is generated in response to a write signal and a write latency signal and the second... Agent: Sk Hynix Inc.

20150146493 - Non-volatile memory validity: An embodiment provides a method, including: determining current validity timing of a non-volatile memory device having changing validity timing via: writing information to a non-volatile memory device; waiting a time after the writing; and reading the information written to the non-volatile memory device following the time. Other aspects are described... Agent: Lenovo (singapore) Pte. Ltd.

20150146494 - Partial access mode for dynamic random access memory: Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2N cells/bit reduces the variation in the retention time among memory cells. The conversion can be realized very simply from the structure of the DRAM array... Agent: Micron Technology, Inc.

20150146495 - Semiconductor device including a clock adjustment circuit: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time... Agent:

05/21/2015 > 46 patent applications in 24 patent subcategories.

20150138861 - Content addressable memory: This disclosure provides a content addressable memory which includes: a data memory cell for storing a data bit; a mask memory cell for storing a mask bit; and a comparing and readout unit connected to at least one read word line for receiving at least one read word signal, connected... Agent:

20150138862 - Three-dimensional semiconductor devices and fabricating methods thereof: A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of... Agent:

20150138863 - Interleaved write assist for hierarchical bitline sram architectures: An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a... Agent: Lsi Corporation

20150138864 - Memory architecture with alternating segments and multiple bitlines: Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization... Agent: Lsi Corporation

20150138865 - Semiconductor memory device and driving method thereof: A semiconductor memory device in which capacitance of a capacitor is lower and integration degree is higher. A plurality of memory blocks is connected to one bit line BL_m. A memory block MB_n_m includes a sub bit line SBL_n_m, a write switch, and a plurality of memory cells. A sub... Agent:

20150138866 - Semiconductor memory: According to an embodiment, a semiconductor memory includes word lines, a plurality of sets of a pair of bit lines, memory cells, a writing/reading circuit, and a word line selection circuit. In a state where inverted data of program data has been written to the memory cells, a stress is... Agent: Kabushiki Kaisha Toshiba

20150138868 - Bitline circuits for embedded charge trap multi-time-programmable-read-only-memory: A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit,... Agent: International Business Machines Corporation

20150138869 - Non-volatile memory: A non-volatile memory includes a memory unit. The memory unit includes a first word line, a second word line, a control line, a logic circuit, a bit line, a first cell, and a second cell. The logic circuit has a first input terminal connected to the first word line, a... Agent: Faraday Technology Corporation

20150138870 - One-time programmable memory and system-on chip including one-time programmable memory: A one-time programmable (OTP) memory includes an OTP cell array including a plurality of OTP cells that each include a programming transistor configured to change irreversibly when programmed; a temperature compensation reference voltage generating unit configured to sense a temperature of the OTP cell memory and generate a reference voltage... Agent:

20150138867 - Wordline decoder circuits for embedded charge trap multi-time-programmable-read-only-memory: Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage... Agent: International Business Machines Corporation

20150138874 - Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some... Agent:

20150138872 - Electronic device including a memory and method for fabricating the same: An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes first lines extending along a first direction; second lines extending along a second direction that intersects with the first direction; a silicon-added metal oxide layer disposed in each intersection region of the first lines and the second... Agent: Sk Hynix Inc.

20150138871 - Memory structure and operation method therefor: Provided is an operation method applicable to a resistive memory cell including a transistor and a resistive memory element. The operation method includes: in a programming operation, generating a programming current flowing through the transistor and the resistive memory element so that a resistance state of the resistive memory element... Agent: Macronix International Co., Ltd.

20150138873 - Silicon based nanoscale crossbar memory: The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further... Agent:

20150138875 - Stabilization of resistive memory: The present disclosure includes apparatuses and methods including stabilization of resistive memory. A number of embodiments include applying a programming signal to a resistive memory cell, wherein the programming signal includes a first portion having a first polarity and a second portion having a second polarity, wherein the second polarity... Agent:

20150138876 - Global bitline write assist for sram architectures: An SRAM device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment. The SRAM device further includes a global bitline traversing the segmented memory cell array and communicatively coupled to the... Agent: Lsi Corporation

20150138878 - Electronic apparatus: This invention makes is possible to protect programs and shorten the activation time of an electronic apparatus even if a non-volatile memory such as an MRAM stores the programs including a boot program, and is used as a main memory. Upon power-on or receiving a reset signal, a program stored... Agent:

20150138877 - Nonvolatile logic gate device: A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of... Agent: Nec Corporation

20150138879 - Read circuit for memory: Embodiments are directed to detecting a state of a memory element in a memory device, comprising: applying a pulse of a predetermined magnitude and duration to the memory element to induce a transition in the state of the memory element when a polarity of the pulse is opposite to the... Agent:

20150138880 - Memory cells having a plurality of resistance variable materials: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable... Agent:

20150138881 - Thyristor memory cell integrated circuit: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row... Agent: The University Of Connecticut

20150138883 - Non-volatile semiconductor device: A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a... Agent:

20150138882 - Nonvolatile memory devices, operating methods thereof and memory systems including the same: Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to... Agent:

20150138884 - Memory systems including nonvolatile buffering and methods of operating the same: A nonvolatile memory system can include a nonvolatile memory device that can be configured to store data and a nonvolatile memory buffer circuit that can be configured to store data of a type that is predetermined to be flushed to the nonvolatile memory device in a sudden power off backup... Agent:

20150138885 - Non-volatile semiconductor storage device, and semiconductor device: A non-volatile semiconductor storage device includes a memory cell array divided into blocks, each of which is a erasable unit, the blocks, the blocks including a first block which is determined to be a bad block and a second block which is determined to be a partial bad block, a... Agent: Kabushiki Kaisha Toshiba

20150138888 - Memory system: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to... Agent: Kabushiki Kaisha Toshiba

20150138887 - Method and system for improving the radiation tolerance of floating gate memories: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel... Agent:

20150138889 - Method of programming non-volatile memory device and apparatuses for performing the method: A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells... Agent:

20150138886 - Non-volatile semiconductor storage device, and memory system: A non-volatile semiconductor storage device includes an memory cell array including first and second blocks, each of which includes a plurality of memory strings each having n (n: natural number) memory cells, and a optionally a peripheral circuit for controlling the memory cell array. In this non-volatile semiconductor storage device,... Agent: Kabushiki Kaisha Toshiba

20150138890 - Nonvolatile memory devices and driving methods thereof: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.... Agent: Samsung Electronics Co., Ltd.

20150138891 - Embedded charge trap multi-time-programmable-read-only-memory for high performance logic technology: An embedded Multi-Time-Read-Only-Memory having a (MOSFET) cells' array having an initial threshold voltage (VT0) including the MOSFETs arranged in a row and column matrix, having gates in each row coupled to a wordline (WL) running in a first direction and sources in each one of the columns coupled to a... Agent: International Business Machiness Corporation

20150138892 - Single poly eeprom device: The present invention proposes a single poly EEPROM cell including a first control gate capacitor, a first tunnel gate capacitor, a first sense transistor, and a first selection transistor. In a single poly EEPROM cell according to the present invention, a Fowler Nordheim (FN) tunneling method is used in order... Agent: Changwon National University Industry Academy Cooperation Corps

20150138893 - High voltage switch, nonvolatile memory device comprising same, and related method of operation: A high voltage switch operates in response to a first drive voltage and a second drive voltage higher than the first drive voltage. The high voltage switch comprises a PMOS transistor transmitting the second drive voltage to an output terminal according to a voltage applied to its gate, a first... Agent:

20150138894 - Finding optimal read thresholds and related voltages for solid state memory: A read is performed using a first iteration of a read threshold voltage that is set to a default voltage to obtain a first characteristic. A second iteration of the read threshold voltage is generated using the default voltage and an offset. A read is performed using the second iteration... Agent:

20150138899 - Data storage device and operating method thereof: An operating method of a data storage device may include performing a first write operation on a first memory region, and performing a second write operation on a second memory region to store position information on the first write operation.... Agent: Sk Hynix Inc.

20150138900 - Data storage device and operating method thereof: An operating method of a data storage device includes performing a read operation on a nonvolatile memory device based on a read request and a logical address from a host device, determining whether one or more physical addresses, which correspond to one or more logical addresses continuous to the logical... Agent: Sk Hynix Inc.

20150138895 - High capacity memory system using standard controller component: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of... Agent:

20150138896 - Apparatuses and methods for performing logical operations using sensing circuitry: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation... Agent:

20150138898 - Shared tracking circuit: A system includes a first plurality of memory macros and a first tracking circuit associated with a memory macro of the first plurality of memory macros. Each memory macro of the first plurality of memory macros includes a corresponding global control circuit configured to receive a first reset signal. The... Agent:

20150138897 - Stack position determination in memory devices configured for stacked arrangements: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is... Agent:

20150138901 - Memory circuitry using write assist voltage boost: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is... Agent: Arm Limited

20150138902 - Three-dimensional (3-d) write assist scheme for memory cells: An integrated circuit that includes an array of memory cells and an array of write logic cells. The integrated circuit also includes a write address decoder comprising a plurality of write outputs. The array of write logic cells is electrically connected to the plurality of write outputs. The array of... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150138903 - Writing to multi-port memories: A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is... Agent:

20150138904 - Memory circuit and method of operating the memory circuit: A memory circuit includes a memory cell, a data line configured to be coupled with the memory cell, a node, a precharge circuit, a first transistor of a first type, and a second transistor of the first type. The precharge circuit is configured to charge the node toward a predetermined... Agent:

20150138905 - Low leakage state retention synchronizer: Described is an apparatus which comprises: a first memory unit having an input and an output, wherein the first memory unit operates on a first power supply which is operable to be turned off; a second memory unit having an input coupled to the output of the first memory unit,... Agent:

20150138906 - Systems and methods for non-volatile memory: A self powered memory system is disclosed. The system includes a volatile supply component, a battery component, a switch component, and a volatile memory component. The volatile supply component is configured to provide a time varying supply. The battery component is configured to generate a non-volatile supply. The switch component... Agent: Infineon Technologies Ag

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