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Independent 3d stacking / Apple Inc.




Independent 3d stacking


Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a first level die encapsulated in an oxide layer, and a plurality of through oxide vias (TOVs) extending through the oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less.



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USPTO Applicaton #: #20170053897
Inventors: Kwan-yu Lai, Jun Zhai, Kunzhong Hu


The Patent Description & Claims data below is from USPTO Patent Application 20170053897, Independent 3d stacking.


CROSS-REFERENCE TO RELATED APPLICATIONS

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This application claims the benefit of priority from U.S. Provisional Application No. 62/208,544, filed on Aug. 21, 2015, which is herein incorporated by reference.

BACKGROUND

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Field

Embodiments described herein relate to semiconductor packaging. More particularly, embodiments relate to packages including 3D stacked die.

Background Information

The current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming, and other mobile devices requires the integration of more performance and features into increasingly smaller spaces. Additionally, while the form factor (e.g. thickness) and footprint (e.g. area) for semiconductor die packaging is decreasing, the number of input/output (I/O) pads is increasing.

Various multiple-die packaging solutions such as system in package (SiP) and package on package (PoP) have become more popular to meet the demand for higher die/component density devices. In an SiP a number of different die are enclosed within the package as a single module. Thus, the SiP may perform all or most of the functions of an electronic system.

A 3D stacking implementation such as chip on wafer (CoW) includes mounting of die onto a support wafer, followed by singulation of stacked die SiPs. A 3D stacking implementation such as wafer to wafer (W2 W) includes mounting of a top wafer onto a bottom wafer, followed by singulation of stacked die SiPs. Both of the conventional 3D stacking implementations require that one of the package level tiers (e.g. mounted die, or die within wafer) to be bigger or equal to the other tier. For example, CoW may involve the singulated area of the support wafer being bigger than the die mounted on the support wafer, while W2 W may involve equal areas of the singulated wafers.

SUMMARY

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Embodiments describe semiconductor die packages. In one embodiment, a package includes a first level redistribution layer (RDL), and a front side of a first package level on the RDL. The first package level includes one or more first level die encapsulated within a gap fill oxide layer on the RDL. A plurality of through oxide vias (TOVs) extend through the gap fill oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less. A second level die is included in a second package level, and the second level die is hybrid bonded to a back side of the first package level, with the hybrid bond including direct bonded oxide-oxide surfaces and direct bonded metal-metal surfaces. The second level die may be encapsulated in molding compound, for example, on the first package level. In an embodiment, the RDL is formed on an in electrical contact with a front side of the first level die and the plurality of TOVs.

In an embodiment, the first package level includes a first package level RDL on a back side of the first level die and the gap fill oxide layer. The second level die may be hybrid bonded to a planarized back surface of the first package level RDL. For example, the first package level RDL may include an oxide dielectric layer and metal redistribution line, and the second level die is hybrid bonded to the oxide dielectric layer and the metal redistribution line. The first level die may include a plurality of through silicon vias (TSVs), with the first package level RDL formed on an in electrical contact with the plurality of TSVs.

In accordance with some embodiments, the TOVs may be arranged in rows. For example, the plurality of TOVs may include a first row of TOVs and a second row of TOVs. In a particular arrangement, the first and second rows of TOVs are laterally adjacent to a first pair of laterally opposite sides of the first level die. A second-first level die and a third-first level die can be located laterally adjacent to a second pair of laterally opposite sides of the first level die. In such an arrangement, the RDL may be formed on an in electrical contact with a front side of the first level die, a front side of the second-first level die, a front side of the third-first level die, the first row of TOVs, and the second row of TOVs. The first level die may additionally include a plurality of TSVs, for example, with a maximum width of about 10 microns or less.

In an embodiment, a package includes an RDL, and a front side of a first package level on a back side of the RDL. A first level die is encapsulated in a gap fill oxide layer on the back side of the RDL. A first row of TOVs and a second row of TOVs protrude from the back side of the RDL, and the first level die is located laterally between the first and second rows of TOVs. A plurality of second level die are hybrid bonded to a back side of the first package level with direct bonded oxide-oxide surfaces and direct bonded metal-metal surfaces.

The first package level may additionally include a first package level RDL on a back side of the first level die and the gap fill oxide layer. For example, the first package level RDL may include an oxide dielectric layer and a metal redistribution line, and the second level die is hybrid bonded to the oxide dielectric layer and the metal redistribution line.

The first package level may additionally include a second-first level die and a third-first level die laterally adjacent to opposite sides of the first level die. The first level die, second-first level die, and third-first level die may all be on an in electrical contact with the RDL. In an embodiment, the first level die is rectangular, the first and second rows of TOVs are laterally adjacent to a first pair of laterally opposite sides of the first level die, and the second-first level die and the third-first level die are laterally adjacent to a second pair of laterally opposite sides of the first level die. In accordance with embodiments, the first level die, the first row of TOVs, and the second row of TOVs may all have a height of 20 microns or less. In accordance with embodiments, a plurality of TSVs may be within the first level die, with each TSV having a maximum width of 10 microns or less.

In an embodiment, a method of forming a package includes forming a first package level on a carrier substrate, the first package level including a first level die encapsulated in a gap fill oxide layer, and a plurality of though oxide vias (TOVs). The TOVs may have a height of about 20 microns or less. A second level die is hybrid bonded to the first package level with direct bonded oxide-oxide surfaces and metal-metal surfaces. The second level die is encapsulated on a back side of the first package level. The carrier substrate is removed, and a RDL is formed on a front side of the first package level.

In an embodiment, the method of forming the package additionally includes attaching the first level die to the carrier substrate, depositing the gap fill oxide layer over the first level die, planarizing the gap fill oxide layer, and forming the plurality of TOVs in the gap fill oxide layer. In an embodiment, the first level die is ground to reduce a thickness of the first level die after attaching the first level die to the carrier substrate and prior to depositing the gap fill oxide layer over the first level die. In an embodiment, a first level RDL is formed on the planarized gap fill oxide layer and first level die, and the first level RDL is planarized, and the second level die is hybrid bonded to the planarized first level RDL.

BRIEF DESCRIPTION OF THE DRAWINGS

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FIG. 1 is a flow chart illustrating a method of forming a package in accordance with an embodiment.

FIG. 2 is a schematic cross-sectional side view illustration of a first level die including blind vias in accordance with an embodiment.

FIG. 3 is a cross-sectional side view illustration of first level die attached to a carrier substrate in accordance with an embodiment.

FIG. 4 is a cross-sectional side view illustration of thinned first level die in accordance with an embodiment.

FIG. 5 is a cross-sectional side view illustration of a gap fill oxide layer formed over thinned first level die in accordance with an embodiment.

FIG. 6 is a cross-sectional side view illustration of a planarized gap fill oxide layer including through oxide vias in accordance with an embodiment.

FIG. 7 is a cross-sectional side view illustration of a first level redistribution layer formed over a planarized gap fill oxide layer including through oxide vias in accordance with an embodiment.

FIG. 8 is a cross-sectional side view illustration of a first package level including a planarized first level redistribution layer in accordance with an embodiment.

FIG. 9 is a cross-sectional side view illustration including a close-up view of second level die hybrid bonded to a first package level in accordance with an embodiment.

FIG. 10 is a cross-sectional side view illustration of encapsulated second level die on a first package level in accordance with an embodiment.

FIG. 11 is a cross-sectional side view illustration of package including hybrid bonded second level die in accordance with an embodiment.

FIG. 12 is a cross-sectional side view illustration of package including a thinned second package level in accordance with an embodiment.

FIG. 13 is a schematic bottom view illustration of a package including stacked die, through oxide vias, and through silicon vias in accordance with an embodiment.

FIG. 14 is a flow chart illustrating a method of forming a package in accordance with an embodiment.




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stats Patent Info
Application #
US 20170053897 A1
Publish Date
02/23/2017
Document #
14935310
File Date
11/06/2015
USPTO Class
Other USPTO Classes
International Class
/
Drawings
18


Packages

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20170223|20170053897|independent 3d stacking|Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a first level die encapsulated in an oxide layer, and a plurality of through oxide vias (TOVs) extending through the oxide layer. In an |Apple-Inc
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