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Method for duty cycle distortion detection through decision feedback equalizer taps / Oracle International Corporation




Method for duty cycle distortion detection through decision feedback equalizer taps


An embodiment includes a receiver circuit, a feedback circuit and a control circuit. The receiver circuit is configured to receive each data bit of a plurality of data bits. The feedback circuit is configured to measure a first interference level generated by a first data bit of a first subset of the plurality of data bits on a second data bit of the plurality of data bits to generate one of a first plurality of feedback values. The feedback circuit is also configured...



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USPTO Applicaton #: #20160301435
Inventors: Jianghui Su, Yan Yan, Jieda Li


The Patent Description & Claims data below is from USPTO Patent Application 20160301435, Method for duty cycle distortion detection through decision feedback equalizer taps.


BACKGROUND

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OF THE INVENTION

1. Field of the Invention

This invention relates to high performance computing network systems, and more particularly, to clock and data recovery methods for systems using serialized data transmission.

2. Description of the Relevant Art

The performance of computing systems is dependent on both hardware and software. In order to increase the throughput of computing systems, the parallelization of tasks is utilized as much as possible. To this end, compilers may extract parallelized tasks from program code and hardware may include multiple copies of structures to execute the parallelized tasks. The structures may include functional units, processor cores, and nodes.

Communication between the multiple structures may utilize wide communication buses, i.e., buses that transport data words of 16-bits, 32-bits, 64-bits, or more in parallel. The physical implementation of such communication buses may consume significant area/cost on an integrated circuit (IC), a circuit board or in cables between circuit boards. Additionally, cross-capacitance, electromagnetic interference (EMI), and parasitic inductance on wide buses increase the power consumption and noise effects of the computing system. Such parasitic effects may become more pronounced with increased operational frequencies and reduced geometric dimensions of the wide buses themselves, bond wires, integrated circuit (IC) package leads, and external supply lines. Mismatch of impedance values at the end of transmission lines may result in reflection or ringing, increased propagation delays, and voltage droop of the signals being transmitted.

Reducing the problems with high-speed parallel data transmission may include use of high-speed serial communication. Several examples of high-speed serial communications standards include wired standards, such as, Ethernet, Universal Serial Bus (USB, and USB 3.0 in particular), and Serial AT Attachment (SATA). While these examples typically involve communication over a length of cable between two circuit boards, high-speed serial communications may be used between devices on a common circuit board or between functional blocks within a single IC. Serial communication is also used in wireless standards, such as Wi-Fi™ and Bluetooth™. One way of further reducing communication lines and the associated issues is by eliminating a dedicated clock signal in the communication path. In some embodiments, a receiver may share a clock source with a transmitter and therefore may not require a separate clock signal. However, if a clock signal is not shared between a transmitter and a receiver, then a method for transmitting a clock signal from the transmitting circuit to the receiving circuit is required. One method for transmitting a clock signal is to embed the clock signal within the data stream.

A challenge may arise from variations of the duty cycle of a received stream of data bits from a transmitter. Generally speaking, a 50% duty cycle is desired such that the length of time each bit of data is valid is the same for each data bit. If the duty cycle deviates from 50% then the data bit valid times will alternate between being long and short. For example, in a 1 Gigabit per second (Gbps) communication link, a 50% duty cycle results in each data bit being valid for 1 nanosecond. If the duty cycle deviates to 60%, then the data bits will alternate between being valid for 1.2 nanoseconds and 0.8 nanoseconds. The shorter bit times may result in errors by the receiver reading the data.

SUMMARY

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OF THE EMBODIMENTS

Systems and methods for improving the reliability and accuracy of clock and data recovery within systems using serialized data transmission are contemplated. In one embodiment, an apparatus may include a receiver circuit, a feedback circuit, and a control circuit. The receiver circuit may be configured to serially receive each data bit of a plurality of data bits. The feedback circuit may be configured to measure a first level of interference generated by a first data bit of a first subset of the plurality of data bits on a second data bit of the plurality of data bits to generate a respective one of a first plurality of feedback values. The second data bit may be received subsequent to the first data bit. The feedback circuit may also be configured to measure a second level of interference generated by a third data bit of a second subset of the plurality of data bits on a fourth data bit of the plurality of data bits to generate a respective one of a second plurality of feedback values. The fourth data bit may be received subsequent to the third data bit. The control circuit may be configured to determine a value of a duty cycle dependent upon a comparison of the first plurality of feedback values to the second plurality of feedback values.

In another embodiment, the control circuit may be further configured to determine an amount of variance of the value of the duty cycle from a target duty cycle value. In a further embodiment, the control circuit may be further configured to send a value corresponding to the amount of variance to a transmitter circuit responsible for sending the plurality of data bits to the receiver circuit.

In one embodiment, the first data bit of the first subset of the plurality of data bits may occupy an odd numbered sequence position. In a further embodiment, the third data bit of the second subset of the plurality of data bits may occupy an even numbered sequence.

In another embodiment, the plurality of data bits may include a pseudo random binary sequence (PRBS). In a further embodiment, the receiver circuit may be further configured to receive the PRBS during a calibration operation.

These and other embodiments will become apparent upon reference to the following description and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

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FIG. 1 is a generalized block diagram illustrating an embodiment of a computer system.

FIG. 2 is a generalized block diagram illustrating an embodiment of a serial communication link.

FIG. 3 includes two figures, FIG. 3A illustrating an embodiment of a transmitter in a serial communication link and FIG. 3B illustrating a timing diagram associated with FIG. 3A.

FIG. 4 illustrates an embodiment of a receiver in a serial communication link.

FIG. 5 is a representation of a timing diagram of a serial data stream corresponding to an embodiment of a serial communication link.

FIG. 6 includes two figures. FIG. 6A is a representation of a timing diagram illustrating two embodiments of serialized data from an embodiment of a serial communication link. FIG. 6B is an illustration of two graphs of feedback magnitudes corresponding to the embodiment of FIG. 6A.

FIG. 7 is a flow diagram illustrating a method for detecting duty cycle distortion in an embodiment of a receiver in a serial communication link.

FIG. 8 is a flow diagram illustrating a method for correcting duty cycle distortion in an embodiment of a transceiver in a serial communication link.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the disclosure to the particular form illustrated, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include,” “including,” and “includes” mean including, but not limited to.

Various units, circuits, or other components may be described as “configured to” perform a task or tasks. In such contexts, “configured to” is a broad recitation of structure generally meaning “having circuitry that” performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, paragraph (f), interpretation for that unit/circuit/component. More generally, the recitation of any element is expressly intended not to invoke 35 U.S.C. §112, paragraph (f), interpretation for that element unless the language “means for” or “step for” is specifically recited.

DETAILED DESCRIPTION

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OF EMBODIMENTS

In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, one having ordinary skill in the art should recognize that the invention may be practiced without these specific details. In some instances, well-known circuits, structures, signals, computer program instruction, and techniques have not been shown in detail to avoid obscuring the present invention.

Some examples of applications utilizing serial communication links include network routers (wired and wireless), fiber optic communication systems, gigabit Ethernet systems, flat panel displays, Bluetooth links between portable devices and components, and cache coherence links in chip multi-threading (CMT) systems with multiple nodes. An example of a hard disk drive (HDD) connected to a processor mother board through a high speed serial interface, utilizing serial communication links is provided as an illustration of duty cycle distortion (DCD) detection and correction methods. The high speed serial interface may be any suitable standard such as, e.g., Serial Advance Technology Attachment (SATA) or Universal Serial Bus 3.0 (USB 3.0), or may be a proprietary high speed interface. Although a HDD connection through a high speed serial interface is used as an example, the steps and techniques described may be applied to other systems such as gigabit Ethernet or Fibre Channel networks.

In view of the above, methods and mechanisms for detecting and correcting duty cycle distortion within systems using serial data transmission are desired. Various embodiments of a serial communication link are described in this disclosure. The embodiments illustrated in the drawings and described below may provide techniques for detecting and correcting duty cycle distortion within a serial communication link.

Serial Communication Link Overview

Referring to FIG. 1, a generalized block diagram illustrating one embodiment of a computing system 100 is shown. Computing system 100 may include host processor 101, coupled to communication unit 110a through interface 105. Communication unit 110a may be coupled to communication unit 110b through communication channels 120a and 120b. Communication unit 110b may be coupled to hard disk drive (HDD) 150 through interface 130.

Host processor 101 may request a file from HDD 150. In some embodiments, host processor 150 may be a motherboard including one or more processor cores. In some embodiments, the processor cores may implement any suitable instruction set architecture (ISA), such as, e.g., SPARC, PowerPC™, or x86 ISAs, or a combination thereof. Host processor 101 may include one or more bus interfaces, such as, e.g., interface 105, which may allow host processor 101 to communication to other functional blocks within SoC 100 such as, communication unit 110a for example. Interface 105 may be a parallel bus interface of any suitable width, such as, for example 16, 32, or 64 bits wide.




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stats Patent Info
Application #
US 20160301435 A1
Publish Date
10/13/2016
Document #
14681796
File Date
04/08/2015
USPTO Class
Other USPTO Classes
International Class
/
Drawings
9


Decision Feedback Equalizer Duty Cycle

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Oracle International Corporation


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20161013|20160301435|duty cycle distortion detection through decision feedback equalizer taps|An embodiment includes a receiver circuit, a feedback circuit and a control circuit. The receiver circuit is configured to receive each data bit of a plurality of data bits. The feedback circuit is configured to measure a first interference level generated by a first data bit of a first subset |Oracle-International-Corporation
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