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1. Technical Field
Embodiments described herein are related to the field of high-speed interface design, and more particularly to bit stream encoding techniques.
2. Description of the Related Art
Computing systems typically include a number of interconnected integrated circuits. In some cases, the integrated circuits may communicate through parallel interfaces, which simultaneously communicate multiple bits of data. In other cases, the integrated circuits may employ a serial interface, which sequentially communicates one bit of data at a time. In some cases, both parallel and serial interfaces, individual bits of communicated data may be differentially encoded.
In some cases, the integrated circuits or devices within a computing system may communicate over the serial or parallel interfaces using one of various communication protocols. Such protocols may allow for the transmission of messages between various components of the computing system in addition to the transmission of data. The transmitted messages may include reports of levels of activity, requests for specific modes of operation, and the like.
During operation a computing system, data to be transmitted may be encoded prior to transmission. In cases where a parallel interface is employed, such encoding may be employed to reduce an amount of switching noise. Alternatively, encoding may be used to produce a sufficient number of data transitions to allow clock and data recovery circuits to properly lock to a received data stream.
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OF THE EMBODIMENTS
Various embodiments of an apparatus to encode a serial data are disclosed. Broadly speaking, a system and method are contemplated that includes a logic circuit, an encoder circuit, and a transmit unit. The encoder circuit may be configured to receive an ordered stream of data bits from the logic circuit and select N sequential data bits of the ordered stream of data bits, where N is a positive integer. The encoder circuit may then select M sequential data bits of the N sequential data bits, where M is a positive integer less than N. The M sequential data bits may then be encoded, by the encoder circuit, to produce an encoded code word. The encoded code word may include P data bits, where P is a positive integer greater than M and less than N. The encoder circuit may then concatenate the encoded code word with a proper subset of the N sequential data bits to form a transmission word, where the proper subset excludes the M sequential data bits. The transmit unit may then transmit the transmission data word in a serial fashion.
In one embodiment, the encoded code word includes a first data bit at a first bit location in the encoded code word and a second data bit a second bit location in the encoded code word. The second bit location is adjacent to the first bit location, and a first logic value of the first data bit is different from a second logic value of the second data bit. The encoded code word includes a third data bit at a third bit location in the encoded code word, where a third logic value of the third data bit is the same as the first logic value.
In another specific embodiment, the value of N is programmable. In another non-limiting embodiment, the transmit unit may be configured to determine a quality level of transmission of the transmission data word.
BRIEF DESCRIPTION OF THE DRAWINGS
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The following detailed description makes reference to the accompanying drawings, which are now briefly described.
FIG. 1 illustrates an embodiment of a computing system.
FIG. 2 illustrates another embodiment of a computing system.
FIG. 3 illustrates a block diagram of a serial data stream.
FIG. 4 illustrates an embodiment of an encoding unit.
FIG. 5 illustrates an embodiment of a decoding unit.
FIG. 6 illustrates a chart depicting an example mapping between codes words in an L-code space to code words in an S-code space.
FIG. 7 illustrates a flow diagram depicting an embodiment of a method of operating encoding and transmitting serial data in a computing system.
FIG. 8 illustrates a flow diagram depicting an embodiment of a method for receiving a serial data stream.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the disclosure to the particular form illustrated, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include,” “including,” and “includes” mean including, but not limited to.
Various units, circuits, or other components may be described as “configured to” perform a task or tasks. In such contexts, “configured to” is a broad recitation of structure generally meaning “having circuitry that” performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, paragraph (f) interpretation for that unit/circuit/component. More generally, the recitation of any element is expressly intended not to invoke 35 U.S.C. §112, paragraph (f) interpretation for that element unless the language “means for” or “step for” is specifically recited.
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A computing system may include one or more integrated circuits, such as, e.g., a central processing unit (CPU) and memories. Each one of the integrated circuits of the computing system may communicate through either a serial or parallel interface. In a parallel interface, multiple data bits are communicated simultaneously, while in a serial interface, data is communicated as a series of sequential single data bits. The data may be communicated in accordance to one of various communication protocols.
In the case of a serial interface, transitions from one data state to another in the transmitted stream are employed to recover timing information necessary to sample the signal stream. The process of recovering timing information is commonly referred to as Clock Data Recovery (CDR) and, in many cases, relies on naturally occurring randomness within the transmitted data to recover the timing information.
In some cases, however, the signal stream may include few transitions as a same data value is transmitted for a period of time. When this occurs, CDR may be difficult, which may result in a loss of data by the receiving unit, resulting in a failure of the communication link. Some computer systems employ an encoding scheme to increase the number of transitions in the signal stream, although such schemes may require an increase in the data overhead, i.e., additional data bits may be transmitted. The embodiments in the drawings and described herein may provide techniques for encoding a serial data stream with low overhead and providing sufficient transitions for CDR.
A block diagram of a computing system is illustrated in FIG. 1. In the illustrated embodiment, the computing system 100 includes a CPU 101 coupled to Random Access Memory (RAM) 102, and display adapter 104. CPU 101 is additionally coupled to input/output (I/O) adapter 105, user interface adapter 106, and communications adapter 107. In various embodiments, computing system 100 may be configured as a desktop system, a laptop system, or in any suitable form factor.
RAM 102 may include any suitable type of memory, such as Fully Buffered Dual Inline Memory Module (FB-DIMM), Double Data Rate or Double Data Rate 2 Synchronous Dynamic Random Access Memory (DDR/DDR2 SDRAM), or Rambus® DRAM (RDRAM®), for example. It is noted that although one RAM is shown, in various embodiments, any suitable number of RAMs may be employed.
CPU 101 may implement any suitable instruction set architecture (ISA), such as, e.g., the SPARC™, PowerPC™, or x86 ISAs, or combination thereof. In some embodiments, CPU 101 may include one or more processor cores configured to implement one of the aforementioned ISAs. CPU 101 may also include one or more cache memories which may be configured to store instructions and/or data during operation.
CPU 101 may include one or more bus transceiver units 109 that allow CPU 101 to connect to bus 108. In some embodiments, bus 108 may be a high-speed serial interface that may conform to an industry standard specification, such as, e.g., PCI Express™, or MIPI Physical Layer. In some embodiments, transceiver unit 109 may include clock and data recover circuits in addition to encoder and decoder circuits.
I/O adapter 105 may be configured to coordinate data transfer between CPU 101 and one or more peripheral devices. Such peripheral devices may include, without limitation, storage devices (e.g., magnetic or optical media-based storage devices including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral devices. In some embodiments, I/O adapter 105 may be configured to implement a version of Universal Serial Bus (USB) protocol or IEEE 1394 (Firewire®) protocol.