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Charge measurement

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20140240022 patent thumbnailZoom

Charge measurement


An apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output. The apparatus also comprises a controllable current source coupled to the first input of the comparator and configured for supplying or drawing current. The apparatus also comprises a digital logic circuit that is configured for controlling an amount of current supplied or drawn by the controllable current source. The apparatus is configured for measuring a charge associated with an external source that is coupled to the first input of the comparator.
Related Terms: Digital Logic

Browse recent Atmel Corporation patents - San Jose, CA, US
USPTO Applicaton #: #20140240022 - Class: 327336 (USPTO) -


Inventors: Fredrik Larsen

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The Patent Description & Claims data below is from USPTO Patent Application 20140240022, Charge measurement.

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CLAIM OF PRIORITY

This application is a continuation of and claims priority under 35 USC §119(e) to U.S. patent application Ser. No. 13/667,171, filed on Nov. 2, 2012, the entire contents of which are hereby incorporated by reference.

TECHNICAL FIELD

This disclosure relates generally to charge measurement using an integrator.

BACKGROUND

An integrator is a device that generally outputs a signal proportional to the time integral of the input. The input and output of the integrator may be either a voltage or a current signal.

SUMMARY

In one general aspect, an apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output of the comparator. The apparatus also comprises a controllable current source that includes an output coupled to the first input of the comparator and configured for supplying or drawing current.

In addition, the apparatus comprises a digital logic circuit that includes an input coupled to the output of the comparator and an output coupled to an input of the controllable current source. The digital logic circuit is configured for controlling an amount of current supplied or drawn by the controllable current source. The apparatus is configured for regulating a voltage associated with an external source that is coupled to the first input of the comparator and keeps track of the charge used to regulate the voltage. In some implementations, voltage regulation is performed by starting at a reference voltage, introducing a charge, and then regulating back to the reference voltage. In this manner, the charge that is added can be measured.

Particular implementations of the apparatus may include one or more of the following features. The digital logic circuit may be configured to use successive approximation to control the amount of current supplied or drawn by the controllable current source such that a voltage at the first input of the comparator due to the charge associated with an external source approaches the reference voltage. By supplying or drawing the current, an amount of charge proportional to the amount of current supplied or drawn, and the time for which the current is supplied or drawn, may be added or removed, respectively.

The apparatus may be configured for providing a digital output proportional to the measured charge associated with the external source. The digital output may be provided without using an analog to digital converter (ADC) by the apparatus.

The apparatus may be configured for integrating a current associated with the external source. The apparatus may be configured for measuring a voltage associated with the external source. The apparatus may be configured for measuring a capacitance associated with the external source.

The controllable current source may include a digital to analog converter circuit (DAC) that is configured for providing a current at the output of the controllable current source. The digital logic circuit may be configured for regulating a voltage associated with the external source at the first input of the comparator by controlling the controllable current source such that an amount of the current provided by the controllable current source is controlled.

The digital logic circuit may comprise a digital filter that includes an input coupled to the output of the comparator. The digital filter may be configured for producing at an output of the digital filter a filtered version of the information at the output of the comparator.

The digital logic circuit also may comprise a delay circuit that includes an input coupled to the output of the digital filter. The delay circuit may be configured for providing at an output of the delay circuit a delayed version of the filtered information produced by the digital filter.

The delay circuit may be configured to delay the filtered information produced by the digital filter by a time step of a clock signal provided to the digital logic circuit such that the output of the delay circuit follows the output of the digital filter delayed by the time step.

The digital logic circuit also may comprise an exclusive-or (XOR) circuit that includes a first input coupled to the output of the digital filter and a second input coupled to the output of the delay circuit. The XOR circuit may be configured for providing an UPDATE signal at an output of the XOR circuit.

The UPDATE signal may be based on a difference between the output of the digital filter and the output of the delay circuit. The UPDATE signal may indicate when a voltage at the first input of the comparator that is produced due to the external source and the current supplied or drawn by the controllable current source crosses the reference voltage.

The digital logic circuit also may comprise a control setting circuit that includes a first input coupled to the output of the XOR circuit for receiving the UPDATE signal, a second input for receiving a RESET signal and a third input coupled to the output of the digital filter. In addition, the control setting circuit may include an output coupled to the input of the controllable current source. The control setting circuit may be configured for controlling an active current configuration of the controllable current source.

The control setting circuit may be configured for providing control information for controlling the active current configuration of the controllable current source based on the UPDATE signal and the filtered information produced by the digital filter. The control information may be configured to drive the controllable current source to source current or sink current based on a sign of the filtered information produced by the digital filter.

The digital logic circuit also may comprise a digital accumulator that includes a first input coupled to the output of the control setting circuit for measuring an amount of current supplied or drawn by the controllable current source, a second input for receiving the RESET signal and an output for providing a RESULT signal that is proportional to the charge associated with the external source.

The digital accumulator may be configured for accumulating a value proportional to the amount of charge supplied to or drawn from the external source based on current supplied or drawn by the controllable current source and a time for which the current is supplied or drawn, an amount of the current being based on successive control information provided at the output of the control setting circuit for controlling the active current configuration of the controllable current source during a measurement cycle.

The digital logic circuit also may comprise a compensation circuit that includes an input coupled to the output of the control setting circuit and an output coupled to the input of the digital accumulator. The compensation circuit may be configured for coupling the control setting circuit and the digital accumulator, and compensating the amount of current supplied or drawn by the controllable current source based on a digital lookup table. The compensated amount of current may be provided to the digital accumulator at the output of the compensation circuit.

A dynamic range or resolution of the apparatus may be controlled by digitally controlling the time step of the clock signal. The resolution of the apparatus is based on the minimum possible charge that can be sinked or sourced. Since charge is a function of current and time, resolution is a function of the minimum current and minimum time step of the clock signal (that is, the maximum clock frequency). The dynamic range is based on the integration time and may be increased by increasing the integration time. In this context, the integration time is the time for which the current is supplied or drawn by the by the controllable current source.

The RESET signal may be configured for resetting the control setting circuit to a base setting when a new measurement is to be made. The base setting of the control setting circuit may be configured to control the controllable current source such that a maximum amount of current is supplied or drawn by the controllable current source.

The apparatus also may comprise a controllable voltage source coupled to the second input of the comparator and configured for providing a reference voltage. Alternatively, the apparatus may comprise a static voltage source.

In another general aspect, an external source is coupled to a first input of a comparator included in an integrator circuit for measuring a voltage proportional to a first amount of charge associated with the external source. A supplementary charge is added to the external source using a controllable current source included in the integrator circuit that is coupled to the external source. The supplementary charge is due to a current provided by the controllable current source. A difference between a voltage at the first input of the comparator due to the external source and a reference voltage coupled to the second input of the comparator is measured using the comparator. An amount of the current provided by the controllable current source is adjusted based on measuring the difference. The amount of current is adjusted in successive steps of a clock signal such that the voltage at the first input of the comparator approaches the reference voltage. It is determined whether the voltage at the first input of the comparator has crossed the reference voltage based on a sign of the measured difference at an output of the comparator. Responsive to determining that the voltage at the first input of the comparator has crossed the reference voltage, the amount of current provided by the controllable current source is adjusted by reversing a direction of the current. Adjusting the amount of current also includes adjusting the strength of the current.

A value proportional to an amount of charge is accumulated using a digital accumulator included in the integrator circuit. The amount of charge is proportional to the current provided by the controllable current source and an amount of time for which current is provided by the controllable current source. It is determined whether a minimum setting for the current provided by the controllable current source is reached. Based on determining that the minimum setting for the current provided by the controllable current source is reached, the accumulated value proportional to the amount of charge is provided at the output of the digital accumulator as an indication of the first amount of charge associated with the external source.

Particular implementations may include one or more of the following features. Adjusting the amount of the current provided by the controllable current source may comprise providing a control signal to the controllable current source using a control setting circuit included in the integrator circuit. The control signal may be configured for controlling the controllable current source such that the amount of current provided by the controllable current source is adjusted. The control setting circuit may generate the control signal based on an indication of the measured difference at the output of the comparator and the sign of the measured difference at the output of the comparator.

The control setting circuit may be configured to use successive approximation to adjust the amount of current provided by the controllable current source such that the voltage at the first input of the comparator due to the external source may approach the reference voltage. A dynamic range or resolution of the measurement associated with the amount of current provided by the controllable current source may be controlled by digitally controlling the time step of the clock signal.

The details of one or more disclosed implementations are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual block diagram of an exemplary circuit that may be used for successive approximation integration.

FIG. 2 is a conceptual block diagram of an exemplary circuit that may be used for implementing successive approximation integration.

FIG. 3 is a graph illustrating an exemplary measurement sequence using a successive approximation integrator.

FIGS. 4A-4C are conceptual block diagrams of exemplary measurement circuits in which a successive approximation integrator may be applied.

FIG. 5 is a flow chart illustrating an exemplary process for charge measurement using a successive approximation integrator.

DETAILED DESCRIPTION

Typically, a traditional current integrator may consist of an operational amplifier (commonly known in abbreviated form as “op-amp”) configured with a capacitive negative feedback. The two inputs of the op-amp may be considered as the two inputs of the integrator. The capacitance in the negative feedback may accumulate a charge that is proportional to the current that is sinked or sourced from the input of the integrator. In this context, “sinking” a current refers to drawing a current from the input of the integrator, while “sourcing” a current refers to providing a current to the input of the integrator.

When current is supplied to a capacitor, the capacitor stores the associated energy as charge. The amount of charge is proportional to the current supplied, and the time period for which the current is supplied. Similarly, the charge stored in a capacitor may be reduced by drawing a current from the capacitor. The relationship between the current supplied to or drawn from a capacitor, the charge associated with the capacitor, and the time period for which the current flows, is given by equation (1):

Q=I*t  (1)

In equation (1), Q is the total amount of charge that is added to or removed from a capacitor, I is the current that is supplied to or from the capacitor and t is the amount of time for which the current is supplied to or from the capacitor.

Referring back to the current integrator described previously, the charge accumulated by the capacitance in the negative feedback may create a voltage at the output of the integrator that is proportional to the charge accumulated and the size of the capacitance, which is illustrated by equation (2):

VINT=(1/CINT)*I*t  (2)

In equation (2), VINT is the voltage created at the output of the integrator, CINT is the capacitance across the op-amp connected in the negative feedback, I is the current provided to the integrator and t is the time for which the current is provided.

Integrators have several applications. Integrators may be used to integrate current or voltage. In addition, integrators may be used to measure capacitive sensors. For example, capacitive touch screen displays may be implemented using integrators configured for measuring capacitance.

As an example of another application, the capacitance of a circuit that is connected to an input of an integrator, which is referred to as self-capacitance, may be measured using the integrator. Self-capacitance of an input of the integrator may be measured by measuring the charge that is used to move the input voltage by a known amount dV (that is, change in voltage). This can be accomplished by changing the reference voltage REF at the second input of the integrator between known voltages, which causes the integrator to “regulate” the other input between the same voltages while also keeping track of the charges required to do so.

An integrator also may be used for measuring mutual capacitance. Generally, the goal of mutual capacitance measuring is it to measure coupling capacitance (referred to as Cm) between two wires. This may be measured by connecting one wire to the first input of the integrator and the other wire (typically referred to as X line) to a controllable voltage source. After the integrator is stable, the X line is pulsed, and a charge proportional to Cm and the change in X line voltage is transferred to CINT. The change in the voltage at the first input of the integrator due to charge being added is momentary and therefore does not affect the calculation.

In some implementations involving digital applications, the analog output from the integrator may need to be converted in to a digital result using, for example, an analog-to-digital converter (ADC) that is coupled to the integrator forming one unit. The accuracy and resolution of the digital result may depend on the accuracy and resolution of the ADC. In such implementations, the ADC may be a primary factor in determining the cost associated with the integration.

It may be useful to implement an integrator that performs efficient and accurate digital measurement of charge adjustments required to make the voltage of a circuit connected to the first input of the integrator same as the REF voltage that is connected to the second input of the integrator. Controlling the measurement digitally allows compensation and digital filtering to be used to lower the analog requirements, thereby reducing the cost. In addition, digital measurement removes the need for a dedicated ADC, which may lead to significant cost reduction and performance improvement.

In some implementations, such an integrator may be realized by digital circuits that use successive approximation integration for measuring a voltage at one input of the integrator, compared to a REF voltage at the other input of the integrator. Such an integrator may be known as a successive approximation integrator, also referred to by the acronym SAINT.

FIG. 1 is a conceptual block diagram of an exemplary circuit 100 that may be used for successive approximation integration. The circuit 100 includes a successive approximation integrator (SAINT) 110. Connected to an input of the SAINT 110 is a capacitive sensor 140, while a controllable voltage source 114 is connected to another input of the SAINT 110. The SAINT 110 includes a comparator 112, a controllable current source 116 and a digital logic circuit 120 that is configured for controlling the successive approximation mechanism.

The comparator 112, which has a positive input and a negative input, is configured for providing an output based on comparing two voltages that are connected to the two inputs. The output of the comparator may be a binary output. For example, the output of the comparator may be one of two predetermined voltage levels. One voltage level may indicate a ‘1’ while the other voltage level may indicate a ‘0’. In one implementation, the comparator may output a ‘1’ if the voltage at the positive input is higher than the voltage at the negative input, and may output a ‘0’ otherwise. However, in other implementations, the output of the comparator may be the reverse of the above.

In some implementations, the controllable voltage source 114 may be included in the SAINT 110, while in other implementations the controllable voltage source 114 may be external to the SAINT 110. The controllable voltage source 114 is connected to an input of the comparator 112. The controllable voltage source 114 is configured for providing a reference voltage REF at the input of the comparator to which the voltage source is connected. In some implementations, the controllable voltage source 114 is connected to the negative input of the comparator 112. However, in other implementations, the controllable voltage source 114 may be connected to the positive input of the comparator 112.

In some implementations, instead of a controllable voltage source 114, a static reference voltage may be connected to an input of the comparator 112. In such implementations, the external circuit or sensor that is connected to the other input of the comparator 112 may be charged or discharged to a fixed voltage prior to integrating the input.

The controllable current source 116 may be a digital-to-analog converter with a current output (also known as IDAC). The controllable current source or IDAC 116 has an input that is connected to an output of the digital logic circuit 120, while an output of the IDAC 116 is coupled to the SENSOR_LINE at the input of the comparator 112 to which the SENSOR_LINE is connected, for example, the positive input of the comparator 112.

The IDAC 116 is configured for sinking or sourcing a current to/from the capacitive sensor 140. When the voltage at the positive input of the comparator 112 due to the capacitive sensor 140 and the charge added or stored in the sensor 140, is higher than the reference voltage REF at the negative input of the comparator 112 due to the controllable voltage source 114, the IDAC 116 sinks or draws current away from the capacitive sensor 140. This has the effect of reducing the voltage at the positive input of the comparator 112 due to the capacitive sensor 140, such that the voltage at the positive input of the comparator 112 approaches the REF voltage. Conversely, when the voltage at the positive input of the comparator 112 due to the capacitive sensor 140 and the charge added or stored in the sensor 140, is lower than the REF voltage, the IDAC 116 sources or provides current to the capacitive sensor 140, which has the effect of increasing the voltage at the positive input of the comparator 112, such that the voltage at the positive input of the comparator 112 approaches the REF voltage.

The digital logic circuit 120 is configured for controlling the current output of the IDAC 116 such that the voltage at the positive input of the comparator 112 is regulated. The voltage at the positive input of the comparator 112 (which is same as the voltage on the SENSOR LINE that connects the capacitive sensor 140 to the positive input of the comparator 112) is regulated to the voltage on the negative input of the comparator 112. This voltage is based on the voltage due to the capacitive sensor 140, parasitic capacitance on the SENSOR LINE, and charges present on the capacitor plates and the electrical wires.

In one implementation, the digital logic circuit 120 regulates the voltage on the SENSOR LINE such that the voltage at the positive input of the comparator 112 is same as the REF voltage. The digital logic circuit 120 performs this voltage regulation by sinking or sourcing progressively smaller amounts of current to the capacitive sensor 140 using the IDAC 116.

The digital logic circuit 120 may compute the total amount of charge that is added to, or removed from, the capacitive sensor 140 due to the current from the IDAC 116 that is supplied for regulating the voltage on the SENSOR LINE. The total amount of charge may be computed by determining the amount of time for which a known amount of current is supplied to or from the capacitive sensor 140, using equation (1).

The capacitive sensor 140 represents an external circuit that provides a capacitive load or coupling to ground (or some other common reference) at one input of the integrator to which it is connected. The capacitive sensor is also referred to interchangeably as a sensor or a capacitor.

Therefore, as described in the preceding section, the circuit 100 performs voltage regulation by sinking or sourcing progressively smaller amounts of current in successive iterations such that the SENSOR LINE voltage approximates the REF voltage. By performing voltage regulation in this manner, the circuit 100 may be used for measuring an amount of charge associated with the voltage regulation. The circuit 100 is hence referred to as a successive approximation integrator or SAINT. The implementation of a successive approximation integrator is described in greater detail in the following sections.

FIG. 2 is a conceptual block diagram of an exemplary circuit 200 that may be used for implementing successive approximation integration. For example, the circuit 200 may be used for the successive approximation integration described with reference to circuit 100.

The circuit 200 includes a successive approximation integrator (SAINT) 210 and an external capacitor 240 that is connected to an input of the SAINT 210. Connected to another input of the SAINT 210 is a controllable voltage source 214. The SAINT 210 includes a comparator 212, a controllable current source 216 and a digital logic circuit 220.

The external capacitor 240 represents an external circuit that is being measured using the SAINT 210. The external capacitor 240 is similar to the capacitive sensor 140. The external capacitor 240 with a stored charge provides a voltage at the input of the SAINT 210 to which the external capacitor is connected. The external capacitor 240 is also referred to interchangeably as a capacitive sensor 240, or as sensor 240.

The digital logic circuit 220 may be an exemplary implementation of the digital logic circuit 120. The digital logic circuit 220 includes a filter 222, which is connected to a delay circuit 224 and an XOR logic circuit 226. In addition, the digital logic circuit 220 includes a control setting circuit 228, a compensation circuit 230 and an accumulator circuit 232.

The comparator 212 is similar to the comparator 112. The comparator 212 has a positive input and a negative input and it is configured for providing an output based on comparing two voltages that are connected to the two inputs. The external capacitor 214 is connected to the SAINT 210 at the positive input of the comparator 212. The controllable voltage source 214 is connected to the negative input of the comparator 212.

The controllable voltage source 214, which is similar to the controllable voltage source 114, is configured for providing a reference voltage REF. While FIG. 2 shows the controllable voltage source 214 connected to the negative input of the comparator 212, in some implementations, the controllable voltage source 214 may be connected to the positive input of the comparator 212.

The controllable current source 216, which may be similar to the controllable current source 116, includes an IDAC. The controllable current source or IDAC 216 has an input that is connected to the digital logic circuit 220, while the output of the IDAC 216 is coupled to the external capacitor 240 at the positive input of the comparator 212. The IDAC 216 is configured for sinking or sourcing a current from the capacitor 240 so that the SENSOR LINE voltage at the positive input of the comparator 212 due to the capacitor 240 is same as the reference voltage REF at the negative input of the comparator 212.

The filter 222 in the digital logic circuit 220 is connected to the output of the comparator 212. The filter 222 is a digital filter that is configured for providing at its output a filtered version of the comparator 212 output. In some implementations, the filter 222 may be a time hysteresis based filter. However, in other implementations, the filter 222 may be some other type of digital filter.

The delay circuit 224 is coupled to the output of the filter 222. The delay circuit 224 is configured for providing, at its output, a time-delayed version of its input. The amount of delay may be pre-configured at the time of implementation of the digital logic circuit 220. Therefore, the delay circuit 224 provides at its output a delayed version of the digital signal provided by the filter 222.

The XOR logic circuit 226 has two inputs—one input is coupled to the output of the filter 222, while the second input is coupled to the output of the delay circuit 224. The XOR logic circuit 226 is configured to compare the digital signal provided by the filter 222 with the delayed version of the digital signal provided by the delay circuit 224.

When the SENSOR LINE voltage crosses the REF voltage, that is, either exceeds or goes below the REF voltage, due to the addition or removal of current by the IDAC 216, the comparator 212 output changes and hence the digital signal provided by the filter 222 changes. Therefore, the signal provided to the second input of the XOR logic circuit 226 by the delay circuit 224 becomes different from the digital signal provided by the filter 222 at the first input of the XOR logic circuit. Consequently, the XOR logic circuit 226 generates a pulse at its output, since the two input signals differ from one another. The pulse at the output of the XOR logic circuit 226, which is denoted by the UPDATE signal in FIG. 2, indicates that the amount of charge that has been added to or removed from the external capacitor 240 by the IDAC 216 current is more than the amount needed to make the SENSOR LINE voltage same as the REF voltage.

The control setting circuit 228 receives the UPDATE signal through an input that is coupled to the output of the XOR circuit 226. In addition, the control setting circuit 228 has an input connected to the output of the digital filter 222 for receiving the SIGN signal from the digital filter 222. The control setting circuit 228 also receives a RESET signal based on a START signal that is input to the integrator 210.

The control setting circuit 228 is configured for controlling the active current configuration of the IDAC 216. Upon receiving the UPDATE signal, control setting circuit 228 controls the IDAC 216 such that the amount of current provided to, or removed from, the capacitor 240 is reduced by a pre-determined factor. In addition, the sign of the current is changed, that is, the direction of the current is reversed. Therefore, if the IDAC 216 was previously providing current to the capacitor 240, the control signal from the control setting circuit 228 configures the IDAC 216 such that the IDAC 216 now draws current from the capacitor 240, and vice versa. By reducing the amount of current provided to the capacitor 240 and changing the direction of the current, the integrator 210 is able to find successively more accurate results such that the SENSOR LINE voltage approaches the REF voltage with greater accuracy.

The compensation circuit 230 is coupled to the output of the control setting circuit 228. The compensation circuit 230 reads the control signal from the control setting circuit 228 to the IDAC 216 such that the compensation circuit 230 is able to determine the settings for the IDAC 216, that is, amount of current that is to be supplied to or from the capacitor 240 by the IDAC 216. In addition, the compensation circuit 230 determines the time period for which the current is to be supplied to or from the capacitor 240. Based on determining the current and the time period, the compensation circuit 230 may compute the amount of charge that is sinked or sourced from the capacitor 240 due to the control signal from the control setting circuit 228.

In some implementations, upon determining the IDAC 216 setting, the compensation circuit 230 may perform compensation on the IDAC settings using a digital lookup table. The compensation circuit 230 provides information on the amount of charge sinked or sourced from the capacitor 240, either compensated or otherwise, to the accumulator circuit 232.

The accumulator circuit 232 is configured for providing at its output a result signal, denoted by RESULT in FIG. 2, which indicates a digital value proportional to the amount of charge sinked or sourced from the external capacitor 240 such that the SENSOR LINE voltage is same as the REF voltage. During the measurement process, the accumulator circuit 232 stores the amount of charge internally based on the information received from the compensation circuit 230 in successive iterations of the measurement sequence.

In some implementations, the compensation circuit 230 may not be present. In such implementations, the accumulator circuit 232 is directly coupled to the output of the control setting circuit 228 and reads the control signal sent from the control setting circuit 228 to the IDAC 216 in each iteration. From the control signal, the accumulator circuit 232 is able to determine the amount of charge that is sinked or sourced from the capacitor 240 in the respective iteration, in a manner similar to that described previously with reference to the compensation circuit 230.

Using the digital circuit 220 as described in the preceding section, the integrator 210 measures a delta charge, that is, a change in the charge at the external capacitor 240 that is added by some external event. The delta charge introduces a change in voltage at the SENSOR LINE, as described by the relation dV=dQ/C, where dV is the change in input voltage caused by the change in charge dQ and C is the capacitance of the input line (which is assumed to be constant). Therefore, to regulate the SENSOR LINE voltage back to the voltage it had (that is, the REF voltage) before the unknown charge was introduced, the integrator 210 removes the same amount of charge as was introduced by the external event. While regulating the voltage back to the REF voltage, the integrator digitally keeps track of the charges used to do so. The integrator 210 regulates the SENSOR LINE voltage to the REF voltage by successively adding or removing, or both, exponentially smaller and smaller charges using the IDAC 216 current, until the SENSOR LINE voltage is equal to the REF voltage. As indicated by equation (1), charge may be added or removed by controlling the amount of current and the time for which the current is added or removed.

The accumulator circuit 232 receives, from the compensation circuit 230, a digital value proportional to the charge added or removed from the capacitor 240 in each iteration of the measurement sequence, or alternatively, determines the charge added or removed by reading the control signal from the control setting circuit 228, and updates the charge stored based on the charge added or removed in the present iteration of the measurement sequence. When the SENSOR LINE voltage is same as the REF voltage, the value of the RESULT signal at the output of the accumulator circuit 232 is proportional to the charge that is used to make the voltage on the positive input (SENSOR_LINE) same as the voltage on negative input.

The RESULT signal is most accurate when the minimum setting of the IDAC 216 and the minimum time step, which is described in the following sections, are reached and a new update is signaled (for example, by a change in the sign of the comparator 212 output). For further iterations of the measurement sequence after this point, the integrator 210 continues to oscillate between plus and minus the minimum setting of the IDAC 216, until a new measurement is triggered. At this stage, the charge measurement may be considered completed.

When a new charge measurement is to be conducted, the START signal may be used to trigger a reset of the control setting circuit 228 and the accumulator circuit 232. The START signal provides a RESET trigger to the control setting circuit 228, which resets the control setting circuit 228 to plus or minus the maximum setting for the IDAC 216, depending on the sign of the active output from the filter circuit 222. The sign of the active output of the filter circuit 222 is input to the control setting circuit 228 as denoted by the SIGN signal. In addition, the START signal provides a RESET trigger to the accumulator circuit 232, which clears the value that was previously accumulated in the accumulator circuit 232 from the previous measurement. In some implementations, there is a finite time interval between successive measurements such that a charge transfer from a previous measurement is completed so that the SIGN signal is settled correctly.

FIG. 3 is a graph 300 illustrating an exemplary measurement sequence using a successive approximation integrator. The measurement plotted in graph 300 may be implemented using the circuit 200, as described in the following section. However, the measurement plotted in graph 300 may be implemented by other circuits or system configurations.



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stats Patent Info
Application #
US 20140240022 A1
Publish Date
08/28/2014
Document #
14272648
File Date
05/08/2014
USPTO Class
327336
Other USPTO Classes
International Class
06G7/18
Drawings
6


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