FreshPatents.com Logo
stats FreshPatents Stats
1 views for this patent on FreshPatents.com
2014: 1 views
Updated: October 26 2014
newTOP 200 Companies filing patents this week


    Free Services  

  • MONITOR KEYWORDS
  • Enter keywords & we'll notify you when a new patent matches your request (weekly update).

  • ORGANIZER
  • Save & organize patents so you can view them later.

  • RSS rss
  • Create custom RSS feeds. Track keywords without receiving email.

  • ARCHIVE
  • View the last few months of your Keyword emails.

  • COMPANY DIRECTORY
  • Patents sorted by company.

Follow us on Twitter
twitter icon@FreshPatents

Charge measurement

last patentdownload pdfdownload imgimage previewnext patent


20140240022 patent thumbnailZoom

Charge measurement


An apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output. The apparatus also comprises a controllable current source coupled to the first input of the comparator and configured for supplying or drawing current. The apparatus also comprises a digital logic circuit that is configured for controlling an amount of current supplied or drawn by the controllable current source. The apparatus is configured for measuring a charge associated with an external source that is coupled to the first input of the comparator.
Related Terms: Digital Logic

Browse recent Atmel Corporation patents - San Jose, CA, US
USPTO Applicaton #: #20140240022 - Class: 327336 (USPTO) -


Inventors: Fredrik Larsen

view organizer monitor keywords


The Patent Description & Claims data below is from USPTO Patent Application 20140240022, Charge measurement.

last patentpdficondownload pdfimage previewnext patent

CLAIM OF PRIORITY

This application is a continuation of and claims priority under 35 USC §119(e) to U.S. patent application Ser. No. 13/667,171, filed on Nov. 2, 2012, the entire contents of which are hereby incorporated by reference.

TECHNICAL FIELD

This disclosure relates generally to charge measurement using an integrator.

BACKGROUND

An integrator is a device that generally outputs a signal proportional to the time integral of the input. The input and output of the integrator may be either a voltage or a current signal.

SUMMARY

In one general aspect, an apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output of the comparator. The apparatus also comprises a controllable current source that includes an output coupled to the first input of the comparator and configured for supplying or drawing current.

In addition, the apparatus comprises a digital logic circuit that includes an input coupled to the output of the comparator and an output coupled to an input of the controllable current source. The digital logic circuit is configured for controlling an amount of current supplied or drawn by the controllable current source. The apparatus is configured for regulating a voltage associated with an external source that is coupled to the first input of the comparator and keeps track of the charge used to regulate the voltage. In some implementations, voltage regulation is performed by starting at a reference voltage, introducing a charge, and then regulating back to the reference voltage. In this manner, the charge that is added can be measured.

Particular implementations of the apparatus may include one or more of the following features. The digital logic circuit may be configured to use successive approximation to control the amount of current supplied or drawn by the controllable current source such that a voltage at the first input of the comparator due to the charge associated with an external source approaches the reference voltage. By supplying or drawing the current, an amount of charge proportional to the amount of current supplied or drawn, and the time for which the current is supplied or drawn, may be added or removed, respectively.

The apparatus may be configured for providing a digital output proportional to the measured charge associated with the external source. The digital output may be provided without using an analog to digital converter (ADC) by the apparatus.

The apparatus may be configured for integrating a current associated with the external source. The apparatus may be configured for measuring a voltage associated with the external source. The apparatus may be configured for measuring a capacitance associated with the external source.

The controllable current source may include a digital to analog converter circuit (DAC) that is configured for providing a current at the output of the controllable current source. The digital logic circuit may be configured for regulating a voltage associated with the external source at the first input of the comparator by controlling the controllable current source such that an amount of the current provided by the controllable current source is controlled.

The digital logic circuit may comprise a digital filter that includes an input coupled to the output of the comparator. The digital filter may be configured for producing at an output of the digital filter a filtered version of the information at the output of the comparator.

The digital logic circuit also may comprise a delay circuit that includes an input coupled to the output of the digital filter. The delay circuit may be configured for providing at an output of the delay circuit a delayed version of the filtered information produced by the digital filter.

The delay circuit may be configured to delay the filtered information produced by the digital filter by a time step of a clock signal provided to the digital logic circuit such that the output of the delay circuit follows the output of the digital filter delayed by the time step.

The digital logic circuit also may comprise an exclusive-or (XOR) circuit that includes a first input coupled to the output of the digital filter and a second input coupled to the output of the delay circuit. The XOR circuit may be configured for providing an UPDATE signal at an output of the XOR circuit.

The UPDATE signal may be based on a difference between the output of the digital filter and the output of the delay circuit. The UPDATE signal may indicate when a voltage at the first input of the comparator that is produced due to the external source and the current supplied or drawn by the controllable current source crosses the reference voltage.

The digital logic circuit also may comprise a control setting circuit that includes a first input coupled to the output of the XOR circuit for receiving the UPDATE signal, a second input for receiving a RESET signal and a third input coupled to the output of the digital filter. In addition, the control setting circuit may include an output coupled to the input of the controllable current source. The control setting circuit may be configured for controlling an active current configuration of the controllable current source.

The control setting circuit may be configured for providing control information for controlling the active current configuration of the controllable current source based on the UPDATE signal and the filtered information produced by the digital filter. The control information may be configured to drive the controllable current source to source current or sink current based on a sign of the filtered information produced by the digital filter.

The digital logic circuit also may comprise a digital accumulator that includes a first input coupled to the output of the control setting circuit for measuring an amount of current supplied or drawn by the controllable current source, a second input for receiving the RESET signal and an output for providing a RESULT signal that is proportional to the charge associated with the external source.

The digital accumulator may be configured for accumulating a value proportional to the amount of charge supplied to or drawn from the external source based on current supplied or drawn by the controllable current source and a time for which the current is supplied or drawn, an amount of the current being based on successive control information provided at the output of the control setting circuit for controlling the active current configuration of the controllable current source during a measurement cycle.

The digital logic circuit also may comprise a compensation circuit that includes an input coupled to the output of the control setting circuit and an output coupled to the input of the digital accumulator. The compensation circuit may be configured for coupling the control setting circuit and the digital accumulator, and compensating the amount of current supplied or drawn by the controllable current source based on a digital lookup table. The compensated amount of current may be provided to the digital accumulator at the output of the compensation circuit.

A dynamic range or resolution of the apparatus may be controlled by digitally controlling the time step of the clock signal. The resolution of the apparatus is based on the minimum possible charge that can be sinked or sourced. Since charge is a function of current and time, resolution is a function of the minimum current and minimum time step of the clock signal (that is, the maximum clock frequency). The dynamic range is based on the integration time and may be increased by increasing the integration time. In this context, the integration time is the time for which the current is supplied or drawn by the by the controllable current source.

The RESET signal may be configured for resetting the control setting circuit to a base setting when a new measurement is to be made. The base setting of the control setting circuit may be configured to control the controllable current source such that a maximum amount of current is supplied or drawn by the controllable current source.

The apparatus also may comprise a controllable voltage source coupled to the second input of the comparator and configured for providing a reference voltage. Alternatively, the apparatus may comprise a static voltage source.

In another general aspect, an external source is coupled to a first input of a comparator included in an integrator circuit for measuring a voltage proportional to a first amount of charge associated with the external source. A supplementary charge is added to the external source using a controllable current source included in the integrator circuit that is coupled to the external source. The supplementary charge is due to a current provided by the controllable current source. A difference between a voltage at the first input of the comparator due to the external source and a reference voltage coupled to the second input of the comparator is measured using the comparator. An amount of the current provided by the controllable current source is adjusted based on measuring the difference. The amount of current is adjusted in successive steps of a clock signal such that the voltage at the first input of the comparator approaches the reference voltage. It is determined whether the voltage at the first input of the comparator has crossed the reference voltage based on a sign of the measured difference at an output of the comparator. Responsive to determining that the voltage at the first input of the comparator has crossed the reference voltage, the amount of current provided by the controllable current source is adjusted by reversing a direction of the current. Adjusting the amount of current also includes adjusting the strength of the current.

A value proportional to an amount of charge is accumulated using a digital accumulator included in the integrator circuit. The amount of charge is proportional to the current provided by the controllable current source and an amount of time for which current is provided by the controllable current source. It is determined whether a minimum setting for the current provided by the controllable current source is reached. Based on determining that the minimum setting for the current provided by the controllable current source is reached, the accumulated value proportional to the amount of charge is provided at the output of the digital accumulator as an indication of the first amount of charge associated with the external source.

Particular implementations may include one or more of the following features. Adjusting the amount of the current provided by the controllable current source may comprise providing a control signal to the controllable current source using a control setting circuit included in the integrator circuit. The control signal may be configured for controlling the controllable current source such that the amount of current provided by the controllable current source is adjusted. The control setting circuit may generate the control signal based on an indication of the measured difference at the output of the comparator and the sign of the measured difference at the output of the comparator.

The control setting circuit may be configured to use successive approximation to adjust the amount of current provided by the controllable current source such that the voltage at the first input of the comparator due to the external source may approach the reference voltage. A dynamic range or resolution of the measurement associated with the amount of current provided by the controllable current source may be controlled by digitally controlling the time step of the clock signal.

The details of one or more disclosed implementations are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual block diagram of an exemplary circuit that may be used for successive approximation integration.

FIG. 2 is a conceptual block diagram of an exemplary circuit that may be used for implementing successive approximation integration.

FIG. 3 is a graph illustrating an exemplary measurement sequence using a successive approximation integrator.

FIGS. 4A-4C are conceptual block diagrams of exemplary measurement circuits in which a successive approximation integrator may be applied.

FIG. 5 is a flow chart illustrating an exemplary process for charge measurement using a successive approximation integrator.

DETAILED DESCRIPTION

Typically, a traditional current integrator may consist of an operational amplifier (commonly known in abbreviated form as “op-amp”) configured with a capacitive negative feedback. The two inputs of the op-amp may be considered as the two inputs of the integrator. The capacitance in the negative feedback may accumulate a charge that is proportional to the current that is sinked or sourced from the input of the integrator. In this context, “sinking” a current refers to drawing a current from the input of the integrator, while “sourcing” a current refers to providing a current to the input of the integrator.

When current is supplied to a capacitor, the capacitor stores the associated energy as charge. The amount of charge is proportional to the current supplied, and the time period for which the current is supplied. Similarly, the charge stored in a capacitor may be reduced by drawing a current from the capacitor. The relationship between the current supplied to or drawn from a capacitor, the charge associated with the capacitor, and the time period for which the current flows, is given by equation (1):

Q=I*t  (1)

In equation (1), Q is the total amount of charge that is added to or removed from a capacitor, I is the current that is supplied to or from the capacitor and t is the amount of time for which the current is supplied to or from the capacitor.

Referring back to the current integrator described previously, the charge accumulated by the capacitance in the negative feedback may create a voltage at the output of the integrator that is proportional to the charge accumulated and the size of the capacitance, which is illustrated by equation (2):

VINT=(1/CINT)*I*t  (2)



Download full PDF for full patent description/claims.

Advertise on FreshPatents.com - Rates & Info


You can also Monitor Keywords and Search for tracking patents relating to this Charge measurement patent application.
###
monitor keywords



Keyword Monitor How KEYWORD MONITOR works... a FREE service from FreshPatents
1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored.
3. Each week you receive an email with patent applications related to your keywords.  
Start now! - Receive info on patent apps like Charge measurement or other areas of interest.
###


Previous Patent Application:
Setting switch size and transition pattern in a resonant clock distribution system
Next Patent Application:
Super delta monopulse beamformer
Industry Class:
Miscellaneous active electrical nonlinear devices, circuits, and systems
Thank you for viewing the Charge measurement patent info.
- - - Apple patents, Boeing patents, Google patents, IBM patents, Jabil patents, Coca Cola patents, Motorola patents

Results in 0.54094 seconds


Other interesting Freshpatents.com categories:
Amazon , Microsoft , IBM , Boeing Facebook

###

Data source: patent applications published in the public domain by the United States Patent and Trademark Office (USPTO). Information published here is for research/educational purposes only. FreshPatents is not affiliated with the USPTO, assignee companies, inventors, law firms or other assignees. Patent applications, documents and images may contain trademarks of the respective companies/authors. FreshPatents is not responsible for the accuracy, validity or otherwise contents of these public document patent application filings. When possible a complete PDF is provided, however, in some cases the presented document/images is an abstract or sampling of the full patent application for display purposes. FreshPatents.com Terms/Support
-g2-0.2035
     SHARE
  
           


stats Patent Info
Application #
US 20140240022 A1
Publish Date
08/28/2014
Document #
14272648
File Date
05/08/2014
USPTO Class
327336
Other USPTO Classes
International Class
06G7/18
Drawings
6


Digital Logic


Follow us on Twitter
twitter icon@FreshPatents