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Positive edge reset flip-flop with dual-port slave latch




Title: Positive edge reset flip-flop with dual-port slave latch.
Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode. ...


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USPTO Applicaton #: #20140232440
Inventors: Steven Bartling, Sudhanshu Khanna


The Patent Description & Claims data below is from USPTO Patent Application 20140232440, Positive edge reset flip-flop with dual-port slave latch.

This Application clams priority from Provisional Application No. 61/766,228, filed Feb. 19, 2013.

BACKGROUND

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Several trends presently exist in the semiconductor and electronics industry. Devices are continually being made smaller, faster and requiring less power. One reason for these trends is that more personal devices are being fabricated that are relatively small and portable, thereby relying on a battery as their primary supply. For example, cellular phones, personal computing devices, and personal sound systems are devices that are in great demand in the consumer market. It is also important that data on these devices be retained even when no power is supplied to the electronic device. Non-volatile memory circuits and non-volatile logic circuits are often used to meet these requirements.

Non-volatile logic implementation often requires updating sequential elements, such as flip-flops, from a source external to the sequential element, such as a non-volatile memory. When non-volatile logic circuits are implemented to allow the updating of sequential elements, it is desired that the implementation of the non-volatile logic circuit does not significantly slow the operation of a sequential element.

BRIEF DESCRIPTION OF THE DRAWINGS

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FIG. 1 is a block diagram of a scan-able positive edge reset flip-flop with a dual-port slave latch according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a 2-to-1 multiplexer according to an embodiment of the invention. (Prior Art)

FIG. 3 is a schematic diagram of a master latch according to an embodiment of the invention. (Prior Art)

FIG. 4 is a schematic diagram of transfer gate. (Prior Art)

FIG. 5 is a schematic diagram of a dual-port slave latch according to an embodiment of the invention.

FIG. 6 is a schematic diagram of a clocked inverter according to an embodiment of the invention. (Prior Art)

FIG. 7 is a schematic diagram of a clocked inverter according to an embodiment of the invention. (Prior Art)

FIG. 8 is a schematic diagram of a tri-state inverter according to an embodiment of the invention. (Prior Art)

FIG. 9 is a schematic diagram of a tri-state inverter according to an embodiment of the invention. (Prior Art)

FIG. 10 is a schematic diagram of a clocked inverter according to an embodiment of the invention. (Prior Art)

FIG. 11 is a schematic diagram of a tri-state inverter according to an embodiment of the invention. (Prior Art)

FIG. 12 is a block diagram of a positive edge reset flip-flop with a dual-port slave latch according to an embodiment of the invention.

FIG. 13 is a timing diagram showing data bit D1, MXO, clock signal CKT, MLO, QN and the output of the flip-flop Q according to an embodiment of the invention.

FIG. 14 is a timing diagram showing scan data bit SD, MXO, clock signal CKT, MLO, QN and the output of the flip-flop Q according to an embodiment of the invention.

FIG. 15 is a timing diagram showing signals D2, SS, SX, QN, and Q according to an embodiment of the invention.

FIG. 16 is a timing diagram showing signals RET, D2, SS, SX, QN, and Q according to an embodiment of the invention.

FIG. 17 is a schematic diagram of an internal clock generating circuit according to an embodiment of the invention.

DETAILED DESCRIPTION

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In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The multiplexer is configured to receive a first data bit D1, a scan data bit SD, a scan enable control signal SE and a binary logical compliment signal SEN of the scan enable control signal SE. The scan enable control signals SE and SEN determine when the data output MXO of the multiplexer is the compliment of data bit D1 or scan data bit SD. The master latch is configured to receive the data output MXO from the multiplexer, a clock signal CKT, a binary logical compliment signal CLKZ of the clock signal CKT, a retain control signal RET, the binary logical compliment signal RETN of the retain control signal RET, a reset signal RE and the binary logical compliment REN of the reset signal RE. The signals CKT, CLKZ, RET RETN, RE and REN determine when the binary logical value of the data output MXO from the multiplexer is presented on the output ML0 of the latch and when the ML0 of the master latch is latched in the master latch or when MLO is tri-stated or is kept high.

A transfer gate transfers data from the output MLO of the master latch to the slave latch when the clock signal CKT transitions from a low logical value to a logical high value. The slave latch is configured to receive the output of the transfer gate, a second data bit D2, the clock signal CKT, the binary logical compliment signal CLKZ of the clock signal CKT, the retain control signal RET, the binary logical compliment signal RETN of the retain control signal RET, a slave control signal SS and the binary logical compliment signal SSN of the slave control signal SS. The signals CKT, CLKZ, RET, RETN, SS and SSN determine whether the binary logical value of the output of transfer gate or the second data bit (D2) is latched in the slave latch.

Non-volatile logic implementations often require updating sequential elements (e.g. flip-flops) from an external source (e.g. non-volatile memory). In an embodiment of the invention, the slave latch includes a second data input (port). The second data input is used to insert data from an external source. A tri-state inverter is added to the slave latch to accommodate the second data input. This will be explained in more detail later in the specification. When external data needs to be inserted into the slave latch, the tri-state inverter is enabled. During this time, the latch feedback is disabled by causing a forward inverter to be tri-stated with the opposite control signal as the former tri-state inverter.

The added circuitry used to add the second input to the slave latch are not part of the critical timing path of the flip-flop. As a result, change to the regular performance of the flip-flop is negligible.

FIG. 1 is a block diagram of a scan-able positive edge reset flip-flop 100 with a dual-port slave latch 108 according to an embodiment of the invention. In a functional (i.e. normal) mode of operation, the scan enable signal SE is driven to a logical low level and the binary compliment signal SEN of SE is held at a logical high level. Because the flip-flop 100 is being operated in the functional mode, the retention mode signal RET is held at a logical low level, the binary compliment signal RETN of signal RET is held at a logical high level, the slave control signal SS is held at a logical low level, the binary compliment signal SSN of the slave control signal SS is held a logical high level and RE is held at a logical low level and REN is high. Power is needed for functional mode operation so power supply VDD1 and power supply VDD2 are applied to the flip-flop 100.

FIG. 13 is a timing diagram showing data bit D1, clock signal CKT and the output of the flip-flop Q during the functional mode of operation. Because the scan signal SE is low, the binary logical compliment of D1 is passed to the output MXO of the multiplexer. FIG. 2 illustrates an embodiment of a 2-to-1 multiplexer 102. The signal output MXO is then presented to the input IN of the master latch 104. FIG. 3 is a schematic diagram of a master latch 104 according to an embodiment of the invention. The master latch 104 includes a first clocked inverter 302 (see FIG. 6 for an embodiment of the first clocked inverter 302), a second clocked inverter 304 (see FIG. 7 for an embodiment of the second clocked inverter 304) and a tri-state inverter 306 (see FIG. 8 for an embodiment of the tri-state inverter 306) with tri-state controls RET and RETN. The clock signals CKT and CLKZ are generated from external clock CLK and RE (see FIG. 17).

When the clock signal CKT transitions from a high to a low logical level, the logical compliment of the data on the input IN of the master latch 104 is presented on node 308 of the master latch 104. Because the flop-flop 100 is operating in the functional mode, the tri-state inverter 306 is active and drives the output MLO of the master latch 104 to the same logical value as the input MXO of the master latch 104. When the clock signal CKT transitions from the low logical level to a high logical level (i.e. positive edge of CKT), the logical level on node 308 is latched and the logical level on the output MLO of the master latch 104 is transferred by the transfer gate 106 to QN. Inverter 110 passes the complement of the output MLO of the master latch to the output Q. In this embodiment of the invention, the overall signal path from the input D1 of the multiplexor 102 to the Q output of inverter 110 in the slave latch 108 is non-inverting. However, in other embodiments, the overall signal path can be inverting.




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stats Patent Info
Application #
US 20140232440 A1
Publish Date
08/21/2014
Document #
File Date
12/31/1969
USPTO Class
Other USPTO Classes
International Class
/
Drawings
0


Lexer Multiplex

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20140821|20140232440|positive edge reset flip-flop with dual-port slave latch|In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and |Texas-Instruments-Incorporated
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