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Mim capacitor in finfet structure




Title: Mim capacitor in finfet structure.
Abstract: A method of forming a FinFET structure having a metal-insulator-metal capacitor. Silicon fins are formed on a semiconductor substrate followed by formation of the metal-insulator-metal capacitor on the silicon fins by depositing sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride. A polysilicon layer is deposited over the metal-insulator-metal capacitor followed by etching back the polysilicon layer and the metal-insulator-metal capacitor layers from ends of the silicon fins so that the first and second ends of the silicon fins protrude from the polysilicon layer. A spacer may be formed on surfaces facing the ends of the silicon fins followed by the formation of epitaxial silicon over the ends of the silicon fins. Also disclosed is a FinFET structure having a metal-insulator-metal capacitor. ...


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USPTO Applicaton #: #20140231890
Inventors: Veeraraghavan S. Basker, Effendi Leobandung, Tenko Yamashita, Chun-chen Yeh


The Patent Description & Claims data below is from USPTO Patent Application 20140231890, Mim capacitor in finfet structure.

BACKGROUND

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The present invention relates to FinFET structures and, more particularly, relates to a metal-insulator-metal capacitor fabrication process in a FinFET structure.

Semiconductor circuits typically include both active semiconductor devices, such as but not limited to transistors and diodes, as well as passive devices, such as but not limited to resistors and capacitors. As semiconductor technology has advanced over several decades, both the active semiconductor devices and the passive devices have conventionally been scaled to increasingly smaller dimensions to reduce costs.

Capacitors are one of the fundamental components in today's electronic devices and operate by storing a charge. For example, capacitors are often used in dynamic random access memory (DRAM) and other similar devices.

FinFET devices and FinFET structures are nonplanar devices and structures typically built on a semiconductor on insulator (SOI) substrate. The FinFET devices may comprise a vertical semiconductor fin, rather than a planar semiconductor surface, having a single or double gate wrapped around the fin. In an effort to provide for continued scaling of semiconductor structures to continuously smaller dimensions while maintaining or enhancing semiconductor device performance, the design and fabrication of semiconductor fin devices and semiconductor fin structures has evolved within the semiconductor fabrication art.

BRIEF

SUMMARY

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The various advantages and purposes of the exemplary embodiments as described above and hereafter are achieved by providing, according to a first aspect of the exemplary embodiments, a method of forming a FinFET structure which includes forming silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; depositing sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride on the sides and horizontal surface of the silicon fins; depositing a polysilicon layer over the second layer of titanium nitride on the silicon fins and over the semiconductor substrate; selectively etching the polysilicon layer and the sequential layers of first layer of titanium nitride, dielectric layer and second layer of titanium nitride from a first end and a second end of the silicon fins so that the first and second ends of the silicon fins protrude from the polysilicon layer, the polysilicon layer having a surface that faces each of the first and second ends of the silicon fins; forming a spacer over each of the two surfaces and a portion of the first and second ends of the silicon fins such that the first and second ends of the silicon fins protrude from the spacers; forming epitaxial silicon over the first and second ends of the silicon fins to form sources and drains, wherein the combination of the first layer of titanium nitride, dielectric layer and second layer of titanium nitride forms a metal-insulator-metal capacitor situated between each silicon fin and the polysilicon layer.

According to a second aspect of the exemplary embodiments there is provided a method of forming a FinFET structure having a metal-insulator-metal capacitor which includes forming silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; forming a metal-insulator-metal capacitor on the sides and horizontal surface of the silicon fins by depositing sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride; depositing a polysilicon layer over the metal-insulator-metal capacitor and over the semiconductor substrate; selectively etching the polysilicon layer and the metal-insulator-metal capacitor from a first end and a second end of the silicon fins so that the first and second ends of the silicon fins protrude from the polysilicon layer, the polysilicon layer having a surface that faces each of the first and second ends of the silicon fins; forming a spacer over each of the two surfaces and a portion of the first and second ends of the silicon fins such that the first and second ends of the silicon fins protrude from the spacers; and forming epitaxial silicon over the first and second ends of the silicon fins to form sources and drains,.

According to a third aspect of the exemplary embodiments, there is provided a FinFET structure which includes silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride on the sides and horizontal surface of the silicon fins; a polysilicon gate layer over the second layer of titanium nitride on the silicon fins and over the semiconductor substrate such that first and second ends of the silicon fins protrude from the polysilicon layer, the polysilicon layer having a surface that faces each of the first and second ends of the silicon fins; a spacer over each of the two surfaces and a portion of the first and second ends of the silicon fins such that the first and second ends of the silicon fins protrude from the spacers; epitaxial silicon over the first and second ends of the silicon fins to form sources and drains, wherein the combination of the first layer of titanium nitride, dielectric layer and second layer of titanium nitride forms a metal-insulator-metal capacitor situated between each silicon fin and the polysilicon layer.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

The features of the exemplary embodiments believed to be novel and the elements characteristic of the exemplary embodiments are set forth with particularity in the appended claims. The Figures are for illustration purposes only and are not drawn to scale. The exemplary embodiments, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:

FIGS. 1A to 1H illustrate a process for forming fins on a semiconductor substrate wherein:

FIG. 1A illustrates a starting structure including a semiconductor on insulator (SOI) substrate, an oxide layer, an amorphous silicon layer and a hard mask layer;

FIG. 1B illustrates the patterning of the amorphous silicon layer and the hard mask layer;

FIG. 1C illustrates the removal of the hard mask layer, leaving only stripes of amorphous silicon;

FIG. 1D illustrates the deposition of a conformal layer of nitride;

FIG. 1E illustrates the etching of the nitride to form sidewall spacers;

FIG. 1F illustrates the etching of the stripes of amorphous silicon to leave only the sidewall spacers;

FIG. 1G illustrates the etching of the oxide layer and the silicon layer of the SOI substrate using the sidewall spacers as a mask to result in stripes of oxide on silicon fins; and

FIG. 1H illustrates the etching of the sidewall spacers and the oxide stripes to result in silicon fins.

FIGS. 2A and 2B illustrate a starting structure of the exemplary embodiments which include fins on a semiconductor substrate.

FIGS. 3A and 3B illustrate forming sequential layers of a first titanium nitride, a dielectric and a second titanium nitride on the fins.

FIGS. 4A and 4B illustrate a next step of depositing a polysilicon layer.

FIGS. 5A and 5B illustrate etching back the polysilicon layer and sequential layers of a first titanium nitride, a dielectric and a second titanium nitride from ends of the fins.

FIGS. 6A and 6B illustrate the forming of a spacer on the polysilicon layer and portions of the ends of the fins.

FIG. 7 is a perspective view of the structure shown in FIGS. 6A and 6B.

FIGS. 8A and 8B illustrate the formation of epitaxial silicon on the ends of the fins to form a merged source and merged drain.

FIG. 9 is a perspective view of the structure shown in FIG. 8A and 8B.

DETAILED DESCRIPTION

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Referring to the Figures in more detail, and particularly referring to FIGS. 1A to 1H, there is illustrated a preferred process for forming a semiconductor substrate having fins for practicing the exemplary embodiments. The preferred process may be referred to as the sidewall image transfer process.

In FIG. 1A, the process begins with a semiconductor on insulator (SOI) substrate 102, also frequently referred to as a silicon on insulator substrate. The SOI substrate 102 may comprise a semiconductor base 104 (usually silicon but may be other semiconductor materials), a dielectric layer 106, usually an oxide layer (may also be called a buried oxide or BOX layer), and a semiconductor material 108, which is usually silicon. For the purposes of the present exemplary embodiments, it is preferred that semiconductor material 108 is silicon and will be referred to as such in the discussion that follows. On top of silicon 108 is an oxide layer 110, followed by an amorphous silicon layer 112 and hard mask layer 114, usually a nitride. Not shown in FIG. 1A are photoresist and other layers which may be used to pattern the hard mask layer 114.

Referring now to FIG. 1B, the hard mask layer 114 has been patterned and etched down through the amorphous silicon layer 112, stopping on the oxide layer 110.




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stats Patent Info
Application #
US 20140231890 A1
Publish Date
08/21/2014
Document #
File Date
12/31/1969
USPTO Class
Other USPTO Classes
International Class
/
Drawings
0


Semiconductor Silicon Capacitor Finfet Finfet Structure Metal Capacitor Mim Capacitor Semiconductor Substrate Titanium Titanium Nitride

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International Business Machines Corporation


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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)   Field Effect Device   Having Insulated Electrode (e.g., Mosfet, Mos Diode)   Insulated Gate Capacitor Or Insulated Gate Transistor Combined With Capacitor (e.g., Dynamic Memory Cell)  

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20140821|20140231890|mim capacitor in finfet structure|A method of forming a FinFET structure having a metal-insulator-metal capacitor. Silicon fins are formed on a semiconductor substrate followed by formation of the metal-insulator-metal capacitor on the silicon fins by depositing sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium |International-Business-Machines-Corporation
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