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Wire-last integration method and structure for iii-v nanowire devices

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Wire-last integration method and structure for iii-v nanowire devices


In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches...
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USPTO Applicaton #: #20140203290
Inventors: Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight, Amlan Majumdar



The Patent Description & Claims data below is from USPTO Patent Application 20140203290, Wire-last integration method and structure for iii-v nanowire devices.

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stats Patent Info
Application #
US 20140203290 A1
Publish Date
07/24/2014
Document #
13967953
File Date
08/15/2013
USPTO Class
257 76
Other USPTO Classes
257347, 977762, 977938
International Class
01L29/78
Drawings
13


Your Message Here(14K)


Semiconductor Material
Semiconductor
Elective
Gates
Rounding
Replacement Gate
Wafer


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International Business Machines Corporation

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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)   Specified Wide Band Gap (1.5ev) Semiconductor Material Other Than Gaasp Or Gaalas  

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