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Bbul top side substrate layer enabling dual sided silicon interconnect and stacking flexibility

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Bbul top side substrate layer enabling dual sided silicon interconnect and stacking flexibility


An apparatus including a die including a first side and an opposite second side including a device side with contact points; and a build-up carrier including at least one layer of conductive material disposed on a first side of the die, and a plurality of alternating layers of conductive material and dielectric material disposed on the second side of the die, wherein the at least one layer of conductive material on the first side of the die is coupled to at least one...
Related Terms: Silicon

USPTO Applicaton #: #20140159250
Inventors: Robert M. Nickerson



The Patent Description & Claims data below is from USPTO Patent Application 20140159250, Bbul top side substrate layer enabling dual sided silicon interconnect and stacking flexibility.

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stats Patent Info
Application #
US 20140159250 A1
Publish Date
06/12/2014
Document #
13976394
File Date
12/31/2011
USPTO Class
257774
Other USPTO Classes
257782, 438121
International Class
/
Drawings
7


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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)   Combined With Electrical Contact Or Lead   Of Specified Configuration   Via (interconnection Hole) Shape  

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