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Semiconductor device and a method of manufacturing the same

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Semiconductor device and a method of manufacturing the same


A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
Related Terms: Semiconductor Electrode Semiconductor Device

Browse recent Hitachi Ulsi Systems Co., Ltd. patents - Tokyo, JP
USPTO Applicaton #: #20140159245 - Class: 257773 (USPTO) -
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead >Of Specified Configuration

Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima

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The Patent Description & Claims data below is from USPTO Patent Application 20140159245, Semiconductor device and a method of manufacturing the same.

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CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of application Ser. No. 10/633,583 filed Aug. 5, 2003.

BACKGROUND OF THE INVENTION

This invention relates to a semiconductor device and also to a manufacturing technique thereof. More particularly, the invention relates to a semiconductor device having bump electrodes and also to a technique effective for application to the manufacturing technique thereof.

With multi-pin semiconductor devices such, for example, as LCD (liquid crystal display) drivers, a problem is involved in that the chip size increases with an increasing number of electrode pads. This is for the reason that the electrode pad for leading out an electrode of an integrated circuit within a semiconductor chip cannot be made small in size in comparison with the size reduction of element and wiring in view of the securing practice for bonding strength, bonding accuracy and standards on the part of packaging semiconductor chips, so that the chip size is determined depending on the number and size of electrode pads. To avoid this, with the case of multi-pin semiconductor devices, a technique or system is now being adopted wherein electrode pads are arranged in a more inner region of a semiconductor chip where elements and wirings are arranged (i.e. an active region).

It will be noted that semiconductor devices having bump electrodes are disclosed, for example, in Japanese Patent No. 3022565. In this patent, a technique is disclosed wherein a dummy pattern is arranged below electrode pads.

SUMMARY

OF THE INVENTION

We have first found that the above-mentioned structure of the type wherein electrode pads are arranged in the active region has the following new problem.

More particularly, because elements and wirings are formed below electrode pads and thus, structures provided below electrode pads differ from one another, the heights of electrode pads within the main surface of a semiconductor chip, i.e. the heights of bump electrodes bonded to the respective electrode pads, become non-uniform even if electrode pads are adjacent to each other or the bump thicknesses are made uniform. This eventually presents a problem that connection failure occurs between the electrode pads of a semiconductor chip and corresponding wirings of a packaging body for the semiconductor chip.

An object of the invention is to provide a technique wherein the heights of a plurality of electrode pads within a main surface of a semiconductor chip can be made uniform.

The above and other objects and novel features of the invention will become apparent from the following description with reference to the accompanying drawings.

A typical embodiment of the invention among those embodiments set forth in this application is briefly described below.

According to the invention, a semiconductor device is provided wherein underlying structures provided below a plurality of electrode pads arranged in a region of a main surface of a semiconductor chip where elements and wirings are arranged are made uniform.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of an essential part of an instance of wiring provided as an underlying layer of an electrode pad of a semiconductor device according to one embodiment of the invention;

FIG. 2 is a plan view of an essential part of an instance of wiring, at the same layer as in FIG. 1, provided as an underlying layer of an electrode pad of the semiconductor device according to one embodiment of the invention;

FIG. 3 is a plan view of an essential part of an instance of wiring, at the same layer as in FIGS. 1 and 2, provided as an underlying layer of an electrode pad of the semiconductor device according to one embodiment of the invention;

FIG. 4 is a sectional view, taken along line Y1-Y1 at the wiring of FIG. 1;

FIG. 5 is a sectional view of the wiring of FIG. 2, taken along line Y2-Y2 at the wiring of FIG. 2;

FIG. 6 is a sectional view, taken along line Y3-Y3 at the wiring of FIG. 3;

FIG. 7 is a plan view of an essential part of an instance of wiring, at the same layer as in FIGS. 1 to 3, provided as an underlying layer of an electrode pad of the semiconductor device according to another embodiment of the invention;

FIG. 8 is a sectional view, taken along line Y4-Y4 at the wiring of FIG. 7;

FIG. 9 is a plan view of an essential part of an instance of a wiring in an underlying layer of an electrode pad of a semiconductor device according to a further embodiment of the invention;

FIG. 10 is a plan view of an essential part of an instance of a wiring in an underlying layer, which is at the same layer level as in FIG. 9, of the electrode pad of the semiconductor device according to the further embodiment of the invention;

FIG. 11 is a plan view of an essential part of an instance of a wiring in an underlying layer, which is at the same layer level as in FIGS. 9 and 10, of the electrode pad of the semiconductor device according to the further embodiment of the invention;

FIG. 12 is a sectional view, taken along line Y5-Y5 at the wiring of FIG. 9;

FIG. 13 is a sectional view, taken along line Y6-Y6 at the wiring of FIG. 10;

FIG. 14 is a sectional view, taken along line Y7-Y7 at the wiring of FIG. 11

FIG. 15 is a plan view of an essential part of an instance of a wiring in an underlying layer of an electrode pad of a semiconductor device according to a still further embodiment of the invention;

FIG. 16 is a plan view of an essential part of an instance of a wiring in an underlying layer of an electrode pad of a semiconductor device according to another embodiment of the invention;

FIG. 17 is a plan view of an essential part of an instance of a wiring in an underlying layer of an electrode pad of a semiconductor device according to yet another embodiment of the invention;

FIG. 18 is a plan view of an essential part of an instance of a wiring in an underlying layer, which is the same layer level as in FIG. 17, of the electrode pad of the semiconductor device according to the yet another embodiment of the invention;

FIG. 19 is a plan view of an essential part of an instance of a wiring in an underlying layer, which is the same layer level as in FIGS. 17 and 18, of the electrode pad of the semiconductor device according to the yet another embodiment of the invention;

FIG. 20 is an illustrative view showing the comparison between the technique checked by us (not improved) and the technique made according to one embodiment of the invention (i.e. an improved technique) with respect to the occupation rate of the underlying wirings within a pad region;

FIG. 21 is a plan view of an essential part of an instance of a semiconductor substrate in an underlying layer of an electrode pad of a semiconductor device according to another embodiment of the invention;

FIG. 22 is a plan view of an essential part of an instance of a semiconductor substrate in an underlying layer of an electrode pad, which is different from the electrode pad of FIG. 21, of the semiconductor device according to another embodiment of the invention;

FIG. 23 is a sectional view, taken along line Y8-Y8 at the semiconductor substrate of FIG. 21;

FIG. 24 is a sectional view, taken along line Y9-Y9 at the semiconductor substrate of FIG. 22;

FIG. 25 is a plan view showing, as a whole, an instance of a semiconductor chip constituting a semiconductor device according to the invention;

FIG. 26 is a plan view of an instance of a second-layer wiring beneath an electrode pad of the semiconductor device according to another embodiment of the invention;

FIG. 27 is a plan view of an instance of a second-layer wiring beneath an electrode pad, different from that of FIG. 26, of the semiconductor device embodying the invention;

FIG. 28 is a plan view of an instance of a second-layer wiring beneath an electrode pad, different from those of FIGS. 26 and 27, of the semiconductor device embodying the invention;

FIG. 29 is a plan view of an instance of a second-layer wiring beneath an electrode pad, different from those of FIGS. 26 to 28, of the semiconductor device embodying the invention;

FIG. 30 is a plan view of an instance of a second-layer wiring beneath an electrode pad, different from those of FIGS. 26 to 29, of the semiconductor device embodying the invention;

FIG. 31 is a plan view of an instance of a second-layer wiring beneath an electrode pad, different from those of FIGS. 26 to 30, of the semiconductor device embodying the invention;

FIG. 32 is a plan view of an instance of a first-layer wiring beneath the electrode pad, which is the same as shown in FIG. 26, of the semiconductor device embodying the invention;

FIG. 33 is a plan view of an instance of a first-layer wiring beneath the electrode pad, which is the same as shown in FIG. 27, of the semiconductor device embodying the invention;

FIG. 34 is a plan view of an instance of a first-layer wiring beneath the electrode pad, which is the same as shown in FIG. 28, of the semiconductor device embodying the invention;

FIG. 35 is a plan view of an instance of a first-layer wiring beneath the electrode pad, which is the same as shown in FIG. 29, of the semiconductor device embodying the invention;

FIG. 36 is a plan view of an instance of a first-layer wiring beneath the electrode pad, which is the same as shown in FIG. 30, of the semiconductor device embodying the invention;

FIG. 37 is a plan view of an instance of a first-layer wiring beneath the electrode pad, which is the same as shown in FIG. 31, of the semiconductor device embodying the invention;

FIG. 38 is a plan view of an instance of a main surface of a semiconductor substrate in the underlying layer of the electrode pad, which is the same as shown in FIG. 26, of the semiconductor device embodying the invention;

FIG. 39 is a plan view of an instance of a main surface of a semiconductor substrate in the underlying layer of the electrode pad, which is the same as shown in FIG. 27, of the semiconductor device embodying the invention;



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stats Patent Info
Application #
US 20140159245 A1
Publish Date
06/12/2014
Document #
14178781
File Date
02/12/2014
USPTO Class
257773
Other USPTO Classes
International Class
01L23/48
Drawings
32


Semiconductor
Electrode
Semiconductor Device


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