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Semiconductor device and a method of manufacturing the same

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20140159245 patent thumbnailZoom

Semiconductor device and a method of manufacturing the same


A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
Related Terms: Semiconductor Electrode Semiconductor Device

Browse recent Hitachi Ulsi Systems Co., Ltd. patents - Tokyo, JP
USPTO Applicaton #: #20140159245 - Class: 257773 (USPTO) -
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Combined With Electrical Contact Or Lead >Of Specified Configuration



Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima

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The Patent Description & Claims data below is from USPTO Patent Application 20140159245, Semiconductor device and a method of manufacturing the same.

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CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of application Ser. No. 10/633,583 filed Aug. 5, 2003.

BACKGROUND OF THE INVENTION

This invention relates to a semiconductor device and also to a manufacturing technique thereof. More particularly, the invention relates to a semiconductor device having bump electrodes and also to a technique effective for application to the manufacturing technique thereof.

With multi-pin semiconductor devices such, for example, as LCD (liquid crystal display) drivers, a problem is involved in that the chip size increases with an increasing number of electrode pads. This is for the reason that the electrode pad for leading out an electrode of an integrated circuit within a semiconductor chip cannot be made small in size in comparison with the size reduction of element and wiring in view of the securing practice for bonding strength, bonding accuracy and standards on the part of packaging semiconductor chips, so that the chip size is determined depending on the number and size of electrode pads. To avoid this, with the case of multi-pin semiconductor devices, a technique or system is now being adopted wherein electrode pads are arranged in a more inner region of a semiconductor chip where elements and wirings are arranged (i.e. an active region).

It will be noted that semiconductor devices having bump electrodes are disclosed, for example, in Japanese Patent No. 3022565. In this patent, a technique is disclosed wherein a dummy pattern is arranged below electrode pads.

SUMMARY

OF THE INVENTION

We have first found that the above-mentioned structure of the type wherein electrode pads are arranged in the active region has the following new problem.

More particularly, because elements and wirings are formed below electrode pads and thus, structures provided below electrode pads differ from one another, the heights of electrode pads within the main surface of a semiconductor chip, i.e. the heights of bump electrodes bonded to the respective electrode pads, become non-uniform even if electrode pads are adjacent to each other or the bump thicknesses are made uniform. This eventually presents a problem that connection failure occurs between the electrode pads of a semiconductor chip and corresponding wirings of a packaging body for the semiconductor chip.

An object of the invention is to provide a technique wherein the heights of a plurality of electrode pads within a main surface of a semiconductor chip can be made uniform.

The above and other objects and novel features of the invention will become apparent from the following description with reference to the accompanying drawings.

A typical embodiment of the invention among those embodiments set forth in this application is briefly described below.

According to the invention, a semiconductor device is provided wherein underlying structures provided below a plurality of electrode pads arranged in a region of a main surface of a semiconductor chip where elements and wirings are arranged are made uniform.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of an essential part of an instance of wiring provided as an underlying layer of an electrode pad of a semiconductor device according to one embodiment of the invention;

FIG. 2 is a plan view of an essential part of an instance of wiring, at the same layer as in FIG. 1, provided as an underlying layer of an electrode pad of the semiconductor device according to one embodiment of the invention;

FIG. 3 is a plan view of an essential part of an instance of wiring, at the same layer as in FIGS. 1 and 2, provided as an underlying layer of an electrode pad of the semiconductor device according to one embodiment of the invention;

FIG. 4 is a sectional view, taken along line Y1-Y1 at the wiring of FIG. 1;

FIG. 5 is a sectional view of the wiring of FIG. 2, taken along line Y2-Y2 at the wiring of FIG. 2;

FIG. 6 is a sectional view, taken along line Y3-Y3 at the wiring of FIG. 3;

FIG. 7 is a plan view of an essential part of an instance of wiring, at the same layer as in FIGS. 1 to 3, provided as an underlying layer of an electrode pad of the semiconductor device according to another embodiment of the invention;

FIG. 8 is a sectional view, taken along line Y4-Y4 at the wiring of FIG. 7;

FIG. 9 is a plan view of an essential part of an instance of a wiring in an underlying layer of an electrode pad of a semiconductor device according to a further embodiment of the invention;

FIG. 10 is a plan view of an essential part of an instance of a wiring in an underlying layer, which is at the same layer level as in FIG. 9, of the electrode pad of the semiconductor device according to the further embodiment of the invention;

FIG. 11 is a plan view of an essential part of an instance of a wiring in an underlying layer, which is at the same layer level as in FIGS. 9 and 10, of the electrode pad of the semiconductor device according to the further embodiment of the invention;

FIG. 12 is a sectional view, taken along line Y5-Y5 at the wiring of FIG. 9;

FIG. 13 is a sectional view, taken along line Y6-Y6 at the wiring of FIG. 10;

FIG. 14 is a sectional view, taken along line Y7-Y7 at the wiring of FIG. 11

FIG. 15 is a plan view of an essential part of an instance of a wiring in an underlying layer of an electrode pad of a semiconductor device according to a still further embodiment of the invention;

FIG. 16 is a plan view of an essential part of an instance of a wiring in an underlying layer of an electrode pad of a semiconductor device according to another embodiment of the invention;

FIG. 17 is a plan view of an essential part of an instance of a wiring in an underlying layer of an electrode pad of a semiconductor device according to yet another embodiment of the invention;

FIG. 18 is a plan view of an essential part of an instance of a wiring in an underlying layer, which is the same layer level as in FIG. 17, of the electrode pad of the semiconductor device according to the yet another embodiment of the invention;

FIG. 19 is a plan view of an essential part of an instance of a wiring in an underlying layer, which is the same layer level as in FIGS. 17 and 18, of the electrode pad of the semiconductor device according to the yet another embodiment of the invention;

FIG. 20 is an illustrative view showing the comparison between the technique checked by us (not improved) and the technique made according to one embodiment of the invention (i.e. an improved technique) with respect to the occupation rate of the underlying wirings within a pad region;

FIG. 21 is a plan view of an essential part of an instance of a semiconductor substrate in an underlying layer of an electrode pad of a semiconductor device according to another embodiment of the invention;

FIG. 22 is a plan view of an essential part of an instance of a semiconductor substrate in an underlying layer of an electrode pad, which is different from the electrode pad of FIG. 21, of the semiconductor device according to another embodiment of the invention;

FIG. 23 is a sectional view, taken along line Y8-Y8 at the semiconductor substrate of FIG. 21;

FIG. 24 is a sectional view, taken along line Y9-Y9 at the semiconductor substrate of FIG. 22;

FIG. 25 is a plan view showing, as a whole, an instance of a semiconductor chip constituting a semiconductor device according to the invention;

FIG. 26 is a plan view of an instance of a second-layer wiring beneath an electrode pad of the semiconductor device according to another embodiment of the invention;

FIG. 27 is a plan view of an instance of a second-layer wiring beneath an electrode pad, different from that of FIG. 26, of the semiconductor device embodying the invention;

FIG. 28 is a plan view of an instance of a second-layer wiring beneath an electrode pad, different from those of FIGS. 26 and 27, of the semiconductor device embodying the invention;

FIG. 29 is a plan view of an instance of a second-layer wiring beneath an electrode pad, different from those of FIGS. 26 to 28, of the semiconductor device embodying the invention;

FIG. 30 is a plan view of an instance of a second-layer wiring beneath an electrode pad, different from those of FIGS. 26 to 29, of the semiconductor device embodying the invention;

FIG. 31 is a plan view of an instance of a second-layer wiring beneath an electrode pad, different from those of FIGS. 26 to 30, of the semiconductor device embodying the invention;

FIG. 32 is a plan view of an instance of a first-layer wiring beneath the electrode pad, which is the same as shown in FIG. 26, of the semiconductor device embodying the invention;

FIG. 33 is a plan view of an instance of a first-layer wiring beneath the electrode pad, which is the same as shown in FIG. 27, of the semiconductor device embodying the invention;

FIG. 34 is a plan view of an instance of a first-layer wiring beneath the electrode pad, which is the same as shown in FIG. 28, of the semiconductor device embodying the invention;

FIG. 35 is a plan view of an instance of a first-layer wiring beneath the electrode pad, which is the same as shown in FIG. 29, of the semiconductor device embodying the invention;

FIG. 36 is a plan view of an instance of a first-layer wiring beneath the electrode pad, which is the same as shown in FIG. 30, of the semiconductor device embodying the invention;

FIG. 37 is a plan view of an instance of a first-layer wiring beneath the electrode pad, which is the same as shown in FIG. 31, of the semiconductor device embodying the invention;

FIG. 38 is a plan view of an instance of a main surface of a semiconductor substrate in the underlying layer of the electrode pad, which is the same as shown in FIG. 26, of the semiconductor device embodying the invention;

FIG. 39 is a plan view of an instance of a main surface of a semiconductor substrate in the underlying layer of the electrode pad, which is the same as shown in FIG. 27, of the semiconductor device embodying the invention;

FIG. 40 is a plan view of an instance of a main surface of a semiconductor substrate in the underlying layer of the electrode pad, which is the same as shown in FIG. 28, of the semiconductor device embodying the invention;

FIG. 41 is a plan view of an instance of a main surface of a semiconductor substrate in the underlying layer of the electrode pad, which is the same as shown in FIG. 29, of the semiconductor device embodying the invention;

FIG. 42 is a plan view of an instance of a main surface of a semiconductor substrate in the underlying layer of the electrode pad, which is the same as shown in FIG. 30, of the semiconductor device embodying the invention;

FIG. 43 is a plan view of an instance of a main surface of a semiconductor substrate in the underlying layer of the electrode pad, which is the same as shown in FIG. 31, of the semiconductor device embodying the invention;

FIG. 44 is a sectional view, taken along lines Y10-Y10 of FIGS. 27, 33 and 39;

FIG. 45 is a sectional view, taken along lines Y11-Y11 of FIGS. 29, 35 and 41;

FIG. 46 is an illustrative view showing wiring occupation rates of the respective wiring layers provided beneath individual electrode pads of the semiconductor device shown in FIG. 25;

FIG. 47 is a histogram showing the occupation rate of the first-layer wiring of FIG. 46;

FIG. 48 is a histogram showing the occupation rate of the second-layer wiring of FIG. 46;

FIG. 49 is a plan view of an essential part of a liquid crystal display;

FIG. 50 is a sectional view of the essential part of FIG. 49;

FIG. 51 is an enlarged, sectional view of the essential part of FIG. 50;

FIG. 52 is an enlarged, sectional view of the essential part of FIG. 51;

FIG. 53 is a perspective view of an essential part of TCP according to another embodiment of the invention;

FIG. 54 is an enlarged, sectional view of the essential part at the inner lead side of TCP of FIG. 53;

FIG. 55 is a sectional view of an essential part in a packaging state of TCP of FIG. 53 in a liquid crystal display;

FIG. 56 is a sectional view of an essential part in a packaging state of a semiconductor device, embodying the invention, on a liquid crystal display with COF;

FIG. 57 is a sectional view of T-TF/BGA (CSP) of a fan-out type according to a further embodiment of the invention;

FIG. 58 is a plan view of T-TF/BGA (CSP) of a fan-in type according to a still further embodiment of the invention;

FIG. 59 is a sectional view, taken along line X1-X1 of FIG. 58; and

FIG. 60 is an enlarged, sectional view of an essential part of FIGS. 58 and 59.

DETAILED DESCRIPTION

OF THE PREFERRED EMBODIMENTS

Although embodiments of the invention are illustrated by division into a plurality of sections or sub-embodiments if expediently necessary, these are not mutually irrelevant to one another unless otherwise stated. More particularly, one may be in relation with modifications, details, supplemental explanation and the like of part or all of others. In the following embodiments, where reference is made to the number and other parameters of elements (including the number, numerical value, quantity, range and the like), they should not be cons trued as limiting to specified values or numbers, respectively, except the case where otherwise specified or where limited to a specific value apparently in principle. That is, those values smaller than or larger than the respective specified values may also be within the scope of the invention. Moreover, it is as a matter of course that constituent elements (including steps) in the following embodiments are not always essential except the case where otherwise specified or where such elements are considered to be apparently essential in principle. Likewise, if reference is made to the shape, position, relation and the like of the constituent elements, then substantially like or similar shapes and the like are also within the scope of the invention except the case where otherwise specified or where such similar shapes should not be apparently included in principle. This is true of the above-indicated numbers and ranges. Throughout the drawings for illustrating the embodiments of the invention, like reference numerals indicate like parts or members having a similar function, which are not repeatedly explained after once having been illustrated. In the accompanying drawings for illustrating embodiments of the invention, such drawings including plan views may be hatched in some case for easily viewable purposes. The embodiments of the invention are now described with reference to the accompanying drawings

Embodiment 1

This embodiment deals with a semiconductor device having an active-on-pad arrangement wherein a plurality of electrode pads (hereinafter referred to simply as pad or pads) are arranged in an active region having a semiconductor chip element or wirings disposed therein. In this semiconductor device, the structures of underlying layers for the plurality of pads are made uniform. More particularly, the occupation rates of the underlying wirings (wiring occupation rates) for the pads arranged within the respective pad regions are made uniform for every wiring layer. To this end, firstly, a dummy wiring is provided at a region, in which the wiring occupation rate is smaller than those wiring occupation rates of other pad regions, which is taken from a plurality of pad regions having the same wiring layer. In contrast, a slit or slits are formed in a wiring in a region (i.e. in a region where part of a wiring is removed), which has a wiring occupation rate larger than the wiring occupation rates of other pad regions and is taken from the plurality of pad regions having the same wiring layer. Secondly, an active region is arranged at an underlying layer of all the pads of a semiconductor chip, i.e. pads for integrated circuit and dummy pads.

Initially, an arrangement of the dummy wiring is illustrated. FIGS. 1 to 3 are, respectively, a plan view showing an instance of an essential part of each of wirings MXa, MXb, MXc, MXd and MXe in a given wiring layer serving as an underlying layer of pads PD1 to PD3. FIGS. 4 to 6 are, respectively, sectional views, taken along lines Y1-Y1, Y2-Y2 and Y3-Y3 at the wirings MXa to MXe of FIGS. 1 to 3. The pads PD1 to PD3 are, respectively, a portion at which a bump is bonded and are disposed at different positions of the active region of the same semiconductor chip. The pads PD1 to PD3 are equal to one another with respect to the planar size and shape. The wirings MXa, MXb, MXc and MXd, respectively, indicate a wiring for signal or power supply which is necessary for constituting an integrated circuit of a semiconductor chip, whereas the wiring MXe indicates a dummy wiring not necessary for the arrangement of the integrated circuit of the semiconductor chip. All the wirings MXa to MXe are formed on an insulating film ISa by patterning, for example, a metal film made mainly of aluminium or the like or a built-up conductor film made mainly of aluminium or the like and other type of conductor film (e.g. a built-up conductor film obtained by depositing a metal film made mainly, for example, of titanium (Ti), titanium nitride (TiN), aluminium or the like and a film of titanium nitride in this order) according to photolithographic and etching techniques. The wirings are covered with an insulating film ISb. As is particularly shown in FIGS. 3 and 6, the dummy wiring MXe is arranged in a region which corresponds to the pad PD3 region and in which any wiring would not be otherwise arranged. In this way, the occupation rate of the underlying wiring within the pad PD3 region is so designed as to be equal to the occupation rates of the underlying wirings within the pads PD1 and PD2 shown in FIGS. 1 and 2. This permits the upper levels of the insulating film ISb within the regions of the pads PD1 to PD3 of FIGS. 1 to 3 to be uniform as is particularly shown in FIGS. 4 to 6. Moreover, the upper portions of the underlying insulating films ISb within the regions of the pads PD1 to PD3 can be improved with respect to the flatness thereof.

Although it is assumed that the dummy wiring MXe is provided as a wiring in a floating state which is not electrically connected with any other wiring, the dummy wiring may be formed by extending part of a wiring necessary for the arrangement of an integrated circuit (i.e. the wiring MXd in this case) to a region where the arrangement of a dummy wiring is required. In this case, although the wiring per se is not a dummy wiring, a wiring portion extending, for achieving the purpose of this embodiment, to a region not inherently required for arrangement of wiring is taken as a dummy. FIGS. 7 and 8, respectively, show a modification of arrangement of dummy wiring. FIG. 7 is a plan view showing an instance of an essential part of a wiring formed at the same layer level as the wirings shown in FIGS. 1 to 6, and FIG. 8 shows a sectional view taken along line Y4-Y4 at the wiring of FIG. 7. A pad PD4 indicates a pad which is located in an active region of the semiconductor chip different from the region where the pads PD1 to PD3 of FIGS. 1 to 3 are arranged, with its planar size and shape being same as those of the pads PD1 to PD3. Wirings MXf and MXg indicate wirings for signal or power supply which are necessary for the constitution of an integrated circuit of the semiconductor chip. Wiring MXh indicates a dummy wiring. In this connection, the occupation rates of the underlying wirings MXf and MXg within the region of the pad PDF are substantially same as those illustrated in FIGS. 1 to 3. From the standpoint that the occupation rates are made uniform, any dummy wiring is not required, and such a dummy wiring is not arranged within a region of the pad PD4. In this case, the dummy wiring MXh is arranged in the vicinity of an outer periphery of the pad PD4. If this dummy wiring MXh is not provided, the insulating film ISb in the vicinity of the outer periphery of the pad PD4 is recessed at the upper surface thereof, thereby causing steps to occur. Because the flat area of a bump bonded with the pad PD4 is slightly larger than that of the pad PD4, the step at the upper surface of the insulating film ISb in the vicinity of the outer periphery of the pad PD4 is reflected on the upper surface of the bump electrode. As a result, the bump is impeded with flatness at the top thereof and may become, in some case, lower in height than the tops of other bumps. To avoid this, the dummy wiring MXh is arranged in the vicinity of the outer periphery of the pad PD4, so that a step can be prevented from being formed at the upper surface of the insulating film ISb at the outer periphery of the pad PD4, thereby improving the flatness at the upper surface of the pad PD4 and thus ensuring the height of the pad PD4. In this way, the height at the top of the bump bonded with the pad PD4 can be mad equal to the height at the top of other bumps. It will be noted that the bumps are, respectively, formed in a uniform thickness. More particularly, a variation in thickness of bumps can be substantially neglected.

Next, how to arrange the above slits is illustrated. FIGS. 9 to 11 are, respectively, a plan view showing instances of essential parts of wirings MXi, MXj, MXk and MXm in the same given wiring layer which is an underlying layer of the pads PD5 to PD7. FIGS. 12 to 14 are, respectively, sectional views, taken along lines Y5-Y5, Y6-Y6 and Y7-7 at the wirings MXi, MXj, MXk and MXm of FIGS. 9 to 11. The pads PD5 to PD7 are similar to the pads PD1 to PD3, and are not particularly illustrated. The wirings MXi, MXj, MXk and MXm, respectively, indicate those wirings for signal or power supply necessary for arrangement of an integrated circuit of a semiconductor chip. The materials and forming method of these wirings MXi, MXj, MXk and MXm are similar to those of the wirings MXa and the like. As is particularly shown in FIGS. 10, 11, 13 and 14, a slit SL is formed in part of the wirings MXk and MXm, respectively. The slit or slits SL are formed by removing part of the wiring MXk and MXm. This permits the occupation rates of the underlying wirings within the pads PD6, PD7 to become equal to the occupation rate of the underlying wiring within the pad PD5 of FIG. 9. In this manner, the heights of the upper surfaces of the underlying insulating film ISb within the regions of the pad PD5 to PD7 can be made uniform as shown in FIGS. 12 to 14. In addition, the flatness at the upper portion of the underlying insulating film ISb within the pad PD5 to PD7 can be improved. The slit SL may be formed at the center of the wiring MXk as shown in FIG. 10, or may be formed as extending from the outer periphery of the wiring MXm toward the center as shown in FIG. 11. In this embodiment, the slit SL of FIGS. 10 and 11 is formed at a position of the space between adjacent wirings MXi and MXj of FIG. 9. This allows the underlying states of the pads PD5 to PD7 to become more uniform, thereby ensuring a more uniform height and more improved flatness at the upper surface of the underlying insulating film ISb within the regions of the pads PD5 to PD7.

FIGS. 15 and 16, respectively, show modifications of slit SL. FIG. 15 shows an instance wherein each slit SL is bent downwardly at a central side end of the wiring as viewed in FIG. 15. FIG. 16 shows an instance wherein a plurality of slits SL are formed in parallel to one another as extending in vertical directions (in a lengthwise direction of the pad PD6) of FIG. 16. FIGS. 17 to 19 are, respectively, plan views showing instances of essential parts of underlying wirings MXn, MXp, MXq, MXr and MXs in the same given wiring layer of pads PD8 to PD10. The pads PD8 to PD10 are similar to the pads PD1 to PD3, with their illustration being omitted. The wirings MXn, MXp, MXq, MXr and MXs indicate those wirings for signal or power supply necessary for the arrangement of an integrated circuit of a semiconductor chip, and the material and forming method thereof are similar to those of the wiring MXa and the like. In this embodiment, as shown in FIGS. 18 and 19, slit SL is formed by adaptation to a position of space between adjacent wirings of the wirings MXn, MXp and MXq of FIG. 17. In FIG. 19, the slit SL is formed in the form of a frame. It will be noted that the pads PD1 to PD10 may be those pads for signal or power supply necessary for arrangement of an integrated circuit of a semiconductor chip, or may be dummy pads which are not required for the arrangement of the integrated circuit, respectively.

According to this embodiment, the formation of a dummy wiring or slit permits the occupation rates of the underlying wirings of the pads disposed within all the regions of the pads in the main surface of the semiconductor chip to be made uniform for every wiring layer. FIG. 20 shows an instance of comparison between the technique tested by us (i.e. a non-improved technique) and the technique of this embodiment (i.e. an improved technique) with respect to the occupation rates of the underlying wirings within the regions of pads. With the non-improved technique, the respective wiring layers of first-layer wiring M1, second-layer wiring M2 and third-layer wiring M3 have variations in wiring area occupation rate within the respective regions of pads PD1 to PDn. Alternatively, there may be a portion where an active region exists or does not exists in the underlying layer of the respective pads PD1 to PDn. For these reasons, the underlying layers of the pads PD1 to PDn are caused to be stepped, so that the heights of the pads PD1 to PDn vary from one another. In the course of the manufacture of semiconductor devices, an underlying insulating film of wirings is etched back and flattened so as to conveniently carry out, for example, exposure or etching. From the standpoint of exposure or etching, good flatness is obtained at the upper surface of the underlying insulating film. From the standpoint of the heights of the pads PD1 to PDn, there may be some case where even though such an etching-back treatment as mentioned above is effected, the heights of the pad PD1 to PDn greatly vary due to the variation of the wiring occupation area rate within the regions of the pads PD1 to PDn and also due to the presence or absence of an active region. Since the pads PD1 to PDn are arranged in active regions, it is not possible to adopt a technique wherein a solid wiring is provided in the underlying layer of the respective pads PD1 to PDn in order to ensure the flatness at the upper surface of the underlying insulating film.

In contrast, according to this embodiment (after improvement), the respective wiring layers of the first-layer wiring M1, second-layer wiring M2 and third-layer wiring M3 are so designed as to have a uniform wiring area occupation rate within the regions of the pads PD1 to PDn. An active region is provided beneath all the pads PD1 to PDn. In this way, the underlying states of a plurality of pads within a main surface of the semiconductor chip (within a main surface of a wafer for the manufacturing process of a semiconductor device) can be made substantially uniform, under which the heights of the upper surface of the plural pads can be made substantially uniform. Thus, the heights at the tops of the bumps (bump electrodes) bonded with the respective pads can be made substantially uniform. Because the respective pads can be improved in flatness at the upper surfaces thereof, the flatness at the tops of the thus bonded bumps can also be improved. Accordingly, it becomes possible to well connect a plurality of pads of a semiconductor chip and a plurality of wirings of a packaging body for packaging the semiconductor chip via bumps without suffering any inconvenience. It is preferred that the underlying wirings of the respective pads are so formed as to be equal to one another with respect to the shape, size, pattern arranging position and arranging pitch. Thus, the underlying states of a plurality of pads can be further improved and the plurality of pads are made more uniform with respect to the heights and flatness at the upper surfaces of the plurality of pads. Eventually, the height and flatness at the tops of the bumps bonded with the respective pads can be made more uniform.

Thus, according to this embodiment, the underlying states of a plurality of pads are made uniform so as to make more uniform height and flatness at the tops of a plurality of pads. This effect is not lost if the uniformity is within a certain range of error with full uniformity being not ensured. Preferably, the occupation rate of wirings beneath the respective pads is within an error of about 10%, more preferably within an error of about 5%, within which the height and flatness at the upper surfaces of the pads can be made substantially uniform.

In this embodiment, the underlying layers beneath the respective pads are indicated as first-layer wiring M1, second-layer wiring M2 and third-layer wiring M3, and the wiring occupation rates of the respective wiring layers should preferably be at 50% or over. This is for the reason that where a number of insulating films are provided below the respective pads, the upper surface is recessed and steps are liable to develop. Nevertheless, if metal layers which are harder than an insulating film are formed largely in number, a variation of steps is reduced, with the likelihood that the height and flatness at the upper surface of the pads are made uniform.

Next, layout of the active regions is illustrated. FIGS. 21 and 22, respectively, show a plan view of an instance of an essential part of an underlying semiconductor substrate 1S (hereinafter referred to simply as substrate) of pads PD11 and PD 12. FIGS. 23 and 24 are, respectively, sectional views, taken along lines Y8-Y8 and Y9-Y9 of FIGS. 21 and 22. In FIGS. 21 and 22, the drawings are, respectively, hatched at an isolation portion 2 for easy review. This isolation portion 2 is, for example, LOCOS (local oxidation of silicon) formed by oxidation of a substrate 1S or STI (shallow trench isolation) or the like formed by forming a groove in the substrate 1S and burying an insulating film in the groove, and is thus formed for dielectric isolation of individual active regions. The pad PD11 is a pad for signal or power supply which is necessary for constituting an integrated circuit of a semiconductor chip. An active region La, in which a given type of element is formed, is arranged below the pad PD11. On the other hand, pad PD12 is a dummy pad which is not required for arrangement of an integrated circuit of a semiconductor chip. In these figures, there is shown an instance where the planar size of the dummy pad PD12 is larger than that of the pad PD11. An active region Lb is also arranged below the dummy pad PD12. This active region Lb is not provided so as to form a given type of element, but is used as an active region for dummy pad which is provided so that a plurality of pads of a semiconductor chip are made uniform at the upper surface level (i.e. the height of the tops of a plurality of bumps) as set forth hereinabove. The provision of the active regions as the underlying layers of all the pads including the dummy pad PD 12 renders it easy to make uniform flatness and height at the upper surfaces of an underlying insulating film for all the pads. More particularly, the underlying state of a plurality of pads can be made more uniform and thus, the height and flatness of the upper surfaces of a plurality of pads can be made more uniform. This leads to further uniform height and flatness at the tops of the bumps bonded with the respective pads.

Next, a specific application of the semiconductor device according to this embodiment is described. FIG. 25 is a plan view showing, as a whole, an instance of a semiconductor chip 1C for constituting the semiconductor device of this embodiment. This semiconductor chip 1C has, for example, a substrate 1S which is formed in an elongated, rectangular shape and also has, on a main surface thereof, a LCD drive circuit for driving a liquid crystal display (LCD). This LCD driver circuit has the function of supplying a voltage to individual pixels of a cell array of LCD to control the direction of liquid crystal molecules, and has a gate drive circuit 3, a source drive circuit 4, a liquid crystal drive circuit 5, a graphic RAM (random access memory) 6 and a peripheral circuit 7. In the vicinity of the outer periphery of the semiconductor chip 1C, there are arranged the plural pads PD at given intervals along the outer periphery of the semiconductor chips 1C. These plural pads PD are provided on the active region where elements and wirings of the semiconductor chips are arranged. These plural pads PD includes pads for integrated circuit necessary for constituting an integrated circuit and dummy pads not necessary for the constituting an integrated circuit. The pads PD are arranged in a zigzag form in the vicinity of one long side and two short of the semiconductor chip 1C. The plural pads arranged in the zigzag form are made mainly of those for gate output signal and source output signal. More particularly, the plural pads, which have been arranged in a zigzag form at the center of the long side of the semiconductor chip 1C are for source output signal, and the plural pads, which have been arranged in a zigzag form along both short sides of the semiconductor chip 1C are for gate output signal. Such a zigzag arrangement permits a large number of pads required for gate and source output signals to be arranged while suppressing the semiconductor chip 1C from increasing in size. More particularly, the chip size can be reduced, and the number of pads (pins) can be increased. A plurality of pads PD arranged in parallel to one another, not in a zigzag form, in the vicinity of the other long side of the semiconductor chip 1C are those pads for digital or analog input signal. In the vicinity of the four corners of the semiconductor chip 1C, pads PD having a relatively large planar size are arranged. This relatively large-sized PD pad indicates a corner dummy pad. The relative small pad PD has a planar size, for example, of about 35 μm×50 μm. The planar size of the relatively large-sized pad PD (corner dummy pad) is, for example, at about 80 μm×80 μm. The pitch of the adjacent pitch is, for example, at about 30 μm to 50 μm. The total number of the pads PD is, for example, at about 800.

Next, the state of the underlying layer of the pads PD in the semiconductor device according to this embodiment is described with reference to FIGS. 26 to 45. In these figures, a semiconductor device having a three-layered wiring structure is exemplified. FIGS. 26 to 31 are, respectively, a plan view showing an instance of an essential part of wiring Mw in a second wiring layer beneath pads PD13 to PD 18 (PD), and FIGS. 32 to 37 are, respectively, a plan view showing an instance of an essential part of a wiring M1 in a first wiring layer serving as an underlying layer of the same pads PD13 to PD18 as in FIGS. 26 to 31. FIGS. 38 to 43 are, respectively, a plan view of an instance of an essential part of a main surface of a substrate serving as an underlying layer of the same pads PD13 to PD18 as in FIGS. 26 to 31. FIG. 44 is a sectional view, taken along line Y10-Y10 of FIGS. 27, 33 and 39, and FIG. 45 is a sectional view, taken along line Y11-Y-11 of FIGS. 29, 35 and 39. The pads PD12, PD14 are, for example, those pads PD for gate output signal. The pad PD13 indicates a pad provided at an outer side (i.e. at a side nearer to the outer periphery of the semiconductor chip 1C) among those pads arranged in the zigzag form. The pad PD14 indicates a pad provided at an inner side (i.e. at a side nearer to the center of the semiconductor chip 1C) among those zigzag pads. The pad PD15 is a pad PD, for example, for source output signal, and indicates an inner side pad among the zigzag pads. The pad PD16 indicates, for example, a corner dummy pad. The pads PD17, PD18, respectively, indicate a pad PD for analog input signal, for example. It will be noted that although the pads PD13 to PD18 which are part of all the pads are indicated only for illustration, the embodiment of the invention can be applied to all the pads in practice. For easy review of the drawings, the first-layer wiring M1, the second-layer wiring M2 and the isolation portion 2 are depicted as being hatched.

The second-layer wirings M2 provided beneath the pads PD13 to PD18 are illustrated with reference to FIGS. 26 to 31. The second-layer wirings M2 beneath the pads PD13 to PD18 are formed in the same way as or similar to the second-layer wiring M2 of FIGS. 26, 27 and also of FIGS. 30, 31 with respect, for example, to the shape, size and positional relationship of wiring pattern. Moreover, there is a region where although the second-layer wirings M2 provided beneath the pads PD differ from one another with respect to the shape, size and positional relationship of wiring pattern, a slit SL or a dummy wiring is formed so that the occupation rates (wiring occupation rates) of the second-layer wirings M2 within the region of a plurality of pads PD13 to PD18 are equal to one another. It will be noted that the second-layer wirings M2 within the pad PD region may include, aside from the second-layer wirings M2 necessary for constituting the integrated circuit of the semiconductor chip, second-layer wirings M2 for dummy (which may include not only the cases where all the wirings serve for dummy and are in a floating condition, but also the cases where part of the wirings for integrated circuit is used as a dummy) which are provided from the standpoint of not requiring the constitution of the integrated circuit, but ensuring equal occupation rates within the pad region.



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stats Patent Info
Application #
US 20140159245 A1
Publish Date
06/12/2014
Document #
14178781
File Date
02/12/2014
USPTO Class
257773
Other USPTO Classes
International Class
01L23/48
Drawings
32


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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)   Combined With Electrical Contact Or Lead   Of Specified Configuration