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Memory device interconnects and method of manufacture


Title: Memory device interconnects and method of manufacture.
Abstract: An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines extend through the first inter-level dielectric layer. Each of a plurality of source line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines. Each of the plurality of staggered bit line contacts extend through the first and second inter-level dielectric layes to respective bit lines. ... Browse recent Spansion Llc patents
USPTO Applicaton #: #20140145337
Inventors: Shenqing Fang, Connie Wang, Wen Yu, Fei Wang



The Patent Description & Claims data below is from USPTO Patent Application 20140145337, Memory device interconnects and method of manufacture.




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stats Patent Info
Application #
US 20140145337 A1
Publish Date
05/29/2014
Document #
14102450
File Date
12/10/2013
USPTO Class
257760
Other USPTO Classes
438624
International Class
/
Drawings
28


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Integrated Circuit
Memory Device


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