Free Services  

  • MONITOR KEYWORDS
  • Enter keywords & we'll notify you when a new patent matches your request (weekly update).

  • ORGANIZER
  • Save & organize patents so you can view them later.

  • ARCHIVE
  • View the last few months of your Keyword emails.

  • COMPANY DIRECTORY
  • Patents sorted by company.

Follow us on Twitter
twitter icon@FreshPatents

Browse patents:
Next
Prev

Double patterning compatible colorless m1 route




Title: Double patterning compatible colorless m1 route.
Abstract: A method for enabling functionality in circuit designs utilizing colorless DPT M1 route placement that maintains high routing efficiency and guarantees M1 decomposability of a target pattern and the resulting circuit are disclosed. Embodiments include: determining a boundary abutting first and second cells in an IC; determining a side of a first edge pin in the first cell facing a side of a second edge pin in the second cell; determining a first vertical segment of at least a portion of the side of the first edge pin and a second vertical segment of at least a portion of the side of the second edge pin; designating an area between the first vertical segment and the boundary as a first portion of a routing zone; and designating an area between the second vertical segment and the boundary as a second portion of the routing zone. ...


Browse recent Globalfoundries Inc. patents


USPTO Applicaton #: #20140097892
Inventors: Lei Yuan, Jongwook Kye, Mahbub Rashed, Qinglei Wang


The Patent Description & Claims data below is from USPTO Patent Application 20140097892, Double patterning compatible colorless m1 route.

TECHNICAL FIELD

- Top of Page


The present disclosure relates to a selection and placement of route patterns in an integrated circuit (IC) to improve routing efficiency, chip scaling, and circuit performance. The present disclosure is particularly applicable to IC designs in 20 and 14 nanometer (nm) technology nodes and beyond utilizing double patterning technology (DPT).

BACKGROUND

- Top of Page


In placement and routing (P&R) technologies for IC design, use of metal 1 (M1) back-to-back (B2B) routes improves routing efficiency, chip scaling, and circuit performance. FIG. 1 illustrates an exemplary P&R layout of a M1 layer. As shown, cells 101a and 101b have edge pins 103a and 103b connected by M1 B2B route 105. Additionally, the M1 layer includes a power rail 107 (e.g., Vss) and ground rail 109 (e.g., Vdd). As illustrated in FIG. 1, M1 B2B routes 105 improve routing efficiency, chip scaling, and circuit performance, by, for instance, enabling different cells (e.g., 101a and 101b) to be connected via edge pins (e.g., 103a and 103b) within the M1 layer. That is, M1 B2B routes 105 remove the need to connect edge pins (e.g., 103a, 103b) using another layer (e.g., metal 2 layer).

However, features (e.g., routes, edge pins, etc.) and pitches (e.g., spacing between features) of IC designs continue to decrease in size. In order to support such features and pitches, many IC designs form features utilizing DPT. FIG. 2 illustrates an exemplary DPT process. As shown, an overall route pattern 201 is generated from a partial route pattern 201a formed by a first mask (and/or color space) and a partial route pattern 201b formed by a second mask (and/or second color space). By using two separate masks (and/or color spaces), the pitch 203 between features using DPT may be less than (e.g., half) a pitch using a single mask, such as pitch 203a and pitch 203b. IC designs utilizing DPT, however, require zero odd cycles for the designs to be decomposable by the separate masks. Additionally, some odd cycles may be removed using a stitch (e.g., a continuous metal geometry/polygon decomposed into two masks). Stitch generation, however, utilizes complicated stitching color (DPT) rules, particularly in the M1 layer. Thus, a layout decomposition tool, rather than traditional IC P&R technologies, utilizes the stitching color rules to generate stitches.

As such, traditional P&R technologies utilizing DPT either require compliance with color rules (i.e., without the stitching color rules), as described further with respect to FIG. 3, or ignore the affect of DPT, as described further with respect to FIG. 4.

Traditional P&R routing technologies utilizing color rules guarantee M1 decomposability, but generate IC designs having reduced routing efficiency. Adverting to FIG. 3, a target pattern 301 for the M1 layer is composed of edge pins 303 and 305 connected together by a target M1 B2B route 307. A first mask having a critical dimension (CD) 309 is designated to decompose a partial pattern 301a having edge pin 303. Similarly, a second mask having the CD 309 is designated to decompose a partial pattern 301b having edge pin 305. Traditional P&R routing technologies are unaware of stitching color rules and thus generate a route (not shown) connecting edge pins 303 and 305 in another layer (e.g., metal layer 2) rather than generating the M1 B2B route 307. As such, traditional P&R technologies using color rules overly restrict the generation of M1 B2B routes resulting in reduced routing efficiency, chip scaling, and circuit performance of a resulting IC design. Additionally, color rules in the M1 layer are particularly difficult to implement because M1 layer geometries of standard cells frequently contain two-dimensional shapes that require complicated color rules.

Traditional P&R technologies ignoring the effect of DPT rules (i.e., colorless) may allow for additional M1 B2B routes, but do not guarantee M1 decomposability. Adverting to FIG. 4, a target pattern 401 for the M1 layer includes edge pins 403, 405, and 407, with edge pins 403 and 407 connected together by a target M1 B2B route 409. Similar to FIG. 3, the M1 B2B route 409 cannot be decomposed using a single mask. A first mask is designated to decompose a partial pattern 401a having edge pin 403 and a part 409a of M1 B2B route 409. Similarly, a second mask is designated to decompose a partial pattern 401b having edge pins and 405 and 407, and a part 409b of M1 B2B route 409. However, the second mask cannot decompose partial pattern 401b due to a tip-to-tip conflict between edge pin 405 and a part 409b of M1 B2B route 409. Specifically, tip-to-tip distance 411 between edge pin 405 and the part 409b of M1 B2B route 409 is less than a CD for the second mask, resulting in an odd (e.g., three) number of masks being required to decompose the target pattern 401. As such, the M1 B2B route 409 is not decomposable in the masks separately or in combination. Thus, traditional colorless P&R technologies may result in M1 layers that cannot be decomposed utilizing DPT.

A need therefore exists for a methodology enabling M1 B2B routes that maintain high routing efficiency and guarantee M1 decomposability of a target pattern, and a resulting IC.

SUMMARY

- Top of Page


An aspect of the present disclosure is a method including designating an area between edge pins as routing area.

Another aspect of the present disclosure is a circuit having each route connecting edge pins separated from corners of facing sides of the edge pins connected by each route.

Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.

According to the present disclosure, some technical effects may be achieved in part by a method including: determining a boundary abutting first and second cells in an IC; determining a side of a first edge pin in the first cell facing a side of a second edge pin in the second cell; determining a first vertical segment of at least a portion of the side of the first edge pin and a second vertical segment of at least a portion of the side of the second edge pin; designating an area between the first vertical segment and the boundary as a first portion of a routing zone; and designating an area between the second vertical segment and the boundary as a second portion of the routing zone.

Some aspects include a method wherein the first vertical segment is separated from at least one corner on the side of the first edge pin by at least a predefined distance. Additional aspects include a method wherein the first and second edge pins are designated as decomposable in a single layer using a plurality of masks, the method including: determining the predefined distance based on a side-to-side, tip-to-side, or tip-to-tip minimum resolution of a single patterning, for at least one of the plurality of masks, or a combination thereof. Further aspects include a method wherein the first vertical segment is separated from both corners on the side of the first edge pin by at least the predefined distance.

Additional aspects include: determining a side of a third edge pin in the first cell facing the side of the second edge pin; determining a third vertical segment comprising at least a portion of the side of the third edge pin, wherein the third vertical segment is separated from at least one corner on the side of the third edge pin by at least the predefined distance; and designating an area between the third vertical segment and the boundary as a third portion of the routing zone. Some aspects include a method wherein the second vertical segment is separated from at least one corner on the side of the second edge pin by at least the predefined distance. Additional aspects include: determining a first critical corner on the side of the first edge pin based on the first critical corner being separated from an outer edge of the first cell by the third edge pin, wherein the first vertical segment is separated from the first critical corner by at least the predefined distance; and determining a second critical corner on the side of the third edge pin based on the second critical corner being separated from an outer edge of the first cell by the first edge pin, wherein the third vertical segment is separated from the second critical corner by at least the predefined distance. Further aspects include designating a route, connecting the first and second edge pins, to be decomposable based on the route being placed inside the routing zone. Some aspects include: designating the first edge pin to be decomposed in a single layer using a first mask; designating the second edge pin to be decomposed in the single layer using a second mask; and designating the route to be decomposed in the single layer using the first and second masks.

Another aspect of the present disclosure is a circuit including: a plurality of cells in an IC; a plurality of edge pins in the cells, each edge pin being in one of the cells; and a plurality of routes connecting the edge pins, each of the routes connecting one edge pin in one of the cells to another edge pin in another cell that is adjacent to the one cell, wherein each of the routes is placed between portions of facing sides of the edge pins connected by the route, the portions being separated from corners of the facing sides.

Aspects include a circuit wherein the routes and edge pins are formed in a single layer. Further aspects include a circuit wherein the single layer consists of the routes and edge pins. Additional aspects include a circuit wherein the routes and edge pins have a minimum resolution less than a minimum resolution of single patterning of a mask associated with the single layer, the minimum resolution of the routes and edge pins being based on a side-to-side, tip-to-side, and tip-to-tip minimum resolution of the routes and edge pins. Some aspects include a circuit wherein each of the routes is separated from at least one corner of each edge pin connected by the route by at least the minimum resolution of single patterning. Further aspects include a circuit wherein each of the routes is separated from corners of each edge pin connected by the route by at least the minimum resolution of single patterning. Additional aspects include a circuit wherein at least one of the routes is decomposed in the single layer by a plurality of masks. Some aspects include a circuit wherein at least one cell of the cells has two or more edge pins, each of the two or more edge pins being connected to an edge pin of the adjacent cell by the routes.

Another aspect of the present disclosure is a method including: determining a boundary abutting first and second cells in an IC; determining a side of a first edge pin in the first cell facing a side of a second edge pin in the second cell; designating the first edge pin to be decomposed in a single layer using a first mask; designating the second edge pin to be decomposed in the single layer using a second mask; determining a first vertical segment of at least a portion of the side of the first edge pin, wherein the first vertical segment is separated from at least one corner on the side of the first edge pin by at least a predefined distance, and wherein the predefined distance is based on a side-to-side, tip-to-side, or tip-to-tip minimum resolution of a single patterning of the first and/or second masks, or a combination thereof; determining a second vertical segment of at least a portion of the side of the second edge pin, wherein the second vertical segment is separated from at least one corner on the side of the second edge pin by at least the predefined distance; designating an area between the first vertical segment and the boundary as a first portion of a routing zone; designating an area between the second vertical segment and the boundary as a second portion of the routing zone; designating a route connecting the first and second edge pins to be decomposable based on the route being placed inside the routing zone; and designating the route to be decomposed in the single layer using the first and second masks.

Some aspects include a method wherein the first vertical segment is separated from both corners on the side of the first edge pin by at least the predefined distance, and wherein the second vertical segment is separated from both corners on the side of the second edge pin by at least the predefined distance. Additional aspects include determining a critical corner on the side of the first edge pin based on the critical corner being separated from an outer edge of the first cell by another edge pin, wherein the first vertical segment is separated from the first critical corner by at least the predefined distance.

Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

- Top of Page


The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

FIG. 1 illustrates an exemplary P&R layout of a M1 layer;

FIG. 2 illustrates an exemplary DPT process;

FIG. 3 illustrates an exemplary inefficient P&R layout of a M1 layer utilizing a traditional color DPT process;

FIG. 4 illustrates an exemplary P&R layout of a M1 layer utilizing a traditional colorless DPT process that is not decomposable; and

FIGS. 5 through 8 illustrate a DPT compatible colorless process that guarantees decomposability, in accordance with an exemplary embodiment, with

FIGS. 5A and 5B illustrating alternative beginning cell structures.

DETAILED DESCRIPTION

- Top of Page


In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”

The present disclosure addresses and solves the current problem of routing inefficiency attendant upon utilizing DPT for forming B2B routes in IC designs. In accordance with embodiments of the present disclosure, the problems are solved, for instance by, inter alia, designating, within adjacent cells, a routing zone configured to ensure that routes placed in the routing zone are decomposable with routes and edge pins placed inside the adjacent cells.




← Previous       Next → Advertise on FreshPatents.com - Rates & Info


You can also Monitor Keywords and Search for tracking patents relating to this Double patterning compatible colorless m1 route patent application.

###


Browse recent Globalfoundries Inc. patents

Keyword Monitor How KEYWORD MONITOR works... a FREE service from FreshPatents
1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored.
3. Each week you receive an email with patent applications related to your keywords.  
Start now! - Receive info on patent apps like Double patterning compatible colorless m1 route or other areas of interest.
###


Previous Patent Application:
Reconfiguring through silicon vias in stacked multi-die packages
Next Patent Application:
Transmitter and signal processing method
Industry Class:
Miscellaneous active electrical nonlinear devices, circuits, and systems
Thank you for viewing the Double patterning compatible colorless m1 route patent info.
- - -

Results in 0.37461 seconds


Other interesting Freshpatents.com categories:
Computers:  Graphics I/O Processors Dyn. Storage Static Storage Printers

###

Data source: patent applications published in the public domain by the United States Patent and Trademark Office (USPTO). Information published here is for research/educational purposes only. FreshPatents is not affiliated with the USPTO, assignee companies, inventors, law firms or other assignees. Patent applications, documents and images may contain trademarks of the respective companies/authors. FreshPatents is not responsible for the accuracy, validity or otherwise contents of these public document patent application filings. When possible a complete PDF is provided, however, in some cases the presented document/images is an abstract or sampling of the full patent application for display purposes. FreshPatents.com Terms/Support
-g2-0.1766

66.232.115.224
Browse patents:
Next
Prev

stats Patent Info
Application #
US 20140097892 A1
Publish Date
04/10/2014
Document #
File Date
12/31/1969
USPTO Class
Other USPTO Classes
International Class
/
Drawings
0


Cells Designs

Follow us on Twitter
twitter icon@FreshPatents

Globalfoundries Inc.


Browse recent Globalfoundries Inc. patents





Browse patents:
Next
Prev
20140410|20140097892|double patterning compatible colorless m1 route|A method for enabling functionality in circuit designs utilizing colorless DPT M1 route placement that maintains high routing efficiency and guarantees M1 decomposability of a target pattern and the resulting circuit are disclosed. Embodiments include: determining a boundary abutting first and second cells in an IC; determining a side of |Globalfoundries-Inc