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Junction barrier schottky diodes with current surge capability

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Junction barrier schottky diodes with current surge capability


An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.
Related Terms: Silicon Diode Electronic Device Silicon Carbide

Browse recent Cree, Inc. patents - Durham, NC, US
USPTO Applicaton #: #20140077228 - Class: 257 77 (USPTO) -
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Specified Wide Band Gap (1.5ev) Semiconductor Material Other Than Gaasp Or Gaalas >Diamond Or Silicon Carbide

Inventors: Qingchun Zhang, Sei-hyung Ryu

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The Patent Description & Claims data below is from USPTO Patent Application 20140077228, Junction barrier schottky diodes with current surge capability.

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CLAIM OF PRIORITY

The present application is a continuation of U.S. patent application Ser. No. 13/547,014, entitled JUNCTION BARRIER SCHOTTKY DIODES WITH CURRENT SURGE CAPABILITY, which was filed Jul. 11, 2012, which was a continuation of U.S. Pat. No. 8,232,558, entitled JUNCTION BARRIER SCHOTTKY DIODES WITH CURRENT SURGE CAPABILITY, which issued on Jul. 31, 2012, the disclosure of which is hereby incorporated herein by reference as if set forth fully.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and the fabrication of semiconductor devices and more particularly, to Junction Barrier Schottky (JBS) diodes, and the fabrication of such diodes.

BACKGROUND

High voltage silicon carbide (SiC) Schottky diodes, which may have voltage blocking ratings between, for example, about 600V and about 2.5 kV, are expected to compete with silicon PIN diodes having similar voltage ratings. Such diodes may handle as much as about 100 amps or more of forward current, depending on their active area design. High voltage Schottky diodes have a number of important applications, particularly in the field of power conditioning, distribution and control.

An important characteristic of a SiC Schottky diode in such applications is its switching speed. Silicon-based PIN devices typically exhibit relatively poor switching speeds. A silicon PIN diode may have a maximum switching speed of approximately 20 kHz, depending on its voltage rating. In contrast, silicon carbide-based Schottky devices are theoretically capable of much higher switching speeds, for example, in excess of about 100 times better than silicon. In addition, silicon carbide devices may be capable of handling a higher current density than silicon devices.

A conventional SiC Schottky diode structure has an n-type SiC substrate on which an n− epitaxial layer, which functions as a drift region, is formed. The device typically includes a Schottky contact formed directly on the n− layer. A junction termination region, such as a guard ring and/or p-type JTE (junction termination extension) region, is typically formed to surround the Schottky junction active region.

The purpose of junction termination region is to reduce or prevent electric field crowding at the edges of the Schottky junction, and to reduce or prevent the depletion region from interacting with the surface of the device. Surface effects may cause the depletion region to spread unevenly, which may adversely affect the breakdown voltage of the device. Other termination techniques include field plates and floating field rings that may be more strongly influenced by surface effects. A channel stop region may also be formed by implantation of n-type dopants in order to prevent the depletion region from extending to the edge of the device.

Regardless of the type of termination used, the Schottky diode will typically fail if a large enough reverse voltage is applied to the junction. Such failures are generally catastrophic, and may damage or destroy the device. Furthermore, even before the junction has failed, a Schottky diode may experience large reverse leakage currents. In order to reduce such leakage currents, the junction barrier Schottky (JBS) diode was developed. JBS diodes are sometimes referred to as Merged PIN—Schottky (MPS) diodes. A conventional JBS diode 10 is illustrated in FIG. 1. As shown therein, a conventional JBS diode includes an n-type substrate 12 on which an n− drift layer 14 is formed. A plurality of p+ regions 16 are formed, typically by ion implantation, in the surface of the n− drift layer 14. A metal anode contact 18 is formed on the surface of the n− drift layer 14 in contact with both the n− drift layer 14 and the p+ regions 16. The anode contact 18 forms a Schottky junction with the exposed portions of the drift layer 14, and may form an ohmic contact with the p+ regions 16. A cathode contact 20 is formed on the substrate 12. Silicon carbide-based JBS diodes are described, for example, in U.S. Pat. Nos. 6,104,043 and 6,524,900.

In forward operation, the junction J1 between the anode contact 18 and the drift layer 14 turns on before the junction J2 between the p+ regions 16 and the drift layer 14. Thus, at low forward voltages, the device exhibits Schottky diode behavior. That is, current transport in the device is dominated by majority carriers (electrons) injected across the Schottky junction J1 at low forward voltages. As there may be no minority carrier injection (and thus no minority charge storage) in the device at normal operating voltages, JBS diodes have fast switching speeds characteristic of Schottky diodes.

Under reverse bias conditions, however, the depletion regions formed by the PN junctions J2 between the p+ regions 16 and the drift layer 14 expand to block reverse current through the device 10, protecting the Schottky junction J1 and limiting reverse leakage current in the device 10. Thus, in reverse bias, the JBS diode 10 behaves like a PIN diode. The voltage blocking ability of the device 10 is typically determined by the thickness and doping of the drift layer 14 and the design of the edge termination.

One problem commonly encountered with silicon carbide JBS diodes is their ability to handle current surges. Silicon carbide JBS Schottky diodes are typically designed for use in power switching applications, such as power factor control (PFC) in high voltage distribution systems. In such applications, surge currents can be experienced during power on and/or after line cycle dropouts. When a current surge occurs, substantial power can be dissipated in the diode, which can result in catastrophic failure of the device due to thermal runaway.

A JBS Schottky diode can be designed so that the the junction J2 between the p+ regions 16 and the drift layer 14 turns on under high current conditions, resulting in an injection of miority carriers (holes) across the junction J2 into the drift layer 14. This injection of minority carriers modulates the conductivity of the drift layer 14, reducing the resistance to current and therefore reducing the potential for failure of the device as a result of the current surge. However, designing the p+ regions 16 so that the junction J2 turns on at high currents can undesirably increase the on-state resistance of the device at lower currents.

SUMMARY

An electronic device according to some embodiments includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first width and a first spacing between adjacent ones of the JBS regions. The device further includes a surge protection region at the surface of the drift region adjacent the Schottky contact. The surge protection region has a second width greater than the first width and includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a third width less than the first width and has a second spacing between adjacent ones of the surge protection subregions that may be less than the first spacing between adjacent ones of the JBS regions.

The first spacing may be about 4 μm to about 6 μm and the second spacing may be about 1 μm to about 3 μm. The first width may be about 1 μm to about 3 μm and the third width may be about 1 μm to about 3 μm.

The surge protection subregions may extend into the drift layer from the surface of the drift layer by a depth of about 0.3 μm to about 0.5 μm. A doping level of the drift region may be about 5×1014 cm−3 to about 1×1016 cm−3.

The first spacing, the second spacing and the third width are configured such that a voltage drop from a surface of the drift layer to a center of a junction between one of the surge protection subregions and the drift region may be sufficient to cause the junction to become forward biased at a forward current that is higher than a rated current of the Schottky diode so as to provide a current surge handling ability in the Schottky diode.

An interface between the Schottky contact and the surge protection subregions may be an ohmic contact.

The drift layer may include 4H-SiC. The drift layer may have a doping level of about 5×1015 cm−3 to 1 1016 cm−3, and the current surge control subregions may have a doping level greater than 5×1018 cm−3.

A portion of the drift region beneath the surge protection regions may have a higher electric potential than a portion of the drift region beneath the JBS regions in response to a forward voltage applied to the Schottky contact.

The device may further include a plurality of current surge control regions in the drift layer adjacent the Schottky contact.

The first conductivity type may include n-type and the second conductivity type may include p-type.

The surge control subregions include a plurality of trenches in the drift region and a plurality of doped regions in the drift layer extending beneath respective ones of the plurality of trenches.

The surge protection subregions may define vertical current paths in the drift region between respective ones of the surge protection subregions, a depth of the surge protection regions may be defined by a depth of the trenches and a depth of the doped regions.

Methods of forming a Schottky diode according to some embodiments include forming a plurality of junction barrier Schottky (JBS) regions at a surface of a silicon carbide drift region having a first conductivity type, the plurality of JBS regions having a second conductivity type opposite the first conductivity type and having a first spacing between adjacent ones of the JBS regions. The methods further include forming a surge protection region at the surface of the drift region adjacent the Schottky contact, the surge protection region including a plurality of surge protection subregions having the second conductivity type and each of the surge protection subregions having a second spacing between adjacent ones of the surge protection subregions that may be less than the first spacing between adjacent ones of the JBS regions. A Schottky contact is formed on the drift region.

The first spacing may be about 4 μm to about 6 μm and the second spacing may be about 1 μm to about 3 μm.

Forming the plurality of JBS regions and forming the surge protection region may include selectively implanting dopant ions of the second conductivity into the drift layer, and annealing the implanted ions at a temperature greater than 1700° C.

The methods may further include forming a graphite coating on the drift layer including the implanted ions, annealing the implanted ions may include annealing the graphite coating.

The methods may further include etching a plurality of trenches in the drift layer before implanting the ions, implanting the ions may include implanting the ions into the plurality of trenches.

Forming the Schottky contact on the drift region may include forming the Schottky contact to the drift region and an ohmic contact to the surge protection subregions using a single metal.

An electronic device according to further embodiments includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The plurality of JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate certain embodiment(s) of the invention. In the drawings:

FIG. 1 is a cross-sectional view of a conventional JBS diode.

FIG. 2 is a top view of a JBS diode including surge protection regions.

FIG. 3 is a cross-sectional view of a JBS diode including a surge protection region.

FIG. 4 is a cross-sectional view of a JBS diode according to some embodiments.

FIG. 5 is a detail view illustrating additional aspects of the JBS diode of FIG. 4.

FIG. 6 is a cross-sectional view of an intermediate structure formed during fabrication of a JBS diode according to some embodiments.

FIG. 7A is a cross-sectional view of an intermediate structure formed during fabrication of a JBS diode according to further embodiments.

FIG. 7B is a cross-sectional view of a JBS diode according to further embodiments.

FIG. 8A illustrates a simulated device structure and simulation results for a device according to some embodiments.

FIG. 8B illustrates a simulated device structure and simulation results for a comparison device.

FIG. 9 illustrates simulated current versus voltage characteristics for a device according to some embodiments.

FIG. 10 illustrates simulated hole concentration characteristics for a device according to some embodiments.

FIG. 11 illustrates simulated voltage potential characteristics for a device according to some embodiments.

FIG. 12 illustrates an implantation mask pattern that can be used according to some embodiments.

DETAILED DESCRIPTION

OF EMBODIMENTS OF THE INVENTION

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stats Patent Info
Application #
US 20140077228 A1
Publish Date
03/20/2014
Document #
14087416
File Date
11/22/2013
USPTO Class
257 77
Other USPTO Classes
International Class
/
Drawings
8


Silicon
Diode
Electronic Device
Silicon Carbide


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