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Semiconductor device with resistance circuit

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Semiconductor device with resistance circuit


A semiconductor device has a resistance circuit including a resistance element as a first thin film arranged on an isolation oxide film provided on a surface of a semiconductor substrate, a second thin film comprised of silicon nitride formed on the first thin film, an intermediate insulating film formed on the second thin film, a contact hole passing through the second thin film, and a metal wiring formed on the contract hole. The first thin film has a low concentration impurity region and a high concentration impurity region at each of both ends of the low concentration impurity region. The second thin film is formed on the first thin film so as to be disposed on each of the high concentration impurity regions but not on the low concentration impurity region. An insulated gate field effect transistor is provided in a region of the semiconductor substrate surrounded by the isolation oxide film.
Related Terms: Semiconductor Semiconductor Device Silicon Field Effect Transistor High Concentration Semiconductor Substrate Silicon Nitride

Browse recent Seiko Instruments Inc. patents - Chiba, JP
USPTO Applicaton #: #20140054719 - Class: 257380 (USPTO) -
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device >Having Insulated Electrode (e.g., Mosfet, Mos Diode) >Insulated Gate Field Effect Transistor In Integrated Circuit >Combined With Passive Components (e.g., Resistors) >Polysilicon Resistor

Inventors: Hirofumi Harada

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The Patent Description & Claims data below is from USPTO Patent Application 20140054719, Semiconductor device with resistance circuit.

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having a semiconductor integrated circuit with a resistance circuit formed on the same semiconductor substrate.

2. Description of the Related Art

In a semiconductor integrated circuit, the following types of resistors are used: a diffused resistor made from a monocrystalline silicon semiconductor substrate into which impurities of a conductivity type opposite to that of the semiconductor substrate are introduced, and a polycrystalline silicon resistor made of polycrystalline silicon into which impurities are introduced.

A sectional view in which a resistance element used for a conventional resistance circuit and an insulated gate field effect transistor (hereinafter, abbreviated to MISFET) are combined is shown in FIG. 2.

A MISFET 102 includes a thin gate oxide film 3, source and drain regions 4, and a gate electrode 5. The MISFET 102 is surrounded by a thick isolation oxide film 2. On those films, an intermediate insulating film 8 is formed, and electrical connection is achieved by metal wiring 10 via contact holes 9.

Further, a resistance element 101 is formed of a polycrystalline silicon film deposited on the flat and thick isolation oxide film 2.

In the polycrystalline silicon film forming the resistance element, there are formed high concentration impurity regions 6 at both ends of the polycrystalline silicon film and a low concentration impurity region 7 sandwiched between the high concentration impurity regions 6. The resistance value of the resistance element is determined depending on a resistivity, which is determined depending on the impurity concentration of the low concentration impurity region 7 having high resistance, and the length and the width of the low concentration impurity region 7. The high concentration impurity regions 6 are used for obtaining ohmic contact with respect to the metal wiring.

The intermediate insulating film 8 is formed on the resistance element 101, and electrical connection is achieved by the metal wiring 10 via the contact holes 9. In the resistance circuit used for the semiconductor integrated circuit, a plurality of the resistance elements of FIG. 2 are formed on the same substrate surface so as to be connected in series or in parallel to one another via the metal wiring.

The intermediate insulating film 8 formed on the MISFET 102 and the resistance element 101 contains boron or phosphorus, and is flattened through thermal treatment of 850° C. or higher. Thus, the difference in height in the semiconductor integrated circuit caused by the film patterns is reduced. Further, after the metal wiring is formed, a silicon nitride passivation film 11 is provided thereon as a protective film.

The contact holes provided in the flattened intermediate insulating film 8 as described above have depths that differ depending on the underlying structures. In the example described above, since parts of the intermediate insulating film provided on the source and the drain in the semiconductor substrate are the thickest, and a part of the intermediate insulating film provided on the resistance element is the thinnest, the contact holes for the source and the drain are the deepest, and the contact holes for the resistance element are the shallowest when the contact holes are formed in the respective parts.

When the contact holes with two depths are formed simultaneously, the contact holes for the resistance element, on which the thin intermediate insulating film is provided, are finished first, and hence until the contact holes for the source and the drain are completely made, excessive over-etching is performed on the contact holes for the resistance element. Accordingly it is necessary to set the thickness of the polycrystalline silicon film to be thick enough to prevent the contact hole from passing through the resistance element during the over-etching, or it is necessary to ensure the resistance to etching.

As a method for solving the above-mentioned problem, for example, such methods illustrated in FIGS. 3 and 4 are proposed.

In FIG. 3, in order to improve the strength to the over-etching, the contact hole 9 for connection with the metal wiring 10 is formed on a thick polycrystalline silicon film 16. Meanwhile, the resistance element main body 7 is formed of a thin polycrystalline silicon film, and the thick polycrystalline silicon film and the thin polycrystalline silicon film are connected to each other through via holes 13 provided separately from the contact hole 9 for connection with the metal wiring 10.

Further, in FIG. 4, the corresponding part to the thick polycrystalline silicon film in FIG. 3 is replaced by an impurity diffusion region 17 formed in the semiconductor substrate. Then, similar to the case of FIG. 3, the resistance element main body is formed of a thin polycrystalline silicon film, and the impurity diffusion regions and the thin polycrystalline silicon are connected to each other through via holes 13 provided separately from the contact holes 9 for connection with the metal wiring.

Such method of providing a polycrystalline silicon resistor is disclosed in, for example, Japanese Published Patent Application H09-051072.

As for manufacturing the conventional resistance element, the following problems arise.

For example, when the polycrystalline silicon resistor is employed, in order to aim for improvement in accuracy of the resistance value or increase in resistance value, the reduction of the thickness of the polycrystalline silicon film is aimed for in some cases. Particularly in recent years, along with advancement of devices and improvement in controllability of the thickness of the film to be deposited, it has become easier to realize a thin film. However, as described above, thin films have a problem of resistance to over-etching, and hence it has been difficult to utilize a resistance element formed of a thin film of 500 Å or smaller in the semiconductor integrated circuit.

In order to realize a resistance element formed of a thin film with a method other than those illustrated in FIGS. 3 and 4, there is a method of forming the resistance element by performing photomasking steps and etching steps separately for respective contacts. However, this method has a problem of causing increase in cost due to addition of the masking step. Further, when the contact holes having one depth are formed after the contact holes having another depth are formed, it is necessary to perform the photolithography process while the contact holes formed earlier are opened, which may cause contamination and adhesion of foreign matters and reduce the quality.

SUMMARY

OF THE INVENTION

In order to solve the above-mentioned problems, the present invention employs the following measures.

That is, a semiconductor device includes a resistance circuit including: a resistance element formed of a first thin film; a second thin film formed on the resistance element; an intermediate insulating film formed on the second thin film; a contact hole for the resistance element, the contact hole passing through the second thin film and being provided in the intermediate insulating film at a depth reaching the first thin film; and a metal wiring formed on the contact hole.

Alternatively, in the semiconductor device including the resistance circuit, the second thin film is formed on the first thin film and has the same shape in plan view as the resistance element formed of the first thin film.

Alternatively, in the semiconductor device including the resistance circuit, the second thin film is formed on the first thin film and is formed in separated regions each including the contact hole.

Alternatively, in the semiconductor device including the resistance circuit, the second thin film is formed on the first thin film and is formed in a region including the resistance element formed of the first thin film, the region being wider than the resistance element.

Further, in the semiconductor device including the resistance circuit, the first thin film has a thickness of 500 Å or smaller.

Further, in the semiconductor device including the resistance circuit: the first thin film is a first polycrystalline silicon film; and the first polycrystalline silicon film contains impurities of a first conductivity type at an impurity concentration in a range of 1×1015 atoms/cm3 to 5×1019 atoms/cm3.

Alternatively, in the semiconductor device including the resistance circuit, the first thin film is a thin film made of one of CrSi, CrSiN, CrSiO, NiCr, and TiN.

Alternatively, in the semiconductor device including the resistance circuit, the second thin film is a second polycrystalline silicon film containing impurities of a second conductivity type, which is opposite to the first conductivity type of the first polycrystalline silicon film.

Alternatively, in the semiconductor device including the resistance circuit, the second thin film is a second polycrystalline silicon film which does not contain impurities.

Alternatively, in the semiconductor device including the resistance circuit, the second thin film is a silicon nitride film.

Further, in the semiconductor device including the resistance circuit, the second thin film has a thickness in a range of 150 Å to 350 Å.

According to the present invention, it is possible to provide a semiconductor device formed of a semiconductor integrated circuit having a built-in resistance element with high accuracy and high resistance since it becomes easier to form a thin film of 500 Å or smaller for the resistance element.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a schematic sectional view illustrating a resistance element and a MISFET according to a first embodiment of the present invention;

FIG. 2 is a schematic sectional view illustrating a conventional resistance element and a conventional MISFET;

FIG. 3 is a schematic sectional view of a conventional resistance element;

FIG. 4 is a schematic sectional view of a conventional resistance element;

FIGS. 5A to 5C are sectional views illustrating a process flow for manufacturing the resistance element and the MISFET according to the first embodiment of the present invention;

FIGS. 6A to 6C are sectional views illustrating the process flow for manufacturing the resistance element and the MISFET according to the first embodiment of the present invention, which follows the process flow illustrated in FIGS. 5A to 5C;

FIG. 7 is a schematic sectional view illustrating a resistance element and a MISFET according to a second embodiment of the present invention;



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stats Patent Info
Application #
US 20140054719 A1
Publish Date
02/27/2014
Document #
14073167
File Date
11/06/2013
USPTO Class
257380
Other USPTO Classes
International Class
01L27/06
Drawings
7


Semiconductor
Semiconductor Device
Silicon
Field Effect Transistor
High Concentration
Semiconductor Substrate
Silicon Nitride


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