CROSS-REFERENCE TO RELATED APPLICATIONS
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This application is a continuation of U.S. application Ser. No. 13/487,762, which issued as U.S. Pat. No. 8,538,002 on Sep. 17, 2013. which is a continuation of U.S. application Ser. No. 12/200,330, which issued as U.S. Pat. No. 8,194,845, which is a continuation of U.S. application Ser. No. 09/805,395, which issued as U.S. Pat. No. 7,421,066, which is a continuation of U.S. application Ser. No. 08/873,215, which issued as U.S. Pat. No. 6,252,944, and which was reissued as RE39,722, which claims benefit of priority to U.S. Provisional Application No. 60/023,749, filed Jun. 12, 1996.
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The present invention relates in general to a telecommunications system.
Referring to FIGS. 2 and 13, there is illustrated a prior art technique for combining telephone and voice mail systems. The dilemma is how to provide communication between the switching system (“PBX”) 200 and the voice mail (“VM”) system 201. Communication with the PBX 200 is typically done through either the CO lines or on the station (extension) side. Since CO lines are more of a precious resource than the station connections, the prior art system shown in FIG. 2 communicates between the voice mail system 201 and the PBX 200 on the station side using connection 202. Connection 202 may be an analog telephone line or via an EKT (electronic key telephone) integrated connection. Alternatively, a proprietary EKT line 204 may be coupled to an analog telephone adapter 205, which uses analog line 203 to couple to voice mail system 201.
Such systems are typically configured by programming the PBX 200 to perform a transfer to an extension that is connected to the voice mail system 201 upon one or more occurrences, such as when the outside call received by the PBX 200 intended for a particular extension receives a busy signal or the extension rings a certain number of times. At this point in time, the call resides within the PBX 200 (step 1301). Next, the PBX 200 transfers the call using a flash-hook and then dialing the extension number (step 1302) pertaining to the voice mail system 201 in order to transfer the call to the voice mail system 201. At this point in time, the call cow resides within the voice mail system 201, which may play a greeting to the incoming call (step 1303). In response to the greeting played by the voice mail system 201, the call may send a signal, which is detected by the voice mail system 201 (step 1304). Thereafter, die voice mail system may record a message received from the call (the incoming call resides in the voice mail system 201; step 1306), or the voice mail system 201 may transfer the call to a desired destination, such as a station extension (the incoming call is now resident within the telephone system 200; step 1305). In-band signaling, a serial connection, etc. may he added to farther improve the system, but it is still configured as two separate systems—a PBX 200 coupled to a separate voice mail system 201.
Another prior art system not shown herein is the use of a personal computer with a voice adapter card inserted therein for interconnecting to a switching system. Again, the same problems arise, since there is a separate voice mail system coupled to a telephone system where software in the personal computer operates the voice mail portion.
BRIEF DESCRIPTION OF THE DRAWINGS
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FIG. 1 illustrates, in block diagram form, components of embodiments of the present invention;
FIG. 2 illustrates a prior art system coupling a switching system and a voice mail system;
FIG. 3 illustrates, in block diagram form, components of a port card implemented within embodiments of the present invention;
FIG. 4 illustrates a flow diagram of a process for recording an incoming call;
FIG. 5 illustrates a flow diagram of a process for implementing a beep timer;
FIG. 6 illustrates a flow diagram for terminating a recording;
FIGS. 7A-7D illustrate a flow diagram implementing interactive help;
FIG. 8 illustrates a flow diagram for implementing context sensitive help;
FIG. 9 illustrates a flow diagram implementing real-time call screening;
FIG. 10 illustrates functions implemented within a signal processing circuit within embodiments of the present invention;
FIG. 11 illustrates an electronic key telephone interface;
FIG. 12 illustrates a loop start CO interface;
FIG. 13 illustrates a prior an process for call processing;
FIG. 14 illustrates an EKT;
FIG. 15 illustrates a process for implementing an auto attendant within embodiments of the present invention; and
FIGS. 16-17 illustrate processes for implementing Quick Groups.
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In the following description, numerous technical details are set forth such as specific word length and specific hardware interfaces, etc. to provide a thorough understanding of embodiments of the present invention. However, it will be obvious to those skilled in the art that embodiments of the present invention may be practiced without such specific details. In other instances, well-known circuits have been shown m block diagram form in order not to obscure embodiments of the present invention in unnecessary detail For the most part, details concerning timing considerations and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of embodiments of the present invention and are within the skills of persons of ordinary skill in the relevant art.
The use of the word “a” or “air” when used in conjunction with the term “comprising” in the claims and/or the specification may mean “one,” but it is also consistent with the meaning of “one or more, ”“at least one,” and “one or more than one.” The use of the term “or” in the claims is used to mean “and/or” unless explicitly indicated to refer to alternatives only or the alternatives are mutually exclusive, although the disclosure supports a definition that refers to only alternatives and “and/or.” Throughout this application, the terms “about” or “approximately” are used to indicate that a value includes the inherent variation of error for the device, the method being employed to determine the value, or the variation that exists among the study subjects.
As used in this specification and claim(s), the words “comprising” (and any form of comprising, such as “comprise” and “comprises”), “having” (and any form of having, such as “have” and “has”), “including” (and any form of including, such as “includes” and “include”), and “containing” (and any form of containing, such as “contains” and “contain”) are inclusive or open-ended and do not exclude additional, unrecited elements or method steps.
The term “or combinations thereof” as used, herein refers to all permutations and combinations of the listed items preceding the term. For example, “A, B, C, or combinations thereof” is intended to include at least one of: A, B, C, AB, AC, BC, or ABC, and if order is important in a particular context, also BA, CA, CB, CBA, BCA, ACB, BAC, or CAB. Continuing with this example, expressly included are combinations that contain repeats of one or more item or term, such as BB, AAA, MB, BBC, AAABCCCC, CBBAAA, CABABB, and so forth. The skilled artisan will understand that typically there is no limit on the number of items or terms in any combination, unless otherwise apparent from the context.
While the hardware and methods of this invention have been described in terms of described embodiments, it will be apparent to those of skill in the art that variations may be applied to the hardware and/or methods and in the steps or in the sequence of steps of the methods described herein without departing from the concept, spirit, and scope of the invention.
Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
Referring to FIG. 1, there is illustrated, in block diagram form, system 100 for integrating call processing and voice processing using a single processing means, which in this example is a microprocessor 101. Microprocessor 101, which may be a Motorola 68000 class microprocessor, communicates with hard disk 107 using driver circuitry 108. Hard disk 107 may store program data, voice prompts, voice mail messages, and all other types of speech used within system 100.
Microprocessor 101 may also include a watchdog timer 109 and real-time clock source 110.
Microprocessor 101 may be coupled via bus 105 to flash memory 111 and dynamic random access memory (“DRAM”) 112. Flash memory 111 may be used to store bootstrap data for use during power up of system 100. DRAM 112 may store a program accessed by microprocessor 101 during operation of system 100.
Bus 105 also couples microprocessor 101 to signal processing circuitry, which may be a digital signal processor (“DSP”) 102. Digital signal processor (“DSP”) 102 may implement a number of functions traditionally implemented by discrete analog components.
Referring next to FIG. 10, there are illustrated some functions that may be
implemented in DSP 102. DTMF receivers 1001 may be implemented using frequency domain filtering techniques. DTMF receivers 1001 may detect standard DTMF (touch-tone) signals or digits.
Automatic gain control (“AGC”) 1002 may be a closed-loop gain control system, which normalizes received audio levels during recording.
Recording buffers 1003, which are coupled to AGC 1002, may receive and store speech samples after they have passed through AGC block 1002. These speech samples may be converted to μ-law PCM (Pulse Code Modulation) and double buffered (several samples per buffer). Microprocessor 101 may copy the record data out of DSP buffers 1003 into RAM buffers (not shown), which may be located in the microprocessor 101 data RAM area.
Fax tone detector 1004 may be implemented using frequency domain filtering techniques. Fax tone detector 1004 may detect a standard 1100 Hz FAX CNG tone (also referred to as the Calling Tone).
Caller ID modems 1005 may be 1200 band FSK modems similar to Bell 202-type modems. Caller ID modems 1005 may be implemented as a frequency discriminator where a time delayed (e.g., quadrature) signal is multiplied by the original signal, low pass filtered, then sliced, which produce the square wave caller ID data stream.
Call processing tone generators 3007 may be free running oscillators, which generate the appropriate tones (and tone pairs) that make up industry standard call processing tones. These tones may include dial tone, busy/reorder tone, ring back tone, single frequency (440 Hz) tone, and DTMF dialer tones.
Play buffers 1008 may replay data from hard disk 107 through microprocessor 101 and place this play data in buffers 1008. This data may be converted from an 8-bit μ-law PCM signal to 14-bit linear data.
Conference bridges 1006 may allow multiple conference bridges to mix together conferees into a multi-party conference. These conferees may be a mixture of inside and outside parties. A combination of “loudest speaker” and “summing” may be utilized.
DSP 102 may communicate with microprocessor 101 via a host interface port (“HIP”) via bus 105. The HIP link may support a command-based protocol which may be used to directly read or write DSP memory locations. DSP 102 may be a RAM-based part and may have its program downloaded from microprocessor 101. Once downloaded and running, microprocessor 101 (the host) may poll, for events or receive interrupts indicating that data is available. DSP 102 speech connections may be made over an industry standard 32-time slot, 2.048 megabits per second. (Mb/s) digital serial link 124. Link 124 may occupy one of the digital highways implemented by digital cross-point matrix 103. Each service of DSP 102 may occupy a single time slot. For example, DTMF receiver 1001 may occupy time slot 0 while conference bridge circuit 12 may occupy time slot 31.
Digital cross-point matrix 103 may also be coupled to bus 105 and operate to connect any voice path to any other voice path. Digital cross-point matrix 103 may be a VLSI (Very Large Scale Integration) integrated circuit. An example of digital cross-point matrix 103 is manufactured by MITEL Semiconductor Corporation as part No. 8980. Digital cross-point matrix 103 may communicate with microprocessor 101 via a memory mapped input/output (“I/O”) scheme. A command/control protocol may be used for communication between microprocessor 101 and digital cross-point matrix 103 via bus 105. Cross-point matrix 103 may be coupled by highway 124 to DSP 102. Cross-point matrix 103 may be coupled by connection 325 to highway 121. Cross-point matrix 103 may also be coupled to peripheral cards by highways 122 and 123. The peripheral cards are described in further detail below with respect to FIG. 3.
Connections 121-125 are also referred to herein as “highways,” which may be transmission links using time-division multiplexing (“TDM”) as a means for transmitting and receiving data.
Digital cross-point matrix 103 may be capable of making 256 simultaneous fully non-blocking connections within system 100. However, system 100 may be upgraded by adding additional DSPs and/or cross-point matrices.
Cross-point matrix 103 may make connections using the TDM highway by receiving instructions from microprocessor 1.01 to interconnect channels within the frames of the TDM bit stream. This results in the non-blocking capability of cross-point matrix 103, and also allows for a single voice resource, caller, or voice message to be simultaneously coupled to multiple other voice resources, station or CO originated callers, and/or voice messages.
Gate array 104 may be an SRAM (Static Random Access Memory) based device. An example of gate array 104 is manufactured by XILINX. Gate array 104 may be responsible for generating system timing. A master clock signal may be provided by microprocessor 101 at 16.384 MHz. This clock signal may be divided down to provide a number of phase coherent system clocks such as 4.096 MHz, 2.048 MHz, and 8 KHz (frame sync). In addition, a 5-bit time slot counter may be implemented, which allows all the system CODECs to detect the appropriate time slot to use (e.g., 0-31). An additional divider chain may be included to divide the system clock down to 20 Hz, which may be used by the ringing generator power supply (not shown).
Gate array 104 may be downloaded at boot-up by system software. Gate array 104 may be based on a SRAM architecture. That is, the internal fusible links commonly found in programmable logic may be actually stored in volatile SRAM. Because of this architecture, gate array 104 may be downloaded after power-up. Also, note the added flexibility of being able to modify the logic by simply loading new system software.
Bus 105 may also be coupled to modem 106, which may provide a capability of calling into system 100 on a remote basis to load additional programs, voice prompts, etc., or updates thereto, into hard disk 107. Modem 106 may be coupled to coder/decoder (“CODEC”) 113, which may be coupled to highway 121. This connection may allow coupling of modem 106 through cross-point matrix 103 to CO lines through highway 122 and the p-card described below with respect to FIG. 3.
Highway 121 may also be coupled to a dual subscriber line access chip 114, which is well-known in the art, and which may be coupled to analog ports 115 and 116, which may provide an ability for system 100 to communicate to analog-type connections such as cordless telephones and fax machines.
Highway 121 may also be coupled to CODEC 117, which may be coupled to transformer 118 to a music source 119, which may provide an ability to couple an external music source to a received call through cross-point matrix 103 for such things as providing the received call with music on hold.
Power to system 100 may be provided through switching power supply 120, which may convert AC to the various DC supply voltages needed by circuitry within system 100.
Referring next to FIG. 3, there is illustrated peripheral-card (“p-card”) 300, which may be coupled to main board 190 of system 100. Main board 190 may communicate with p-card 300 via a multi-drop async serial link 307. This connection 307 may be made directly to microprocessor 101 (via butlers not shown). P-card 300 may provide interconnections between CO lines and extension lines to system 100.
Microcontroller 301 may be an 8-bit microcontroller, an example of which is manufactured by Hitachi as Part No. H8, which may control all the real-time functions associated with p-card 300. Microcontroller 301 may be responsible for all low-level communication with the EKTs 1400 (electronic key telephones) (see FIG. 14) and CO lines. A low-level event is an event which is specific to the hardware and is required to be handled in real-time. These events may be unique to the EKT or CO trunk protocol. In contrast, high-level events can be abstracted to have no correlation to actual hardware. An example of a high-level event might be “Turn the SPKR LED On.” The corresponding low-level event would be “Send HEX Code 21 to EKT Address 4.” This level of abstraction helps stabilize the complex system software. Another example would be that system software can send a command to seize a CO trunk without being concerned with the low-level differences between a ground start or DID trunk. Some of the low-level tasks may include updating EKT LEDs and LCD displays, decoding key press messages from the EKTs 1400, scanning the CO status bits, and filtering RING and CO seizure events.
Microcontroller 301 may convert these low-level real-time events to high-level events, which may form a protocol referred to as the ESi Command Language (“ECL”). This ECL protocol may be implemented on multi-drop async serial channel 307 between main board 190 and all p-cards 300 in system 100. Microcontroller 301 may contain 2 async serial ports. One of these serial ports may be connected to main board 190, and the other port drives data transceiver and multiplexer 302.
When p-card 300 is plugged into main board 190 (e.g., via ribbon cable (not shown)) a card address is assigned to p-card 300. This card address may be read by microcontroller 301 and used to filter commands over communication link 307. When main board 190 software wants to communicate with the specific p-card 300, the address may be sent in a message packet, which all p-cards 300 receive. P-cards 300 may match the address in the message to the hard wired address on the ribbon cable. If a match is made, that p-card 300 responds to the command set.
Microcontroller 301 may contain an internal program memory (not shown), and may be connected to an external SRAM 303. The internal program memory may contain a bootstrap program, which upon reset or power-up, may request a fresh firmware load from main board 190. This firmware load may be transferred to SRAM 303. Upon download completion, the program may be run from within SRAM 303. This scheme may allow for microcontroller 301 -firmware to be updated and loaded at any time.
Main board 190 may source all system timing through block 304. Timing signals to p-card 300 may include a 2.048 MHz clock signal, an 8 KHz frame sync, which may signify the first time slot of a 32 time slot highway, and 5 time slot counter bits, which may represent a binary count from 0 to 31.
As mentioned above, p-card 300 may be assigned a card slot address when it is connected to main board 190. This card slot address may be used to calculate which time slots p-card 300 should be using. The time slots used for the CO CODECS 1204 (see FIG. 12) may be generated by time slot assignment circuitry contained in the DSLAC chip. There may be two separate 2.048 MHz (32 time slot) highways 122 and 123 that run between main board 190 and p-card 300. One (123) may be for the EKTs 1400 and the other (122) may be for the COs.
Referring to FIGS. 3 and 11, EKT interface 306 describes a connection between system 100 and electronic key telephone (“EKT”) 1400. This interlace may include two physical pairs of wires running between system 100 (often referred to as a Key System Unit (“KSU”)) and EKT 1400. One of these pairs may support an analog bi-directional audio path, and the other may support a bi-directional digital control channel.
EKT 1400 may be connected to the KSU via transformers 1101 and 1102, providing a high degree of isolation as well as longitudinal balance. Transformer 1101 may be for the audio path, and transformer 1102 may be for the data path on each end of the connection. Power may be supplied to EKT 1400 by phantoming the power through the center taps of transformers 1101 and 1102. The KSU may supply a nominal voltage of 36 volts DC, which may pass through a positive temperature co-efficient varistor (“PTC”) 1103. PTC 1103 may act as a resettable fuse, which may become very resistive during excessive current flow (such as when a short in the station wiring occurs). EKT 1400 may regulate down to +12 and +5 volts.
The audio path may be a dry analog bi-directional path including a traditional hybrid (2:4 wire converters) on each end. The audio path on p-card 300 may be converted to a 4-wire path by the hybrid circuit in interface 306. The separate transmit and receive paths may be gain adjusted and connected to CODEC 1104. CODEC 1104 may convert the analog signals to digital and may present these voice signals to EKT highway 123. EKT highway 123 may include a 2.048 Mb/s serial stream, which may be divided into 32 64 Kb/s time slots. Each CODEC 1104 may occupy one time slot on highway 123. System 100 may reserve two time slots per EKT 1400 for future migration to a fully digital 2B+D EKT where two 64 Kb/s digital channels may be available to each station instrument.
Timing for CODECs 1104 may be supplied by time slot generation block 304, which may be coupled to the time slot counter output from system timing block 104 (see FIG. 1).
The EKT data may be produced by a UART (Universal Asynchronous Receiver/Transmitter) in microcontroller 301. This NRZ transmit and receive data may be presented to data transceiver and multiplexer 302. A single data transceiver may be used for all 8 EKT circuits and may be multiplexed through an 8-channel analog mux to each EKT data transformer 1102 in a round-robin fashion.
Messages to EKT 1400 may include commands such as POLL, TURN_ON_LED, WRITE_LCD_CHARACTER, RING PHONE, etc. Response messages from EKT 1400 may include a lower level key command in the first 5 bits and a single hook switch bit in the 8th bit. If the 7th bit of the response message is set, a high level response command such as FIRMWARE_VERSION or TERMINAL_TYPE may be present in the first 5 bits.
Referring next to FIGS. 3 and 12, the loop start central office (“CO”) lines may be supplied by a local telecommunications company and may include a wet balanced differential audio pair. The term “wet” refers to the fact that a voltage (e.g., −48 volts) is present on the pair. System 100 may request dial tone from the CO by providing a nominal 200 ohm loop across the TIP and RING conductors and may release the connection by opening the loop.
The CO may ring system 100 by placing a 90 vrms AC, 20 Hz sine wave on the TIP and RING conductors. System 100 may seize the line by going off hook.
P-card 300 may incorporate a unique circuit, which may monitor the voltage present across TIP and RING of each CO. This line voltage monitor circuit 1202 may serve to detect the ring voltage present during ringing (ring detection) and monitoring the CO line status for conditions, such as whether the CO is plugged in or if someone is off hook in front of system 100. The latter may be used to detect theft of sendee or allow a credit card verification terminal to be used without interfering with normal system operation.
Voltage monitor 1202 may include a balanced differential op-amp connected across TIP and RING of the CO lines through a very high impedance (e.g., >10 Mohms). The output, of the four voltage monitor op-amps may be fed to an analog-to-digital converter with a built-in analog multiplexer (not shown). Microcontroller 301 firmware may monitor the line voltages.
There may also be a balanced differential AC coupled op amp across the CO TIP and RING to monitor the low level audio tones present during caller ID. The output of these op-amps may be selected via an analog switch during the idle period and may be connected to the CO line CODEC 1204.
To correctly terminate the CO line (seizure) care may be taken to satisfy the DC loop requirements (e.g., −200 ohms) and the AC Impedance requirements (e.g., −600 ohms). The classic approach has been to terminate TIP and RING with an inductor (called a holding coil), which has a large inductance (e.g., >1 Hy) and a DC resistance of (e.g., −200 ohms). The inductor separates the AC and DC components to give the desired effect. The problem is that the Inductor must be large enough not to saturate with currents as high as 100 milliamps. An inductor that satisfies these requirements is physically cumbersome.
P-card 300 may incorporate a solid state inductor circuit called a gyrator (not shown) to implement the holding coil function. This single transistor may emulate an inductor with the above requirements while taking up very little PCS space.
A small solid state relay (not. shown) may be used as the hook switch. When energized, the gyrator holding coil may be placed across TIP and RING closing the loop. The audio present on TIP and RING maybe AC coupled to a small dry transformer 1203. The secondary of this transformer 1203 may be connected to the AC termination impedance and to the CODEC 1204, which may be implemented on a dual subscriber line access chip (“DSLAC”).
High voltage protection may be provided for all paths on the TIP and RING connections. These paths may include TIP to RING, TIP to GROUND, RING to GROUND, and TIP and RING to GROUND. This high voltage protection is accomplished by first passing the TIP and RING conductors through positive temperature coefficient varistors (not shown). These varistors may act as resectable fuses. When excessive current flows through these varistors, they become resistive thus limiting the current flow. When the excessive current is stopped, the original resistance is restored.
DSLAC 1204 may include two identical circuits, which may contain the CODEC, DSP-based echo canceller, gain control, and time slot assignment circuit. DSLAC 1204 may be controlled by microcontroller 301 to set parameters such as echo canceller coefficients, gain coefficients, and time slots.
Referring next to FIG. 15, the following is an example of how a. call may be processed by system 100. A call may come in on one of the available central office (“CO”) lines (step 1501), wherein a speech path, for the CO line may be coupled through digital cross-point matrix 103 to an available “play” channel (e.g., play buffer 1008) in DSP 102 (step 1502). Also during set-up, a connection may be made to an available DTMF receiver 1001. A connection may also be made to one of the available fax tone detector channels 1004 in case the incoming call is a facsimile transmission. In step 1503, microprocessor 101 may access hard disk 107 and transfer, speech data to play buffers 1008. Next, in step 1504, a determination may be made whether or not FAX tones have been detected by FAX tone detector 1004. If FAX tones are detected, then in step 1505, microprocessor 101 may instruct digital cross-point matrix 103 to connect the incoming call to one of analog ports 115 or 116 coupled to DSLAC 114. If FAX tones are not detected, then the process may determine whether or not DTMF tones have been detected in step 1506. If yes, then in step 1507, digital cross-point matrix 103 may be instructed to connect the incoming call to an extension coupled to p-card 300. If DTMF tones are not detected, then the process may determine whether nor not a predetermined amount of time has passed in step 1508. If yes, then the call may be terminated by freeing resources in step 1509 and tearing down the call in step 1510 to place the system in an idle state (step 1511).
If the incoming caller dialed an extension and that extension has answered, a speech path connection may be made between the extension and the incoming CO line.
Referring next to FIG. 14, there is illustrated EKT 1400, which may include many of the well-known features of a typical telephone, such as LCD display 1401, soft feature keys 1402 for such features as Station, Speed Dial, Line Keys, etc, speaker/handset volume control 1404, and message and speaker LEDs 1403. Further described in detail below are the program/help key 1407, the record/monitor key 1406, and the voice mail key 1405, which may be part of the fixed feature keys on EKT 1400.
Referring next to FIG. 4, there is illustrated a process for recording all or a portion of an incoming call after it has been connected to an extension (e.g., EKT 1400) (e.g., by digital cross-point matrix 103 and p-card 300). Such a recording can occur while a user is speaking with an incoming call over the extension (e.g., EKT 1400), However, such a recording of the incoming call may occur using any telecommunications device coupled to system 100 if it is supplied with some type of mechanism for initiating the recording process to be discussed. In step 401, the user presses record key 1406 on the extension (e.g., EKT 1400). One skilled in the art will, surely appreciate that any means for activating a record signal may be utilized, such as the depression of a physical button, the touching of a touch screen (display 1401 could utilize such a touch screen), or even voice activation of the record sequence. Such a record sequence activation signal may be transmitted from the extension (e.g., EKT 1400) to interface 306 via transformer 1102 (see FIG. 11), which may pass the signal to microprocessor 101 through data transceiver and multiplexer 302 and microcontroller 301. Next, in step 402, a determination may be made whether or not the extension (e.g., EKT 1400) is connected to a valid call. A valid call may be defined as energy being detected on the line, and the energy is not dial tone. If not, the process may proceed to step 403 to ignore the record activation signal. However, if the extension (e.g., EKT 1400) is connected to a valid call, the process may proceed to step 404 to determine whether or not a record resource is available. This may be accomplished by determining whether or not a recording buffer 1003 is available in DSP 102. If not, the process may proceed to step 405 to display an error message to the telephone extension user. This may be accomplished by some type of visual (e.g., on display 1401 or via an LED on EKT 1400) or audible indication provided by the extension (e.g., EKT 1400). This may be implemented by sending from microprocessor 101 to microcontroller 301 such an error message, which is then transmitted to the extension (e.g., EKT 1400) through data transceiver and multiplexer block 302 and transformer 1102 within interface 306. Next, in step 406, a counter may be incremented to record that a record resource was not available.
If in step 404, a recording buffer 1003 is available (e.g., in DSP 102), such a recording buffer 1003 may be assigned to the record sequence in step 407. Thereafter, in step 408, the recording buffer 1003 may be connected, to the appropriate speech path via highway 124 and digital cross-point matrix 103. As noted above in the discussion regarding digital cross-point matrix 103, digital cross-point matrix 103 may have the ability to couple multiple resources to each other. Therefore, digital cross-point matrix 103 may be able to couple recording buffer 1003 (along with automatic gain control function 1002) to the incoming call, which has previously been connected (and remains connected) to the pertinent extension (e.g., EKT 1400).
Thereafter, in step 409, the recording process begins. In addition to recording the ongoing phone conservation, system 100 may also store the called extension number, the incoming calling telephone number, and the date and time of the call. These data may be stored in a recording record, which may be associated with the actual recording. The recording data record may be written to hard disk 107, and may be available for display when the recording is accessed. At the time the recording begins, a timer may be started to accumulate the duration of the recording. When the call is completed, the duration may be added to the recording data record, and may be written to hard disk 107. When the recording is played back, the incoming caller phone number, the date and time of the recording, and the duration may be displayed (e.g., on display 1401). Next, in step 410, a determination may be made whether or not a beep tone feature has been enabled. If not the process may proceed to step 601 in FIG. 6, However, if a beep tone feature has been enabled, the process may proceed to step 411 to start a beep timer, which may be required by law in certain jurisdictions. Implementation of step 411 is further described below with respect to FIG. 5.
The recording sequence illustrated in FIG. 4 may be implemented as a software program stored within hard disk 107, which may be up-loaded to DRAM 112 for operation by microprocessor 101.
Referring next to FIG. 6, there is illustrated a process for terminating a recording sequence. In step 601, one of the parties (e.g., the incoming call or EKT 1400) may hang up, or the termination of the recording sequence may be initiated by again pressing record key 1406 (deactivation of the recording sequence). In response to one of these signals, in step 602. the recording process may be stopped. Thereafter, in step 603, the recording, which may have been temporarily stored within recording buffer 1003, may be recorded in the mailbox assigned to the extension (e.g., EKT 1400) that initiated the recording sequence. The other data, such as the called and caller telephone numbers, time and date information, and recording duration may also be stored within the extension telephone\'s mailbox. Such a mailbox may be stored within hard disk 107. Thereafter, in step 604, the beep timer may be terminated. Thereafter, in step 605, recording buffer 1003, which may have been assigned to this record sequence, may be freed. Then, in step 606, digital cross-point matrix 103 may disconnect the speech path from recording buffer 1003, and the process may end at step 607.
Referring next to FIG. 5, there is a flow diagram illustrating a process for implementing a beep timer. A beep timer may be provided so that an audible beep is heard by both parties during a conservation that is being recorded. The beep may be heard every 15 seconds, and may have a configurable duration between 40 and 500 milliseconds. In step 501, the beep timer has been enabled. In step 502, a determination may be made whether or not recording buffer 1003 is still connected to the pertinent speech path. If not, the process may proceed to step 503 to terminate the beep timer. However, if recording buffer 1003 is still connected to the speech path (e.g., by digital cross-point matrix 103), the process may proceed to step 504 where the speech path transmit is opened. Next, in step 505, the speech path may be connected to a tone produced by call processing tone generator 1007 by DSP 102. As a result, the tone may be heard by one or both of the incoming call and/or extension user. In step 506, a delay period (e.g., 200 milliseconds) may be allowed to pass. After passage of the delay period, the tone generator 1007 may be disconnected from the speech path in step 507. The beep timer process may be started again in step 508. The process may end step 509. An advantage of the recording sequence is that it can he performed without any interruption in the connection between the call and the extension (e.g., EKT 1400), Additionally, it may be performed with merely the activation of a single signal. However, a sequence of signals may be utilized to initiate the recording sequence, such as the entering of a code (e.g., by the user using the touch-tone keypad on EKT 1400).
Furthermore, the recording sequence may be initiated while a user is screening an incoming call or while a voice message is being placed in the user\'s mailbox. These recordings may be accomplished following the process described in FIG. 4 as was described earlier for recording all or a portion of an incoming call.
Referring next to FIGS. 7A-7D, there is illustrated a flow diagram for implementing an interactive help sequence (e.g., verbal user guide) whereby “help” messages may be provided to a user of system 100. This feature can alleviate the need for the user to possess and access a written help manual. Note, however, that one skilled in the art will appreciate that the process illustrated in FIGS. 7A-7D may be utilized to play or display any type of messages to a user, and not just those associated with a help menu.