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Nand flash memory having multiple cell substrates

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Nand flash memory having multiple cell substrates


A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.

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USPTO Applicaton #: #20140022846 - Class: 36518512 (USPTO) -


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The Patent Description & Claims data below is from USPTO Patent Application 20140022846, Nand flash memory having multiple cell substrates.

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stats Patent Info
Application #
US 20140022846 A1
Publish Date
01/23/2014
Document #
File Date
07/24/2014
USPTO Class
Other USPTO Classes
International Class
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