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Nand flash memory having multiple cell substrates

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20140022846 patent thumbnailZoom

Nand flash memory having multiple cell substrates


A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.
Related Terms: Semiconductor Memory Cell Elective Cells Erase Flash Memory Memory Cells Charge Pump Circuit Flash Memory 구조 Nand Flash

Browse recent Mosaid Technologies Incorporated patents - Ottawa, CA
USPTO Applicaton #: #20140022846 - Class: 36518512 (USPTO) -


Inventors: Jin-ki Kim

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The Patent Description & Claims data below is from USPTO Patent Application 20140022846, Nand flash memory having multiple cell substrates.

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CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 13/073,150, filed on Mar. 28, 2011, which is a continuation of U.S. application Ser. No. 12/143,285, filed on Jun. 20, 2008, now issued as U.S. Pat. No. 7,940,572 on May 10, 2011, which claims the benefit of priority of U.S. Provisional Patent Application No. 61/019,415 filed on Jan. 7, 2008, which are hereby incorporated by reference.

TECHNICAL FIELD

The present invention relates generally to NAND flash memory. More particularly, the present invention relates to erasing NAND flash memory cells.

BACKGROUND

Flash memory is a commonly used type of non-volatile memory in widespread use as storage for consumer electronics and mass storage applications. Flash memory is pervasive in popular consumer products such as digital audio/video players, cell phones and digital cameras, for storing application data and/or media data. Flash memory can further be used as a dedicated storage device, such as a portable flash drive pluggable into a universal serial port (USB) of a personal computer, and a magnetic hard disk drive (HDD) replacement for example. It is well known that flash memory is non-volatile, meaning that it retains stored data in the absence of power, which provides a power savings advantage for the above mentioned consumer products. Flash memory is suited for such applications due to its relatively high density for a given area of its memory array.

FIG. 1A is a general block diagram of typical flash memory device. Flash memory 2 includes well known input and output buffer circuits, such as input/output (I/O) buffer block 3a and control buffer block 3b for receiving external control and data input signals and providing data output signals. The control buffer block 3b receiving the control signals, such as CE# and WE#, may include other basic logic circuits, for implementing rudimentary functions that may be related to control of the data input and buffers for example. Flash memory 2 includes control circuit 3c, for controlling various high level functions of the flash circuits such as read, program and erase operations for example, an address register 4 for storing address information, a data register 5 for storing program data information, a command register 6 for storing command data information, high voltage circuits for generating the required program and erase voltages, and core memory circuits for accessing the memory array 7. Memory array 7 includes flash memory cells, arranged as NAND cell strings for example. The NAND cell strings of a column are coupled to a bitline, which is connected to a page buffer/sense amplifier circuit 8. Sense amplifier circuit 8 senses read data from a selected page of memory cells and provides program data to a selected page of memory cells. One page of memory cells refers to all the memory cells connected to the same wordline. Driving the wordlines is row drivers/decoders, shown as a row address decoder 9a and row address buffer 9b. There can be one or more stages of decoding, and row address buffer 9b can include block decoding logic.

The control circuit 3c includes a command decoder and logic for executing internal flash operations, such as read, program and erase functions. Those skilled in the art will understand that these operations are executed in response to the command data stored in the command register 6, sometimes in combination with the address data and program data stored in the respective address register 4 and data register 5, depending on the operation to be executed. The command data, address data and program data are issued by a memory controller and latched into the corresponding registers by flash memory 2. The functions of the shown circuit blocks of flash memory 2 are well known in the art. Persons skilled in the art will understand that flash memory 2 shown in FIG. 1A represents one possible flash memory configuration amongst many possible configurations. In FIG. 1A, memory array 7, sense amplifier circuit 8, data register 5, row address decoder 9a and row address buffer 9b are part of one memory bank.

FIG. 1B is a floor plan layout a prior art flash memory device to show the area occupied by various circuit blocks. Typically, all the circuit blocks shown in FIG. 1A are formed in the floor plan layout of FIG. 1B. In FIG. 1B, flash memory chip 10 is a semiconductor material rectangular in shape, upon which are formed transistor circuits and structures. Occupying a large proportion of the area are two memory arrays or memory tiles, 12 and 14, which generally correspond to memory array 7 of FIG. 1A. While the present example flash memory 10 includes two memory arrays, alternative designs can include a single memory array or more than two memory arrays. Located between memory arrays 12 and 14 are row decoders 16 that drive wordlines to the required voltage level for read, program and erase operations. Row decoders 16 generally correspond to row address decoder 9a and row address buffer 9b of FIG. 1A. In the example of FIG. 1B, wordlines (not shown) extend in a horizontal direction. Located below each of memory arrays 12 and 14 are page buffers 18 and 20, each being electrically connected to bitlines (not shown) for providing program data and for sensing read data. Page buffers 18 and 20 generally correspond to data register 5 and sense amplifier 8 of FIG. 1A. The combination of memory array 12, row decoders 16 and page buffer 18 is referred to as a memory bank or plane. Similarly, the combination of memory array 14, row decoders 16 and pager buffer 20 is referred to as another memory bank or plane. The page buffers 18 and 20 receive and provide data via data lines (not shown), which are coupled to the input and output (I/O) circuits in logic block 22. Logic block 22 further includes other circuits such as a command decoder and registers. Another large area is dedicated for a charge pump 24, which is responsible for generating high voltages required for programming and erasing data stored in the flash memory cells of the first memory array 12 and the second memory array 14. Charge pump 24 generally corresponds to the high voltage generator of FIG. 1A. The elements of flash memory chip 10 have been generically described, but persons skilled in the art will understand that each of the outlined blocks of FIG. 1B will include all the circuits necessary to achieve proper operation of flash memory chip 10.

In the presently shown example of FIG. 1B, the flash memory chip 10 is designed to have NAND flash memory cells arranged in NAND cell strings within memory arrays 12 and 14. The NAND cell strings are organized into memory blocks, such as Block[1] to Block[n], where n can be any non-zero integer value. The selection of the number of blocks in each array is a design parameter of flash memory chip 10.

FIG. 2 depicts an example memory array of flash memory chip 10 of FIG. 1B. The example illustrated in FIG. 2 has two memory blocks in one memory array. In FIG. 2, one NAND cell string is outlined with a dashed box 30, which includes a string select device 32, flash memory cells 34, and a sourceline select device 36 connected in series between bitline BL1 and common source line CSL. There can be “i” flash memory cells 34 per NAND cell string, where i is a non-zero integer value. Accordingly, wordlines WL1 to WLi are electrically coupled to corresponding gates of the flash memory cells 34. A string select line (SSL) and a source select line (GSL) are electrically coupled to select devices 32 and 36 respectively. In the present example, all the transistors of the NAND cell string 30 are n-channel devices.

A memory block 38, being the same as memory Block[1] of FIG. 1B for example, will include all the NAND cell strings having select devices and flash memory cells connected to the same wordlines, string select line and source select line. The width of memory block 38 is set by the number of bitlines, which in the case of FIG. 2 is “j” bitlines where j is a non-zero integer value. Memory block 40 includes further NAND cell strings connected to bitlines BL1 to BLj. A bitline and the NAND cell strings electrically connected to it is referred to as a column.

All the circuits of flash memory chip 10 of FIG. 1B, including the NAND cell strings shown in FIG. 2 are formed by using well-known semiconductor manufacturing processes. In such processes, transistors of the same type are grouped together and formed in their own well. For example, n-type transistors are formed in a p-type well and p-type transistors are formed in an n-type well. In some cases, only a single well is used, where its type depends on the type of the substrate. In most NAND flash memory devices, all the NAND cell strings in a memory array are formed in one well, which results in disadvantages that are described later on.

FIG. 3 is a cross-sectional diagram of memory array 14 taken along line A-A′ of FIG. 1B, and angled to show specific features on its surface. The cross-sectional structure of the semiconductor substrate where page buffer 20 and logic block 22 are formed is not shown. In FIG. 3, the substrate 50 is a p-type substrate having an n-well 52 and a p-well 54. P-well 54 is formed within n-well 52 such that p-well 54 is spaced from substrate 50. All the NAND cell strings 30 of FIG. 2, and more specifically the transistor devices of NAND cell strings 30, are formed within p-well 54. The well structure shown in FIG. 3 is commonly known as a triple-well structure, or a triple pocket structure. On the surface of p-well 54 are the NAND cell strings 30, simply represented as trapezoid boxes, where each NAND cell string of a column is connected in parallel to a bitline, such as bitline BLk where “k” is a variable representing a logical bitline position less than BLj. With reference to FIG. 2, the bitline is connected to the string select device 32 of each NAND cell string 30. Accordingly, the NAND cell strings that share common select lines and wordlines are part of one memory block. FIG. 3 illustrates four memory blocks 56, 58, 60 and 62 to simply the drawing, however those skilled in the art will understand that there can be any number of memory blocks in memory arrays 12 and 14. Both the n-well 52 and the p-well 54 receives an erase voltage Verase during erase operations, and are both biased to 0V or VSS during all other operations such as program and read for example. Verase can be coupled to n-well 52 and p-well 54 at multiple different locations.

FIG. 4 is a cross section diagram of a NAND cell string 30 of FIG. 3, having the equivalent circuit diagram shown in FIG. 2. Each flash memory cell includes a polysilicon wordline 70 and a polysilicon floating gate 72, where the floating gate 72 is formed over a thin gate oxide 74. On either side of thin gate oxide 74 and formed within p-type well 54 are n-type diffusion regions 76. The sourceline select device 36 includes a polysilicon gate 78 formed over a thick gate oxide 80, and an n-type diffusion region 82 acting as the common source line CSL. Diffusion region 82 is shared with all the NAND cell strings in the memory block, as illustrated in FIG. 2. The string select device 32 includes a polysilicon gate 84 formed over a thick gate oxide 86, and an n-type diffusion region 88 that is electrically connected to a bitline 90.

As is well known in the art, NAND flash memory devices are block erasable, meaning that individual memory blocks can be selectively erased through Fowler-Nordheim (F-N) tunneling, based on a block address or other selection signal. In order to erase a memory block such as memory block 38 of FIG. 2, the wordlines of the selected memory block are biased to 0V, SSL and GSL are floated, and both the n-well 52 and the p-well 54 are biased to Verase. Verase is a high voltage generated by the charge pump 24 of FIG. 1B, and in example flash memory devices is about 20V. Because SSL and GSL are floated during the erase operation, both SSL and GSL are self-boosted when Verase is applied to n-well 52 and p-well 54 due to the capacitive coupling between the wells and SSL and GSL. Depending on the capacitive coupling ratio, GSL and SSL can be boosted to approximately 80% to 90% of Verase. CSL and all bitlines are floated during the erase operation, and eventually self-boost to about Verase-0.6V. Those skilled in the art will understand that the forward bias p-n junction voltage drop across p-well 54 to the n-type diffusion regions 82 and 88. Under these erase bias conditions, trapped electrons (charge) in the floating gate of the flash memory cells are emitted uniformly to the substrate. The threshold voltage (Vth) of the erased flash memory cell becomes negative, meaning that the erased cell will turn on with a gate bias of 0V.

Since the unselected memory blocks reside in the same p-well 54 as the selected memory block, these unselected memory blocks must be inhibited from being erased. A self-boosting erase inhibit scheme described in U.S. Pat. No. 5,473,563 is widely used in NAND flash memory devices to prevent erasure of unselected memory blocks. To prevent erasure of flash memory cells in unselected memory blocks using the self-boosting erase inhibit scheme, all wordlines in unselected memory blocks are floated. Therefore floated wordlines in the unselected memory blocks are boosted to about 90% of Verase when the p-well 54 rises to Verase, by capacitive coupling between the p-well 54 and the wordlines. It should be understood that the final boosted voltage level on the floating wordlines is determined by the coupling ratio between the substrate and wordlines. The boosted voltage of the wordlines in the unselected memory blocks is effective for reducing the electric field between the p-well 54 and the wordlines, thereby minimizing unintended erasure of data stored therein.

Once the erase operation ends, Verase is set to VSS for a block erase verify operation for determining if all the flash memory cells of the selected memory block have been successfully erased. If not, then a subsequent erase operation is executed upon the selected memory block. Verase is also set to VSS during read and program operations, or alternately, a different circuit couples VSS to n-well 52 and p-well 54. For example, n-channel transistor devices can be used to couple n-well 52 and p-well 54 in response to a control signal that is activated during read or program operations. Logic for executing such an operation would be well known to those skilled in the art. A problem with the prior art NAND flash memory is the amount of time required to drive n-well 52 and p-well 54 from VSS to Verase, which directly affects the total erase time. It is apparent from FIG. 1B that the area of one memory bank is large relative to the total area of flash memory chip 10, and thus the capacitance can be in the range of several nF for example. As a result, the rise time of Verase can be between 200 μs to 300 μs, for example.

FIG. 5 is a graph plotting the relationship between the substrate voltage Vsub and time. If an erase operation begins at time=0 and Verase is at VSS, then there is a delay of t_delay before the substrate voltage reaches Verase. As previously mentioned, this delay can range between 200 μs to 300 μs for some example flash memory devices. A solution to improve erase performance is to increase the size of the charge pump circuit that generates Verase. This typically involves a combination of adding capacitor elements or increasing the size of capacitor elements of the charge pump to increase the rate at which the substrate reaches Verase. A larger charge pump would thus reduce t_delay and improve erase performance. Persons skilled in the art understand that capacitor elements used in such charge pumps occupy significant semiconductor area. FIG. 1B clearly shows that charge pump 24 occupies a significant area of flash memory chip 10, especially in comparison with the logic block 22. An example charge pump circuit is shown in U.S. Pat. No. 5,642,309. In view of the tightly packed layout of the example flash memory chip 10 of FIG. 1B, there is insufficient area for increasing the size of charge pump 24. Accordingly, improved erase performance in flash memory chip 10 may not be attained. In some flash memory chip designs, the primary constraint may be to minimize chip size, which directly impacts the cost of the chip. While a minimally sized charge pump will reduce chip area consumption, the drawback is degraded erase performance. Hence there is a trade-off between erase performance and chip area in prior art flash memory chips.

Another problem with the prior art NAND flash memory is the power consumption due to the charging and discharging of the n-well 52 and p-well 54. As previously mentioned, because each of the memory array wells occupy a large proportion of the area of flash memory chip 10 of FIG. 1B, their capacitance can be in the range of several nF for example. This is problematic because after each erase cycle, an erase verify operation is executed to check that the erased memory cells have the erased threshold voltage. An erase verify operation is similar to a normal NAND flash read operation, and therefore the n-well 52 and p-well 54 are biased to VSS. If the verify operation fails, then the erase cycle is repeated and the wells are charged back to Verase. This process may repeat several times, thus consuming power.

A further problem with the prior art NAND flash memory is the exposure of unselected memory blocks to the Verase well voltage when a selected memory block is to be erased. Although the previously described self-boosting erase inhibit scheme can be used to minimize erase disturbance in the cells of the unselected memory blocks, there is still a voltage difference between Verase of the well and the wordlines that are at about 80% to 90% of Verase in the unselected blocks. While the resulting erase disturb may be small for one erase cycle, the cumulative effect will be significant. For example, if it is assumed that the memory array has 2048 memory blocks and the erase time for one memory block is about 2 ms, then erasing all the memory blocks just once will expose each memory block to 2047×2 ms of erase stress. The cumulative erase disturb stress is more significant in multi-level NAND flash cells.

SUMMARY

It is an object of the present invention to obviate or mitigate at least one disadvantage of previous NAND Flash memories.

According to an embodiment of the present invention achieves a NAND flash memory chip having high speed erase performance while minimizing charge pump circuit area, power consumption and erase stress for unselected memory blocks.

For example, in accordance with one embodiment, there is provided with a NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to the single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area. Furthermore, because the well sector capacitance is reduced, the amount of power consumed for charging and discharging the well sector during erase operations is also reduced.

In a first aspect, the present invention provides NAND Flash memory. The NAND flash memory includes a first well sector, a second well sector, a bitline and a page buffer. The first well sector has a first NAND cell string for selectively receiving an erase voltage during an erase operation. The second well sector has a second NAND cell string for selectively receiving the erase voltage during the erase operation. The bitline is electrically connected to the first NAND cell string and the second NAND cell string. The page buffer is electrically connected to the bitline. The first well sector can include a third NAND cell string electrically connected to a second bitline, and the second well sector can include a fourth NAND cell string electrically connected to the second bitline, where the second bitline is electrically connected to the page buffer. The first NAND cell string and the third NAND cell string are part of one memory block, and the second NAND cell string and the fourth NAND cell string are part of another memory block.

Alternately, the first well sector can include a third NAND cell string electrically connected to the bitline, and the second well sector can include a fourth NAND cell string electrically connected to the bitline. The first NAND cell string is part of a first memory block, the third NAND cell string is part of a second memory block, the second NAND cell string is part of a third memory block, and the fourth NAND cell string is part of a fourth memory block. The NAND flash memory can further include a block decoder for selecting one of the first memory block, the second memory block, the third memory block and the fourth memory block for erasure, in response to a block address. A charge pump and a selector can be provided, where the charge pump provides an erase voltage and the selector couples the erase voltage to one of the first well sector and the second well sector in response to the block address.

The bitline described in the first aspect can include a first bitline segment electrically connected to the first NAND cell string and a second bitline segment electrically connected to the second NAND cell string through an isolation device, where the isolation device is located between the first well sector and the second well sector. The isolation device can have its gate terminal biased to a voltage greater than a supply voltage VDD during a program operation, a read operation and the erase operation. Alternately, the isolation device can be rendered electrically non-conductive in the erase operation for isolating the first bitline segment from the second bitline segment when one of the first NAND cell string and the second NAND cell string is selected for erasure. The isolation device can be turned off in response to a control signal or in response to a well sector selection signal. The NAND flash memory can further include a bitline segment decoder for enabling the isolation device in response to a well sector selection signal during a read operation, the bitline segment decoder disabling the isolation device in response to an erase control signal during an erase operation. The bitline segment decoder can include an isolation device driver for receiving the erase control signal and the well sector selection signal, the isolation device driver providing an isolation drive signal for controlling the isolation device when the well sector selection signal is at an active logic level. The isolation device driver can include an override circuit for driving the well sector selection signal to the active logic level in response to another well sector selection signal at the active logic level.

In a second aspect, the present invention provides a NAND Flash memory. The NAND Flash memory includes at least two well sectors each including at least one memory block of NAND cell strings, and isolation devices. The at least one memory block in each of the at least two well sectors is electrically connected to corresponding bitline segments, and the isolation devices are coupled between the bitline segments corresponding to the at least two well sectors. Each of the at least two well sectors can include two memory blocks. The isolation devices can have gate terminals biased to a predetermined voltage which can be greater than a supply voltage VDD. Alternately, the isolation devices are turned off during an erase operation, or are selectively turned off during a read operation. During a read operation the isolation devices between a selected well sector including a selected memory block and a page buffer are turned on. The NAND flash memory further includes a selector for selectively passing an erase voltage to one of the at least two well sectors. The selector couples the erase voltage to one of the at least two well sectors in response to a portion of a block address, the block address being decoded to select one memory block for erasure. The NAND flash memory can further include a page buffer electrically connected to the bitline segments corresponding to one of the at least two well sectors.

In a third aspect, the present invention provides a method for erasing a selected memory block in a NAND Flash device. The method includes selecting a memory block in a first well sector, the first well sector including at least two memory blocks; biasing the memory block formed in the first well sector for erasure; biasing an unselected memory block formed in the first well sector for inhibiting erasure; applying an erase voltage to the first well sector; and, inhibiting application of the erase voltage to a second well sector including at least another two memory blocks. The method can further include decoupling bitline segments corresponding to the first well sector and the second well sector from each other before applying the erase voltage to the first well sector. Alternately, the method can further include decoupling bitline segments corresponding to the first well sector and the second well sector from each other with an isolation device when a bitline voltage of the first well sector is at least a predetermined bias voltage applied to a gate terminal of the isolation device.

Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:

FIG. 1A is a block diagram of a flash memory device;

FIG. 1B is a floor plan layout a prior art flash memory device;

FIG. 2 is a circuit schematic showing circuit details of two memory blocks in one memory array of the flash memory chip of FIG. 1B;

FIG. 3 is a cross-sectional diagram of one memory array of the flash memory chip of FIG. 1B;

FIG. 4 is a cross section diagram of a NAND cell string of FIG. 3;

FIG. 5 is a graph plotting the relationship between the substrate voltage Vsub and time;

FIG. 6 is a block diagram of a NAND flash memory bank according to an embodiment of the present invention;

FIG. 7A is a block diagram of a row decoder used in the NAND flash memory bank of FIG. 6;

FIG. 7B is circuit schematic of a memory block drive circuit shown in FIG. 7A;

FIG. 8A is a block diagram of a NAND flash memory bank having one memory block per well sector, according to an example of the NAND flash memory bank of FIG. 6;

FIG. 8B is a cross-sectional diagram of one memory array of the NAND flash memory bank of FIG. 8A;

FIG. 9A is a block diagram of a NAND flash memory bank having multiple memory blocks per well sector, according to another example of the NAND flash memory bank of FIG. 6;

FIG. 9B is a cross-sectional diagram of one memory array of the NAND flash memory bank of FIG. 9A;

FIG. 10 is the cross-sectional diagram of FIG. 9B including isolation devices formed in-line with the bitlines;

FIG. 11 is a circuit schematic of a memory bank having dynamically controlled isolation devices, according to one example;

FIG. 12 is a circuit schematic of a memory bank having dynamically controlled isolation devices, according to another example;

FIG. 13 is a circuit schematic of a memory bank having dynamically controlled isolation devices, according to yet another example; and,

FIG. 14 is a flow chart showing a method of erasing a memory block, according an embodiment of the present invention.



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stats Patent Info
Application #
US 20140022846 A1
Publish Date
01/23/2014
Document #
14032816
File Date
09/20/2013
USPTO Class
36518512
Other USPTO Classes
International Class
11C16/16
Drawings
18


Semiconductor
Memory Cell
Elective
Cells
Erase
Flash Memory
Memory Cells
Charge Pump Circuit
Flash Memory 구조
Nand Flash


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