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High voltage device with a parallel resistor

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High voltage device with a parallel resistor


Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.
Related Terms: Semiconductor Semiconductor Device

Browse recent Taiwan Semiconductor Manufacturing Company, Ltd. patents - Hsin-chu, TW
USPTO Applicaton #: #20140021560 - Class: 257380 (USPTO) -
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device >Having Insulated Electrode (e.g., Mosfet, Mos Diode) >Insulated Gate Field Effect Transistor In Integrated Circuit >Combined With Passive Components (e.g., Resistors) >Polysilicon Resistor

Inventors: Ru-yi Su, Fu-chih Yang, Chun Lin Tsai, Ker Hsiao Huo, Jen-hao Yeh, Chun-wei Hsu

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The Patent Description & Claims data below is from USPTO Patent Application 20140021560, High voltage device with a parallel resistor.

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BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.

These ICs include high voltage semiconductor devices. As geometry size continues to be scaled down, it has become increasingly more difficult for existing high voltage semiconductor devices to achieve certain performance criteria. As an example, a breakdown voltage may become a performance limitation for traditional high voltage semiconductor devices. In conventional high voltage semiconductor devices, improvement in the breakdown voltage by reducing drift region doping may lead to an undesirable increase in an on-state resistance of the device.

Therefore, while existing high voltage semiconductor devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flowchart illustrating a method for fabricating a high voltage semiconductor device according to various aspects of the present disclosure.

FIGS. 2-9 are diagrammatic fragmentary cross-sectional side views of various embodiments of a high voltage semiconductor device in accordance with various aspects of the present disclosure.

FIGS. 10-13 are simplified top views of various embodiments of a high voltage semiconductor device in accordance with various aspects of the present disclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity.

Illustrated in FIG. 1 is a flowchart of a method 10 of fabricating a high voltage semiconductor device according to various aspects of the present disclosure. The method 10 includes a block 12 in which a drift region is formed in a substrate. The drift region includes doped regions with different types of conductivity. The method 10 includes a block 14 in which a dielectric isolation structure is formed over the drift region. In some embodiments, the dielectric isolation structure includes a local oxidation of silicon (LOCOS) that protrudes out of a surface of the substrate. The method 10 includes a block 16 in which a gate of a transistor is formed over a portion of the dielectric isolation structure. The method 10 includes a block 18 in which a resistor device is formed over the dielectric isolation structure. The resistor device includes a plurality of winding segments. In some embodiments, the winding segments have substantially uniform dimensions and spacing. The method 10 includes a block 20 in which a source and a drain in the substrate. The source and the drain are separated by the drift region and the dielectric isolation structure. The resistor device and the gate are disposed between the source and the drain.

It is understood that additional steps may be performed to complete the fabrication of the high voltage semiconductor device. For example, the method may include a step in which an interconnect structure is formed over the substrate. The interconnect structure either electrically couples the resistor device in parallel to the transistor, or leaves the resistor electrically floating.

FIG. 2 illustrates a diagrammatic fragmentary cross-sectional side view of a high voltage semiconductor device 20A according to an embodiment of the present disclosure. It is understood that FIG. 2 has been simplified for a better understanding of the inventive concepts of the present disclosure.

Referring to FIG. 2, the high voltage semiconductor device 20A includes a portion of a substrate 30. The substrate 30 is doped with a P-type dopant such as boron. In another embodiment, the substrate 30 may be doped with an N-type dopant such as phosphorous or arsenic. The substrate 30 may also include other suitable elementary semiconductor materials, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

A buried well 35 is formed in a portion of the substrate 30 through an ion implantation process known in the art. The buried well 35 is formed to have an opposite type of conductivity than that of the substrate 30. In the illustrated embodiment, the buried well 35 is N-type doped, since the substrate 30 herein is a P-type substrate. In another embodiment where the substrate 30 is an N-type substrate, the buried well 35 is P-type doped. The buried well 35 may be formed by an implantation process having a dose that is in a range from about 1×1012 atoms/centimeter2 to about 2×1012 atoms/centimeter2. The buried well 35 may have a doping concentration that is in a range from about 1×1015 atoms/centimeter3 to about 1×1016 atoms/centimeter3.

A high voltage doped well 50 is formed in the substrate 30. The high voltage doped well 50 may be formed by an ion implantation process known in the art. For example, the doped well 50 may be formed by an implantation process having a dose that is in a range from about 3×1012 atoms/centimeter2 to about 4×1012 atoms/centimeter2. In an embodiment, the high voltage doped well has a doping concentration that is in a range from about 1×1015 atoms/centimeter3 to about 1×1016 atoms/centimeter3. A patterned photoresist layer (not illustrated) may be formed over the substrate 35 as a mask during the implantation process.

The high voltage doped well 50 is doped with the same type of conductivity as the buried well 35 (i.e., opposite from that of the substrate 30). Thus, the high voltage doped well 50 is a high voltage N-well (HVNW) in the illustrated embodiment. The high voltage doped well 50 may also be referred to as a drift region 50. In some embodiments, the buried well 35 may be considered to be a part of the high voltage doped well 50 and may be considered to be a part of the drift region 50 as well.

A plurality of isolation structures are formed over the drift region 50, for example isolation structures 80 and 81 shown in FIG. 2. The isolation structures 80-81 may include a dielectric material. In the embodiment shown in FIG. 2, the isolation structures 80-81 are Local Oxidation of Silicon (LOCOS) devices (also referred to as field oxide). The LOCOS devices may be formed using a nitride mask and thermal-growing an oxide material through the mask openings. At least a portion of the LOCOS devices protrude downwardly into, and protrude upwardly out of, the drift region 50. Furthermore, the LOCOS devices may have uneven thicknesses (or depths). For example, the edge portions of the LOCOS devices may have tapered shapes and thus smaller thicknesses. In some embodiments, the non-edge portions of the LOCOS devices have a thickness 90, which may be in a range from about 0.2 microns (um) to about 1 um in certain embodiments.

Alternatively, the isolation structures 80-81 may include shallow trench isolation (STI) devices or deep trench isolation (DTI) devices. The dielectric structures 80-81 help define boundaries of certain doped regions to be formed later, for example boundaries of source and drain regions of a Field Effect Transistor (FET) device.

A doped extension region 100 is formed in the drift region 50. In the embodiment shown, the doped extension region 100 is formed between the high voltage doped well 50 and the buried well 35. The doped extension region 100 has the same type of conductivity as the substrate 30 but an opposite type of conductivity as the drift region 50. Thus, in the embodiment shown, the doped extension region 100 has a P-type of conductivity.

In certain embodiments, the doped extension region 100 may be formed by two separate ion implantation processes. The first ion implantation process forms a doped region at least partially in the upper portion of the drift region 50 (near the upper surface of the drift region 50). The second ion implantation process forms a deeper and wider doped region that “extends” or “protrudes” laterally outward. Subsequently, a thermal process may be performed to inter-diffuse and merge the two doped regions into a single doped region, thereby forming the doped extension region 100. As a result, the doped extension region 100 has a protruding portion 105 (or protruding tip) that laterally extends or protrudes partially into the drift region 50. Therefore, the doped extension region 100 may also be referred to as a P-body extension region 100 herein.



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stats Patent Info
Application #
US 20140021560 A1
Publish Date
01/23/2014
Document #
13551262
File Date
07/17/2012
USPTO Class
257380
Other USPTO Classes
438238, 257E27016, 257E21616
International Class
/
Drawings
14


Semiconductor
Semiconductor Device


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