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Semiconductor device and a method of increasing a resistance value of an electric fuse

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Semiconductor device and a method of increasing a resistance value of an electric fuse


Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
Related Terms: Semiconductor Semiconductor Device Barrier Film Resin

Browse recent Renesas Electronics Corporation patents - Kawasaki, JP
USPTO Applicaton #: #20140021559 - Class: 257379 (USPTO) -
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device >Having Insulated Electrode (e.g., Mosfet, Mos Diode) >Insulated Gate Field Effect Transistor In Integrated Circuit >Combined With Passive Components (e.g., Resistors)



Inventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi

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The Patent Description & Claims data below is from USPTO Patent Application 20140021559, Semiconductor device and a method of increasing a resistance value of an electric fuse.

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CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No. 12/760,648, filed Apr. 15, 2010, which, in turn, is a continuation of U.S. application Ser. No. 11/683,053, filed Mar. 7, 2007 (now U.S. Pat. No. 7,745,905); and which application claims priority from Japanese patent application No. 2006-256226 filed on Sep. 21, 2006, the entire contents of which are hereby incorporated by reference into this application.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device which receives the supply of an electric current so as to be permitted to increase the resistance of the device itself, and a method of increasing the resistance of an electric fuse.

Hitherto, there has been used a fuse which receives the supply of an electric current to be permitted to increase the resistance of the fuse itself. In the present specification, such a fuse is called an electric fuse. The electric fuse is set inside an insulator layer. In the specification, a structure having an insulator layer and an electric fuse is called an electric fuse structure. In the specification, an increase in the resistance of an electric fuse is, for example, a phenomenon that the value of an electric current flowing into the electric fuse becomes small, that is, the electric fuse turns into a state that the fuse has a higher resistance than before, or a phenomenon that the flow of an electric current between two elements connected to both ends of the electric fuse stops completely, that is, the electric fuse is cut or melted/cut, or the resistance of the electric fuse becomes infinite. Examples of the electric fuse described in the specification include a fuse for making the use of an electric circuit impossible, a fuse which is used in an analog device or the like to adjust the voltage of the device, and a fuse which is used as a tag for leaving the hysteresis of a process, a test result or the like. [Patent Document 1] Pamphlet of WO 97/12401 [Patent Document 2] U.S. Pat. No. 5,969,404 [Patent Document 3] U.S. Pat. No. 6,323,535 [Patent Document 4] U.S. Pat. No. 6,433,404

[Patent Non-document 1] V. Klee et al., “A 0.13 μm logic based embedded DRAM technology with electrical fuses, Cu interconnect in SiLk™, sub-7 ns access and its extension to the 0.10 μm generation”, IEDM Conference (2001).

SUMMARY

OF THE INVENTION

Increases in the resistance of conventional electric fuses are realized by an electromigration phenomenon. For this reason, in some cases, it is necessary to supply a large electric current to an electric fuse. In such cases, a structure around the electric fuse may be damaged by heat generated from the fuse.

In light of the above-mentioned problems, the present invention has been made. Thus, an object of the invention is to provide a semiconductor device which is permitted to increase the resistance of the device itself without damaging any surrounding structure, and a method of increasing the resistance of an electric fuse.

An aspect of the present invention is a semiconductor device comprising an insulator layer and an electric fuse formed in the insulator layer. The electric fuse has a larger linear expansion coefficient than that of the insulator layer, and further has a lower melting point than that of the insulator layer.

According to this structure, the resistance of the electric fuse can be increased even if the value of an electric current supplied to the electric fuse is small. Accordingly, the amount of heat generated from the electric fuse is small. As a result, a structure around the electric fuse is prevented from being damaged.

Another aspect of the invention is a semiconductor device comprising a semiconductor substrate, a gate electrode formed over the semiconductor substrate, an interlayer dielectric covering the gate electrode, a fine layer formed over the interlayer dielectric, a semiglobal layer formed over the fine layer, a global layer formed over the semiglobal layer, and an electric fuse formed in at least one selected from the fine layer, the semiglobal layer, and the global layer.

According to this structure, when an electric current is supplied to the electric fuse, the distance over which heat generated from the electric fuse reaches the semiconductor substrate is large; therefore, the resistance of the electric fuse can be increased without damaging the semiconductor substrate.

Still another aspect of the invention is a semiconductor device comprising an insulator layer, and an electric fuse which is formed in the insulator layer, and has a meandering shape comprising a linear portion and a bent portion, wherein the distance between moieties near the bent portion is smaller than the distance between moieties other than the moieties near the bent portion.

According to this structure, heat from a central portion of the electric fuse does not diffuse outside easily since the electric fuse is meandering. Therefore, a structure around the electric fuse is restrained from being damaged by heat generated from the electric fuse. Moreover, a time required for an increase in the resistance of the electric fuse can be shortened since a large amount of heat is locally given only to the bent portion.

A different aspect of the invention is a method of increasing the resistance of an electric fuse wherein an electric current is supplied to the electric fuse which is any one of the above-mentioned electric fuses. In this way, the electric fuse is melted and is further cracked. Thereafter, a part of the melted electric fuse is absorbed into the crack by use of a capillary phenomenon. As a result, a discontinuous portion is formed in the electric fuse. According to this method, an electric fuse can be cut by a smaller electric current than that given to an electric fuse in any conventional method of using electromigration to cut the electric fuse.

A further different aspect of the invention is a method of increasing the resistance of an electric fuse comprising the steps of: supplying an electric current to the electric fuse which is any one of the above-mentioned electric fuses, thereby making the electric fuse narrow by use of pinch effect; and then stopping the supply of the electric current, thereby forming a cavity in the electric fuse by use of retaining force of the electric fuse. According to this method, an electric fuse can be cut by a smaller electric current than that given to an electric fuse in the above-mentioned method of cutting the electric fuse by use of a capillary phenomenon.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view illustrating a structure of an electronic circuit to which an electric fuse of an embodiment of the invention is fitted.

FIG. 2 is a view illustrating a structure of the whole of a semiconductor device wherein an electric fuse structure of the embodiment is formed.

FIG. 3 is a schematic view illustrating the electric fuse of the embodiment which has a meandering shape.

FIG. 4 is a sectional view taken on line IV-IV in FIG. 3.

FIG. 5 is a schematic view illustrating the electric fuse of the embodiment which is made only of a liner portion.

FIG. 6 is a sectional view taken on line VI-VI in FIG. 5.

FIG. 7 is a schematic view illustrating another example of the electric fuse of the embodiment which has a meandering shape.

FIG. 8 is a photograph showing a state that linear portions of an electric fuse of the embodiment which has a meandering shape contact each other by leakage or solid dissolution.

FIG. 9 is a view illustrating a basic example of the electric fuse structure of the embodiment.

FIG. 10 is a first different example of the electric fuse structure of the embodiment.

FIG. 11A is a second different example of the electric fuse structure of the embodiment.

FIG. 11B is a third different example of the electric fuse structure of the embodiment.

FIG. 12A is a fourth different example of the electric fuse structure of the embodiment.

FIG. 12B is a fifth different example of the electric fuse structure of the embodiment.

FIG. 13 is a sixth different example of the electric fuse structure of the embodiment.

FIG. 14A is a seventh different example of the electric fuse structure of the embodiment.

FIG. 14B is an eighth different example of the electric fuse structure of the embodiment.

FIG. 15 is a ninth different example of the electric fuse structure of the embodiment.

FIG. 16A is a tenth different example of the electric fuse structure of the embodiment.

FIG. 16B is an eleventh different example of the electric fuse structure of the embodiment.

FIG. 17 is a twelfth different example of the electric fuse structure of the embodiment.

FIG. 18A is a thirteenth different example of the electric fuse structure of the embodiment.

FIG. 18B is a fourteenth different example of the electric fuse structure of the embodiment.

FIG. 19 is a fifteenth different example of the electric fuse structure of the embodiment.

FIG. 20A is a sixteenth different example of the electric fuse structure of the embodiment.

FIG. 20B is a seventeenth different example of the electric fuse structure of the embodiment.

FIG. 21 is a view for explaining the direction of force acting on the electric fuse which is the basic example of the embodiment when an electric current flows into this electric fuse.

FIG. 22 is a view for explaining a state that the electric fuse of the basic example swells.

FIG. 23 is a top view illustrating a first state of the electric fuse of the basic example when it is cut.

FIG. 24 is a sectional view taken on line XXIV-XXIV in FIG. 23.

FIG. 25 is a top view illustrating a second state of the electric fuse of the basic example when it is cut.

FIG. 26 is a sectional view taken on line XXVI-XXVI in FIG. 25.

FIG. 27 is a top view illustrating a third state of the electric fuse of the basic example when it is cut.

FIG. 28 is a sectional view taken on line XXVIII-XXVIII in FIG. 27.

FIG. 29 is a top view illustrating a fourth state of the electric fuse of the basic example when it is cut.

FIG. 30 is a sectional view taken on line XXX-XXX in FIG. 29.

FIG. 31 is a top view illustrating a fifth state of the electric fuse of the basic example when it is cut.

FIG. 32 is a sectional view taken on line XXXII-XXXII in FIG. 31.

FIG. 33 is a photograph (of a cross section) showing a state that an electric fuse is absorbed into a crack formed in an insulator layer in an electric fuse structure.

FIG. 34 is a photograph (of a top face) showing the state that the electric fuse is absorbed into the crack formed in the insulator layer in the electric fuse structure.

FIG. 35 is a view illustrating an electric current pulse as an improper pulse, and an electric current pulse as a proper pulse.

FIG. 36 is a photograph showing an electric fuse cut by an electric current pulse as an improper pulse, and an electric fuse cut by an electric current pulse as a proper pulse.

FIG. 37 is a graph showing a relationship between rise time of electric current pulses and the ratio of the resistance of an electric fuse after the fuse is cut to that of the electric fuse before the fuse is cut.

FIG. 38 is a top view illustrating an example of the position of a cut portion of an electric fuse made only of a linear portion.

FIG. 39 is a chart wherein positions of cut portions of plural electric fuses each made only of a linear portion are plotted.

FIG. 40 is a view for explaining an electric fuse structure wherein a central portion is selectively to be cut.

FIG. 41 is a photograph showing an electric fuse structure wherein a central portion was selectively cut.

FIG. 42 is a view illustrating the distance between linear portions.

FIG. 43 is a view illustrating a state that linear portions short-circuit through a cut piece.

FIG. 44 is a view illustrating an electric fuse structure having a construction for preventing linear portions from short-circuiting.

FIG. 45 is a view for explaining a method of cutting an electric fuse by use of pinch effect.

FIG. 46 is a photograph showing an electric fuse cut by pinch effect.

FIG. 47 is a graph of a relationship between time and the distance between a moiety having a temperature of 600° C. when the temperature of an electric fuse was kept at 1200° C. and the electric fuse.

DETAILED DESCRIPTION

OF THE PREFERRED EMBODIMENTS

With reference to the attached drawings, embodiments of the semiconductor device according to the present invention and the method of increasing the resistance of an electric fuse according to the invention will be described hereinafter.

Embodiment 1

An electric fuse of an embodiment 1 of the present invention is not any electric fuse formed in the same layer in which a gate electrode is formed, as in the prior art. The electric fuse of the embodiment 1 is formed in a fine layer in a multi-layered structure including the fine layer, a semiglobal layer and a global layer in a semiconductor device. Therefore, the electric fuse is prevented from damaging its semiconductor substrate.

According to the structure of the semiconductor device of the embodiment 1, other elements, such as a transistor for controlling the flow of an electric current for increasing the resistance of the fuse, can be arranged in a space from the semiconductor substrate to the electric fuse; therefore, it is possible to make small the occupation area of elements arranged in a direction parallel to a main surface of the semiconductor substrate of the semiconductor device.

The increase in the resistance of the electric fuse of the embodiment 1 is realized not by any electromigration phenomenon but a capillary phenomenon. Accordingly, the resistance of the electric fuse can be increased only by causing a relatively small electric current to flow into the electric fuse. As a result, a structure around the electric fuse is prevented from being damaged. Moreover, the time necessary for an increase in the resistance of the electric fuse can be largely shortened.

In the embodiment 1, the electric fuse is a member for separating a redundant circuit and any other circuit electrically from each other. However, the usage of the electric fuse of the invention is not limited thereto. The electric fuse of the invention can be applied to any article as long as the article is an article having a resistance that can be increased by receiving the supply of an electric current. The raw material of the electric fuse is suitably a metal or a metal compound. However, the raw material of the electric fuse of the invention is not limited thereto as long as a resistance-increasing method that will be described below can be applied to the raw material.

First, the electric fuse structure of the embodiment 1 is specifically described herein. As illustrated in FIG. 1, the electric fuse (electric fuse 10) of the embodiment 1 is set inside a semiconductor device, and is connected to a power source electrode VDD and an earth electrode VSS so as to be present therebetween. A resistor 60 is arranged between a terminal 10a of the electric fuse 10 and the power source electrode VDD, and a resistor 70 is arranged between a terminal 10b of the electric fuse 10 and the earth electrode VSS. A transistor 40 and a decision circuit 50 are connected to a wiring between the resistor 70 and the terminal 10b. The decision circuit 50 is a circuit for detecting whether or not the resistance of the electric fuse 10 turns into a predetermined value or more. An inverter circuit 30 is connected to the gate electrode of the transistor 40. In accordance with an electric signal given from the inverter circuit 30 to the transistor 40, an electric current flows from the power source electrode VDD through the electric fuse 10 to the earth electrode VSS. Accordingly, in the method of increasing the resistance of the electric fuse 10 in the embodiment 1, whether or not the resistance of the electric fuse is increased can be controlled in accordance with an electric signal given to the transistor 40 from the outside. Whether or not the resistance of the electric fuse 10 is over the predetermined value is decided by the decision circuit 50.

Next, the structure of the semiconductor of the embodiment 1 is described herein with reference to FIG. 2. The semiconductor device of the embodiment 1 has plural stacked metal wiring layers. The metal wiring layers are named M1, M2, . . . M8 and M9, respectively, in the order from the side of a semiconductor substrate SC upwards. The metal wiring layers are connected to each other through vias. The vias are named V1, V2, . . . , V7 and V8, respectively, in the order from the side of the semiconductor substrate SC upwards.

Out of the layers including the metal wiring layers M1, M2, . . . M8 and M9, and the vias V1, V2, . . . , V7 and V8, layers positioned at a lower side are called a fine layer 100, and layers positioned at an upper side are called a global layer 300. The layers positioned between the fine layer 100 and the global layer 300 are called a semiglobal layer 200.

The metal wiring layers in the fine layer 100 each have the smallest wiring width and thickness among the metal wiring layers constituting the semiconductor device. The metal wiring layers in the semiglobal layer 200 each have a larger wiring width and a larger thickness than those of the metal wiring layers in the fine layer 100. The metal wiring layers in the global layer 300 each have a larger wiring width and a larger thickness than those of the metal wiring layers in the semiglobal layer 200. Examples of dimensions of the fine layer 100, the semiglobal layer 200 and the global layer 300 are shown in Table 1.



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stats Patent Info
Application #
US 20140021559 A1
Publish Date
01/23/2014
Document #
14033036
File Date
09/20/2013
USPTO Class
257379
Other USPTO Classes
257529
International Class
01L23/525
Drawings
34


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Semiconductor
Semiconductor Device
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Resin


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Active Solid-state Devices (e.g., Transistors, Solid-state Diodes)   Field Effect Device   Having Insulated Electrode (e.g., Mosfet, Mos Diode)   Insulated Gate Field Effect Transistor In Integrated Circuit   Combined With Passive Components (e.g., Resistors)