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Thin film solar cell with ceramic handling layer

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20140014172 patent thumbnailZoom

Thin film solar cell with ceramic handling layer


A solar cell may comprise a stack of thin continuous epitaxial single crystal solar cell layers on a single crystal wafer, and a handling layer on the stack, the handling layer having a waffle-shaped structure with an array of either square or circular apertures, wherein the handling layer includes electrical contacts to the stack. The solar cell may comprise a boundary layer between the stack and the handling layer, the boundary layer being attached to both the stack and the handling layer, and the boundary layer being greater than 10 nanometers thick and parallel to the layers in the stack. The waffle-shaped structure may include perpendicular sets of first and second parallel ridges, wherein at least one of the sets is aligned at a small angle to a cleavage plane of the single crystal wafer.
Related Terms: Wafer

USPTO Applicaton #: #20140014172 - Class: 136256 (USPTO) -
Batteries: Thermoelectric And Photoelectric > Photoelectric >Cells >Contact, Coating, Or Surface Geometry

Inventors: Ananda H. Kumar, Tirunelveli S. Ravi, Vidyut Gopal

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The Patent Description & Claims data below is from USPTO Patent Application 20140014172, Thin film solar cell with ceramic handling layer.

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CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 12/766,765 filed Apr. 23, 2010, which is a continuation-in-part of U.S. patent application Ser. No. 12/399,248 filed Mar. 6, 2009, now U.S. Pat. No. 8,030,119 Issued Oct. 4, 2011, which claims the benefit of U.S. Provisional Patent Application Ser. No. 61/068,629, filed Mar. 8, 2008. The foregoing disclosures are incorporated herein by reference in their entirety.

FIELD OF THE INVENTION

This invention relates generally to solar cells, and more particularly to solar cells with ceramic handling layers, and methods and systems for fabricating said solar cells with ceramic handling layers.

BACKGROUND OF THE INVENTION

Silicon is the basic ingredient of many solar cell technologies ranging from thin film amorphous silicon solar cells to single-crystal silicon wafer-based solar cells. High efficiency solar cells start with electronic grade polysilicon grown by chemical vapor deposition. The polysilicon is melted and ingots are pulled from the melt in the Czochralski process and often zone refined to produce silicon ingots or ribbons of different degrees of crystal perfection. The silicon ingot is then sliced into thin wafers by sawing or laser cutting, and solar cells are formed on the wafers by traditional semiconductor techniques and interconnected and packaged to last at least 25 years. Such silicon wafers are relatively expensive and thus severely impact the costs of solar cells in formed and packaged in the standard wafers.

Throughout the past quarter century, there have been significant innovations in all aspects of solar cell manufacture and accompanying reduction in cost. For example, from 1990 to 2006, wafers have decreased in thickness from 400 μm to 200 μm. The cost of crystalline silicon still constitutes a significant part of the overall cost, as measured by many of the metrics used to characterize the cost of crystalline solar technology.

A flow chart of a conventional process for manufacturing solar panels is illustrated in FIG. 1. In step 102, stock single-crystal silicon wafers are used as substrates which are cut into shapes that are approximately square, often with rounded corners due to the size and shape of the original wafer (200 mm diameter typically). In step 104, a photovoltaic (PV) cell structure, which is basically a diode, is fabricated on the top surface of the wafers. The fabrication process uses epitaxial or diffusion furnace methods to form the required thin silicon layers doped n-type and p-type and sometimes intrinsic (i-type). The PV cells are then assembled into an X-Y array on a substrate 106 and contacts to the n-type and p-type layers are added, often by soldering tinned copper ribbons to bus bars grown on the PV wafers. It has been difficult or impossible to attain very thin solar cells using the prior art process in which individual PC cells are formed prior to assembly into the final X-Y array needed for a completed solar panel.

The best expectation for further reductions in silicon thickness, and thereby the cost of monocrystalline silicon solar cells, is offered by techniques in which a crystal monocrystalline silicon substrate, often referred to as the base, source or mother wafer, is first treated to form a separation layer, a thin epitaxial silicon layer is then deposited on the treated surface, and finally the deposited epitaxial layer is separated from the source substrate to be used as thin (2-100 μm) single crystal silicon solar cells. The silicon substrate is thereafter sequentially re-used to form several additional such epitaxial layers, each producing its own solar cell. There are several known standard techniques for growing the separation layer, such as forming a composite porous silicon layer by anodically etching a discontinuous oxide masking layer, or by high energy implantation of oxygen or hydrogen to form the separation layer within mother wafer.

The epitaxial silicon layer that is formed has to be separated intact from the mother wafer with little damage in order to thereafter fabricate the eventual solar cell module. The separation may be preceded by formation of the p-n junctions and of part or all of the interconnections while the epitaxial layer is still attached to the mother wafer. We believe that this separation process is preferably done by “peeling” in the case where the separation layer is highly porous silicon. Peeling implies parting of an interface starting from one edge and continuing until complete separation occurs.

One basic process in the prior art for manufacturing epitaxial single crystal silicon solar modules includes the following steps: (1) forming a separation layer on a relatively thick, single crystal silicon substrate; (2) growing a single crystal epitaxial layer; 3) separating the epitaxial layer and fabricating the solar cells on the epitaxial layer and the basic cell interconnections on the solar cells; and (4) assembling and packaging several such cells to form a solar panel. Despite the great potential of this prior art method for producing relatively inexpensive, highly efficient solar cells, the method has eluded commercial success for at least three main reasons: (1) some of the unit processes are deficient and difficult to reproduce especially for thin epitaxial wafers; (2) manufacturing strategy generally starts and ends with making individual wafer-size solar cells and, thereafter, assembling them into solar panels; and (3) thin cells break easily, and their economical processing awaits the development of new tools and equipment.

SUMMARY

OF THE INVENTION

The present invention turns the prior art strategy on its head, starting with the solar panel and rethinking the unit manufacturing steps in panel size, starting from the surface treatment of the source wafers through to module encapsulation, completely eliminating the need for handling individual thin epitaxial silicon cells. According to one aspect of the invention, the manufacturing sequence is reversed from the conventional prior art sequence. In this aspect of the invention, multiple source wafer tiles are bonded to a support prior to the formation of individual cells, thereby enabling the use of large-scale processing for solar cell fabrication, instead of the wafer-by-wafer approach previously used. This rethinking involves key innovations that make these unit processes robust and reliable. This approach has been enabled by some key innovations described in this invention. This essentially fulfills the vision for the 2020 module, where “Cell and module manufacturing is based on process steps applied to whole panels instead of individual cells” articulated by G. Beaucarne et al. at the 21st European PVEC Conference in 2006. More importantly, panel size semiconductor processing enables a significant reduction in the cost of solar energy production.

One aspect of the invention includes mounting multiple wafers on a support plate, often called a susceptor, and processing the wafers in common. Examples of the processing include forming a separation layer, depositing silicon to form the solar cell structure, forming contacts, and separating the solar cells as a unit from the wafers.

Another aspect of the invention includes forming a separation layer in the multiple wafers by anodizing preferably monocrystalline wafers to form a porous silicon layer. Although the anodization may be done on an assembled array of solar cell tiles, it may also be done on individual wafers.

The support plate for anodization may be generally planar or may have windows formed there through for exposing the back side of the wafers supported on the ribs surrounding the windows. Thereby, liquid electrolyte may be used as a backside contact.

The anodization may be performed in a serial arrangement of multiple wafer supports removably disposed and arranged between the anode and cathode in tank containing electrolytic etching solution. The supports are sealed to the tank walls.

The anodization forms a porous silicon layer. If desired, the porosity may be graded by varying the anodization conditions during the anodization.

The porous silicon layer may be smoothed to provide a better epitaxial base, for example, by a high temperature anneal in hydrogen, for example, a temperature of at least 1000 C.

Silicon layers, preferably epitaxial, may be deposited by chemical vapor deposition on the porous silicon layer. Dopant precursors may be included in the deposition to produce a layered semiconductor structure including p-n junctions. The epitaxial deposition may be performed in a radiantly heated reactor with wafers mounted inside of a sleeve formed on two sides by wafer supports each mounting an array of solar cells.

Contacts may be fully or partially added to the silicon structures still attached to the wafer supports. Additional layers may be applied to facilitate further processing.

The fully or partially processed solar cells may be delaminated from the mother wafers across the separation (porous) layer by a progressive peeling action including clamps and a linear array of vertical actuators associated with the clamps. Examples of the clamps are segmented electrostatic clamps or a segmented vacuum clamp.

According to further aspects of the invention, a method of fabricating a solar cell comprises: forming a stack of thin continuous epitaxial solar cell layers on a silicon wafer; forming a handling layer on the stack, wherein the handling layer includes electrical contacts to the stack; and separating the stack from the silicon wafer, wherein the stack remains attached to the handling layer. The handling layer may be a glass/ceramic material, such as a glass, glass-bonded ceramic or glass-ceramic, with a CTE which is greater than or equal to the CTE of the stack over the temperature range from ambient temperatures to processing temperatures experienced during formation of the handling layer. Further, before forming the handling layer on the stack a boundary layer may be formed on the stack—the boundary layer being silicon oxide, silicon nitride or alumina, which may act as diffusion barriers and/or passivation layers.

According to yet further aspects of the invention a solar cell comprises: a stack of thin single crystal solar cell layers; a handling layer; and a boundary layer between the stack and the handling layer, the boundary layer being attached to both the stack and the handling layer, the boundary layer being greater than 10 nanometers thick and parallel to the layers in the stack. The handling layer may be waffle-shaped with an array of either square or circular apertures.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures, wherein:

FIG. 1 is a flow chart of a prior art manufacturing process for solar panels;

FIG. 2 is a schematic side cross-sectional view of mother wafers attached to a susceptor without windows;

FIG. 3 is a schematic side cross-sectional view of mother wafers attached to a susceptor with windows;

FIG. 4 is a schematic isometric view of wafers attached to a susceptor;

FIG. 5 is a schematic isometric view of an anodic etcher capable of simultaneously etching multiplicities of wafers attached in a vertical orientation to each of a plurality of susceptors;

FIG. 6 is a schematic side cross-sectional view of the anodic etcher of FIG. 5;

FIG. 7 is a schematic isometric view of an anodic etcher capable of simultaneously etching a number of wafers, each attached in a vertical orientation to a support frame;

FIG. 8 is a schematic isometric view of a wafer sleeve comprising two susceptors, each with a multiplicity of wafers attached thereto;

FIG. 9 is a schematic side cross-sectional view of two mother wafers attached to a susceptor with PV cell structures formed on the upper surfaces of each mother wafer;

FIG. 10 is a schematic side cross-sectional view of the wafers and susceptor from FIG. 9 with a glue layer and glass layer attached to the upper surfaces of the PV cell structures which will become the backsides of the completed PV cells;

FIG. 11 is a schematic side cross-sectional view of the wafers and susceptor from FIG. 9 with a handling layer attached to the upper surfaces of the PV cell structures which will become the backsides of the completed PV cells;

FIG. 12 is a schematic side cross-sectional view of the wafers and susceptor from FIG. 11 with a glue layer and glass layer attached to the upper surfaces of the handling layers which will become the backsides of the completed PV cells;

FIG. 13 is a schematic isometric view of a solar cell panel showing the metal connection strings;

FIG. 14 is a side cross-sectional view of an array of wafer tiles covered by a flexible film and clamped to a segmented electrostatic chuck prior to separation of the highly porous silicon film. Cross-section A-A is illustrated;

FIG. 15 is a side cross-sectional view of an array of wafer tiles covered by a flexible film and clamped to a segmented electrostatic chuck after the beginning of separation of the highly porous film etched in FIG. 7;

FIG. 16 is a top view through cross-section A-A of the electrostatic chuck in FIGS. 14 and 15;

FIG. 17 is a side cross-sectional view of an array of wafer tiles not covered by a flexible film and clamped to a segmented vacuum chuck prior to the separation of the highly porous silicon film. Cross-section B-B is illustrated;

FIG. 18 is a side cross-sectional view of the array of wafer tiles not covered by a flexible film and clamped to a segmented vacuum chuck after the beginning of separation of the highly porous silicon film;

FIG. 19 is a top view through cross-section B-B of the vacuum chuck in FIGS. 17 and 18;

FIG. 20 is a flow chart of the first part of a manufacturing process for solar panels in a first embodiment of the present invention;

FIG. 21 is a flow chart of the first part of a manufacturing process for solar panels in a second embodiment of the present invention;

FIG. 22 is a flow chart of the first part of a manufacturing process for solar panels in a third embodiment of the present invention;

FIG. 23 is a flow chart of the first part of a manufacturing process for solar panels in a fourth embodiment of the present invention;

FIG. 24 is a flow chart of the final part of a manufacturing process for solar panels using PV cells with backside contacts only;

FIG. 25 is a flow chart of the final part of a manufacturing process for solar panels using PV cells with frontside and backside contacts;

FIG. 26 is top view representation of a solar cell with a waffle-shaped handling layer with square apertures;

FIG. 27 is a top view representation of a solar cell with a waffle-shaped handling layer with circular apertures;



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stats Patent Info
Application #
US 20140014172 A1
Publish Date
01/16/2014
Document #
13936959
File Date
07/08/2013
USPTO Class
136256
Other USPTO Classes
International Class
01L31/0216
Drawings
31


Wafer


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