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Pixel and method for feedback based resetting of a pixel

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Pixel and method for feedback based resetting of a pixel


A storage system, a non-transitory computer readable medium and a method for pre-fetching. The method may include presenting, by a storage system and to at least one host computer, a logical address space; determining, by a fetch module, to fetch a certain data portion from a data storage device to a cache memory of the storage system; determining, by a pre-fetch module, whether to pre-fetch at least one additional data portion from at least one data storage device to the cache memory based upon at least one characteristic of a mapping tree that maps one or more contiguous ranges of addresses related to the logical address space and one or more contiguous ranges of addresses related to the physical address space; and pre-fetching the at least one additional data portions if it is determined to pre-fetch the at least one additional data portions.
Related Terms: Computer Readable Data Storage Host Computer Mapping Storage Device Address Space Cache Cache Memory Contiguous Logical Address

USPTO Applicaton #: #20140002701 - Class: 348294 (USPTO) -


Inventors: Vladimir Koifman

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The Patent Description & Claims data below is from USPTO Patent Application 20140002701, Pixel and method for feedback based resetting of a pixel.

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FIELD OF THE INVENTION

The invention relates to methods for compensating for noises such as reset and KTC noises and to devices that have noise compensation capabilities.

BACKGROUND OF THE INVENTION

Digital cameras include a two-dimensional photo-detector array. A single pixel can include one or more photo-detectors as well as multiple transistors. Typical photo-detectors include photodiodes, phototransistors, photo-gates, hole accumulation diodes, pinned diodes, avalanche diodes, buried accumulation and transfer layer devices.

The performance of CMOS pixels is limited by their thermal noise. This noise is also known as reset noise of KTC noise. During a reset phase of the pixel a reset voltage is provided to the pixel and especially to a reset transistor of the pixel. When this reset phase ends the reset transistor enters a non-conductive stage and thermal noise is generated.

Various prior art pixels are known. The most commonly used pixels are either CCD pixels or CMOS pixels. Prior art CMOS pixels and two dimensional CMOS arrays are illustrated in the following U.S. patents which are incorporated herein by reference: U.S. Pat. No. 6,777,660 of Lee, titled “CMOS active pixel reset noise reduction”; U.S. Pat. No. 6,762,401 of Lee, titled “CMOS image sensor capable of increasing fill factor and driving method thereof”; U.S. Pat. No. 6,567,495 of Harada titled “solid-state imaging device and a method of reading a signal charge in a solid-state imaging device which can reduce smear and can provide an excellent image characteristics”; U.S. Pat. No. 6,750,912 of Tennant et al., titled “Active-passive imager pixel array with small groups of pixels having short common bus lines”; U.S. Pat. No. 6,697,111 of Kozlowski et al., titled “compact low-noise active pixel sensor with progressive row reset”; U.S. Pat. No. 6,665,013 of Fossum et al., titled “active pixel sensor having intra-pixel charge transfer with analog-to-digital converter”; U.S. Pat. No. 6,587,142 of Kozlowski et al., titled “low-noise active-pixel sensor for imaging arrays with high speed row reset”; U.S. Pat. No. 6,538,245 of Kozlowski, titled “amplified CMOS transducer for single photon read-out of photo-detectors”; U.S. Pat. No. 6,532,040 of Kozlowski et al., titled “low-noise active-pixel sensor for imaging arrays with high-speed row reset”; U.S. Pat. No. 5,892,540 of Kozlowski et al., titled “low noise amplifier for passive pixel CMOS imager”; U.S. Pat. No. 5,238,276 of Dhuse et al., titled “imaging system having a sensor array reset noise reduction mechanism” and U.S. Pat. No. 6,326,230 of Pain et al., titled “high speed CMOS imager with motion artifact suppression and anti-blooming”

Correlated double sampling is a well known technique that can reduce thermal noise but it is based upon dedicated components that enable sampling of various signals. Furthermore—it is applicable to roller shutter pixel arrays in which different pixels are exposed to light during different periods and is not applicable to global shutter arrays in which all pixels are exposed to light during the same period.

There is a need to provide efficient means to improve pixel performances.

SUMMARY

OF THE INVENTION

According to an embodiment of the invention a method for reset noise compensation may be provided and may include (a) resetting a photodiode of the pixel by activating a first transistor connected to the photodiode at a first node; (b) setting a voltage of a second node to a predefined value by activating a third transistor that couples the second node to a first conductor that is connected to a voltage source; (c) deactivating the first transistor and activating a second transistor that is connected between the first node and the second node; (d) deactivating the third transistor and measuring the voltage of the second node to provide a measurement result, by activating a fourth transistor and a fifth transistor, wherein the fourth transistor is connected to the second node and to the fifth transistor and wherein the first transistor is connected to the first conductor; (e) evaluating, based upon the measurement result, the predefined value and a gain factor, a value of a compensation signal to be provided to a feedback node that is connected to the second node via a feedback capacitor; wherein the gain factor is indicative of a ratio between changes in a voltage of the feedback node and changes induced in the voltage of the second node as a result of the changes in the voltage of the feedback node; and (f) providing the compensation signal to the feedback node.

The method may one or more iterations of noise compensation, measurements of second node voltage and additional compensation.

The method may include (g) measuring, after completion of the providing of the compensation signal, the voltage of the second node to provide another measurement result; (h) determining whether to provide to the second node another compensation signal; and (i) if it is determined to provide the other compensation signal then evaluating a value of the other compensation signal and providing the other compensation signal to the second node.

Additional embodiments of the invention include a device arranged to execute the method described above, including any stages—and any combinations of same. For example, the device may include an array of pixels and a control unit. The array of pixels may include multiple ideally identical pixels.

The pixel may include a photodiode and first till fifth transistors; wherein the photodiode, the first transistor and the second transistor are connected to a first node; wherein the second transistor, third transistor and fourth transistor are connected to a second node; wherein the fifth transistor is connected between the fourth transistor and a first conductor. The control circuit may be arranged to: (a) activate the first transistor to facilitate a reset of the photodiode; (b) activate the third transistor to set a voltage of a second node to a predefined value; (c) deactivate the first transistor and activate the second transistor; (d) deactivate the third transistor and activate the fourth and fifth transistors to allow a reception of a fifth transistor signal indicative of the voltage of the second node; (e) measure the fifth transistor signal to provide a measurement result; (f) evaluate, based upon the measurement result, the predefined value and a gain factor, a value of a compensation signal to be provided to a feedback node that is connected to the second node via a feedback capacitor; wherein the gain factor is indicative of a ratio between changes in a voltage of the feedback node and changes induced in the voltage of the second node as a result of the changes in the voltage of the feedback node; and (g) provide the compensation signal to the feedback node.

The control circuit is arranged to (h) deactivate the third transistor and activate the fourth and fifth transistors to allow an another reception of the fifth transistor signal; (i) measure the fifth transistor signal to provide another measurement result; (j) determine whether to provide to the second node another compensation signal; and if it is determined to provide the other compensation signal then (k) evaluate a value of the other compensation signal and provide the other compensation signal to the second node.

The gain factor may be smaller than twenty percent, may range between ten percent and two percent, may be smaller than ten percent or have other values.

According to an embodiment of the invention the pixel may include the feedback node and the control circuit may be arranged to provide the compensation signal to the feedback node of the pixel by activating a sixth transistor (of the pixel) that is connected to the feedback node.

According to an embodiment of the invention the pixel the feedback node can belong to another pixel. That other pixel can be adjacent to the pixel, can belong to an adjacent row, to a non-adjacent row, and the like.

The feedback node of the other pixel can be connected between a fourth transistor and a fifth transistor of the other pixel.

The pixel can include a feedback node that is used for compensating noise of a further pixel. The feedback node can be connected to a second transistor of the other pixel.

The pixel may belong to an array of pixels that are activated simultaneously.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

FIG. 1 illustrates a device and a pixel of the device according to an embodiment of the invention;

FIG. 2 illustrates multiple pixels according to an embodiment of the invention;

FIG. 3 illustrates multiple pixels according to an embodiment of the invention;

FIG. 4 illustrates a method according to an embodiment of the invention; and

FIGS. 5-7 illustrate methods according to an embodiment of the invention.

It will be appreciated that for simplicity and clarity of illustration, elements shown in the figure s have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figure s to indicate corresponding or analogous elements.

DETAILED DESCRIPTION

OF THE DRAWINGS

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.

It will be appreciated that for simplicity and clarity of illustration, elements shown in the figure s have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figure s to indicate corresponding or analogous elements.

Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

Additional embodiments of the invention include a device arranged to execute the method described above, including any stages—and any combinations of same. For example, the device may include an array of pixels and a control unit. The array of pixels may include multiple ideally identical pixels.

FIG. 1 illustrates a device and a pixel of the device according to an embodiment of the invention.

Device 10 includes a pixel array 20 and a control circuit 30. The pixel array 20 may include multiple pixels that are arranged in rows and columns. The pixels are ideally identical to each other—under perfect manufacturing conditions the pixels should be exactly equal to each other.

FIG. 1 illustrates a pixel 40 of the pixel array 20. The pixel 40 includes a photodiode 60 and first till fifth transistors 51-56. The photodiode 60, the first transistor 51 and the second transistor 52 are connected to a first node 71. The second transistor 51, third transistor 53 and fourth transistor 54 are connected to a second node 72. The fifth transistor 55 is connected between the fourth transistor 54 and a first conductor 81.

The control circuit 30 may be arranged to: (a) activate the first transistor 51 to facilitate a reset of the photodiode 60, (b) activate the third transistor 53 to set a voltage of a second node 72 to a predefined value; (c) deactivate the first transistor 51 and activate the second transistor 52; (d) deactivate the third transistor 53 and activate the fourth and fifth transistors 54 and 55 to allow a reception of a fifth transistor signal 95 indicative of the voltage of the second node 72; (e) measure the fifth transistor signal 95 to provide a measurement result; the fifth transistor signal can be current (as in the case of FIG. 1) or voltage; (f) evaluate, based upon the measurement result, the predefined value and a gain factor, a value of a compensation signal 96 to be provided to a feedback node 74 that is connected to the second node 72 via a feedback capacitor 90; wherein the gain factor is indicative of a ratio between changes in a voltage of the feedback node 74 and changes induced in the voltage of the second node 72 as a result of the changes in the voltage of the feedback node 74; and (g) provide the compensation signal 96 to the feedback node 74. The compensation signal changes the voltage of the feedback node 74 and this in turn changes (by the gain factor) the voltage of the second node 72 and thus compensates (reduced or even eliminates) any noises introduced to the second node 72 due to the reset and the activation of the second transistor.

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stats Patent Info
Application #
US 20140002701 A1
Publish Date
01/02/2014
Document #
13535379
File Date
06/28/2012
USPTO Class
348294
Other USPTO Classes
348E05091
International Class
04N5/335
Drawings
8


Computer Readable
Data Storage
Host Computer
Mapping
Storage Device
Address Space
Cache
Cache Memory
Contiguous
Logical Address


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