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Lattice matching layer for use in a multilayer substrate structure

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Lattice matching layer for use in a multilayer substrate structure


A lattice matching layer for use in a multilayer substrate structure comprises a lattice matching layer. The lattice matching layer includes a first chemical element and a second chemical element. Each of the first and second chemical elements has a hexagonal close-packed structure at room temperature that transforms to a body-centered cubic structure at an α-β phase transition temperature higher than the room temperature. The hexagonal close-packed structure of the first chemical element has a first lattice parameter. The hexagonal close-packed structure of the second chemical element has a second lattice parameter. The second chemical element is miscible with the first chemical element to form an alloy with a hexagonal close-packed structure at the room temperature. A lattice constant of the alloy is approximately equal to a lattice constant of a member of group III-V compound semiconductors.
Related Terms: Semiconductor Lattice C Alloy Lattice Semiconductors

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USPTO Applicaton #: #20130333611 - Class: 117 6 (USPTO) - 12/19/13 - Class 117 
Single-crystal, Oriented-crystal, And Epitaxy Growth Processes; Non-coating Apparatus Therefor > Processes Of Growth From Solid Or Gel State (e.g., Solid Phase Recrystallization) >At Pressure Above 1 Atmosphere

Inventors: Indranil De, Francisco Machuca

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The Patent Description & Claims data below is from USPTO Patent Application 20130333611, Lattice matching layer for use in a multilayer substrate structure.

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CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority of provisional applications 61/662,918, filed on Jun. 22, 2012 and 61/659,944, filed on Jun. 14, 2012, the contents of which are incorporated herein by reference in their entireties.

TECHNICAL FIELD

The example embodiments of the present invention generally pertain to semiconductor materials, methods, and devices, and more particularly to a multilayer substrate structure for epitaxial growth of group III-V compound semiconductors.

BACKGROUND

Group III-V compound semiconductor, such as gallium nitride (GaN), gallium arsenide (GaAs), indium nitride (InN), aluminum nitride (AlN) and gallium phosphide (GaP), are widely used in the manufacture of electronic devices, such as microwave frequency integrated circuits, light-emitting diodes, laser diodes, solar cells, high-power and high-frequency electronics, and opto-electronic devices. To improve throughput and reduce manufacturing cost it is desired to increase size (e.g., diameter) of substrates. Because growing III-V compound semiconductors of large size is very expensive a great number of foreign materials including metals, metal oxides, metal nitrides as well as semiconductors, such as silicon carbide (SiC), sapphire and silicon, are commonly used as substrates for epitaxial growth of III-V compound semiconductors.

However, epitaxy growth of group III-V compound semiconductors (e.g., GaN) on substrates (e.g., sapphire) poses many challenges on crystalline quality (e.g., grain boundaries, dislocations and other extended defects, and point defects) of the epitaxial layers due to lattice mismatch and coefficient of thermal expansion mismatch between the GaN layer and the underlying substrate, a foreign material. Differences in the coefficient of thermal expansion between the GaN layer and the underlying substrate result in large curvatures across the wafer, resulting during and post processing upon returning to room temperature, and the large mismatch in lattice constants leads to a high dislocation density, unwanted strain and defects propagating into the epitaxial GaN layer. In order to cope with these problems, stress relaxation strategies are employed, such as growing buffer layers between the GaN layer and the sapphire substrate, or counter balancing compressive and tensile strain by alternating appropriate material layers. However, by adding the buffer layer or stress relieving layers, the dislocation density may remain high and the manufacturing cost and complexity increases significantly because of the use of the same deposition techniques involved in growing the active device layers.

BRIEF

SUMMARY

According to one exemplary embodiment of the present invention, a multilayer substrate structure comprises a lattice matching layer. The lattice matching layer includes a first chemical element and a second chemical element. Each of the first and second chemical elements has a hexagonal close-packed structure at room temperature that transforms to a body-centered cubic structure at an α-β phase transition temperature higher than the room temperature. The hexagonal close-packed structure of the first chemical element has a first lattice parameter. The hexagonal close-packed structure of the second chemical element has a second lattice parameter. The second chemical element is miscible with the first chemical element to form an alloy with a hexagonal close-packed structure at room temperature. A lattice constant of the alloy is approximately equal to a lattice constant of a member of group III-V compound semiconductors.

According to one exemplary embodiment of the present invention, a method of fabricating a multilayer substrate structure comprises growing a lattice matching layer. The lattice matching layer includes a first chemical element and a second chemical element. Each of the first and second chemical elements has a hexagonal close-packed structure at room temperature that transforms to a body-centered cubic structure at an α-β phase transition temperature higher than room temperature. The hexagonal close-packed structure of the first chemical element has a first lattice parameter. The hexagonal close-packed structure of the second chemical element has a second lattice parameter. The second chemical element is miscible with the first chemical element to form an alloy with a hexagonal close-packed structure at room temperature. A lattice constant of the alloy is approximately equal to a lattice constant of a member of group III-V compound semiconductors.

According to one exemplary embodiment of the present invention, a multilayer substrate structure comprises a lattice matching layer. The lattice matching layer includes a first chemical element and a second chemical element. Each of the first and second chemical elements has a hexagonal close-packed structure at room temperature that transforms to a body-centered cubic structure at an α-β phase transition temperature higher than the room temperature. The hexagonal close-packed structure of the first chemical element has a first lattice parameter. The hexagonal close-packed structure of the second chemical element has a second lattice parameter. The second chemical element is miscible with the first chemical element to form an alloy with a hexagonal close-packed structure at room temperature. A linear relation exists between the first and second chemical elements and their associated lattice parameters at constant temperature to allow lattice constant of the alloy approximately equal to that of a group III-V compound semiconductor.

BRIEF DESCRIPTION OF THE DRAWING(S)

Having thus described the example embodiments of the present invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

FIGS. 1A-1D illustrate cross-sectional views of exemplary multilayer substrate structures in accordance with exemplary embodiments;

FIG. 2A illustrates a schematic of a hexagonal close-packed structure;

FIG. 2B illustrates a schematic of a unit cell showing lattice constants;

FIG. 3 illustrates a periodic table; and

FIG. 4 illustrates a phase diagram correlation between transition temperature and atomic percentage of constituent elements in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

The various embodiments are described more fully with reference to the accompanying drawings. These example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to readers of this specification having knowledge in the technical field. Like numbers refer to like elements throughout.



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stats Patent Info
Application #
US 20130333611 A1
Publish Date
12/19/2013
Document #
13794285
File Date
03/11/2013
USPTO Class
117/6
Other USPTO Classes
423409, 2525191, 423412, 428220, 117 84, 117108, 117103, 117 88, 2041921, 117 13, 117 37, 117 81, 117/9, 117 95, 205188
International Class
/
Drawings
4


Semiconductor
Lattice C
Alloy
Lattice
Semiconductors


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