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Etsoi with reduced extension resistance

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Etsoi with reduced extension resistance


A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.
Related Terms: Semiconductor Electrode Erosion Germanium Semiconductor Device Silicon Semiconductor Devices

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USPTO Applicaton #: #20130320447 - Class: 257347 (USPTO) - 12/05/13 - Class 257 
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Field Effect Device >Having Insulated Electrode (e.g., Mosfet, Mos Diode) >Single Crystal Semiconductor Layer On Insulating Substrate (soi)

Inventors: Bin Yang, Man Fai Ng

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The Patent Description & Claims data below is from USPTO Patent Application 20130320447, Etsoi with reduced extension resistance.

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TECHNICAL FIELD

The present disclosure relates to silicon-on-insulator (SOT), particularly extremely thin silicon-on-insulator (ETSOI), and FinFET semiconductor devices with reduced extension resistance. The present disclosure is particularly applicable to semiconductors for 22 nanometer (nm) node devices and beyond.

BACKGROUND

The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of lightly doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.

The drive for high performance requires high speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. Metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion. However, simply replacing polysilicon gate electrodes with metal gate electrodes may engender issues in forming the metal gate electrode prior to high temperature annealing to activate the source/drain implants, as at a temperature in excess of 900° C. This fabrication technique may degrade the metal gate electrode or cause interaction with the gate dielectric, thereby adversely impacting transistor performance.

Replacement gate techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes. For example, an amorphous silicon (a-Si) or polysilicon gate is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, the polysilicon is removed and replaced with a metal gate.

For improving low off-state leakage current, due to the fundamentally superior short channel control characteristics, ETSOI and FinFET are the best candidates for complementary metal-oxide-semiconductors (CMOS) beyond the 22 nm node. As illustrated in FIG. 1, an ETSOI semiconductor device begins with an ETSOI substrate comprising a silicon substrate 101, a buried oxide layer 103, and a thin silicon layer 105. A gate electrode 107 (including, from top to bottom, silicon nitride (SiN) cap 109, a-Si layer 111, and gate oxide layer 113) is patterned on the silicon layer of the ETSOI substrate. The silicon layer thickness is typically between about 6 nm and about 8 nm.

Adverting to FIG. 2A, during the patterning of gate electrode 107, the region 201 immediately adjacent to gate 107 is eroded by about 1 nm by the overetch process needed to insure that no gate-stack residual left in the non-gated area. Then, in defining spacers 203, illustrated in FIG. 2B, the ETSOI is thither thinned by about 1 to about 2 nm from the spacer etch/strip/clean steps, i.e., when the resist is stripped post halo extension implants. This causes very thin “bottle-neck” ETSOI extension regions 205 that have a high extension resistance (Rext) that is a times higher than a conventional SOI or bulk CMOS.

An approach to mitigate the high ETSOI Rext is to form a raised source/drain 207 on the ETSOI by an epitaxial growth process. However, since the raised source/drain epitaxial growth does not change the silicon thickness at the thinnest portion of the extension, under the spacers 203 that separate the gate electrode from the source/drain epitaxial growth, the “bottle-neck” region cannot be remedied merely by forming raised source/drain 207. Rext is still dominated by the extension region resistance. High Rext limits the application of ETSOI to low power applications. In order to enable ETSOI for high performance logic devices, the Rext must be significantly reduced.

A need therefore exists for methodology enabling the formation of an SOI semiconductor device which is compatible with high-k metal gate integration and which has low off-state leakage current and reduced Rext, and for the resulting device.

SUMMARY

An aspect of the present disclosure is an improved method of fabricating a semiconductor exhibiting improved short channel effects and reduced extension.

Another aspect of the present disclosure is a semiconductor exhibiting improved short channel effects and reduced extension resistance.

Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.

According to the present disclosure, some technical effects may be achieved in part by a method of fabricating a semiconductor, the method comprising: forming an SOI substrate; epitaxially forming a silicon-containing layer on the SOI substrate; and forming a gate electrode on the epitaxially formed silicon-containing layer.

Aspects of the present disclosure include the SOI substrate comprising a thin layer of silicon, as at a thickness of about 6 nm to about 8 nm, on a silicon substrate, with a buried oxide layer (BOX) therebetween. Additional aspects include removing the gate electrode and forming a replacement gate electrode. Other aspects include forming a first spacer on each side of the gate electrode. Further aspects include forming raised source/drain regions adjacent each first spacer. Another aspect includes forming the source/drain regions as faceted source/drain regions. Other aspects include forming a second spacer on each first spacer; and forming a silicide on the source/drain regions. Another aspect includes removing the gate electrode, thereby exposing a portion of the silicon-containing layer; and removing the exposed portion of the silicon-containing layer. Additional aspects include removing the exposed portion of the silicon-containing layer by selectively etching the silicon-containing layer; and stopping on the SOI substrate. Other aspects include forming a replacement gate electrode on the SOI substrate between the first spacers. Further aspects include the replacement gate electrode comprising a high-k metal gate electrode. Additional aspects include forming the silicon-containing layer by epitaxially growing silicon germanium to a thickness of about 8 nm to about 12 nm.

Another aspect of the present disclosure is a semiconductor device comprising: an SOI substrate; a gate electrode formed on the SOI substrate; an epitaxially formed silicon-containing layer on the SOI substrate, surrounding the gate electrode.

Aspects include the SOI substrate comprising a thin silicon layer, as at a thickness of about 6 nm to about 8 nm, on a silicon substrate with a BOX therebetween. Further aspects include a first spacer on the silicon-containing layer on each side of the gate electrode and a source/drain region on the silicon-containing layer, adjacent each first spacer. Another aspect includes the source/drain regions being raised and faceted. Other aspects include a second spacer on each first spacer. Additional aspects include the gate electrode comprising a high-k metal gate electrode. Further aspects include the silicon-containing layer comprising silicon germanium at a thickness of about 8 nm to about 12 nm.

Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

FIG. 1 schematically illustrates a conventional ETSOI semiconductor device;

FIGS. 2A and 2B schematically illustrate ETSOI erosion during formation of an ETSOI semiconductor device; and

FIGS. 3 through 14 schematically illustrate sequential steps of a method in accordance with an exemplary embodiment.



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stats Patent Info
Application #
US 20130320447 A1
Publish Date
12/05/2013
Document #
13963634
File Date
08/09/2013
USPTO Class
257347
Other USPTO Classes
438151
International Class
/
Drawings
8


Semiconductor
Electrode
Erosion
Germanium
Semiconductor Device
Silicon
Semiconductor Devices


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