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Disguising test pads in a semiconductor package

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Disguising test pads in a semiconductor package


A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads.
Related Terms: Semiconductor

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USPTO Applicaton #: #20130033284 - Class: 32476201 (USPTO) - 02/07/13 - Class 324 


Inventors: Arie Frenklakh

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The Patent Description & Claims data below is from USPTO Patent Application 20130033284, Disguising test pads in a semiconductor package.

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CLAIM OF PRIORITY

This application is a divisional of U.S. patent application Ser. No. 13/041,895 filed on Mar. 7, 2011 entitled DISGUISING TEST PADS IN A SEMICONDUCTOR PACKAGE, which is a divisional of U.S. patent application Ser. No. 11/958,059 filed on Dec. 17, 2007 entitled DISGUISING TEST PADS IN A SEMICONDUCTOR PACKAGE, which applications are incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention relate to a semiconductor package and method of fabricating same.

2. Description of the Related Art

The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones. Electrically Erasable Programmable Read Only Memory (EEPROM), including flash EEPROM, and Electrically Programmable Read Only Memory (EPROM) are among the most popular non-volatile semiconductor memories.

As with most storage devices, defects occur to some of the semiconductor memory components or storage areas during fabrication. For example, the individual storage elements or memory cells of a semiconductor memory array may be defective. Additionally, the peripheral circuitry for the memory array, including word lines, bit lines, decoders, etc., may be defective, rendering the associated storage elements defective as well.

Portions of a typical semiconductor memory fabrication process are shown in the prior art flowchart of FIG. 1. In step 20, wafer level testing is conducted prior to packaging the memory chips to form memory devices. A wafer can include hundreds or thousands of memory chips, each of which will include a memory array and peripheral components such as the control and logic circuits for accessing the memory cells of the array. During wafer level testing 20, the functionality of the memory chips is tested so that defective components are not needlessly integrated into a packaged device.

After wafer level testing 20, the wafer is divided into individual memory chips and one or more of the memory chips are mounted to a substrate, possibly along with a controller chip, and electrical connections are formed in step 22. In particular, the substrate may include a conductance pattern of photolithographically defined electrical traces. The controller and memory chips may be die bonded and electrically connected to the substrate to allow electrical communication between the controller chip and memory chips, as well as between the chip set and the outside world. After bonding and electrical connection in step 22, the die and substrate may be packaged in step 24 by encapsulating the die and substrate in a molding compound.

The packaged memory devices are then subjected to burn-in and electrical test processes in steps 26 and 28, respectively. Burn-in is performed to stress the memory arrays and peripheral circuitry of the chips. Burn-in is typically conducted at elevated temperatures (e.g., 125° C.) at which high voltages are applied at various portions of each chip to stress and identify weaker elements. Those die packages passing burn-in may undergo an electrical test in step 28. Referring to FIG. 2, during the burn-in and/or electrical test, electrical function of a package 30 may be tested using a memory test pad matrix 32 provided within the package.

The memory test pad matrix 32 includes a plurality of electrical test pads 34 exposed through the molding compound and electrically coupled to the memory die within the package. During burn-in and/or electrical test, the package may be inserted into a socket on a test card, whereupon the test pads are contacted by probes to test the electrical properties and functioning of the semiconductor package to determine whether the finished semiconductor package performs per specification. FIG. 2 also shows a plurality of contact fingers 36 for electrical connection of the package 30 with the outside world.

Referring now to prior art FIG. 3, assuming the package passes electrical inspection, the memory test pad matrix 32 may then be covered, as for example by a sticker or ink-jet printing 40. Although data stored within the flash memory of semiconductor packages is encrypted, market research has revealed that memory card users are concerned over access to internal memory through the test pads. In particular, users are concerned that the test pads are not appropriately concealed and that their stored content is not appropriately protected when they see a sticker covering what they know to be the test pads. It is known to address this concern by eliminating the test pads and testing the memory through an external interface. However, this approach is a much slower process and less efficient than testing via the test pads 34.

SUMMARY

OF THE INVENTION

An embodiment of the present invention relates to a method of disguising test pads of a semiconductor package and a semiconductor package formed thereby. The semiconductor package includes a substrate having a conductive pattern. Test pads are defined in the conductive pattern for allowing electrical test of the completed semiconductor package. In accordance with embodiments of the invention, the test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads. Where formed into letters, a single test pad may form an entire letter. Alternatively, a plurality of test pads together may form a single letter.

Alternative embodiments of the present invention relate to a method of disguising a cover for test pads of a semiconductor package, and a semiconductor package formed thereby. After the completed semiconductor package is tested via the test pads, the memory test pads may be covered with a cover. In accordance with this alternative embodiment, the cover may include a marking, such as text and/or an image. The purpose of the marking is to disguise the fact that the cover is provided to cover test pads. In particular, by providing a marking on the cover, users may believe that the cover is provided as a label, solely for the purpose of presenting the marking. Thus, if the disguise is effective, users would have no reason to believe that the package includes easily accessible test pads.

In an alternative embodiment, the test pads may be formed in a non-standard location and/or a non-standard configuration. By placing the test pads in a non-standard location and/or configuration, and then covering the test pads with a cover bearing a marking as described above, this further disguises the purpose of the cover.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a prior art flowchart of a semiconductor fabrication process.

FIG. 2 is a bottom view of a prior art semiconductor package including test pads.

FIG. 3 is a bottom view of the prior art semiconductor package of FIG. 2, with the test pads covered with a conformal coating.

FIG. 4 is a flowchart of a process for fabricating a semiconductor package according to the present invention.

FIG. 5 is a bottom view of a semiconductor package for use in the present invention including disguised test pads.



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Previous Patent Application:
Probing device
Next Patent Application:
Methods for reliability testing of semiconductor devices
Industry Class:
Electricity: measuring and testing
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stats Patent Info
Application #
US 20130033284 A1
Publish Date
02/07/2013
Document #
13647585
File Date
10/09/2012
USPTO Class
32476201
Other USPTO Classes
International Class
01R31/26
Drawings
9


Semiconductor


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