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Multiplexed amplifier with reduced glitching


Title: Multiplexed amplifier with reduced glitching.
Abstract: In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths. ... Browse recent Texas Instruments Incorporated patents
USPTO Applicaton #: #20130021188
Inventors: Robert F. Payne



The Patent Description & Claims data below is from USPTO Patent Application 20130021188, Multiplexed amplifier with reduced glitching.




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stats Patent Info
Application #
US 20130021188 A1
Publish Date
01/24/2013
Document #
13554972
File Date
07/20/2012
USPTO Class
341162
Other USPTO Classes
International Class
03M1/34
Drawings
4


Your Message Here(14K)


Data Path
Duty Cycle
Glitch
Multiplex


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