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Multiplexed amplifier with reduced glitching

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Multiplexed amplifier with reduced glitching

In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths.
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USPTO Applicaton #: #20130021188
Inventors: Robert F. Payne

The Patent Description & Claims data below is from USPTO Patent Application 20130021188, Multiplexed amplifier with reduced glitching.

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US 20130021188 A1
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