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Apparatus for pseudo-return-to-zero modulation

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Apparatus for pseudo-return-to-zero modulation


A Pseudo-Return-to-Zero modulator is provided with a narrow pulse clock generator, a modulator driver, and an optical modulator. The narrow pulse clock generator generates a narrow pulse clock of order n, where one of levels occupies half a symbol period and the other level occupies (n−1) plus half a symbol period, n being equal to or more than two. The modulator driver generates an electrical signal in response to binary data and the narrow pulse clock. The optical modulator modulates an optical carrier in response to the electrical signal so that the modulated optical carrier is in a PRZ(n) format.
Related Terms: Binary Data Optical Modulator

Browse recent Nec Corporation patents - Tokyo, JP
Inventor: Emmanuel Le Taillandier De Gabory
USPTO Applicaton #: #20120320442 - Class: 359238 (USPTO) - 12/20/12 - Class 359 


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The Patent Description & Claims data below is from USPTO Patent Application 20120320442, Apparatus for pseudo-return-to-zero modulation.

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TECHNICAL FIELD

The present invention relates generally to optical communications technologies and more particularly to Pseudo-Return-to-Zero Modulation scheme.

BACKGROUND ART

Return-to-Zero (RZ) and Non-Return-to-Zero (NRZ) are widely used as the modulation name when they are implemented for On-Off Keying (OOK). In the case of OOK for optical communications, the signal is carried by a light carrier and the coding is performed as: (a) Light is emitted during the symbol period when the coded bit is “1”. (b) No light is emitted during the symbol period when the coded bit is “0”.

However, when consecutive identical bits appear, RZ and NRZ implementations are widely used: (a) Light is temporary shut (no light emitted) between consecutive coded “1” bits: this is RZ. (b) Light is not shut between consecutive coded “1” bits: this is NRZ. Apparatuses for implementing the RZ modulation are disclosed in Japanese Unexamined Patent Publications No. H09-230290 and 2004-180343, for example.

In addition, RZ and NRZ can be used in conjunction with phase modulation schemes such as Binary Phase Shift Keying (BPSK), QPSK (Quaternary Phase Shift Keying), combination of Amplitude and Phase Modulation, such as 2ASK-4PSK, Quadrature Amplitude Modulation (QAM), and the like. Consecutively, if RZ is used in conjunction with the said modulation formats, the amplitude is forced to zero between consecutive symbols. In the same way, if NRZ is used with the said modulation formats, the amplitude is not forced to zero between consecutive symbols. Its value is decided according to the constellation map of the said modulation format. Note that from this point no distinction is made between Differential Phase Shift Keying (DPSK) and PSK, as the difference is only in data coding but optical signals are identical. Apparatuses for implementing the RZ-DPSK modulation are disclosed in Japanese Unexamined Patent Publications No. 2003-60580 and 2007-512748, for example.

Depending on the transmission line or condition, one may choose to implement either RZ or NRZ. On one hand, RZ is known has offering better receiver sensitivity, better tolerance to Polarization Mode Dispersion (PMD) impairments, and reduced effects of optical amplitude ripples between symbols. On the other hand, NRZ signals have narrower optical spectra, offering therefore better tolerance to filtering effects, or better tolerance to Chromatic Dispersion (CD).

Pseudo-Return-to-Zero of index n (PRZ(n)) has been introduced as the modulation scheme, where the amplitude of the lightwave signal is forced to zero every n symbols and not forced to zero for other cases. According to Le Taillandier de Gabory et al. (ECOC 2009, paper 3.4.4), PRZ enables to monitor intra-polarization skew for polarization multiplexed signals and also enables to discriminate the multiplex polarizations. Moreover, according to Le Taillandier de Gabory et al. (IEICE Society Conference 2009, paper B-10-85), PRZ enables to enhance to tolerance of optical polarization demultiplexing to first order Polarization Mode Dispersion (PMD).

According to the definition of PRZ(n), PRZ (1) can be identified as RZ and PRZ(∞) can be identified as NRZ. Therefore, in the scope of the present invention, we reduce PRZ(n) to the cases where n is finite and n is greater or equal to 2.

In PRZ(n) format, the amplitude returns to zero between consecutive symbols every n symbols and does not return to zero in the other cases, unless the symbol amplitude is zero or crosses zero. PRZ(n) format is not a RZ format of at a n-time slower clock frequency, as the amplitude is forced to zero and is relaxed at a very steep slope (same slope as RZ). PRZ(n) causes dips on the optical amplitude every n symbols. On the contrary, RZ format at a n time slower clock frequency would cause a n-time slower slope when the amplitude is forced to zero and would cause degradation of the quality of the transmission as the central part of symbols are affected by the slow slope of the amplitude change. Therefore, RZ at an n-time slower clock speed cannot be used as a substitute to PRZ(n).

A proposed way to generate PRZ(n) carving is to use the transitions of a PSK modulator between consecutive trains of n identical symbols. This configuration implies some disadvantages.

First, an additional optical modulator is needed to carve PRZ dips. Moreover, the additional modulator will require also Auto Bias Control (ABC) circuit in order to avoid drift of the bias point, and therefore degradation of the signal quality because of thermal drift or device aging. Therefore, such a scheme will increase both the size and the cost of an optical transmitter implementing PRZ carving.

Second, the additional optical modulator used to carve PRZ dips causes loss to the optical signal. Typically, the insertion loss is in the order of 6 dB. This causes, de facto a loss in optical signal to noise ratio of the emitter, and therefore this affects the quality of the emitted signal. One may want to compensate this loss by using a light source laser with a higher power for the output signal. If such a laser is available, its power consumption will be higher.

Third, the optical modulator used to imprint the data onto the optical carrier and the optical modulator used to cave PRZ dips will be separated by optical fiber. As the refractive index and length of the optical fiber changes with temperature, the synchronicity of both said modulator will be affected by temperature drifts, and therefore the quality of the emitted signal will suffer from temperature changes.

Fourth, integrated modulators for dual polarization (DP) are bound to be a cost effective solution, as encouraged by the standardization activities of the Optical I. Forum (OIF). However, as PSK modulators have a strong polarization dependent loss (PDL), the effective only solution to use a PSK modulator in conjunction with a DP modulator to carve PRZ dips, is to place the PSK modulator before the PRZ modulator. In that configuration, both polarizations will have the same PRZ carving at the same index. In that case, polarization discrimination based on the PRZ dips is no longer possible.

Fifth, in the case of high index n for the PRZ carving, typically when n is equal or greater than 8, carving PRZ (n) dips with a PSK modulator requires a wide and flat bandwidth characteristics for the modulator, as the transmission contains at the same time low frequency components, the long trains of constant amplitude occurring during the n constant symbol trains, and high frequency components, the PSK modulation transmission, by which the dips are curved occurring at the transition between opposite trains of n symbols. However, for 100 G PRZ-DP-QPSK, the baud rate is 25 Gbaud and in such case the PRZ carving may cause degradation on the emitted signal when n is in the order of 8 with standard PSK modulators. Imposing a tighter specification on the flatness or bandwidth of the modulator leads to an increase in cost.

Moreover, one could think of using a high speed Digital to Analog Converter (DAC) in order to control precisely the position of the emitted light signal on the constellation map, when the light signal is modulated by a Cartesian modulator; in order to carve PRZ dips in this manner, one would need to generate a signal coding the modulated symbol and the transition between symbols at the same time. This means that at least two values have to be generated by symbol, requiring a DAC operating for at least twice the baud rate. However, in the case of 100 Gb/s DP-QPSK modulation format, the baud rate is 25 Gbaud, therefore one would require at least a 50 Gb/s DAC to control at the same time the emitted symbol and the transition on the constellation map. These devices are not commercially available at this point, and when they will be, they will be at a high price and consume a high amount of electrical power.

However, there is room for improvement in simplicity, size, cost, emitted signal power, stability and functionality of PRZ carving apparatuses. There is a need for a simple, small-sized, cost effective, low loss, stable and versatile PRZ carving apparatus.

CITATION LIST Patent Literature

Japanese Unexamined Patent Publication No. H09-230290

Japanese Unexamined Patent Publication No. 2004-180343 Japanese Unexamined Patent Publication No. 2003-60580 Japanese Unexamined Patent Publication No. 2007-512748 Non-Patent Literature

Le Taillandier de Gabory et al., “Pseudo-Return-to-Zero Modulation Scheme: Application to the Compensation of Intra-Polarization Skew for PolMux Signals”, ECOC 2009, paper 3.4.4.

Le Taillandier de Gabory et al., “DGD Tolerance Enhancement of Optical Polarization Demultiplexing by using Pseudo-Return-to-Zero Modulation Scheme”, IEICE Society Conference 2009, paper B-10-85.

Le Taillandier de Gabory et al., “A Method of Accurately Optimizing the Timing of Phase Modulation in Wide Temporal Ranges for DQPSK Transmitters”, OFC 2009, paper JWA42.

Seimetz et al., “Coherent RZ-8PSK Transmission at 30 Gbit/s over 1200 km Employing Homodyne Detection with Digital Carrier Phase Estimation”, ECOC 2007, paper 08.3.4.

Zhou et al., “Cascaded two-modulus algorithm for blind polarization demultiplexing of 114-Gb/s PDM-8-QAM optical signals”, OFC 2009, paper OWG3.

Sano et al., “240-Gb/s Polarization-Multiplexed 64-QAM Modulation and Blind Detection Using PLC-LN Hybrid Integrated Modulator and Digital Coherent Receiver”, ECOC 2009, paper PDP 2.2.

SUMMARY

OF THE INVENTION

A Pseudo-Return-to-Zero modulator is provided with a narrow pulse clock generator, a modulator driver, and an optical modulator. The narrow pulse clock generator generates a narrow pulse clock of order n, where n is equal to or more than two and one of levels occupies half a symbol period and the other level occupies (n−1) plus half a symbol period. The modulator driver generates an electrical signal in response to binary data and the narrow pulse clock. The optical modulator modulates an optical carrier in response to the electrical signal so that the modulated optical carrier is in a PRZ(n) format.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1D are constellation maps of OOK, BPSK, QPSK and 8PSK, respectively;

FIG. 2A is an eye diagram for an NRZ signal;

FIGS. 2B to 2D are eye diagrams for PRZ signals;

FIG. 3 is a schematic representation of a narrow pulse clock generator generating a narrow pulse clock signal;

FIG. 4 is a representation of the time charts of the apparatus of FIG. 3;

FIG. 5 is a schematic representation of a modulator driver generating signals to drive a modulator carving PRZ dips on an optical carrier and modulating it;

FIG. 6 is a representation of the time charts of the modulator driver of FIG. 5;

FIG. 7 is a schematic representation of another modulator driver generating signals to drive a modulator carving PRZ dips on an optical carrier and modulating it;

FIG. 8 is a representation of the time chart of the modulator driver of FIG. 7;

FIG. 9 is a schematic representation of another modulator driver generating signals to drive a modulator carving PRZ dips on an optical carrier and modulating it;

FIG. 10 is a representation of the time chart of the modulator driver of FIG. 9;

FIG. 11 is a schematic representation of an exemplary configuration of a QPSK transmitter emitting PRZ(n)-QPSK modulated signal according to the present invention;

FIG. 12 is a schematic representation of an exemplary configuration of a DP-QPSK transmitter emitting PRZ(n)-DP-QPSK modulated signal according to the present invention;

FIG. 13 is a schematic representation of an exemplary configuration of an OOK transmitter emitting PRZ(n)-OOK modulated signal according to the present invention;

FIG. 14 is a schematic representation of an exemplary configuration of a BPSK transmitter emitting PRZ(n)-BPSK modulated signal according to the present invention;

FIG. 15 is a schematic representation of an exemplary configuration of a high order modulation transmitter emitting a PRZ(n) carved signal according to the present invention; and

FIG. 16 is a schematic representation of an exemplary configuration of a transponder emitting PRZ(n) carved signal according to the present invention.

DESCRIPTION OF EMBODIMENTS

In one exemplary embodiment, a modulator driver is provided which receives binary data and feeds an electrical signal to an optical modulator, so that the optical carrier will be modulated according to the binary data and PRZ(n) carving will be performed on the optical carrier. The modulator driver generates an electrical signal according to the provided data and clock signals. The electrical signal is fed to the optical modulator. The light signal modulated by the modulator will carry the information of the binary data and will have dips carved according to PRZ(n) carved on the optical amplitude.

In one exemplary embodiment, the optical modulator is an intensity modulator and the modulation format is OOK. The modulator driver generates an electrical signal according to the provided data and clock signals. Said electrical signal is fed to the intensity modulator to emit a PRZ(n)-OOK signal.

In another exemplary embodiment, the optical modulator is a PSK modulator and the modulation format is BPSK. The modulator driver generates an electrical signal according to the provided data and clock signals. Said electrical signal is fed to the PSK modulator to emit a PRZ(n)-BPSK signal.

In still another exemplary embodiment, the optical modulator is a PSK modulator, and is followed by other phase modulators. An example of this modulation scheme is given by Le Taillandier de Gabory et al. (OFC 2009, paper JWA42), where a PSK modulator is followed by a phase modulator to generate a QPSK signal in a serial modulation scheme. The modulator driver generates an electrical signal according to the provided data and clock signals. The electrical signal is fed to the PSK modulator. The PSK modulator modulates the light according to PRZ(n)-BPSK format and the modulation format at the output of the last modulator is PRZ(n)-xPSK, where x is equal or greater than 4.

In still another exemplary embodiment, the optical modulator is a Cartesian modulator and the modulation format is QPSK (See FIG. 11). Two modulator drivers are used; one receives the In Phase (I) data and the other receives the Quadrature Phase (Q) data for the QPSK modulation. Both modulator drivers receive the same clock at the baud rate. The modulator driver receiving the I data generates an electrical signal according to the provided data and clock signals. The electrical signal is fed to the nested modulator corresponding to the I arm of the Cartesian modulator. In the same way, the modulator driver receiving the Q data generates an electrical signal according to the provided data and clock signals. The electrical signal is fed to the nested modulator corresponding to the Q arm of the Cartesian modulator to emit a PRZ(n)-QPSK signal from the Cartesian modulator.

In still another exemplary embodiment, the optical modulator is a Cartesian modulator, followed by other phase modulations. An example of this modulation scheme is given by Seimetz et al. (ECOC 2007, paper 08.3.4), where a QPSK Cartesian modulator is followed by a phase modulator to generate an 8PSK signal in a serial modulation scheme. Another example is given by Zhou et al. (OFC 2009, paper OWG3) where a Cartesian modulator is followed by a phase modulator to generate an 8QAM signal in a serial modulation scheme. Two modulator drivers are used to generate the I data and Q data of the Cartesian modulator. The Cartesian modulator generates a signal modulated according to the I and Q data provided to the modulator drivers and having PRZ(n) dips carved. The modulation format at the output of the last modulator is PRZ(n)-xPSK. In still another exemplary embodiment, the modulation format at the output of the last modulator is PRZ (n)-xQAM.

In still another exemplary embodiment, the optical modulator is an xQAM modulator consisting in several nested Cartesian QPSK modulators. An example is given by Sano et al. (ECOC 2009, paper PDP 2.2), where 64QAM signal is generated in this way. Each nested Cartesian modulator has two modulator drivers, one for the I data and one for the Q data. The lightwave signal is modulated as PRZ(n)-xQAM by the modulator.

In one exemplary embodiment, the optical modulator is dual driven. The modulator driver generates an electrical signal for the positive input and one signal for the negative input of the dual drive modulator. The optical signal emitted by the modulator has PRZ(n) dips carved on the optical amplitude.

In an alternative exemplary embodiment, the optical modulator is single driven. The modulator driver generates a single electrical signal to be fed to the modulator. The optical signal after the modulator has PRZ(n) dips carved on the optical amplitude.

In one exemplary embodiment, the modulator driver generates an electrical signal so that the optical signal emitted by the optical modulator is modulated according to the data provided to the modulator driver and so that the optical amplitude is forced to zero every n symbol, carving therefore PRZ(n) dips.

In an alternative exemplary embodiment, the modulator driver generates an electrical signal so that the optical signal emitted by the optical modulator is modulated according to the data provided to the modulator driver and so that the optical amplitude is forced to pass by the zero point every n symbol, carving therefore PRZ (n) symbols.

In the following, exemplary embodiments of the present invention will be described below in detail with reference to attached drawings.

FIGS. 1A to 1D are constellation maps for different modulation formats. FIG. 1A is the constellation map of OOK, where the numeral 100 denotes the “0” symbol and the numeral 101 denotes the “1” symbol of OOK.

FIG. 1B is the constellation map of BPSK, where the numeral 110 denotes the null point, where the optical amplitude is zero, the numeral 111 denotes the “1” symbol and the numeral 112 denotes the “0” symbol. When generated from a Mach-Zehnder modulator, a transition from the “1” symbol 111 to the “0” symbol 112 passes through zero. Therefore, whereas the “1” symbol 111 and “0” symbol 112 have the same optical amplitude, any inversion of the data induces a pass through the null point 110.

FIG. 1C is the constellation map of QPSK, where the numeral 130 denotes the null point and the numerals 131, 132, 133 and 134 denote the four different phases, which codes two binary bits onto a symbol. All symbols have the same optical amplitude; however, a transition between symbols can induce three different amplitude levels. Namely, in the case where the constellation map is generated by a Cartesian modulator, composed of two nested QPSK modulators, the transitions between two symbols are as follows: when the phase is constant between two symbols, the optical amplitude stays constant at the transition; when the phase changes by pi radians, the signal crosses the null point 130, which causes the transition between symbols to have a null amplitude; when the phase between symbols changes by pi/2 radians, the amplitude is in a medium amplitude state, lowering from the amplitude at the symbol center, but still being higher than 0.

FIG. 1D is the constellation map of 8PSK modulation, where the numeral 140 denotes the null point and the numerals 141 to 148 denote the eight phases which code three binary bits of data on each symbol.

FIGS. 2A to 2D are eye diagrams representing the optical amplitude on 14 symbol periods. The diagram 210 is a measurement of an eye diagram for a 55 GB/s NRZ-QPSK signal, where the QPSK modulation was generated with a Cartesian modulator. The symbol period is 36.36 ps. Between every two symbols, the three possible amplitude levels correspond to the three possible amplitudes for transitions between coded phases described with the constellation of FIG. 1D.

The diagram 220 is a measurement of an eye diagram for a 55 Gb/s PRZ(4)-QPSK signal, where the QPSK modulation is identical to the one on the diagram 210. The numeral 221 denotes a PRZ(4) dip, which appear every four symbols for PRZ(4), therefore every 145.45 ps.

The diagram 230 is a measurement of an eye diagram for a 55 Gb/s PRZ(8)-QPSK signal, where the QPSK modulation is identical to the one on the diagram 210. The numeral 231 denotes a PRZ(8) dip, which appear every eight symbols for PRZ(8), therefore every 290.91 ps.

The diagram 240 is a measurement of an eye diagram of 110 Gb/s PRZ(4,8)-DP-QPSK, which is the polarization multiplexed signal of the signals measured on the diagrams 220 and 230, where the symbol of the signals and the PRZ dips are synchronous. The numeral 241 denotes the peaks of PRZ(8), which are synchronous with half of the dips of PRZ(4). The numeral 242 denotes the other half of the dips of PRZ(4), which are not synchronous to the PRZ(8) dips, therefore synchronous with a standard three possible level QPSK transition.

FIG. 3 is a schematic representation of a narrow pulse clock generator used to generate a narrow pulse clock. We call a narrow pulse clock of order n, where one of the levels occupies half a symbol period and the other level occupies (n−1) plus half a symbol period. The period of the narrow pulse clock of order n is n times the symbol period. With this definition, a narrow pulse clock of order 1 is a 50% duty cycle clock. Therefore, from here on, we consider only a narrow pulse clock of finite order n, where n is greater or equal to 2.

The narrow pulse clock generator 300 receives an electrical signal 301 which is a standard 50% duty clock of frequency f. The electrical signal 301 is divided twice by dividers 310 and 311. One of the resultant tributaries is divided in frequency by n, by a frequency divider 320. Therefore, the electrical signal 303 is a 50% duty cycle clock at the frequency f/n. The electrical signal 303 is fed to the D input of a D flip-flop (DFF) 330, and the clock at f is fed to the clock input. The output signal Q of the D flip-flop 330, which is denoted by the numeral 304, is divided by a divider 312. One resultant tributary is fed to the D input of a D flip-flop 331. The clock signal at f is also fed into the inverted clock input of the D flip-flop 331. The other output of the divider 312 is fed to a logical AND circuit 340. The other input of the logical AND circuit 340 is connected to the inverted output Q, which is denoted by the numeral 305, of the D flip-flop 331. The relative phases of the D flip-flops 330, 331 and the AND circuit 340 are adjusted so that the output 302 of the AND circuit 340 is a narrow pulse clock of order n, as illustrated on FIG. 4. The narrow pulse clock generator 300 transforms the input clock at the frequency f into an output narrow pulse clock of order n.

FIG. 4 is a time chart of signals of the schematic representation depicted on FIG. 3, where n is taken as n=4. The signals 401, 402, 403, 404 and 405 are the respective time charts of the signals 301, 302, 303, 304 and 305 of FIG. 3.

The numeral 401 denotes a clock at the frequency f. The numeral 403 denotes a clock at the frequency f/4. The numeral 404 is another clock at f/4, which is shifted by half a period of f (2/f) from the clock 403. The numeral 405 denotes another clock at f/4, which is shifted by 8/f from 403. The output signal 402 is a narrow pulse clock of order 4, generated by the narrow pulse clock generator 300 when n=4.

FIG. 5 is the schematic representation of a modulator driver 500, which generates two electrical signals 503 and 504 used to drive a modulator, to modulate an optical signal passing through the modulator according to a signal binary data 501 and to carve PRZ(n) dips on the optical signal according to a narrow pulse clock of order n, which is denoted by the numeral 502.

The modulator driver 500 has two inputs receiving the binary data signal 501 and the narrow pulse clock 502. The binary data signal 501 carries binary data according to which an optical signal will be modulated. The narrow pulse clock 502 may be generated by the narrow pulse clock generator 300 shown in FIG. 3. The numeral 520 denotes a differential amplifier which amplifies the binary data signal 501. The non inverted output of the differential amplifier 520 is fed to one input of a logical AND circuit 511. The inverted output of the differential amplifier 520 is fed to one input of a logical AND circuit 512. The narrow pulse clock 502 is divided by the divider 510. One output of 510 is fed into the other input of the AND circuit 511, which is inverted. The other output of the divider 510 is fed into the other input of the AND circuit 512, which is also inverted. The outputs of the respective AND circuits 511 and 512 are respectively connected to amplifiers 521 and 522, which amplify their respective levels. The respective outputs 503 and 504 of the AND circuits 521 and 522 have suitable amplitudes to drive an optical modulator.

FIG. 6 is a time chart of the signals of the schematic representation depicted on FIG. 5, where the numeral 502 denotes a narrow pulse clock of order 4 and the data carried by the binary data signal 501 is the following bit sequence: 0,1,1,1,1,1,0,1,0,0,1. The signals 601, 602, 603, and 604 are the respective time charts of the signals 501, 502, 503 and 504 of FIG. 5.



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stats Patent Info
Application #
US 20120320442 A1
Publish Date
12/20/2012
Document #
13131965
File Date
02/20/2010
USPTO Class
359238
Other USPTO Classes
359237
International Class
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Drawings
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