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Power conversion device

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20120307540 patent thumbnailZoom

Power conversion device


The present invention aims to provide a power converter with an arm including switching devices connected in parallel, realizing long lifespans of switching devices. An inverter includes an upper and a lower arm, and gate drive circuits each driving the corresponding arm according to a gate control signal Gup_s indicating ON/OFF periods. Each arm includes switching devices connected in parallel. Each gate drive circuit includes: a switching gate control circuit 230u bringing a switching device 210u into conduction at the beginning of the ON period and bringing the same out of conduction within the ON period; and a conduction gate control circuit 231u bringing switching devices 211u and 212u within a period from when the switching device 210u is brought into conduction until the same is brought out of conduction, wherein the switching device 210u has a lower parasitic capacitance than the switching devices 211u and the 212u.

Inventor: Masaki Tagome
USPTO Applicaton #: #20120307540 - Class: 363131 (USPTO) - 12/06/12 - Class 363 


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The Patent Description & Claims data below is from USPTO Patent Application 20120307540, Power conversion device.

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TECHNICAL FIELD

The present invention relates to a power converter such as an inverter and a DC/DC converter having an arm composed of a plurality of switching devices connected in parallel.

BACKGROUND ART

In recent years, power converters such as inverters and DC/DC converters have increased their output power for the use in hybrid electric vehicles, electric vehicles, and the likes. In a high-output power converter, switching devices constituting an arm are required to manage high voltage and high current. To support high voltage, the switching devices are connected in series, and to support high current, the switching devices are connected in parallel. For example, Patent Literature 1 discloses an inverter having an arm composed of a plurality of switching devices connected in parallel.

CITATION LIST Patent Literature

[Patent Literature 1] Japanese Patent Application Publication No. 2005-6412

SUMMARY

OF INVENTION Technical Problem

When switching devices are connected in parallel, it is likely that a large amount of current flows in a particular device due to variations in the electrical properties of the devices. Hence, the device in which a larger amount of current flows generates a large amount of heat, and the lifespan of the device is likely to be short. In particular, parallel connection is more problematic during the switching operation than during the regular operation. That is, in addition to the variations in the electrical properties (e.g. on-resistance, threshold voltage), the difference in the junction temperature, the difference in the wiring inductance, and variations in properties of the gate drive circuits have an influence during the switching operation, and when compared with the case of a single device, the problem of variations is more significant in the case of the switching operation.

The present invention is made in view of the problems above, and aims to provide a power converter having an arm composed of a plurality of switching devices connected in parallel and realizing long lifespans of the switching devices.

Solution to Problem

To achieve the aim, the present invention provides a power converter comprising: an upper arm; a lower arm; and gate drive circuits each configured to drive a corresponding one of the arms according to a reference signal, the reference signal having a first-potential period and a second-potential period, wherein each arm includes a set of switching devices connected in parallel, each gate drive circuit includes: a switching gate control circuit configured to bring a first switching device among the corresponding set of switching devices at the beginning of the first-potential period, and to bring the first switching device out of conduction at a point within the first-potential period; and a conduction gate control circuit configured to bring a second switching device among the corresponding set of switching devices into conduction at a point within a period from when the first switching device is brought into conduction, which corresponds to the beginning of the first-potential period, until the first switching device is brought out of conduction, and the first switching device has a smaller parasitic capacitance than the second switching device.

Advantageous Effects of Invention

In the power converter pertaining to the present invention with the structure described in Solution to Problem, among the switching devices included in the arm, the switching loss occurs in the first switching device which performs the switching operation, and the conduction loss occurs in the second switching device which performs the conduction operation.

Hence, in the first switching device, heat caused by switching loss is generated, but heat caused by conduction loss is suppressed. In the second switching device, heat caused by conduction loss is generated, but heat caused by switching loss is suppressed. Therefore, the switching devices are prevented from having a short lifespan due to heat generation.

Conduction loss and switching loss, which are power loss occurring in switching devices and are recognized as common properties of switching devices, have a trade-off relationship. That is, a switching device with a reduced conduction loss has a relatively large switching loss, and a switching device with a reduced switching loss has a relatively large conduction loss.

In the power converter pertaining to the present invention, however, switching loss and conduction loss occur in different switching devices. Hence, switching loss and conduction loss, which conventionally have a trade-off relationship, can be each reduced in terms of the entire apparatus. That is, the present invention provides a highly efficient power converter that can reduce both types of loss in terms of the entire apparatus.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows the entire structure of a synchronous motor drive system using a power converter pertaining to the present invention.

FIG. 2 is a waveform diagram showing switching operations performed by an upper arm and a lower arm of an inverter.

FIG. 3 shows detailed structures of a gate control circuit and an arm of an inverter pertaining to Embodiment 1.

FIG. 4 is a timing chart illustrating operations performed by a gate control circuit.

FIG. 5 shows the current-voltage characteristic of a switching device.

FIG. 6 shows detailed structures of a gate control circuit and an arm of an inverter pertaining to Modification 1 of Embodiment 1.

FIG. 7 shows detailed structures of a gate control circuit and an arm of an inverter pertaining to Modification 2 of Embodiment 1.

FIG. 8 shows detailed structures of a gate control circuit and an arm of an inverter pertaining to Modification 3 of Embodiment 1.

FIG. 9 is a timing chart illustrating operations performed by a gate control circuit pertaining to Modification 3.

FIG. 10 shows detailed structures of a gate control circuit and an arm of an inverter pertaining to Modification 4 of Embodiment 1.

FIG. 11 illustrates mechanism by which a lower arm 22u malfunctions due to a turning on of a upper arm 21u.

FIG. 12 shows detailed structures of a gate control circuit and an arm of an inverter pertaining to Embodiment 2.

FIG. 13 is a timing chart illustrating operations performed by a gate control circuit of an inverter pertaining to Embodiment 2.

FIG. 14 shows detailed structures of a gate control circuit and an arm of an inverter pertaining to Embodiment 3.

FIG. 15 shows operations of gate control circuit in an inverter pertaining to Embodiment 3 and switching operations thereof.

FIG. 16 shows detailed structures of a gate control circuit and an arm of an inverter pertaining to Embodiment 3.

FIG. 17 shows detailed structures of a gate control circuit and an arm of an inverter pertaining to Embodiment 4.

FIG. 18 shows the entire structure of a synchronous motor drive system using an inverter pertaining to Embodiment 5.

FIG. 19 shows a positional relationship between an arm and a capacitor of the inverter pertaining to Embodiment 5.

FIG. 20 shows detailed structures of a gate control circuit and an arm of an inverter pertaining to Embodiment 6.

FIG. 21 compares voltage-current characteristics in saturation regions of IGBT and MOSFET.

FIG. 22 shows the entire structure of a synchronous motor drive system using a DC/DC converter pertaining to the present invention.

FIG. 23 shows detailed structures of an arm 81 and a gate drive circuit 83 depicted in FIG. 22.

DESCRIPTION OF EMBODIMENTS

The following describes embodiments of a power converter pertaining to the present invention, with reference to the drawings.

Embodiment 1

FIG. 1 shows the entire structure of a synchronous motor drive system using a power converter pertaining to the present invention.

The synchronous motor drive system shown in the drawing includes a battery 1, an inverter 2 as a power converter pertaining to the present invention, a motor 3, and a control circuit 4.

The battery 1 is a DC power source, and supplies DC power to the inverter 2.

The inverter 2 is a three-phase inverter that converts DC power supplied by the batter 1 to AC power and supplies three-phase AC power to the motor 3.

The motor 3 is rotatably driven by three-phase AC power supplied from the inverter 2.

The control circuit 4 controls the inverter 2 so that the motor 3 operates in a desired manner.

The following describes the details of the inverter 2 pertaining to the present embodiment.

An inverter has the same number of legs as AC power outputs. The inverter 2 pertaining to the present embodiment includes a leg 25u, a leg 25v and a leg 25w.

The leg 25u includes: an upper arm 21u and a lower arm 22u, which are connected in series between the positive terminal and the negative terminal of the battery 1 (the upper arm 21u is connected to the positive side, and the lower arm 22u is connected to the negative side); and an upper arm-side gate drive circuit (upper arm drive circuit) 23u and a lower arm-side gate drive circuit (lower arm drive circuit) 24u, which respectively correspond to the upper arm 21u and the lower arm 22u. Similarly, the legs 25v and 25w respectively include upper arms 21v and 21w, lower arms 22v and 22w, upper arm-side gate drive circuits (upper arm drive circuits) 23v and 23w, and lower arm-side gate drive circuits (lower arm drive circuits) 24v and 24w.

FIG. 2 is a waveform diagram showing basic operations of the upper arm-side gate driver circuit and the lower arm-side gate drive circuit for the U phase.

The symbol Is_u represents a current-instruction signal, which is externally input to the control circuit 4 and indicates a waveform of a current to be applied to the U phase. This waveform matches the waveform of the current to be applied to the U-phase coil of the motor 3. The symbol fc represents a carrier signal used for PWM operations, which is generated by a carrier signal generation circuit included in the control circuit 4. The control circuit 4 compares the carrier signal fc with the current-instruction signal and thereby generates a gate control signals Gup_s and Gun_s, and outputs the gate control signals Gup_s and Gun_s to the upper arm-side gate drive circuit and the lower arm-side gate drive circuit, respectively.

Although only the U-phase among the three phases is described above, the control circuit 4 also generates and outputs gate control signals Gvp_s and Gvn_s and gate control signals Gwp_s and Gwn_s for the V phase and the W phase, respectively. In the following, only the U-phase will be explained. However, the inverter 2 has the same structure for the V phase and the W phase.

FIG. 3 shows the details of the upper arm 21u and the upper arm-side gate drive circuit 23u depicted in FIG. 1.

The upper arm-side gate drive circuit 23u includes a switching gate control circuit 230u, and a conduction gate control circuit 231u. The upper arm 21u includes three switching devices 210u, 211u and 212u. Here, each of the switching devices 210u, 211u and 212u is made up of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The switching gate drive circuit 230u is connected to the control terminal of the switching device 210u, and the conduction gate control circuit 231u is connected to the respective control terminals of the switching devices 211u and 212u. The switching devices 210u, 211u and 212u are connected in parallel, and their respective high electrical potential-side primary terminals are connected to one another, and their respective low electrical potential-side primary terminals are connected to one another.

The gate control signal Gup_s output from the control circuit 4 is input to each of the switching gate control circuit 230u and the conduction gate control circuit 231u. Based on the gate control signal Gup_s, the switching gate control circuit 230u outputs a switching gate drive signal Gup_sw to the control terminal of the switching device 210u. The conduction gate control circuit 231u outputs a conduction gate drive signal Gup_on to the respective control terminals of the switching devices 211u and 212u.

The following describes the details of the switching gate drive signal Gup_sw output by the switching gate control circuit 230u and the conduction gate drive signal Gup_on output by the conduction gate control circuit 231u, with reference to FIG. 4.

The gate control signal Gup_s output by the control circuit 4 has a first-potential period, for which the electrical potential is at the High level, and a second-potential period, for which the electrical potential is at the Low level. The gate control signal Gup_s serves as a reference signal used by the switching gate control circuit 230u and the conduction gate control circuit 231u to operate.

The switching gate control circuit 230u raises the switching gate drive signal Gup_sw at time t1, which is when a rise is detected in the gate control signal Gup_s input by the control circuit 4. Then, the switching gate control circuit 230u drops the switching gate drive signal Gup_sw within a shorter period than the first-potential period for which the electrical potential of the gate control signal Gup_s is at the High level. That is, the switching gate control circuit 230u drops the switching gate drive signal Gup_sw at time t3. Furthermore, the switching gate control circuit 230u raises the switching gate drive signal Gup_sw again at time t4, which is when a drop is detected in the gate control signal Gup_s. Then, the switching gate control circuit 230u drops the switching gate drive signal Gup_sw within a shorter period than the second-potential period for which the electrical potential of the gate control signal Gup_s is at the Low level. That is, the switching gate control circuit 230u drops the switching gate drive signal Gup_sw at time t6.

Through the operations described above, the switching gate control circuit 230u outputs, as the switching gate drive signal Gup_sw, a square wave twice within the period of one cycle of the gate control signal Gup_s.

On the other hand, the conduction gate control circuit 231u raises the conduction gate drive signal Gup_on at time t2 in the period of one cycle of the gate control signal Gup_s. The time t2 indicates a point within the period between t1 and t3 for which the switching gate drive signal Gup_sw is raised to the High level along with the rise of the gate control signal Gup_s. Then, the conduction gate control circuit 231u drops the conduction gate drive signal Gup_on at time t5. The time t5 is a point within the period between t4 and t6 for which the switching gate drive signal Gup_sw is raised to the High level along with the drop of the gate control signal Gup_s.

By the operations described above, the upper arm 21u will be conductive during the period between t1 and t6, for which at least one of the switching gate drive signal Gup_sw and the conduction gate drive signal Gup_on is at the High electrical potential. In the upper arm 21u, however, the operation for switching is performed by the switching device 210u, and the operation for establishing electrical conduction is performed by the switching device 211u and the switching device 212u. As a result, among losses occurring in the upper arm 21u, switching loss occurs in the switching device 210u, and conduction loss occurs in the switching device 211u and the switching device 212u.

As described above, in the inverter pertaining to the present embodiment, the location where switching loss occurs and the location where conduction loss occurs are separated. Specifically, the farmer occurs in the switching device that performs the switching operation and the latter occurs in the switching devices that perform the conduction operation. Conduction loss and switching loss, which are power loss occurring in switching devices and are recognized as common properties of switching devices, have a trade-off relationship. That is, a switching device with a reduced conduction loss has a relatively large switching loss, and a switching device with a reduced switching loss has a relatively large conduction loss.

In the inverter pertaining to the present embodiment, however, switching loss and conduction loss occur in different switching devices. Hence, switching loss and conduction loss, which conventionally have a trade-off relationship, can be each reduced in terms of the entire apparatus. That is, the present invention provides a highly efficient inverter that can reduce both types of loss in terms of the entire apparatus.

Note that the switching devices 210u, 211u and 212u, which constitute the upper arm and are connected in parallel, do not necessarily have the same maximum voltage rating and the same maximum current rating. For example, the switching device 210u, which mainly performs the switching operation, may have a relatively small maximum current rating compared to the switching devices 211u and 212u each of which mainly performs the conduction operation. Generally, the level of the maximum current rating depends on the chip area of the switching device. Therefore, as the maximum current rating decreases, the conduction loss increases, but the switching loss decreases. Regarding the switching device 210u, which mainly performs the switching operation, it is not very necessary to consider the conduction loss. Therefore, in order to reduce the switching loss, it is preferable that the maximum current rating is low. It is however necessary to conduct the maximum current, and to allow the occurrence of loss for a short period.

Generally, switching devices using MOSFET can bare approximately three to ten times the current rating for a short period. For example, as can be seen from FIG. 5 which shows the current-voltage characteristic of a MOSFET having a current rating of 20 A, a MOSFET can operate within the saturation region when the current is at 60 A. Therefore, a device having a maximum current rating that is approximately ⅓ of the switching device 211u and the switching device 212u can be used as the switching device 210u, which mainly performs the switching operation.

It is preferable that the switching devices 211u and 212u, which mainly perform the conduction operation, have a relatively large maximum current rating compared to the switching device 210u which mainly performs the switching operation. Regarding the switching devices 211u and 212u, it is not very necessary to consider the switching loss, and the maximum current rating of a switching device and conduction/switching loss have the relationship as described above. Therefore, in order to reduce the conduction loss, it is advantageous that the maximum current rating is low.

However, if the maximum current rating is unnecessarily high, it means that the chip area is large. This leads to increase in size of the apparatus. Hence, it is preferable that the maximum current rating is approximately twice to four times the maximum amount of current applied to the upper arm.

In the above, switching devices suitable for the conduction operation and the switching operation are described focusing on the relationship between the maximum current rating and the conduction loss and the switching loss. However, the upper limit of the maximum current rating may be determined not only by the current carrying capacity as the characteristic of the device, but also by the thermal resistance of the entire package. For example, when the switching device 210u and the switching devices 211u and 212u are all arranged on a single substrate and sealed with mold resin to form a single module, the maximum current rating is determined by the thermal resistance of the entire package. The maximum current rating determined by the thermal resistance of the entire package has essentially no correlation with the amounts of conduction loss and switching loss.

On the other hand, parasitic capacitance is determined by the properties of a switching device per se, and when the same material and the same structure are adopted in switching devices, parasitic capacitance and current carrying capacity generally correlate with each other in each switching device. That is, parasitic capacitance increases as the chip area increases. In other words, among switching devices made up from the same material and have the same structure, a switching device with a higher parasitic capacitance exhibits a smaller amount of conduction loss and a larger amount of switching loss. Therefore, which switching device is suitable for the conduction operation and which is for the switching operation can be determined based on the parasitic capacitance. Specifically, it is preferable that the switching devices 211u and 212u, which mainly perform the conduction operation, have a relatively large parasitic capacitance compared to the switching device 210u, which mainly performs the switching operation. In addition, a switching device increases its speed of performing the switching operation as the parasitic capacitance decreases. For this reason, there is a merit to select a switching device with a low parasitic capacitance as the switching device 210u which is required to perform the switching operation at high speed.

Note that the parasitic capacitance of a switching device is “input capacitance” occurring between a source and a gate, “output capacitance” occurring between a source and a drain, or “feedback capacitance” occurring between a drain and a gate. Generally, each type of capacitance is not determined independently, and when one of them is doubled, the other two are also approximately doubled. Therefore, switching devices to be used may be selected based on any type of capacitance.

Here, as described above, when the material and the structure of switching devices are the same, current carrying capacity and parasitic capacitance correlate with each other. However, when the material and the structure are different, there can be no correlation. For example, in a comparison between a switching device using silicon carbide (SiC) and a switching device using silicon (Si), the SiC device has a smaller chip area and a smaller parasitic capacitance even with the same current carrying capacity. Therefore, switching loss can be further reduced when a switching device 210u which mainly performs the switching operation is made up from a SiC device with low parasitic capacitance which can perform the switching operation at high speed.

Moreover, although SiC devices are costly, they have higher thermal resistance than Si devices. When the switching device 210u, the switching devices 211u and 212u are enclosed within a single package, the temperature of the entire package depends largely on heat generated by the switching devices 211u and 212u performing the conduction operation, and the temperature of the switching device 210u further rises locally when performing the switching operation. Considering the above, in the case the switching device 210u and the switching devices 211u and 212u are enclosed within a single package, it is preferable that Si devices, which are relatively cheap, are used as the switching devices 211u and 212u, and a SiC device, which has high thermal resistance, is used as the switching device 210u whose temperature temporarily rises when performing the switching operation.

Modification 1 of Embodiment 1

The example described above has s structure in which the upper arm 21u made up from a plurality of MOSFETs connected in parallel. However, the present invention is not limited to this. The switching devices may be insulated gate bipolar transistors (IGBTs), field effect transistors (J-FETs), bipolar transistors, or their combinations. FIG. 6 shows detailed structures of a gate control circuit and an arm of an inverter pertaining to Modification 1 of Embodiment 1. The structure shown in this figure is the same as the structure shown in FIG. 3 except that the upper arm 21u is replaced with an upper arm 31u, and performs the same operation. The upper arm 31u includes switching devices 310u, 311u and 312u, which are all IGBTs. As with Embodiment 1, when the switching devices are IGBTs, switching loss and conduction loss can be reduced separately. That is, both of them can be reduced, and this realizes a high-efficiency inverter.

Here, the present modification, in which the switching devices included in the upper arm are not MOSFETs but IGBTs, is advantageous when the conduction loss of the inverter is larger enough than the switching loss of the same.

Generally, MOSFETs have lower switching loss than IGBTs, but have higher conduction loss than IGBTs. Hence, when conduction loss is major among loss occurring in an inverter, it is advantages that the switching devices of the inverter to which the present invention is applied are IGBTs.

In the description of Embodiment 1 above, it is stated that when all the switching devices are MOSFETS, it is preferable that the switching device 210u which mainly performs the switching operation has a lower maximum current rating than the switching devices 211u and 212u. However, since IGBTs have higher switching loss and lower breakdown resistance than MOSFETs, the reliability of the inverter is degraded when the switching device which mainly performs the switching operation is made up from an IGBT and has low current carrying capacity (Generally, breakdown resistance and current carrying capacity have a trade-off relationship). Therefore, in the case of an inverter using IGBTs, it is preferable that the switching devices which mainly perform the switching operation are also made up from devices that have approximately the same current carrying capacity as the switching devices which mainly perform the conduction operation.

Modification 2 of Embodiment 1

Next, a modification in which the upper arm includes different types of switching devices is described.

FIG. 7 shows detailed structures of a gate control circuit and an arm of an inverter pertaining to Modification 2 of Embodiment 1. The structure shown in this figure is the same as the structure shown in FIG. 3 except that the upper arm 21u is replaced with an upper arm 41u, and performs the same. The upper arm 41u includes switching devices 410u, 411u and 412u. The switching device 410u is a MOSFET, which is a unipolar device, and the switching devices 411u and 412u are IGBTs, which are bipolar devices.

In the present modification, as with Embodiment 1, switching loss and conduction loss can be reduced separately. That is, both of them can be reduced, and this realizes a high-efficiency inverter.

Generally, MOSFETs, which are unipolar devices, have a larger conductance resistance and a larger chip area than IGBTs, which are bipolar devices. Therefore, MOSFETs have higher conduction loss than IGBTs. On the other hand, since MOSFETs can perform the switching operation at higher speed than IGBTs, and can reduce the switching loss. Therefore, when the switching devices included in the upper arm are the combination of MOSFETs and IGBTs as with the present modification, that is, when the switching devices which mainly perform the switching operation are MOSFETs and the switching devices which mainly perform the conduction operation are IGBTs, the advantages of both switching devices can be maximized, and further effect of loss reduction can be achieved.

Modification 3 of Embodiment 1


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stats Patent Info
Application #
US 20120307540 A1
Publish Date
12/06/2012
Document #
13576736
File Date
02/04/2011
USPTO Class
363131
Other USPTO Classes
International Class
02M7/537
Drawings
24


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