Digital signal routing circuit   

Abstract: An integrated circuit for digital signal routing. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44 kHz or 48 kHz.

This application claims the benefit of U.S. Provisional Application No. 61/491,041, filed May 27, 2011, the entire disclosure of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a signal routing circuit, and in particular to a signal routing circuit that can be used as a digital audio hub, for interconnecting various signal sources and signal destinations in consumer devices, of which smartphones are just one example.

2. Description of the Related Art

It is known to provide an integrated circuit that acts as an “audio hub”, which is able to receive a number of signals from analog and digital sources, converting the analog signals to digital signals and then combining or processing the signals in the digital domain, in order to generate output signals. If required, the output signals can be converted by the audio hub into analog signals, in order to be applied to analog transducers such as headphones or speakers. Such a digital audio hub device can be incorporated into a consumer device, such as a smartphone or the like, allowing the received signals to be processed in predetermined ways.

It is desirable to allow the customer of the “audio hub” integrated circuit to use it to interconnect a number of different signal processing components within a consumer device in a flexible manner, without being restricted to specific external devices or to specific processing paths.

The invention is defined by the claims appended hereto.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention, and to show how it may be out into effect, reference will now be made, by way of example, to the accompanying drawings, in which:—

FIG. 1 shows a mobile telephone and various peripheral devices;

FIG. 2a shows components of the audio processing circuitry in the mobile telephone of FIG. 1;

FIG. 2b shows components of the audio processing circuitry in an alternative mobile telephone;

FIG. 3 is a first more detailed block diagram, showing the form of the audio hub routing circuitry in the audio processing circuitry of FIG. 2a or 2b;

FIG. 4 is a still more detailed block diagram, showing the form of the pre-conditioning circuitry in the routing circuitry of FIG. 3;

FIG. 5 is a further still more detailed block diagram, showing the form of the switching circuitry in the routing circuitry of FIG. 3;

FIG. 6 is a further still more detailed block diagram, showing an alternative form of the switching circuitry in the routing circuitry of FIG. 3;

FIG. 7 is a further still more detailed block diagram, showing the form of the down-sampling circuitry in the routing circuitry of FIG. 3;

FIG. 8 is a further still more detailed block diagram, showing the form of the up-sampling circuitry in the routing circuitry of FIG. 3;

FIG. 9 is a further still more detailed block diagram, showing the form of the post-conditioning circuitry in the routing circuitry of FIG. 3;

FIG. 10 is a further still more detailed block diagram, showing the form of the digital mixing core in the routing circuitry of FIG. 3;

FIG. 11 shows in more detail a part of a functional block in the digital mixing core of FIG. 10;

FIG. 12 shows in more detail a part of another functional block in the digital mixing core of FIG. 10;

FIG. 13 shows in more detail a part of a further functional block in the digital mixing core of FIG. 10;

FIG. 14 is a further block diagram, showing the digital mixing core of FIG. 10, and showing more detail of the functional blocks;

FIG. 15 is a block diagram, illustrating a different aspect of the digital mixing core in one embodiment;

FIG. 16 is a block diagram, illustrating the different aspect of the digital mixing core in another embodiment;

FIG. 17 is a block diagram, illustrating the different aspect of the digital mixing core in a further embodiment;

FIG. 18 is a block diagram, illustrating the different aspect of the digital mixing core in a still further embodiment;

FIG. 19 is a block diagram, illustrating the different aspect of the digital mixing core in a still further embodiment;

FIG. 20 is a block diagram, illustrating a part of the digital mixing core in one embodiment;

FIG. 21 is a block diagram, illustrating a part of the digital mixing core in another embodiment;

FIG. 22 is a block diagram, illustrating a form of a multiply-accumulate block in the digital mixing core;

FIG. 23 is a block diagram, illustrating in more detail an alternative form of the multiply-accumulate block in the digital mixing core;

FIG. 24 is a flow chart, illustrating a process performed in the mixer;

FIG. 25 is a further illustration of the process shown in FIG. 24;

FIG. 26 is a first timing diagram, illustrating the process of FIG. 24;

FIG. 27 is a second timing diagram, illustrating more detail of the process of FIG. 26;

FIG. 28 is a third timing diagram, illustrating a further alternative process;

FIG. 29 is a fourth timing diagram, illustrating a still further alternative process;

FIG. 30 is a flow chart, illustrating a method of defining the operation of the switching circuitry; and

FIG. 31 is a representation of a computer screenshot, illustrating a stage in the method of FIG. 30;

FIG. 32 is a block diagram, showing the routings in a use case defined by the process of FIG. 30;

FIG. 33 is a register map, illustrating an initial state of the register bank in the process of FIG. 30;

FIG. 34 is a block diagram, providing an alternative illustration of the routings in the use case of FIG. 32 on the digital mixing core of FIG. 14;

FIG. 35 is a register map, illustrating a state of the register bank at a further point in the process of FIG. 30;

FIG. 36 is a representation of the digital mixing core, showing the functional blocks involved in the use case shown in FIG. 32;

FIG. 37a shows a routing in a further use case;

FIG. 37b shows a routing in a still further use case;

FIG. 38 is a timing diagram, illustrating a first series of calculations in a process carried out in the mixer;

FIG. 39 is a timing diagram, illustrating a second series of calculations in a process carried out in the mixer;

FIG. 40 is a timing diagram, illustrating a third series of calculations in a process carried out in the mixer;

FIG. 41 is a timing diagram, illustrating a fourth series of calculations in a process carried out in the mixer;

FIG. 42 is a timing diagram, illustrating a fifth series of calculations in a process carried out in the mixer;

FIG. 43 is a block diagram, illustrating a clock generator in the switching circuit;

FIG. 44 is a block diagram, illustrating a further aspect of the clock generator;

FIG. 44a is a block diagram, illustrating an alternative form of the clock generator;

FIG. 44b is a block diagram, illustrating a further alternative form of the clock generator;

FIG. 44c is a block diagram, illustrating a further aspect of the alternative forms of the clock generator;

FIG. 45 is a block diagram, illustrating a mixer according to one embodiment;

FIG. 46 is a flow chart, illustrating a first method performed in the mixer of FIG. 45;

FIG. 47 is a flow chart, illustrating a second method performed in the mixer of FIG. 45;

FIG. 48 is a flow chart, illustrating a third method performed in the mixer of FIG. 45;

FIG. 49 is a block diagram, illustrating in more detail the enable and clock control block of the mixer of FIG. 45;

FIG. 50 is a flow chart, illustrating a method performed in the enable and clock control block of FIG. 49;

FIG. 51 is a flow chart, illustrating a further method performed in the enable and clock control block of FIG. 49;

FIG. 52a is a block diagram, illustrating in more detail the channel scheduler in the mixer of FIG. 45;

FIG. 52b is a flow chart, illustrating a method performed in the channel scheduler of FIG. 52a;

FIG. 53 is a flow chart, illustrating a further method performed in the channel scheduler of FIG. 52a;

FIG. 54 is a block diagram, illustrating in more detail the calculation block of the mixer of FIG. 45;

FIG. 55 is a flow chart, illustrating a part of the method performed in the channel scheduler block of FIG. 52a and calculation block of FIG. 54;

FIG. 56 is a schematic diagram, illustrating a part of an electronic device according to an aspect of the invention;

FIG. 57 is a schematic diagram, illustrating a part of a second electronic device according to an aspect of the invention;

FIG. 58 is a schematic diagram, illustrating a part of a third electronic device according to an aspect of the invention;

FIG. 59 is a schematic diagram, illustrating a part of a fourth electronic device according to an aspect of the invention;

FIG. 60 is a schematic diagram, illustrating a part of a fifth electronic device according to an aspect of the invention; and

FIG. 61 is a schematic diagram, illustrating a part of a sixth electronic device according to an aspect of the invention.

DETAILED DESCRIPTION

FIG. 1 shows a consumer device according to an aspect of the invention, in this example a mobile telephone 1, more specifically in the form of a smartphone. In this example, the mobile telephone 1 has a screen 3 and a keypad 5, although of course the invention is equally applicable to devices with touchscreens or other user interfaces. The mobile telephone 1 also has an inbuilt speaker 7 and an inbuilt main microphone 9, which are both analog transducers. The mobile telephone 1 also has a plurality of, in this particular example four, microphones 11 (which may be analog or digital microphones), allowing multiple ambient noise signals to be received, for example for use in a noise cancellation system.

As shown in FIG. 1, the mobile telephone 1 can have a jack socket (not illustrated) or similar connection means, such as a USB socket or a multi-pin connector socket, allowing a headset, comprising a pair of stereo earpieces 13 and possibly a microphone 15, to be connected to it by wire. Alternatively, the mobile telephone 1 can be connected wirelessly, for example using the Bluetooth (trade mark) communications protocol, to a wireless headset 17, having earpieces 19 and possibly a microphone 21. Although not illustrated, the earpieces 13, 19 may comprise one or more ambient noise microphones (which may be analog or digital microphones), allowing one or more ambient noise signals to be received, for example for use in a noise cancellation system.

Alternatively, or additionally, the mobile telephone 1 can have a socket or similar connection means allowing it to be connected to an external audio system 23 for music playback for example, the system comprising one or more speakers 25. The external audio system 23 might for example be a tabletop stereo sound system or an in-car audio system. Circuitry 27 of the external audio system 23 can include a radio receiver or other audio source, which may provide an audio input to the mobile telephone 1, so that the radio or other audio can be played back through the speaker 7 or through the earpieces 13, 19 of a selected one of the headsets. Alternatively, music stored on the phone can be played back through the speakers 25 of the external audio system 23.

It can thus be seen that there are many possible audio signals that can be output. For example, if the mobile telephone 1 has a connector allowing it to be fitted into a docking station in a motor vehicle and is equipped with a satellite navigation system, the mobile telephone 1 might need to be able simultaneously to: (a) handle a mobile telephone conversation via either the wired or the wireless handset; (b) provide stereo music from its memory to the external audio system 23; and (c) provide tones for confirmation of button presses and provide navigation instructions via the inbuilt speaker. Consequently, switching circuitry in the mobile telephone 1 must, according to the above example, be able to handle at least these three separate output audio data signals, as well as the input audio data signal of the mobile telephone conversation.

FIG. 2a shows components of the audio handling system in the mobile telephone 1. Communication with the cellular telephone network 29 is handled by a baseband processor (sometimes referred to as a communications processor) 31. An applications processor 33 handles, amongst other processes, processes in which audio data is reproduced from or stored into a memory 35 (which may be solid-state or on a disk, and which may be built-in or attachable, for example, either permanently in the mobile telephone or on a removable memory device) and other processes in which audio data is generated internally within the telephone 1. For example, the applications processor 33 may handle the reproduction of stereo music stored digitally in the memory 35, may handle recording of telephone conversations and other audio data into the memory 35, and will also handle the generation of satellite navigation commands and the generation of tones to confirm the pressing of any button on the keypad 5. A wireless transceiver (or wireless codec) 37 handles communications using the Bluetooth (trade mark) protocol or another short-range communications protocol, for example with the wireless headset 17.

The baseband processor 31, the applications processor 33, and the wireless transceiver 37 all send audio data to, and receive audio data from, switching circuitry in the form of an audio hub 39. The audio hub 39 takes the form of an integrated circuit in this described embodiment. In the embodiment described above, the audio signals between the audio hub 39 and the baseband processor 31, the applications processor 33, and the wireless transceiver 37 are all digital, and some of them may be in stereo, comprising a left data stream and a right data stream. Additionally, at least in the case of communication with the applications processor 33, further data streams may be multiplexed into the audio signals, for example to enable the applications processor 33 to provide stereo music and also other audio signals such as key press confirmation tones simultaneously.

The audio hub 39 communicates with the baseband processor 31, the applications processor 33, and the wireless transceiver 37 over respective audio data links, i.e. buses, 38b, 38a, 38c, and the audio hub 39 has respective digital interfaces 40b, 40a, 40c for these data links.

The audio hub 39 also provides audio signals to, and receives audio signals from, the built-in analog audio transducers of the mobile telephone 1. As shown in FIG. 2, the audio hub 39 provides output audio signals to the speaker 7, and receives input audio signals from the microphones 9, 11.

The audio hub 39 can also be connected to other output transducers 43, which may be analog or digital transducers, and which may be built in to the mobile telephone 1 (for example in the case of a haptic output transducer) or in devices external to the mobile telephone 1 (for example the earpieces 13 of the wired headset shown in FIG. 1). The audio hub 39 can also be connected to other input transducers 45, which again may be analog or digital transducers, and which again may be built in to the mobile telephone 1 (for example an ultrasound microphone) or in devices external to the mobile telephone 1 (for example the microphone 15 of the wired headset).

The audio hub 39 may also be required to receive signals from other sources such as an FM radio receiver 41, which may be in the external audio system 23, or may be provided on a separate IC in the mobile telephone 1, and which may generate either analog or digital signals.

It is to be appreciated that FIG. 2 shows just one possible use of the audio hub 39, whereas audio hub integrated circuits in accordance with the invention are usable in an extremely wide range of electronic devices, including industrial, professional or consumer devices, such as cameras (DSC and/or video), portable media players, PDAs, games consoles, satellite navigation devices, tablets, notebook computers, TVs or the like.

An audio hub integrated circuit can be optimised for one particular category out of a wide range of industrial, professional or consumer devices. For example, while FIG. 1 shows one particular form of smartphone 1, it will be appreciated that other smartphone models will have different levels of functionality, and will therefore have different audio handling requirements, and the audio hub integrated circuit can be designed to be able to handle this wide range of requirements. As described below, the audio hub 39 is optimised for use in smartphones, but is able to be used in a wide range of smartphones having different audio handling requirements.

In any event, even if an audio hub integrated circuit has been optimised for use in one category of consumer device, such as smartphones, it will likely be usable in a range of types of consumer device, since it is agnostic as to what the various signals represent. The number and type of interfaces, and the number and type of signal processing blocks, provided in the audio hub integrated circuit will determine the range of types of consumer device in which it will be usable, and a manufacturer can choose whether to make an audio hub integrated circuit that might be cheaper to manufacture because it has restricted functionality but is well designed for one specific purpose, or whether to make an audio hub integrated circuit that has greater functionality and can therefore be used for many different purposes.

FIG. 2b shows components of the audio handling system in an alternative mobile telephone. Again, communication with the cellular telephone network 29 is handled by a baseband processor (or communications processor) 31, and an applications processor 33 handles processes in which audio data is reproduced from or stored into a memory 35 and other processes in which audio data is generated internally within the telephone 1. For example, the applications processor 33 may handle the reproduction of stereo music stored digitally in the memory 35, may handle recording of telephone conversations and other audio data into the memory 35, and will also handle the generation of satellite navigation commands and the generation of tones to confirm the pressing of any button on the keypad 5. In this alternative mobile telephone, there is no wireless codec. As a result, the audio hub 39a only needs to have first and second digital audio interfaces 40a and 40b, to which the Applications Processor 33 and the Communications Processor 31 respectively can be connected. An audio hub 39 as shown in FIG. 2 could easily be used in this alternative mobile telephone. However, an audio hub 39a having only two digital audio interfaces would be sufficient, and might be smaller and cheaper than an audio hub having three digital audio interfaces.

Although reference is made herein to “audio signals”, the electrical signals that are handled by the “audio hub” integrated circuit can represent any physical phenomenon. For example, the term “audio signals” can mean not just signals that represent sounds that are audible by the human ear (for example in the frequency range of 20 Hz-20 kHz), but can also mean input and/or output signals from and/or to haptic transducers (typically at frequencies below 20 Hz, or at least below 300 Hz) and/or input and/or output signals from and/or to ultrasonic transducers (for example in the frequency range of 20 kHz-300 kHz) and/or to infrasonic transducers (typically at frequencies below 20 Hz). Possibly, an “audio hub” may not receive any audio signals in a range audible by the human ear, for instance an “audio hub” dedicated in design or in a particular use case may only receive haptic or ultrasonic signals related “audio signals”.

FIG. 3 is a block diagram, showing in more detail the form of the audio hub, or routing circuit 39. In this case, the audio hub, or routing circuit, is optimised for use in a device such as a smartphone, and will be described accordingly, although it will be appreciated that this illustrated circuit is only one example of a routing circuit in accordance with the invention, and the described use in a smartphone is only one possible use of the illustrated circuit. Thus, the audio hub has the functionality of an audio codec, taking audio data in one format and processing it, in a different format if required.

The audio hub routing circuit 39 acts as an audio codec, and is based around an audio processing engine, in the form of a digital mixing core 50, for example for providing signal routing between the various inputs and outputs of the audio hub routing circuit 39, including mixing audio signals from multiple inputs into a single output, and for providing signal processing functions. The signal processing functions may include some or all of: speaker enhancements such as multi-band compression, virtual surround sound (stereo widening) or compensation for non-linearities of speaker or device performance; voice path enhancements such as adaptive ambient noise cancellation, speech clarity enhancement, transmit noise cancellation, echo cancellation or sidetone and wind noise filtering; or digital mixing functions such as fully flexible signal routing, volume control and soft muting, equalisation, dynamic range control, programmable filtering and sample rate conversion, for example.

The audio hub routing circuit 39 has a number of digital audio interfaces 52.1, . . . , 52.N, which are intended to be connected to other circuits within the device, and supply signals to and from the digital mixing core 50. The number of digital audio interfaces can be selected during the design of the audio hub based on its expected range of uses. In this embodiment of the invention, optimised for use in a device such as a smartphone, there is a first digital audio interface that is primarily intended for connection to the applications processor 33, a second digital audio interface that is primarily intended for connection to the baseband processor 31, and a third digital audio interface that is primarily intended for connection to the wireless transceiver 37. The digital audio interfaces 52.1, . . . , 52.N may be interchangeable, but one interface can advantageously be made markedly wider than the others, so that it can be connected to one of the processors that is expected to need the most simultaneous accesses to the routing circuit.

In an embodiment of the invention, optimised for use in a device such as a digital still camera, there might be only one digital audio interface; in an embodiment of the invention, optimised for use in a device such as a simpler phone where the wireless transceiver function may not be required or may be performed by the baseband processor for example, there might be only two digital audio interfaces (as shown in FIG. 2b). It is also possible for an embodiment to have no digital audio interfaces. By contrast, in an embodiment of the invention intended for use in a home cinema surround sound device there might be, for example, six or more digital audio interfaces. Also the term “audio interface” should be understood to cover interfaces for carrying other similar streams of data such as ultrasonic or haptic data for example.

The audio hub routing circuit 39 also has pre-conditioning circuitry 54, for receiving analog input signals, for example from analog input transducers (such as microphones) 56, and an analog FM radio receiver 58. As with the digital interfaces, the number of analog inputs can be chosen during the design of the audio hub, based on the expected range of uses of the routing circuit, and it is possible for an embodiment to have no analog interfaces.

One or more analog input transducer can be in the form of a touchscreen, which might for example receive inputs from a user of the device, and pass these to a processor of the device over one of the digital audio interfaces, so that the processor can generate control signals for one or more operational feature of the device.

Signals from the pre-conditioning circuitry 54 are passed to switching circuitry 60, which also receives digital input signals, for example from digital input transducers (such as digital microphones) 62.

The switching circuitry 60 is connected to down-sampling circuitry 64, and the down-sampled signals from the down-sampling circuitry 64 are supplied to the digital mixing core 50, which is described in more detail below.

Output signals from the digital mixing core 50 are passed to up-sampling circuitry 66, and some of the up-sampled signals are passed to post-conditioning circuitry 68, which is connected to output terminals, to which analog output transducers (such as loudspeakers) 70 can be connected.

Other signals taken from the up-sampling circuitry 66 are also passed to a digital output formatting block 72 for connection to suitable transducers 74, such as digital input amplifiers connected to remote loudspeakers. For example, the digital output formatting block 72 might be able to put the signals into a Stereo Pulse Density Modulation (SPDM) format.

As before, the number of analog and/or digital outputs can be designed based on the expected range of uses of the routing circuit, and it is possible for an embodiment to have no analog or have no digital output interfaces. The analog outputs can be used in pairs for stereo outputs, or can be used mono. Different analog outputs are optimised for different uses, for example for the loads of speakers used in headphones or in speaker cabinets, and for example for grounded or differential (H-bridge) speaker loads.

The audio hub routing circuit 39 of this particular embodiment also includes a low latency processing block 90, which is connected to receive digital signals directly from the output of the switching circuitry 60, and to pass output signals via adders 92.1, . . . , 92.P onto the output lines from the up-sampling circuitry 66. The low latency processing block 90 can be suitable for providing a specific signal processing function, for signals that should not be subject to any unnecessary delay, that is to say any additional delay introduced by the digital mixing core 50, however small this may be. In this illustrated embodiment, the low latency processing block 90 includes digital filters, which may be adaptive, for use in a feedforward noise cancellation system. In this embodiment since the input signals are taken before the down-sampling block, the sample rate of the data streams and associated signal processing occurs at a substantially higher sample rate (e.g. 8 times, or even 64 times, the usual 48 kHz sample rate. i.e. 384 kHz, or 3.072 MHz) than the signal processing in the digital mixer core, so the low latency may be achieved more easily.

That is, one or more microphones can be used to generate signals that represent ambient noise in the region of the device (for example in a handset or in a headset). These signals are filtered, in order to generate output signals that can be passed to one or more speaker (typically in the same handset or headset), such that these signals produce sounds that are equal in amplitude but opposite in phase to (and thus have the effect of cancelling out) the ambient noise. In order for this type of system to work optimally, the time taken for the signal processing should be substantially equal for the time taken for the sound waves to pass around the device, and so it can be seen that any latency in the signal processing will have an effect on how optimally the system works.

In this embodiment, there are connections between the digital mixing core 50 and the low latency processing block 90, for example so that adaptive filters in the low latency processing block 90, for use in a feedforward noise cancellation system for example, can be controlled from the digital mixing core 50, possibly on the basis of results of signal processing in the digital mixing core 50.

The audio hub routing circuit 39 also includes a control interface 100, for receiving control signals, for example from a processor integrated circuit, typically the Applications Processor 33, located in the device. These control signals might for example inform the routing circuit 39 of the operational state of the overall device, for example which functions are active.

The audio hub routing circuit 39 also includes a clock generator 80, for receiving master clock signals and generating system clocks, as described in more detail below. In this illustrated embodiment, the clock generator 80 receives Q master clock signals and generates R system clocks. For example, in the case of a smartphone, a master clock signal at a frequency of 13 MHz might be available whenever the telephone related circuitry is active, but, when the telephone related circuitry is not active (as in “flight safe mode” for example), the 13 MHz clock might not be available, and the only available clock might be a 32 kHz crystal.

Digital signals output from the up-sampling circuitry 66 are also passed to a multiplexer 84, which can select one or more of these output signals to be fed back as an input to the digital mixing core 50. The fed back signals can be used for echo cancelling, for example.

FIG. 4 is a more detailed block diagram of the pre-conditioning circuitry 54 in the audio hub routing circuit 39 of this embodiment.

As described above, the pre-conditioning circuitry 54 has a number of inputs, for receiving analog input signals, for example from analog input transducers 56, an FM receiver circuit 58, or the like. Each of these inputs is connected to a respective pre-conditioning block 138, comprising an amplifier 140, with the resulting amplified signal being passed to a respective analog-digital converter (ADC) 142. The analog-digital converters 142 in this illustrated embodiment are over-sampling ADCs, e.g. delta-sigma ADCs. The gain of each of the amplifiers 140 can be controlled independently, by writing suitable values to registers on the chip.

FIG. 5 is a more detailed block diagram of the switching circuitry 60 in the audio hub routing circuit 39 of this embodiment. The switching circuitry receives a number of pre-conditioned signals from the pre-conditioning circuitry 54, these signals being digitised versions of the analog input signals. Each of the pre-conditioned signals is passed to a first input of a multiplexer 160. The second input of each multiplexer 160 is connected to receive a respective digital input signal, received from the digital input transducers 62.

External components are then typically connected to the routing circuit 39 such that, for use in a given device, or at least at any one time, each multiplexer is receiving a signal only from one of the analog inputs or from one of the digital inputs, but preferably not from both. Depending on whether the input signals to the audio hub routing circuit 39 are analog, or digital, or a mixture of the two, the multiplexers 160 can be controlled so that the appropriate signals are selected as the switched digital output signals.

FIG. 5 shows an implementation in which there are the same number (say, M) of connections for digital input transducers 62 as there are connections for analog input signals, and so there are M multiplexers 160, each receiving a signal from one of the analog inputs and a signal from one of the digital inputs.

FIG. 6 is a more detailed block diagram showing an alternative form of the switching circuitry 60 in the audio hub routing circuit 39. As in FIG. 5, each of the digitised versions of the analog input signals is passed to a first input of a respective multiplexer 160.

In this case, the M-bit wide combined digital input signal is passed to a number of M-bit multiplexers 164, a respective one of which has its output connected to the second input of each switch 160. The multiplexers 164 are controlled so that they select a respective one of the bits of the combined digital input signal, and the switches 160 are controlled as described above to select either the digitised version of the analog input signal, or the digital input signal as the output signal of the switching circuitry 60.

Although illustrated as single wire data streams, the input digital data streams or the digitised data streams may be multi-bit, either as parallel buses or serial multi-bit data streams, and may be time-multiplexed on a single bus, with consequent adjustment of the structure of the multiplexer blocks.

FIG. 7 is a more detailed block diagram showing one possible form of the down-sampling circuitry 64 in the audio hub routing circuit 39.

Each of the signals output from the switching circuitry 60 is passed to a respective down-sampler 170 to generate a respective down-sampled signal. The down-sampler 170 could for example comprise a digital filter, such as a FIR filter or an IIR filter with different input and output sample rates.

Where, as described above, the analog-digital converters 142 are over-sampling ADCs, the down-sampler 170 can convert the digital signals to a lower sample rate, that can conveniently be processed by the signal processing circuitry in the digital mixing core 50, albeit with a larger bit width to avoid increasing quantisation noise.

FIG. 8 is a more detailed block diagram showing one possible form of the up-sampling circuitry 66 in the audio hub routing circuit 39.

Each of the signals output from the digital mixing core 50 is passed to a respective up-sampler 180 to generate a respective up-sampled signal. The up-sampler 180 could for example take the form of a digital filter, such as a FIR filter or an IIR filter.

FIG. 9 is a more detailed block diagram of the post-conditioning circuitry 68 in the audio hub routing circuit 39.

The post-conditioning circuitry 68 has a number of inputs, each for one of the up-sampled signals generated by the up-sampling circuitry 66, and each connected to a respective post-conditioning block 188.

Each post-conditioning block 188 includes a respective digital-analog converter 190, and the resulting analog signal is passed to a respective amplifier 192, and the resulting amplified signal is output. The amplifiers 192 can provide single-ended outputs (as shown in FIG. 9) or differential outputs, and they can be of any convenient type of amplifier, such as Class A/B, Class D, or Class G amplifiers, high power amplifiers, or high voltage amplifiers.

FIG. 10 is a further schematic diagram of the audio hub routing circuit 39, in this case showing the first digital audio interface 52.1 and the Nth digital audio interface 52.N, but showing only in outline the pre-conditioning circuitry 54, the switching circuitry 60, the down-sampling circuitry 64, the up-sampling circuitry 66, the post-conditioning circuitry 68, and the digital output formatting block 72, and showing more detail of the digital mixing core 50.

Specifically, the digital mixing core 50 includes multiple digital signal processing blocks, of which a first digital signal processing block (DSP1) 102 and an Nth digital signal processing block (DSPN) 112 are shown. The digital signal processing blocks 102, 112 can be programmed at first instantiation, or by download of DSP code stored either on-chip or off-chip, to perform a wide range of signal processing functions, but they can be optimised for performing specific functions. For example, each programmable digital signal processing block might have an amount or type of memory or specialised computational hardware that allows it to perform specific functions, or might have a special instruction set that is optimised for expected functions. The number of such programmable digital signal processing blocks, and their specific properties, can be chosen depending on the expected range of uses of the audio hub 39. In an example where one possible intended use of the audio hub routing circuit 39 is in a smartphone, a first programmable digital signal processing block can be used for processing voice signals in the transmit path of the phone, a second programmable digital signal processing block can be used for processing voice signals in the receive path of the phone, and a third programmable digital signal processing block can be used for processing non-voice signals.

In addition, signal processing blocks optimised for a more restricted range of functions can be provided. In this illustrated example, the digital mixing core 50 also includes fully programmable five-band equalisers, of which two such equalisers 118, 120 are shown, and the digital mixing core 50 also includes filters, which are fully programmable such that they can have high-pass and/or low-pass functionality, and of which one such filter 134 is shown in FIG. 10.

The digital mixing core 50 also includes a dynamic range compression (DRC) block 150. Also shown in FIG. 10 is another functional block 154 that might have some other signal processing functionality.

Further, the audio processing engine 50 includes an up-sampling block 162, and a down-sampling block 164, for moving between domains with signals at different sample rates. For example, the up-sampling block 162 and down-sampling block 164 include respective sample rate conversion (SRC) blocks for converting between the voice processing domain with sample rates of 8 kHz or 16 kHz and the more general audio processing domain of 48 kHz, as well as SRC blocks for converting between other integer ratios, and additional SRC blocks for converting between asynchronous sample rates.

Although not shown in FIG. 10, a further possibility is to provide a functional block in the form of a tone generator, which outputs an audio or haptic signal having a predetermined characteristic, without requiring any input audio signal. Similarly, a further possibility, albeit not shown in FIG. 10, is to provide a functional block that requires an audio input, but does not provide an audio output, for instance a block that contains a rarely updated asynchronous control signal for use by another block, such as a signal level threshold detect signal for muting other audio paths or for disabling ambient noise cancellation if there is little ambient noise.

There are thus provided various functional blocks within the digital mixing core 50, as well as signal inputs to the digital mixing core 50, and signal outputs from the digital mixing core 50. These are all interconnected by the mixing fabric of the digital mixing core 50, as described in more detail below.

From the point of view of the mixing fabric, every signal input to the digital mixing core 50, and every output from one of the functional blocks, represents a signal source port. In FIG. 10, each of these signal source ports is represented by a solid black circle.

Also, from the point of view of the mixing fabric, every signal output from the digital mixing core 50, and every input to one of the functional blocks, represents a signal destination port. In FIG. 10, each of these signal destination ports is represented by a solid black diamond.

Thus, it can be seen in FIG. 10 that some functional blocks have one input, while other functional blocks have multiple inputs. For example, the equaliser 120 has one input 122, while DSP1 102 has at least four inputs 104, 106, 108, 110. This means that DSP1 is able to process at least four separate streams of input data.

Although described as single ports, the source ports and the destination ports may be multi-bit, handling either parallel (for example 16-bit or 24-bit) or serial multi-bit data streams, and may be time-multiplexed on a single connection.

Further, the mixing fabric is such that each of the signal destination ports, that is, the inputs for any of the functional blocks or the signal outputs from the digital mixing core 50, is associated with a mixing “channel” comprising a predetermined number of “selector ports” each of which can be configured to receive signal data from a selectable single source port. These channels or mixer elements are illustrated, butted against respective signal destination ports in FIGS. 11-13, in which each of these selector ports is represented by a solid black square.

Some channels may simply forward the data unchanged to the respective destination port but the mixing fabric is such that at least some of the channel output data signal streams may be derived from a mix of signals from signal sources, possibly scaled by different respective scaling factors. This mixing operation performed by a given channel may be different in different applications or use cases of the audio hub.

FIGS. 11 to 13 illustrate various examples of channels or mixer elements of the mixing fabric, shown shaded, attached to signal destinations on various functional blocks. Each mixer element comprises one or more selector ports, to each of which a single chosen signal source may be attached as described below.

FIG. 11 shows a situation where a functional block 170 has one input (destination port, from the point of view of the mixing fabric) 171. FIG. 11(a) shows that this input 171 can receive a signal from one signal source on one selector port 172, and FIG. 11(b) shows a more detailed view of the same channel structure in which the signal from the one signal source can be scaled before being applied to the input 171.

FIG. 12 shows a situation where a functional block 174 has two inputs 175, 176 and two respective channels or mixer elements. FIG. 12(a) shows that the input 175 can receive signals from two signal sources on selector ports 177, 178 respectively, and that the input 176 can receive signals from two signal sources on selector ports 179, 180 respectively, and FIG. 12(b) shows a more detailed view of the same channel structure in which the signals from the two selector ports 177, 178 can be scaled and added together before being applied to the input 175, while the signals from the two selector ports 179, 180 can be scaled and added together before being applied to the input 176.

FIG. 13 shows a situation where a functional block 181 has one input 182. FIG. 13(a) shows that the input 182 can receive signals from four signal sources 183, 184, 185, 186, and FIG. 13(b) shows a more detailed view of the same channel structure in which the signals from the four signal sources 183, 184, 185, 186 can be scaled and added together before being applied to the input 182.

FIG. 14 is therefore a slightly more detailed version of FIG. 10, showing channels with various numbers of selector ports butted onto respective destination ports (block inputs) of each of the signal destinations (that is, the functional blocks and the signal outputs from the mixing core).

For example, the input 122 of the equaliser 120 is able to receive signals from four signal sources on respective selector ports 188, 189, 190, 191; while the input 104 of DSP1 102 is able to receive signals from three signal sources on respective selector ports 192, 193, 194; the input 106 of DSP1 102 is able to receive signals from two signal sources on respective selector ports 195, 196; the input 108 of DSP1 102 is able to receive signals from one signal source on selector port 197; and the input 110 of DSP1 102 is able to receive signals from one signal source on selector port 198.

As mentioned above, the mixing fabric allows signals from arbitrarily selected signal sources to be routed to the signal destinations, while being combined in cases where a single signal destination is required to receive a mix of signals from multiple signal sources. That is, the mixing fabric allows the user to select which signal sources are to be connected to which signal destinations, based on whichever criteria the user chooses to apply, without restrictions imposed by the mixing fabric itself.

It would be possible to physically implement the mixing fabric as shown in FIG. 14, with separate adders and multipliers as shown for each signal destination on each functional block. However it is greatly advantageous in terms of silicon real estate, power, and centralisation of control functions to implement the mixing fabric as a single mixer circuit (or possibly a number of such mixer circuits, for a more complex system, with the number of mixer circuits still being very much smaller than the number of signal destinations), and time multiplex this circuit between the various destinations, such that it services the requirements of each required signal destination in turn within each audio signal sample period.

The mixing fabric thus includes a mixer (or a plurality of mixers), shared between the signal sources and destinations on a time division multiplexed basis. That is, within one data sample period, the same mixer can route data from many signal sources (or many groups of signal sources) to respective signal destinations. However, the clock frequency of the mixer block is less than would be required to be able to establish signal paths between every signal source and every signal destination during one data sample period. Thus, the mixer block does not simply cycle through all of the possible signal paths. When there is a single mixer, operating at a particular mixer clock frequency CR, and there are a number of signal sources Ns,i and signal destinations Nd,i operating at the ith sample rate of the set of available sample rates SR,i, then CR is very much less than the sum of the product SR,i·Nd,i·Ns,i taken over all values of i. When there are a number m of such mixers, operating at the mixer clock frequency CR, then the product m·CR is very much less than the sum of the product SR,i·Nd,i·Ns,i taken over all values of i. When there are multiple mixer clock frequencies CR,j, and a number mj of mixers operating at the jth mixer clock frequency CR,j, then the sum of the product mj·CR,j taken over all values of j is very much less than the sum of the product SR,i·Nd,i·Ns,i taken over all values of i. The routings can be configured by the user of the audio hub circuit, and moreover can be reconfigured in use, in order to provide different functionality in different situations.

FIG. 15 is a block diagram, illustrating the general form of the digital mixing core 50 in the audio codec 39 of FIG. 3, emphasising the mixing fabric rather than the functional blocks.

FIG. 15 shows a single block 200, representing in general terms the set of various functional blocks, i.e. signal processing blocks, 200.1, . . . , 200.N in the digital mixing core 50. FIG. 15 also shows an input 214, at which signals are introduced into the mixing core 50, and an output 216 at which signals are led out of the mixing core 39. (It will be appreciated from the description of FIG. 10 above that a typical circuit will include multiple inputs and outputs, and thus the input 214 and output 216 are representative of those multiple inputs and outputs, for ease of illustration.)

Thus, functional blocks 200 can act as signal sources, providing signal source ports, and the input 214 can also act as a signal source, providing a signal source port, while the functional blocks 200 can also act as signal destinations, providing signal destination ports, and the output 216 can also act as a signal destination, providing a signal destination port. A signal processing block acts as a signal destination when receiving a signal to be processed, and as a signal source when passing a processed signal to an output or a subsequent functional block.

Each of the signal source ports associated with one of the functional blocks has a respective source buffer 202.1, . . . , 202.N associated therewith, and the signal source port associated with the input 214 has a source buffer 202.P associated therewith. Each of the source buffers 202.1, . . . , 202.N, 202.P is connected through a source selector block to a mixer 206. In this illustrated embodiment, the source selector block takes the form of a bus 204, which allows the mixer 206 to take data from the respective source buffer associated with any of the signal sources.

Output data from the mixer 206 is passed through a destination selector block to a respective destination buffer 210.1, . . . , 210.N, 210.Q associated with a respective one of the signal destination ports. Specifically, each destination buffer 210.1, . . . , 210.N is associated with a respective signal destination port on one of the functional blocks 200.1, . . . , 200.N, and the destination buffer 210.Q is associated with the signal destination port on the output 216. In this illustrated embodiment, the destination selector block takes the form of a bus 208, which allows the mixer 206 to pass data to the respective destination buffer associated with any of the signal destination ports.

The source buffers 202.1, . . . , 202.N and the destination buffers 210.1, . . . , 210.N can be located physically adjacent to the respective functional blocks 200, or to the mixer 206, or at any convenient location, as determined during the design of the routing circuit 39. Similarly, the buffer 202.P can be located close to the relevant signal input or to the mixer 206, and the buffer 210.Q can be located close to the relevant signal output or to the mixer 206.

Moreover, the design of circuitry connected to the input 214 or the output 216 might mean that it is not necessary to provide buffers within the digital mixing core 50. For example, an output register of a down-sampler connected to the input 214, or an input register of an upsampler connected to the output 216 might already provide suitable buffering. In other words, some source or destination buffers may be provided outside the digital mixing core.

In this illustrated embodiment, the buses 204, 208 are separate, allowing the mixer to read data from one of the buffers 202.1, . . . , 202.N, 202.P and write data to one of the buffers 210.1, . . . , 210.N, 210.Q simultaneously. In an alternative embodiment, a single bus could be used for this purpose, with a bus arbitration scheme to ensure that the mixer 206 does not attempt to read data from one of the buffers 202.1, . . . , 202.N, 202.P and write data to one of the buffers 210.1, . . . , 210.N, 210.Q at exactly the same time. However the separation of the input and output busses is advantageous in making it much easier to avoid timing conflicts between inputs and outputs and avoids having to share bandwidth of the bus.

In this illustrated embodiment, there is a single mixer 206, which services all of the signal destinations.

FIG. 16 is a block diagram, illustrating an alternative general form of the digital mixing core 50 in the routing circuit 39 of FIG. 3.

As in FIG. 15, FIG. 16 shows a single block 200, representing in general terms various functional blocks, i.e. signal processing blocks, 200.1, . . . , 200.N in the digital mixing core 50. FIG. 16 also shows an input 214, at which signals are introduced into the mixing core 50, and an output 216 at which signals are led out of the mixing core 39.

As in FIG. 15, each of the functional blocks that is capable of acting as a signal source has a respective buffer 202.1, . . . , 202.N, 202.P associated therewith. In this embodiment, the source selector comprises a first source bus 220 and a second source bus 222. Each of the first source bus 220 and a second source bus 222 is connected to every one of the buffers 202.1, . . . , 202.N, 202.P so that it can receive signals therefrom. The first source bus 220 is connected to a first mixer 224, and the second source bus 222 is connected to a second mixer 226. Thus, the first source bus 220 allows the first mixer 224 to take data from the respective buffer associated with any of the signal sources, and the second source bus 222 similarly allows the second mixer 226 to take data from the respective buffer associated with any of the signal sources.

Output data from each mixer 224, 226 is passed through a destination selector to a respective buffer 210.1, . . . , 210.N, 210.Q, with each buffer 210.1, . . . , 210.N, 210.Q being associated with a respective one of the signal destinations. In this embodiment, the destination selector block includes a multiplexer 228 and a bus 230. The multiplexer 228 determines based on an applied control signal (not shown) which of the first mixer 224 and the second mixer 226 is able at any one time to pass output data to the bus 230, and hence to the respective buffer associated with any of the signal destinations. One simple possibility is for the control signal to allow Mixer A 224 and Mixer B 226 to talk to bus 230 in alternate cycles of a fast processor clock.

Thus, in this embodiment, two mixers 224, 226 are provided. In fact, there can be any number of mixers, in order to provide the required or anticipated signal throughput. In general the mixer fabric will have more input signals to be mixed than destinations to service, so the input bus will saturate first, so two or more input buses (or any number of input buses that is small relative to the number of destinations) and the associated plurality of mixers may provide a useful increase in mixer fabric bandwidth if required.

FIG. 17 is a block diagram, illustrating the general form of an alternative digital mixing core 50 in the routing circuit 39 of FIG. 3.

As in FIG. 15, FIG. 17 shows a single block 200, representing in general terms various functional blocks, i.e. signal processing blocks, 200.1, . . . , 200.N in the digital mixing core 50. FIG. 17 also shows an input 214, at which signals are introduced into the mixing core 50, and an output 216 at which signals are led out of the mixing core 39.

Each of the functional blocks that is capable of acting as a signal source has a respective buffer 202.1, . . . , 202.N, 202.P associated therewith. Each of the buffers 202.1, . . . , 202.N, 202.P is connected through a first source selector to a mixer 206. In this illustrated embodiment, the source selector takes the form of a multiplexer 240, which can be controlled so as to allow the mixer 206 to take data from the respective buffer associated with any of the signal sources.

Output data from the mixer 206 is passed through a destination selector to a respective buffer 210.1, . . . , 210.N, 210.Q. Each buffer 210.1, . . . , 210.N, 210.Q is associated with a respective one of the signal destinations. In this illustrated embodiment, the destination selector takes the form of a multiplexer 242, which allows the mixer 206 to pass data to the respective buffer associated with any of the signal destinations.

Again, in this illustrated embodiment, there is a single mixer 206, which services all of the signal destinations.

FIG. 18 is a block diagram, illustrating a further alternative general form of the digital mixing core 50 in the routing circuit 39 of FIG. 3.

As before, FIG. 18 shows a single block 200, representing in general terms various functional blocks, i.e. signal processing blocks, 200.1, . . . , 200.N in the digital mixing core 50. FIG. 18 also shows an input 214, at which signals are introduced into the mixing core 50, and an output 216 at which signals are led out of the mixing core 39.

Each of the functional blocks that is capable of acting as a signal source has a respective buffer 202.1, . . . , 202.N, 202.P associated therewith. Each of the buffers 202.1, . . . , 202.N, 202.P is connected to a first source selector.

In this embodiment, the source selector comprises a first multiplexer 248 and a second multiplexer 250, which are connected to a first mixer 252 and a second mixer 254 respectively. Each multiplexer 248, 250 is connected with all of the buffers 202.1, . . . , 202.N, 202.P, and so the source selector allows each of the mixers 252, 254 to take data from the respective buffer associated with any of the signal sources.

Output data from the mixers 252, 254 is passed through a destination selector to a respective buffer 210.1, . . . , 210.N, 210.Q, with each buffer 210.1, . . . , 210.N, 210.Q being associated with a respective one of the signal destinations. In this embodiment, the destination selector takes the form of a multiplexer 256, which determines based on applied control signals (not shown) which of the first mixer 252 and the second mixer 254 is able at any one time to pass output data, and which of the buffers 210.1, . . . , 210.N, 210.Q associated with the signal destinations can receive that data.

Thus, in this embodiment, two mixers 252, 254 are provided, and either mixer can provide data to any of the signal destinations. In fact, there can be any number of mixers, in order to provide the required or anticipated signal throughput.

FIG. 19 is a block diagram, illustrating a further alternative general form of the digital mixing core 50 in the routing circuit 39 of FIG. 3. The digital mixing core 50 shown in FIG. 19 is the same as that shown in FIG. 18, except that the destination selector associates each signal destination with one of the mixers 252, 254.

Thus, the signal destinations are divided into two groups, for example on the basis that each group will be expected to use an approximately equal share of the total available mixer resources. As shown in FIG. 19, one group of destinations includes the output 216 and the functional blocks 200.1, . . . , 200.J, while the other group of destinations includes the functional blocks 200.K, . . . , 200.N.

The destination selector then comprises two multiplexers 256a, 256b, associated with the mixers 252, 254 respectively. Output data from the mixer 252 is passed through the multiplexer 256a to a respective buffer 210.1, . . . , 210.J, 210.Q, with each buffer 210.1, . . . , 210.J, 210.Q being associated with a respective one of the signal destinations in the first group. Output data from the mixer 254 is passed through the multiplexer 256b to a respective buffer 210.K, . . . , 210.N, with each buffer 210.K, . . . , 210.N being associated with a respective one of the signal destinations in the second group.

FIG. 20 is a block diagram, showing the form of the mixer and the buffers and source and destination selectors in the digital mixing core 50. In FIG. 20, there is one mixer, as in FIGS. 15 and 17. When there is more than one mixer, as in FIGS. 16, 18 and 19, some or all of the mixer structure is duplicated.

In FIG. 20, the mixer 290 is shown connected to receive input data from buffers 202.1, . . . , 202.N, 202.P associated with the respective signal sources, and is connected to pass output data to buffers 210.1, . . . , 210.N, 210.Q associated with the signal destinations.

The mixer 290 is based around a multiply-accumulate block (MAC) 292, the structure of which is described in more detail below. This multiply-accumulate block 292 is time-multiplexed between the different sources and destinations, again as described below.

A source selector block 294 determines at any given moment which one of the data sources acts as a first source of data (MAC Input 1) for the multiply-accumulate block 292, and a destination selector block 296 determines at any given moment which one of the data destinations acts as the destination for data output from the multiply-accumulate block 292.

The source selector block 294 selects the source on the basis of a source input select signal received from a controller 300, on the basis of information received from a register bank 298. The destination selector block 296 selects the destination on the basis of an output destination select signal received from the controller 300, again on the basis of information received from register bank 298. As mentioned above, the source selector block 294 and destination selector block 296 can take any convenient form, for example they can be in the form of suitably controlled buses or multiplexers.

The register bank 298 also acts as a second source of data (MAC Input 2) for the multiply-accumulate block 292. MAC Input 2 provides the scaling factor to be applied to the selected data being processed.

FIG. 21 is a block diagram, showing an alternative form of the mixer and the associated buffers and selector blocks in the digital mixing core 50.

In this embodiment, the mixer 310 comprises a multiply-accumulate block 292, and is connected to a source selector block 294 and a destination selector block 296, which are the same as the source selector block 294 and destination selector block 296 shown in FIG. 15.

In the embodiment shown in FIG. 21, a register bank 312 and a controller 314 have generally the same functions as the corresponding components of the mixer 290 shown in FIG. 20, but are not considered to be part of the mixer. Instead, a memory 316 within the mixer 310 stores data received from the register bank 312, and supplies the source input select signal to the source selector bank 294 and the output destination select signal to the destination selector bank 296 on the basis of the data received from the register bank 312.

FIG. 22 is a block diagram, showing one possible form of the multiply-accumulate block in the mixer of FIG. 20 or 21.

In FIG. 22, the multiply-accumulate (MAC) block 292 is shown, receiving the data from the first source (MAC Input 1) and the data from the second source (MAC Input 2) as inputs to a multiplier 330. The output of the multiplier 330 is applied as an input to an adder 332, and the output of the adder 332 is applied in turn to a register 334, acting as a one clock period delay element, based on a clock signal that it receives. The output of the register 334 is provided as an output of the multiply-accumulate block 292, and is also fed back to a second input of the adder 332.

(As an alternative, it would be possible to take the output of the adder 332 as the output of the MAC block.)

Thus, during one clock period, the multiply-accumulate block 292 receives data from the first source (MAC Input 1), multiplies that data value by a multiplication coefficient, in the form of the data from the second source (MAC Input 2), and adds the result to the previously received sum. This can be allowed to continue for several clock periods, so that the output of the multiply-accumulate block 292 represents the sum of several data values received from the first source, each scaled by a respective multiplication coefficient. When the desired sum has been calculated, and the output has been buffered in the intended destination buffer 210, the value stored in the register 334 can be cleared. Alternatively the value can just be left, and overwritten by the next partial sum by disabling the adder for the next first received data.

FIG. 23 is a block diagram, showing an alternative form of the multiply-accumulate block in the mixer of FIG. 20 or 21.

The multiply-accumulate block 292 shown in FIG. 23 is the same as that shown in FIG. 22, except that the output of the register 334 is passed to one input of a controllable multiplexer 336. The other input of the multiplexer 336 is connected to the input of the multiply-accumulate block 292 by means of a bypass path 338. This means that, when the required output data is simply the input data from the first source (MAC Input 1), without any scaling or mixing with other data values, the bypass path input of the multiplexer 336 can be selected, and connected to the output of the multiply-accumulate block 292.

FIG. 24 is a flow chart, FIG. 25 is an overview, and FIG. 26 is a timing diagram, illustrating the operation of a mixer as illustrated in FIG. 20 or 21.

FIG. 26 shows a relatively high-speed clock DCK, and a lower speed clock SCK. The frequency of the lower speed clock SCK is the sample rate of the audio data streams and thus determines the rate at which this data needs to be processed. For example, voice processing for a telephone call might require data to be generated at a frequency of 8 kHz, while other audio data processing applications might require data to be generated at a frequency of 48 kHz. In this illustrated embodiment, only the leading edge of each clock cycle is used, and so it is irrelevant that SCK is not shown with a 50% duty cycle.

The high-speed clock DCK determines the speed at which the multiply-accumulate block 292 operates, i.e. the speed at which the MAC cycles through the various inputs. It will be noted that a typical value for the data clock DCK might be, say, 48 MHz, which might for example be of the order of 1000 times faster than the sample rate clock SCK for a typical process. Thus, FIG. 26 is not to scale, but it illustrates the processes required.

FIGS. 24, 25 and 26 illustrate the operation of the mixer 290 in the case where data from two sources are to be mixed together and applied to an output. During a first period of the sample clock signal SCK, or first time interval T1 (or any earlier time interval), a first process, process A, is performed by one of the functional blocks 200.A (or, equivalently, data is received on an input of the digital mixing core), and this produces a first data value (step 450 in FIG. 24), which is made available, i.e. stored, in the data source buffer 202.A associated with that data source within the first time interval T1. The first data value is stored in the data source buffer 202.A (step 452 in FIG. 24), such that it is available to the mixer 290 for the whole of the subsequent sample clock period, or second time interval, T2.

FIGS. 25 and 26 show a partitioning of the buffer 202.A, such that data is written to a first half 202.A1 of the buffer 202.A at some time during the first time interval T1, and is then transferred to a second half 202.A2 of the buffer 202.A at the end of the first time interval T1, such that it can be accessed by the mixer 290 from the second half 202.A2 of the buffer 202.A at any time throughout the second time interval T2.

During the same first time interval T1 (or any earlier time interval), a second process, process B, is performed by one of the functional blocks 200.B (or, equivalently, data is received on an input of the digital mixing core), and this produces a second data value (step 454 in FIG. 24), which is made available in the data source buffer 202.B associated with that data source. The second data value is stored in the data source buffer 202.B (step 456 in FIG. 24), such that it is available to the mixer 290 for the whole of the subsequent sample clock period T2. FIGS. 25 and 26 show a partitioning of the buffer 202.B in the same way as the buffer 202.A, described above.

At a point in time t2a during the sample clock period T2, the multiply-accumulate block 292 is caused to obtain on the first input (MAC Input 1) the data from the buffer 202.A2, and so it obtains the first sample of data (step 458 in FIG. 24) on the rising edge of the data clock DCK. (Data transitions could equally well be timed to occur on the falling edges of the data clock DCK.) During the clock period of the data clock DCK between the period t2a and t2b, this first sample of data is scaled (denoted by the “X” 350), by being multiplied in the multiplier 350 by a multiplication coefficient obtained on the second input (MAC Input 2) (step 460 in FIG. 24). The result of this scaling is stored in the register 334 of FIG. 22.

At the point in time t2b after that clock period between t2a and t2b of the data clock DCK, the multiply-accumulate block 292 is caused to obtain on the first input (MAC Input 1) the data from the buffer 202.B2, and so it samples the second data value (step 462 in FIG. 24). During the clock period of the data clock DCK between the period between t2b and t2c, the second sampled data value is scaled (denoted by the “X” 352), by being multiplied in the same multiplier 350 by a second scaling coefficient obtained on the second input (MAC Input 2) (step 464 in FIG. 24). The result of this scaling is added (denoted by the “+” 354) to the result of scaling of the first sample of data (step 466 in FIG. 24).

The result of this addition is stored in a first half 210.Z1 of the output buffer 210.Z associated with the data destination that is intended to receive the output data, namely the functional block (or the output of the digital mixing core) 200.Z (step 468 in FIG. 24). As before, FIGS. 25 and 26 show a partitioning of the buffer 210.Z, such that data is written to a first half 210.Z1 of the buffer 210.Z during the second time interval T2, and is then transferred to a second half 210.Z2 of the buffer 210.Z, where it remains available until the end of the subsequent sample clock period T3.

At an arbitrary time t3a during the sample clock period T3, the output data is sampled by the functional block 200.Z acting as the data destination (step 470 in FIG. 24), and it can then be processed by that functional block in a subsequent process (step 472 in FIG. 24). Of course, if the data destination is an output of the digital mixing core, the result data can be output during the sample period T3 (step 474 in FIG. 24).

Thus, the multiply-accumulate block 292 generates the required data in such a way that this required data is available to the block that is intended to receive it at the required time, no matter where in the audio sample period that is. This greatly simplifies the timing considerations required in configuring the digital mixer core. That is, the arrangement of source buffers and destination buffers means that the operation of the multiply-accumulate block 292 can be scheduled in the knowledge that the data that it requires from the data source(s) will be available for the whole of one sample period (so that the scheduling does not need to take account of the exact points in time, within that sample period, at which the data will become available), and that the data that it supplies to a data destination will be available for the whole of another sample period, (so that the scheduling does not need to take account of the exact point in time, within that sample periods, at which the data will be required).

In other words, data presented at a source port by the start of one sample period will be available for processing by the destination block for the whole of the following sample period. Assuming the destination block can complete its operations within the latter sample period, the latency per stage in the signal processing chain is thus a fixed two sample periods, one for the mixer and one for the processing. This greatly simplifies latency calculations for the signal chain.

This latency is also independent of the clocks used to clock the mixer (and to clock the functional blocks), which makes any clock frequency scaling invisible to the audio signal path.

If additional latency is required in some path, for example to match that introduced by extensive processing in a parallel path, the mixer output may be fed back, repeatedly if necessary, to its input, via a signal processing block comprising a simple register.

As described above, FIG. 26 is an illustrative timing diagram (not to scale), showing one data sample from a first data source (process A) being combined with one data sample from a second data source (process B) to generate one result sample that is provided to a data destination (process Z).

Of course, most real processes require this operation to be performed repeatedly, once per sample period, and FIG. 27 is a further timing diagram showing this repetition.

Thus, in FIG. 27, as in FIG. 26:

in sample clock period T1, data from process A (e.g. functional block 200.A) is stored in buffer 202.A1, data from process B (e.g. functional block 200.B) is stored in buffer 202.B1; at the start of sample clock period T2, data stored in buffer 202.A1 is transferred to buffer 202.A2 data stored in buffer 202.B1 is transferred to buffer 202.B2; during sample clock period T2, data from buffers 202.A2 and 202.B2 is mixed (MIX 1), with the result stored in buffer 210.Z1 at the start of sample clock period T3, data stored in buffer 210.Z1 is transferred to buffer 210.Z2 during sample clock period T3, data from buffer 210.Z2 is made available to the data destination (e.g. functional block 200.Z).

The process is repeated one sample clock period later. That is:

in sample clock period T2, data from process A (e.g. functional block 200.A) is stored in buffer 202.A1, data from process B (e.g. functional block 200.B) is stored in buffer 202.B1; at the start of sample clock period T3,

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