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Digital signal routing circuit

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Digital signal routing circuit


An integrated circuit for digital signal routing. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44 kHz or 48 kHz.

Inventors: Graeme Gordon Mackay, Jonathan Timothy Wigner, Gordon Richard McLeod
USPTO Applicaton #: #20120300960 - Class: 381119 (USPTO) - 11/29/12 - Class 381 
Electrical Audio Signal Processing Systems And Devices > With Mixer



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The Patent Description & Claims data below is from USPTO Patent Application 20120300960, Digital signal routing circuit.

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This application claims the benefit of U.S. Provisional Application No. 61/491,041, filed May 27, 2011, the entire disclosure of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a signal routing circuit, and in particular to a signal routing circuit that can be used as a digital audio hub, for interconnecting various signal sources and signal destinations in consumer devices, of which smartphones are just one example.

2. Description of the Related Art

It is known to provide an integrated circuit that acts as an “audio hub”, which is able to receive a number of signals from analog and digital sources, converting the analog signals to digital signals and then combining or processing the signals in the digital domain, in order to generate output signals. If required, the output signals can be converted by the audio hub into analog signals, in order to be applied to analog transducers such as headphones or speakers. Such a digital audio hub device can be incorporated into a consumer device, such as a smartphone or the like, allowing the received signals to be processed in predetermined ways.

It is desirable to allow the customer of the “audio hub” integrated circuit to use it to interconnect a number of different signal processing components within a consumer device in a flexible manner, without being restricted to specific external devices or to specific processing paths.

The invention is defined by the claims appended hereto.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention, and to show how it may be out into effect, reference will now be made, by way of example, to the accompanying drawings, in which:—

FIG. 1 shows a mobile telephone and various peripheral devices;

FIG. 2a shows components of the audio processing circuitry in the mobile telephone of FIG. 1;

FIG. 2b shows components of the audio processing circuitry in an alternative mobile telephone;

FIG. 3 is a first more detailed block diagram, showing the form of the audio hub routing circuitry in the audio processing circuitry of FIG. 2a or 2b;

FIG. 4 is a still more detailed block diagram, showing the form of the pre-conditioning circuitry in the routing circuitry of FIG. 3;

FIG. 5 is a further still more detailed block diagram, showing the form of the switching circuitry in the routing circuitry of FIG. 3;

FIG. 6 is a further still more detailed block diagram, showing an alternative form of the switching circuitry in the routing circuitry of FIG. 3;

FIG. 7 is a further still more detailed block diagram, showing the form of the down-sampling circuitry in the routing circuitry of FIG. 3;

FIG. 8 is a further still more detailed block diagram, showing the form of the up-sampling circuitry in the routing circuitry of FIG. 3;

FIG. 9 is a further still more detailed block diagram, showing the form of the post-conditioning circuitry in the routing circuitry of FIG. 3;

FIG. 10 is a further still more detailed block diagram, showing the form of the digital mixing core in the routing circuitry of FIG. 3;

FIG. 11 shows in more detail a part of a functional block in the digital mixing core of FIG. 10;

FIG. 12 shows in more detail a part of another functional block in the digital mixing core of FIG. 10;

FIG. 13 shows in more detail a part of a further functional block in the digital mixing core of FIG. 10;

FIG. 14 is a further block diagram, showing the digital mixing core of FIG. 10, and showing more detail of the functional blocks;

FIG. 15 is a block diagram, illustrating a different aspect of the digital mixing core in one embodiment;

FIG. 16 is a block diagram, illustrating the different aspect of the digital mixing core in another embodiment;

FIG. 17 is a block diagram, illustrating the different aspect of the digital mixing core in a further embodiment;

FIG. 18 is a block diagram, illustrating the different aspect of the digital mixing core in a still further embodiment;

FIG. 19 is a block diagram, illustrating the different aspect of the digital mixing core in a still further embodiment;

FIG. 20 is a block diagram, illustrating a part of the digital mixing core in one embodiment;

FIG. 21 is a block diagram, illustrating a part of the digital mixing core in another embodiment;

FIG. 22 is a block diagram, illustrating a form of a multiply-accumulate block in the digital mixing core;

FIG. 23 is a block diagram, illustrating in more detail an alternative form of the multiply-accumulate block in the digital mixing core;

FIG. 24 is a flow chart, illustrating a process performed in the mixer;

FIG. 25 is a further illustration of the process shown in FIG. 24;

FIG. 26 is a first timing diagram, illustrating the process of FIG. 24;

FIG. 27 is a second timing diagram, illustrating more detail of the process of FIG. 26;

FIG. 28 is a third timing diagram, illustrating a further alternative process;

FIG. 29 is a fourth timing diagram, illustrating a still further alternative process;

FIG. 30 is a flow chart, illustrating a method of defining the operation of the switching circuitry; and

FIG. 31 is a representation of a computer screenshot, illustrating a stage in the method of FIG. 30;

FIG. 32 is a block diagram, showing the routings in a use case defined by the process of FIG. 30;

FIG. 33 is a register map, illustrating an initial state of the register bank in the process of FIG. 30;

FIG. 34 is a block diagram, providing an alternative illustration of the routings in the use case of FIG. 32 on the digital mixing core of FIG. 14;

FIG. 35 is a register map, illustrating a state of the register bank at a further point in the process of FIG. 30;

FIG. 36 is a representation of the digital mixing core, showing the functional blocks involved in the use case shown in FIG. 32;

FIG. 37a shows a routing in a further use case;

FIG. 37b shows a routing in a still further use case;

FIG. 38 is a timing diagram, illustrating a first series of calculations in a process carried out in the mixer;

FIG. 39 is a timing diagram, illustrating a second series of calculations in a process carried out in the mixer;

FIG. 40 is a timing diagram, illustrating a third series of calculations in a process carried out in the mixer;

FIG. 41 is a timing diagram, illustrating a fourth series of calculations in a process carried out in the mixer;



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Key IP Translations - Patent Translations


stats Patent Info
Application #
US 20120300960 A1
Publish Date
11/29/2012
Document #
13481403
File Date
05/25/2012
USPTO Class
381119
Other USPTO Classes
International Class
04B1/00
Drawings
62



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