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Capacitance difference detecting method

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Capacitance difference detecting method

A capacitance difference detecting method, comprising: (a) utilizing a voltage control unit to cooperate with a first capacitor to be detected and a second capacitor to be detected to generate a first voltage and a second voltage; and (b) computing a capacitance difference between the first capacitor to be detected and the second capacitor to be detected according to the first voltage, the second voltage and a parameter of the voltage control unit.

Inventors: Kun-Chih Lin, Wen-Chi Wu
USPTO Applicaton #: #20120286811 - Class: 324679 (USPTO) - 11/15/12 - Class 324 

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The Patent Description & Claims data below is from USPTO Patent Application 20120286811, Capacitance difference detecting method.

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This application is a division application of co-pending U.S. application Ser. No. 12/703,732, filed on Feb. 10, 2010 and included herein by reference.


1. Field of the Invention

The present invention relates to a capacitance difference detecting method, and particularly relates to a capacitance difference detecting method that need not to measure real capacitance value of the capacitor to be detected.

2. Description of the Prior Art

In modern electronic apparatuses, the capacitor type detector, which is always applied to a touch sensing device such as a touch sensing panel, is a well know technology. However, a prior art capacitor type detector may has different problems. For example, if the capacitor type detector is utilized as the touch sensing panel, the adhesion of ITO may cause non equal capacitance. Additionally, an electronic apparatus may have the problem of parasitical capacitance, background capacitance or system distribution, which may cause low yield or high cost to examine product defect. Besides, if the background capacitance is too large but the variance for detected capacitance of the capacitor type detector is too small (for example, the capacitance variation caused by finger touch), it will be hard to determine the variation of the detecting capacitance. High resolution is needed to determine capacitance variation in this case.

FIG. 1 is a circuit diagram illustrating a prior art capacitance difference detecting circuit. In FIG. 1, the capacitance difference detecting circuit 100 utilizes a relaxation oscillator to compute capacitance value. In this case, the capacitors 101 and 103 are repeatedly charged and discharged, and a frequency of the oscillator and the value of current ID1 are utilized to compute the capacitance value of capacitors 101 and 103. The relation thereof can be shown as Equation 1, wherein FOSC indicates an oscillator frequency, Cstray indicates capacitance of the capacitor 101, and CS indicates capacitance value of the capacitor 103.

Fosc∝dV·(Cstray+CS)/ID1  (1)

Since detail concept for such technology is well known by persons skilled in the art, it is omitted for brevity here. Such capacitance detecting method needs an ADC (analog to digital converter, not illustrated here since there are too many kinds of ADCs in this field) to detect. However, the detecting range of the ADC varies corresponding to different parasitical capacitance, background capacitance. Also, the dynamic range and the sensitivity of the ADC vary corresponding to different detecting ranges, such that the yield and production time are affected.

FIG. 2 illustrates another example of a prior art capacitance difference detecting circuit. In the capacitance difference detecting circuit 200 in FIG. 2, the ADC 201 serves to detect voltage. The detected voltage can be shown as Equation (2)

V S = VDD · C S C S + C Stray ( 2 )

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