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Memory apparatus and refresh method therof

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Memory apparatus and refresh method therof


A memory apparatus includes a memory cell array comprising a plurality of memory cells connected with a plurality of bit lines and a plurality of word lines, a page buffer unit connected to the plurality of bit lines and latch data read from a memory cell selected from the plurality of memory cells, and a control unit configured to generate a refresh signal according to a prestored current status and provide the refresh signal to the page buffer unit in order to substantially prevent loss of the data latched by the page buffer unit.

Browse recent Hynix Semiconductor Inc. patents - Icheon-si, KR
Inventor: Sang Hyun SONG
USPTO Applicaton #: #20120275239 - Class: 36518905 (USPTO) - 11/01/12 - Class 365 


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The Patent Description & Claims data below is from USPTO Patent Application 20120275239, Memory apparatus and refresh method therof.

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CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2011-0040836, filed on Apr. 29, 2011, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

The present invention relates generally to a memory apparatus, and more particularly, to a non-volatile memory apparatus and a refresh method thereof.

2. Related Art

A memory apparatus such as a NAND flash memory includes a memory cell array, a page buffer circuit, and a control logic circuit for controlling the memory cell array and the page buffer circuit.

A memory cell array includes a plurality of strings. And each string includes a series of memory cells connected to each other with transistors formed at the ends. The memory cells of the plurality of strings are electrically connected through word lines, and each string is electrically connected to the page buffer circuit for sensing data through bit lines.

The control logic circuit controls the memory cell array and the operation of the page buffer circuit described above.

A page buffer circuit includes a plurality of latch circuits. A page buffer circuit can program a latched data to a memory cell connected to a selected bit line or perform a data read operation by loading and outputting of the data stored in a memory cell, which is connected to a selected bit line, to a latch.

A latch circuit in a page buffer circuit as described above may include a main latch unit having a general latch and a sub-latch unit having a dynamic latch. The general latch of the main latch unit may provide adequate data retention and driving force but hinders the efforts to achieve a high degree of device integration. The dynamic latch of the sub-latch unit is more suitable for achieving a high degree of integration than the general latch but exhibits poor data retention and driving force characteristics. For this reason, it is necessary to periodically perform a refresh operation in a dynamic latch. The number of sub-latch units may may vary depending on the programming method, such as a single level cell (SLC) method, a multi-level cell (MLC) method, etc., implemented in the flash memory apparatus.

For performing the refresh operation on the sub-latch unit having the dynamic latch as described above, a signal is generated in the predetermined units of a logic control unit.

Generating the signal to perform the sub-latch unit refresh operation on the sub-latch unit imposes a burden on the logic control unit. Furthermore, when the refresh operation is performed only in the predetermined units of the logic control unit, it may delay an operation time.

SUMMARY

A memory apparatus and a refresh method thereof increases the operation speed of a non-volatile memory apparatus by automatically performing a refresh operation of a page buffer unit.

In an embodiment of the present invention, a memory apparatus comprises: a memory cell array comprising a plurality of memory cells connected with a plurality of bit lines and a plurality of word lines; a page buffer unit connected to the plurality of bit lines and configured to latch data read from a memory cell selected from the plurality of memory cells; and a control unit configured to generate a refresh signal according to a prestored current status and provide the refresh signal to the page buffer unit in order to substantially prevent loss of the data latched by the page buffer unit.

In an embodiment of the present invention, a memory apparatus comprises: a memory cell array comprising a plurality of memory cells connected with a plurality of bit lines and a plurality of word lines; a control unit configured to select one or more memory cells from the plurality of memory cells in response to a read command, and control a data read operation; and a page buffer unit configured to latch data read from the selected one or more memory cells and generate an internal refresh signal in order to substantially prevent loss of the latched data when a control signal is input from the control unit.

A method of refreshing a memory apparatus according to an embodiment of the present invention includes the steps of: selecting one or more memory cells from a memory cell array when a read command input, and reading data from a selected memory cell; latching the read data in a page buffer unit; generating an internal refresh signal when the data is latched in the page buffer unit; and performing a refresh operation by the internal refresh signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

FIG. 1 is a is a block diagram illustrating the configuration of a non-volatile memory apparatus according to an embodiment;

FIG. 2 is a circuit diagram schematically illustrating a part of a page buffer unit of a non-volatile memory apparatus according to an embodiment;

FIG. 3 is a block diagram schematically illustrating a part of a page buffer unit of a non-volatile memory apparatus according to an embodiment;

FIGS. 4a and 4b are block diagrams illustrating a second control unit of a non-volatile memory apparatus according to an embodiment;

FIG. 5 is a timing diagram explaining the operation of a second control unit of a non-volatile memory apparatus according to an embodiment; and



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stats Patent Info
Application #
US 20120275239 A1
Publish Date
11/01/2012
Document #
13219624
File Date
08/27/2011
USPTO Class
36518905
Other USPTO Classes
365222
International Class
11C7/10
Drawings
6



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