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Processor for executing highly efficient vliw

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Processor for executing highly efficient vliw

A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

Browse recent Panasonic Corporation patents - Osaka, JP
Inventors: Shuichi TAKAYAMA, Nobuo HIGAKI
USPTO Applicaton #: #20120272044 - Class: 712205 (USPTO) - 10/25/12 - Class 712 

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The Patent Description & Claims data below is from USPTO Patent Application 20120272044, Processor for executing highly efficient vliw.

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Distributed micro instructions set processor architecture for high-efficiency signal processing
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Request coalescing for instruction streams
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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)
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