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Processes and systems for engineering a barrier surface for copper deposition

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Processes and systems for engineering a barrier surface for copper deposition


An integrated system for processing a substrate in controlled environment to enable deposition of a thin copper seed layer on a surface of a metallic barrier layer of a copper interconnect is provided. The system includes a lab-ambient transfer chamber, a vacuum transfer chamber, a vacuum process module for cleaning an exposed surface of a metal oxide of a underlying metal, a vacuum process module for depositing the metallic barrier layer, and a controlled-ambient transfer chamber filled with an inert gas, wherein at least one controlled-ambient process module is coupled to the controlled-ambient transfer chamber. In addition, the system includes an electroless copper deposition process module used to deposit the thin layer of copper seed layer on the surface of the metallic barrier layer.

Browse recent Lam Research Corporation patents - Fremont, CA, US
Inventors: Yezdi Dordi, John Boyd, Tiruchirapalli Arunagiri, Hyungsuk Alexander Yoon, Fritz C. Redeker, William Thie, Arthur M. Howald
USPTO Applicaton #: #20120269987 - Class: 427539 (USPTO) - 10/25/12 - Class 427 
Coating Processes > Direct Application Of Electrical, Magnetic, Wave, Or Particulate Energy >Pretreatment Of Substrate Or Post-treatment Of Coated Substrate >Ionized Gas Utilized (e.g., Electrically Powered Source, Corona Discharge, Plasma, Glow Discharge, Etc.) >Plasma (e.g., Cold Plasma, Corona, Glow Discharge, Etc.) >Oxygen Containing Atmosphere

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The Patent Description & Claims data below is from USPTO Patent Application 20120269987, Processes and systems for engineering a barrier surface for copper deposition.

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CLAIM OF PRIORITY

This application claims priority as a divisional of U.S. application Ser. No. 11/514,038, titled “Processes and Systems for Engineering a Barrier Surface for Copper Deposition,” filed on Aug. 30, 2006, which claims priority to U.S. Provisional Application Ser. No. 60/686,787, titled “High Rate Electroless Plating and Integration Flow to Form Cu Interconnects,” filed on Aug. 31, 2005, and U.S. application Ser. No. 11/461,415, titled “System and Method for Forming Patterned Copper lines Through Electroless Copper Plating,” filed on Jul. 27, 2006, the disclosures of which are hereby incorporated by reference.

CROSS REFERENCE TO RELATED APPLICATION

This application is related to U.S. patent application Ser. No. 11/513,634), entitled “Processes and Systems for Engineering a Copper Surface for Selective Metal Deposition,” and U.S. patent application Ser. No. 11/513,446, entitled “Processes and Systems for Engineering a Silicon-Type Surface For Selective Metal Deposition to Form a Metal Silicide,” both of which are filed on the same day as the instant application. The disclosure of these related applications is incorporated herein by reference in their entireties for all purposes.

BACKGROUND

Integrated circuits use conductive interconnects to wire together the individual devices on a semiconductor substrate, or to communicate externally to the integrated circuit. Interconnect metallization for vias and trenches may include aluminum alloys and copper. Electro-migration (EM) is a well-known reliability problem for metal interconnects, caused by electrons pushing and moving metal atoms in the direction of current flow at a rate determined by the current density. Electro-migration can eventually lead to the thinning of the metal line, which can result in higher resistivity or, worst case, a metal line breakage. Fortunately, not every interconnect metal line on an IC has current moving in the same direction all the time, as it mostly does in power supply and ground lines. However, as metal lines get narrower (International Technology Roadmap for Semiconductors (ITRS) calls for a ˜0.7× reduction in the line width for every technology node), electro-migration becomes more of an issue.

In aluminum lines, EM is a bulk phenomenon and is well controlled by the addition of small amounts of a dopant, such as copper. EM in copper lines, on the other hand, is a surface phenomenon. It can occur wherever the copper is free to move, typically at an interface where there is poor adhesion between the copper and another material. In today\'s dual-damascene process, this happens most often on the top of the copper line where it interfaces with what is typically a SiC diffusion barrier layer, but it can also happen at the copper/barrier interface. With each migration to the next technology node, and resulting increase in current density, the problem worsens.

The solution to EM problems, as well as related stress voids, another common reliability problem, has been a story of process integration: optimized depositions (i.e. reducing thickness of barrier and seed layers), pre- and post-deposition wafer cleanings, surface treatments, etc., all aimed at providing homogeneous surfaces and good adhesion between layers to minimize metal atom migration and void propagation. In the dual-damascene process, trenches and holes (for contacts and vias) are etched in the dielectric, then lined with a barrier material, such as tantalum (Ta), tantalum nitride (TaN), or a combination of both films, followed by the deposition of a copper seed layer, copper electroplating, copper planarization using CMP and then deposition of a dielectric stack, such as SiC/low-k/SiC. Since an oxide readily forms on copper when copper is exposed to air, proper post-CMP cleaning and removal of the copper oxide before capping the copper with SiC is required to ensure good adhesion between copper and SiC. Removal of the copper oxide prior to the SiC deposition is essential to good EM performance and reducing resultant metal resistivity.

Recently, capping Copper with a cobalt-alloy capping layer, such as CoWP (cobalt tungsten phosphide), CoWB (cobalt tungsten boride), or CoWBP (cobalt tungsten boro-phosphide), before the SiC dielectric barrier layer, has been shown to significantly improve electro-migration, compared to SiC over copper. FIG. 1 shows that the cobalt-alloy capping layers 20, 30 are deposited over copper layers 23, 33 and under dielectric capping SiC layers 25, 35, respectively. Ta and/or TaN barrier layers are illustrated as layers 24, 34. The cobalt-alloy layers 20, 30 improve the adhesion between copper 23, 33 and SiC cap layers 25, 35. The cobalt-alloy layers 20, 30 can also exhibit certain copper diffusion barrier characteristics. The cobalt-alloy capping layers can be selectively deposited on copper by electroless deposition. However, the electroless deposition can be inhibited by thin copper oxide layer, which can be formed when copper is exposed to air. Further, contaminants on the copper and dielectric surfaces can cause pattern-dependent plating effects include pattern-dependent thickness of the Co alloy, as well as pattern-dependent copper line thickness loss in part due to etching during the ‘incubation’ time required to initiate the Co plating reaction. Therefore, it is important to control the processing environment to limit (or control) the growth of native copper oxide, and to remove copper oxide and organic contaminants on the copper surface and organic and metallic contaminants on the dielectric surface immediately prior to depositing the metallic capping layer, such as a cobalt-alloy. Further, to reduce pattern-dependent deposition variability, the dielectric surface must be controlled to normalize its influence across structures of different pattern densities. Engineering the metal-to-metal interface between the copper layers 23, 33, between copper and barrier layers 33 and 34, 23 and 24, and the adhesion promoting layers (or metallic capping layers), such as the cobalt-alloy layers 20, 20, is very critical in ensuring good interfacial adhesion and good EM performance. Further, as metal lines become narrower, physical vapor deposition (PVD) barrier and seed films form a larger part of the metal line, increase the effective resistivity, and hence current density. Thin and conformal barrier and seed layers can mitigate this trend, with atomic layer deposition (ALD) barriers (TaN, Ru or hybrid combinations) providing conformal step coverage and acceptable barrier properties, and electroless Cu process providing a conformal seed layer. Until now, however, there is no electroless Cu seed layer that can adhere to the ALD TaN barrier films produced.

In view of the foregoing, there is a need for systems and processes that produce a metal-to-metal interface with improved electro-migration performance, low sheet resistance, and improved interfacial adhesion for copper interconnects.

SUMMARY

Broadly speaking, the embodiments fill the need by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically barrier-to-copper interface, to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects. It should be appreciated that the present invention can be implemented in numerous ways, including as a solution, a method, a process, an apparatus, or a system. Several inventive embodiments of the present invention are described below.

In one embodiment, a method of preparing a substrate surface of a substrate to deposit a metallic barrier layer to line a copper interconnect structure of the substrate and to deposit a thin copper seed layer on a surface of the metallic barrier layer in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes cleaning an exposed surface of a underlying metal to remove surface metal oxide in the integrated system, wherein the underlying metal is part of a underlying interconnect electrically connected to the copper interconnect. The method also includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, wherein after depositing the metallic barrier layer, the substrate is transferred and processed in controlled environment to prevent the formation of metallic barrier oxide. The method further includes depositing the thin copper seed layer in the integrated system, and depositing a gap-fill copper layer over the thin copper seed layer in the integrated system.

In another embodiment, a method of preparing a substrate surface of a substrate to deposit a metallic barrier layer to line a copper interconnect structure of the substrate and to selectively deposit a thin copper seed layer on a surface of the metallic barrier layer in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes cleaning an exposed surface of an underlying metal to remove surface oxide in the integrated system, wherein the underlying metal is part of a underlying interconnect, the copper interconnect is electrically connected to underlying interconnect, and depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, wherein after depositing the metallic barrier layer, the substrate is transferred and processed in controlled environment to prevent the formation of metallic barrier oxide. The method also includes selectively depositing the thin copper seed layer in the integrated system, and depositing a gap-fill copper layer over the thin copper seed layer in the integrated system in the integrated system.

The method further includes removing copper overburden and metallic barrier overburden in the integrated system, wherein removing copper overburden and metallic barrier overburden creates the planarized copper surface, and removing metal-organic complex contaminants and metal oxides from the substrate surface in the integrated system. In addition, the method includes removing organic contaminants from the substrate surface in the integrated system, and reducing the planarized copper surface that is removed of metal-organic complex contaminants, metal oxides, and organic contaminants in the integrated system. Additionally, the method includes depositing a thin layer of a cobalt-alloy material on the reduced planarized copper surface in the integrated system.

In another embodiment, a method of preparing a metallic barrier surface of a substrate to deposit a thin copper seed layer on a surface of a metallic barrier layer of a copper interconnect structure in an integrated system to improve electromigration performance of the copper interconnect structure is provided. The method includes reducing a surface of the metallic barrier layer to convert metallic barrier oxide on the surface of the metallic barrier layer to make the surface of the metallic barrier layer to be metallic-rich in the integrated system. The method also includes depositing the thin copper seed layer in the integrated system, and depositing a gap-fill copper layer over the thin copper seed layer in the integrated system.

In another embodiment, an integrated system for processing a substrate in controlled environment to enable deposition of a thin copper seed layer on a surface of a metallic barrier layer of a copper interconnect is provided. The system includes a lab-ambient transfer chamber capable of transferring the substrate from a substrate cassette coupled to the lab-ambient transfer chamber into the integrated system, and a vacuum transfer chamber operated under vacuum at a pressure less than 1 Torr, wherein at least one vacuum process module is coupled to the vacuum transfer chamber. The system also includes a vacuum process module for cleaning an exposed surface of a metal oxide of a underlying metal in the integrated system, wherein the underlying metal is part of a underlying interconnect, the copper interconnect is electrically connected to the underlying interconnect, wherein the vacuum process module for cleaning is one of the at least one vacuum process module coupled to the vacuum transfer chamber, and is operated under vacuum at a pressure less than 1 Torr.

The system further includes a vacuum process module for depositing the metallic barrier layer, wherein the vacuum process module for depositing the metallic barrier layer one of the at least one vacuum process module is coupled to the vacuum transfer chamber, and is operated under vacuum at a pressure less than 1 Torr, and a controlled-ambient transfer chamber filled with an inert gas selected from a group of inert gases, wherein at least one controlled-ambient process module is coupled to the controlled-ambient transfer chamber. In addition, the system includes an electroless copper deposition process module used to deposit the thin layer of copper seed layer on the surface of the metallic barrier layer, wherein the electroless copper deposition process module is one of the at least one controlled environment process modules coupled to the controlled-ambient transfer chamber.

In another embodiment, an integrated system for processing a substrate in controlled environment to enable selective deposition of a thin copper seed layer on a surface of a metallic barrier layer of a copper interconnect and preparing a planarized copper surface of the copper interconnect to selectively depositing a thin layer of a cobalt-alloy material in an integrated system to improve electromigration performance of the copper interconnect is provided. The system includes a lab-ambient transfer chamber capable of transferring the substrate from a substrate cassette coupled to the lab-ambient transfer chamber into the integrated system, and a vacuum transfer chamber operated under vacuum at a pressure less than 1 Torr, wherein at least one vacuum process module is coupled to the vacuum transfer chamber. The system also includes an Ar sputtering process module to clean an exposed surface of a metal oxide of a underlying metal in the integrated system, wherein the underlying metal is part of a underlying interconnect, the copper interconnect is electrically connected to the underlying interconnect, the Ar sputtering process module one of the at least one vacuum process module is coupled to the vacuum transfer chamber, and an atomic layer deposition (ALD) process module for depositing a thin first metallic barrier layer, wherein the ALD process module is one of the at least one vacuum process module coupled to the vacuum transfer chamber.

The system further includes a PVD process chamber for depositing a thin second metallic barrier layer, wherein the PVD process module is one of the at least one vacuum process module coupled to the vacuum transfer chamber, and a hydrogen reduction process module for reducing a metal oxide or metal nitride to a metal, wherein the hydrogen reduction process module is one of the at least one vacuum process module coupled to the vacuum transfer chamber. In addition, the system includes an oxygen plasma process module for removing organic contaminants from the substrate surface, wherein the oxygen plasma process module is one of the at least one vacuum process module coupled to the vacuum transfer chamber, and a controlled-ambient transfer chamber filled with an inert gas selected from a group of inert gases, wherein at least one controlled-ambient process module is coupled to the controlled-ambient transfer chamber. Additionally, the system includes an electroless copper deposition process module used to deposit the thin layer of copper seed layer and a gap-fill copper layer on the surface of the metallic barrier layer, the electroless copper deposition process module being one of the at least one controlled-ambient process module coupled to the controlled-ambient transfer chamber.

The system also includes an electroless cobalt-alloy deposition process module used to deposit the thin layer of the cobalt-alloy material on the prepared planarized copper surface, the electroless copper alloy deposition process module being one of the at least one controlled-ambient process module coupled to the controlled-ambient transfer chamber, and a planarizing process module used to remove a copper overburden and a barrier overburden of the copper interconnect, the planarizing process module is one of the at least one controlled-ambient process module coupled to the controlled-ambient transfer module. In addition, the system includes a wet clean process module used to remove metallic contamination on the substrate surface, the wet clean process module is one of the at least one controlled-ambient process module coupled to the controlled-ambient transfer module.

In yet another embodiment, an integrated system for processing a substrate in controlled environment to enable deposition of a thin copper seed layer on a surface of a metallic barrier layer of a copper interconnect is provided. The system includes a lab-ambient transfer chamber capable of transferring the substrate from a substrate cassette coupled to the lab-ambient transfer chamber into the integrated system, and a vacuum transfer chamber operated under vacuum at a pressure less than 1 Torr, wherein at least one vacuum process module is coupled to the vacuum transfer chamber. The system further includes a vacuum process module for reducing the metallic barrier layer, wherein the vacuum process module for reducing the metallic barrier layer one of the at least one vacuum process module is coupled to the vacuum transfer chamber, and is operated under vacuum at a pressure less than 1 Torr. In addition, the system includes a controlled-ambient transfer chamber filled with an inert gas selected from a group of inert gases, wherein at least one controlled-ambient process module is coupled to the controlled-ambient transfer chamber, and an electroless copper deposition process module used to deposit the thin layer of copper seed layer on the surface of the metallic barrier layer, wherein the electroless copper deposition process module is one of the at least one controlled environment process modules coupled to the controlled-ambient transfer chamber.

Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, and like reference numerals designate like structural elements.

FIG. 1 shows an exemplary cross section interconnects.

FIGS. 2A-2D show cross sections of an interconnect structure at various stages of interconnect processing.

FIG. 3 shows various forms of contaminants on substrate surface after metal CMP.

FIG. 4A shows an exemplary process flow to prepare a copper surface for electrolessly depositing a cobalt-alloy.

FIG. 4B shows an exemplary system used to process a substrate through a process flow of FIG. 4A.

FIGS. 5A-5C show cross sections of an interconnect structure at various stages of interconnect processing.

FIG. 6A shows an exemplary process flow to prepare a copper surface for electrolessly depositing a cobalt-alloy.

FIG. 6B shows an exemplary system used to process a substrate through a process flow of FIG. 6A.

FIGS. 7A-7C show cross sections of an interconnect structure at various stages of interconnect processing.

FIG. 8A shows an exemplary process flow to prepare a copper surface for electrolessly depositing a cobalt-alloy.

FIG. 8B shows an exemplary system used to process a substrate through a process flow of FIG. 8A.

FIGS. 9A-9E show cross sections of a metal line structure at various stages of processing.

FIG. 10A shows an exemplary process flow to prepare a barrier layer surface for electrolessly depositing a copper layer.

FIG. 10B shows an exemplary system used to process a substrate through a process flow of FIG. 10A.

FIG. 10C shows an exemplary process flow to prepare a barrier layer surface for electrolessly depositing a copper layer.

FIG. 10D shows an exemplary system used to process a substrate through a process flow of FIG. 10C.

FIG. 11A shows an exemplary process flow to prepare a barrier layer surface for electrolessly depositing a copper layer and to prepare a copper surface for electrolessly depositing a cobalt-alloy.

FIG. 11B shows an exemplary system used to process a substrate through a process flow of FIG. 11A.

FIGS. 12A-12D show cross sections of an interconnect structure at various stages of processing.

FIG. 13A shows an exemplary process flow to prepare a barrier surface for electroless copper deposition and to prepare a copper surface for electrolessly depositing a cobalt-alloy.

FIG. 13B shows an exemplary system used to process a substrate through a process flow of FIG. 13A.

FIGS. 14A-14D show cross section of a gate structure at various stages of forming metal silicide.

FIG. 15A shows an exemplary process flow to prepare exposed silicon surface to form a metal silicide.

FIG. 15B shows an exemplary system used to process a substrate through a process flow of FIG. 15A.

FIG. 16 shows a schematic diagram of system integration for an integrated system with ambient-controlled processing environments.



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stats Patent Info
Application #
US 20120269987 A1
Publish Date
10/25/2012
Document #
13534366
File Date
06/27/2012
USPTO Class
427539
Other USPTO Classes
118 50, 427123, 118719
International Class
/
Drawings
30



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